drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  44                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  45
  46 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  47
  48 #ifdef RTE_LIBRTE_IEEE1588
  49 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  50 #else
  51 #define I40E_TX_IEEE1588_TMST 0
  52 #endif
  53
  54 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  55                 PKT_TX_IP_CKSUM |                \
  56                 PKT_TX_L4_MASK |                 \
  57                 PKT_TX_TCP_SEG |                 \
  58                 PKT_TX_OUTER_IP_CKSUM)
  59
  60 #define I40E_TX_OFFLOAD_MASK (  \
  61                 PKT_TX_IP_CKSUM |       \
  62                 PKT_TX_L4_MASK |        \
  63                 PKT_TX_OUTER_IP_CKSUM | \
  64                 PKT_TX_TCP_SEG |        \
  65                 PKT_TX_QINQ_PKT |       \
  66                 PKT_TX_VLAN_PKT |       \
  67                 PKT_TX_TUNNEL_MASK |    \
  68                 I40E_TX_IEEE1588_TMST)
  69
  70 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  71                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  72
  73 static inline void
  74 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  75 {
  76         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  77                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  78                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  79                 mb->vlan_tci =
  80                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  81                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  82                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  83         } else {
  84                 mb->vlan_tci = 0;
  85         }
  86 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  87         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  88                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  89                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
  90                 mb->vlan_tci_outer = mb->vlan_tci;
  91                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  92                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  93                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  94                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  95         } else {
  96                 mb->vlan_tci_outer = 0;
  97         }
  98 #endif
  99         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 100                    mb->vlan_tci, mb->vlan_tci_outer);
 101 }
 102
 103 /* Translate the rx descriptor status to pkt flags */
 104 static inline uint64_t
 105 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 106 {
 107         uint64_t flags;
 108
 109         /* Check if RSS_HASH */
 110         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 111                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 112                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 113
 114         /* Check if FDIR Match */
 115         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 116                                                         PKT_RX_FDIR : 0);
 117
 118         return flags;
 119 }
 120
 121 static inline uint64_t
 122 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 123 {
 124         uint64_t flags = 0;
 125         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 126
 127 #define I40E_RX_ERR_BITS 0x3f
 128         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 129                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 130                 return flags;
 131         }
 132
 133         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 134                 flags |= PKT_RX_IP_CKSUM_BAD;
 135         else
 136                 flags |= PKT_RX_IP_CKSUM_GOOD;
 137
 138         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 139                 flags |= PKT_RX_L4_CKSUM_BAD;
 140         else
 141                 flags |= PKT_RX_L4_CKSUM_GOOD;
 142
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 144                 flags |= PKT_RX_EIP_CKSUM_BAD;
 145
 146         return flags;
 147 }
 148
 149 /* Function to check and set the ieee1588 timesync index and get the
 150  * appropriate flags.
 151  */
 152 #ifdef RTE_LIBRTE_IEEE1588
 153 static inline uint64_t
 154 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 155 {
 156         uint64_t pkt_flags = 0;
 157         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 158                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 159                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 160
 161         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 162                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 163                 pkt_flags = PKT_RX_IEEE1588_PTP;
 164         if (tsyn & 0x04) {
 165                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 166                 mb->timesync = tsyn & 0x03;
 167         }
 168
 169         return pkt_flags;
 170 }
 171 #endif
 172
 173 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 174 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 176 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 177 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 178
 179 static inline uint64_t
 180 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 181 {
 182         uint64_t flags = 0;
 183 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 184         uint16_t flexbh, flexbl;
 185
 186         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 187                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 188                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 189         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 190                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 191                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 192
 193
 194         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 195                 mb->hash.fdir.hi =
 196                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 197                 flags |= PKT_RX_FDIR_ID;
 198         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 199                 mb->hash.fdir.hi =
 200                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 201                 flags |= PKT_RX_FDIR_FLX;
 202         }
 203         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 204                 mb->hash.fdir.lo =
 205                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 206                 flags |= PKT_RX_FDIR_FLX;
 207         }
 208 #else
 209         mb->hash.fdir.hi =
 210                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 211         flags |= PKT_RX_FDIR_ID;
 212 #endif
 213         return flags;
 214 }
 215
 216 static inline void
 217 i40e_parse_tunneling_params(uint64_t ol_flags,
 218                             union i40e_tx_offload tx_offload,
 219                             uint32_t *cd_tunneling)
 220 {
 221         /* EIPT: External (outer) IP header type */
 222         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 223                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 224         else if (ol_flags & PKT_TX_OUTER_IPV4)
 225                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 226         else if (ol_flags & PKT_TX_OUTER_IPV6)
 227                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 228
 229         /* EIPLEN: External (outer) IP header length, in DWords */
 230         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 231                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 232
 233         /* L4TUNT: L4 Tunneling Type */
 234         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 235         case PKT_TX_TUNNEL_IPIP:
 236                 /* for non UDP / GRE tunneling, set to 00b */
 237                 break;
 238         case PKT_TX_TUNNEL_VXLAN:
 239         case PKT_TX_TUNNEL_GENEVE:
 240                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 241                 break;
 242         case PKT_TX_TUNNEL_GRE:
 243                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 244                 break;
 245         default:
 246                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 247                 return;
 248         }
 249
 250         /* L4TUNLEN: L4 Tunneling Length, in Words
 251          *
 252          * We depend on app to set rte_mbuf.l2_len correctly.
 253          * For IP in GRE it should be set to the length of the GRE
 254          * header;
 255          * for MAC in GRE or MAC in UDP it should be set to the length
 256          * of the GRE or UDP headers plus the inner MAC up to including
 257          * its last Ethertype.
 258          */
 259         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 260                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 261 }
 262
 263 static inline void
 264 i40e_txd_enable_checksum(uint64_t ol_flags,
 265                         uint32_t *td_cmd,
 266                         uint32_t *td_offset,
 267                         union i40e_tx_offload tx_offload)
 268 {
 269         /* Set MACLEN */
 270         if (ol_flags & PKT_TX_TUNNEL_MASK)
 271                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 272                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 273         else
 274                 *td_offset |= (tx_offload.l2_len >> 1)
 275                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 276
 277         /* Enable L3 checksum offloads */
 278         if (ol_flags & PKT_TX_IP_CKSUM) {
 279                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 280                 *td_offset |= (tx_offload.l3_len >> 2)
 281                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 282         } else if (ol_flags & PKT_TX_IPV4) {
 283                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 284                 *td_offset |= (tx_offload.l3_len >> 2)
 285                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 286         } else if (ol_flags & PKT_TX_IPV6) {
 287                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 288                 *td_offset |= (tx_offload.l3_len >> 2)
 289                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 290         }
 291
 292         if (ol_flags & PKT_TX_TCP_SEG) {
 293                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 294                 *td_offset |= (tx_offload.l4_len >> 2)
 295                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 296                 return;
 297         }
 298
 299         /* Enable L4 checksum offloads */
 300         switch (ol_flags & PKT_TX_L4_MASK) {
 301         case PKT_TX_TCP_CKSUM:
 302                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 303                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 304                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 305                 break;
 306         case PKT_TX_SCTP_CKSUM:
 307                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 308                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 309                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 310                 break;
 311         case PKT_TX_UDP_CKSUM:
 312                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 313                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 314                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 315                 break;
 316         default:
 317                 break;
 318         }
 319 }
 320
 321 /* Construct the tx flags */
 322 static inline uint64_t
 323 i40e_build_ctob(uint32_t td_cmd,
 324                 uint32_t td_offset,
 325                 unsigned int size,
 326                 uint32_t td_tag)
 327 {
 328         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 329                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 330                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 331                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 332                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 333 }
 334
 335 static inline int
 336 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 337 {
 338         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 339         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 340         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 341         uint16_t nb_tx_desc = txq->nb_tx_desc;
 342         uint16_t desc_to_clean_to;
 343         uint16_t nb_tx_to_clean;
 344
 345         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 346         if (desc_to_clean_to >= nb_tx_desc)
 347                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 348
 349         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 350         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 351                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 352                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 353                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 354                         "(port=%d queue=%d)", desc_to_clean_to,
 355                                 txq->port_id, txq->queue_id);
 356                 return -1;
 357         }
 358
 359         if (last_desc_cleaned > desc_to_clean_to)
 360                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 361                                                         desc_to_clean_to);
 362         else
 363                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 364                                         last_desc_cleaned);
 365
 366         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 367
 368         txq->last_desc_cleaned = desc_to_clean_to;
 369         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 370
 371         return 0;
 372 }
 373
 374 static inline int
 375 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 376 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 377 #else
 378 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 379 #endif
 380 {
 381         int ret = 0;
 382
 383 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 384         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 385                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 386                              "rxq->rx_free_thresh=%d, "
 387                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 388                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 389                 ret = -EINVAL;
 390         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 391                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 392                              "rxq->rx_free_thresh=%d, "
 393                              "rxq->nb_rx_desc=%d",
 394                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 395                 ret = -EINVAL;
 396         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 397                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 398                              "rxq->nb_rx_desc=%d, "
 399                              "rxq->rx_free_thresh=%d",
 400                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 401                 ret = -EINVAL;
 402         }
 403 #else
 404         ret = -EINVAL;
 405 #endif
 406
 407         return ret;
 408 }
 409
 410 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 411 #define I40E_LOOK_AHEAD 8
 412 #if (I40E_LOOK_AHEAD != 8)
 413 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 414 #endif
 415 static inline int
 416 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 417 {
 418         volatile union i40e_rx_desc *rxdp;
 419         struct i40e_rx_entry *rxep;
 420         struct rte_mbuf *mb;
 421         uint16_t pkt_len;
 422         uint64_t qword1;
 423         uint32_t rx_status;
 424         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 425         int32_t i, j, nb_rx = 0;
 426         uint64_t pkt_flags;
 427         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 428
 429         rxdp = &rxq->rx_ring[rxq->rx_tail];
 430         rxep = &rxq->sw_ring[rxq->rx_tail];
 431
 432         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 433         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 434                                 I40E_RXD_QW1_STATUS_SHIFT;
 435
 436         /* Make sure there is at least 1 packet to receive */
 437         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 438                 return 0;
 439
 440         /**
 441          * Scan LOOK_AHEAD descriptors at a time to determine which
 442          * descriptors reference packets that are ready to be received.
 443          */
 444         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 445                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 446                 /* Read desc statuses backwards to avoid race condition */
 447                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 448                         qword1 = rte_le_to_cpu_64(\
 449                                 rxdp[j].wb.qword1.status_error_len);
 450                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 451                                         I40E_RXD_QW1_STATUS_SHIFT;
 452                 }
 453
 454                 rte_smp_rmb();
 455
 456                 /* Compute how many status bits were set */
 457                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 458                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 459
 460                 nb_rx += nb_dd;
 461
 462                 /* Translate descriptor info to mbuf parameters */
 463                 for (j = 0; j < nb_dd; j++) {
 464                         mb = rxep[j].mbuf;
 465                         qword1 = rte_le_to_cpu_64(\
 466                                 rxdp[j].wb.qword1.status_error_len);
 467                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 468                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 469                         mb->data_len = pkt_len;
 470                         mb->pkt_len = pkt_len;
 471                         mb->ol_flags = 0;
 472                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 473                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 474                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 475                         mb->packet_type =
 476                                 ptype_tbl[(uint8_t)((qword1 &
 477                                 I40E_RXD_QW1_PTYPE_MASK) >>
 478                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 479                         if (pkt_flags & PKT_RX_RSS_HASH)
 480                                 mb->hash.rss = rte_le_to_cpu_32(\
 481                                         rxdp[j].wb.qword0.hi_dword.rss);
 482                         if (pkt_flags & PKT_RX_FDIR)
 483                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 484
 485 #ifdef RTE_LIBRTE_IEEE1588
 486                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 487 #endif
 488                         mb->ol_flags |= pkt_flags;
 489
 490                 }
 491
 492                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 493                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 494
 495                 if (nb_dd != I40E_LOOK_AHEAD)
 496                         break;
 497         }
 498
 499         /* Clear software ring entries */
 500         for (i = 0; i < nb_rx; i++)
 501                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 502
 503         return nb_rx;
 504 }
 505
 506 static inline uint16_t
 507 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 508                         struct rte_mbuf **rx_pkts,
 509                         uint16_t nb_pkts)
 510 {
 511         uint16_t i;
 512         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 513
 514         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 515
 516         for (i = 0; i < nb_pkts; i++)
 517                 rx_pkts[i] = stage[i];
 518
 519         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 520         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 521
 522         return nb_pkts;
 523 }
 524
 525 static inline int
 526 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 527 {
 528         volatile union i40e_rx_desc *rxdp;
 529         struct i40e_rx_entry *rxep;
 530         struct rte_mbuf *mb;
 531         uint16_t alloc_idx, i;
 532         uint64_t dma_addr;
 533         int diag;
 534
 535         /* Allocate buffers in bulk */
 536         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 537                                 (rxq->rx_free_thresh - 1));
 538         rxep = &(rxq->sw_ring[alloc_idx]);
 539         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 540                                         rxq->rx_free_thresh);
 541         if (unlikely(diag != 0)) {
 542                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 543                 return -ENOMEM;
 544         }
 545
 546         rxdp = &rxq->rx_ring[alloc_idx];
 547         for (i = 0; i < rxq->rx_free_thresh; i++) {
 548                 if (likely(i < (rxq->rx_free_thresh - 1)))
 549                         /* Prefetch next mbuf */
 550                         rte_prefetch0(rxep[i + 1].mbuf);
 551
 552                 mb = rxep[i].mbuf;
 553                 rte_mbuf_refcnt_set(mb, 1);
 554                 mb->next = NULL;
 555                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 556                 mb->nb_segs = 1;
 557                 mb->port = rxq->port_id;
 558                 dma_addr = rte_cpu_to_le_64(\
 559                         rte_mbuf_data_iova_default(mb));
 560                 rxdp[i].read.hdr_addr = 0;
 561                 rxdp[i].read.pkt_addr = dma_addr;
 562         }
 563
 564         /* Update rx tail regsiter */
 565         rte_wmb();
 566         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 567
 568         rxq->rx_free_trigger =
 569                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 570         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 571                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 572
 573         return 0;
 574 }
 575
 576 static inline uint16_t
 577 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 578 {
 579         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 580         struct rte_eth_dev *dev;
 581         uint16_t nb_rx = 0;
 582
 583         if (!nb_pkts)
 584                 return 0;
 585
 586         if (rxq->rx_nb_avail)
 587                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 588
 589         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 590         rxq->rx_next_avail = 0;
 591         rxq->rx_nb_avail = nb_rx;
 592         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 593
 594         if (rxq->rx_tail > rxq->rx_free_trigger) {
 595                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 596                         uint16_t i, j;
 597
 598                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 599                         dev->data->rx_mbuf_alloc_failed +=
 600                                 rxq->rx_free_thresh;
 601
 602                         rxq->rx_nb_avail = 0;
 603                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 604                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 605                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 606
 607                         return 0;
 608                 }
 609         }
 610
 611         if (rxq->rx_tail >= rxq->nb_rx_desc)
 612                 rxq->rx_tail = 0;
 613
 614         if (rxq->rx_nb_avail)
 615                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 616
 617         return 0;
 618 }
 619
 620 static uint16_t
 621 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 622                           struct rte_mbuf **rx_pkts,
 623                           uint16_t nb_pkts)
 624 {
 625         uint16_t nb_rx = 0, n, count;
 626
 627         if (unlikely(nb_pkts == 0))
 628                 return 0;
 629
 630         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 631                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 632
 633         while (nb_pkts) {
 634                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 635                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 636                 nb_rx = (uint16_t)(nb_rx + count);
 637                 nb_pkts = (uint16_t)(nb_pkts - count);
 638                 if (count < n)
 639                         break;
 640         }
 641
 642         return nb_rx;
 643 }
 644 #else
 645 static uint16_t
 646 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 647                           struct rte_mbuf __rte_unused **rx_pkts,
 648                           uint16_t __rte_unused nb_pkts)
 649 {
 650         return 0;
 651 }
 652 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 653
 654 uint16_t
 655 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 656 {
 657         struct i40e_rx_queue *rxq;
 658         volatile union i40e_rx_desc *rx_ring;
 659         volatile union i40e_rx_desc *rxdp;
 660         union i40e_rx_desc rxd;
 661         struct i40e_rx_entry *sw_ring;
 662         struct i40e_rx_entry *rxe;
 663         struct rte_eth_dev *dev;
 664         struct rte_mbuf *rxm;
 665         struct rte_mbuf *nmb;
 666         uint16_t nb_rx;
 667         uint32_t rx_status;
 668         uint64_t qword1;
 669         uint16_t rx_packet_len;
 670         uint16_t rx_id, nb_hold;
 671         uint64_t dma_addr;
 672         uint64_t pkt_flags;
 673         uint32_t *ptype_tbl;
 674
 675         nb_rx = 0;
 676         nb_hold = 0;
 677         rxq = rx_queue;
 678         rx_id = rxq->rx_tail;
 679         rx_ring = rxq->rx_ring;
 680         sw_ring = rxq->sw_ring;
 681         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 682
 683         while (nb_rx < nb_pkts) {
 684                 rxdp = &rx_ring[rx_id];
 685                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 686                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 687                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 688
 689                 /* Check the DD bit first */
 690                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 691                         break;
 692
 693                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 694                 if (unlikely(!nmb)) {
 695                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 696                         dev->data->rx_mbuf_alloc_failed++;
 697                         break;
 698                 }
 699
 700                 rxd = *rxdp;
 701                 nb_hold++;
 702                 rxe = &sw_ring[rx_id];
 703                 rx_id++;
 704                 if (unlikely(rx_id == rxq->nb_rx_desc))
 705                         rx_id = 0;
 706
 707                 /* Prefetch next mbuf */
 708                 rte_prefetch0(sw_ring[rx_id].mbuf);
 709
 710                 /**
 711                  * When next RX descriptor is on a cache line boundary,
 712                  * prefetch the next 4 RX descriptors and next 8 pointers
 713                  * to mbufs.
 714                  */
 715                 if ((rx_id & 0x3) == 0) {
 716                         rte_prefetch0(&rx_ring[rx_id]);
 717                         rte_prefetch0(&sw_ring[rx_id]);
 718                 }
 719                 rxm = rxe->mbuf;
 720                 rxe->mbuf = nmb;
 721                 dma_addr =
 722                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 723                 rxdp->read.hdr_addr = 0;
 724                 rxdp->read.pkt_addr = dma_addr;
 725
 726                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 727                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 728
 729                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 730                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 731                 rxm->nb_segs = 1;
 732                 rxm->next = NULL;
 733                 rxm->pkt_len = rx_packet_len;
 734                 rxm->data_len = rx_packet_len;
 735                 rxm->port = rxq->port_id;
 736                 rxm->ol_flags = 0;
 737                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 738                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 739                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 740                 rxm->packet_type =
 741                         ptype_tbl[(uint8_t)((qword1 &
 742                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 743                 if (pkt_flags & PKT_RX_RSS_HASH)
 744                         rxm->hash.rss =
 745                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 746                 if (pkt_flags & PKT_RX_FDIR)
 747                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 748
 749 #ifdef RTE_LIBRTE_IEEE1588
 750                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 751 #endif
 752                 rxm->ol_flags |= pkt_flags;
 753
 754                 rx_pkts[nb_rx++] = rxm;
 755         }
 756         rxq->rx_tail = rx_id;
 757
 758         /**
 759          * If the number of free RX descriptors is greater than the RX free
 760          * threshold of the queue, advance the receive tail register of queue.
 761          * Update that register with the value of the last processed RX
 762          * descriptor minus 1.
 763          */
 764         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 765         if (nb_hold > rxq->rx_free_thresh) {
 766                 rx_id = (uint16_t) ((rx_id == 0) ?
 767                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 768                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 769                 nb_hold = 0;
 770         }
 771         rxq->nb_rx_hold = nb_hold;
 772
 773         return nb_rx;
 774 }
 775
 776 uint16_t
 777 i40e_recv_scattered_pkts(void *rx_queue,
 778                          struct rte_mbuf **rx_pkts,
 779                          uint16_t nb_pkts)
 780 {
 781         struct i40e_rx_queue *rxq = rx_queue;
 782         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 783         volatile union i40e_rx_desc *rxdp;
 784         union i40e_rx_desc rxd;
 785         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 786         struct i40e_rx_entry *rxe;
 787         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 788         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 789         struct rte_mbuf *nmb, *rxm;
 790         uint16_t rx_id = rxq->rx_tail;
 791         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 792         struct rte_eth_dev *dev;
 793         uint32_t rx_status;
 794         uint64_t qword1;
 795         uint64_t dma_addr;
 796         uint64_t pkt_flags;
 797         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 798
 799         while (nb_rx < nb_pkts) {
 800                 rxdp = &rx_ring[rx_id];
 801                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 802                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 803                                         I40E_RXD_QW1_STATUS_SHIFT;
 804
 805                 /* Check the DD bit */
 806                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 807                         break;
 808
 809                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 810                 if (unlikely(!nmb)) {
 811                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 812                         dev->data->rx_mbuf_alloc_failed++;
 813                         break;
 814                 }
 815
 816                 rxd = *rxdp;
 817                 nb_hold++;
 818                 rxe = &sw_ring[rx_id];
 819                 rx_id++;
 820                 if (rx_id == rxq->nb_rx_desc)
 821                         rx_id = 0;
 822
 823                 /* Prefetch next mbuf */
 824                 rte_prefetch0(sw_ring[rx_id].mbuf);
 825
 826                 /**
 827                  * When next RX descriptor is on a cache line boundary,
 828                  * prefetch the next 4 RX descriptors and next 8 pointers
 829                  * to mbufs.
 830                  */
 831                 if ((rx_id & 0x3) == 0) {
 832                         rte_prefetch0(&rx_ring[rx_id]);
 833                         rte_prefetch0(&sw_ring[rx_id]);
 834                 }
 835
 836                 rxm = rxe->mbuf;
 837                 rxe->mbuf = nmb;
 838                 dma_addr =
 839                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 840
 841                 /* Set data buffer address and data length of the mbuf */
 842                 rxdp->read.hdr_addr = 0;
 843                 rxdp->read.pkt_addr = dma_addr;
 844                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 845                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 846                 rxm->data_len = rx_packet_len;
 847                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 848
 849                 /**
 850                  * If this is the first buffer of the received packet, set the
 851                  * pointer to the first mbuf of the packet and initialize its
 852                  * context. Otherwise, update the total length and the number
 853                  * of segments of the current scattered packet, and update the
 854                  * pointer to the last mbuf of the current packet.
 855                  */
 856                 if (!first_seg) {
 857                         first_seg = rxm;
 858                         first_seg->nb_segs = 1;
 859                         first_seg->pkt_len = rx_packet_len;
 860                 } else {
 861                         first_seg->pkt_len =
 862                                 (uint16_t)(first_seg->pkt_len +
 863                                                 rx_packet_len);
 864                         first_seg->nb_segs++;
 865                         last_seg->next = rxm;
 866                 }
 867
 868                 /**
 869                  * If this is not the last buffer of the received packet,
 870                  * update the pointer to the last mbuf of the current scattered
 871                  * packet and continue to parse the RX ring.
 872                  */
 873                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 874                         last_seg = rxm;
 875                         continue;
 876                 }
 877
 878                 /**
 879                  * This is the last buffer of the received packet. If the CRC
 880                  * is not stripped by the hardware:
 881                  *  - Subtract the CRC length from the total packet length.
 882                  *  - If the last buffer only contains the whole CRC or a part
 883                  *  of it, free the mbuf associated to the last buffer. If part
 884                  *  of the CRC is also contained in the previous mbuf, subtract
 885                  *  the length of that CRC part from the data length of the
 886                  *  previous mbuf.
 887                  */
 888                 rxm->next = NULL;
 889                 if (unlikely(rxq->crc_len > 0)) {
 890                         first_seg->pkt_len -= ETHER_CRC_LEN;
 891                         if (rx_packet_len <= ETHER_CRC_LEN) {
 892                                 rte_pktmbuf_free_seg(rxm);
 893                                 first_seg->nb_segs--;
 894                                 last_seg->data_len =
 895                                         (uint16_t)(last_seg->data_len -
 896                                         (ETHER_CRC_LEN - rx_packet_len));
 897                                 last_seg->next = NULL;
 898                         } else
 899                                 rxm->data_len = (uint16_t)(rx_packet_len -
 900                                                                 ETHER_CRC_LEN);
 901                 }
 902
 903                 first_seg->port = rxq->port_id;
 904                 first_seg->ol_flags = 0;
 905                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 906                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 907                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 908                 first_seg->packet_type =
 909                         ptype_tbl[(uint8_t)((qword1 &
 910                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 911                 if (pkt_flags & PKT_RX_RSS_HASH)
 912                         first_seg->hash.rss =
 913                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 914                 if (pkt_flags & PKT_RX_FDIR)
 915                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 916
 917 #ifdef RTE_LIBRTE_IEEE1588
 918                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 919 #endif
 920                 first_seg->ol_flags |= pkt_flags;
 921
 922                 /* Prefetch data of first segment, if configured to do so. */
 923                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 924                         first_seg->data_off));
 925                 rx_pkts[nb_rx++] = first_seg;
 926                 first_seg = NULL;
 927         }
 928
 929         /* Record index of the next RX descriptor to probe. */
 930         rxq->rx_tail = rx_id;
 931         rxq->pkt_first_seg = first_seg;
 932         rxq->pkt_last_seg = last_seg;
 933
 934         /**
 935          * If the number of free RX descriptors is greater than the RX free
 936          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 937          * register. Update the RDT with the value of the last processed RX
 938          * descriptor minus 1, to guarantee that the RDT register is never
 939          * equal to the RDH register, which creates a "full" ring situtation
 940          * from the hardware point of view.
 941          */
 942         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 943         if (nb_hold > rxq->rx_free_thresh) {
 944                 rx_id = (uint16_t)(rx_id == 0 ?
 945                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 946                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 947                 nb_hold = 0;
 948         }
 949         rxq->nb_rx_hold = nb_hold;
 950
 951         return nb_rx;
 952 }
 953
 954 /* Check if the context descriptor is needed for TX offloading */
 955 static inline uint16_t
 956 i40e_calc_context_desc(uint64_t flags)
 957 {
 958         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 959                 PKT_TX_TCP_SEG |
 960                 PKT_TX_QINQ_PKT |
 961                 PKT_TX_TUNNEL_MASK;
 962
 963 #ifdef RTE_LIBRTE_IEEE1588
 964         mask |= PKT_TX_IEEE1588_TMST;
 965 #endif
 966
 967         return (flags & mask) ? 1 : 0;
 968 }
 969
 970 /* set i40e TSO context descriptor */
 971 static inline uint64_t
 972 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 973 {
 974         uint64_t ctx_desc = 0;
 975         uint32_t cd_cmd, hdr_len, cd_tso_len;
 976
 977         if (!tx_offload.l4_len) {
 978                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 979                 return ctx_desc;
 980         }
 981
 982         /**
 983          * in case of non tunneling packet, the outer_l2_len and
 984          * outer_l3_len must be 0.
 985          */
 986         hdr_len = tx_offload.outer_l2_len +
 987                 tx_offload.outer_l3_len +
 988                 tx_offload.l2_len +
 989                 tx_offload.l3_len +
 990                 tx_offload.l4_len;
 991
 992         cd_cmd = I40E_TX_CTX_DESC_TSO;
 993         cd_tso_len = mbuf->pkt_len - hdr_len;
 994         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 995                 ((uint64_t)cd_tso_len <<
 996                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 997                 ((uint64_t)mbuf->tso_segsz <<
 998                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 999
1000         return ctx_desc;
1001 }
1002
1003 uint16_t
1004 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1005 {
1006         struct i40e_tx_queue *txq;
1007         struct i40e_tx_entry *sw_ring;
1008         struct i40e_tx_entry *txe, *txn;
1009         volatile struct i40e_tx_desc *txd;
1010         volatile struct i40e_tx_desc *txr;
1011         struct rte_mbuf *tx_pkt;
1012         struct rte_mbuf *m_seg;
1013         uint32_t cd_tunneling_params;
1014         uint16_t tx_id;
1015         uint16_t nb_tx;
1016         uint32_t td_cmd;
1017         uint32_t td_offset;
1018         uint32_t td_tag;
1019         uint64_t ol_flags;
1020         uint16_t nb_used;
1021         uint16_t nb_ctx;
1022         uint16_t tx_last;
1023         uint16_t slen;
1024         uint64_t buf_dma_addr;
1025         union i40e_tx_offload tx_offload = {0};
1026
1027         txq = tx_queue;
1028         sw_ring = txq->sw_ring;
1029         txr = txq->tx_ring;
1030         tx_id = txq->tx_tail;
1031         txe = &sw_ring[tx_id];
1032
1033         /* Check if the descriptor ring needs to be cleaned. */
1034         if (txq->nb_tx_free < txq->tx_free_thresh)
1035                 i40e_xmit_cleanup(txq);
1036
1037         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1038                 td_cmd = 0;
1039                 td_tag = 0;
1040                 td_offset = 0;
1041
1042                 tx_pkt = *tx_pkts++;
1043                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1044
1045                 ol_flags = tx_pkt->ol_flags;
1046                 tx_offload.l2_len = tx_pkt->l2_len;
1047                 tx_offload.l3_len = tx_pkt->l3_len;
1048                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1049                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1050                 tx_offload.l4_len = tx_pkt->l4_len;
1051                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1052
1053                 /* Calculate the number of context descriptors needed. */
1054                 nb_ctx = i40e_calc_context_desc(ol_flags);
1055
1056                 /**
1057                  * The number of descriptors that must be allocated for
1058                  * a packet equals to the number of the segments of that
1059                  * packet plus 1 context descriptor if needed.
1060                  */
1061                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1062                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1063
1064                 /* Circular ring */
1065                 if (tx_last >= txq->nb_tx_desc)
1066                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1067
1068                 if (nb_used > txq->nb_tx_free) {
1069                         if (i40e_xmit_cleanup(txq) != 0) {
1070                                 if (nb_tx == 0)
1071                                         return 0;
1072                                 goto end_of_tx;
1073                         }
1074                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1075                                 while (nb_used > txq->nb_tx_free) {
1076                                         if (i40e_xmit_cleanup(txq) != 0) {
1077                                                 if (nb_tx == 0)
1078                                                         return 0;
1079                                                 goto end_of_tx;
1080                                         }
1081                                 }
1082                         }
1083                 }
1084
1085                 /* Descriptor based VLAN insertion */
1086                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1087                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1088                         td_tag = tx_pkt->vlan_tci;
1089                 }
1090
1091                 /* Always enable CRC offload insertion */
1092                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1093
1094                 /* Fill in tunneling parameters if necessary */
1095                 cd_tunneling_params = 0;
1096                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1097                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1098                                                     &cd_tunneling_params);
1099                 /* Enable checksum offloading */
1100                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1101                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1102                                                  &td_offset, tx_offload);
1103
1104                 if (nb_ctx) {
1105                         /* Setup TX context descriptor if required */
1106                         volatile struct i40e_tx_context_desc *ctx_txd =
1107                                 (volatile struct i40e_tx_context_desc *)\
1108                                                         &txr[tx_id];
1109                         uint16_t cd_l2tag2 = 0;
1110                         uint64_t cd_type_cmd_tso_mss =
1111                                 I40E_TX_DESC_DTYPE_CONTEXT;
1112
1113                         txn = &sw_ring[txe->next_id];
1114                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1115                         if (txe->mbuf != NULL) {
1116                                 rte_pktmbuf_free_seg(txe->mbuf);
1117                                 txe->mbuf = NULL;
1118                         }
1119
1120                         /* TSO enabled means no timestamp */
1121                         if (ol_flags & PKT_TX_TCP_SEG)
1122                                 cd_type_cmd_tso_mss |=
1123                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1124                         else {
1125 #ifdef RTE_LIBRTE_IEEE1588
1126                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1127                                         cd_type_cmd_tso_mss |=
1128                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1129                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1130 #endif
1131                         }
1132
1133                         ctx_txd->tunneling_params =
1134                                 rte_cpu_to_le_32(cd_tunneling_params);
1135                         if (ol_flags & PKT_TX_QINQ_PKT) {
1136                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1137                                 cd_type_cmd_tso_mss |=
1138                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1139                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1140                         }
1141                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1142                         ctx_txd->type_cmd_tso_mss =
1143                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1144
1145                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1146                                 "tunneling_params: %#x;\n"
1147                                 "l2tag2: %#hx;\n"
1148                                 "rsvd: %#hx;\n"
1149                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1150                                 tx_pkt, tx_id,
1151                                 ctx_txd->tunneling_params,
1152                                 ctx_txd->l2tag2,
1153                                 ctx_txd->rsvd,
1154                                 ctx_txd->type_cmd_tso_mss);
1155
1156                         txe->last_id = tx_last;
1157                         tx_id = txe->next_id;
1158                         txe = txn;
1159                 }
1160
1161                 m_seg = tx_pkt;
1162                 do {
1163                         txd = &txr[tx_id];
1164                         txn = &sw_ring[txe->next_id];
1165
1166                         if (txe->mbuf)
1167                                 rte_pktmbuf_free_seg(txe->mbuf);
1168                         txe->mbuf = m_seg;
1169
1170                         /* Setup TX Descriptor */
1171                         slen = m_seg->data_len;
1172                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1173
1174                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1175                                 "buf_dma_addr: %#"PRIx64";\n"
1176                                 "td_cmd: %#x;\n"
1177                                 "td_offset: %#x;\n"
1178                                 "td_len: %u;\n"
1179                                 "td_tag: %#x;\n",
1180                                 tx_pkt, tx_id, buf_dma_addr,
1181                                 td_cmd, td_offset, slen, td_tag);
1182
1183                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1184                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1185                                                 td_offset, slen, td_tag);
1186                         txe->last_id = tx_last;
1187                         tx_id = txe->next_id;
1188                         txe = txn;
1189                         m_seg = m_seg->next;
1190                 } while (m_seg != NULL);
1191
1192                 /* The last packet data descriptor needs End Of Packet (EOP) */
1193                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1194                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1195                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1196
1197                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1198                         PMD_TX_FREE_LOG(DEBUG,
1199                                         "Setting RS bit on TXD id="
1200                                         "%4u (port=%d queue=%d)",
1201                                         tx_last, txq->port_id, txq->queue_id);
1202
1203                         td_cmd |= I40E_TX_DESC_CMD_RS;
1204
1205                         /* Update txq RS bit counters */
1206                         txq->nb_tx_used = 0;
1207                 }
1208
1209                 txd->cmd_type_offset_bsz |=
1210                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1211                                         I40E_TXD_QW1_CMD_SHIFT);
1212         }
1213
1214 end_of_tx:
1215         rte_wmb();
1216
1217         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1218                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1219                    (unsigned) tx_id, (unsigned) nb_tx);
1220
1221         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1222         txq->tx_tail = tx_id;
1223
1224         return nb_tx;
1225 }
1226
1227 static __rte_always_inline int
1228 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1229 {
1230         struct i40e_tx_entry *txep;
1231         uint16_t i;
1232
1233         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1234                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1235                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1236                 return 0;
1237
1238         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1239
1240         for (i = 0; i < txq->tx_rs_thresh; i++)
1241                 rte_prefetch0((txep + i)->mbuf);
1242
1243         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1244                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1245                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1246                         txep->mbuf = NULL;
1247                 }
1248         } else {
1249                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1250                         rte_pktmbuf_free_seg(txep->mbuf);
1251                         txep->mbuf = NULL;
1252                 }
1253         }
1254
1255         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1256         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1257         if (txq->tx_next_dd >= txq->nb_tx_desc)
1258                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1259
1260         return txq->tx_rs_thresh;
1261 }
1262
1263 /* Populate 4 descriptors with data from 4 mbufs */
1264 static inline void
1265 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1266 {
1267         uint64_t dma_addr;
1268         uint32_t i;
1269
1270         for (i = 0; i < 4; i++, txdp++, pkts++) {
1271                 dma_addr = rte_mbuf_data_iova(*pkts);
1272                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1273                 txdp->cmd_type_offset_bsz =
1274                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1275                                         (*pkts)->data_len, 0);
1276         }
1277 }
1278
1279 /* Populate 1 descriptor with data from 1 mbuf */
1280 static inline void
1281 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1282 {
1283         uint64_t dma_addr;
1284
1285         dma_addr = rte_mbuf_data_iova(*pkts);
1286         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1287         txdp->cmd_type_offset_bsz =
1288                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1289                                 (*pkts)->data_len, 0);
1290 }
1291
1292 /* Fill hardware descriptor ring with mbuf data */
1293 static inline void
1294 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1295                      struct rte_mbuf **pkts,
1296                      uint16_t nb_pkts)
1297 {
1298         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1299         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1300         const int N_PER_LOOP = 4;
1301         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1302         int mainpart, leftover;
1303         int i, j;
1304
1305         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1306         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1307         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1308                 for (j = 0; j < N_PER_LOOP; ++j) {
1309                         (txep + i + j)->mbuf = *(pkts + i + j);
1310                 }
1311                 tx4(txdp + i, pkts + i);
1312         }
1313         if (unlikely(leftover > 0)) {
1314                 for (i = 0; i < leftover; ++i) {
1315                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1316                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1317                 }
1318         }
1319 }
1320
1321 static inline uint16_t
1322 tx_xmit_pkts(struct i40e_tx_queue *txq,
1323              struct rte_mbuf **tx_pkts,
1324              uint16_t nb_pkts)
1325 {
1326         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1327         uint16_t n = 0;
1328
1329         /**
1330          * Begin scanning the H/W ring for done descriptors when the number
1331          * of available descriptors drops below tx_free_thresh. For each done
1332          * descriptor, free the associated buffer.
1333          */
1334         if (txq->nb_tx_free < txq->tx_free_thresh)
1335                 i40e_tx_free_bufs(txq);
1336
1337         /* Use available descriptor only */
1338         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1339         if (unlikely(!nb_pkts))
1340                 return 0;
1341
1342         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1343         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1344                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1345                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1346                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1347                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1348                                                 I40E_TXD_QW1_CMD_SHIFT);
1349                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1350                 txq->tx_tail = 0;
1351         }
1352
1353         /* Fill hardware descriptor ring with mbuf data */
1354         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1355         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1356
1357         /* Determin if RS bit needs to be set */
1358         if (txq->tx_tail > txq->tx_next_rs) {
1359                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1360                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1361                                                 I40E_TXD_QW1_CMD_SHIFT);
1362                 txq->tx_next_rs =
1363                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1364                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1365                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1366         }
1367
1368         if (txq->tx_tail >= txq->nb_tx_desc)
1369                 txq->tx_tail = 0;
1370
1371         /* Update the tx tail register */
1372         rte_wmb();
1373         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1374
1375         return nb_pkts;
1376 }
1377
1378 static uint16_t
1379 i40e_xmit_pkts_simple(void *tx_queue,
1380                       struct rte_mbuf **tx_pkts,
1381                       uint16_t nb_pkts)
1382 {
1383         uint16_t nb_tx = 0;
1384
1385         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1386                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1387                                                 tx_pkts, nb_pkts);
1388
1389         while (nb_pkts) {
1390                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1391                                                 I40E_TX_MAX_BURST);
1392
1393                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1394                                                 &tx_pkts[nb_tx], num);
1395                 nb_tx = (uint16_t)(nb_tx + ret);
1396                 nb_pkts = (uint16_t)(nb_pkts - ret);
1397                 if (ret < num)
1398                         break;
1399         }
1400
1401         return nb_tx;
1402 }
1403
1404 static uint16_t
1405 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1406                    uint16_t nb_pkts)
1407 {
1408         uint16_t nb_tx = 0;
1409         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1410
1411         while (nb_pkts) {
1412                 uint16_t ret, num;
1413
1414                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1415                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1416                                                 num);
1417                 nb_tx += ret;
1418                 nb_pkts -= ret;
1419                 if (ret < num)
1420                         break;
1421         }
1422
1423         return nb_tx;
1424 }
1425
1426 /*********************************************************************
1427  *
1428  *  TX prep functions
1429  *
1430  **********************************************************************/
1431 uint16_t
1432 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1433                 uint16_t nb_pkts)
1434 {
1435         int i, ret;
1436         uint64_t ol_flags;
1437         struct rte_mbuf *m;
1438
1439         for (i = 0; i < nb_pkts; i++) {
1440                 m = tx_pkts[i];
1441                 ol_flags = m->ol_flags;
1442
1443                 /* Check for m->nb_segs to not exceed the limits. */
1444                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1445                         if (m->nb_segs > I40E_TX_MAX_SEG ||
1446                             m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1447                                 rte_errno = -EINVAL;
1448                                 return i;
1449                         }
1450                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1451                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1452                         /* MSS outside the range (256B - 9674B) are considered
1453                          * malicious
1454                          */
1455                         rte_errno = -EINVAL;
1456                         return i;
1457                 }
1458
1459                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1460                         rte_errno = -ENOTSUP;
1461                         return i;
1462                 }
1463
1464 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1465                 ret = rte_validate_tx_offload(m);
1466                 if (ret != 0) {
1467                         rte_errno = ret;
1468                         return i;
1469                 }
1470 #endif
1471                 ret = rte_net_intel_cksum_prepare(m);
1472                 if (ret != 0) {
1473                         rte_errno = ret;
1474                         return i;
1475                 }
1476         }
1477         return i;
1478 }
1479
1480 /*
1481  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1482  * application used, which assume having sequential ones. But from driver's
1483  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1484  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1485  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1486  * use queue_idx from 0 to 95 to access queues, while real queue would be
1487  * different. This function will do a queue mapping to find VSI the queue
1488  * belongs to.
1489  */
1490 static struct i40e_vsi*
1491 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1492 {
1493         /* the queue in MAIN VSI range */
1494         if (queue_idx < pf->main_vsi->nb_qps)
1495                 return pf->main_vsi;
1496
1497         queue_idx -= pf->main_vsi->nb_qps;
1498
1499         /* queue_idx is greater than VMDQ VSIs range */
1500         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1501                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1502                 return NULL;
1503         }
1504
1505         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1506 }
1507
1508 static uint16_t
1509 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1510 {
1511         /* the queue in MAIN VSI range */
1512         if (queue_idx < pf->main_vsi->nb_qps)
1513                 return queue_idx;
1514
1515         /* It's VMDQ queues */
1516         queue_idx -= pf->main_vsi->nb_qps;
1517
1518         if (pf->nb_cfg_vmdq_vsi)
1519                 return queue_idx % pf->vmdq_nb_qps;
1520         else {
1521                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1522                 return (uint16_t)(-1);
1523         }
1524 }
1525
1526 int
1527 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1528 {
1529         struct i40e_rx_queue *rxq;
1530         int err = -1;
1531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532
1533         PMD_INIT_FUNC_TRACE();
1534
1535         if (rx_queue_id < dev->data->nb_rx_queues) {
1536                 rxq = dev->data->rx_queues[rx_queue_id];
1537
1538                 err = i40e_alloc_rx_queue_mbufs(rxq);
1539                 if (err) {
1540                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1541                         return err;
1542                 }
1543
1544                 rte_wmb();
1545
1546                 /* Init the RX tail regieter. */
1547                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1548
1549                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1550
1551                 if (err) {
1552                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1553                                     rx_queue_id);
1554
1555                         i40e_rx_queue_release_mbufs(rxq);
1556                         i40e_reset_rx_queue(rxq);
1557                 } else
1558                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1559         }
1560
1561         return err;
1562 }
1563
1564 int
1565 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1566 {
1567         struct i40e_rx_queue *rxq;
1568         int err;
1569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         if (rx_queue_id < dev->data->nb_rx_queues) {
1572                 rxq = dev->data->rx_queues[rx_queue_id];
1573
1574                 /*
1575                 * rx_queue_id is queue id application refers to, while
1576                 * rxq->reg_idx is the real queue index.
1577                 */
1578                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1579
1580                 if (err) {
1581                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1582                                     rx_queue_id);
1583                         return err;
1584                 }
1585                 i40e_rx_queue_release_mbufs(rxq);
1586                 i40e_reset_rx_queue(rxq);
1587                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1588         }
1589
1590         return 0;
1591 }
1592
1593 int
1594 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1595 {
1596         int err = -1;
1597         struct i40e_tx_queue *txq;
1598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         if (tx_queue_id < dev->data->nb_tx_queues) {
1603                 txq = dev->data->tx_queues[tx_queue_id];
1604
1605                 /*
1606                 * tx_queue_id is queue id application refers to, while
1607                 * rxq->reg_idx is the real queue index.
1608                 */
1609                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1610                 if (err)
1611                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1612                                     tx_queue_id);
1613                 else
1614                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1615         }
1616
1617         return err;
1618 }
1619
1620 int
1621 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1622 {
1623         struct i40e_tx_queue *txq;
1624         int err;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626
1627         if (tx_queue_id < dev->data->nb_tx_queues) {
1628                 txq = dev->data->tx_queues[tx_queue_id];
1629
1630                 /*
1631                 * tx_queue_id is queue id application refers to, while
1632                 * txq->reg_idx is the real queue index.
1633                 */
1634                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1635
1636                 if (err) {
1637                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1638                                     tx_queue_id);
1639                         return err;
1640                 }
1641
1642                 i40e_tx_queue_release_mbufs(txq);
1643                 i40e_reset_tx_queue(txq);
1644                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1645         }
1646
1647         return 0;
1648 }
1649
1650 const uint32_t *
1651 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1652 {
1653         static const uint32_t ptypes[] = {
1654                 /* refers to i40e_rxd_pkt_type_mapping() */
1655                 RTE_PTYPE_L2_ETHER,
1656                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1657                 RTE_PTYPE_L2_ETHER_LLDP,
1658                 RTE_PTYPE_L2_ETHER_ARP,
1659                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1660                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1661                 RTE_PTYPE_L4_FRAG,
1662                 RTE_PTYPE_L4_ICMP,
1663                 RTE_PTYPE_L4_NONFRAG,
1664                 RTE_PTYPE_L4_SCTP,
1665                 RTE_PTYPE_L4_TCP,
1666                 RTE_PTYPE_L4_UDP,
1667                 RTE_PTYPE_TUNNEL_GRENAT,
1668                 RTE_PTYPE_TUNNEL_IP,
1669                 RTE_PTYPE_INNER_L2_ETHER,
1670                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1671                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1672                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1673                 RTE_PTYPE_INNER_L4_FRAG,
1674                 RTE_PTYPE_INNER_L4_ICMP,
1675                 RTE_PTYPE_INNER_L4_NONFRAG,
1676                 RTE_PTYPE_INNER_L4_SCTP,
1677                 RTE_PTYPE_INNER_L4_TCP,
1678                 RTE_PTYPE_INNER_L4_UDP,
1679                 RTE_PTYPE_UNKNOWN
1680         };
1681
1682         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1683 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1684             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1685 #endif
1686             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1687             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1688             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1689             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1690             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1691                 return ptypes;
1692         return NULL;
1693 }
1694
1695 int
1696 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1697                         uint16_t queue_idx,
1698                         uint16_t nb_desc,
1699                         unsigned int socket_id,
1700                         const struct rte_eth_rxconf *rx_conf,
1701                         struct rte_mempool *mp)
1702 {
1703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704         struct i40e_adapter *ad =
1705                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1706         struct i40e_vsi *vsi;
1707         struct i40e_pf *pf = NULL;
1708         struct i40e_vf *vf = NULL;
1709         struct i40e_rx_queue *rxq;
1710         const struct rte_memzone *rz;
1711         uint32_t ring_size;
1712         uint16_t len, i;
1713         uint16_t reg_idx, base, bsf, tc_mapping;
1714         int q_offset, use_def_burst_func = 1;
1715
1716         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1717                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1718                 vsi = &vf->vsi;
1719                 if (!vsi)
1720                         return -EINVAL;
1721                 reg_idx = queue_idx;
1722         } else {
1723                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1724                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1725                 if (!vsi)
1726                         return -EINVAL;
1727                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1728                 if (q_offset < 0)
1729                         return -EINVAL;
1730                 reg_idx = vsi->base_queue + q_offset;
1731         }
1732
1733         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1734             (nb_desc > I40E_MAX_RING_DESC) ||
1735             (nb_desc < I40E_MIN_RING_DESC)) {
1736                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1737                             "invalid", nb_desc);
1738                 return -EINVAL;
1739         }
1740
1741         /* Free memory if needed */
1742         if (dev->data->rx_queues[queue_idx]) {
1743                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1744                 dev->data->rx_queues[queue_idx] = NULL;
1745         }
1746
1747         /* Allocate the rx queue data structure */
1748         rxq = rte_zmalloc_socket("i40e rx queue",
1749                                  sizeof(struct i40e_rx_queue),
1750                                  RTE_CACHE_LINE_SIZE,
1751                                  socket_id);
1752         if (!rxq) {
1753                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1754                             "rx queue data structure");
1755                 return -ENOMEM;
1756         }
1757         rxq->mp = mp;
1758         rxq->nb_rx_desc = nb_desc;
1759         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1760         rxq->queue_id = queue_idx;
1761         rxq->reg_idx = reg_idx;
1762         rxq->port_id = dev->data->port_id;
1763         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1764                                                         0 : ETHER_CRC_LEN);
1765         rxq->drop_en = rx_conf->rx_drop_en;
1766         rxq->vsi = vsi;
1767         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1768
1769         /* Allocate the maximun number of RX ring hardware descriptor. */
1770         len = I40E_MAX_RING_DESC;
1771
1772         /**
1773          * Allocating a little more memory because vectorized/bulk_alloc Rx
1774          * functions doesn't check boundaries each time.
1775          */
1776         len += RTE_PMD_I40E_RX_MAX_BURST;
1777
1778         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1779                               I40E_DMA_MEM_ALIGN);
1780
1781         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1782                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1783         if (!rz) {
1784                 i40e_dev_rx_queue_release(rxq);
1785                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1786                 return -ENOMEM;
1787         }
1788
1789         /* Zero all the descriptors in the ring. */
1790         memset(rz->addr, 0, ring_size);
1791
1792         rxq->rx_ring_phys_addr = rz->iova;
1793         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1794
1795         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1796
1797         /* Allocate the software ring. */
1798         rxq->sw_ring =
1799                 rte_zmalloc_socket("i40e rx sw ring",
1800                                    sizeof(struct i40e_rx_entry) * len,
1801                                    RTE_CACHE_LINE_SIZE,
1802                                    socket_id);
1803         if (!rxq->sw_ring) {
1804                 i40e_dev_rx_queue_release(rxq);
1805                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1806                 return -ENOMEM;
1807         }
1808
1809         i40e_reset_rx_queue(rxq);
1810         rxq->q_set = TRUE;
1811         dev->data->rx_queues[queue_idx] = rxq;
1812
1813         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1814
1815         if (!use_def_burst_func) {
1816 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1817                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1818                              "satisfied. Rx Burst Bulk Alloc function will be "
1819                              "used on port=%d, queue=%d.",
1820                              rxq->port_id, rxq->queue_id);
1821 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1822         } else {
1823                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1824                              "not satisfied, Scattered Rx is requested, "
1825                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1826                              "not enabled on port=%d, queue=%d.",
1827                              rxq->port_id, rxq->queue_id);
1828                 ad->rx_bulk_alloc_allowed = false;
1829         }
1830
1831         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1832                 if (!(vsi->enabled_tc & (1 << i)))
1833                         continue;
1834                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1835                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1836                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1837                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1838                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1839
1840                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1841                         rxq->dcb_tc = i;
1842         }
1843
1844         return 0;
1845 }
1846
1847 void
1848 i40e_dev_rx_queue_release(void *rxq)
1849 {
1850         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1851
1852         if (!q) {
1853                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1854                 return;
1855         }
1856
1857         i40e_rx_queue_release_mbufs(q);
1858         rte_free(q->sw_ring);
1859         rte_free(q);
1860 }
1861
1862 uint32_t
1863 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1864 {
1865 #define I40E_RXQ_SCAN_INTERVAL 4
1866         volatile union i40e_rx_desc *rxdp;
1867         struct i40e_rx_queue *rxq;
1868         uint16_t desc = 0;
1869
1870         rxq = dev->data->rx_queues[rx_queue_id];
1871         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1872         while ((desc < rxq->nb_rx_desc) &&
1873                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1874                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1875                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1876                 /**
1877                  * Check the DD bit of a rx descriptor of each 4 in a group,
1878                  * to avoid checking too frequently and downgrading performance
1879                  * too much.
1880                  */
1881                 desc += I40E_RXQ_SCAN_INTERVAL;
1882                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1883                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1884                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1885                                         desc - rxq->nb_rx_desc]);
1886         }
1887
1888         return desc;
1889 }
1890
1891 int
1892 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1893 {
1894         volatile union i40e_rx_desc *rxdp;
1895         struct i40e_rx_queue *rxq = rx_queue;
1896         uint16_t desc;
1897         int ret;
1898
1899         if (unlikely(offset >= rxq->nb_rx_desc)) {
1900                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1901                 return 0;
1902         }
1903
1904         desc = rxq->rx_tail + offset;
1905         if (desc >= rxq->nb_rx_desc)
1906                 desc -= rxq->nb_rx_desc;
1907
1908         rxdp = &(rxq->rx_ring[desc]);
1909
1910         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1911                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1912                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1913
1914         return ret;
1915 }
1916
1917 int
1918 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1919 {
1920         struct i40e_rx_queue *rxq = rx_queue;
1921         volatile uint64_t *status;
1922         uint64_t mask;
1923         uint32_t desc;
1924
1925         if (unlikely(offset >= rxq->nb_rx_desc))
1926                 return -EINVAL;
1927
1928         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1929                 return RTE_ETH_RX_DESC_UNAVAIL;
1930
1931         desc = rxq->rx_tail + offset;
1932         if (desc >= rxq->nb_rx_desc)
1933                 desc -= rxq->nb_rx_desc;
1934
1935         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1936         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1937                 << I40E_RXD_QW1_STATUS_SHIFT);
1938         if (*status & mask)
1939                 return RTE_ETH_RX_DESC_DONE;
1940
1941         return RTE_ETH_RX_DESC_AVAIL;
1942 }
1943
1944 int
1945 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1946 {
1947         struct i40e_tx_queue *txq = tx_queue;
1948         volatile uint64_t *status;
1949         uint64_t mask, expect;
1950         uint32_t desc;
1951
1952         if (unlikely(offset >= txq->nb_tx_desc))
1953                 return -EINVAL;
1954
1955         desc = txq->tx_tail + offset;
1956         /* go to next desc that has the RS bit */
1957         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1958                 txq->tx_rs_thresh;
1959         if (desc >= txq->nb_tx_desc) {
1960                 desc -= txq->nb_tx_desc;
1961                 if (desc >= txq->nb_tx_desc)
1962                         desc -= txq->nb_tx_desc;
1963         }
1964
1965         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1966         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
1967         expect = rte_cpu_to_le_64(
1968                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
1969         if ((*status & mask) == expect)
1970                 return RTE_ETH_TX_DESC_DONE;
1971
1972         return RTE_ETH_TX_DESC_FULL;
1973 }
1974
1975 int
1976 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1977                         uint16_t queue_idx,
1978                         uint16_t nb_desc,
1979                         unsigned int socket_id,
1980                         const struct rte_eth_txconf *tx_conf)
1981 {
1982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         struct i40e_vsi *vsi;
1984         struct i40e_pf *pf = NULL;
1985         struct i40e_vf *vf = NULL;
1986         struct i40e_tx_queue *txq;
1987         const struct rte_memzone *tz;
1988         uint32_t ring_size;
1989         uint16_t tx_rs_thresh, tx_free_thresh;
1990         uint16_t reg_idx, i, base, bsf, tc_mapping;
1991         int q_offset;
1992
1993         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1994                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1995                 vsi = &vf->vsi;
1996                 if (!vsi)
1997                         return -EINVAL;
1998                 reg_idx = queue_idx;
1999         } else {
2000                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2001                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2002                 if (!vsi)
2003                         return -EINVAL;
2004                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2005                 if (q_offset < 0)
2006                         return -EINVAL;
2007                 reg_idx = vsi->base_queue + q_offset;
2008         }
2009
2010         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2011             (nb_desc > I40E_MAX_RING_DESC) ||
2012             (nb_desc < I40E_MIN_RING_DESC)) {
2013                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2014                             "invalid", nb_desc);
2015                 return -EINVAL;
2016         }
2017
2018         /**
2019          * The following two parameters control the setting of the RS bit on
2020          * transmit descriptors. TX descriptors will have their RS bit set
2021          * after txq->tx_rs_thresh descriptors have been used. The TX
2022          * descriptor ring will be cleaned after txq->tx_free_thresh
2023          * descriptors are used or if the number of descriptors required to
2024          * transmit a packet is greater than the number of free TX descriptors.
2025          *
2026          * The following constraints must be satisfied:
2027          *  - tx_rs_thresh must be greater than 0.
2028          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2029          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2030          *  - tx_rs_thresh must be a divisor of the ring size.
2031          *  - tx_free_thresh must be greater than 0.
2032          *  - tx_free_thresh must be less than the size of the ring minus 3.
2033          *
2034          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2035          * race condition, hence the maximum threshold constraints. When set
2036          * to zero use default values.
2037          */
2038         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2039                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2040         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2041                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2042         if (tx_rs_thresh >= (nb_desc - 2)) {
2043                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2044                              "number of TX descriptors minus 2. "
2045                              "(tx_rs_thresh=%u port=%d queue=%d)",
2046                              (unsigned int)tx_rs_thresh,
2047                              (int)dev->data->port_id,
2048                              (int)queue_idx);
2049                 return I40E_ERR_PARAM;
2050         }
2051         if (tx_free_thresh >= (nb_desc - 3)) {
2052                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2053                              "number of TX descriptors minus 3. "
2054                              "(tx_free_thresh=%u port=%d queue=%d)",
2055                              (unsigned int)tx_free_thresh,
2056                              (int)dev->data->port_id,
2057                              (int)queue_idx);
2058                 return I40E_ERR_PARAM;
2059         }
2060         if (tx_rs_thresh > tx_free_thresh) {
2061                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2062                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2063                              " tx_rs_thresh=%u port=%d queue=%d)",
2064                              (unsigned int)tx_free_thresh,
2065                              (unsigned int)tx_rs_thresh,
2066                              (int)dev->data->port_id,
2067                              (int)queue_idx);
2068                 return I40E_ERR_PARAM;
2069         }
2070         if ((nb_desc % tx_rs_thresh) != 0) {
2071                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2072                              "number of TX descriptors. (tx_rs_thresh=%u"
2073                              " port=%d queue=%d)",
2074                              (unsigned int)tx_rs_thresh,
2075                              (int)dev->data->port_id,
2076                              (int)queue_idx);
2077                 return I40E_ERR_PARAM;
2078         }
2079         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2080                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2081                              "tx_rs_thresh is greater than 1. "
2082                              "(tx_rs_thresh=%u port=%d queue=%d)",
2083                              (unsigned int)tx_rs_thresh,
2084                              (int)dev->data->port_id,
2085                              (int)queue_idx);
2086                 return I40E_ERR_PARAM;
2087         }
2088
2089         /* Free memory if needed. */
2090         if (dev->data->tx_queues[queue_idx]) {
2091                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2092                 dev->data->tx_queues[queue_idx] = NULL;
2093         }
2094
2095         /* Allocate the TX queue data structure. */
2096         txq = rte_zmalloc_socket("i40e tx queue",
2097                                   sizeof(struct i40e_tx_queue),
2098                                   RTE_CACHE_LINE_SIZE,
2099                                   socket_id);
2100         if (!txq) {
2101                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2102                             "tx queue structure");
2103                 return -ENOMEM;
2104         }
2105
2106         /* Allocate TX hardware ring descriptors. */
2107         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2108         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2109         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2110                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2111         if (!tz) {
2112                 i40e_dev_tx_queue_release(txq);
2113                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2114                 return -ENOMEM;
2115         }
2116
2117         txq->nb_tx_desc = nb_desc;
2118         txq->tx_rs_thresh = tx_rs_thresh;
2119         txq->tx_free_thresh = tx_free_thresh;
2120         txq->pthresh = tx_conf->tx_thresh.pthresh;
2121         txq->hthresh = tx_conf->tx_thresh.hthresh;
2122         txq->wthresh = tx_conf->tx_thresh.wthresh;
2123         txq->queue_id = queue_idx;
2124         txq->reg_idx = reg_idx;
2125         txq->port_id = dev->data->port_id;
2126         txq->txq_flags = tx_conf->txq_flags;
2127         txq->vsi = vsi;
2128         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2129
2130         txq->tx_ring_phys_addr = tz->iova;
2131         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2132
2133         /* Allocate software ring */
2134         txq->sw_ring =
2135                 rte_zmalloc_socket("i40e tx sw ring",
2136                                    sizeof(struct i40e_tx_entry) * nb_desc,
2137                                    RTE_CACHE_LINE_SIZE,
2138                                    socket_id);
2139         if (!txq->sw_ring) {
2140                 i40e_dev_tx_queue_release(txq);
2141                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2142                 return -ENOMEM;
2143         }
2144
2145         i40e_reset_tx_queue(txq);
2146         txq->q_set = TRUE;
2147         dev->data->tx_queues[queue_idx] = txq;
2148
2149         /* Use a simple TX queue without offloads or multi segs if possible */
2150         i40e_set_tx_function_flag(dev, txq);
2151
2152         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2153                 if (!(vsi->enabled_tc & (1 << i)))
2154                         continue;
2155                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2156                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2157                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2158                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2159                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2160
2161                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2162                         txq->dcb_tc = i;
2163         }
2164
2165         return 0;
2166 }
2167
2168 void
2169 i40e_dev_tx_queue_release(void *txq)
2170 {
2171         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2172
2173         if (!q) {
2174                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2175                 return;
2176         }
2177
2178         i40e_tx_queue_release_mbufs(q);
2179         rte_free(q->sw_ring);
2180         rte_free(q);
2181 }
2182
2183 const struct rte_memzone *
2184 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2185 {
2186         const struct rte_memzone *mz;
2187
2188         mz = rte_memzone_lookup(name);
2189         if (mz)
2190                 return mz;
2191
2192         mz = rte_memzone_reserve_aligned(name, len,
2193                                          socket_id, 0, I40E_RING_BASE_ALIGN);
2194         return mz;
2195 }
2196
2197 void
2198 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2199 {
2200         uint16_t i;
2201
2202         /* SSE Vector driver has a different way of releasing mbufs. */
2203         if (rxq->rx_using_sse) {
2204                 i40e_rx_queue_release_mbufs_vec(rxq);
2205                 return;
2206         }
2207
2208         if (!rxq->sw_ring) {
2209                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2210                 return;
2211         }
2212
2213         for (i = 0; i < rxq->nb_rx_desc; i++) {
2214                 if (rxq->sw_ring[i].mbuf) {
2215                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2216                         rxq->sw_ring[i].mbuf = NULL;
2217                 }
2218         }
2219 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2220         if (rxq->rx_nb_avail == 0)
2221                 return;
2222         for (i = 0; i < rxq->rx_nb_avail; i++) {
2223                 struct rte_mbuf *mbuf;
2224
2225                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2226                 rte_pktmbuf_free_seg(mbuf);
2227         }
2228         rxq->rx_nb_avail = 0;
2229 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2230 }
2231
2232 void
2233 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2234 {
2235         unsigned i;
2236         uint16_t len;
2237
2238         if (!rxq) {
2239                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2240                 return;
2241         }
2242
2243 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2244         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2245                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2246         else
2247 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2248                 len = rxq->nb_rx_desc;
2249
2250         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2251                 ((volatile char *)rxq->rx_ring)[i] = 0;
2252
2253         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2254         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2255                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2256
2257 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2258         rxq->rx_nb_avail = 0;
2259         rxq->rx_next_avail = 0;
2260         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2261 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2262         rxq->rx_tail = 0;
2263         rxq->nb_rx_hold = 0;
2264         rxq->pkt_first_seg = NULL;
2265         rxq->pkt_last_seg = NULL;
2266
2267         rxq->rxrearm_start = 0;
2268         rxq->rxrearm_nb = 0;
2269 }
2270
2271 void
2272 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2273 {
2274         struct rte_eth_dev *dev;
2275         uint16_t i;
2276
2277         dev = &rte_eth_devices[txq->port_id];
2278
2279         if (!txq || !txq->sw_ring) {
2280                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2281                 return;
2282         }
2283
2284         /**
2285          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2286          *  so need to free remains more carefully.
2287          */
2288         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2289                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2290                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2291                 if (txq->tx_tail < i) {
2292                         for (; i < txq->nb_tx_desc; i++) {
2293                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2294                                 txq->sw_ring[i].mbuf = NULL;
2295                         }
2296                         i = 0;
2297                 }
2298                 for (; i < txq->tx_tail; i++) {
2299                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2300                         txq->sw_ring[i].mbuf = NULL;
2301                 }
2302         } else {
2303                 for (i = 0; i < txq->nb_tx_desc; i++) {
2304                         if (txq->sw_ring[i].mbuf) {
2305                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2306                                 txq->sw_ring[i].mbuf = NULL;
2307                         }
2308                 }
2309         }
2310 }
2311
2312 void
2313 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2314 {
2315         struct i40e_tx_entry *txe;
2316         uint16_t i, prev, size;
2317
2318         if (!txq) {
2319                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2320                 return;
2321         }
2322
2323         txe = txq->sw_ring;
2324         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2325         for (i = 0; i < size; i++)
2326                 ((volatile char *)txq->tx_ring)[i] = 0;
2327
2328         prev = (uint16_t)(txq->nb_tx_desc - 1);
2329         for (i = 0; i < txq->nb_tx_desc; i++) {
2330                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2331
2332                 txd->cmd_type_offset_bsz =
2333                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2334                 txe[i].mbuf =  NULL;
2335                 txe[i].last_id = i;
2336                 txe[prev].next_id = i;
2337                 prev = i;
2338         }
2339
2340         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2341         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2342
2343         txq->tx_tail = 0;
2344         txq->nb_tx_used = 0;
2345
2346         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2347         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2348 }
2349
2350 /* Init the TX queue in hardware */
2351 int
2352 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2353 {
2354         enum i40e_status_code err = I40E_SUCCESS;
2355         struct i40e_vsi *vsi = txq->vsi;
2356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2357         uint16_t pf_q = txq->reg_idx;
2358         struct i40e_hmc_obj_txq tx_ctx;
2359         uint32_t qtx_ctl;
2360
2361         /* clear the context structure first */
2362         memset(&tx_ctx, 0, sizeof(tx_ctx));
2363         tx_ctx.new_context = 1;
2364         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2365         tx_ctx.qlen = txq->nb_tx_desc;
2366
2367 #ifdef RTE_LIBRTE_IEEE1588
2368         tx_ctx.timesync_ena = 1;
2369 #endif
2370         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2371         if (vsi->type == I40E_VSI_FDIR)
2372                 tx_ctx.fd_ena = TRUE;
2373
2374         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2375         if (err != I40E_SUCCESS) {
2376                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2377                 return err;
2378         }
2379
2380         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2381         if (err != I40E_SUCCESS) {
2382                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2383                 return err;
2384         }
2385
2386         /* Now associate this queue with this PCI function */
2387         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2388         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2389                                         I40E_QTX_CTL_PF_INDX_MASK);
2390         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2391         I40E_WRITE_FLUSH(hw);
2392
2393         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2394
2395         return err;
2396 }
2397
2398 int
2399 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2400 {
2401         struct i40e_rx_entry *rxe = rxq->sw_ring;
2402         uint64_t dma_addr;
2403         uint16_t i;
2404
2405         for (i = 0; i < rxq->nb_rx_desc; i++) {
2406                 volatile union i40e_rx_desc *rxd;
2407                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2408
2409                 if (unlikely(!mbuf)) {
2410                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2411                         return -ENOMEM;
2412                 }
2413
2414                 rte_mbuf_refcnt_set(mbuf, 1);
2415                 mbuf->next = NULL;
2416                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2417                 mbuf->nb_segs = 1;
2418                 mbuf->port = rxq->port_id;
2419
2420                 dma_addr =
2421                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2422
2423                 rxd = &rxq->rx_ring[i];
2424                 rxd->read.pkt_addr = dma_addr;
2425                 rxd->read.hdr_addr = 0;
2426 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2427                 rxd->read.rsvd1 = 0;
2428                 rxd->read.rsvd2 = 0;
2429 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2430
2431                 rxe[i].mbuf = mbuf;
2432         }
2433
2434         return 0;
2435 }
2436
2437 /*
2438  * Calculate the buffer length, and check the jumbo frame
2439  * and maximum packet length.
2440  */
2441 static int
2442 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2443 {
2444         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2445         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2446         struct rte_eth_dev_data *data = pf->dev_data;
2447         uint16_t buf_size, len;
2448
2449         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2450                 RTE_PKTMBUF_HEADROOM);
2451
2452         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2453                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2454         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2455                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2456                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2457                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2458                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2459                 rxq->hs_mode = i40e_header_split_enabled;
2460                 break;
2461         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2462         default:
2463                 rxq->rx_hdr_len = 0;
2464                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2465                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2466                 rxq->hs_mode = i40e_header_split_none;
2467                 break;
2468         }
2469
2470         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2471         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2472         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2473                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2474                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2475                         PMD_DRV_LOG(ERR, "maximum packet length must "
2476                                     "be larger than %u and smaller than %u,"
2477                                     "as jumbo frame is enabled",
2478                                     (uint32_t)ETHER_MAX_LEN,
2479                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2480                         return I40E_ERR_CONFIG;
2481                 }
2482         } else {
2483                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2484                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2485                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2486                                     "larger than %u and smaller than %u, "
2487                                     "as jumbo frame is disabled",
2488                                     (uint32_t)ETHER_MIN_LEN,
2489                                     (uint32_t)ETHER_MAX_LEN);
2490                         return I40E_ERR_CONFIG;
2491                 }
2492         }
2493
2494         return 0;
2495 }
2496
2497 /* Init the RX queue in hardware */
2498 int
2499 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2500 {
2501         int err = I40E_SUCCESS;
2502         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2503         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2504         uint16_t pf_q = rxq->reg_idx;
2505         uint16_t buf_size;
2506         struct i40e_hmc_obj_rxq rx_ctx;
2507
2508         err = i40e_rx_queue_config(rxq);
2509         if (err < 0) {
2510                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2511                 return err;
2512         }
2513
2514         /* Clear the context structure first */
2515         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2516         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2517         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2518
2519         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2520         rx_ctx.qlen = rxq->nb_rx_desc;
2521 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2522         rx_ctx.dsize = 1;
2523 #endif
2524         rx_ctx.dtype = rxq->hs_mode;
2525         if (rxq->hs_mode)
2526                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2527         else
2528                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2529         rx_ctx.rxmax = rxq->max_pkt_len;
2530         rx_ctx.tphrdesc_ena = 1;
2531         rx_ctx.tphwdesc_ena = 1;
2532         rx_ctx.tphdata_ena = 1;
2533         rx_ctx.tphhead_ena = 1;
2534         rx_ctx.lrxqthresh = 2;
2535         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2536         rx_ctx.l2tsel = 1;
2537         /* showiv indicates if inner VLAN is stripped inside of tunnel
2538          * packet. When set it to 1, vlan information is stripped from
2539          * the inner header, but the hardware does not put it in the
2540          * descriptor. So set it zero by default.
2541          */
2542         rx_ctx.showiv = 0;
2543         rx_ctx.prefena = 1;
2544
2545         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2546         if (err != I40E_SUCCESS) {
2547                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2548                 return err;
2549         }
2550         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2551         if (err != I40E_SUCCESS) {
2552                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2553                 return err;
2554         }
2555
2556         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2557
2558         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2559                 RTE_PKTMBUF_HEADROOM);
2560
2561         /* Check if scattered RX needs to be used. */
2562         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2563                 dev_data->scattered_rx = 1;
2564         }
2565
2566         /* Init the RX tail regieter. */
2567         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2568
2569         return 0;
2570 }
2571
2572 void
2573 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2574 {
2575         uint16_t i;
2576
2577         PMD_INIT_FUNC_TRACE();
2578
2579         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2580                 if (!dev->data->tx_queues[i])
2581                         continue;
2582                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2583                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2584         }
2585
2586         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2587                 if (!dev->data->rx_queues[i])
2588                         continue;
2589                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2590                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2591         }
2592 }
2593
2594 void
2595 i40e_dev_free_queues(struct rte_eth_dev *dev)
2596 {
2597         uint16_t i;
2598
2599         PMD_INIT_FUNC_TRACE();
2600
2601         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2602                 if (!dev->data->rx_queues[i])
2603                         continue;
2604                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2605                 dev->data->rx_queues[i] = NULL;
2606         }
2607         dev->data->nb_rx_queues = 0;
2608
2609         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2610                 if (!dev->data->tx_queues[i])
2611                         continue;
2612                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2613                 dev->data->tx_queues[i] = NULL;
2614         }
2615         dev->data->nb_tx_queues = 0;
2616 }
2617
2618 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2619 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2620
2621 enum i40e_status_code
2622 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2623 {
2624         struct i40e_tx_queue *txq;
2625         const struct rte_memzone *tz = NULL;
2626         uint32_t ring_size;
2627         struct rte_eth_dev *dev;
2628
2629         if (!pf) {
2630                 PMD_DRV_LOG(ERR, "PF is not available");
2631                 return I40E_ERR_BAD_PTR;
2632         }
2633
2634         dev = pf->adapter->eth_dev;
2635
2636         /* Allocate the TX queue data structure. */
2637         txq = rte_zmalloc_socket("i40e fdir tx queue",
2638                                   sizeof(struct i40e_tx_queue),
2639                                   RTE_CACHE_LINE_SIZE,
2640                                   SOCKET_ID_ANY);
2641         if (!txq) {
2642                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2643                                         "tx queue structure.");
2644                 return I40E_ERR_NO_MEMORY;
2645         }
2646
2647         /* Allocate TX hardware ring descriptors. */
2648         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2649         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2650
2651         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2652                                       I40E_FDIR_QUEUE_ID, ring_size,
2653                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2654         if (!tz) {
2655                 i40e_dev_tx_queue_release(txq);
2656                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2657                 return I40E_ERR_NO_MEMORY;
2658         }
2659
2660         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2661         txq->queue_id = I40E_FDIR_QUEUE_ID;
2662         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2663         txq->vsi = pf->fdir.fdir_vsi;
2664
2665         txq->tx_ring_phys_addr = tz->iova;
2666         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2667         /*
2668          * don't need to allocate software ring and reset for the fdir
2669          * program queue just set the queue has been configured.
2670          */
2671         txq->q_set = TRUE;
2672         pf->fdir.txq = txq;
2673
2674         return I40E_SUCCESS;
2675 }
2676
2677 enum i40e_status_code
2678 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2679 {
2680         struct i40e_rx_queue *rxq;
2681         const struct rte_memzone *rz = NULL;
2682         uint32_t ring_size;
2683         struct rte_eth_dev *dev;
2684
2685         if (!pf) {
2686                 PMD_DRV_LOG(ERR, "PF is not available");
2687                 return I40E_ERR_BAD_PTR;
2688         }
2689
2690         dev = pf->adapter->eth_dev;
2691
2692         /* Allocate the RX queue data structure. */
2693         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2694                                   sizeof(struct i40e_rx_queue),
2695                                   RTE_CACHE_LINE_SIZE,
2696                                   SOCKET_ID_ANY);
2697         if (!rxq) {
2698                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2699                                         "rx queue structure.");
2700                 return I40E_ERR_NO_MEMORY;
2701         }
2702
2703         /* Allocate RX hardware ring descriptors. */
2704         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2705         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2706
2707         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2708                                       I40E_FDIR_QUEUE_ID, ring_size,
2709                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2710         if (!rz) {
2711                 i40e_dev_rx_queue_release(rxq);
2712                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2713                 return I40E_ERR_NO_MEMORY;
2714         }
2715
2716         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2717         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2718         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2719         rxq->vsi = pf->fdir.fdir_vsi;
2720
2721         rxq->rx_ring_phys_addr = rz->iova;
2722         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2723         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2724
2725         /*
2726          * Don't need to allocate software ring and reset for the fdir
2727          * rx queue, just set the queue has been configured.
2728          */
2729         rxq->q_set = TRUE;
2730         pf->fdir.rxq = rxq;
2731
2732         return I40E_SUCCESS;
2733 }
2734
2735 void
2736 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2737         struct rte_eth_rxq_info *qinfo)
2738 {
2739         struct i40e_rx_queue *rxq;
2740
2741         rxq = dev->data->rx_queues[queue_id];
2742
2743         qinfo->mp = rxq->mp;
2744         qinfo->scattered_rx = dev->data->scattered_rx;
2745         qinfo->nb_desc = rxq->nb_rx_desc;
2746
2747         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2748         qinfo->conf.rx_drop_en = rxq->drop_en;
2749         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2750 }
2751
2752 void
2753 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2754         struct rte_eth_txq_info *qinfo)
2755 {
2756         struct i40e_tx_queue *txq;
2757
2758         txq = dev->data->tx_queues[queue_id];
2759
2760         qinfo->nb_desc = txq->nb_tx_desc;
2761
2762         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2763         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2764         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2765
2766         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2767         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2768         qinfo->conf.txq_flags = txq->txq_flags;
2769         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2770 }
2771
2772 void __attribute__((cold))
2773 i40e_set_rx_function(struct rte_eth_dev *dev)
2774 {
2775         struct i40e_adapter *ad =
2776                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2777         uint16_t rx_using_sse, i;
2778         /* In order to allow Vector Rx there are a few configuration
2779          * conditions to be met and Rx Bulk Allocation should be allowed.
2780          */
2781         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2782                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2783                     !ad->rx_bulk_alloc_allowed) {
2784                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2785                                      " Vector Rx preconditions",
2786                                      dev->data->port_id);
2787
2788                         ad->rx_vec_allowed = false;
2789                 }
2790                 if (ad->rx_vec_allowed) {
2791                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2792                                 struct i40e_rx_queue *rxq =
2793                                         dev->data->rx_queues[i];
2794
2795                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2796                                         ad->rx_vec_allowed = false;
2797                                         break;
2798                                 }
2799                         }
2800                 }
2801         }
2802
2803         if (dev->data->scattered_rx) {
2804                 /* Set the non-LRO scattered callback: there are Vector and
2805                  * single allocation versions.
2806                  */
2807                 if (ad->rx_vec_allowed) {
2808                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2809                                             "callback (port=%d).",
2810                                      dev->data->port_id);
2811
2812                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2813 #ifdef RTE_ARCH_X86
2814                         /*
2815                          * since AVX frequency can be different to base
2816                          * frequency, limit use of AVX2 version to later
2817                          * plaforms, not all those that could theoretically
2818                          * run it.
2819                          */
2820                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2821                                 dev->rx_pkt_burst =
2822                                         i40e_recv_scattered_pkts_vec_avx2;
2823 #endif
2824                 } else {
2825                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2826                                            "allocation callback (port=%d).",
2827                                      dev->data->port_id);
2828                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2829                 }
2830         /* If parameters allow we are going to choose between the following
2831          * callbacks:
2832          *    - Vector
2833          *    - Bulk Allocation
2834          *    - Single buffer allocation (the simplest one)
2835          */
2836         } else if (ad->rx_vec_allowed) {
2837                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2838                                     "burst size no less than %d (port=%d).",
2839                              RTE_I40E_DESCS_PER_LOOP,
2840                              dev->data->port_id);
2841
2842                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2843 #ifdef RTE_ARCH_X86
2844                 /*
2845                  * since AVX frequency can be different to base
2846                  * frequency, limit use of AVX2 version to later
2847                  * plaforms, not all those that could theoretically
2848                  * run it.
2849                  */
2850                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2851                         dev->rx_pkt_burst = i40e_recv_pkts_vec_avx2;
2852 #endif
2853         } else if (ad->rx_bulk_alloc_allowed) {
2854                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2855                                     "satisfied. Rx Burst Bulk Alloc function "
2856                                     "will be used on port=%d.",
2857                              dev->data->port_id);
2858
2859                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2860         } else {
2861                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2862                                     "satisfied, or Scattered Rx is requested "
2863                                     "(port=%d).",
2864                              dev->data->port_id);
2865
2866                 dev->rx_pkt_burst = i40e_recv_pkts;
2867         }
2868
2869         /* Propagate information about RX function choice through all queues. */
2870         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2871                 rx_using_sse =
2872                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2873                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
2874                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
2875                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
2876
2877                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2878                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2879
2880                         if (rxq)
2881                                 rxq->rx_using_sse = rx_using_sse;
2882                 }
2883         }
2884 }
2885
2886 void __attribute__((cold))
2887 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2888 {
2889         struct i40e_adapter *ad =
2890                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2891
2892         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2893         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2894                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2895                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2896                         PMD_INIT_LOG(DEBUG, "Vector tx"
2897                                      " can be enabled on this txq.");
2898
2899                 } else {
2900                         ad->tx_vec_allowed = false;
2901                 }
2902         } else {
2903                 ad->tx_simple_allowed = false;
2904         }
2905 }
2906
2907 void __attribute__((cold))
2908 i40e_set_tx_function(struct rte_eth_dev *dev)
2909 {
2910         struct i40e_adapter *ad =
2911                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2912         int i;
2913
2914         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2915                 if (ad->tx_vec_allowed) {
2916                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2917                                 struct i40e_tx_queue *txq =
2918                                         dev->data->tx_queues[i];
2919
2920                                 if (txq && i40e_txq_vec_setup(txq)) {
2921                                         ad->tx_vec_allowed = false;
2922                                         break;
2923                                 }
2924                         }
2925                 }
2926         }
2927
2928         if (ad->tx_simple_allowed) {
2929                 if (ad->tx_vec_allowed) {
2930                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2931                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2932 #ifdef RTE_ARCH_X86
2933                         /*
2934                          * since AVX frequency can be different to base
2935                          * frequency, limit use of AVX2 version to later
2936                          * plaforms, not all those that could theoretically
2937                          * run it.
2938                          */
2939                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2940                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx2;
2941 #endif
2942                 } else {
2943                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2944                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2945                 }
2946                 dev->tx_pkt_prepare = NULL;
2947         } else {
2948                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2949                 dev->tx_pkt_burst = i40e_xmit_pkts;
2950                 dev->tx_pkt_prepare = i40e_prep_pkts;
2951         }
2952 }
2953
2954 void __attribute__((cold))
2955 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
2956 {
2957         struct i40e_adapter *ad =
2958                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2959         int i;
2960
2961         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
2962                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
2963 }
2964
2965 void __attribute__((cold))
2966 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
2967 {
2968         struct i40e_adapter *ad =
2969                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         int i;
2972
2973         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
2974                 ad->pctypes_tbl[i] = 0ULL;
2975         ad->flow_types_mask = 0ULL;
2976         ad->pctypes_mask = 0ULL;
2977
2978         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
2979                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
2980         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
2981                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
2982         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
2983                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
2984         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
2985                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
2986         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
2987                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
2988         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
2989                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
2990         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
2991                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
2992         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
2993                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
2994         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
2995                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
2996         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
2997                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
2998         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
2999                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3000
3001         if (hw->mac.type == I40E_MAC_X722) {
3002                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3003                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3004                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3005                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3006                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3007                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3008                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3009                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3010                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3011                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3012                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3013                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3014         }
3015
3016         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3017                 if (ad->pctypes_tbl[i])
3018                         ad->flow_types_mask |= (1ULL << i);
3019                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3020         }
3021 }
3022
3023 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3024 int __attribute__((weak))
3025 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3026 {
3027         return -1;
3028 }
3029
3030 uint16_t __attribute__((weak))
3031 i40e_recv_pkts_vec(
3032         void __rte_unused *rx_queue,
3033         struct rte_mbuf __rte_unused **rx_pkts,
3034         uint16_t __rte_unused nb_pkts)
3035 {
3036         return 0;
3037 }
3038
3039 uint16_t __attribute__((weak))
3040 i40e_recv_scattered_pkts_vec(
3041         void __rte_unused *rx_queue,
3042         struct rte_mbuf __rte_unused **rx_pkts,
3043         uint16_t __rte_unused nb_pkts)
3044 {
3045         return 0;
3046 }
3047
3048 uint16_t __attribute__((weak))
3049 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3050                         struct rte_mbuf __rte_unused **rx_pkts,
3051                         uint16_t __rte_unused nb_pkts)
3052 {
3053         return 0;
3054 }
3055
3056 uint16_t __attribute__((weak))
3057 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3058                         struct rte_mbuf __rte_unused **rx_pkts,
3059                         uint16_t __rte_unused nb_pkts)
3060 {
3061         return 0;
3062 }
3063
3064 int __attribute__((weak))
3065 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3066 {
3067         return -1;
3068 }
3069
3070 int __attribute__((weak))
3071 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3072 {
3073         return -1;
3074 }
3075
3076 void __attribute__((weak))
3077 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3078 {
3079         return;
3080 }
3081
3082 uint16_t __attribute__((weak))
3083 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3084                           struct rte_mbuf __rte_unused **tx_pkts,
3085                           uint16_t __rte_unused nb_pkts)
3086 {
3087         return 0;
3088 }
3089
3090 uint16_t __attribute__((weak))
3091 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3092                           struct rte_mbuf __rte_unused **tx_pkts,
3093                           uint16_t __rte_unused nb_pkts)
3094 {
3095         return 0;
3096 }