drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 142                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 143                 return flags;
 144         }
 145
 146         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 147                 flags |= PKT_RX_IP_CKSUM_BAD;
 148         else
 149                 flags |= PKT_RX_IP_CKSUM_GOOD;
 150
 151         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 152                 flags |= PKT_RX_L4_CKSUM_BAD;
 153         else
 154                 flags |= PKT_RX_L4_CKSUM_GOOD;
 155
 156         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 157                 flags |= PKT_RX_EIP_CKSUM_BAD;
 158
 159         return flags;
 160 }
 161
 162 /* Function to check and set the ieee1588 timesync index and get the
 163  * appropriate flags.
 164  */
 165 #ifdef RTE_LIBRTE_IEEE1588
 166 static inline uint64_t
 167 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 168 {
 169         uint64_t pkt_flags = 0;
 170         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 171                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 172                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 173
 174         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 175                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 176                 pkt_flags = PKT_RX_IEEE1588_PTP;
 177         if (tsyn & 0x04) {
 178                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 179                 mb->timesync = tsyn & 0x03;
 180         }
 181
 182         return pkt_flags;
 183 }
 184 #endif
 185
 186 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 187 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 188 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 189 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 190 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 191
 192 static inline uint64_t
 193 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 194 {
 195         uint64_t flags = 0;
 196 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 197         uint16_t flexbh, flexbl;
 198
 199         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 200                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 201                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 202         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 203                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 204                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 205
 206
 207         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 208                 mb->hash.fdir.hi =
 209                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 210                 flags |= PKT_RX_FDIR_ID;
 211         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 212                 mb->hash.fdir.hi =
 213                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 214                 flags |= PKT_RX_FDIR_FLX;
 215         }
 216         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 217                 mb->hash.fdir.lo =
 218                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 219                 flags |= PKT_RX_FDIR_FLX;
 220         }
 221 #else
 222         mb->hash.fdir.hi =
 223                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 224         flags |= PKT_RX_FDIR_ID;
 225 #endif
 226         return flags;
 227 }
 228
 229 static inline void
 230 i40e_parse_tunneling_params(uint64_t ol_flags,
 231                             union i40e_tx_offload tx_offload,
 232                             uint32_t *cd_tunneling)
 233 {
 234         /* EIPT: External (outer) IP header type */
 235         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 236                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 237         else if (ol_flags & PKT_TX_OUTER_IPV4)
 238                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 239         else if (ol_flags & PKT_TX_OUTER_IPV6)
 240                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 241
 242         /* EIPLEN: External (outer) IP header length, in DWords */
 243         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 244                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 245
 246         /* L4TUNT: L4 Tunneling Type */
 247         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 248         case PKT_TX_TUNNEL_IPIP:
 249                 /* for non UDP / GRE tunneling, set to 00b */
 250                 break;
 251         case PKT_TX_TUNNEL_VXLAN:
 252         case PKT_TX_TUNNEL_GENEVE:
 253                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 254                 break;
 255         case PKT_TX_TUNNEL_GRE:
 256                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 257                 break;
 258         default:
 259                 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
 260                 return;
 261         }
 262
 263         /* L4TUNLEN: L4 Tunneling Length, in Words
 264          *
 265          * We depend on app to set rte_mbuf.l2_len correctly.
 266          * For IP in GRE it should be set to the length of the GRE
 267          * header;
 268          * for MAC in GRE or MAC in UDP it should be set to the length
 269          * of the GRE or UDP headers plus the inner MAC up to including
 270          * its last Ethertype.
 271          */
 272         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 273                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 274 }
 275
 276 static inline void
 277 i40e_txd_enable_checksum(uint64_t ol_flags,
 278                         uint32_t *td_cmd,
 279                         uint32_t *td_offset,
 280                         union i40e_tx_offload tx_offload)
 281 {
 282         /* Set MACLEN */
 283         if (ol_flags & PKT_TX_TUNNEL_MASK)
 284                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 285                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 286         else
 287                 *td_offset |= (tx_offload.l2_len >> 1)
 288                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 289
 290         /* Enable L3 checksum offloads */
 291         if (ol_flags & PKT_TX_IP_CKSUM) {
 292                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 293                 *td_offset |= (tx_offload.l3_len >> 2)
 294                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 295         } else if (ol_flags & PKT_TX_IPV4) {
 296                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 297                 *td_offset |= (tx_offload.l3_len >> 2)
 298                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 299         } else if (ol_flags & PKT_TX_IPV6) {
 300                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 301                 *td_offset |= (tx_offload.l3_len >> 2)
 302                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 303         }
 304
 305         if (ol_flags & PKT_TX_TCP_SEG) {
 306                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 307                 *td_offset |= (tx_offload.l4_len >> 2)
 308                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 309                 return;
 310         }
 311
 312         /* Enable L4 checksum offloads */
 313         switch (ol_flags & PKT_TX_L4_MASK) {
 314         case PKT_TX_TCP_CKSUM:
 315                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 316                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 317                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 318                 break;
 319         case PKT_TX_SCTP_CKSUM:
 320                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 321                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 322                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 323                 break;
 324         case PKT_TX_UDP_CKSUM:
 325                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 326                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 327                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 328                 break;
 329         default:
 330                 break;
 331         }
 332 }
 333
 334 /* Construct the tx flags */
 335 static inline uint64_t
 336 i40e_build_ctob(uint32_t td_cmd,
 337                 uint32_t td_offset,
 338                 unsigned int size,
 339                 uint32_t td_tag)
 340 {
 341         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 342                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 343                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 344                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 345                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 346 }
 347
 348 static inline int
 349 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 350 {
 351         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 352         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 353         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 354         uint16_t nb_tx_desc = txq->nb_tx_desc;
 355         uint16_t desc_to_clean_to;
 356         uint16_t nb_tx_to_clean;
 357
 358         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 359         if (desc_to_clean_to >= nb_tx_desc)
 360                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 361
 362         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 363         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 364                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 365                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 366                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 367                         "(port=%d queue=%d)", desc_to_clean_to,
 368                                 txq->port_id, txq->queue_id);
 369                 return -1;
 370         }
 371
 372         if (last_desc_cleaned > desc_to_clean_to)
 373                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 374                                                         desc_to_clean_to);
 375         else
 376                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 377                                         last_desc_cleaned);
 378
 379         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 380
 381         txq->last_desc_cleaned = desc_to_clean_to;
 382         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 383
 384         return 0;
 385 }
 386
 387 static inline int
 388 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 389 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 390 #else
 391 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 392 #endif
 393 {
 394         int ret = 0;
 395
 396 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 397         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 398                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 399                              "rxq->rx_free_thresh=%d, "
 400                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 401                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 402                 ret = -EINVAL;
 403         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 404                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 405                              "rxq->rx_free_thresh=%d, "
 406                              "rxq->nb_rx_desc=%d",
 407                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 408                 ret = -EINVAL;
 409         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 410                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 411                              "rxq->nb_rx_desc=%d, "
 412                              "rxq->rx_free_thresh=%d",
 413                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 414                 ret = -EINVAL;
 415         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 416                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 417                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 418                              "rxq->nb_rx_desc=%d, "
 419                              "I40E_MAX_RING_DESC=%d, "
 420                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 421                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 422                              RTE_PMD_I40E_RX_MAX_BURST);
 423                 ret = -EINVAL;
 424         }
 425 #else
 426         ret = -EINVAL;
 427 #endif
 428
 429         return ret;
 430 }
 431
 432 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 433 #define I40E_LOOK_AHEAD 8
 434 #if (I40E_LOOK_AHEAD != 8)
 435 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 436 #endif
 437 static inline int
 438 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 439 {
 440         volatile union i40e_rx_desc *rxdp;
 441         struct i40e_rx_entry *rxep;
 442         struct rte_mbuf *mb;
 443         uint16_t pkt_len;
 444         uint64_t qword1;
 445         uint32_t rx_status;
 446         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 447         int32_t i, j, nb_rx = 0;
 448         uint64_t pkt_flags;
 449
 450         rxdp = &rxq->rx_ring[rxq->rx_tail];
 451         rxep = &rxq->sw_ring[rxq->rx_tail];
 452
 453         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 454         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 455                                 I40E_RXD_QW1_STATUS_SHIFT;
 456
 457         /* Make sure there is at least 1 packet to receive */
 458         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 459                 return 0;
 460
 461         /**
 462          * Scan LOOK_AHEAD descriptors at a time to determine which
 463          * descriptors reference packets that are ready to be received.
 464          */
 465         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 466                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 467                 /* Read desc statuses backwards to avoid race condition */
 468                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 469                         qword1 = rte_le_to_cpu_64(\
 470                                 rxdp[j].wb.qword1.status_error_len);
 471                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 472                                         I40E_RXD_QW1_STATUS_SHIFT;
 473                 }
 474
 475                 rte_smp_rmb();
 476
 477                 /* Compute how many status bits were set */
 478                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 479                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 480
 481                 nb_rx += nb_dd;
 482
 483                 /* Translate descriptor info to mbuf parameters */
 484                 for (j = 0; j < nb_dd; j++) {
 485                         mb = rxep[j].mbuf;
 486                         qword1 = rte_le_to_cpu_64(\
 487                                 rxdp[j].wb.qword1.status_error_len);
 488                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 489                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 490                         mb->data_len = pkt_len;
 491                         mb->pkt_len = pkt_len;
 492                         mb->ol_flags = 0;
 493                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 494                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 495                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 496                         mb->packet_type =
 497                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 498                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 499                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 500                         if (pkt_flags & PKT_RX_RSS_HASH)
 501                                 mb->hash.rss = rte_le_to_cpu_32(\
 502                                         rxdp[j].wb.qword0.hi_dword.rss);
 503                         if (pkt_flags & PKT_RX_FDIR)
 504                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 505
 506 #ifdef RTE_LIBRTE_IEEE1588
 507                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 508 #endif
 509                         mb->ol_flags |= pkt_flags;
 510
 511                 }
 512
 513                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 514                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 515
 516                 if (nb_dd != I40E_LOOK_AHEAD)
 517                         break;
 518         }
 519
 520         /* Clear software ring entries */
 521         for (i = 0; i < nb_rx; i++)
 522                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 523
 524         return nb_rx;
 525 }
 526
 527 static inline uint16_t
 528 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 529                         struct rte_mbuf **rx_pkts,
 530                         uint16_t nb_pkts)
 531 {
 532         uint16_t i;
 533         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 534
 535         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 536
 537         for (i = 0; i < nb_pkts; i++)
 538                 rx_pkts[i] = stage[i];
 539
 540         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 541         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 542
 543         return nb_pkts;
 544 }
 545
 546 static inline int
 547 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 548 {
 549         volatile union i40e_rx_desc *rxdp;
 550         struct i40e_rx_entry *rxep;
 551         struct rte_mbuf *mb;
 552         uint16_t alloc_idx, i;
 553         uint64_t dma_addr;
 554         int diag;
 555
 556         /* Allocate buffers in bulk */
 557         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 558                                 (rxq->rx_free_thresh - 1));
 559         rxep = &(rxq->sw_ring[alloc_idx]);
 560         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 561                                         rxq->rx_free_thresh);
 562         if (unlikely(diag != 0)) {
 563                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 564                 return -ENOMEM;
 565         }
 566
 567         rxdp = &rxq->rx_ring[alloc_idx];
 568         for (i = 0; i < rxq->rx_free_thresh; i++) {
 569                 if (likely(i < (rxq->rx_free_thresh - 1)))
 570                         /* Prefetch next mbuf */
 571                         rte_prefetch0(rxep[i + 1].mbuf);
 572
 573                 mb = rxep[i].mbuf;
 574                 rte_mbuf_refcnt_set(mb, 1);
 575                 mb->next = NULL;
 576                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 577                 mb->nb_segs = 1;
 578                 mb->port = rxq->port_id;
 579                 dma_addr = rte_cpu_to_le_64(\
 580                         rte_mbuf_data_dma_addr_default(mb));
 581                 rxdp[i].read.hdr_addr = 0;
 582                 rxdp[i].read.pkt_addr = dma_addr;
 583         }
 584
 585         /* Update rx tail regsiter */
 586         rte_wmb();
 587         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 588
 589         rxq->rx_free_trigger =
 590                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 591         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 592                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 593
 594         return 0;
 595 }
 596
 597 static inline uint16_t
 598 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 599 {
 600         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 601         uint16_t nb_rx = 0;
 602
 603         if (!nb_pkts)
 604                 return 0;
 605
 606         if (rxq->rx_nb_avail)
 607                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 608
 609         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 610         rxq->rx_next_avail = 0;
 611         rxq->rx_nb_avail = nb_rx;
 612         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 613
 614         if (rxq->rx_tail > rxq->rx_free_trigger) {
 615                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 616                         uint16_t i, j;
 617
 618                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 619                                    "port_id=%u, queue_id=%u",
 620                                    rxq->port_id, rxq->queue_id);
 621                         rxq->rx_nb_avail = 0;
 622                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 623                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 624                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 625
 626                         return 0;
 627                 }
 628         }
 629
 630         if (rxq->rx_tail >= rxq->nb_rx_desc)
 631                 rxq->rx_tail = 0;
 632
 633         if (rxq->rx_nb_avail)
 634                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 635
 636         return 0;
 637 }
 638
 639 static uint16_t
 640 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 641                           struct rte_mbuf **rx_pkts,
 642                           uint16_t nb_pkts)
 643 {
 644         uint16_t nb_rx = 0, n, count;
 645
 646         if (unlikely(nb_pkts == 0))
 647                 return 0;
 648
 649         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 650                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 651
 652         while (nb_pkts) {
 653                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 654                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 655                 nb_rx = (uint16_t)(nb_rx + count);
 656                 nb_pkts = (uint16_t)(nb_pkts - count);
 657                 if (count < n)
 658                         break;
 659         }
 660
 661         return nb_rx;
 662 }
 663 #else
 664 static uint16_t
 665 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 666                           struct rte_mbuf __rte_unused **rx_pkts,
 667                           uint16_t __rte_unused nb_pkts)
 668 {
 669         return 0;
 670 }
 671 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 672
 673 uint16_t
 674 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 675 {
 676         struct i40e_rx_queue *rxq;
 677         volatile union i40e_rx_desc *rx_ring;
 678         volatile union i40e_rx_desc *rxdp;
 679         union i40e_rx_desc rxd;
 680         struct i40e_rx_entry *sw_ring;
 681         struct i40e_rx_entry *rxe;
 682         struct rte_mbuf *rxm;
 683         struct rte_mbuf *nmb;
 684         uint16_t nb_rx;
 685         uint32_t rx_status;
 686         uint64_t qword1;
 687         uint16_t rx_packet_len;
 688         uint16_t rx_id, nb_hold;
 689         uint64_t dma_addr;
 690         uint64_t pkt_flags;
 691
 692         nb_rx = 0;
 693         nb_hold = 0;
 694         rxq = rx_queue;
 695         rx_id = rxq->rx_tail;
 696         rx_ring = rxq->rx_ring;
 697         sw_ring = rxq->sw_ring;
 698
 699         while (nb_rx < nb_pkts) {
 700                 rxdp = &rx_ring[rx_id];
 701                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 702                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 703                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 704
 705                 /* Check the DD bit first */
 706                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 707                         break;
 708
 709                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 710                 if (unlikely(!nmb))
 711                         break;
 712                 rxd = *rxdp;
 713
 714                 nb_hold++;
 715                 rxe = &sw_ring[rx_id];
 716                 rx_id++;
 717                 if (unlikely(rx_id == rxq->nb_rx_desc))
 718                         rx_id = 0;
 719
 720                 /* Prefetch next mbuf */
 721                 rte_prefetch0(sw_ring[rx_id].mbuf);
 722
 723                 /**
 724                  * When next RX descriptor is on a cache line boundary,
 725                  * prefetch the next 4 RX descriptors and next 8 pointers
 726                  * to mbufs.
 727                  */
 728                 if ((rx_id & 0x3) == 0) {
 729                         rte_prefetch0(&rx_ring[rx_id]);
 730                         rte_prefetch0(&sw_ring[rx_id]);
 731                 }
 732                 rxm = rxe->mbuf;
 733                 rxe->mbuf = nmb;
 734                 dma_addr =
 735                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 736                 rxdp->read.hdr_addr = 0;
 737                 rxdp->read.pkt_addr = dma_addr;
 738
 739                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 740                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 741
 742                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 743                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 744                 rxm->nb_segs = 1;
 745                 rxm->next = NULL;
 746                 rxm->pkt_len = rx_packet_len;
 747                 rxm->data_len = rx_packet_len;
 748                 rxm->port = rxq->port_id;
 749                 rxm->ol_flags = 0;
 750                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 751                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 752                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 753                 rxm->packet_type =
 754                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 755                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 756                 if (pkt_flags & PKT_RX_RSS_HASH)
 757                         rxm->hash.rss =
 758                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 759                 if (pkt_flags & PKT_RX_FDIR)
 760                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 761
 762 #ifdef RTE_LIBRTE_IEEE1588
 763                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 764 #endif
 765                 rxm->ol_flags |= pkt_flags;
 766
 767                 rx_pkts[nb_rx++] = rxm;
 768         }
 769         rxq->rx_tail = rx_id;
 770
 771         /**
 772          * If the number of free RX descriptors is greater than the RX free
 773          * threshold of the queue, advance the receive tail register of queue.
 774          * Update that register with the value of the last processed RX
 775          * descriptor minus 1.
 776          */
 777         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 778         if (nb_hold > rxq->rx_free_thresh) {
 779                 rx_id = (uint16_t) ((rx_id == 0) ?
 780                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 781                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 782                 nb_hold = 0;
 783         }
 784         rxq->nb_rx_hold = nb_hold;
 785
 786         return nb_rx;
 787 }
 788
 789 uint16_t
 790 i40e_recv_scattered_pkts(void *rx_queue,
 791                          struct rte_mbuf **rx_pkts,
 792                          uint16_t nb_pkts)
 793 {
 794         struct i40e_rx_queue *rxq = rx_queue;
 795         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 796         volatile union i40e_rx_desc *rxdp;
 797         union i40e_rx_desc rxd;
 798         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 799         struct i40e_rx_entry *rxe;
 800         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 801         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 802         struct rte_mbuf *nmb, *rxm;
 803         uint16_t rx_id = rxq->rx_tail;
 804         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 805         uint32_t rx_status;
 806         uint64_t qword1;
 807         uint64_t dma_addr;
 808         uint64_t pkt_flags;
 809
 810         while (nb_rx < nb_pkts) {
 811                 rxdp = &rx_ring[rx_id];
 812                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 813                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 814                                         I40E_RXD_QW1_STATUS_SHIFT;
 815
 816                 /* Check the DD bit */
 817                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 818                         break;
 819
 820                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 821                 if (unlikely(!nmb))
 822                         break;
 823                 rxd = *rxdp;
 824                 nb_hold++;
 825                 rxe = &sw_ring[rx_id];
 826                 rx_id++;
 827                 if (rx_id == rxq->nb_rx_desc)
 828                         rx_id = 0;
 829
 830                 /* Prefetch next mbuf */
 831                 rte_prefetch0(sw_ring[rx_id].mbuf);
 832
 833                 /**
 834                  * When next RX descriptor is on a cache line boundary,
 835                  * prefetch the next 4 RX descriptors and next 8 pointers
 836                  * to mbufs.
 837                  */
 838                 if ((rx_id & 0x3) == 0) {
 839                         rte_prefetch0(&rx_ring[rx_id]);
 840                         rte_prefetch0(&sw_ring[rx_id]);
 841                 }
 842
 843                 rxm = rxe->mbuf;
 844                 rxe->mbuf = nmb;
 845                 dma_addr =
 846                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 847
 848                 /* Set data buffer address and data length of the mbuf */
 849                 rxdp->read.hdr_addr = 0;
 850                 rxdp->read.pkt_addr = dma_addr;
 851                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 852                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 853                 rxm->data_len = rx_packet_len;
 854                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 855
 856                 /**
 857                  * If this is the first buffer of the received packet, set the
 858                  * pointer to the first mbuf of the packet and initialize its
 859                  * context. Otherwise, update the total length and the number
 860                  * of segments of the current scattered packet, and update the
 861                  * pointer to the last mbuf of the current packet.
 862                  */
 863                 if (!first_seg) {
 864                         first_seg = rxm;
 865                         first_seg->nb_segs = 1;
 866                         first_seg->pkt_len = rx_packet_len;
 867                 } else {
 868                         first_seg->pkt_len =
 869                                 (uint16_t)(first_seg->pkt_len +
 870                                                 rx_packet_len);
 871                         first_seg->nb_segs++;
 872                         last_seg->next = rxm;
 873                 }
 874
 875                 /**
 876                  * If this is not the last buffer of the received packet,
 877                  * update the pointer to the last mbuf of the current scattered
 878                  * packet and continue to parse the RX ring.
 879                  */
 880                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 881                         last_seg = rxm;
 882                         continue;
 883                 }
 884
 885                 /**
 886                  * This is the last buffer of the received packet. If the CRC
 887                  * is not stripped by the hardware:
 888                  *  - Subtract the CRC length from the total packet length.
 889                  *  - If the last buffer only contains the whole CRC or a part
 890                  *  of it, free the mbuf associated to the last buffer. If part
 891                  *  of the CRC is also contained in the previous mbuf, subtract
 892                  *  the length of that CRC part from the data length of the
 893                  *  previous mbuf.
 894                  */
 895                 rxm->next = NULL;
 896                 if (unlikely(rxq->crc_len > 0)) {
 897                         first_seg->pkt_len -= ETHER_CRC_LEN;
 898                         if (rx_packet_len <= ETHER_CRC_LEN) {
 899                                 rte_pktmbuf_free_seg(rxm);
 900                                 first_seg->nb_segs--;
 901                                 last_seg->data_len =
 902                                         (uint16_t)(last_seg->data_len -
 903                                         (ETHER_CRC_LEN - rx_packet_len));
 904                                 last_seg->next = NULL;
 905                         } else
 906                                 rxm->data_len = (uint16_t)(rx_packet_len -
 907                                                                 ETHER_CRC_LEN);
 908                 }
 909
 910                 first_seg->port = rxq->port_id;
 911                 first_seg->ol_flags = 0;
 912                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 913                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 914                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 915                 first_seg->packet_type =
 916                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 917                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 918                 if (pkt_flags & PKT_RX_RSS_HASH)
 919                         first_seg->hash.rss =
 920                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 921                 if (pkt_flags & PKT_RX_FDIR)
 922                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 923
 924 #ifdef RTE_LIBRTE_IEEE1588
 925                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 926 #endif
 927                 first_seg->ol_flags |= pkt_flags;
 928
 929                 /* Prefetch data of first segment, if configured to do so. */
 930                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 931                         first_seg->data_off));
 932                 rx_pkts[nb_rx++] = first_seg;
 933                 first_seg = NULL;
 934         }
 935
 936         /* Record index of the next RX descriptor to probe. */
 937         rxq->rx_tail = rx_id;
 938         rxq->pkt_first_seg = first_seg;
 939         rxq->pkt_last_seg = last_seg;
 940
 941         /**
 942          * If the number of free RX descriptors is greater than the RX free
 943          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 944          * register. Update the RDT with the value of the last processed RX
 945          * descriptor minus 1, to guarantee that the RDT register is never
 946          * equal to the RDH register, which creates a "full" ring situtation
 947          * from the hardware point of view.
 948          */
 949         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 950         if (nb_hold > rxq->rx_free_thresh) {
 951                 rx_id = (uint16_t)(rx_id == 0 ?
 952                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 953                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 954                 nb_hold = 0;
 955         }
 956         rxq->nb_rx_hold = nb_hold;
 957
 958         return nb_rx;
 959 }
 960
 961 /* Check if the context descriptor is needed for TX offloading */
 962 static inline uint16_t
 963 i40e_calc_context_desc(uint64_t flags)
 964 {
 965         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 966                 PKT_TX_TCP_SEG |
 967                 PKT_TX_QINQ_PKT |
 968                 PKT_TX_TUNNEL_MASK;
 969
 970 #ifdef RTE_LIBRTE_IEEE1588
 971         mask |= PKT_TX_IEEE1588_TMST;
 972 #endif
 973
 974         return (flags & mask) ? 1 : 0;
 975 }
 976
 977 /* set i40e TSO context descriptor */
 978 static inline uint64_t
 979 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 980 {
 981         uint64_t ctx_desc = 0;
 982         uint32_t cd_cmd, hdr_len, cd_tso_len;
 983
 984         if (!tx_offload.l4_len) {
 985                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 986                 return ctx_desc;
 987         }
 988
 989         /**
 990          * in case of non tunneling packet, the outer_l2_len and
 991          * outer_l3_len must be 0.
 992          */
 993         hdr_len = tx_offload.outer_l2_len +
 994                 tx_offload.outer_l3_len +
 995                 tx_offload.l2_len +
 996                 tx_offload.l3_len +
 997                 tx_offload.l4_len;
 998
 999         cd_cmd = I40E_TX_CTX_DESC_TSO;
1000         cd_tso_len = mbuf->pkt_len - hdr_len;
1001         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1002                 ((uint64_t)cd_tso_len <<
1003                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1004                 ((uint64_t)mbuf->tso_segsz <<
1005                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1006
1007         return ctx_desc;
1008 }
1009
1010 uint16_t
1011 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1012 {
1013         struct i40e_tx_queue *txq;
1014         struct i40e_tx_entry *sw_ring;
1015         struct i40e_tx_entry *txe, *txn;
1016         volatile struct i40e_tx_desc *txd;
1017         volatile struct i40e_tx_desc *txr;
1018         struct rte_mbuf *tx_pkt;
1019         struct rte_mbuf *m_seg;
1020         uint32_t cd_tunneling_params;
1021         uint16_t tx_id;
1022         uint16_t nb_tx;
1023         uint32_t td_cmd;
1024         uint32_t td_offset;
1025         uint32_t tx_flags;
1026         uint32_t td_tag;
1027         uint64_t ol_flags;
1028         uint16_t nb_used;
1029         uint16_t nb_ctx;
1030         uint16_t tx_last;
1031         uint16_t slen;
1032         uint64_t buf_dma_addr;
1033         union i40e_tx_offload tx_offload = {0};
1034
1035         txq = tx_queue;
1036         sw_ring = txq->sw_ring;
1037         txr = txq->tx_ring;
1038         tx_id = txq->tx_tail;
1039         txe = &sw_ring[tx_id];
1040
1041         /* Check if the descriptor ring needs to be cleaned. */
1042         if (txq->nb_tx_free < txq->tx_free_thresh)
1043                 i40e_xmit_cleanup(txq);
1044
1045         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1046                 td_cmd = 0;
1047                 td_tag = 0;
1048                 td_offset = 0;
1049                 tx_flags = 0;
1050
1051                 tx_pkt = *tx_pkts++;
1052                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1053
1054                 ol_flags = tx_pkt->ol_flags;
1055                 tx_offload.l2_len = tx_pkt->l2_len;
1056                 tx_offload.l3_len = tx_pkt->l3_len;
1057                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1058                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1059                 tx_offload.l4_len = tx_pkt->l4_len;
1060                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1061
1062                 /* Calculate the number of context descriptors needed. */
1063                 nb_ctx = i40e_calc_context_desc(ol_flags);
1064
1065                 /**
1066                  * The number of descriptors that must be allocated for
1067                  * a packet equals to the number of the segments of that
1068                  * packet plus 1 context descriptor if needed.
1069                  */
1070                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1071                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1072
1073                 /* Circular ring */
1074                 if (tx_last >= txq->nb_tx_desc)
1075                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1076
1077                 if (nb_used > txq->nb_tx_free) {
1078                         if (i40e_xmit_cleanup(txq) != 0) {
1079                                 if (nb_tx == 0)
1080                                         return 0;
1081                                 goto end_of_tx;
1082                         }
1083                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1084                                 while (nb_used > txq->nb_tx_free) {
1085                                         if (i40e_xmit_cleanup(txq) != 0) {
1086                                                 if (nb_tx == 0)
1087                                                         return 0;
1088                                                 goto end_of_tx;
1089                                         }
1090                                 }
1091                         }
1092                 }
1093
1094                 /* Descriptor based VLAN insertion */
1095                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1096                         tx_flags |= tx_pkt->vlan_tci <<
1097                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1098                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1099                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1100                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1101                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1102                 }
1103
1104                 /* Always enable CRC offload insertion */
1105                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1106
1107                 /* Fill in tunneling parameters if necessary */
1108                 cd_tunneling_params = 0;
1109                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1110                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1111                                                     &cd_tunneling_params);
1112                 /* Enable checksum offloading */
1113                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1114                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1115                                                  &td_offset, tx_offload);
1116
1117                 if (nb_ctx) {
1118                         /* Setup TX context descriptor if required */
1119                         volatile struct i40e_tx_context_desc *ctx_txd =
1120                                 (volatile struct i40e_tx_context_desc *)\
1121                                                         &txr[tx_id];
1122                         uint16_t cd_l2tag2 = 0;
1123                         uint64_t cd_type_cmd_tso_mss =
1124                                 I40E_TX_DESC_DTYPE_CONTEXT;
1125
1126                         txn = &sw_ring[txe->next_id];
1127                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1128                         if (txe->mbuf != NULL) {
1129                                 rte_pktmbuf_free_seg(txe->mbuf);
1130                                 txe->mbuf = NULL;
1131                         }
1132
1133                         /* TSO enabled means no timestamp */
1134                         if (ol_flags & PKT_TX_TCP_SEG)
1135                                 cd_type_cmd_tso_mss |=
1136                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1137                         else {
1138 #ifdef RTE_LIBRTE_IEEE1588
1139                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1140                                         cd_type_cmd_tso_mss |=
1141                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1142                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1143 #endif
1144                         }
1145
1146                         ctx_txd->tunneling_params =
1147                                 rte_cpu_to_le_32(cd_tunneling_params);
1148                         if (ol_flags & PKT_TX_QINQ_PKT) {
1149                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1150                                 cd_type_cmd_tso_mss |=
1151                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1152                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1153                         }
1154                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1155                         ctx_txd->type_cmd_tso_mss =
1156                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1157
1158                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1159                                 "tunneling_params: %#x;\n"
1160                                 "l2tag2: %#hx;\n"
1161                                 "rsvd: %#hx;\n"
1162                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1163                                 tx_pkt, tx_id,
1164                                 ctx_txd->tunneling_params,
1165                                 ctx_txd->l2tag2,
1166                                 ctx_txd->rsvd,
1167                                 ctx_txd->type_cmd_tso_mss);
1168
1169                         txe->last_id = tx_last;
1170                         tx_id = txe->next_id;
1171                         txe = txn;
1172                 }
1173
1174                 m_seg = tx_pkt;
1175                 do {
1176                         txd = &txr[tx_id];
1177                         txn = &sw_ring[txe->next_id];
1178
1179                         if (txe->mbuf)
1180                                 rte_pktmbuf_free_seg(txe->mbuf);
1181                         txe->mbuf = m_seg;
1182
1183                         /* Setup TX Descriptor */
1184                         slen = m_seg->data_len;
1185                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1186
1187                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1188                                 "buf_dma_addr: %#"PRIx64";\n"
1189                                 "td_cmd: %#x;\n"
1190                                 "td_offset: %#x;\n"
1191                                 "td_len: %u;\n"
1192                                 "td_tag: %#x;\n",
1193                                 tx_pkt, tx_id, buf_dma_addr,
1194                                 td_cmd, td_offset, slen, td_tag);
1195
1196                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1197                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1198                                                 td_offset, slen, td_tag);
1199                         txe->last_id = tx_last;
1200                         tx_id = txe->next_id;
1201                         txe = txn;
1202                         m_seg = m_seg->next;
1203                 } while (m_seg != NULL);
1204
1205                 /* The last packet data descriptor needs End Of Packet (EOP) */
1206                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1207                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1208                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1209
1210                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1211                         PMD_TX_FREE_LOG(DEBUG,
1212                                         "Setting RS bit on TXD id="
1213                                         "%4u (port=%d queue=%d)",
1214                                         tx_last, txq->port_id, txq->queue_id);
1215
1216                         td_cmd |= I40E_TX_DESC_CMD_RS;
1217
1218                         /* Update txq RS bit counters */
1219                         txq->nb_tx_used = 0;
1220                 }
1221
1222                 txd->cmd_type_offset_bsz |=
1223                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1224                                         I40E_TXD_QW1_CMD_SHIFT);
1225         }
1226
1227 end_of_tx:
1228         rte_wmb();
1229
1230         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1231                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1232                    (unsigned) tx_id, (unsigned) nb_tx);
1233
1234         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1235         txq->tx_tail = tx_id;
1236
1237         return nb_tx;
1238 }
1239
1240 static inline int __attribute__((always_inline))
1241 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1242 {
1243         struct i40e_tx_entry *txep;
1244         uint16_t i;
1245
1246         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1247                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1248                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1249                 return 0;
1250
1251         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1252
1253         for (i = 0; i < txq->tx_rs_thresh; i++)
1254                 rte_prefetch0((txep + i)->mbuf);
1255
1256         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1257                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1258                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1259                         txep->mbuf = NULL;
1260                 }
1261         } else {
1262                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1263                         rte_pktmbuf_free_seg(txep->mbuf);
1264                         txep->mbuf = NULL;
1265                 }
1266         }
1267
1268         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1269         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1270         if (txq->tx_next_dd >= txq->nb_tx_desc)
1271                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1272
1273         return txq->tx_rs_thresh;
1274 }
1275
1276 /* Populate 4 descriptors with data from 4 mbufs */
1277 static inline void
1278 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1279 {
1280         uint64_t dma_addr;
1281         uint32_t i;
1282
1283         for (i = 0; i < 4; i++, txdp++, pkts++) {
1284                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1285                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1286                 txdp->cmd_type_offset_bsz =
1287                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1288                                         (*pkts)->data_len, 0);
1289         }
1290 }
1291
1292 /* Populate 1 descriptor with data from 1 mbuf */
1293 static inline void
1294 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1295 {
1296         uint64_t dma_addr;
1297
1298         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1299         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1300         txdp->cmd_type_offset_bsz =
1301                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1302                                 (*pkts)->data_len, 0);
1303 }
1304
1305 /* Fill hardware descriptor ring with mbuf data */
1306 static inline void
1307 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1308                      struct rte_mbuf **pkts,
1309                      uint16_t nb_pkts)
1310 {
1311         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1312         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1313         const int N_PER_LOOP = 4;
1314         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1315         int mainpart, leftover;
1316         int i, j;
1317
1318         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1319         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1320         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1321                 for (j = 0; j < N_PER_LOOP; ++j) {
1322                         (txep + i + j)->mbuf = *(pkts + i + j);
1323                 }
1324                 tx4(txdp + i, pkts + i);
1325         }
1326         if (unlikely(leftover > 0)) {
1327                 for (i = 0; i < leftover; ++i) {
1328                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1329                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1330                 }
1331         }
1332 }
1333
1334 static inline uint16_t
1335 tx_xmit_pkts(struct i40e_tx_queue *txq,
1336              struct rte_mbuf **tx_pkts,
1337              uint16_t nb_pkts)
1338 {
1339         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1340         uint16_t n = 0;
1341
1342         /**
1343          * Begin scanning the H/W ring for done descriptors when the number
1344          * of available descriptors drops below tx_free_thresh. For each done
1345          * descriptor, free the associated buffer.
1346          */
1347         if (txq->nb_tx_free < txq->tx_free_thresh)
1348                 i40e_tx_free_bufs(txq);
1349
1350         /* Use available descriptor only */
1351         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1352         if (unlikely(!nb_pkts))
1353                 return 0;
1354
1355         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1356         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1357                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1358                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1359                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1360                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1361                                                 I40E_TXD_QW1_CMD_SHIFT);
1362                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1363                 txq->tx_tail = 0;
1364         }
1365
1366         /* Fill hardware descriptor ring with mbuf data */
1367         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1368         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1369
1370         /* Determin if RS bit needs to be set */
1371         if (txq->tx_tail > txq->tx_next_rs) {
1372                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1373                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1374                                                 I40E_TXD_QW1_CMD_SHIFT);
1375                 txq->tx_next_rs =
1376                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1377                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1378                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1379         }
1380
1381         if (txq->tx_tail >= txq->nb_tx_desc)
1382                 txq->tx_tail = 0;
1383
1384         /* Update the tx tail register */
1385         rte_wmb();
1386         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1387
1388         return nb_pkts;
1389 }
1390
1391 static uint16_t
1392 i40e_xmit_pkts_simple(void *tx_queue,
1393                       struct rte_mbuf **tx_pkts,
1394                       uint16_t nb_pkts)
1395 {
1396         uint16_t nb_tx = 0;
1397
1398         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1399                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1400                                                 tx_pkts, nb_pkts);
1401
1402         while (nb_pkts) {
1403                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1404                                                 I40E_TX_MAX_BURST);
1405
1406                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1407                                                 &tx_pkts[nb_tx], num);
1408                 nb_tx = (uint16_t)(nb_tx + ret);
1409                 nb_pkts = (uint16_t)(nb_pkts - ret);
1410                 if (ret < num)
1411                         break;
1412         }
1413
1414         return nb_tx;
1415 }
1416
1417 /*
1418  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1419  * application used, which assume having sequential ones. But from driver's
1420  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1421  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1422  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1423  * use queue_idx from 0 to 95 to access queues, while real queue would be
1424  * different. This function will do a queue mapping to find VSI the queue
1425  * belongs to.
1426  */
1427 static struct i40e_vsi*
1428 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1429 {
1430         /* the queue in MAIN VSI range */
1431         if (queue_idx < pf->main_vsi->nb_qps)
1432                 return pf->main_vsi;
1433
1434         queue_idx -= pf->main_vsi->nb_qps;
1435
1436         /* queue_idx is greater than VMDQ VSIs range */
1437         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1438                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1439                 return NULL;
1440         }
1441
1442         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1443 }
1444
1445 static uint16_t
1446 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1447 {
1448         /* the queue in MAIN VSI range */
1449         if (queue_idx < pf->main_vsi->nb_qps)
1450                 return queue_idx;
1451
1452         /* It's VMDQ queues */
1453         queue_idx -= pf->main_vsi->nb_qps;
1454
1455         if (pf->nb_cfg_vmdq_vsi)
1456                 return queue_idx % pf->vmdq_nb_qps;
1457         else {
1458                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1459                 return (uint16_t)(-1);
1460         }
1461 }
1462
1463 int
1464 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1465 {
1466         struct i40e_rx_queue *rxq;
1467         int err = -1;
1468         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469
1470         PMD_INIT_FUNC_TRACE();
1471
1472         if (rx_queue_id < dev->data->nb_rx_queues) {
1473                 rxq = dev->data->rx_queues[rx_queue_id];
1474
1475                 err = i40e_alloc_rx_queue_mbufs(rxq);
1476                 if (err) {
1477                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1478                         return err;
1479                 }
1480
1481                 rte_wmb();
1482
1483                 /* Init the RX tail regieter. */
1484                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1485
1486                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1487
1488                 if (err) {
1489                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1490                                     rx_queue_id);
1491
1492                         i40e_rx_queue_release_mbufs(rxq);
1493                         i40e_reset_rx_queue(rxq);
1494                 } else
1495                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1496         }
1497
1498         return err;
1499 }
1500
1501 int
1502 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1503 {
1504         struct i40e_rx_queue *rxq;
1505         int err;
1506         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507
1508         if (rx_queue_id < dev->data->nb_rx_queues) {
1509                 rxq = dev->data->rx_queues[rx_queue_id];
1510
1511                 /*
1512                 * rx_queue_id is queue id aplication refers to, while
1513                 * rxq->reg_idx is the real queue index.
1514                 */
1515                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1516
1517                 if (err) {
1518                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1519                                     rx_queue_id);
1520                         return err;
1521                 }
1522                 i40e_rx_queue_release_mbufs(rxq);
1523                 i40e_reset_rx_queue(rxq);
1524                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1525         }
1526
1527         return 0;
1528 }
1529
1530 int
1531 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1532 {
1533         int err = -1;
1534         struct i40e_tx_queue *txq;
1535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         if (tx_queue_id < dev->data->nb_tx_queues) {
1540                 txq = dev->data->tx_queues[tx_queue_id];
1541
1542                 /*
1543                 * tx_queue_id is queue id aplication refers to, while
1544                 * rxq->reg_idx is the real queue index.
1545                 */
1546                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1547                 if (err)
1548                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1549                                     tx_queue_id);
1550                 else
1551                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1552         }
1553
1554         return err;
1555 }
1556
1557 int
1558 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1559 {
1560         struct i40e_tx_queue *txq;
1561         int err;
1562         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563
1564         if (tx_queue_id < dev->data->nb_tx_queues) {
1565                 txq = dev->data->tx_queues[tx_queue_id];
1566
1567                 /*
1568                 * tx_queue_id is queue id aplication refers to, while
1569                 * txq->reg_idx is the real queue index.
1570                 */
1571                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1572
1573                 if (err) {
1574                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1575                                     tx_queue_id);
1576                         return err;
1577                 }
1578
1579                 i40e_tx_queue_release_mbufs(txq);
1580                 i40e_reset_tx_queue(txq);
1581                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1582         }
1583
1584         return 0;
1585 }
1586
1587 const uint32_t *
1588 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1589 {
1590         static const uint32_t ptypes[] = {
1591                 /* refers to i40e_rxd_pkt_type_mapping() */
1592                 RTE_PTYPE_L2_ETHER,
1593                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1594                 RTE_PTYPE_L2_ETHER_LLDP,
1595                 RTE_PTYPE_L2_ETHER_ARP,
1596                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1597                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1598                 RTE_PTYPE_L4_FRAG,
1599                 RTE_PTYPE_L4_ICMP,
1600                 RTE_PTYPE_L4_NONFRAG,
1601                 RTE_PTYPE_L4_SCTP,
1602                 RTE_PTYPE_L4_TCP,
1603                 RTE_PTYPE_L4_UDP,
1604                 RTE_PTYPE_TUNNEL_GRENAT,
1605                 RTE_PTYPE_TUNNEL_IP,
1606                 RTE_PTYPE_INNER_L2_ETHER,
1607                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1608                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1609                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1610                 RTE_PTYPE_INNER_L4_FRAG,
1611                 RTE_PTYPE_INNER_L4_ICMP,
1612                 RTE_PTYPE_INNER_L4_NONFRAG,
1613                 RTE_PTYPE_INNER_L4_SCTP,
1614                 RTE_PTYPE_INNER_L4_TCP,
1615                 RTE_PTYPE_INNER_L4_UDP,
1616                 RTE_PTYPE_UNKNOWN
1617         };
1618
1619         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1620 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1621             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1622 #endif
1623             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1624             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1625             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1626                 return ptypes;
1627         return NULL;
1628 }
1629
1630 int
1631 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1632                         uint16_t queue_idx,
1633                         uint16_t nb_desc,
1634                         unsigned int socket_id,
1635                         const struct rte_eth_rxconf *rx_conf,
1636                         struct rte_mempool *mp)
1637 {
1638         struct i40e_vsi *vsi;
1639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1641         struct i40e_adapter *ad =
1642                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1643         struct i40e_rx_queue *rxq;
1644         const struct rte_memzone *rz;
1645         uint32_t ring_size;
1646         uint16_t len, i;
1647         uint16_t base, bsf, tc_mapping;
1648         int use_def_burst_func = 1;
1649
1650         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1651                 struct i40e_vf *vf =
1652                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1653                 vsi = &vf->vsi;
1654         } else
1655                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1656
1657         if (vsi == NULL) {
1658                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1659                             "index exceeds the maximum");
1660                 return I40E_ERR_PARAM;
1661         }
1662         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1663                         (nb_desc > I40E_MAX_RING_DESC) ||
1664                         (nb_desc < I40E_MIN_RING_DESC)) {
1665                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1666                             "invalid", nb_desc);
1667                 return I40E_ERR_PARAM;
1668         }
1669
1670         /* Free memory if needed */
1671         if (dev->data->rx_queues[queue_idx]) {
1672                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1673                 dev->data->rx_queues[queue_idx] = NULL;
1674         }
1675
1676         /* Allocate the rx queue data structure */
1677         rxq = rte_zmalloc_socket("i40e rx queue",
1678                                  sizeof(struct i40e_rx_queue),
1679                                  RTE_CACHE_LINE_SIZE,
1680                                  socket_id);
1681         if (!rxq) {
1682                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1683                             "rx queue data structure");
1684                 return -ENOMEM;
1685         }
1686         rxq->mp = mp;
1687         rxq->nb_rx_desc = nb_desc;
1688         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1689         rxq->queue_id = queue_idx;
1690         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1691                 rxq->reg_idx = queue_idx;
1692         else /* PF device */
1693                 rxq->reg_idx = vsi->base_queue +
1694                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1695
1696         rxq->port_id = dev->data->port_id;
1697         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1698                                                         0 : ETHER_CRC_LEN);
1699         rxq->drop_en = rx_conf->rx_drop_en;
1700         rxq->vsi = vsi;
1701         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1702
1703         /* Allocate the maximun number of RX ring hardware descriptor. */
1704         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1705         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1706         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1707                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1708         if (!rz) {
1709                 i40e_dev_rx_queue_release(rxq);
1710                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1711                 return -ENOMEM;
1712         }
1713
1714         /* Zero all the descriptors in the ring. */
1715         memset(rz->addr, 0, ring_size);
1716
1717         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1718         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1719
1720 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1721         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1722 #else
1723         len = nb_desc;
1724 #endif
1725
1726         /* Allocate the software ring. */
1727         rxq->sw_ring =
1728                 rte_zmalloc_socket("i40e rx sw ring",
1729                                    sizeof(struct i40e_rx_entry) * len,
1730                                    RTE_CACHE_LINE_SIZE,
1731                                    socket_id);
1732         if (!rxq->sw_ring) {
1733                 i40e_dev_rx_queue_release(rxq);
1734                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1735                 return -ENOMEM;
1736         }
1737
1738         i40e_reset_rx_queue(rxq);
1739         rxq->q_set = TRUE;
1740         dev->data->rx_queues[queue_idx] = rxq;
1741
1742         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1743
1744         if (!use_def_burst_func) {
1745 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1746                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1747                              "satisfied. Rx Burst Bulk Alloc function will be "
1748                              "used on port=%d, queue=%d.",
1749                              rxq->port_id, rxq->queue_id);
1750 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1751         } else {
1752                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1753                              "not satisfied, Scattered Rx is requested, "
1754                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1755                              "not enabled on port=%d, queue=%d.",
1756                              rxq->port_id, rxq->queue_id);
1757                 ad->rx_bulk_alloc_allowed = false;
1758         }
1759
1760         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1761                 if (!(vsi->enabled_tc & (1 << i)))
1762                         continue;
1763                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1764                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1765                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1766                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1767                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1768
1769                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1770                         rxq->dcb_tc = i;
1771         }
1772
1773         return 0;
1774 }
1775
1776 void
1777 i40e_dev_rx_queue_release(void *rxq)
1778 {
1779         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1780
1781         if (!q) {
1782                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1783                 return;
1784         }
1785
1786         i40e_rx_queue_release_mbufs(q);
1787         rte_free(q->sw_ring);
1788         rte_free(q);
1789 }
1790
1791 uint32_t
1792 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1793 {
1794 #define I40E_RXQ_SCAN_INTERVAL 4
1795         volatile union i40e_rx_desc *rxdp;
1796         struct i40e_rx_queue *rxq;
1797         uint16_t desc = 0;
1798
1799         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1800                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1801                 return 0;
1802         }
1803
1804         rxq = dev->data->rx_queues[rx_queue_id];
1805         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1806         while ((desc < rxq->nb_rx_desc) &&
1807                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1808                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1809                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1810                 /**
1811                  * Check the DD bit of a rx descriptor of each 4 in a group,
1812                  * to avoid checking too frequently and downgrading performance
1813                  * too much.
1814                  */
1815                 desc += I40E_RXQ_SCAN_INTERVAL;
1816                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1817                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1818                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1819                                         desc - rxq->nb_rx_desc]);
1820         }
1821
1822         return desc;
1823 }
1824
1825 int
1826 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1827 {
1828         volatile union i40e_rx_desc *rxdp;
1829         struct i40e_rx_queue *rxq = rx_queue;
1830         uint16_t desc;
1831         int ret;
1832
1833         if (unlikely(offset >= rxq->nb_rx_desc)) {
1834                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1835                 return 0;
1836         }
1837
1838         desc = rxq->rx_tail + offset;
1839         if (desc >= rxq->nb_rx_desc)
1840                 desc -= rxq->nb_rx_desc;
1841
1842         rxdp = &(rxq->rx_ring[desc]);
1843
1844         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1845                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1846                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1847
1848         return ret;
1849 }
1850
1851 int
1852 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1853                         uint16_t queue_idx,
1854                         uint16_t nb_desc,
1855                         unsigned int socket_id,
1856                         const struct rte_eth_txconf *tx_conf)
1857 {
1858         struct i40e_vsi *vsi;
1859         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1861         struct i40e_tx_queue *txq;
1862         const struct rte_memzone *tz;
1863         uint32_t ring_size;
1864         uint16_t tx_rs_thresh, tx_free_thresh;
1865         uint16_t i, base, bsf, tc_mapping;
1866
1867         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1868                 struct i40e_vf *vf =
1869                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1870                 vsi = &vf->vsi;
1871         } else
1872                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1873
1874         if (vsi == NULL) {
1875                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1876                             "exceeds the maximum", queue_idx);
1877                 return I40E_ERR_PARAM;
1878         }
1879
1880         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1881                         (nb_desc > I40E_MAX_RING_DESC) ||
1882                         (nb_desc < I40E_MIN_RING_DESC)) {
1883                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1884                             "invalid", nb_desc);
1885                 return I40E_ERR_PARAM;
1886         }
1887
1888         /**
1889          * The following two parameters control the setting of the RS bit on
1890          * transmit descriptors. TX descriptors will have their RS bit set
1891          * after txq->tx_rs_thresh descriptors have been used. The TX
1892          * descriptor ring will be cleaned after txq->tx_free_thresh
1893          * descriptors are used or if the number of descriptors required to
1894          * transmit a packet is greater than the number of free TX descriptors.
1895          *
1896          * The following constraints must be satisfied:
1897          *  - tx_rs_thresh must be greater than 0.
1898          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1899          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1900          *  - tx_rs_thresh must be a divisor of the ring size.
1901          *  - tx_free_thresh must be greater than 0.
1902          *  - tx_free_thresh must be less than the size of the ring minus 3.
1903          *
1904          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1905          * race condition, hence the maximum threshold constraints. When set
1906          * to zero use default values.
1907          */
1908         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1909                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1910         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1911                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1912         if (tx_rs_thresh >= (nb_desc - 2)) {
1913                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1914                              "number of TX descriptors minus 2. "
1915                              "(tx_rs_thresh=%u port=%d queue=%d)",
1916                              (unsigned int)tx_rs_thresh,
1917                              (int)dev->data->port_id,
1918                              (int)queue_idx);
1919                 return I40E_ERR_PARAM;
1920         }
1921         if (tx_free_thresh >= (nb_desc - 3)) {
1922                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1923                              "number of TX descriptors minus 3. "
1924                              "(tx_free_thresh=%u port=%d queue=%d)",
1925                              (unsigned int)tx_free_thresh,
1926                              (int)dev->data->port_id,
1927                              (int)queue_idx);
1928                 return I40E_ERR_PARAM;
1929         }
1930         if (tx_rs_thresh > tx_free_thresh) {
1931                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1932                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1933                              " tx_rs_thresh=%u port=%d queue=%d)",
1934                              (unsigned int)tx_free_thresh,
1935                              (unsigned int)tx_rs_thresh,
1936                              (int)dev->data->port_id,
1937                              (int)queue_idx);
1938                 return I40E_ERR_PARAM;
1939         }
1940         if ((nb_desc % tx_rs_thresh) != 0) {
1941                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1942                              "number of TX descriptors. (tx_rs_thresh=%u"
1943                              " port=%d queue=%d)",
1944                              (unsigned int)tx_rs_thresh,
1945                              (int)dev->data->port_id,
1946                              (int)queue_idx);
1947                 return I40E_ERR_PARAM;
1948         }
1949         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1950                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1951                              "tx_rs_thresh is greater than 1. "
1952                              "(tx_rs_thresh=%u port=%d queue=%d)",
1953                              (unsigned int)tx_rs_thresh,
1954                              (int)dev->data->port_id,
1955                              (int)queue_idx);
1956                 return I40E_ERR_PARAM;
1957         }
1958
1959         /* Free memory if needed. */
1960         if (dev->data->tx_queues[queue_idx]) {
1961                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1962                 dev->data->tx_queues[queue_idx] = NULL;
1963         }
1964
1965         /* Allocate the TX queue data structure. */
1966         txq = rte_zmalloc_socket("i40e tx queue",
1967                                   sizeof(struct i40e_tx_queue),
1968                                   RTE_CACHE_LINE_SIZE,
1969                                   socket_id);
1970         if (!txq) {
1971                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1972                             "tx queue structure");
1973                 return -ENOMEM;
1974         }
1975
1976         /* Allocate TX hardware ring descriptors. */
1977         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1978         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1979         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1980                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1981         if (!tz) {
1982                 i40e_dev_tx_queue_release(txq);
1983                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1984                 return -ENOMEM;
1985         }
1986
1987         txq->nb_tx_desc = nb_desc;
1988         txq->tx_rs_thresh = tx_rs_thresh;
1989         txq->tx_free_thresh = tx_free_thresh;
1990         txq->pthresh = tx_conf->tx_thresh.pthresh;
1991         txq->hthresh = tx_conf->tx_thresh.hthresh;
1992         txq->wthresh = tx_conf->tx_thresh.wthresh;
1993         txq->queue_id = queue_idx;
1994         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1995                 txq->reg_idx = queue_idx;
1996         else /* PF device */
1997                 txq->reg_idx = vsi->base_queue +
1998                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1999
2000         txq->port_id = dev->data->port_id;
2001         txq->txq_flags = tx_conf->txq_flags;
2002         txq->vsi = vsi;
2003         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2004
2005         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2006         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2007
2008         /* Allocate software ring */
2009         txq->sw_ring =
2010                 rte_zmalloc_socket("i40e tx sw ring",
2011                                    sizeof(struct i40e_tx_entry) * nb_desc,
2012                                    RTE_CACHE_LINE_SIZE,
2013                                    socket_id);
2014         if (!txq->sw_ring) {
2015                 i40e_dev_tx_queue_release(txq);
2016                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2017                 return -ENOMEM;
2018         }
2019
2020         i40e_reset_tx_queue(txq);
2021         txq->q_set = TRUE;
2022         dev->data->tx_queues[queue_idx] = txq;
2023
2024         /* Use a simple TX queue without offloads or multi segs if possible */
2025         i40e_set_tx_function_flag(dev, txq);
2026
2027         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2028                 if (!(vsi->enabled_tc & (1 << i)))
2029                         continue;
2030                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2031                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2032                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2033                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2034                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2035
2036                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2037                         txq->dcb_tc = i;
2038         }
2039
2040         return 0;
2041 }
2042
2043 void
2044 i40e_dev_tx_queue_release(void *txq)
2045 {
2046         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2047
2048         if (!q) {
2049                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2050                 return;
2051         }
2052
2053         i40e_tx_queue_release_mbufs(q);
2054         rte_free(q->sw_ring);
2055         rte_free(q);
2056 }
2057
2058 const struct rte_memzone *
2059 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2060 {
2061         const struct rte_memzone *mz;
2062
2063         mz = rte_memzone_lookup(name);
2064         if (mz)
2065                 return mz;
2066
2067         if (rte_xen_dom0_supported())
2068                 mz = rte_memzone_reserve_bounded(name, len,
2069                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2070         else
2071                 mz = rte_memzone_reserve_aligned(name, len,
2072                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2073         return mz;
2074 }
2075
2076 void
2077 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2078 {
2079         uint16_t i;
2080
2081         /* SSE Vector driver has a different way of releasing mbufs. */
2082         if (rxq->rx_using_sse) {
2083                 i40e_rx_queue_release_mbufs_vec(rxq);
2084                 return;
2085         }
2086
2087         if (!rxq->sw_ring) {
2088                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2089                 return;
2090         }
2091
2092         for (i = 0; i < rxq->nb_rx_desc; i++) {
2093                 if (rxq->sw_ring[i].mbuf) {
2094                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2095                         rxq->sw_ring[i].mbuf = NULL;
2096                 }
2097         }
2098 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2099         if (rxq->rx_nb_avail == 0)
2100                 return;
2101         for (i = 0; i < rxq->rx_nb_avail; i++) {
2102                 struct rte_mbuf *mbuf;
2103
2104                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2105                 rte_pktmbuf_free_seg(mbuf);
2106         }
2107         rxq->rx_nb_avail = 0;
2108 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2109 }
2110
2111 void
2112 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2113 {
2114         unsigned i;
2115         uint16_t len;
2116
2117         if (!rxq) {
2118                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2119                 return;
2120         }
2121
2122 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2123         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2124                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2125         else
2126 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2127                 len = rxq->nb_rx_desc;
2128
2129         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2130                 ((volatile char *)rxq->rx_ring)[i] = 0;
2131
2132 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2133         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2134         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2135                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2136
2137         rxq->rx_nb_avail = 0;
2138         rxq->rx_next_avail = 0;
2139         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2140 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2141         rxq->rx_tail = 0;
2142         rxq->nb_rx_hold = 0;
2143         rxq->pkt_first_seg = NULL;
2144         rxq->pkt_last_seg = NULL;
2145
2146         rxq->rxrearm_start = 0;
2147         rxq->rxrearm_nb = 0;
2148 }
2149
2150 void
2151 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2152 {
2153         uint16_t i;
2154
2155         if (!txq || !txq->sw_ring) {
2156                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2157                 return;
2158         }
2159
2160         for (i = 0; i < txq->nb_tx_desc; i++) {
2161                 if (txq->sw_ring[i].mbuf) {
2162                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2163                         txq->sw_ring[i].mbuf = NULL;
2164                 }
2165         }
2166 }
2167
2168 void
2169 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2170 {
2171         struct i40e_tx_entry *txe;
2172         uint16_t i, prev, size;
2173
2174         if (!txq) {
2175                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2176                 return;
2177         }
2178
2179         txe = txq->sw_ring;
2180         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2181         for (i = 0; i < size; i++)
2182                 ((volatile char *)txq->tx_ring)[i] = 0;
2183
2184         prev = (uint16_t)(txq->nb_tx_desc - 1);
2185         for (i = 0; i < txq->nb_tx_desc; i++) {
2186                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2187
2188                 txd->cmd_type_offset_bsz =
2189                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2190                 txe[i].mbuf =  NULL;
2191                 txe[i].last_id = i;
2192                 txe[prev].next_id = i;
2193                 prev = i;
2194         }
2195
2196         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2197         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2198
2199         txq->tx_tail = 0;
2200         txq->nb_tx_used = 0;
2201
2202         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2203         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2204 }
2205
2206 /* Init the TX queue in hardware */
2207 int
2208 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2209 {
2210         enum i40e_status_code err = I40E_SUCCESS;
2211         struct i40e_vsi *vsi = txq->vsi;
2212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2213         uint16_t pf_q = txq->reg_idx;
2214         struct i40e_hmc_obj_txq tx_ctx;
2215         uint32_t qtx_ctl;
2216
2217         /* clear the context structure first */
2218         memset(&tx_ctx, 0, sizeof(tx_ctx));
2219         tx_ctx.new_context = 1;
2220         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2221         tx_ctx.qlen = txq->nb_tx_desc;
2222
2223 #ifdef RTE_LIBRTE_IEEE1588
2224         tx_ctx.timesync_ena = 1;
2225 #endif
2226         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2227         if (vsi->type == I40E_VSI_FDIR)
2228                 tx_ctx.fd_ena = TRUE;
2229
2230         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2231         if (err != I40E_SUCCESS) {
2232                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2233                 return err;
2234         }
2235
2236         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2237         if (err != I40E_SUCCESS) {
2238                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2239                 return err;
2240         }
2241
2242         /* Now associate this queue with this PCI function */
2243         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2244         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2245                                         I40E_QTX_CTL_PF_INDX_MASK);
2246         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2247         I40E_WRITE_FLUSH(hw);
2248
2249         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2250
2251         return err;
2252 }
2253
2254 int
2255 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2256 {
2257         struct i40e_rx_entry *rxe = rxq->sw_ring;
2258         uint64_t dma_addr;
2259         uint16_t i;
2260
2261         for (i = 0; i < rxq->nb_rx_desc; i++) {
2262                 volatile union i40e_rx_desc *rxd;
2263                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2264
2265                 if (unlikely(!mbuf)) {
2266                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2267                         return -ENOMEM;
2268                 }
2269
2270                 rte_mbuf_refcnt_set(mbuf, 1);
2271                 mbuf->next = NULL;
2272                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2273                 mbuf->nb_segs = 1;
2274                 mbuf->port = rxq->port_id;
2275
2276                 dma_addr =
2277                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2278
2279                 rxd = &rxq->rx_ring[i];
2280                 rxd->read.pkt_addr = dma_addr;
2281                 rxd->read.hdr_addr = 0;
2282 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2283                 rxd->read.rsvd1 = 0;
2284                 rxd->read.rsvd2 = 0;
2285 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2286
2287                 rxe[i].mbuf = mbuf;
2288         }
2289
2290         return 0;
2291 }
2292
2293 /*
2294  * Calculate the buffer length, and check the jumbo frame
2295  * and maximum packet length.
2296  */
2297 static int
2298 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2299 {
2300         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2301         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2302         struct rte_eth_dev_data *data = pf->dev_data;
2303         uint16_t buf_size, len;
2304
2305         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2306                 RTE_PKTMBUF_HEADROOM);
2307
2308         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2309                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2310         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2311                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2312                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2313                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2314                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2315                 rxq->hs_mode = i40e_header_split_enabled;
2316                 break;
2317         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2318         default:
2319                 rxq->rx_hdr_len = 0;
2320                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2321                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2322                 rxq->hs_mode = i40e_header_split_none;
2323                 break;
2324         }
2325
2326         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2327         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2328         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2329                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2330                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2331                         PMD_DRV_LOG(ERR, "maximum packet length must "
2332                                     "be larger than %u and smaller than %u,"
2333                                     "as jumbo frame is enabled",
2334                                     (uint32_t)ETHER_MAX_LEN,
2335                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2336                         return I40E_ERR_CONFIG;
2337                 }
2338         } else {
2339                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2340                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2341                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2342                                     "larger than %u and smaller than %u, "
2343                                     "as jumbo frame is disabled",
2344                                     (uint32_t)ETHER_MIN_LEN,
2345                                     (uint32_t)ETHER_MAX_LEN);
2346                         return I40E_ERR_CONFIG;
2347                 }
2348         }
2349
2350         return 0;
2351 }
2352
2353 /* Init the RX queue in hardware */
2354 int
2355 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2356 {
2357         int err = I40E_SUCCESS;
2358         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2359         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2360         uint16_t pf_q = rxq->reg_idx;
2361         uint16_t buf_size;
2362         struct i40e_hmc_obj_rxq rx_ctx;
2363
2364         err = i40e_rx_queue_config(rxq);
2365         if (err < 0) {
2366                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2367                 return err;
2368         }
2369
2370         /* Clear the context structure first */
2371         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2372         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2373         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2374
2375         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2376         rx_ctx.qlen = rxq->nb_rx_desc;
2377 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2378         rx_ctx.dsize = 1;
2379 #endif
2380         rx_ctx.dtype = rxq->hs_mode;
2381         if (rxq->hs_mode)
2382                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2383         else
2384                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2385         rx_ctx.rxmax = rxq->max_pkt_len;
2386         rx_ctx.tphrdesc_ena = 1;
2387         rx_ctx.tphwdesc_ena = 1;
2388         rx_ctx.tphdata_ena = 1;
2389         rx_ctx.tphhead_ena = 1;
2390         rx_ctx.lrxqthresh = 2;
2391         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2392         rx_ctx.l2tsel = 1;
2393         /* showiv indicates if inner VLAN is stripped inside of tunnel
2394          * packet. When set it to 1, vlan information is stripped from
2395          * the inner header, but the hardware does not put it in the
2396          * descriptor. So set it zero by default.
2397          */
2398         rx_ctx.showiv = 0;
2399         rx_ctx.prefena = 1;
2400
2401         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2402         if (err != I40E_SUCCESS) {
2403                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2404                 return err;
2405         }
2406         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2407         if (err != I40E_SUCCESS) {
2408                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2409                 return err;
2410         }
2411
2412         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2413
2414         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2415                 RTE_PKTMBUF_HEADROOM);
2416
2417         /* Check if scattered RX needs to be used. */
2418         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2419                 dev_data->scattered_rx = 1;
2420         }
2421
2422         /* Init the RX tail regieter. */
2423         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2424
2425         return 0;
2426 }
2427
2428 void
2429 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2430 {
2431         uint16_t i;
2432
2433         PMD_INIT_FUNC_TRACE();
2434
2435         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2436                 if (!dev->data->tx_queues[i])
2437                         continue;
2438                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2439                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2440         }
2441
2442         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2443                 if (!dev->data->rx_queues[i])
2444                         continue;
2445                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2446                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2447         }
2448 }
2449
2450 void
2451 i40e_dev_free_queues(struct rte_eth_dev *dev)
2452 {
2453         uint16_t i;
2454
2455         PMD_INIT_FUNC_TRACE();
2456
2457         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2458                 if (!dev->data->rx_queues[i])
2459                         continue;
2460                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2461                 dev->data->rx_queues[i] = NULL;
2462         }
2463         dev->data->nb_rx_queues = 0;
2464
2465         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2466                 if (!dev->data->tx_queues[i])
2467                         continue;
2468                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2469                 dev->data->tx_queues[i] = NULL;
2470         }
2471         dev->data->nb_tx_queues = 0;
2472 }
2473
2474 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2475 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2476
2477 enum i40e_status_code
2478 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2479 {
2480         struct i40e_tx_queue *txq;
2481         const struct rte_memzone *tz = NULL;
2482         uint32_t ring_size;
2483         struct rte_eth_dev *dev;
2484
2485         if (!pf) {
2486                 PMD_DRV_LOG(ERR, "PF is not available");
2487                 return I40E_ERR_BAD_PTR;
2488         }
2489
2490         dev = pf->adapter->eth_dev;
2491
2492         /* Allocate the TX queue data structure. */
2493         txq = rte_zmalloc_socket("i40e fdir tx queue",
2494                                   sizeof(struct i40e_tx_queue),
2495                                   RTE_CACHE_LINE_SIZE,
2496                                   SOCKET_ID_ANY);
2497         if (!txq) {
2498                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2499                                         "tx queue structure.");
2500                 return I40E_ERR_NO_MEMORY;
2501         }
2502
2503         /* Allocate TX hardware ring descriptors. */
2504         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2505         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2506
2507         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2508                                       I40E_FDIR_QUEUE_ID, ring_size,
2509                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2510         if (!tz) {
2511                 i40e_dev_tx_queue_release(txq);
2512                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2513                 return I40E_ERR_NO_MEMORY;
2514         }
2515
2516         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2517         txq->queue_id = I40E_FDIR_QUEUE_ID;
2518         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2519         txq->vsi = pf->fdir.fdir_vsi;
2520
2521         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2522         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2523         /*
2524          * don't need to allocate software ring and reset for the fdir
2525          * program queue just set the queue has been configured.
2526          */
2527         txq->q_set = TRUE;
2528         pf->fdir.txq = txq;
2529
2530         return I40E_SUCCESS;
2531 }
2532
2533 enum i40e_status_code
2534 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2535 {
2536         struct i40e_rx_queue *rxq;
2537         const struct rte_memzone *rz = NULL;
2538         uint32_t ring_size;
2539         struct rte_eth_dev *dev;
2540
2541         if (!pf) {
2542                 PMD_DRV_LOG(ERR, "PF is not available");
2543                 return I40E_ERR_BAD_PTR;
2544         }
2545
2546         dev = pf->adapter->eth_dev;
2547
2548         /* Allocate the RX queue data structure. */
2549         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2550                                   sizeof(struct i40e_rx_queue),
2551                                   RTE_CACHE_LINE_SIZE,
2552                                   SOCKET_ID_ANY);
2553         if (!rxq) {
2554                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2555                                         "rx queue structure.");
2556                 return I40E_ERR_NO_MEMORY;
2557         }
2558
2559         /* Allocate RX hardware ring descriptors. */
2560         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2561         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2562
2563         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2564                                       I40E_FDIR_QUEUE_ID, ring_size,
2565                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2566         if (!rz) {
2567                 i40e_dev_rx_queue_release(rxq);
2568                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2569                 return I40E_ERR_NO_MEMORY;
2570         }
2571
2572         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2573         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2574         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2575         rxq->vsi = pf->fdir.fdir_vsi;
2576
2577         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2578         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2579
2580         /*
2581          * Don't need to allocate software ring and reset for the fdir
2582          * rx queue, just set the queue has been configured.
2583          */
2584         rxq->q_set = TRUE;
2585         pf->fdir.rxq = rxq;
2586
2587         return I40E_SUCCESS;
2588 }
2589
2590 void
2591 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2592         struct rte_eth_rxq_info *qinfo)
2593 {
2594         struct i40e_rx_queue *rxq;
2595
2596         rxq = dev->data->rx_queues[queue_id];
2597
2598         qinfo->mp = rxq->mp;
2599         qinfo->scattered_rx = dev->data->scattered_rx;
2600         qinfo->nb_desc = rxq->nb_rx_desc;
2601
2602         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2603         qinfo->conf.rx_drop_en = rxq->drop_en;
2604         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2605 }
2606
2607 void
2608 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2609         struct rte_eth_txq_info *qinfo)
2610 {
2611         struct i40e_tx_queue *txq;
2612
2613         txq = dev->data->tx_queues[queue_id];
2614
2615         qinfo->nb_desc = txq->nb_tx_desc;
2616
2617         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2618         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2619         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2620
2621         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2622         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2623         qinfo->conf.txq_flags = txq->txq_flags;
2624         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2625 }
2626
2627 void __attribute__((cold))
2628 i40e_set_rx_function(struct rte_eth_dev *dev)
2629 {
2630         struct i40e_adapter *ad =
2631                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2632         uint16_t rx_using_sse, i;
2633         /* In order to allow Vector Rx there are a few configuration
2634          * conditions to be met and Rx Bulk Allocation should be allowed.
2635          */
2636         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2637                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2638                     !ad->rx_bulk_alloc_allowed) {
2639                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2640                                      " Vector Rx preconditions",
2641                                      dev->data->port_id);
2642
2643                         ad->rx_vec_allowed = false;
2644                 }
2645                 if (ad->rx_vec_allowed) {
2646                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2647                                 struct i40e_rx_queue *rxq =
2648                                         dev->data->rx_queues[i];
2649
2650                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2651                                         ad->rx_vec_allowed = false;
2652                                         break;
2653                                 }
2654                         }
2655                 }
2656         }
2657
2658         if (dev->data->scattered_rx) {
2659                 /* Set the non-LRO scattered callback: there are Vector and
2660                  * single allocation versions.
2661                  */
2662                 if (ad->rx_vec_allowed) {
2663                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2664                                             "callback (port=%d).",
2665                                      dev->data->port_id);
2666
2667                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2668                 } else {
2669                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2670                                            "allocation callback (port=%d).",
2671                                      dev->data->port_id);
2672                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2673                 }
2674         /* If parameters allow we are going to choose between the following
2675          * callbacks:
2676          *    - Vector
2677          *    - Bulk Allocation
2678          *    - Single buffer allocation (the simplest one)
2679          */
2680         } else if (ad->rx_vec_allowed) {
2681                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2682                                     "burst size no less than %d (port=%d).",
2683                              RTE_I40E_DESCS_PER_LOOP,
2684                              dev->data->port_id);
2685
2686                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2687         } else if (ad->rx_bulk_alloc_allowed) {
2688                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2689                                     "satisfied. Rx Burst Bulk Alloc function "
2690                                     "will be used on port=%d.",
2691                              dev->data->port_id);
2692
2693                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2694         } else {
2695                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2696                                     "satisfied, or Scattered Rx is requested "
2697                                     "(port=%d).",
2698                              dev->data->port_id);
2699
2700                 dev->rx_pkt_burst = i40e_recv_pkts;
2701         }
2702
2703         /* Propagate information about RX function choice through all queues. */
2704         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2705                 rx_using_sse =
2706                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2707                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2708
2709                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2710                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2711
2712                         if (rxq)
2713                                 rxq->rx_using_sse = rx_using_sse;
2714                 }
2715         }
2716 }
2717
2718 void __attribute__((cold))
2719 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2720 {
2721         struct i40e_adapter *ad =
2722                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2723
2724         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2725         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2726                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2727                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2728                         PMD_INIT_LOG(DEBUG, "Vector tx"
2729                                      " can be enabled on this txq.");
2730
2731                 } else {
2732                         ad->tx_vec_allowed = false;
2733                 }
2734         } else {
2735                 ad->tx_simple_allowed = false;
2736         }
2737 }
2738
2739 void __attribute__((cold))
2740 i40e_set_tx_function(struct rte_eth_dev *dev)
2741 {
2742         struct i40e_adapter *ad =
2743                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2744         int i;
2745
2746         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2747                 if (ad->tx_vec_allowed) {
2748                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2749                                 struct i40e_tx_queue *txq =
2750                                         dev->data->tx_queues[i];
2751
2752                                 if (txq && i40e_txq_vec_setup(txq)) {
2753                                         ad->tx_vec_allowed = false;
2754                                         break;
2755                                 }
2756                         }
2757                 }
2758         }
2759
2760         if (ad->tx_simple_allowed) {
2761                 if (ad->tx_vec_allowed) {
2762                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2763                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2764                 } else {
2765                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2766                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2767                 }
2768         } else {
2769                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2770                 dev->tx_pkt_burst = i40e_xmit_pkts;
2771         }
2772 }
2773
2774 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2775 int __attribute__((weak))
2776 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2777 {
2778         return -1;
2779 }
2780
2781 uint16_t __attribute__((weak))
2782 i40e_recv_pkts_vec(
2783         void __rte_unused *rx_queue,
2784         struct rte_mbuf __rte_unused **rx_pkts,
2785         uint16_t __rte_unused nb_pkts)
2786 {
2787         return 0;
2788 }
2789
2790 uint16_t __attribute__((weak))
2791 i40e_recv_scattered_pkts_vec(
2792         void __rte_unused *rx_queue,
2793         struct rte_mbuf __rte_unused **rx_pkts,
2794         uint16_t __rte_unused nb_pkts)
2795 {
2796         return 0;
2797 }
2798
2799 int __attribute__((weak))
2800 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2801 {
2802         return -1;
2803 }
2804
2805 int __attribute__((weak))
2806 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2807 {
2808         return -1;
2809 }
2810
2811 void __attribute__((weak))
2812 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2813 {
2814         return;
2815 }
2816
2817 uint16_t __attribute__((weak))
2818 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2819                    struct rte_mbuf __rte_unused **tx_pkts,
2820                    uint16_t __rte_unused nb_pkts)
2821 {
2822         return 0;
2823 }