drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_OUTER_IPV4 |              \
  78                 PKT_TX_OUTER_IPV6 |              \
  79                 PKT_TX_IPV4 |                    \
  80                 PKT_TX_IPV6 |                    \
  81                 PKT_TX_IP_CKSUM |                \
  82                 PKT_TX_L4_MASK |                 \
  83                 PKT_TX_TCP_SEG |                 \
  84                 PKT_TX_OUTER_IP_CKSUM)
  85
  86 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  87                                       struct rte_mbuf **tx_pkts,
  88                                       uint16_t nb_pkts);
  89
  90 static inline void
  91 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  92 {
  93         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  94                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  95                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  96                 mb->vlan_tci =
  97                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  98                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  99                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 100         } else {
 101                 mb->vlan_tci = 0;
 102         }
 103 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 104         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 105                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 106                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 107                 mb->vlan_tci_outer = mb->vlan_tci;
 108                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 109                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 110                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 111                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 112         } else {
 113                 mb->vlan_tci_outer = 0;
 114         }
 115 #endif
 116         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 117                    mb->vlan_tci, mb->vlan_tci_outer);
 118 }
 119
 120 /* Translate the rx descriptor status to pkt flags */
 121 static inline uint64_t
 122 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 123 {
 124         uint64_t flags;
 125
 126         /* Check if RSS_HASH */
 127         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 128                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 129                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 130
 131         /* Check if FDIR Match */
 132         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 133                                                         PKT_RX_FDIR : 0);
 134
 135         return flags;
 136 }
 137
 138 static inline uint64_t
 139 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 140 {
 141         uint64_t flags = 0;
 142         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 143
 144 #define I40E_RX_ERR_BITS 0x3f
 145         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 146                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 147                 return flags;
 148         }
 149
 150         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 151                 flags |= PKT_RX_IP_CKSUM_BAD;
 152         else
 153                 flags |= PKT_RX_IP_CKSUM_GOOD;
 154
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 156                 flags |= PKT_RX_L4_CKSUM_BAD;
 157         else
 158                 flags |= PKT_RX_L4_CKSUM_GOOD;
 159
 160         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 161                 flags |= PKT_RX_EIP_CKSUM_BAD;
 162
 163         return flags;
 164 }
 165
 166 /* Function to check and set the ieee1588 timesync index and get the
 167  * appropriate flags.
 168  */
 169 #ifdef RTE_LIBRTE_IEEE1588
 170 static inline uint64_t
 171 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 172 {
 173         uint64_t pkt_flags = 0;
 174         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 175                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 176                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 177
 178         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 179                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 180                 pkt_flags = PKT_RX_IEEE1588_PTP;
 181         if (tsyn & 0x04) {
 182                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 183                 mb->timesync = tsyn & 0x03;
 184         }
 185
 186         return pkt_flags;
 187 }
 188 #endif
 189
 190 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 191 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 192 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 193 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 194 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 195
 196 static inline uint64_t
 197 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 198 {
 199         uint64_t flags = 0;
 200 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 201         uint16_t flexbh, flexbl;
 202
 203         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 204                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 205                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 206         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 207                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 208                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 209
 210
 211         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 212                 mb->hash.fdir.hi =
 213                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 214                 flags |= PKT_RX_FDIR_ID;
 215         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 216                 mb->hash.fdir.hi =
 217                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 218                 flags |= PKT_RX_FDIR_FLX;
 219         }
 220         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 221                 mb->hash.fdir.lo =
 222                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 223                 flags |= PKT_RX_FDIR_FLX;
 224         }
 225 #else
 226         mb->hash.fdir.hi =
 227                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 228         flags |= PKT_RX_FDIR_ID;
 229 #endif
 230         return flags;
 231 }
 232
 233 static inline void
 234 i40e_parse_tunneling_params(uint64_t ol_flags,
 235                             union i40e_tx_offload tx_offload,
 236                             uint32_t *cd_tunneling)
 237 {
 238         /* EIPT: External (outer) IP header type */
 239         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 240                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 241         else if (ol_flags & PKT_TX_OUTER_IPV4)
 242                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 243         else if (ol_flags & PKT_TX_OUTER_IPV6)
 244                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 245
 246         /* EIPLEN: External (outer) IP header length, in DWords */
 247         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 248                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 249
 250         /* L4TUNT: L4 Tunneling Type */
 251         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 252         case PKT_TX_TUNNEL_IPIP:
 253                 /* for non UDP / GRE tunneling, set to 00b */
 254                 break;
 255         case PKT_TX_TUNNEL_VXLAN:
 256         case PKT_TX_TUNNEL_GENEVE:
 257                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 258                 break;
 259         case PKT_TX_TUNNEL_GRE:
 260                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 261                 break;
 262         default:
 263                 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
 264                 return;
 265         }
 266
 267         /* L4TUNLEN: L4 Tunneling Length, in Words
 268          *
 269          * We depend on app to set rte_mbuf.l2_len correctly.
 270          * For IP in GRE it should be set to the length of the GRE
 271          * header;
 272          * for MAC in GRE or MAC in UDP it should be set to the length
 273          * of the GRE or UDP headers plus the inner MAC up to including
 274          * its last Ethertype.
 275          */
 276         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 277                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 278 }
 279
 280 static inline void
 281 i40e_txd_enable_checksum(uint64_t ol_flags,
 282                         uint32_t *td_cmd,
 283                         uint32_t *td_offset,
 284                         union i40e_tx_offload tx_offload)
 285 {
 286         /* Set MACLEN */
 287         if (ol_flags & PKT_TX_TUNNEL_MASK)
 288                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 289                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 290         else
 291                 *td_offset |= (tx_offload.l2_len >> 1)
 292                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 293
 294         /* Enable L3 checksum offloads */
 295         if (ol_flags & PKT_TX_IP_CKSUM) {
 296                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 297                 *td_offset |= (tx_offload.l3_len >> 2)
 298                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 299         } else if (ol_flags & PKT_TX_IPV4) {
 300                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 301                 *td_offset |= (tx_offload.l3_len >> 2)
 302                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 303         } else if (ol_flags & PKT_TX_IPV6) {
 304                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 305                 *td_offset |= (tx_offload.l3_len >> 2)
 306                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 307         }
 308
 309         if (ol_flags & PKT_TX_TCP_SEG) {
 310                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 311                 *td_offset |= (tx_offload.l4_len >> 2)
 312                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 313                 return;
 314         }
 315
 316         /* Enable L4 checksum offloads */
 317         switch (ol_flags & PKT_TX_L4_MASK) {
 318         case PKT_TX_TCP_CKSUM:
 319                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 320                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 321                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 322                 break;
 323         case PKT_TX_SCTP_CKSUM:
 324                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 325                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 326                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 327                 break;
 328         case PKT_TX_UDP_CKSUM:
 329                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 330                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 331                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 332                 break;
 333         default:
 334                 break;
 335         }
 336 }
 337
 338 /* Construct the tx flags */
 339 static inline uint64_t
 340 i40e_build_ctob(uint32_t td_cmd,
 341                 uint32_t td_offset,
 342                 unsigned int size,
 343                 uint32_t td_tag)
 344 {
 345         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 346                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 347                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 348                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 349                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 350 }
 351
 352 static inline int
 353 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 354 {
 355         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 356         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 357         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 358         uint16_t nb_tx_desc = txq->nb_tx_desc;
 359         uint16_t desc_to_clean_to;
 360         uint16_t nb_tx_to_clean;
 361
 362         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 363         if (desc_to_clean_to >= nb_tx_desc)
 364                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 365
 366         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 367         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 368                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 369                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 370                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 371                         "(port=%d queue=%d)", desc_to_clean_to,
 372                                 txq->port_id, txq->queue_id);
 373                 return -1;
 374         }
 375
 376         if (last_desc_cleaned > desc_to_clean_to)
 377                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 378                                                         desc_to_clean_to);
 379         else
 380                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 381                                         last_desc_cleaned);
 382
 383         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 384
 385         txq->last_desc_cleaned = desc_to_clean_to;
 386         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 387
 388         return 0;
 389 }
 390
 391 static inline int
 392 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 393 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 394 #else
 395 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 396 #endif
 397 {
 398         int ret = 0;
 399
 400 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 401         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 402                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 403                              "rxq->rx_free_thresh=%d, "
 404                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 405                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 406                 ret = -EINVAL;
 407         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 408                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 409                              "rxq->rx_free_thresh=%d, "
 410                              "rxq->nb_rx_desc=%d",
 411                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 412                 ret = -EINVAL;
 413         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 414                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 415                              "rxq->nb_rx_desc=%d, "
 416                              "rxq->rx_free_thresh=%d",
 417                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 418                 ret = -EINVAL;
 419         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 420                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 421                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 422                              "rxq->nb_rx_desc=%d, "
 423                              "I40E_MAX_RING_DESC=%d, "
 424                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 425                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 426                              RTE_PMD_I40E_RX_MAX_BURST);
 427                 ret = -EINVAL;
 428         }
 429 #else
 430         ret = -EINVAL;
 431 #endif
 432
 433         return ret;
 434 }
 435
 436 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 437 #define I40E_LOOK_AHEAD 8
 438 #if (I40E_LOOK_AHEAD != 8)
 439 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 440 #endif
 441 static inline int
 442 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 443 {
 444         volatile union i40e_rx_desc *rxdp;
 445         struct i40e_rx_entry *rxep;
 446         struct rte_mbuf *mb;
 447         uint16_t pkt_len;
 448         uint64_t qword1;
 449         uint32_t rx_status;
 450         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 451         int32_t i, j, nb_rx = 0;
 452         uint64_t pkt_flags;
 453
 454         rxdp = &rxq->rx_ring[rxq->rx_tail];
 455         rxep = &rxq->sw_ring[rxq->rx_tail];
 456
 457         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 458         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 459                                 I40E_RXD_QW1_STATUS_SHIFT;
 460
 461         /* Make sure there is at least 1 packet to receive */
 462         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 463                 return 0;
 464
 465         /**
 466          * Scan LOOK_AHEAD descriptors at a time to determine which
 467          * descriptors reference packets that are ready to be received.
 468          */
 469         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 470                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 471                 /* Read desc statuses backwards to avoid race condition */
 472                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 473                         qword1 = rte_le_to_cpu_64(\
 474                                 rxdp[j].wb.qword1.status_error_len);
 475                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 476                                         I40E_RXD_QW1_STATUS_SHIFT;
 477                 }
 478
 479                 rte_smp_rmb();
 480
 481                 /* Compute how many status bits were set */
 482                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 483                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 484
 485                 nb_rx += nb_dd;
 486
 487                 /* Translate descriptor info to mbuf parameters */
 488                 for (j = 0; j < nb_dd; j++) {
 489                         mb = rxep[j].mbuf;
 490                         qword1 = rte_le_to_cpu_64(\
 491                                 rxdp[j].wb.qword1.status_error_len);
 492                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 493                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 494                         mb->data_len = pkt_len;
 495                         mb->pkt_len = pkt_len;
 496                         mb->ol_flags = 0;
 497                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 498                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 499                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 500                         mb->packet_type =
 501                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 502                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 503                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 504                         if (pkt_flags & PKT_RX_RSS_HASH)
 505                                 mb->hash.rss = rte_le_to_cpu_32(\
 506                                         rxdp[j].wb.qword0.hi_dword.rss);
 507                         if (pkt_flags & PKT_RX_FDIR)
 508                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 509
 510 #ifdef RTE_LIBRTE_IEEE1588
 511                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 512 #endif
 513                         mb->ol_flags |= pkt_flags;
 514
 515                 }
 516
 517                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 518                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 519
 520                 if (nb_dd != I40E_LOOK_AHEAD)
 521                         break;
 522         }
 523
 524         /* Clear software ring entries */
 525         for (i = 0; i < nb_rx; i++)
 526                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 527
 528         return nb_rx;
 529 }
 530
 531 static inline uint16_t
 532 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 533                         struct rte_mbuf **rx_pkts,
 534                         uint16_t nb_pkts)
 535 {
 536         uint16_t i;
 537         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 538
 539         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 540
 541         for (i = 0; i < nb_pkts; i++)
 542                 rx_pkts[i] = stage[i];
 543
 544         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 545         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 546
 547         return nb_pkts;
 548 }
 549
 550 static inline int
 551 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 552 {
 553         volatile union i40e_rx_desc *rxdp;
 554         struct i40e_rx_entry *rxep;
 555         struct rte_mbuf *mb;
 556         uint16_t alloc_idx, i;
 557         uint64_t dma_addr;
 558         int diag;
 559
 560         /* Allocate buffers in bulk */
 561         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 562                                 (rxq->rx_free_thresh - 1));
 563         rxep = &(rxq->sw_ring[alloc_idx]);
 564         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 565                                         rxq->rx_free_thresh);
 566         if (unlikely(diag != 0)) {
 567                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 568                 return -ENOMEM;
 569         }
 570
 571         rxdp = &rxq->rx_ring[alloc_idx];
 572         for (i = 0; i < rxq->rx_free_thresh; i++) {
 573                 if (likely(i < (rxq->rx_free_thresh - 1)))
 574                         /* Prefetch next mbuf */
 575                         rte_prefetch0(rxep[i + 1].mbuf);
 576
 577                 mb = rxep[i].mbuf;
 578                 rte_mbuf_refcnt_set(mb, 1);
 579                 mb->next = NULL;
 580                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 581                 mb->nb_segs = 1;
 582                 mb->port = rxq->port_id;
 583                 dma_addr = rte_cpu_to_le_64(\
 584                         rte_mbuf_data_dma_addr_default(mb));
 585                 rxdp[i].read.hdr_addr = 0;
 586                 rxdp[i].read.pkt_addr = dma_addr;
 587         }
 588
 589         /* Update rx tail regsiter */
 590         rte_wmb();
 591         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 592
 593         rxq->rx_free_trigger =
 594                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 595         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 596                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 597
 598         return 0;
 599 }
 600
 601 static inline uint16_t
 602 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 603 {
 604         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 605         struct rte_eth_dev *dev;
 606         uint16_t nb_rx = 0;
 607
 608         if (!nb_pkts)
 609                 return 0;
 610
 611         if (rxq->rx_nb_avail)
 612                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 613
 614         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 615         rxq->rx_next_avail = 0;
 616         rxq->rx_nb_avail = nb_rx;
 617         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 618
 619         if (rxq->rx_tail > rxq->rx_free_trigger) {
 620                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 621                         uint16_t i, j;
 622
 623                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 624                         dev->data->rx_mbuf_alloc_failed +=
 625                                 rxq->rx_free_thresh;
 626
 627                         rxq->rx_nb_avail = 0;
 628                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 629                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 630                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 631
 632                         return 0;
 633                 }
 634         }
 635
 636         if (rxq->rx_tail >= rxq->nb_rx_desc)
 637                 rxq->rx_tail = 0;
 638
 639         if (rxq->rx_nb_avail)
 640                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 641
 642         return 0;
 643 }
 644
 645 static uint16_t
 646 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 647                           struct rte_mbuf **rx_pkts,
 648                           uint16_t nb_pkts)
 649 {
 650         uint16_t nb_rx = 0, n, count;
 651
 652         if (unlikely(nb_pkts == 0))
 653                 return 0;
 654
 655         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 656                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 657
 658         while (nb_pkts) {
 659                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 660                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 661                 nb_rx = (uint16_t)(nb_rx + count);
 662                 nb_pkts = (uint16_t)(nb_pkts - count);
 663                 if (count < n)
 664                         break;
 665         }
 666
 667         return nb_rx;
 668 }
 669 #else
 670 static uint16_t
 671 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 672                           struct rte_mbuf __rte_unused **rx_pkts,
 673                           uint16_t __rte_unused nb_pkts)
 674 {
 675         return 0;
 676 }
 677 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 678
 679 uint16_t
 680 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 681 {
 682         struct i40e_rx_queue *rxq;
 683         volatile union i40e_rx_desc *rx_ring;
 684         volatile union i40e_rx_desc *rxdp;
 685         union i40e_rx_desc rxd;
 686         struct i40e_rx_entry *sw_ring;
 687         struct i40e_rx_entry *rxe;
 688         struct rte_eth_dev *dev;
 689         struct rte_mbuf *rxm;
 690         struct rte_mbuf *nmb;
 691         uint16_t nb_rx;
 692         uint32_t rx_status;
 693         uint64_t qword1;
 694         uint16_t rx_packet_len;
 695         uint16_t rx_id, nb_hold;
 696         uint64_t dma_addr;
 697         uint64_t pkt_flags;
 698
 699         nb_rx = 0;
 700         nb_hold = 0;
 701         rxq = rx_queue;
 702         rx_id = rxq->rx_tail;
 703         rx_ring = rxq->rx_ring;
 704         sw_ring = rxq->sw_ring;
 705
 706         while (nb_rx < nb_pkts) {
 707                 rxdp = &rx_ring[rx_id];
 708                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 709                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 710                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 711
 712                 /* Check the DD bit first */
 713                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 714                         break;
 715
 716                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 717                 if (unlikely(!nmb)) {
 718                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 719                         dev->data->rx_mbuf_alloc_failed++;
 720                         break;
 721                 }
 722
 723                 rxd = *rxdp;
 724                 nb_hold++;
 725                 rxe = &sw_ring[rx_id];
 726                 rx_id++;
 727                 if (unlikely(rx_id == rxq->nb_rx_desc))
 728                         rx_id = 0;
 729
 730                 /* Prefetch next mbuf */
 731                 rte_prefetch0(sw_ring[rx_id].mbuf);
 732
 733                 /**
 734                  * When next RX descriptor is on a cache line boundary,
 735                  * prefetch the next 4 RX descriptors and next 8 pointers
 736                  * to mbufs.
 737                  */
 738                 if ((rx_id & 0x3) == 0) {
 739                         rte_prefetch0(&rx_ring[rx_id]);
 740                         rte_prefetch0(&sw_ring[rx_id]);
 741                 }
 742                 rxm = rxe->mbuf;
 743                 rxe->mbuf = nmb;
 744                 dma_addr =
 745                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 746                 rxdp->read.hdr_addr = 0;
 747                 rxdp->read.pkt_addr = dma_addr;
 748
 749                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 750                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 751
 752                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 753                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 754                 rxm->nb_segs = 1;
 755                 rxm->next = NULL;
 756                 rxm->pkt_len = rx_packet_len;
 757                 rxm->data_len = rx_packet_len;
 758                 rxm->port = rxq->port_id;
 759                 rxm->ol_flags = 0;
 760                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 761                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 762                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 763                 rxm->packet_type =
 764                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 765                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 766                 if (pkt_flags & PKT_RX_RSS_HASH)
 767                         rxm->hash.rss =
 768                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 769                 if (pkt_flags & PKT_RX_FDIR)
 770                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 771
 772 #ifdef RTE_LIBRTE_IEEE1588
 773                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 774 #endif
 775                 rxm->ol_flags |= pkt_flags;
 776
 777                 rx_pkts[nb_rx++] = rxm;
 778         }
 779         rxq->rx_tail = rx_id;
 780
 781         /**
 782          * If the number of free RX descriptors is greater than the RX free
 783          * threshold of the queue, advance the receive tail register of queue.
 784          * Update that register with the value of the last processed RX
 785          * descriptor minus 1.
 786          */
 787         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 788         if (nb_hold > rxq->rx_free_thresh) {
 789                 rx_id = (uint16_t) ((rx_id == 0) ?
 790                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 791                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 792                 nb_hold = 0;
 793         }
 794         rxq->nb_rx_hold = nb_hold;
 795
 796         return nb_rx;
 797 }
 798
 799 uint16_t
 800 i40e_recv_scattered_pkts(void *rx_queue,
 801                          struct rte_mbuf **rx_pkts,
 802                          uint16_t nb_pkts)
 803 {
 804         struct i40e_rx_queue *rxq = rx_queue;
 805         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 806         volatile union i40e_rx_desc *rxdp;
 807         union i40e_rx_desc rxd;
 808         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 809         struct i40e_rx_entry *rxe;
 810         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 811         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 812         struct rte_mbuf *nmb, *rxm;
 813         uint16_t rx_id = rxq->rx_tail;
 814         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 815         struct rte_eth_dev *dev;
 816         uint32_t rx_status;
 817         uint64_t qword1;
 818         uint64_t dma_addr;
 819         uint64_t pkt_flags;
 820
 821         while (nb_rx < nb_pkts) {
 822                 rxdp = &rx_ring[rx_id];
 823                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 824                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 825                                         I40E_RXD_QW1_STATUS_SHIFT;
 826
 827                 /* Check the DD bit */
 828                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 829                         break;
 830
 831                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 832                 if (unlikely(!nmb)) {
 833                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 834                         dev->data->rx_mbuf_alloc_failed++;
 835                         break;
 836                 }
 837
 838                 rxd = *rxdp;
 839                 nb_hold++;
 840                 rxe = &sw_ring[rx_id];
 841                 rx_id++;
 842                 if (rx_id == rxq->nb_rx_desc)
 843                         rx_id = 0;
 844
 845                 /* Prefetch next mbuf */
 846                 rte_prefetch0(sw_ring[rx_id].mbuf);
 847
 848                 /**
 849                  * When next RX descriptor is on a cache line boundary,
 850                  * prefetch the next 4 RX descriptors and next 8 pointers
 851                  * to mbufs.
 852                  */
 853                 if ((rx_id & 0x3) == 0) {
 854                         rte_prefetch0(&rx_ring[rx_id]);
 855                         rte_prefetch0(&sw_ring[rx_id]);
 856                 }
 857
 858                 rxm = rxe->mbuf;
 859                 rxe->mbuf = nmb;
 860                 dma_addr =
 861                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 862
 863                 /* Set data buffer address and data length of the mbuf */
 864                 rxdp->read.hdr_addr = 0;
 865                 rxdp->read.pkt_addr = dma_addr;
 866                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 867                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 868                 rxm->data_len = rx_packet_len;
 869                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 870
 871                 /**
 872                  * If this is the first buffer of the received packet, set the
 873                  * pointer to the first mbuf of the packet and initialize its
 874                  * context. Otherwise, update the total length and the number
 875                  * of segments of the current scattered packet, and update the
 876                  * pointer to the last mbuf of the current packet.
 877                  */
 878                 if (!first_seg) {
 879                         first_seg = rxm;
 880                         first_seg->nb_segs = 1;
 881                         first_seg->pkt_len = rx_packet_len;
 882                 } else {
 883                         first_seg->pkt_len =
 884                                 (uint16_t)(first_seg->pkt_len +
 885                                                 rx_packet_len);
 886                         first_seg->nb_segs++;
 887                         last_seg->next = rxm;
 888                 }
 889
 890                 /**
 891                  * If this is not the last buffer of the received packet,
 892                  * update the pointer to the last mbuf of the current scattered
 893                  * packet and continue to parse the RX ring.
 894                  */
 895                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 896                         last_seg = rxm;
 897                         continue;
 898                 }
 899
 900                 /**
 901                  * This is the last buffer of the received packet. If the CRC
 902                  * is not stripped by the hardware:
 903                  *  - Subtract the CRC length from the total packet length.
 904                  *  - If the last buffer only contains the whole CRC or a part
 905                  *  of it, free the mbuf associated to the last buffer. If part
 906                  *  of the CRC is also contained in the previous mbuf, subtract
 907                  *  the length of that CRC part from the data length of the
 908                  *  previous mbuf.
 909                  */
 910                 rxm->next = NULL;
 911                 if (unlikely(rxq->crc_len > 0)) {
 912                         first_seg->pkt_len -= ETHER_CRC_LEN;
 913                         if (rx_packet_len <= ETHER_CRC_LEN) {
 914                                 rte_pktmbuf_free_seg(rxm);
 915                                 first_seg->nb_segs--;
 916                                 last_seg->data_len =
 917                                         (uint16_t)(last_seg->data_len -
 918                                         (ETHER_CRC_LEN - rx_packet_len));
 919                                 last_seg->next = NULL;
 920                         } else
 921                                 rxm->data_len = (uint16_t)(rx_packet_len -
 922                                                                 ETHER_CRC_LEN);
 923                 }
 924
 925                 first_seg->port = rxq->port_id;
 926                 first_seg->ol_flags = 0;
 927                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 928                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 929                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 930                 first_seg->packet_type =
 931                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 932                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 933                 if (pkt_flags & PKT_RX_RSS_HASH)
 934                         first_seg->hash.rss =
 935                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 936                 if (pkt_flags & PKT_RX_FDIR)
 937                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 938
 939 #ifdef RTE_LIBRTE_IEEE1588
 940                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 941 #endif
 942                 first_seg->ol_flags |= pkt_flags;
 943
 944                 /* Prefetch data of first segment, if configured to do so. */
 945                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 946                         first_seg->data_off));
 947                 rx_pkts[nb_rx++] = first_seg;
 948                 first_seg = NULL;
 949         }
 950
 951         /* Record index of the next RX descriptor to probe. */
 952         rxq->rx_tail = rx_id;
 953         rxq->pkt_first_seg = first_seg;
 954         rxq->pkt_last_seg = last_seg;
 955
 956         /**
 957          * If the number of free RX descriptors is greater than the RX free
 958          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 959          * register. Update the RDT with the value of the last processed RX
 960          * descriptor minus 1, to guarantee that the RDT register is never
 961          * equal to the RDH register, which creates a "full" ring situtation
 962          * from the hardware point of view.
 963          */
 964         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 965         if (nb_hold > rxq->rx_free_thresh) {
 966                 rx_id = (uint16_t)(rx_id == 0 ?
 967                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 968                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 969                 nb_hold = 0;
 970         }
 971         rxq->nb_rx_hold = nb_hold;
 972
 973         return nb_rx;
 974 }
 975
 976 /* Check if the context descriptor is needed for TX offloading */
 977 static inline uint16_t
 978 i40e_calc_context_desc(uint64_t flags)
 979 {
 980         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 981                 PKT_TX_TCP_SEG |
 982                 PKT_TX_QINQ_PKT |
 983                 PKT_TX_TUNNEL_MASK;
 984
 985 #ifdef RTE_LIBRTE_IEEE1588
 986         mask |= PKT_TX_IEEE1588_TMST;
 987 #endif
 988
 989         return (flags & mask) ? 1 : 0;
 990 }
 991
 992 /* set i40e TSO context descriptor */
 993 static inline uint64_t
 994 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 995 {
 996         uint64_t ctx_desc = 0;
 997         uint32_t cd_cmd, hdr_len, cd_tso_len;
 998
 999         if (!tx_offload.l4_len) {
1000                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1001                 return ctx_desc;
1002         }
1003
1004         /**
1005          * in case of non tunneling packet, the outer_l2_len and
1006          * outer_l3_len must be 0.
1007          */
1008         hdr_len = tx_offload.outer_l2_len +
1009                 tx_offload.outer_l3_len +
1010                 tx_offload.l2_len +
1011                 tx_offload.l3_len +
1012                 tx_offload.l4_len;
1013
1014         cd_cmd = I40E_TX_CTX_DESC_TSO;
1015         cd_tso_len = mbuf->pkt_len - hdr_len;
1016         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1017                 ((uint64_t)cd_tso_len <<
1018                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1019                 ((uint64_t)mbuf->tso_segsz <<
1020                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1021
1022         return ctx_desc;
1023 }
1024
1025 uint16_t
1026 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1027 {
1028         struct i40e_tx_queue *txq;
1029         struct i40e_tx_entry *sw_ring;
1030         struct i40e_tx_entry *txe, *txn;
1031         volatile struct i40e_tx_desc *txd;
1032         volatile struct i40e_tx_desc *txr;
1033         struct rte_mbuf *tx_pkt;
1034         struct rte_mbuf *m_seg;
1035         uint32_t cd_tunneling_params;
1036         uint16_t tx_id;
1037         uint16_t nb_tx;
1038         uint32_t td_cmd;
1039         uint32_t td_offset;
1040         uint32_t tx_flags;
1041         uint32_t td_tag;
1042         uint64_t ol_flags;
1043         uint16_t nb_used;
1044         uint16_t nb_ctx;
1045         uint16_t tx_last;
1046         uint16_t slen;
1047         uint64_t buf_dma_addr;
1048         union i40e_tx_offload tx_offload = {0};
1049
1050         txq = tx_queue;
1051         sw_ring = txq->sw_ring;
1052         txr = txq->tx_ring;
1053         tx_id = txq->tx_tail;
1054         txe = &sw_ring[tx_id];
1055
1056         /* Check if the descriptor ring needs to be cleaned. */
1057         if (txq->nb_tx_free < txq->tx_free_thresh)
1058                 i40e_xmit_cleanup(txq);
1059
1060         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1061                 td_cmd = 0;
1062                 td_tag = 0;
1063                 td_offset = 0;
1064                 tx_flags = 0;
1065
1066                 tx_pkt = *tx_pkts++;
1067                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1068
1069                 ol_flags = tx_pkt->ol_flags;
1070                 tx_offload.l2_len = tx_pkt->l2_len;
1071                 tx_offload.l3_len = tx_pkt->l3_len;
1072                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1073                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1074                 tx_offload.l4_len = tx_pkt->l4_len;
1075                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1076
1077                 /* Calculate the number of context descriptors needed. */
1078                 nb_ctx = i40e_calc_context_desc(ol_flags);
1079
1080                 /**
1081                  * The number of descriptors that must be allocated for
1082                  * a packet equals to the number of the segments of that
1083                  * packet plus 1 context descriptor if needed.
1084                  */
1085                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1086                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1087
1088                 /* Circular ring */
1089                 if (tx_last >= txq->nb_tx_desc)
1090                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1091
1092                 if (nb_used > txq->nb_tx_free) {
1093                         if (i40e_xmit_cleanup(txq) != 0) {
1094                                 if (nb_tx == 0)
1095                                         return 0;
1096                                 goto end_of_tx;
1097                         }
1098                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1099                                 while (nb_used > txq->nb_tx_free) {
1100                                         if (i40e_xmit_cleanup(txq) != 0) {
1101                                                 if (nb_tx == 0)
1102                                                         return 0;
1103                                                 goto end_of_tx;
1104                                         }
1105                                 }
1106                         }
1107                 }
1108
1109                 /* Descriptor based VLAN insertion */
1110                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1111                         tx_flags |= tx_pkt->vlan_tci <<
1112                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1113                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1114                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1115                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1116                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1117                 }
1118
1119                 /* Always enable CRC offload insertion */
1120                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1121
1122                 /* Fill in tunneling parameters if necessary */
1123                 cd_tunneling_params = 0;
1124                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1125                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1126                                                     &cd_tunneling_params);
1127                 /* Enable checksum offloading */
1128                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1129                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1130                                                  &td_offset, tx_offload);
1131
1132                 if (nb_ctx) {
1133                         /* Setup TX context descriptor if required */
1134                         volatile struct i40e_tx_context_desc *ctx_txd =
1135                                 (volatile struct i40e_tx_context_desc *)\
1136                                                         &txr[tx_id];
1137                         uint16_t cd_l2tag2 = 0;
1138                         uint64_t cd_type_cmd_tso_mss =
1139                                 I40E_TX_DESC_DTYPE_CONTEXT;
1140
1141                         txn = &sw_ring[txe->next_id];
1142                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1143                         if (txe->mbuf != NULL) {
1144                                 rte_pktmbuf_free_seg(txe->mbuf);
1145                                 txe->mbuf = NULL;
1146                         }
1147
1148                         /* TSO enabled means no timestamp */
1149                         if (ol_flags & PKT_TX_TCP_SEG)
1150                                 cd_type_cmd_tso_mss |=
1151                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1152                         else {
1153 #ifdef RTE_LIBRTE_IEEE1588
1154                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1155                                         cd_type_cmd_tso_mss |=
1156                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1157                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1158 #endif
1159                         }
1160
1161                         ctx_txd->tunneling_params =
1162                                 rte_cpu_to_le_32(cd_tunneling_params);
1163                         if (ol_flags & PKT_TX_QINQ_PKT) {
1164                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1165                                 cd_type_cmd_tso_mss |=
1166                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1167                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1168                         }
1169                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1170                         ctx_txd->type_cmd_tso_mss =
1171                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1172
1173                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1174                                 "tunneling_params: %#x;\n"
1175                                 "l2tag2: %#hx;\n"
1176                                 "rsvd: %#hx;\n"
1177                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1178                                 tx_pkt, tx_id,
1179                                 ctx_txd->tunneling_params,
1180                                 ctx_txd->l2tag2,
1181                                 ctx_txd->rsvd,
1182                                 ctx_txd->type_cmd_tso_mss);
1183
1184                         txe->last_id = tx_last;
1185                         tx_id = txe->next_id;
1186                         txe = txn;
1187                 }
1188
1189                 m_seg = tx_pkt;
1190                 do {
1191                         txd = &txr[tx_id];
1192                         txn = &sw_ring[txe->next_id];
1193
1194                         if (txe->mbuf)
1195                                 rte_pktmbuf_free_seg(txe->mbuf);
1196                         txe->mbuf = m_seg;
1197
1198                         /* Setup TX Descriptor */
1199                         slen = m_seg->data_len;
1200                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1201
1202                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1203                                 "buf_dma_addr: %#"PRIx64";\n"
1204                                 "td_cmd: %#x;\n"
1205                                 "td_offset: %#x;\n"
1206                                 "td_len: %u;\n"
1207                                 "td_tag: %#x;\n",
1208                                 tx_pkt, tx_id, buf_dma_addr,
1209                                 td_cmd, td_offset, slen, td_tag);
1210
1211                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1212                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1213                                                 td_offset, slen, td_tag);
1214                         txe->last_id = tx_last;
1215                         tx_id = txe->next_id;
1216                         txe = txn;
1217                         m_seg = m_seg->next;
1218                 } while (m_seg != NULL);
1219
1220                 /* The last packet data descriptor needs End Of Packet (EOP) */
1221                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1222                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1223                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1224
1225                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1226                         PMD_TX_FREE_LOG(DEBUG,
1227                                         "Setting RS bit on TXD id="
1228                                         "%4u (port=%d queue=%d)",
1229                                         tx_last, txq->port_id, txq->queue_id);
1230
1231                         td_cmd |= I40E_TX_DESC_CMD_RS;
1232
1233                         /* Update txq RS bit counters */
1234                         txq->nb_tx_used = 0;
1235                 }
1236
1237                 txd->cmd_type_offset_bsz |=
1238                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1239                                         I40E_TXD_QW1_CMD_SHIFT);
1240         }
1241
1242 end_of_tx:
1243         rte_wmb();
1244
1245         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1246                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1247                    (unsigned) tx_id, (unsigned) nb_tx);
1248
1249         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1250         txq->tx_tail = tx_id;
1251
1252         return nb_tx;
1253 }
1254
1255 static inline int __attribute__((always_inline))
1256 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1257 {
1258         struct i40e_tx_entry *txep;
1259         uint16_t i;
1260
1261         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1262                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1263                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1264                 return 0;
1265
1266         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1267
1268         for (i = 0; i < txq->tx_rs_thresh; i++)
1269                 rte_prefetch0((txep + i)->mbuf);
1270
1271         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1272                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1273                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1274                         txep->mbuf = NULL;
1275                 }
1276         } else {
1277                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1278                         rte_pktmbuf_free_seg(txep->mbuf);
1279                         txep->mbuf = NULL;
1280                 }
1281         }
1282
1283         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1284         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1285         if (txq->tx_next_dd >= txq->nb_tx_desc)
1286                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1287
1288         return txq->tx_rs_thresh;
1289 }
1290
1291 /* Populate 4 descriptors with data from 4 mbufs */
1292 static inline void
1293 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1294 {
1295         uint64_t dma_addr;
1296         uint32_t i;
1297
1298         for (i = 0; i < 4; i++, txdp++, pkts++) {
1299                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1300                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1301                 txdp->cmd_type_offset_bsz =
1302                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1303                                         (*pkts)->data_len, 0);
1304         }
1305 }
1306
1307 /* Populate 1 descriptor with data from 1 mbuf */
1308 static inline void
1309 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1310 {
1311         uint64_t dma_addr;
1312
1313         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1314         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1315         txdp->cmd_type_offset_bsz =
1316                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1317                                 (*pkts)->data_len, 0);
1318 }
1319
1320 /* Fill hardware descriptor ring with mbuf data */
1321 static inline void
1322 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1323                      struct rte_mbuf **pkts,
1324                      uint16_t nb_pkts)
1325 {
1326         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1327         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1328         const int N_PER_LOOP = 4;
1329         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1330         int mainpart, leftover;
1331         int i, j;
1332
1333         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1334         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1335         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1336                 for (j = 0; j < N_PER_LOOP; ++j) {
1337                         (txep + i + j)->mbuf = *(pkts + i + j);
1338                 }
1339                 tx4(txdp + i, pkts + i);
1340         }
1341         if (unlikely(leftover > 0)) {
1342                 for (i = 0; i < leftover; ++i) {
1343                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1344                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1345                 }
1346         }
1347 }
1348
1349 static inline uint16_t
1350 tx_xmit_pkts(struct i40e_tx_queue *txq,
1351              struct rte_mbuf **tx_pkts,
1352              uint16_t nb_pkts)
1353 {
1354         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1355         uint16_t n = 0;
1356
1357         /**
1358          * Begin scanning the H/W ring for done descriptors when the number
1359          * of available descriptors drops below tx_free_thresh. For each done
1360          * descriptor, free the associated buffer.
1361          */
1362         if (txq->nb_tx_free < txq->tx_free_thresh)
1363                 i40e_tx_free_bufs(txq);
1364
1365         /* Use available descriptor only */
1366         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1367         if (unlikely(!nb_pkts))
1368                 return 0;
1369
1370         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1371         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1372                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1373                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1374                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1375                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1376                                                 I40E_TXD_QW1_CMD_SHIFT);
1377                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1378                 txq->tx_tail = 0;
1379         }
1380
1381         /* Fill hardware descriptor ring with mbuf data */
1382         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1383         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1384
1385         /* Determin if RS bit needs to be set */
1386         if (txq->tx_tail > txq->tx_next_rs) {
1387                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1388                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1389                                                 I40E_TXD_QW1_CMD_SHIFT);
1390                 txq->tx_next_rs =
1391                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1392                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1393                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1394         }
1395
1396         if (txq->tx_tail >= txq->nb_tx_desc)
1397                 txq->tx_tail = 0;
1398
1399         /* Update the tx tail register */
1400         rte_wmb();
1401         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1402
1403         return nb_pkts;
1404 }
1405
1406 static uint16_t
1407 i40e_xmit_pkts_simple(void *tx_queue,
1408                       struct rte_mbuf **tx_pkts,
1409                       uint16_t nb_pkts)
1410 {
1411         uint16_t nb_tx = 0;
1412
1413         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1414                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1415                                                 tx_pkts, nb_pkts);
1416
1417         while (nb_pkts) {
1418                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1419                                                 I40E_TX_MAX_BURST);
1420
1421                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1422                                                 &tx_pkts[nb_tx], num);
1423                 nb_tx = (uint16_t)(nb_tx + ret);
1424                 nb_pkts = (uint16_t)(nb_pkts - ret);
1425                 if (ret < num)
1426                         break;
1427         }
1428
1429         return nb_tx;
1430 }
1431
1432 /*
1433  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1434  * application used, which assume having sequential ones. But from driver's
1435  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1436  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1437  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1438  * use queue_idx from 0 to 95 to access queues, while real queue would be
1439  * different. This function will do a queue mapping to find VSI the queue
1440  * belongs to.
1441  */
1442 static struct i40e_vsi*
1443 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1444 {
1445         /* the queue in MAIN VSI range */
1446         if (queue_idx < pf->main_vsi->nb_qps)
1447                 return pf->main_vsi;
1448
1449         queue_idx -= pf->main_vsi->nb_qps;
1450
1451         /* queue_idx is greater than VMDQ VSIs range */
1452         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1453                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1454                 return NULL;
1455         }
1456
1457         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1458 }
1459
1460 static uint16_t
1461 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1462 {
1463         /* the queue in MAIN VSI range */
1464         if (queue_idx < pf->main_vsi->nb_qps)
1465                 return queue_idx;
1466
1467         /* It's VMDQ queues */
1468         queue_idx -= pf->main_vsi->nb_qps;
1469
1470         if (pf->nb_cfg_vmdq_vsi)
1471                 return queue_idx % pf->vmdq_nb_qps;
1472         else {
1473                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1474                 return (uint16_t)(-1);
1475         }
1476 }
1477
1478 int
1479 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1480 {
1481         struct i40e_rx_queue *rxq;
1482         int err = -1;
1483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484
1485         PMD_INIT_FUNC_TRACE();
1486
1487         if (rx_queue_id < dev->data->nb_rx_queues) {
1488                 rxq = dev->data->rx_queues[rx_queue_id];
1489
1490                 err = i40e_alloc_rx_queue_mbufs(rxq);
1491                 if (err) {
1492                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1493                         return err;
1494                 }
1495
1496                 rte_wmb();
1497
1498                 /* Init the RX tail regieter. */
1499                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1500
1501                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1502
1503                 if (err) {
1504                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1505                                     rx_queue_id);
1506
1507                         i40e_rx_queue_release_mbufs(rxq);
1508                         i40e_reset_rx_queue(rxq);
1509                 } else
1510                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1511         }
1512
1513         return err;
1514 }
1515
1516 int
1517 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1518 {
1519         struct i40e_rx_queue *rxq;
1520         int err;
1521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1522
1523         if (rx_queue_id < dev->data->nb_rx_queues) {
1524                 rxq = dev->data->rx_queues[rx_queue_id];
1525
1526                 /*
1527                 * rx_queue_id is queue id aplication refers to, while
1528                 * rxq->reg_idx is the real queue index.
1529                 */
1530                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1531
1532                 if (err) {
1533                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1534                                     rx_queue_id);
1535                         return err;
1536                 }
1537                 i40e_rx_queue_release_mbufs(rxq);
1538                 i40e_reset_rx_queue(rxq);
1539                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1540         }
1541
1542         return 0;
1543 }
1544
1545 int
1546 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1547 {
1548         int err = -1;
1549         struct i40e_tx_queue *txq;
1550         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1551
1552         PMD_INIT_FUNC_TRACE();
1553
1554         if (tx_queue_id < dev->data->nb_tx_queues) {
1555                 txq = dev->data->tx_queues[tx_queue_id];
1556
1557                 /*
1558                 * tx_queue_id is queue id aplication refers to, while
1559                 * rxq->reg_idx is the real queue index.
1560                 */
1561                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1562                 if (err)
1563                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1564                                     tx_queue_id);
1565                 else
1566                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1567         }
1568
1569         return err;
1570 }
1571
1572 int
1573 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1574 {
1575         struct i40e_tx_queue *txq;
1576         int err;
1577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578
1579         if (tx_queue_id < dev->data->nb_tx_queues) {
1580                 txq = dev->data->tx_queues[tx_queue_id];
1581
1582                 /*
1583                 * tx_queue_id is queue id aplication refers to, while
1584                 * txq->reg_idx is the real queue index.
1585                 */
1586                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1587
1588                 if (err) {
1589                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1590                                     tx_queue_id);
1591                         return err;
1592                 }
1593
1594                 i40e_tx_queue_release_mbufs(txq);
1595                 i40e_reset_tx_queue(txq);
1596                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1597         }
1598
1599         return 0;
1600 }
1601
1602 const uint32_t *
1603 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1604 {
1605         static const uint32_t ptypes[] = {
1606                 /* refers to i40e_rxd_pkt_type_mapping() */
1607                 RTE_PTYPE_L2_ETHER,
1608                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1609                 RTE_PTYPE_L2_ETHER_LLDP,
1610                 RTE_PTYPE_L2_ETHER_ARP,
1611                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1612                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1613                 RTE_PTYPE_L4_FRAG,
1614                 RTE_PTYPE_L4_ICMP,
1615                 RTE_PTYPE_L4_NONFRAG,
1616                 RTE_PTYPE_L4_SCTP,
1617                 RTE_PTYPE_L4_TCP,
1618                 RTE_PTYPE_L4_UDP,
1619                 RTE_PTYPE_TUNNEL_GRENAT,
1620                 RTE_PTYPE_TUNNEL_IP,
1621                 RTE_PTYPE_INNER_L2_ETHER,
1622                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1623                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1624                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1625                 RTE_PTYPE_INNER_L4_FRAG,
1626                 RTE_PTYPE_INNER_L4_ICMP,
1627                 RTE_PTYPE_INNER_L4_NONFRAG,
1628                 RTE_PTYPE_INNER_L4_SCTP,
1629                 RTE_PTYPE_INNER_L4_TCP,
1630                 RTE_PTYPE_INNER_L4_UDP,
1631                 RTE_PTYPE_UNKNOWN
1632         };
1633
1634         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1635 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1636             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1637 #endif
1638             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1639             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1640             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1641                 return ptypes;
1642         return NULL;
1643 }
1644
1645 int
1646 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1647                         uint16_t queue_idx,
1648                         uint16_t nb_desc,
1649                         unsigned int socket_id,
1650                         const struct rte_eth_rxconf *rx_conf,
1651                         struct rte_mempool *mp)
1652 {
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct i40e_adapter *ad =
1655                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1656         struct i40e_vsi *vsi;
1657         struct i40e_pf *pf = NULL;
1658         struct i40e_vf *vf = NULL;
1659         struct i40e_rx_queue *rxq;
1660         const struct rte_memzone *rz;
1661         uint32_t ring_size;
1662         uint16_t len, i;
1663         uint16_t reg_idx, base, bsf, tc_mapping;
1664         int q_offset, use_def_burst_func = 1;
1665
1666         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1667                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1668                 vsi = &vf->vsi;
1669                 if (!vsi)
1670                         return -EINVAL;
1671                 reg_idx = queue_idx;
1672         } else {
1673                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1674                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1675                 if (!vsi)
1676                         return -EINVAL;
1677                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1678                 if (q_offset < 0)
1679                         return -EINVAL;
1680                 reg_idx = vsi->base_queue + q_offset;
1681         }
1682
1683         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1684             (nb_desc > I40E_MAX_RING_DESC) ||
1685             (nb_desc < I40E_MIN_RING_DESC)) {
1686                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1687                             "invalid", nb_desc);
1688                 return -EINVAL;
1689         }
1690
1691         /* Free memory if needed */
1692         if (dev->data->rx_queues[queue_idx]) {
1693                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1694                 dev->data->rx_queues[queue_idx] = NULL;
1695         }
1696
1697         /* Allocate the rx queue data structure */
1698         rxq = rte_zmalloc_socket("i40e rx queue",
1699                                  sizeof(struct i40e_rx_queue),
1700                                  RTE_CACHE_LINE_SIZE,
1701                                  socket_id);
1702         if (!rxq) {
1703                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1704                             "rx queue data structure");
1705                 return -ENOMEM;
1706         }
1707         rxq->mp = mp;
1708         rxq->nb_rx_desc = nb_desc;
1709         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1710         rxq->queue_id = queue_idx;
1711         rxq->reg_idx = reg_idx;
1712         rxq->port_id = dev->data->port_id;
1713         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1714                                                         0 : ETHER_CRC_LEN);
1715         rxq->drop_en = rx_conf->rx_drop_en;
1716         rxq->vsi = vsi;
1717         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1718
1719         /* Allocate the maximun number of RX ring hardware descriptor. */
1720         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1721         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1722         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1723                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1724         if (!rz) {
1725                 i40e_dev_rx_queue_release(rxq);
1726                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1727                 return -ENOMEM;
1728         }
1729
1730         /* Zero all the descriptors in the ring. */
1731         memset(rz->addr, 0, ring_size);
1732
1733         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1734         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1735
1736         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1737
1738         /* Allocate the software ring. */
1739         rxq->sw_ring =
1740                 rte_zmalloc_socket("i40e rx sw ring",
1741                                    sizeof(struct i40e_rx_entry) * len,
1742                                    RTE_CACHE_LINE_SIZE,
1743                                    socket_id);
1744         if (!rxq->sw_ring) {
1745                 i40e_dev_rx_queue_release(rxq);
1746                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1747                 return -ENOMEM;
1748         }
1749
1750         i40e_reset_rx_queue(rxq);
1751         rxq->q_set = TRUE;
1752         dev->data->rx_queues[queue_idx] = rxq;
1753
1754         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1755
1756         if (!use_def_burst_func) {
1757 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1758                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1759                              "satisfied. Rx Burst Bulk Alloc function will be "
1760                              "used on port=%d, queue=%d.",
1761                              rxq->port_id, rxq->queue_id);
1762 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1763         } else {
1764                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1765                              "not satisfied, Scattered Rx is requested, "
1766                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1767                              "not enabled on port=%d, queue=%d.",
1768                              rxq->port_id, rxq->queue_id);
1769                 ad->rx_bulk_alloc_allowed = false;
1770         }
1771
1772         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1773                 if (!(vsi->enabled_tc & (1 << i)))
1774                         continue;
1775                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1776                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1777                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1778                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1779                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1780
1781                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1782                         rxq->dcb_tc = i;
1783         }
1784
1785         return 0;
1786 }
1787
1788 void
1789 i40e_dev_rx_queue_release(void *rxq)
1790 {
1791         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1792
1793         if (!q) {
1794                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1795                 return;
1796         }
1797
1798         i40e_rx_queue_release_mbufs(q);
1799         rte_free(q->sw_ring);
1800         rte_free(q);
1801 }
1802
1803 uint32_t
1804 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1805 {
1806 #define I40E_RXQ_SCAN_INTERVAL 4
1807         volatile union i40e_rx_desc *rxdp;
1808         struct i40e_rx_queue *rxq;
1809         uint16_t desc = 0;
1810
1811         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1812                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1813                 return 0;
1814         }
1815
1816         rxq = dev->data->rx_queues[rx_queue_id];
1817         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1818         while ((desc < rxq->nb_rx_desc) &&
1819                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1820                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1821                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1822                 /**
1823                  * Check the DD bit of a rx descriptor of each 4 in a group,
1824                  * to avoid checking too frequently and downgrading performance
1825                  * too much.
1826                  */
1827                 desc += I40E_RXQ_SCAN_INTERVAL;
1828                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1829                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1830                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1831                                         desc - rxq->nb_rx_desc]);
1832         }
1833
1834         return desc;
1835 }
1836
1837 int
1838 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1839 {
1840         volatile union i40e_rx_desc *rxdp;
1841         struct i40e_rx_queue *rxq = rx_queue;
1842         uint16_t desc;
1843         int ret;
1844
1845         if (unlikely(offset >= rxq->nb_rx_desc)) {
1846                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1847                 return 0;
1848         }
1849
1850         desc = rxq->rx_tail + offset;
1851         if (desc >= rxq->nb_rx_desc)
1852                 desc -= rxq->nb_rx_desc;
1853
1854         rxdp = &(rxq->rx_ring[desc]);
1855
1856         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1857                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1858                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1859
1860         return ret;
1861 }
1862
1863 int
1864 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1865                         uint16_t queue_idx,
1866                         uint16_t nb_desc,
1867                         unsigned int socket_id,
1868                         const struct rte_eth_txconf *tx_conf)
1869 {
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         struct i40e_vsi *vsi;
1872         struct i40e_pf *pf = NULL;
1873         struct i40e_vf *vf = NULL;
1874         struct i40e_tx_queue *txq;
1875         const struct rte_memzone *tz;
1876         uint32_t ring_size;
1877         uint16_t tx_rs_thresh, tx_free_thresh;
1878         uint16_t reg_idx, i, base, bsf, tc_mapping;
1879         int q_offset;
1880
1881         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1882                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1883                 vsi = &vf->vsi;
1884                 if (!vsi)
1885                         return -EINVAL;
1886                 reg_idx = queue_idx;
1887         } else {
1888                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1890                 if (!vsi)
1891                         return -EINVAL;
1892                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1893                 if (q_offset < 0)
1894                         return -EINVAL;
1895                 reg_idx = vsi->base_queue + q_offset;
1896         }
1897
1898         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1899             (nb_desc > I40E_MAX_RING_DESC) ||
1900             (nb_desc < I40E_MIN_RING_DESC)) {
1901                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1902                             "invalid", nb_desc);
1903                 return -EINVAL;
1904         }
1905
1906         /**
1907          * The following two parameters control the setting of the RS bit on
1908          * transmit descriptors. TX descriptors will have their RS bit set
1909          * after txq->tx_rs_thresh descriptors have been used. The TX
1910          * descriptor ring will be cleaned after txq->tx_free_thresh
1911          * descriptors are used or if the number of descriptors required to
1912          * transmit a packet is greater than the number of free TX descriptors.
1913          *
1914          * The following constraints must be satisfied:
1915          *  - tx_rs_thresh must be greater than 0.
1916          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1917          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1918          *  - tx_rs_thresh must be a divisor of the ring size.
1919          *  - tx_free_thresh must be greater than 0.
1920          *  - tx_free_thresh must be less than the size of the ring minus 3.
1921          *
1922          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1923          * race condition, hence the maximum threshold constraints. When set
1924          * to zero use default values.
1925          */
1926         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1927                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1928         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1929                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1930         if (tx_rs_thresh >= (nb_desc - 2)) {
1931                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1932                              "number of TX descriptors minus 2. "
1933                              "(tx_rs_thresh=%u port=%d queue=%d)",
1934                              (unsigned int)tx_rs_thresh,
1935                              (int)dev->data->port_id,
1936                              (int)queue_idx);
1937                 return I40E_ERR_PARAM;
1938         }
1939         if (tx_free_thresh >= (nb_desc - 3)) {
1940                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1941                              "number of TX descriptors minus 3. "
1942                              "(tx_free_thresh=%u port=%d queue=%d)",
1943                              (unsigned int)tx_free_thresh,
1944                              (int)dev->data->port_id,
1945                              (int)queue_idx);
1946                 return I40E_ERR_PARAM;
1947         }
1948         if (tx_rs_thresh > tx_free_thresh) {
1949                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1950                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1951                              " tx_rs_thresh=%u port=%d queue=%d)",
1952                              (unsigned int)tx_free_thresh,
1953                              (unsigned int)tx_rs_thresh,
1954                              (int)dev->data->port_id,
1955                              (int)queue_idx);
1956                 return I40E_ERR_PARAM;
1957         }
1958         if ((nb_desc % tx_rs_thresh) != 0) {
1959                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1960                              "number of TX descriptors. (tx_rs_thresh=%u"
1961                              " port=%d queue=%d)",
1962                              (unsigned int)tx_rs_thresh,
1963                              (int)dev->data->port_id,
1964                              (int)queue_idx);
1965                 return I40E_ERR_PARAM;
1966         }
1967         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1968                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1969                              "tx_rs_thresh is greater than 1. "
1970                              "(tx_rs_thresh=%u port=%d queue=%d)",
1971                              (unsigned int)tx_rs_thresh,
1972                              (int)dev->data->port_id,
1973                              (int)queue_idx);
1974                 return I40E_ERR_PARAM;
1975         }
1976
1977         /* Free memory if needed. */
1978         if (dev->data->tx_queues[queue_idx]) {
1979                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1980                 dev->data->tx_queues[queue_idx] = NULL;
1981         }
1982
1983         /* Allocate the TX queue data structure. */
1984         txq = rte_zmalloc_socket("i40e tx queue",
1985                                   sizeof(struct i40e_tx_queue),
1986                                   RTE_CACHE_LINE_SIZE,
1987                                   socket_id);
1988         if (!txq) {
1989                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1990                             "tx queue structure");
1991                 return -ENOMEM;
1992         }
1993
1994         /* Allocate TX hardware ring descriptors. */
1995         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1996         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1997         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1998                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1999         if (!tz) {
2000                 i40e_dev_tx_queue_release(txq);
2001                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2002                 return -ENOMEM;
2003         }
2004
2005         txq->nb_tx_desc = nb_desc;
2006         txq->tx_rs_thresh = tx_rs_thresh;
2007         txq->tx_free_thresh = tx_free_thresh;
2008         txq->pthresh = tx_conf->tx_thresh.pthresh;
2009         txq->hthresh = tx_conf->tx_thresh.hthresh;
2010         txq->wthresh = tx_conf->tx_thresh.wthresh;
2011         txq->queue_id = queue_idx;
2012         txq->reg_idx = reg_idx;
2013         txq->port_id = dev->data->port_id;
2014         txq->txq_flags = tx_conf->txq_flags;
2015         txq->vsi = vsi;
2016         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2017
2018         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2019         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2020
2021         /* Allocate software ring */
2022         txq->sw_ring =
2023                 rte_zmalloc_socket("i40e tx sw ring",
2024                                    sizeof(struct i40e_tx_entry) * nb_desc,
2025                                    RTE_CACHE_LINE_SIZE,
2026                                    socket_id);
2027         if (!txq->sw_ring) {
2028                 i40e_dev_tx_queue_release(txq);
2029                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2030                 return -ENOMEM;
2031         }
2032
2033         i40e_reset_tx_queue(txq);
2034         txq->q_set = TRUE;
2035         dev->data->tx_queues[queue_idx] = txq;
2036
2037         /* Use a simple TX queue without offloads or multi segs if possible */
2038         i40e_set_tx_function_flag(dev, txq);
2039
2040         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2041                 if (!(vsi->enabled_tc & (1 << i)))
2042                         continue;
2043                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2044                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2045                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2046                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2047                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2048
2049                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2050                         txq->dcb_tc = i;
2051         }
2052
2053         return 0;
2054 }
2055
2056 void
2057 i40e_dev_tx_queue_release(void *txq)
2058 {
2059         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2060
2061         if (!q) {
2062                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2063                 return;
2064         }
2065
2066         i40e_tx_queue_release_mbufs(q);
2067         rte_free(q->sw_ring);
2068         rte_free(q);
2069 }
2070
2071 const struct rte_memzone *
2072 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2073 {
2074         const struct rte_memzone *mz;
2075
2076         mz = rte_memzone_lookup(name);
2077         if (mz)
2078                 return mz;
2079
2080         if (rte_xen_dom0_supported())
2081                 mz = rte_memzone_reserve_bounded(name, len,
2082                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2083         else
2084                 mz = rte_memzone_reserve_aligned(name, len,
2085                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2086         return mz;
2087 }
2088
2089 void
2090 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2091 {
2092         uint16_t i;
2093
2094         /* SSE Vector driver has a different way of releasing mbufs. */
2095         if (rxq->rx_using_sse) {
2096                 i40e_rx_queue_release_mbufs_vec(rxq);
2097                 return;
2098         }
2099
2100         if (!rxq->sw_ring) {
2101                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2102                 return;
2103         }
2104
2105         for (i = 0; i < rxq->nb_rx_desc; i++) {
2106                 if (rxq->sw_ring[i].mbuf) {
2107                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2108                         rxq->sw_ring[i].mbuf = NULL;
2109                 }
2110         }
2111 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2112         if (rxq->rx_nb_avail == 0)
2113                 return;
2114         for (i = 0; i < rxq->rx_nb_avail; i++) {
2115                 struct rte_mbuf *mbuf;
2116
2117                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2118                 rte_pktmbuf_free_seg(mbuf);
2119         }
2120         rxq->rx_nb_avail = 0;
2121 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2122 }
2123
2124 void
2125 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2126 {
2127         unsigned i;
2128         uint16_t len;
2129
2130         if (!rxq) {
2131                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2132                 return;
2133         }
2134
2135 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2136         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2137                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2138         else
2139 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2140                 len = rxq->nb_rx_desc;
2141
2142         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2143                 ((volatile char *)rxq->rx_ring)[i] = 0;
2144
2145         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2146         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2147                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2148
2149 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2150         rxq->rx_nb_avail = 0;
2151         rxq->rx_next_avail = 0;
2152         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2153 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2154         rxq->rx_tail = 0;
2155         rxq->nb_rx_hold = 0;
2156         rxq->pkt_first_seg = NULL;
2157         rxq->pkt_last_seg = NULL;
2158
2159         rxq->rxrearm_start = 0;
2160         rxq->rxrearm_nb = 0;
2161 }
2162
2163 void
2164 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2165 {
2166         struct rte_eth_dev *dev;
2167         uint16_t i;
2168
2169         dev = &rte_eth_devices[txq->port_id];
2170
2171         if (!txq || !txq->sw_ring) {
2172                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2173                 return;
2174         }
2175
2176         /**
2177          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2178          *  so need to free remains more carefully.
2179          */
2180         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2181                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2182                 if (txq->tx_tail < i) {
2183                         for (; i < txq->nb_tx_desc; i++) {
2184                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2185                                 txq->sw_ring[i].mbuf = NULL;
2186                         }
2187                         i = 0;
2188                 }
2189                 for (; i < txq->tx_tail; i++) {
2190                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2191                         txq->sw_ring[i].mbuf = NULL;
2192                 }
2193         } else {
2194                 for (i = 0; i < txq->nb_tx_desc; i++) {
2195                         if (txq->sw_ring[i].mbuf) {
2196                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2197                                 txq->sw_ring[i].mbuf = NULL;
2198                         }
2199                 }
2200         }
2201 }
2202
2203 void
2204 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2205 {
2206         struct i40e_tx_entry *txe;
2207         uint16_t i, prev, size;
2208
2209         if (!txq) {
2210                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2211                 return;
2212         }
2213
2214         txe = txq->sw_ring;
2215         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2216         for (i = 0; i < size; i++)
2217                 ((volatile char *)txq->tx_ring)[i] = 0;
2218
2219         prev = (uint16_t)(txq->nb_tx_desc - 1);
2220         for (i = 0; i < txq->nb_tx_desc; i++) {
2221                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2222
2223                 txd->cmd_type_offset_bsz =
2224                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2225                 txe[i].mbuf =  NULL;
2226                 txe[i].last_id = i;
2227                 txe[prev].next_id = i;
2228                 prev = i;
2229         }
2230
2231         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2232         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2233
2234         txq->tx_tail = 0;
2235         txq->nb_tx_used = 0;
2236
2237         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2238         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2239 }
2240
2241 /* Init the TX queue in hardware */
2242 int
2243 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2244 {
2245         enum i40e_status_code err = I40E_SUCCESS;
2246         struct i40e_vsi *vsi = txq->vsi;
2247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2248         uint16_t pf_q = txq->reg_idx;
2249         struct i40e_hmc_obj_txq tx_ctx;
2250         uint32_t qtx_ctl;
2251
2252         /* clear the context structure first */
2253         memset(&tx_ctx, 0, sizeof(tx_ctx));
2254         tx_ctx.new_context = 1;
2255         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2256         tx_ctx.qlen = txq->nb_tx_desc;
2257
2258 #ifdef RTE_LIBRTE_IEEE1588
2259         tx_ctx.timesync_ena = 1;
2260 #endif
2261         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2262         if (vsi->type == I40E_VSI_FDIR)
2263                 tx_ctx.fd_ena = TRUE;
2264
2265         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2266         if (err != I40E_SUCCESS) {
2267                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2268                 return err;
2269         }
2270
2271         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2272         if (err != I40E_SUCCESS) {
2273                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2274                 return err;
2275         }
2276
2277         /* Now associate this queue with this PCI function */
2278         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2279         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2280                                         I40E_QTX_CTL_PF_INDX_MASK);
2281         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2282         I40E_WRITE_FLUSH(hw);
2283
2284         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2285
2286         return err;
2287 }
2288
2289 int
2290 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2291 {
2292         struct i40e_rx_entry *rxe = rxq->sw_ring;
2293         uint64_t dma_addr;
2294         uint16_t i;
2295
2296         for (i = 0; i < rxq->nb_rx_desc; i++) {
2297                 volatile union i40e_rx_desc *rxd;
2298                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2299
2300                 if (unlikely(!mbuf)) {
2301                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2302                         return -ENOMEM;
2303                 }
2304
2305                 rte_mbuf_refcnt_set(mbuf, 1);
2306                 mbuf->next = NULL;
2307                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2308                 mbuf->nb_segs = 1;
2309                 mbuf->port = rxq->port_id;
2310
2311                 dma_addr =
2312                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2313
2314                 rxd = &rxq->rx_ring[i];
2315                 rxd->read.pkt_addr = dma_addr;
2316                 rxd->read.hdr_addr = 0;
2317 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2318                 rxd->read.rsvd1 = 0;
2319                 rxd->read.rsvd2 = 0;
2320 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2321
2322                 rxe[i].mbuf = mbuf;
2323         }
2324
2325         return 0;
2326 }
2327
2328 /*
2329  * Calculate the buffer length, and check the jumbo frame
2330  * and maximum packet length.
2331  */
2332 static int
2333 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2334 {
2335         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2336         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2337         struct rte_eth_dev_data *data = pf->dev_data;
2338         uint16_t buf_size, len;
2339
2340         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2341                 RTE_PKTMBUF_HEADROOM);
2342
2343         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2344                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2345         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2346                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2347                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2348                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2349                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2350                 rxq->hs_mode = i40e_header_split_enabled;
2351                 break;
2352         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2353         default:
2354                 rxq->rx_hdr_len = 0;
2355                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2356                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2357                 rxq->hs_mode = i40e_header_split_none;
2358                 break;
2359         }
2360
2361         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2362         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2363         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2364                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2365                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2366                         PMD_DRV_LOG(ERR, "maximum packet length must "
2367                                     "be larger than %u and smaller than %u,"
2368                                     "as jumbo frame is enabled",
2369                                     (uint32_t)ETHER_MAX_LEN,
2370                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2371                         return I40E_ERR_CONFIG;
2372                 }
2373         } else {
2374                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2375                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2376                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2377                                     "larger than %u and smaller than %u, "
2378                                     "as jumbo frame is disabled",
2379                                     (uint32_t)ETHER_MIN_LEN,
2380                                     (uint32_t)ETHER_MAX_LEN);
2381                         return I40E_ERR_CONFIG;
2382                 }
2383         }
2384
2385         return 0;
2386 }
2387
2388 /* Init the RX queue in hardware */
2389 int
2390 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2391 {
2392         int err = I40E_SUCCESS;
2393         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2394         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2395         uint16_t pf_q = rxq->reg_idx;
2396         uint16_t buf_size;
2397         struct i40e_hmc_obj_rxq rx_ctx;
2398
2399         err = i40e_rx_queue_config(rxq);
2400         if (err < 0) {
2401                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2402                 return err;
2403         }
2404
2405         /* Clear the context structure first */
2406         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2407         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2408         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2409
2410         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2411         rx_ctx.qlen = rxq->nb_rx_desc;
2412 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2413         rx_ctx.dsize = 1;
2414 #endif
2415         rx_ctx.dtype = rxq->hs_mode;
2416         if (rxq->hs_mode)
2417                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2418         else
2419                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2420         rx_ctx.rxmax = rxq->max_pkt_len;
2421         rx_ctx.tphrdesc_ena = 1;
2422         rx_ctx.tphwdesc_ena = 1;
2423         rx_ctx.tphdata_ena = 1;
2424         rx_ctx.tphhead_ena = 1;
2425         rx_ctx.lrxqthresh = 2;
2426         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2427         rx_ctx.l2tsel = 1;
2428         /* showiv indicates if inner VLAN is stripped inside of tunnel
2429          * packet. When set it to 1, vlan information is stripped from
2430          * the inner header, but the hardware does not put it in the
2431          * descriptor. So set it zero by default.
2432          */
2433         rx_ctx.showiv = 0;
2434         rx_ctx.prefena = 1;
2435
2436         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2437         if (err != I40E_SUCCESS) {
2438                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2439                 return err;
2440         }
2441         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2442         if (err != I40E_SUCCESS) {
2443                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2444                 return err;
2445         }
2446
2447         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2448
2449         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2450                 RTE_PKTMBUF_HEADROOM);
2451
2452         /* Check if scattered RX needs to be used. */
2453         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2454                 dev_data->scattered_rx = 1;
2455         }
2456
2457         /* Init the RX tail regieter. */
2458         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2459
2460         return 0;
2461 }
2462
2463 void
2464 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2465 {
2466         uint16_t i;
2467
2468         PMD_INIT_FUNC_TRACE();
2469
2470         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2471                 if (!dev->data->tx_queues[i])
2472                         continue;
2473                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2474                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2475         }
2476
2477         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2478                 if (!dev->data->rx_queues[i])
2479                         continue;
2480                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2481                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2482         }
2483 }
2484
2485 void
2486 i40e_dev_free_queues(struct rte_eth_dev *dev)
2487 {
2488         uint16_t i;
2489
2490         PMD_INIT_FUNC_TRACE();
2491
2492         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2493                 if (!dev->data->rx_queues[i])
2494                         continue;
2495                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2496                 dev->data->rx_queues[i] = NULL;
2497         }
2498         dev->data->nb_rx_queues = 0;
2499
2500         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2501                 if (!dev->data->tx_queues[i])
2502                         continue;
2503                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2504                 dev->data->tx_queues[i] = NULL;
2505         }
2506         dev->data->nb_tx_queues = 0;
2507 }
2508
2509 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2510 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2511
2512 enum i40e_status_code
2513 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2514 {
2515         struct i40e_tx_queue *txq;
2516         const struct rte_memzone *tz = NULL;
2517         uint32_t ring_size;
2518         struct rte_eth_dev *dev;
2519
2520         if (!pf) {
2521                 PMD_DRV_LOG(ERR, "PF is not available");
2522                 return I40E_ERR_BAD_PTR;
2523         }
2524
2525         dev = pf->adapter->eth_dev;
2526
2527         /* Allocate the TX queue data structure. */
2528         txq = rte_zmalloc_socket("i40e fdir tx queue",
2529                                   sizeof(struct i40e_tx_queue),
2530                                   RTE_CACHE_LINE_SIZE,
2531                                   SOCKET_ID_ANY);
2532         if (!txq) {
2533                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2534                                         "tx queue structure.");
2535                 return I40E_ERR_NO_MEMORY;
2536         }
2537
2538         /* Allocate TX hardware ring descriptors. */
2539         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2540         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2541
2542         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2543                                       I40E_FDIR_QUEUE_ID, ring_size,
2544                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2545         if (!tz) {
2546                 i40e_dev_tx_queue_release(txq);
2547                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2548                 return I40E_ERR_NO_MEMORY;
2549         }
2550
2551         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2552         txq->queue_id = I40E_FDIR_QUEUE_ID;
2553         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2554         txq->vsi = pf->fdir.fdir_vsi;
2555
2556         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2557         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2558         /*
2559          * don't need to allocate software ring and reset for the fdir
2560          * program queue just set the queue has been configured.
2561          */
2562         txq->q_set = TRUE;
2563         pf->fdir.txq = txq;
2564
2565         return I40E_SUCCESS;
2566 }
2567
2568 enum i40e_status_code
2569 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2570 {
2571         struct i40e_rx_queue *rxq;
2572         const struct rte_memzone *rz = NULL;
2573         uint32_t ring_size;
2574         struct rte_eth_dev *dev;
2575
2576         if (!pf) {
2577                 PMD_DRV_LOG(ERR, "PF is not available");
2578                 return I40E_ERR_BAD_PTR;
2579         }
2580
2581         dev = pf->adapter->eth_dev;
2582
2583         /* Allocate the RX queue data structure. */
2584         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2585                                   sizeof(struct i40e_rx_queue),
2586                                   RTE_CACHE_LINE_SIZE,
2587                                   SOCKET_ID_ANY);
2588         if (!rxq) {
2589                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2590                                         "rx queue structure.");
2591                 return I40E_ERR_NO_MEMORY;
2592         }
2593
2594         /* Allocate RX hardware ring descriptors. */
2595         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2596         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2597
2598         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2599                                       I40E_FDIR_QUEUE_ID, ring_size,
2600                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2601         if (!rz) {
2602                 i40e_dev_rx_queue_release(rxq);
2603                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2604                 return I40E_ERR_NO_MEMORY;
2605         }
2606
2607         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2608         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2609         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2610         rxq->vsi = pf->fdir.fdir_vsi;
2611
2612         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2613         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2614         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2615
2616         /*
2617          * Don't need to allocate software ring and reset for the fdir
2618          * rx queue, just set the queue has been configured.
2619          */
2620         rxq->q_set = TRUE;
2621         pf->fdir.rxq = rxq;
2622
2623         return I40E_SUCCESS;
2624 }
2625
2626 void
2627 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2628         struct rte_eth_rxq_info *qinfo)
2629 {
2630         struct i40e_rx_queue *rxq;
2631
2632         rxq = dev->data->rx_queues[queue_id];
2633
2634         qinfo->mp = rxq->mp;
2635         qinfo->scattered_rx = dev->data->scattered_rx;
2636         qinfo->nb_desc = rxq->nb_rx_desc;
2637
2638         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2639         qinfo->conf.rx_drop_en = rxq->drop_en;
2640         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2641 }
2642
2643 void
2644 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2645         struct rte_eth_txq_info *qinfo)
2646 {
2647         struct i40e_tx_queue *txq;
2648
2649         txq = dev->data->tx_queues[queue_id];
2650
2651         qinfo->nb_desc = txq->nb_tx_desc;
2652
2653         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2654         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2655         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2656
2657         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2658         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2659         qinfo->conf.txq_flags = txq->txq_flags;
2660         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2661 }
2662
2663 void __attribute__((cold))
2664 i40e_set_rx_function(struct rte_eth_dev *dev)
2665 {
2666         struct i40e_adapter *ad =
2667                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2668         uint16_t rx_using_sse, i;
2669         /* In order to allow Vector Rx there are a few configuration
2670          * conditions to be met and Rx Bulk Allocation should be allowed.
2671          */
2672         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2673                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2674                     !ad->rx_bulk_alloc_allowed) {
2675                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2676                                      " Vector Rx preconditions",
2677                                      dev->data->port_id);
2678
2679                         ad->rx_vec_allowed = false;
2680                 }
2681                 if (ad->rx_vec_allowed) {
2682                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2683                                 struct i40e_rx_queue *rxq =
2684                                         dev->data->rx_queues[i];
2685
2686                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2687                                         ad->rx_vec_allowed = false;
2688                                         break;
2689                                 }
2690                         }
2691                 }
2692         }
2693
2694         if (dev->data->scattered_rx) {
2695                 /* Set the non-LRO scattered callback: there are Vector and
2696                  * single allocation versions.
2697                  */
2698                 if (ad->rx_vec_allowed) {
2699                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2700                                             "callback (port=%d).",
2701                                      dev->data->port_id);
2702
2703                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2704                 } else {
2705                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2706                                            "allocation callback (port=%d).",
2707                                      dev->data->port_id);
2708                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2709                 }
2710         /* If parameters allow we are going to choose between the following
2711          * callbacks:
2712          *    - Vector
2713          *    - Bulk Allocation
2714          *    - Single buffer allocation (the simplest one)
2715          */
2716         } else if (ad->rx_vec_allowed) {
2717                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2718                                     "burst size no less than %d (port=%d).",
2719                              RTE_I40E_DESCS_PER_LOOP,
2720                              dev->data->port_id);
2721
2722                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2723         } else if (ad->rx_bulk_alloc_allowed) {
2724                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2725                                     "satisfied. Rx Burst Bulk Alloc function "
2726                                     "will be used on port=%d.",
2727                              dev->data->port_id);
2728
2729                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2730         } else {
2731                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2732                                     "satisfied, or Scattered Rx is requested "
2733                                     "(port=%d).",
2734                              dev->data->port_id);
2735
2736                 dev->rx_pkt_burst = i40e_recv_pkts;
2737         }
2738
2739         /* Propagate information about RX function choice through all queues. */
2740         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2741                 rx_using_sse =
2742                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2743                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2744
2745                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2746                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2747
2748                         if (rxq)
2749                                 rxq->rx_using_sse = rx_using_sse;
2750                 }
2751         }
2752 }
2753
2754 void __attribute__((cold))
2755 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2756 {
2757         struct i40e_adapter *ad =
2758                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2759
2760         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2761         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2762                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2763                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2764                         PMD_INIT_LOG(DEBUG, "Vector tx"
2765                                      " can be enabled on this txq.");
2766
2767                 } else {
2768                         ad->tx_vec_allowed = false;
2769                 }
2770         } else {
2771                 ad->tx_simple_allowed = false;
2772         }
2773 }
2774
2775 void __attribute__((cold))
2776 i40e_set_tx_function(struct rte_eth_dev *dev)
2777 {
2778         struct i40e_adapter *ad =
2779                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2780         int i;
2781
2782         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2783                 if (ad->tx_vec_allowed) {
2784                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2785                                 struct i40e_tx_queue *txq =
2786                                         dev->data->tx_queues[i];
2787
2788                                 if (txq && i40e_txq_vec_setup(txq)) {
2789                                         ad->tx_vec_allowed = false;
2790                                         break;
2791                                 }
2792                         }
2793                 }
2794         }
2795
2796         if (ad->tx_simple_allowed) {
2797                 if (ad->tx_vec_allowed) {
2798                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2799                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2800                 } else {
2801                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2802                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2803                 }
2804         } else {
2805                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2806                 dev->tx_pkt_burst = i40e_xmit_pkts;
2807         }
2808 }
2809
2810 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2811 int __attribute__((weak))
2812 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2813 {
2814         return -1;
2815 }
2816
2817 uint16_t __attribute__((weak))
2818 i40e_recv_pkts_vec(
2819         void __rte_unused *rx_queue,
2820         struct rte_mbuf __rte_unused **rx_pkts,
2821         uint16_t __rte_unused nb_pkts)
2822 {
2823         return 0;
2824 }
2825
2826 uint16_t __attribute__((weak))
2827 i40e_recv_scattered_pkts_vec(
2828         void __rte_unused *rx_queue,
2829         struct rte_mbuf __rte_unused **rx_pkts,
2830         uint16_t __rte_unused nb_pkts)
2831 {
2832         return 0;
2833 }
2834
2835 int __attribute__((weak))
2836 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2837 {
2838         return -1;
2839 }
2840
2841 int __attribute__((weak))
2842 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2843 {
2844         return -1;
2845 }
2846
2847 void __attribute__((weak))
2848 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2849 {
2850         return;
2851 }
2852
2853 uint16_t __attribute__((weak))
2854 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2855                    struct rte_mbuf __rte_unused **tx_pkts,
2856                    uint16_t __rte_unused nb_pkts)
2857 {
2858         return 0;
2859 }