drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 142                 return flags;
 143         /* If RXE bit set, all other status bits are meaningless */
 144         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 145                 flags |= PKT_RX_MAC_ERR;
 146                 return flags;
 147         }
 148
 149         /* If RECIPE bit set, all other status indications should be ignored */
 150         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 151                 flags |= PKT_RX_RECIP_ERR;
 152                 return flags;
 153         }
 154         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 155                 flags |= PKT_RX_HBUF_OVERFLOW;
 156         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 157                 flags |= PKT_RX_IP_CKSUM_BAD;
 158         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 159                 flags |= PKT_RX_L4_CKSUM_BAD;
 160         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 161                 flags |= PKT_RX_EIP_CKSUM_BAD;
 162         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 163                 flags |= PKT_RX_OVERSIZE;
 164
 165         return flags;
 166 }
 167
 168 /* Function to check and set the ieee1588 timesync index and get the
 169  * appropriate flags.
 170  */
 171 #ifdef RTE_LIBRTE_IEEE1588
 172 static inline uint64_t
 173 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 174 {
 175         uint64_t pkt_flags = 0;
 176         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 177                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 178                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 179
 180         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 181                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 182                 pkt_flags = PKT_RX_IEEE1588_PTP;
 183         if (tsyn & 0x04) {
 184                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 185                 mb->timesync = tsyn & 0x03;
 186         }
 187
 188         return pkt_flags;
 189 }
 190 #endif
 191
 192 /* For each value it means, datasheet of hardware can tell more details
 193  *
 194  * @note: fix i40e_dev_supported_ptypes_get() if any change here.
 195  */
 196 static inline uint32_t
 197 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 198 {
 199         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 200                 /* L2 types */
 201                 /* [0] reserved */
 202                 [1] = RTE_PTYPE_L2_ETHER,
 203                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 204                 /* [3] - [5] reserved */
 205                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 206                 /* [7] - [10] reserved */
 207                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 208                 /* [12] - [21] reserved */
 209
 210                 /* Non tunneled IPv4 */
 211                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 212                         RTE_PTYPE_L4_FRAG,
 213                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_L4_NONFRAG,
 215                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_L4_UDP,
 217                 /* [25] reserved */
 218                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 219                         RTE_PTYPE_L4_TCP,
 220                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                         RTE_PTYPE_L4_SCTP,
 222                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                         RTE_PTYPE_L4_ICMP,
 224
 225                 /* IPv4 --> IPv4 */
 226                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 227                         RTE_PTYPE_TUNNEL_IP |
 228                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_INNER_L4_FRAG,
 230                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_TUNNEL_IP |
 232                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_INNER_L4_NONFRAG,
 234                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_TUNNEL_IP |
 236                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 237                         RTE_PTYPE_INNER_L4_UDP,
 238                 /* [32] reserved */
 239                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 240                         RTE_PTYPE_TUNNEL_IP |
 241                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 242                         RTE_PTYPE_INNER_L4_TCP,
 243                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 244                         RTE_PTYPE_TUNNEL_IP |
 245                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 246                         RTE_PTYPE_INNER_L4_SCTP,
 247                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 248                         RTE_PTYPE_TUNNEL_IP |
 249                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_INNER_L4_ICMP,
 251
 252                 /* IPv4 --> IPv6 */
 253                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 254                         RTE_PTYPE_TUNNEL_IP |
 255                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 256                         RTE_PTYPE_INNER_L4_FRAG,
 257                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 258                         RTE_PTYPE_TUNNEL_IP |
 259                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 260                         RTE_PTYPE_INNER_L4_NONFRAG,
 261                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 262                         RTE_PTYPE_TUNNEL_IP |
 263                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 264                         RTE_PTYPE_INNER_L4_UDP,
 265                 /* [39] reserved */
 266                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 267                         RTE_PTYPE_TUNNEL_IP |
 268                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 269                         RTE_PTYPE_INNER_L4_TCP,
 270                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 271                         RTE_PTYPE_TUNNEL_IP |
 272                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 273                         RTE_PTYPE_INNER_L4_SCTP,
 274                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 275                         RTE_PTYPE_TUNNEL_IP |
 276                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 277                         RTE_PTYPE_INNER_L4_ICMP,
 278
 279                 /* IPv4 --> GRE/Teredo/VXLAN */
 280                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 281                         RTE_PTYPE_TUNNEL_GRENAT,
 282
 283                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 284                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 285                         RTE_PTYPE_TUNNEL_GRENAT |
 286                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_INNER_L4_FRAG,
 288                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_TUNNEL_GRENAT |
 290                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_INNER_L4_NONFRAG,
 292                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_TUNNEL_GRENAT |
 294                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 295                         RTE_PTYPE_INNER_L4_UDP,
 296                 /* [47] reserved */
 297                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 298                         RTE_PTYPE_TUNNEL_GRENAT |
 299                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 300                         RTE_PTYPE_INNER_L4_TCP,
 301                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 302                         RTE_PTYPE_TUNNEL_GRENAT |
 303                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 304                         RTE_PTYPE_INNER_L4_SCTP,
 305                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 306                         RTE_PTYPE_TUNNEL_GRENAT |
 307                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_INNER_L4_ICMP,
 309
 310                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 311                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 312                         RTE_PTYPE_TUNNEL_GRENAT |
 313                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 314                         RTE_PTYPE_INNER_L4_FRAG,
 315                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 316                         RTE_PTYPE_TUNNEL_GRENAT |
 317                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 318                         RTE_PTYPE_INNER_L4_NONFRAG,
 319                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 320                         RTE_PTYPE_TUNNEL_GRENAT |
 321                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 322                         RTE_PTYPE_INNER_L4_UDP,
 323                 /* [54] reserved */
 324                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 325                         RTE_PTYPE_TUNNEL_GRENAT |
 326                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 327                         RTE_PTYPE_INNER_L4_TCP,
 328                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 329                         RTE_PTYPE_TUNNEL_GRENAT |
 330                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 331                         RTE_PTYPE_INNER_L4_SCTP,
 332                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 333                         RTE_PTYPE_TUNNEL_GRENAT |
 334                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 335                         RTE_PTYPE_INNER_L4_ICMP,
 336
 337                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 338                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 339                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 340
 341                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 342                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 343                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 344                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_INNER_L4_FRAG,
 346                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 348                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_INNER_L4_NONFRAG,
 350                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 352                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 353                         RTE_PTYPE_INNER_L4_UDP,
 354                 /* [62] reserved */
 355                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 356                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 357                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 358                         RTE_PTYPE_INNER_L4_TCP,
 359                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 360                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 361                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 362                         RTE_PTYPE_INNER_L4_SCTP,
 363                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 364                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 365                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_INNER_L4_ICMP,
 367
 368                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 369                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 370                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 371                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 372                         RTE_PTYPE_INNER_L4_FRAG,
 373                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 374                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 375                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 376                         RTE_PTYPE_INNER_L4_NONFRAG,
 377                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 378                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 379                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 380                         RTE_PTYPE_INNER_L4_UDP,
 381                 /* [69] reserved */
 382                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 383                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 384                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 385                         RTE_PTYPE_INNER_L4_TCP,
 386                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 387                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 388                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 389                         RTE_PTYPE_INNER_L4_SCTP,
 390                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 391                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 392                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 393                         RTE_PTYPE_INNER_L4_ICMP,
 394
 395                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 396                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 397                         RTE_PTYPE_TUNNEL_GRENAT |
 398                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 399
 400                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 401                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 402                         RTE_PTYPE_TUNNEL_GRENAT |
 403                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 404                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 405                         RTE_PTYPE_INNER_L4_FRAG,
 406                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 407                         RTE_PTYPE_TUNNEL_GRENAT |
 408                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 409                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 410                         RTE_PTYPE_INNER_L4_NONFRAG,
 411                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 412                         RTE_PTYPE_TUNNEL_GRENAT |
 413                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 414                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 415                         RTE_PTYPE_INNER_L4_UDP,
 416                 /* [77] reserved */
 417                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 418                         RTE_PTYPE_TUNNEL_GRENAT |
 419                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 420                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 421                         RTE_PTYPE_INNER_L4_TCP,
 422                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 423                         RTE_PTYPE_TUNNEL_GRENAT |
 424                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 425                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 426                         RTE_PTYPE_INNER_L4_SCTP,
 427                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 428                         RTE_PTYPE_TUNNEL_GRENAT |
 429                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 430                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 431                         RTE_PTYPE_INNER_L4_ICMP,
 432
 433                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 434                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 435                         RTE_PTYPE_TUNNEL_GRENAT |
 436                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 437                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 438                         RTE_PTYPE_INNER_L4_FRAG,
 439                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 440                         RTE_PTYPE_TUNNEL_GRENAT |
 441                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 442                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 443                         RTE_PTYPE_INNER_L4_NONFRAG,
 444                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 445                         RTE_PTYPE_TUNNEL_GRENAT |
 446                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 447                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 448                         RTE_PTYPE_INNER_L4_UDP,
 449                 /* [84] reserved */
 450                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 451                         RTE_PTYPE_TUNNEL_GRENAT |
 452                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 453                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 454                         RTE_PTYPE_INNER_L4_TCP,
 455                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 456                         RTE_PTYPE_TUNNEL_GRENAT |
 457                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 458                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 459                         RTE_PTYPE_INNER_L4_SCTP,
 460                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 461                         RTE_PTYPE_TUNNEL_GRENAT |
 462                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 463                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 464                         RTE_PTYPE_INNER_L4_ICMP,
 465
 466                 /* Non tunneled IPv6 */
 467                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 468                         RTE_PTYPE_L4_FRAG,
 469                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 470                         RTE_PTYPE_L4_NONFRAG,
 471                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_L4_UDP,
 473                 /* [91] reserved */
 474                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 475                         RTE_PTYPE_L4_TCP,
 476                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 477                         RTE_PTYPE_L4_SCTP,
 478                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 479                         RTE_PTYPE_L4_ICMP,
 480
 481                 /* IPv6 --> IPv4 */
 482                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 483                         RTE_PTYPE_TUNNEL_IP |
 484                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 485                         RTE_PTYPE_INNER_L4_FRAG,
 486                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 487                         RTE_PTYPE_TUNNEL_IP |
 488                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 489                         RTE_PTYPE_INNER_L4_NONFRAG,
 490                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 491                         RTE_PTYPE_TUNNEL_IP |
 492                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 493                         RTE_PTYPE_INNER_L4_UDP,
 494                 /* [98] reserved */
 495                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 496                         RTE_PTYPE_TUNNEL_IP |
 497                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 498                         RTE_PTYPE_INNER_L4_TCP,
 499                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 500                         RTE_PTYPE_TUNNEL_IP |
 501                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 502                         RTE_PTYPE_INNER_L4_SCTP,
 503                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 504                         RTE_PTYPE_TUNNEL_IP |
 505                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 506                         RTE_PTYPE_INNER_L4_ICMP,
 507
 508                 /* IPv6 --> IPv6 */
 509                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 510                         RTE_PTYPE_TUNNEL_IP |
 511                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_INNER_L4_FRAG,
 513                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_TUNNEL_IP |
 515                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_INNER_L4_NONFRAG,
 517                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_TUNNEL_IP |
 519                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 520                         RTE_PTYPE_INNER_L4_UDP,
 521                 /* [105] reserved */
 522                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 523                         RTE_PTYPE_TUNNEL_IP |
 524                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 525                         RTE_PTYPE_INNER_L4_TCP,
 526                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 527                         RTE_PTYPE_TUNNEL_IP |
 528                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 529                         RTE_PTYPE_INNER_L4_SCTP,
 530                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 531                         RTE_PTYPE_TUNNEL_IP |
 532                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_INNER_L4_ICMP,
 534
 535                 /* IPv6 --> GRE/Teredo/VXLAN */
 536                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 537                         RTE_PTYPE_TUNNEL_GRENAT,
 538
 539                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 540                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 541                         RTE_PTYPE_TUNNEL_GRENAT |
 542                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 543                         RTE_PTYPE_INNER_L4_FRAG,
 544                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 545                         RTE_PTYPE_TUNNEL_GRENAT |
 546                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 547                         RTE_PTYPE_INNER_L4_NONFRAG,
 548                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 549                         RTE_PTYPE_TUNNEL_GRENAT |
 550                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 551                         RTE_PTYPE_INNER_L4_UDP,
 552                 /* [113] reserved */
 553                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 554                         RTE_PTYPE_TUNNEL_GRENAT |
 555                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 556                         RTE_PTYPE_INNER_L4_TCP,
 557                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 558                         RTE_PTYPE_TUNNEL_GRENAT |
 559                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 560                         RTE_PTYPE_INNER_L4_SCTP,
 561                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 562                         RTE_PTYPE_TUNNEL_GRENAT |
 563                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 564                         RTE_PTYPE_INNER_L4_ICMP,
 565
 566                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 567                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 568                         RTE_PTYPE_TUNNEL_GRENAT |
 569                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_INNER_L4_FRAG,
 571                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_TUNNEL_GRENAT |
 573                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_INNER_L4_NONFRAG,
 575                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_TUNNEL_GRENAT |
 577                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 578                         RTE_PTYPE_INNER_L4_UDP,
 579                 /* [120] reserved */
 580                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 581                         RTE_PTYPE_TUNNEL_GRENAT |
 582                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 583                         RTE_PTYPE_INNER_L4_TCP,
 584                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 585                         RTE_PTYPE_TUNNEL_GRENAT |
 586                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 587                         RTE_PTYPE_INNER_L4_SCTP,
 588                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 589                         RTE_PTYPE_TUNNEL_GRENAT |
 590                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_INNER_L4_ICMP,
 592
 593                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 594                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 595                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 596
 597                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 598                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 599                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 600                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 601                         RTE_PTYPE_INNER_L4_FRAG,
 602                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 603                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 604                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 605                         RTE_PTYPE_INNER_L4_NONFRAG,
 606                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 607                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 608                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 609                         RTE_PTYPE_INNER_L4_UDP,
 610                 /* [128] reserved */
 611                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 612                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 613                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 614                         RTE_PTYPE_INNER_L4_TCP,
 615                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 616                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 617                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 618                         RTE_PTYPE_INNER_L4_SCTP,
 619                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 620                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 621                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 622                         RTE_PTYPE_INNER_L4_ICMP,
 623
 624                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 625                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 626                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 627                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_INNER_L4_FRAG,
 629                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 631                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_INNER_L4_NONFRAG,
 633                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 635                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 636                         RTE_PTYPE_INNER_L4_UDP,
 637                 /* [135] reserved */
 638                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 639                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 640                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 641                         RTE_PTYPE_INNER_L4_TCP,
 642                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 644                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 645                         RTE_PTYPE_INNER_L4_SCTP,
 646                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 647                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 648                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_INNER_L4_ICMP,
 650
 651                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 652                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 653                         RTE_PTYPE_TUNNEL_GRENAT |
 654                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 655
 656                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 657                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 658                         RTE_PTYPE_TUNNEL_GRENAT |
 659                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 660                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 661                         RTE_PTYPE_INNER_L4_FRAG,
 662                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 663                         RTE_PTYPE_TUNNEL_GRENAT |
 664                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 665                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 666                         RTE_PTYPE_INNER_L4_NONFRAG,
 667                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 668                         RTE_PTYPE_TUNNEL_GRENAT |
 669                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 670                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 671                         RTE_PTYPE_INNER_L4_UDP,
 672                 /* [143] reserved */
 673                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 674                         RTE_PTYPE_TUNNEL_GRENAT |
 675                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 676                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 677                         RTE_PTYPE_INNER_L4_TCP,
 678                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 679                         RTE_PTYPE_TUNNEL_GRENAT |
 680                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 681                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 682                         RTE_PTYPE_INNER_L4_SCTP,
 683                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 684                         RTE_PTYPE_TUNNEL_GRENAT |
 685                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 686                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 687                         RTE_PTYPE_INNER_L4_ICMP,
 688
 689                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 690                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 691                         RTE_PTYPE_TUNNEL_GRENAT |
 692                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 693                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 694                         RTE_PTYPE_INNER_L4_FRAG,
 695                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 696                         RTE_PTYPE_TUNNEL_GRENAT |
 697                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 698                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 699                         RTE_PTYPE_INNER_L4_NONFRAG,
 700                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 701                         RTE_PTYPE_TUNNEL_GRENAT |
 702                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 703                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 704                         RTE_PTYPE_INNER_L4_UDP,
 705                 /* [150] reserved */
 706                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 707                         RTE_PTYPE_TUNNEL_GRENAT |
 708                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 709                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 710                         RTE_PTYPE_INNER_L4_TCP,
 711                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 712                         RTE_PTYPE_TUNNEL_GRENAT |
 713                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 714                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 715                         RTE_PTYPE_INNER_L4_SCTP,
 716                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 717                         RTE_PTYPE_TUNNEL_GRENAT |
 718                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 719                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 720                         RTE_PTYPE_INNER_L4_ICMP,
 721
 722                 /* All others reserved */
 723         };
 724
 725         return type_table[ptype];
 726 }
 727
 728 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 729 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 730 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 731 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 732 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 733
 734 static inline uint64_t
 735 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 736 {
 737         uint64_t flags = 0;
 738 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 739         uint16_t flexbh, flexbl;
 740
 741         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 742                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 743                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 744         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 745                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 746                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 747
 748
 749         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 750                 mb->hash.fdir.hi =
 751                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 752                 flags |= PKT_RX_FDIR_ID;
 753         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 754                 mb->hash.fdir.hi =
 755                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 756                 flags |= PKT_RX_FDIR_FLX;
 757         }
 758         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 759                 mb->hash.fdir.lo =
 760                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 761                 flags |= PKT_RX_FDIR_FLX;
 762         }
 763 #else
 764         mb->hash.fdir.hi =
 765                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 766         flags |= PKT_RX_FDIR_ID;
 767 #endif
 768         return flags;
 769 }
 770 static inline void
 771 i40e_txd_enable_checksum(uint64_t ol_flags,
 772                         uint32_t *td_cmd,
 773                         uint32_t *td_offset,
 774                         union i40e_tx_offload tx_offload,
 775                         uint32_t *cd_tunneling)
 776 {
 777         /* UDP tunneling packet TX checksum offload */
 778         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 779
 780                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 781                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 782
 783                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 784                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 785                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 786                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 787                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 788                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 789
 790                 /* Now set the ctx descriptor fields */
 791                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 792                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 793                                 (tx_offload.l2_len >> 1) <<
 794                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 795
 796         } else
 797                 *td_offset |= (tx_offload.l2_len >> 1)
 798                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 799
 800         /* Enable L3 checksum offloads */
 801         if (ol_flags & PKT_TX_IP_CKSUM) {
 802                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 803                 *td_offset |= (tx_offload.l3_len >> 2)
 804                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 805         } else if (ol_flags & PKT_TX_IPV4) {
 806                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 807                 *td_offset |= (tx_offload.l3_len >> 2)
 808                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 809         } else if (ol_flags & PKT_TX_IPV6) {
 810                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 811                 *td_offset |= (tx_offload.l3_len >> 2)
 812                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 813         }
 814
 815         if (ol_flags & PKT_TX_TCP_SEG) {
 816                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 817                 *td_offset |= (tx_offload.l4_len >> 2)
 818                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 819                 return;
 820         }
 821
 822         /* Enable L4 checksum offloads */
 823         switch (ol_flags & PKT_TX_L4_MASK) {
 824         case PKT_TX_TCP_CKSUM:
 825                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 826                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 827                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 828                 break;
 829         case PKT_TX_SCTP_CKSUM:
 830                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 831                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 832                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 833                 break;
 834         case PKT_TX_UDP_CKSUM:
 835                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 836                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 837                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 838                 break;
 839         default:
 840                 break;
 841         }
 842 }
 843
 844 static inline struct rte_mbuf *
 845 rte_rxmbuf_alloc(struct rte_mempool *mp)
 846 {
 847         struct rte_mbuf *m;
 848
 849         m = __rte_mbuf_raw_alloc(mp);
 850         __rte_mbuf_sanity_check_raw(m, 0);
 851
 852         return m;
 853 }
 854
 855 /* Construct the tx flags */
 856 static inline uint64_t
 857 i40e_build_ctob(uint32_t td_cmd,
 858                 uint32_t td_offset,
 859                 unsigned int size,
 860                 uint32_t td_tag)
 861 {
 862         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 863                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 864                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 865                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 866                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 867 }
 868
 869 static inline int
 870 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 871 {
 872         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 873         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 874         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 875         uint16_t nb_tx_desc = txq->nb_tx_desc;
 876         uint16_t desc_to_clean_to;
 877         uint16_t nb_tx_to_clean;
 878
 879         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 880         if (desc_to_clean_to >= nb_tx_desc)
 881                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 882
 883         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 884         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 885                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 886                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 887                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 888                         "(port=%d queue=%d)", desc_to_clean_to,
 889                                 txq->port_id, txq->queue_id);
 890                 return -1;
 891         }
 892
 893         if (last_desc_cleaned > desc_to_clean_to)
 894                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 895                                                         desc_to_clean_to);
 896         else
 897                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 898                                         last_desc_cleaned);
 899
 900         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 901
 902         txq->last_desc_cleaned = desc_to_clean_to;
 903         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 904
 905         return 0;
 906 }
 907
 908 static inline int
 909 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 910 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 911 #else
 912 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 913 #endif
 914 {
 915         int ret = 0;
 916
 917 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 918         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 919                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 920                              "rxq->rx_free_thresh=%d, "
 921                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 922                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 923                 ret = -EINVAL;
 924         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 925                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 926                              "rxq->rx_free_thresh=%d, "
 927                              "rxq->nb_rx_desc=%d",
 928                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 929                 ret = -EINVAL;
 930         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 931                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 932                              "rxq->nb_rx_desc=%d, "
 933                              "rxq->rx_free_thresh=%d",
 934                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 935                 ret = -EINVAL;
 936         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 937                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 938                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 939                              "rxq->nb_rx_desc=%d, "
 940                              "I40E_MAX_RING_DESC=%d, "
 941                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 942                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 943                              RTE_PMD_I40E_RX_MAX_BURST);
 944                 ret = -EINVAL;
 945         }
 946 #else
 947         ret = -EINVAL;
 948 #endif
 949
 950         return ret;
 951 }
 952
 953 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 954 #define I40E_LOOK_AHEAD 8
 955 #if (I40E_LOOK_AHEAD != 8)
 956 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 957 #endif
 958 static inline int
 959 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 960 {
 961         volatile union i40e_rx_desc *rxdp;
 962         struct i40e_rx_entry *rxep;
 963         struct rte_mbuf *mb;
 964         uint16_t pkt_len;
 965         uint64_t qword1;
 966         uint32_t rx_status;
 967         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 968         int32_t i, j, nb_rx = 0;
 969         uint64_t pkt_flags;
 970
 971         rxdp = &rxq->rx_ring[rxq->rx_tail];
 972         rxep = &rxq->sw_ring[rxq->rx_tail];
 973
 974         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 975         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 976                                 I40E_RXD_QW1_STATUS_SHIFT;
 977
 978         /* Make sure there is at least 1 packet to receive */
 979         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 980                 return 0;
 981
 982         /**
 983          * Scan LOOK_AHEAD descriptors at a time to determine which
 984          * descriptors reference packets that are ready to be received.
 985          */
 986         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 987                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 988                 /* Read desc statuses backwards to avoid race condition */
 989                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 990                         qword1 = rte_le_to_cpu_64(\
 991                                 rxdp[j].wb.qword1.status_error_len);
 992                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 993                                         I40E_RXD_QW1_STATUS_SHIFT;
 994                 }
 995
 996                 /* Compute how many status bits were set */
 997                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 998                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 999
1000                 nb_rx += nb_dd;
1001
1002                 /* Translate descriptor info to mbuf parameters */
1003                 for (j = 0; j < nb_dd; j++) {
1004                         mb = rxep[j].mbuf;
1005                         qword1 = rte_le_to_cpu_64(\
1006                                 rxdp[j].wb.qword1.status_error_len);
1007                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1008                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1009                         mb->data_len = pkt_len;
1010                         mb->pkt_len = pkt_len;
1011                         mb->ol_flags = 0;
1012                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1013                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1014                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1015                         mb->packet_type =
1016                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1017                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1018                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1019                         if (pkt_flags & PKT_RX_RSS_HASH)
1020                                 mb->hash.rss = rte_le_to_cpu_32(\
1021                                         rxdp[j].wb.qword0.hi_dword.rss);
1022                         if (pkt_flags & PKT_RX_FDIR)
1023                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1024
1025 #ifdef RTE_LIBRTE_IEEE1588
1026                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1027 #endif
1028                         mb->ol_flags |= pkt_flags;
1029
1030                 }
1031
1032                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1033                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1034
1035                 if (nb_dd != I40E_LOOK_AHEAD)
1036                         break;
1037         }
1038
1039         /* Clear software ring entries */
1040         for (i = 0; i < nb_rx; i++)
1041                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1042
1043         return nb_rx;
1044 }
1045
1046 static inline uint16_t
1047 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1048                         struct rte_mbuf **rx_pkts,
1049                         uint16_t nb_pkts)
1050 {
1051         uint16_t i;
1052         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1053
1054         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1055
1056         for (i = 0; i < nb_pkts; i++)
1057                 rx_pkts[i] = stage[i];
1058
1059         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1060         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1061
1062         return nb_pkts;
1063 }
1064
1065 static inline int
1066 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1067 {
1068         volatile union i40e_rx_desc *rxdp;
1069         struct i40e_rx_entry *rxep;
1070         struct rte_mbuf *mb;
1071         uint16_t alloc_idx, i;
1072         uint64_t dma_addr;
1073         int diag;
1074
1075         /* Allocate buffers in bulk */
1076         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1077                                 (rxq->rx_free_thresh - 1));
1078         rxep = &(rxq->sw_ring[alloc_idx]);
1079         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1080                                         rxq->rx_free_thresh);
1081         if (unlikely(diag != 0)) {
1082                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1083                 return -ENOMEM;
1084         }
1085
1086         rxdp = &rxq->rx_ring[alloc_idx];
1087         for (i = 0; i < rxq->rx_free_thresh; i++) {
1088                 if (likely(i < (rxq->rx_free_thresh - 1)))
1089                         /* Prefetch next mbuf */
1090                         rte_prefetch0(rxep[i + 1].mbuf);
1091
1092                 mb = rxep[i].mbuf;
1093                 rte_mbuf_refcnt_set(mb, 1);
1094                 mb->next = NULL;
1095                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1096                 mb->nb_segs = 1;
1097                 mb->port = rxq->port_id;
1098                 dma_addr = rte_cpu_to_le_64(\
1099                         rte_mbuf_data_dma_addr_default(mb));
1100                 rxdp[i].read.hdr_addr = 0;
1101                 rxdp[i].read.pkt_addr = dma_addr;
1102         }
1103
1104         /* Update rx tail regsiter */
1105         rte_wmb();
1106         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1107
1108         rxq->rx_free_trigger =
1109                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1110         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1111                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1112
1113         return 0;
1114 }
1115
1116 static inline uint16_t
1117 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1118 {
1119         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1120         uint16_t nb_rx = 0;
1121
1122         if (!nb_pkts)
1123                 return 0;
1124
1125         if (rxq->rx_nb_avail)
1126                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1127
1128         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1129         rxq->rx_next_avail = 0;
1130         rxq->rx_nb_avail = nb_rx;
1131         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1132
1133         if (rxq->rx_tail > rxq->rx_free_trigger) {
1134                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1135                         uint16_t i, j;
1136
1137                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1138                                    "port_id=%u, queue_id=%u",
1139                                    rxq->port_id, rxq->queue_id);
1140                         rxq->rx_nb_avail = 0;
1141                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1142                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1143                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1144
1145                         return 0;
1146                 }
1147         }
1148
1149         if (rxq->rx_tail >= rxq->nb_rx_desc)
1150                 rxq->rx_tail = 0;
1151
1152         if (rxq->rx_nb_avail)
1153                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1154
1155         return 0;
1156 }
1157
1158 static uint16_t
1159 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1160                           struct rte_mbuf **rx_pkts,
1161                           uint16_t nb_pkts)
1162 {
1163         uint16_t nb_rx = 0, n, count;
1164
1165         if (unlikely(nb_pkts == 0))
1166                 return 0;
1167
1168         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1169                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1170
1171         while (nb_pkts) {
1172                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1173                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1174                 nb_rx = (uint16_t)(nb_rx + count);
1175                 nb_pkts = (uint16_t)(nb_pkts - count);
1176                 if (count < n)
1177                         break;
1178         }
1179
1180         return nb_rx;
1181 }
1182 #else
1183 static uint16_t
1184 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1185                           struct rte_mbuf __rte_unused **rx_pkts,
1186                           uint16_t __rte_unused nb_pkts)
1187 {
1188         return 0;
1189 }
1190 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1191
1192 uint16_t
1193 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1194 {
1195         struct i40e_rx_queue *rxq;
1196         volatile union i40e_rx_desc *rx_ring;
1197         volatile union i40e_rx_desc *rxdp;
1198         union i40e_rx_desc rxd;
1199         struct i40e_rx_entry *sw_ring;
1200         struct i40e_rx_entry *rxe;
1201         struct rte_mbuf *rxm;
1202         struct rte_mbuf *nmb;
1203         uint16_t nb_rx;
1204         uint32_t rx_status;
1205         uint64_t qword1;
1206         uint16_t rx_packet_len;
1207         uint16_t rx_id, nb_hold;
1208         uint64_t dma_addr;
1209         uint64_t pkt_flags;
1210
1211         nb_rx = 0;
1212         nb_hold = 0;
1213         rxq = rx_queue;
1214         rx_id = rxq->rx_tail;
1215         rx_ring = rxq->rx_ring;
1216         sw_ring = rxq->sw_ring;
1217
1218         while (nb_rx < nb_pkts) {
1219                 rxdp = &rx_ring[rx_id];
1220                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1221                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1222                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1223
1224                 /* Check the DD bit first */
1225                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1226                         break;
1227
1228                 nmb = rte_rxmbuf_alloc(rxq->mp);
1229                 if (unlikely(!nmb))
1230                         break;
1231                 rxd = *rxdp;
1232
1233                 nb_hold++;
1234                 rxe = &sw_ring[rx_id];
1235                 rx_id++;
1236                 if (unlikely(rx_id == rxq->nb_rx_desc))
1237                         rx_id = 0;
1238
1239                 /* Prefetch next mbuf */
1240                 rte_prefetch0(sw_ring[rx_id].mbuf);
1241
1242                 /**
1243                  * When next RX descriptor is on a cache line boundary,
1244                  * prefetch the next 4 RX descriptors and next 8 pointers
1245                  * to mbufs.
1246                  */
1247                 if ((rx_id & 0x3) == 0) {
1248                         rte_prefetch0(&rx_ring[rx_id]);
1249                         rte_prefetch0(&sw_ring[rx_id]);
1250                 }
1251                 rxm = rxe->mbuf;
1252                 rxe->mbuf = nmb;
1253                 dma_addr =
1254                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1255                 rxdp->read.hdr_addr = 0;
1256                 rxdp->read.pkt_addr = dma_addr;
1257
1258                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1259                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1260
1261                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1262                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1263                 rxm->nb_segs = 1;
1264                 rxm->next = NULL;
1265                 rxm->pkt_len = rx_packet_len;
1266                 rxm->data_len = rx_packet_len;
1267                 rxm->port = rxq->port_id;
1268                 rxm->ol_flags = 0;
1269                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1270                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1271                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1272                 rxm->packet_type =
1273                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1274                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1275                 if (pkt_flags & PKT_RX_RSS_HASH)
1276                         rxm->hash.rss =
1277                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1278                 if (pkt_flags & PKT_RX_FDIR)
1279                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1280
1281 #ifdef RTE_LIBRTE_IEEE1588
1282                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1283 #endif
1284                 rxm->ol_flags |= pkt_flags;
1285
1286                 rx_pkts[nb_rx++] = rxm;
1287         }
1288         rxq->rx_tail = rx_id;
1289
1290         /**
1291          * If the number of free RX descriptors is greater than the RX free
1292          * threshold of the queue, advance the receive tail register of queue.
1293          * Update that register with the value of the last processed RX
1294          * descriptor minus 1.
1295          */
1296         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1297         if (nb_hold > rxq->rx_free_thresh) {
1298                 rx_id = (uint16_t) ((rx_id == 0) ?
1299                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1300                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1301                 nb_hold = 0;
1302         }
1303         rxq->nb_rx_hold = nb_hold;
1304
1305         return nb_rx;
1306 }
1307
1308 uint16_t
1309 i40e_recv_scattered_pkts(void *rx_queue,
1310                          struct rte_mbuf **rx_pkts,
1311                          uint16_t nb_pkts)
1312 {
1313         struct i40e_rx_queue *rxq = rx_queue;
1314         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1315         volatile union i40e_rx_desc *rxdp;
1316         union i40e_rx_desc rxd;
1317         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1318         struct i40e_rx_entry *rxe;
1319         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321         struct rte_mbuf *nmb, *rxm;
1322         uint16_t rx_id = rxq->rx_tail;
1323         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1324         uint32_t rx_status;
1325         uint64_t qword1;
1326         uint64_t dma_addr;
1327         uint64_t pkt_flags;
1328
1329         while (nb_rx < nb_pkts) {
1330                 rxdp = &rx_ring[rx_id];
1331                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1332                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1333                                         I40E_RXD_QW1_STATUS_SHIFT;
1334
1335                 /* Check the DD bit */
1336                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1337                         break;
1338
1339                 nmb = rte_rxmbuf_alloc(rxq->mp);
1340                 if (unlikely(!nmb))
1341                         break;
1342                 rxd = *rxdp;
1343                 nb_hold++;
1344                 rxe = &sw_ring[rx_id];
1345                 rx_id++;
1346                 if (rx_id == rxq->nb_rx_desc)
1347                         rx_id = 0;
1348
1349                 /* Prefetch next mbuf */
1350                 rte_prefetch0(sw_ring[rx_id].mbuf);
1351
1352                 /**
1353                  * When next RX descriptor is on a cache line boundary,
1354                  * prefetch the next 4 RX descriptors and next 8 pointers
1355                  * to mbufs.
1356                  */
1357                 if ((rx_id & 0x3) == 0) {
1358                         rte_prefetch0(&rx_ring[rx_id]);
1359                         rte_prefetch0(&sw_ring[rx_id]);
1360                 }
1361
1362                 rxm = rxe->mbuf;
1363                 rxe->mbuf = nmb;
1364                 dma_addr =
1365                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1366
1367                 /* Set data buffer address and data length of the mbuf */
1368                 rxdp->read.hdr_addr = 0;
1369                 rxdp->read.pkt_addr = dma_addr;
1370                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1371                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1372                 rxm->data_len = rx_packet_len;
1373                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1374
1375                 /**
1376                  * If this is the first buffer of the received packet, set the
1377                  * pointer to the first mbuf of the packet and initialize its
1378                  * context. Otherwise, update the total length and the number
1379                  * of segments of the current scattered packet, and update the
1380                  * pointer to the last mbuf of the current packet.
1381                  */
1382                 if (!first_seg) {
1383                         first_seg = rxm;
1384                         first_seg->nb_segs = 1;
1385                         first_seg->pkt_len = rx_packet_len;
1386                 } else {
1387                         first_seg->pkt_len =
1388                                 (uint16_t)(first_seg->pkt_len +
1389                                                 rx_packet_len);
1390                         first_seg->nb_segs++;
1391                         last_seg->next = rxm;
1392                 }
1393
1394                 /**
1395                  * If this is not the last buffer of the received packet,
1396                  * update the pointer to the last mbuf of the current scattered
1397                  * packet and continue to parse the RX ring.
1398                  */
1399                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1400                         last_seg = rxm;
1401                         continue;
1402                 }
1403
1404                 /**
1405                  * This is the last buffer of the received packet. If the CRC
1406                  * is not stripped by the hardware:
1407                  *  - Subtract the CRC length from the total packet length.
1408                  *  - If the last buffer only contains the whole CRC or a part
1409                  *  of it, free the mbuf associated to the last buffer. If part
1410                  *  of the CRC is also contained in the previous mbuf, subtract
1411                  *  the length of that CRC part from the data length of the
1412                  *  previous mbuf.
1413                  */
1414                 rxm->next = NULL;
1415                 if (unlikely(rxq->crc_len > 0)) {
1416                         first_seg->pkt_len -= ETHER_CRC_LEN;
1417                         if (rx_packet_len <= ETHER_CRC_LEN) {
1418                                 rte_pktmbuf_free_seg(rxm);
1419                                 first_seg->nb_segs--;
1420                                 last_seg->data_len =
1421                                         (uint16_t)(last_seg->data_len -
1422                                         (ETHER_CRC_LEN - rx_packet_len));
1423                                 last_seg->next = NULL;
1424                         } else
1425                                 rxm->data_len = (uint16_t)(rx_packet_len -
1426                                                                 ETHER_CRC_LEN);
1427                 }
1428
1429                 first_seg->port = rxq->port_id;
1430                 first_seg->ol_flags = 0;
1431                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1432                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1433                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1434                 first_seg->packet_type =
1435                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1436                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1437                 if (pkt_flags & PKT_RX_RSS_HASH)
1438                         rxm->hash.rss =
1439                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1440                 if (pkt_flags & PKT_RX_FDIR)
1441                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1442
1443 #ifdef RTE_LIBRTE_IEEE1588
1444                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1445 #endif
1446                 first_seg->ol_flags |= pkt_flags;
1447
1448                 /* Prefetch data of first segment, if configured to do so. */
1449                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1450                         first_seg->data_off));
1451                 rx_pkts[nb_rx++] = first_seg;
1452                 first_seg = NULL;
1453         }
1454
1455         /* Record index of the next RX descriptor to probe. */
1456         rxq->rx_tail = rx_id;
1457         rxq->pkt_first_seg = first_seg;
1458         rxq->pkt_last_seg = last_seg;
1459
1460         /**
1461          * If the number of free RX descriptors is greater than the RX free
1462          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1463          * register. Update the RDT with the value of the last processed RX
1464          * descriptor minus 1, to guarantee that the RDT register is never
1465          * equal to the RDH register, which creates a "full" ring situtation
1466          * from the hardware point of view.
1467          */
1468         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1469         if (nb_hold > rxq->rx_free_thresh) {
1470                 rx_id = (uint16_t)(rx_id == 0 ?
1471                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1472                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1473                 nb_hold = 0;
1474         }
1475         rxq->nb_rx_hold = nb_hold;
1476
1477         return nb_rx;
1478 }
1479
1480 /* Check if the context descriptor is needed for TX offloading */
1481 static inline uint16_t
1482 i40e_calc_context_desc(uint64_t flags)
1483 {
1484         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1485                 PKT_TX_TCP_SEG |
1486                 PKT_TX_QINQ_PKT;
1487
1488 #ifdef RTE_LIBRTE_IEEE1588
1489         mask |= PKT_TX_IEEE1588_TMST;
1490 #endif
1491
1492         return (flags & mask) ? 1 : 0;
1493 }
1494
1495 /* set i40e TSO context descriptor */
1496 static inline uint64_t
1497 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1498 {
1499         uint64_t ctx_desc = 0;
1500         uint32_t cd_cmd, hdr_len, cd_tso_len;
1501
1502         if (!tx_offload.l4_len) {
1503                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1504                 return ctx_desc;
1505         }
1506
1507         /**
1508          * in case of tunneling packet, the outer_l2_len and
1509          * outer_l3_len must be 0.
1510          */
1511         hdr_len = tx_offload.outer_l2_len +
1512                 tx_offload.outer_l3_len +
1513                 tx_offload.l2_len +
1514                 tx_offload.l3_len +
1515                 tx_offload.l4_len;
1516
1517         cd_cmd = I40E_TX_CTX_DESC_TSO;
1518         cd_tso_len = mbuf->pkt_len - hdr_len;
1519         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1520                 ((uint64_t)cd_tso_len <<
1521                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1522                 ((uint64_t)mbuf->tso_segsz <<
1523                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1524
1525         return ctx_desc;
1526 }
1527
1528 uint16_t
1529 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1530 {
1531         struct i40e_tx_queue *txq;
1532         struct i40e_tx_entry *sw_ring;
1533         struct i40e_tx_entry *txe, *txn;
1534         volatile struct i40e_tx_desc *txd;
1535         volatile struct i40e_tx_desc *txr;
1536         struct rte_mbuf *tx_pkt;
1537         struct rte_mbuf *m_seg;
1538         uint32_t cd_tunneling_params;
1539         uint16_t tx_id;
1540         uint16_t nb_tx;
1541         uint32_t td_cmd;
1542         uint32_t td_offset;
1543         uint32_t tx_flags;
1544         uint32_t td_tag;
1545         uint64_t ol_flags;
1546         uint16_t nb_used;
1547         uint16_t nb_ctx;
1548         uint16_t tx_last;
1549         uint16_t slen;
1550         uint64_t buf_dma_addr;
1551         union i40e_tx_offload tx_offload = {0};
1552
1553         txq = tx_queue;
1554         sw_ring = txq->sw_ring;
1555         txr = txq->tx_ring;
1556         tx_id = txq->tx_tail;
1557         txe = &sw_ring[tx_id];
1558
1559         /* Check if the descriptor ring needs to be cleaned. */
1560         if (txq->nb_tx_free < txq->tx_free_thresh)
1561                 i40e_xmit_cleanup(txq);
1562
1563         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1564                 td_cmd = 0;
1565                 td_tag = 0;
1566                 td_offset = 0;
1567                 tx_flags = 0;
1568
1569                 tx_pkt = *tx_pkts++;
1570                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1571
1572                 ol_flags = tx_pkt->ol_flags;
1573                 tx_offload.l2_len = tx_pkt->l2_len;
1574                 tx_offload.l3_len = tx_pkt->l3_len;
1575                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1576                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1577                 tx_offload.l4_len = tx_pkt->l4_len;
1578                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1579
1580                 /* Calculate the number of context descriptors needed. */
1581                 nb_ctx = i40e_calc_context_desc(ol_flags);
1582
1583                 /**
1584                  * The number of descriptors that must be allocated for
1585                  * a packet equals to the number of the segments of that
1586                  * packet plus 1 context descriptor if needed.
1587                  */
1588                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1589                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1590
1591                 /* Circular ring */
1592                 if (tx_last >= txq->nb_tx_desc)
1593                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1594
1595                 if (nb_used > txq->nb_tx_free) {
1596                         if (i40e_xmit_cleanup(txq) != 0) {
1597                                 if (nb_tx == 0)
1598                                         return 0;
1599                                 goto end_of_tx;
1600                         }
1601                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1602                                 while (nb_used > txq->nb_tx_free) {
1603                                         if (i40e_xmit_cleanup(txq) != 0) {
1604                                                 if (nb_tx == 0)
1605                                                         return 0;
1606                                                 goto end_of_tx;
1607                                         }
1608                                 }
1609                         }
1610                 }
1611
1612                 /* Descriptor based VLAN insertion */
1613                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1614                         tx_flags |= tx_pkt->vlan_tci <<
1615                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1616                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1617                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1618                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1619                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1620                 }
1621
1622                 /* Always enable CRC offload insertion */
1623                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1624
1625                 /* Enable checksum offloading */
1626                 cd_tunneling_params = 0;
1627                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1628                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1629                                 tx_offload, &cd_tunneling_params);
1630                 }
1631
1632                 if (nb_ctx) {
1633                         /* Setup TX context descriptor if required */
1634                         volatile struct i40e_tx_context_desc *ctx_txd =
1635                                 (volatile struct i40e_tx_context_desc *)\
1636                                                         &txr[tx_id];
1637                         uint16_t cd_l2tag2 = 0;
1638                         uint64_t cd_type_cmd_tso_mss =
1639                                 I40E_TX_DESC_DTYPE_CONTEXT;
1640
1641                         txn = &sw_ring[txe->next_id];
1642                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1643                         if (txe->mbuf != NULL) {
1644                                 rte_pktmbuf_free_seg(txe->mbuf);
1645                                 txe->mbuf = NULL;
1646                         }
1647
1648                         /* TSO enabled means no timestamp */
1649                         if (ol_flags & PKT_TX_TCP_SEG)
1650                                 cd_type_cmd_tso_mss |=
1651                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1652                         else {
1653 #ifdef RTE_LIBRTE_IEEE1588
1654                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1655                                         cd_type_cmd_tso_mss |=
1656                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1657                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1658 #endif
1659                         }
1660
1661                         ctx_txd->tunneling_params =
1662                                 rte_cpu_to_le_32(cd_tunneling_params);
1663                         if (ol_flags & PKT_TX_QINQ_PKT) {
1664                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1665                                 cd_type_cmd_tso_mss |=
1666                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1667                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1668                         }
1669                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1670                         ctx_txd->type_cmd_tso_mss =
1671                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1672
1673                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1674                                 "tunneling_params: %#x;\n"
1675                                 "l2tag2: %#hx;\n"
1676                                 "rsvd: %#hx;\n"
1677                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1678                                 tx_pkt, tx_id,
1679                                 ctx_txd->tunneling_params,
1680                                 ctx_txd->l2tag2,
1681                                 ctx_txd->rsvd,
1682                                 ctx_txd->type_cmd_tso_mss);
1683
1684                         txe->last_id = tx_last;
1685                         tx_id = txe->next_id;
1686                         txe = txn;
1687                 }
1688
1689                 m_seg = tx_pkt;
1690                 do {
1691                         txd = &txr[tx_id];
1692                         txn = &sw_ring[txe->next_id];
1693
1694                         if (txe->mbuf)
1695                                 rte_pktmbuf_free_seg(txe->mbuf);
1696                         txe->mbuf = m_seg;
1697
1698                         /* Setup TX Descriptor */
1699                         slen = m_seg->data_len;
1700                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1701
1702                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1703                                 "buf_dma_addr: %#"PRIx64";\n"
1704                                 "td_cmd: %#x;\n"
1705                                 "td_offset: %#x;\n"
1706                                 "td_len: %u;\n"
1707                                 "td_tag: %#x;\n",
1708                                 tx_pkt, tx_id, buf_dma_addr,
1709                                 td_cmd, td_offset, slen, td_tag);
1710
1711                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1712                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1713                                                 td_offset, slen, td_tag);
1714                         txe->last_id = tx_last;
1715                         tx_id = txe->next_id;
1716                         txe = txn;
1717                         m_seg = m_seg->next;
1718                 } while (m_seg != NULL);
1719
1720                 /* The last packet data descriptor needs End Of Packet (EOP) */
1721                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1722                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1723                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1724
1725                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1726                         PMD_TX_FREE_LOG(DEBUG,
1727                                         "Setting RS bit on TXD id="
1728                                         "%4u (port=%d queue=%d)",
1729                                         tx_last, txq->port_id, txq->queue_id);
1730
1731                         td_cmd |= I40E_TX_DESC_CMD_RS;
1732
1733                         /* Update txq RS bit counters */
1734                         txq->nb_tx_used = 0;
1735                 }
1736
1737                 txd->cmd_type_offset_bsz |=
1738                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1739                                         I40E_TXD_QW1_CMD_SHIFT);
1740         }
1741
1742 end_of_tx:
1743         rte_wmb();
1744
1745         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1746                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1747                    (unsigned) tx_id, (unsigned) nb_tx);
1748
1749         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1750         txq->tx_tail = tx_id;
1751
1752         return nb_tx;
1753 }
1754
1755 static inline int __attribute__((always_inline))
1756 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1757 {
1758         struct i40e_tx_entry *txep;
1759         uint16_t i;
1760
1761         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1762                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1763                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1764                 return 0;
1765
1766         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1767
1768         for (i = 0; i < txq->tx_rs_thresh; i++)
1769                 rte_prefetch0((txep + i)->mbuf);
1770
1771         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1772                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1773                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1774                         txep->mbuf = NULL;
1775                 }
1776         } else {
1777                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1778                         rte_pktmbuf_free_seg(txep->mbuf);
1779                         txep->mbuf = NULL;
1780                 }
1781         }
1782
1783         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1784         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1785         if (txq->tx_next_dd >= txq->nb_tx_desc)
1786                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1787
1788         return txq->tx_rs_thresh;
1789 }
1790
1791 /* Populate 4 descriptors with data from 4 mbufs */
1792 static inline void
1793 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1794 {
1795         uint64_t dma_addr;
1796         uint32_t i;
1797
1798         for (i = 0; i < 4; i++, txdp++, pkts++) {
1799                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1800                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1801                 txdp->cmd_type_offset_bsz =
1802                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1803                                         (*pkts)->data_len, 0);
1804         }
1805 }
1806
1807 /* Populate 1 descriptor with data from 1 mbuf */
1808 static inline void
1809 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1810 {
1811         uint64_t dma_addr;
1812
1813         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1814         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1815         txdp->cmd_type_offset_bsz =
1816                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1817                                 (*pkts)->data_len, 0);
1818 }
1819
1820 /* Fill hardware descriptor ring with mbuf data */
1821 static inline void
1822 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1823                      struct rte_mbuf **pkts,
1824                      uint16_t nb_pkts)
1825 {
1826         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1827         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1828         const int N_PER_LOOP = 4;
1829         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1830         int mainpart, leftover;
1831         int i, j;
1832
1833         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1834         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1835         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1836                 for (j = 0; j < N_PER_LOOP; ++j) {
1837                         (txep + i + j)->mbuf = *(pkts + i + j);
1838                 }
1839                 tx4(txdp + i, pkts + i);
1840         }
1841         if (unlikely(leftover > 0)) {
1842                 for (i = 0; i < leftover; ++i) {
1843                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1844                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1845                 }
1846         }
1847 }
1848
1849 static inline uint16_t
1850 tx_xmit_pkts(struct i40e_tx_queue *txq,
1851              struct rte_mbuf **tx_pkts,
1852              uint16_t nb_pkts)
1853 {
1854         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1855         uint16_t n = 0;
1856
1857         /**
1858          * Begin scanning the H/W ring for done descriptors when the number
1859          * of available descriptors drops below tx_free_thresh. For each done
1860          * descriptor, free the associated buffer.
1861          */
1862         if (txq->nb_tx_free < txq->tx_free_thresh)
1863                 i40e_tx_free_bufs(txq);
1864
1865         /* Use available descriptor only */
1866         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1867         if (unlikely(!nb_pkts))
1868                 return 0;
1869
1870         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1871         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1872                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1873                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1874                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1875                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1876                                                 I40E_TXD_QW1_CMD_SHIFT);
1877                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1878                 txq->tx_tail = 0;
1879         }
1880
1881         /* Fill hardware descriptor ring with mbuf data */
1882         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1883         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1884
1885         /* Determin if RS bit needs to be set */
1886         if (txq->tx_tail > txq->tx_next_rs) {
1887                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1888                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1889                                                 I40E_TXD_QW1_CMD_SHIFT);
1890                 txq->tx_next_rs =
1891                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1892                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1893                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1894         }
1895
1896         if (txq->tx_tail >= txq->nb_tx_desc)
1897                 txq->tx_tail = 0;
1898
1899         /* Update the tx tail register */
1900         rte_wmb();
1901         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1902
1903         return nb_pkts;
1904 }
1905
1906 static uint16_t
1907 i40e_xmit_pkts_simple(void *tx_queue,
1908                       struct rte_mbuf **tx_pkts,
1909                       uint16_t nb_pkts)
1910 {
1911         uint16_t nb_tx = 0;
1912
1913         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1914                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1915                                                 tx_pkts, nb_pkts);
1916
1917         while (nb_pkts) {
1918                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1919                                                 I40E_TX_MAX_BURST);
1920
1921                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1922                                                 &tx_pkts[nb_tx], num);
1923                 nb_tx = (uint16_t)(nb_tx + ret);
1924                 nb_pkts = (uint16_t)(nb_pkts - ret);
1925                 if (ret < num)
1926                         break;
1927         }
1928
1929         return nb_tx;
1930 }
1931
1932 /*
1933  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1934  * application used, which assume having sequential ones. But from driver's
1935  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1936  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1937  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1938  * use queue_idx from 0 to 95 to access queues, while real queue would be
1939  * different. This function will do a queue mapping to find VSI the queue
1940  * belongs to.
1941  */
1942 static struct i40e_vsi*
1943 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1944 {
1945         /* the queue in MAIN VSI range */
1946         if (queue_idx < pf->main_vsi->nb_qps)
1947                 return pf->main_vsi;
1948
1949         queue_idx -= pf->main_vsi->nb_qps;
1950
1951         /* queue_idx is greater than VMDQ VSIs range */
1952         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1953                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1954                 return NULL;
1955         }
1956
1957         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1958 }
1959
1960 static uint16_t
1961 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1962 {
1963         /* the queue in MAIN VSI range */
1964         if (queue_idx < pf->main_vsi->nb_qps)
1965                 return queue_idx;
1966
1967         /* It's VMDQ queues */
1968         queue_idx -= pf->main_vsi->nb_qps;
1969
1970         if (pf->nb_cfg_vmdq_vsi)
1971                 return queue_idx % pf->vmdq_nb_qps;
1972         else {
1973                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1974                 return (uint16_t)(-1);
1975         }
1976 }
1977
1978 int
1979 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1980 {
1981         struct i40e_rx_queue *rxq;
1982         int err = -1;
1983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (rx_queue_id < dev->data->nb_rx_queues) {
1988                 rxq = dev->data->rx_queues[rx_queue_id];
1989
1990                 err = i40e_alloc_rx_queue_mbufs(rxq);
1991                 if (err) {
1992                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1993                         return err;
1994                 }
1995
1996                 rte_wmb();
1997
1998                 /* Init the RX tail regieter. */
1999                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2000
2001                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
2002
2003                 if (err) {
2004                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
2005                                     rx_queue_id);
2006
2007                         i40e_rx_queue_release_mbufs(rxq);
2008                         i40e_reset_rx_queue(rxq);
2009                 } else
2010                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2011         }
2012
2013         return err;
2014 }
2015
2016 int
2017 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2018 {
2019         struct i40e_rx_queue *rxq;
2020         int err;
2021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022
2023         if (rx_queue_id < dev->data->nb_rx_queues) {
2024                 rxq = dev->data->rx_queues[rx_queue_id];
2025
2026                 /*
2027                 * rx_queue_id is queue id aplication refers to, while
2028                 * rxq->reg_idx is the real queue index.
2029                 */
2030                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2031
2032                 if (err) {
2033                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2034                                     rx_queue_id);
2035                         return err;
2036                 }
2037                 i40e_rx_queue_release_mbufs(rxq);
2038                 i40e_reset_rx_queue(rxq);
2039                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2040         }
2041
2042         return 0;
2043 }
2044
2045 int
2046 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2047 {
2048         int err = -1;
2049         struct i40e_tx_queue *txq;
2050         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         if (tx_queue_id < dev->data->nb_tx_queues) {
2055                 txq = dev->data->tx_queues[tx_queue_id];
2056
2057                 /*
2058                 * tx_queue_id is queue id aplication refers to, while
2059                 * rxq->reg_idx is the real queue index.
2060                 */
2061                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2062                 if (err)
2063                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2064                                     tx_queue_id);
2065                 else
2066                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2067         }
2068
2069         return err;
2070 }
2071
2072 int
2073 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2074 {
2075         struct i40e_tx_queue *txq;
2076         int err;
2077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078
2079         if (tx_queue_id < dev->data->nb_tx_queues) {
2080                 txq = dev->data->tx_queues[tx_queue_id];
2081
2082                 /*
2083                 * tx_queue_id is queue id aplication refers to, while
2084                 * txq->reg_idx is the real queue index.
2085                 */
2086                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2087
2088                 if (err) {
2089                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2090                                     tx_queue_id);
2091                         return err;
2092                 }
2093
2094                 i40e_tx_queue_release_mbufs(txq);
2095                 i40e_reset_tx_queue(txq);
2096                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2097         }
2098
2099         return 0;
2100 }
2101
2102 const uint32_t *
2103 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2104 {
2105         static const uint32_t ptypes[] = {
2106                 /* refers to i40e_rxd_pkt_type_mapping() */
2107                 RTE_PTYPE_L2_ETHER,
2108                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2109                 RTE_PTYPE_L2_ETHER_LLDP,
2110                 RTE_PTYPE_L2_ETHER_ARP,
2111                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2112                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2113                 RTE_PTYPE_L4_FRAG,
2114                 RTE_PTYPE_L4_ICMP,
2115                 RTE_PTYPE_L4_NONFRAG,
2116                 RTE_PTYPE_L4_SCTP,
2117                 RTE_PTYPE_L4_TCP,
2118                 RTE_PTYPE_L4_UDP,
2119                 RTE_PTYPE_TUNNEL_GRENAT,
2120                 RTE_PTYPE_TUNNEL_IP,
2121                 RTE_PTYPE_INNER_L2_ETHER,
2122                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2123                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2124                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2125                 RTE_PTYPE_INNER_L4_FRAG,
2126                 RTE_PTYPE_INNER_L4_ICMP,
2127                 RTE_PTYPE_INNER_L4_NONFRAG,
2128                 RTE_PTYPE_INNER_L4_SCTP,
2129                 RTE_PTYPE_INNER_L4_TCP,
2130                 RTE_PTYPE_INNER_L4_UDP,
2131                 RTE_PTYPE_UNKNOWN
2132         };
2133
2134         if (dev->rx_pkt_burst == i40e_recv_pkts ||
2135 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2136             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
2137 #endif
2138             dev->rx_pkt_burst == i40e_recv_scattered_pkts)
2139                 return ptypes;
2140         return NULL;
2141 }
2142
2143 int
2144 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2145                         uint16_t queue_idx,
2146                         uint16_t nb_desc,
2147                         unsigned int socket_id,
2148                         const struct rte_eth_rxconf *rx_conf,
2149                         struct rte_mempool *mp)
2150 {
2151         struct i40e_vsi *vsi;
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154         struct i40e_adapter *ad =
2155                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2156         struct i40e_rx_queue *rxq;
2157         const struct rte_memzone *rz;
2158         uint32_t ring_size;
2159         uint16_t len, i;
2160         uint16_t base, bsf, tc_mapping;
2161         int use_def_burst_func = 1;
2162
2163         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2164                 struct i40e_vf *vf =
2165                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2166                 vsi = &vf->vsi;
2167         } else
2168                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2169
2170         if (vsi == NULL) {
2171                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2172                             "index exceeds the maximum");
2173                 return I40E_ERR_PARAM;
2174         }
2175         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2176                         (nb_desc > I40E_MAX_RING_DESC) ||
2177                         (nb_desc < I40E_MIN_RING_DESC)) {
2178                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2179                             "invalid", nb_desc);
2180                 return I40E_ERR_PARAM;
2181         }
2182
2183         /* Free memory if needed */
2184         if (dev->data->rx_queues[queue_idx]) {
2185                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2186                 dev->data->rx_queues[queue_idx] = NULL;
2187         }
2188
2189         /* Allocate the rx queue data structure */
2190         rxq = rte_zmalloc_socket("i40e rx queue",
2191                                  sizeof(struct i40e_rx_queue),
2192                                  RTE_CACHE_LINE_SIZE,
2193                                  socket_id);
2194         if (!rxq) {
2195                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2196                             "rx queue data structure");
2197                 return -ENOMEM;
2198         }
2199         rxq->mp = mp;
2200         rxq->nb_rx_desc = nb_desc;
2201         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2202         rxq->queue_id = queue_idx;
2203         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2204                 rxq->reg_idx = queue_idx;
2205         else /* PF device */
2206                 rxq->reg_idx = vsi->base_queue +
2207                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2208
2209         rxq->port_id = dev->data->port_id;
2210         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2211                                                         0 : ETHER_CRC_LEN);
2212         rxq->drop_en = rx_conf->rx_drop_en;
2213         rxq->vsi = vsi;
2214         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2215
2216         /* Allocate the maximun number of RX ring hardware descriptor. */
2217         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2218         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2219         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2220                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2221         if (!rz) {
2222                 i40e_dev_rx_queue_release(rxq);
2223                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2224                 return -ENOMEM;
2225         }
2226
2227         /* Zero all the descriptors in the ring. */
2228         memset(rz->addr, 0, ring_size);
2229
2230         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2231         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2232
2233 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2234         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2235 #else
2236         len = nb_desc;
2237 #endif
2238
2239         /* Allocate the software ring. */
2240         rxq->sw_ring =
2241                 rte_zmalloc_socket("i40e rx sw ring",
2242                                    sizeof(struct i40e_rx_entry) * len,
2243                                    RTE_CACHE_LINE_SIZE,
2244                                    socket_id);
2245         if (!rxq->sw_ring) {
2246                 i40e_dev_rx_queue_release(rxq);
2247                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2248                 return -ENOMEM;
2249         }
2250
2251         i40e_reset_rx_queue(rxq);
2252         rxq->q_set = TRUE;
2253         dev->data->rx_queues[queue_idx] = rxq;
2254
2255         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2256
2257         if (!use_def_burst_func) {
2258 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2259                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2260                              "satisfied. Rx Burst Bulk Alloc function will be "
2261                              "used on port=%d, queue=%d.",
2262                              rxq->port_id, rxq->queue_id);
2263 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2264         } else {
2265                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2266                              "not satisfied, Scattered Rx is requested, "
2267                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2268                              "not enabled on port=%d, queue=%d.",
2269                              rxq->port_id, rxq->queue_id);
2270                 ad->rx_bulk_alloc_allowed = false;
2271         }
2272
2273         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2274                 if (!(vsi->enabled_tc & (1 << i)))
2275                         continue;
2276                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2277                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2278                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2279                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2280                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2281
2282                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2283                         rxq->dcb_tc = i;
2284         }
2285
2286         return 0;
2287 }
2288
2289 void
2290 i40e_dev_rx_queue_release(void *rxq)
2291 {
2292         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2293
2294         if (!q) {
2295                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2296                 return;
2297         }
2298
2299         i40e_rx_queue_release_mbufs(q);
2300         rte_free(q->sw_ring);
2301         rte_free(q);
2302 }
2303
2304 uint32_t
2305 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2306 {
2307 #define I40E_RXQ_SCAN_INTERVAL 4
2308         volatile union i40e_rx_desc *rxdp;
2309         struct i40e_rx_queue *rxq;
2310         uint16_t desc = 0;
2311
2312         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2313                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2314                 return 0;
2315         }
2316
2317         rxq = dev->data->rx_queues[rx_queue_id];
2318         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2319         while ((desc < rxq->nb_rx_desc) &&
2320                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2321                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2322                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2323                 /**
2324                  * Check the DD bit of a rx descriptor of each 4 in a group,
2325                  * to avoid checking too frequently and downgrading performance
2326                  * too much.
2327                  */
2328                 desc += I40E_RXQ_SCAN_INTERVAL;
2329                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2330                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2331                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2332                                         desc - rxq->nb_rx_desc]);
2333         }
2334
2335         return desc;
2336 }
2337
2338 int
2339 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2340 {
2341         volatile union i40e_rx_desc *rxdp;
2342         struct i40e_rx_queue *rxq = rx_queue;
2343         uint16_t desc;
2344         int ret;
2345
2346         if (unlikely(offset >= rxq->nb_rx_desc)) {
2347                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2348                 return 0;
2349         }
2350
2351         desc = rxq->rx_tail + offset;
2352         if (desc >= rxq->nb_rx_desc)
2353                 desc -= rxq->nb_rx_desc;
2354
2355         rxdp = &(rxq->rx_ring[desc]);
2356
2357         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2358                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2359                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2360
2361         return ret;
2362 }
2363
2364 int
2365 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2366                         uint16_t queue_idx,
2367                         uint16_t nb_desc,
2368                         unsigned int socket_id,
2369                         const struct rte_eth_txconf *tx_conf)
2370 {
2371         struct i40e_vsi *vsi;
2372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374         struct i40e_tx_queue *txq;
2375         const struct rte_memzone *tz;
2376         uint32_t ring_size;
2377         uint16_t tx_rs_thresh, tx_free_thresh;
2378         uint16_t i, base, bsf, tc_mapping;
2379
2380         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2381                 struct i40e_vf *vf =
2382                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2383                 vsi = &vf->vsi;
2384         } else
2385                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2386
2387         if (vsi == NULL) {
2388                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2389                             "exceeds the maximum", queue_idx);
2390                 return I40E_ERR_PARAM;
2391         }
2392
2393         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2394                         (nb_desc > I40E_MAX_RING_DESC) ||
2395                         (nb_desc < I40E_MIN_RING_DESC)) {
2396                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2397                             "invalid", nb_desc);
2398                 return I40E_ERR_PARAM;
2399         }
2400
2401         /**
2402          * The following two parameters control the setting of the RS bit on
2403          * transmit descriptors. TX descriptors will have their RS bit set
2404          * after txq->tx_rs_thresh descriptors have been used. The TX
2405          * descriptor ring will be cleaned after txq->tx_free_thresh
2406          * descriptors are used or if the number of descriptors required to
2407          * transmit a packet is greater than the number of free TX descriptors.
2408          *
2409          * The following constraints must be satisfied:
2410          *  - tx_rs_thresh must be greater than 0.
2411          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2412          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2413          *  - tx_rs_thresh must be a divisor of the ring size.
2414          *  - tx_free_thresh must be greater than 0.
2415          *  - tx_free_thresh must be less than the size of the ring minus 3.
2416          *
2417          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2418          * race condition, hence the maximum threshold constraints. When set
2419          * to zero use default values.
2420          */
2421         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2422                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2423         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2424                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2425         if (tx_rs_thresh >= (nb_desc - 2)) {
2426                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2427                              "number of TX descriptors minus 2. "
2428                              "(tx_rs_thresh=%u port=%d queue=%d)",
2429                              (unsigned int)tx_rs_thresh,
2430                              (int)dev->data->port_id,
2431                              (int)queue_idx);
2432                 return I40E_ERR_PARAM;
2433         }
2434         if (tx_free_thresh >= (nb_desc - 3)) {
2435                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2436                              "tx_free_thresh must be less than the "
2437                              "number of TX descriptors minus 3. "
2438                              "(tx_free_thresh=%u port=%d queue=%d)",
2439                              (unsigned int)tx_free_thresh,
2440                              (int)dev->data->port_id,
2441                              (int)queue_idx);
2442                 return I40E_ERR_PARAM;
2443         }
2444         if (tx_rs_thresh > tx_free_thresh) {
2445                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2446                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2447                              " tx_rs_thresh=%u port=%d queue=%d)",
2448                              (unsigned int)tx_free_thresh,
2449                              (unsigned int)tx_rs_thresh,
2450                              (int)dev->data->port_id,
2451                              (int)queue_idx);
2452                 return I40E_ERR_PARAM;
2453         }
2454         if ((nb_desc % tx_rs_thresh) != 0) {
2455                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2456                              "number of TX descriptors. (tx_rs_thresh=%u"
2457                              " port=%d queue=%d)",
2458                              (unsigned int)tx_rs_thresh,
2459                              (int)dev->data->port_id,
2460                              (int)queue_idx);
2461                 return I40E_ERR_PARAM;
2462         }
2463         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2464                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2465                              "tx_rs_thresh is greater than 1. "
2466                              "(tx_rs_thresh=%u port=%d queue=%d)",
2467                              (unsigned int)tx_rs_thresh,
2468                              (int)dev->data->port_id,
2469                              (int)queue_idx);
2470                 return I40E_ERR_PARAM;
2471         }
2472
2473         /* Free memory if needed. */
2474         if (dev->data->tx_queues[queue_idx]) {
2475                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2476                 dev->data->tx_queues[queue_idx] = NULL;
2477         }
2478
2479         /* Allocate the TX queue data structure. */
2480         txq = rte_zmalloc_socket("i40e tx queue",
2481                                   sizeof(struct i40e_tx_queue),
2482                                   RTE_CACHE_LINE_SIZE,
2483                                   socket_id);
2484         if (!txq) {
2485                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2486                             "tx queue structure");
2487                 return -ENOMEM;
2488         }
2489
2490         /* Allocate TX hardware ring descriptors. */
2491         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2492         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2493         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2494                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2495         if (!tz) {
2496                 i40e_dev_tx_queue_release(txq);
2497                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2498                 return -ENOMEM;
2499         }
2500
2501         txq->nb_tx_desc = nb_desc;
2502         txq->tx_rs_thresh = tx_rs_thresh;
2503         txq->tx_free_thresh = tx_free_thresh;
2504         txq->pthresh = tx_conf->tx_thresh.pthresh;
2505         txq->hthresh = tx_conf->tx_thresh.hthresh;
2506         txq->wthresh = tx_conf->tx_thresh.wthresh;
2507         txq->queue_id = queue_idx;
2508         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2509                 txq->reg_idx = queue_idx;
2510         else /* PF device */
2511                 txq->reg_idx = vsi->base_queue +
2512                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2513
2514         txq->port_id = dev->data->port_id;
2515         txq->txq_flags = tx_conf->txq_flags;
2516         txq->vsi = vsi;
2517         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2518
2519         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2520         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2521
2522         /* Allocate software ring */
2523         txq->sw_ring =
2524                 rte_zmalloc_socket("i40e tx sw ring",
2525                                    sizeof(struct i40e_tx_entry) * nb_desc,
2526                                    RTE_CACHE_LINE_SIZE,
2527                                    socket_id);
2528         if (!txq->sw_ring) {
2529                 i40e_dev_tx_queue_release(txq);
2530                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2531                 return -ENOMEM;
2532         }
2533
2534         i40e_reset_tx_queue(txq);
2535         txq->q_set = TRUE;
2536         dev->data->tx_queues[queue_idx] = txq;
2537
2538         /* Use a simple TX queue without offloads or multi segs if possible */
2539         i40e_set_tx_function_flag(dev, txq);
2540
2541         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2542                 if (!(vsi->enabled_tc & (1 << i)))
2543                         continue;
2544                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2545                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2546                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2547                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2548                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2549
2550                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2551                         txq->dcb_tc = i;
2552         }
2553
2554         return 0;
2555 }
2556
2557 void
2558 i40e_dev_tx_queue_release(void *txq)
2559 {
2560         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2561
2562         if (!q) {
2563                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2564                 return;
2565         }
2566
2567         i40e_tx_queue_release_mbufs(q);
2568         rte_free(q->sw_ring);
2569         rte_free(q);
2570 }
2571
2572 const struct rte_memzone *
2573 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2574 {
2575         const struct rte_memzone *mz;
2576
2577         mz = rte_memzone_lookup(name);
2578         if (mz)
2579                 return mz;
2580
2581         if (rte_xen_dom0_supported())
2582                 mz = rte_memzone_reserve_bounded(name, len,
2583                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2584         else
2585                 mz = rte_memzone_reserve_aligned(name, len,
2586                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2587         return mz;
2588 }
2589
2590 void
2591 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2592 {
2593         uint16_t i;
2594
2595         /* SSE Vector driver has a different way of releasing mbufs. */
2596         if (rxq->rx_using_sse) {
2597                 i40e_rx_queue_release_mbufs_vec(rxq);
2598                 return;
2599         }
2600
2601         if (!rxq || !rxq->sw_ring) {
2602                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2603                 return;
2604         }
2605
2606         for (i = 0; i < rxq->nb_rx_desc; i++) {
2607                 if (rxq->sw_ring[i].mbuf) {
2608                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2609                         rxq->sw_ring[i].mbuf = NULL;
2610                 }
2611         }
2612 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2613         if (rxq->rx_nb_avail == 0)
2614                 return;
2615         for (i = 0; i < rxq->rx_nb_avail; i++) {
2616                 struct rte_mbuf *mbuf;
2617
2618                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2619                 rte_pktmbuf_free_seg(mbuf);
2620         }
2621         rxq->rx_nb_avail = 0;
2622 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2623 }
2624
2625 void
2626 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2627 {
2628         unsigned i;
2629         uint16_t len;
2630
2631         if (!rxq) {
2632                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2633                 return;
2634         }
2635
2636 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2637         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2638                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2639         else
2640 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2641                 len = rxq->nb_rx_desc;
2642
2643         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2644                 ((volatile char *)rxq->rx_ring)[i] = 0;
2645
2646 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2647         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2648         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2649                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2650
2651         rxq->rx_nb_avail = 0;
2652         rxq->rx_next_avail = 0;
2653         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2654 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2655         rxq->rx_tail = 0;
2656         rxq->nb_rx_hold = 0;
2657         rxq->pkt_first_seg = NULL;
2658         rxq->pkt_last_seg = NULL;
2659
2660         rxq->rxrearm_start = 0;
2661         rxq->rxrearm_nb = 0;
2662 }
2663
2664 void
2665 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2666 {
2667         uint16_t i;
2668
2669         if (!txq || !txq->sw_ring) {
2670                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2671                 return;
2672         }
2673
2674         for (i = 0; i < txq->nb_tx_desc; i++) {
2675                 if (txq->sw_ring[i].mbuf) {
2676                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2677                         txq->sw_ring[i].mbuf = NULL;
2678                 }
2679         }
2680 }
2681
2682 void
2683 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2684 {
2685         struct i40e_tx_entry *txe;
2686         uint16_t i, prev, size;
2687
2688         if (!txq) {
2689                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2690                 return;
2691         }
2692
2693         txe = txq->sw_ring;
2694         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2695         for (i = 0; i < size; i++)
2696                 ((volatile char *)txq->tx_ring)[i] = 0;
2697
2698         prev = (uint16_t)(txq->nb_tx_desc - 1);
2699         for (i = 0; i < txq->nb_tx_desc; i++) {
2700                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2701
2702                 txd->cmd_type_offset_bsz =
2703                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2704                 txe[i].mbuf =  NULL;
2705                 txe[i].last_id = i;
2706                 txe[prev].next_id = i;
2707                 prev = i;
2708         }
2709
2710         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2711         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2712
2713         txq->tx_tail = 0;
2714         txq->nb_tx_used = 0;
2715
2716         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2717         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2718 }
2719
2720 /* Init the TX queue in hardware */
2721 int
2722 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2723 {
2724         enum i40e_status_code err = I40E_SUCCESS;
2725         struct i40e_vsi *vsi = txq->vsi;
2726         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2727         uint16_t pf_q = txq->reg_idx;
2728         struct i40e_hmc_obj_txq tx_ctx;
2729         uint32_t qtx_ctl;
2730
2731         /* clear the context structure first */
2732         memset(&tx_ctx, 0, sizeof(tx_ctx));
2733         tx_ctx.new_context = 1;
2734         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2735         tx_ctx.qlen = txq->nb_tx_desc;
2736
2737 #ifdef RTE_LIBRTE_IEEE1588
2738         tx_ctx.timesync_ena = 1;
2739 #endif
2740         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2741         if (vsi->type == I40E_VSI_FDIR)
2742                 tx_ctx.fd_ena = TRUE;
2743
2744         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2745         if (err != I40E_SUCCESS) {
2746                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2747                 return err;
2748         }
2749
2750         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2751         if (err != I40E_SUCCESS) {
2752                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2753                 return err;
2754         }
2755
2756         /* Now associate this queue with this PCI function */
2757         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2758         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2759                                         I40E_QTX_CTL_PF_INDX_MASK);
2760         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2761         I40E_WRITE_FLUSH(hw);
2762
2763         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2764
2765         return err;
2766 }
2767
2768 int
2769 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2770 {
2771         struct i40e_rx_entry *rxe = rxq->sw_ring;
2772         uint64_t dma_addr;
2773         uint16_t i;
2774
2775         for (i = 0; i < rxq->nb_rx_desc; i++) {
2776                 volatile union i40e_rx_desc *rxd;
2777                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2778
2779                 if (unlikely(!mbuf)) {
2780                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2781                         return -ENOMEM;
2782                 }
2783
2784                 rte_mbuf_refcnt_set(mbuf, 1);
2785                 mbuf->next = NULL;
2786                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2787                 mbuf->nb_segs = 1;
2788                 mbuf->port = rxq->port_id;
2789
2790                 dma_addr =
2791                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2792
2793                 rxd = &rxq->rx_ring[i];
2794                 rxd->read.pkt_addr = dma_addr;
2795                 rxd->read.hdr_addr = 0;
2796 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2797                 rxd->read.rsvd1 = 0;
2798                 rxd->read.rsvd2 = 0;
2799 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2800
2801                 rxe[i].mbuf = mbuf;
2802         }
2803
2804         return 0;
2805 }
2806
2807 /*
2808  * Calculate the buffer length, and check the jumbo frame
2809  * and maximum packet length.
2810  */
2811 static int
2812 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2813 {
2814         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2815         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2816         struct rte_eth_dev_data *data = pf->dev_data;
2817         uint16_t buf_size, len;
2818
2819         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2820                 RTE_PKTMBUF_HEADROOM);
2821
2822         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2823                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2824         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2825                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2826                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2827                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2828                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2829                 rxq->hs_mode = i40e_header_split_enabled;
2830                 break;
2831         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2832         default:
2833                 rxq->rx_hdr_len = 0;
2834                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2835                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2836                 rxq->hs_mode = i40e_header_split_none;
2837                 break;
2838         }
2839
2840         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2841         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2842         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2843                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2844                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2845                         PMD_DRV_LOG(ERR, "maximum packet length must "
2846                                     "be larger than %u and smaller than %u,"
2847                                     "as jumbo frame is enabled",
2848                                     (uint32_t)ETHER_MAX_LEN,
2849                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2850                         return I40E_ERR_CONFIG;
2851                 }
2852         } else {
2853                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2854                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2855                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2856                                     "larger than %u and smaller than %u, "
2857                                     "as jumbo frame is disabled",
2858                                     (uint32_t)ETHER_MIN_LEN,
2859                                     (uint32_t)ETHER_MAX_LEN);
2860                         return I40E_ERR_CONFIG;
2861                 }
2862         }
2863
2864         return 0;
2865 }
2866
2867 /* Init the RX queue in hardware */
2868 int
2869 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2870 {
2871         int err = I40E_SUCCESS;
2872         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2873         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2874         uint16_t pf_q = rxq->reg_idx;
2875         uint16_t buf_size;
2876         struct i40e_hmc_obj_rxq rx_ctx;
2877
2878         err = i40e_rx_queue_config(rxq);
2879         if (err < 0) {
2880                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2881                 return err;
2882         }
2883
2884         /* Clear the context structure first */
2885         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2886         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2887         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2888
2889         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2890         rx_ctx.qlen = rxq->nb_rx_desc;
2891 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2892         rx_ctx.dsize = 1;
2893 #endif
2894         rx_ctx.dtype = rxq->hs_mode;
2895         if (rxq->hs_mode)
2896                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2897         else
2898                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2899         rx_ctx.rxmax = rxq->max_pkt_len;
2900         rx_ctx.tphrdesc_ena = 1;
2901         rx_ctx.tphwdesc_ena = 1;
2902         rx_ctx.tphdata_ena = 1;
2903         rx_ctx.tphhead_ena = 1;
2904         rx_ctx.lrxqthresh = 2;
2905         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2906         rx_ctx.l2tsel = 1;
2907         rx_ctx.showiv = 1;
2908         rx_ctx.prefena = 1;
2909
2910         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2911         if (err != I40E_SUCCESS) {
2912                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2913                 return err;
2914         }
2915         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2916         if (err != I40E_SUCCESS) {
2917                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2918                 return err;
2919         }
2920
2921         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2922
2923         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2924                 RTE_PKTMBUF_HEADROOM);
2925
2926         /* Check if scattered RX needs to be used. */
2927         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2928                 dev_data->scattered_rx = 1;
2929         }
2930
2931         /* Init the RX tail regieter. */
2932         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2933
2934         return 0;
2935 }
2936
2937 void
2938 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2939 {
2940         uint16_t i;
2941
2942         PMD_INIT_FUNC_TRACE();
2943
2944         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2945                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2946                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2947         }
2948
2949         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2950                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2951                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2952         }
2953 }
2954
2955 void
2956 i40e_dev_free_queues(struct rte_eth_dev *dev)
2957 {
2958         uint16_t i;
2959
2960         PMD_INIT_FUNC_TRACE();
2961
2962         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2963                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2964                 dev->data->rx_queues[i] = NULL;
2965         }
2966         dev->data->nb_rx_queues = 0;
2967
2968         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2969                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2970                 dev->data->tx_queues[i] = NULL;
2971         }
2972         dev->data->nb_tx_queues = 0;
2973 }
2974
2975 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2976 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2977
2978 enum i40e_status_code
2979 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2980 {
2981         struct i40e_tx_queue *txq;
2982         const struct rte_memzone *tz = NULL;
2983         uint32_t ring_size;
2984         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2985
2986         if (!pf) {
2987                 PMD_DRV_LOG(ERR, "PF is not available");
2988                 return I40E_ERR_BAD_PTR;
2989         }
2990
2991         /* Allocate the TX queue data structure. */
2992         txq = rte_zmalloc_socket("i40e fdir tx queue",
2993                                   sizeof(struct i40e_tx_queue),
2994                                   RTE_CACHE_LINE_SIZE,
2995                                   SOCKET_ID_ANY);
2996         if (!txq) {
2997                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2998                                         "tx queue structure.");
2999                 return I40E_ERR_NO_MEMORY;
3000         }
3001
3002         /* Allocate TX hardware ring descriptors. */
3003         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
3004         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3005
3006         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
3007                                       I40E_FDIR_QUEUE_ID, ring_size,
3008                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3009         if (!tz) {
3010                 i40e_dev_tx_queue_release(txq);
3011                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
3012                 return I40E_ERR_NO_MEMORY;
3013         }
3014
3015         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
3016         txq->queue_id = I40E_FDIR_QUEUE_ID;
3017         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3018         txq->vsi = pf->fdir.fdir_vsi;
3019
3020         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
3021         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
3022         /*
3023          * don't need to allocate software ring and reset for the fdir
3024          * program queue just set the queue has been configured.
3025          */
3026         txq->q_set = TRUE;
3027         pf->fdir.txq = txq;
3028
3029         return I40E_SUCCESS;
3030 }
3031
3032 enum i40e_status_code
3033 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
3034 {
3035         struct i40e_rx_queue *rxq;
3036         const struct rte_memzone *rz = NULL;
3037         uint32_t ring_size;
3038         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3039
3040         if (!pf) {
3041                 PMD_DRV_LOG(ERR, "PF is not available");
3042                 return I40E_ERR_BAD_PTR;
3043         }
3044
3045         /* Allocate the RX queue data structure. */
3046         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3047                                   sizeof(struct i40e_rx_queue),
3048                                   RTE_CACHE_LINE_SIZE,
3049                                   SOCKET_ID_ANY);
3050         if (!rxq) {
3051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3052                                         "rx queue structure.");
3053                 return I40E_ERR_NO_MEMORY;
3054         }
3055
3056         /* Allocate RX hardware ring descriptors. */
3057         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3058         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3059
3060         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3061                                       I40E_FDIR_QUEUE_ID, ring_size,
3062                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3063         if (!rz) {
3064                 i40e_dev_rx_queue_release(rxq);
3065                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3066                 return I40E_ERR_NO_MEMORY;
3067         }
3068
3069         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3070         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3071         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3072         rxq->vsi = pf->fdir.fdir_vsi;
3073
3074         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3075         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3076
3077         /*
3078          * Don't need to allocate software ring and reset for the fdir
3079          * rx queue, just set the queue has been configured.
3080          */
3081         rxq->q_set = TRUE;
3082         pf->fdir.rxq = rxq;
3083
3084         return I40E_SUCCESS;
3085 }
3086
3087 void
3088 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3089         struct rte_eth_rxq_info *qinfo)
3090 {
3091         struct i40e_rx_queue *rxq;
3092
3093         rxq = dev->data->rx_queues[queue_id];
3094
3095         qinfo->mp = rxq->mp;
3096         qinfo->scattered_rx = dev->data->scattered_rx;
3097         qinfo->nb_desc = rxq->nb_rx_desc;
3098
3099         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3100         qinfo->conf.rx_drop_en = rxq->drop_en;
3101         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3102 }
3103
3104 void
3105 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3106         struct rte_eth_txq_info *qinfo)
3107 {
3108         struct i40e_tx_queue *txq;
3109
3110         txq = dev->data->tx_queues[queue_id];
3111
3112         qinfo->nb_desc = txq->nb_tx_desc;
3113
3114         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3115         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3116         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3117
3118         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3119         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3120         qinfo->conf.txq_flags = txq->txq_flags;
3121         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3122 }
3123
3124 void __attribute__((cold))
3125 i40e_set_rx_function(struct rte_eth_dev *dev)
3126 {
3127         struct i40e_adapter *ad =
3128                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3129         uint16_t rx_using_sse, i;
3130         /* In order to allow Vector Rx there are a few configuration
3131          * conditions to be met and Rx Bulk Allocation should be allowed.
3132          */
3133         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3134                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3135                     !ad->rx_bulk_alloc_allowed) {
3136                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3137                                      " Vector Rx preconditions",
3138                                      dev->data->port_id);
3139
3140                         ad->rx_vec_allowed = false;
3141                 }
3142                 if (ad->rx_vec_allowed) {
3143                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3144                                 struct i40e_rx_queue *rxq =
3145                                         dev->data->rx_queues[i];
3146
3147                                 if (i40e_rxq_vec_setup(rxq)) {
3148                                         ad->rx_vec_allowed = false;
3149                                         break;
3150                                 }
3151                         }
3152                 }
3153         }
3154
3155         if (dev->data->scattered_rx) {
3156                 /* Set the non-LRO scattered callback: there are Vector and
3157                  * single allocation versions.
3158                  */
3159                 if (ad->rx_vec_allowed) {
3160                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3161                                             "callback (port=%d).",
3162                                      dev->data->port_id);
3163
3164                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3165                 } else {
3166                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3167                                            "allocation callback (port=%d).",
3168                                      dev->data->port_id);
3169                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3170                 }
3171         /* If parameters allow we are going to choose between the following
3172          * callbacks:
3173          *    - Vector
3174          *    - Bulk Allocation
3175          *    - Single buffer allocation (the simplest one)
3176          */
3177         } else if (ad->rx_vec_allowed) {
3178                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3179                                     "burst size no less than %d (port=%d).",
3180                              RTE_I40E_DESCS_PER_LOOP,
3181                              dev->data->port_id);
3182
3183                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3184         } else if (ad->rx_bulk_alloc_allowed) {
3185                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3186                                     "satisfied. Rx Burst Bulk Alloc function "
3187                                     "will be used on port=%d.",
3188                              dev->data->port_id);
3189
3190                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3191         } else {
3192                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3193                                     "satisfied, or Scattered Rx is requested "
3194                                     "(port=%d).",
3195                              dev->data->port_id);
3196
3197                 dev->rx_pkt_burst = i40e_recv_pkts;
3198         }
3199
3200         /* Propagate information about RX function choice through all queues. */
3201         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3202                 rx_using_sse =
3203                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3204                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3205
3206                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3207                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3208
3209                         rxq->rx_using_sse = rx_using_sse;
3210                 }
3211         }
3212 }
3213
3214 void __attribute__((cold))
3215 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3216 {
3217         struct i40e_adapter *ad =
3218                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3219
3220         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3221         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3222                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3223                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3224                         PMD_INIT_LOG(DEBUG, "Vector tx"
3225                                      " can be enabled on this txq.");
3226
3227                 } else {
3228                         ad->tx_vec_allowed = false;
3229                 }
3230         } else {
3231                 ad->tx_simple_allowed = false;
3232         }
3233 }
3234
3235 void __attribute__((cold))
3236 i40e_set_tx_function(struct rte_eth_dev *dev)
3237 {
3238         struct i40e_adapter *ad =
3239                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3240         int i;
3241
3242         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3243                 if (ad->tx_vec_allowed) {
3244                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3245                                 struct i40e_tx_queue *txq =
3246                                         dev->data->tx_queues[i];
3247
3248                                 if (i40e_txq_vec_setup(txq)) {
3249                                         ad->tx_vec_allowed = false;
3250                                         break;
3251                                 }
3252                         }
3253                 }
3254         }
3255
3256         if (ad->tx_simple_allowed) {
3257                 if (ad->tx_vec_allowed) {
3258                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3259                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3260                 } else {
3261                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3262                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3263                 }
3264         } else {
3265                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3266                 dev->tx_pkt_burst = i40e_xmit_pkts;
3267         }
3268 }
3269
3270 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3271 int __attribute__((weak))
3272 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3273 {
3274         return -1;
3275 }
3276
3277 uint16_t __attribute__((weak))
3278 i40e_recv_pkts_vec(
3279         void __rte_unused *rx_queue,
3280         struct rte_mbuf __rte_unused **rx_pkts,
3281         uint16_t __rte_unused nb_pkts)
3282 {
3283         return 0;
3284 }
3285
3286 uint16_t __attribute__((weak))
3287 i40e_recv_scattered_pkts_vec(
3288         void __rte_unused *rx_queue,
3289         struct rte_mbuf __rte_unused **rx_pkts,
3290         uint16_t __rte_unused nb_pkts)
3291 {
3292         return 0;
3293 }
3294
3295 int __attribute__((weak))
3296 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3297 {
3298         return -1;
3299 }
3300
3301 int __attribute__((weak))
3302 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3303 {
3304         return -1;
3305 }
3306
3307 void __attribute__((weak))
3308 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3309 {
3310         return;
3311 }
3312
3313 uint16_t __attribute__((weak))
3314 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3315                    struct rte_mbuf __rte_unused **tx_pkts,
3316                    uint16_t __rte_unused nb_pkts)
3317 {
3318         return 0;
3319 }