drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_TCP_SEG |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  83                                       struct rte_mbuf **tx_pkts,
  84                                       uint16_t nb_pkts);
  85
  86 static inline void
  87 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  88 {
  89         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  90                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  91                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
  92                 mb->vlan_tci =
  93                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  96         } else {
  97                 mb->vlan_tci = 0;
  98         }
  99 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 100         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 101                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 103                 mb->vlan_tci_outer = mb->vlan_tci;
 104                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 107                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 108         } else {
 109                 mb->vlan_tci_outer = 0;
 110         }
 111 #endif
 112         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 113                    mb->vlan_tci, mb->vlan_tci_outer);
 114 }
 115
 116 /* Translate the rx descriptor status to pkt flags */
 117 static inline uint64_t
 118 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 119 {
 120         uint64_t flags;
 121
 122         /* Check if RSS_HASH */
 123         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 124                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 125                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 126
 127         /* Check if FDIR Match */
 128         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 129                                                         PKT_RX_FDIR : 0);
 130
 131         return flags;
 132 }
 133
 134 static inline uint64_t
 135 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 136 {
 137         uint64_t flags = 0;
 138         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 139
 140 #define I40E_RX_ERR_BITS 0x3f
 141         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 142                 return flags;
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 144                 flags |= PKT_RX_IP_CKSUM_BAD;
 145         else
 146                 flags |= PKT_RX_IP_CKSUM_GOOD;
 147
 148         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 149                 flags |= PKT_RX_L4_CKSUM_BAD;
 150         else
 151                 flags |= PKT_RX_L4_CKSUM_GOOD;
 152
 153         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 154                 flags |= PKT_RX_EIP_CKSUM_BAD;
 155
 156         return flags;
 157 }
 158
 159 /* Function to check and set the ieee1588 timesync index and get the
 160  * appropriate flags.
 161  */
 162 #ifdef RTE_LIBRTE_IEEE1588
 163 static inline uint64_t
 164 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 165 {
 166         uint64_t pkt_flags = 0;
 167         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 168                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 169                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 170
 171         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 172                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 173                 pkt_flags = PKT_RX_IEEE1588_PTP;
 174         if (tsyn & 0x04) {
 175                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 176                 mb->timesync = tsyn & 0x03;
 177         }
 178
 179         return pkt_flags;
 180 }
 181 #endif
 182
 183 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 184 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 185 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 186 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 187 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 188
 189 static inline uint64_t
 190 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 191 {
 192         uint64_t flags = 0;
 193 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 194         uint16_t flexbh, flexbl;
 195
 196         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 197                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 198                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 199         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 200                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 201                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 202
 203
 204         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 205                 mb->hash.fdir.hi =
 206                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 207                 flags |= PKT_RX_FDIR_ID;
 208         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 209                 mb->hash.fdir.hi =
 210                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 211                 flags |= PKT_RX_FDIR_FLX;
 212         }
 213         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 214                 mb->hash.fdir.lo =
 215                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 216                 flags |= PKT_RX_FDIR_FLX;
 217         }
 218 #else
 219         mb->hash.fdir.hi =
 220                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 221         flags |= PKT_RX_FDIR_ID;
 222 #endif
 223         return flags;
 224 }
 225
 226 static inline void
 227 i40e_parse_tunneling_params(uint64_t ol_flags,
 228                             union i40e_tx_offload tx_offload,
 229                             uint32_t *cd_tunneling)
 230 {
 231         /* EIPT: External (outer) IP header type */
 232         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 233                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 234         else if (ol_flags & PKT_TX_OUTER_IPV4)
 235                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 236         else if (ol_flags & PKT_TX_OUTER_IPV6)
 237                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 238
 239         /* EIPLEN: External (outer) IP header length, in DWords */
 240         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 241                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 242
 243         /* L4TUNT: L4 Tunneling Type */
 244         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 245         case PKT_TX_TUNNEL_IPIP:
 246                 /* for non UDP / GRE tunneling, set to 00b */
 247                 break;
 248         case PKT_TX_TUNNEL_VXLAN:
 249         case PKT_TX_TUNNEL_GENEVE:
 250                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 251                 break;
 252         case PKT_TX_TUNNEL_GRE:
 253                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 254                 break;
 255         default:
 256                 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
 257                 return;
 258         }
 259
 260         /* L4TUNLEN: L4 Tunneling Length, in Words
 261          *
 262          * We depend on app to set rte_mbuf.l2_len correctly.
 263          * For IP in GRE it should be set to the length of the GRE
 264          * header;
 265          * for MAC in GRE or MAC in UDP it should be set to the length
 266          * of the GRE or UDP headers plus the inner MAC up to including
 267          * its last Ethertype.
 268          */
 269         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 270                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 271 }
 272
 273 static inline void
 274 i40e_txd_enable_checksum(uint64_t ol_flags,
 275                         uint32_t *td_cmd,
 276                         uint32_t *td_offset,
 277                         union i40e_tx_offload tx_offload)
 278 {
 279         /* Set MACLEN */
 280         if (ol_flags & PKT_TX_TUNNEL_MASK)
 281                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 282                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 283         else
 284                 *td_offset |= (tx_offload.l2_len >> 1)
 285                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 286
 287         /* Enable L3 checksum offloads */
 288         if (ol_flags & PKT_TX_IP_CKSUM) {
 289                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 290                 *td_offset |= (tx_offload.l3_len >> 2)
 291                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 292         } else if (ol_flags & PKT_TX_IPV4) {
 293                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 294                 *td_offset |= (tx_offload.l3_len >> 2)
 295                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 296         } else if (ol_flags & PKT_TX_IPV6) {
 297                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 298                 *td_offset |= (tx_offload.l3_len >> 2)
 299                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 300         }
 301
 302         if (ol_flags & PKT_TX_TCP_SEG) {
 303                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 304                 *td_offset |= (tx_offload.l4_len >> 2)
 305                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 306                 return;
 307         }
 308
 309         /* Enable L4 checksum offloads */
 310         switch (ol_flags & PKT_TX_L4_MASK) {
 311         case PKT_TX_TCP_CKSUM:
 312                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 313                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 314                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 315                 break;
 316         case PKT_TX_SCTP_CKSUM:
 317                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 318                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 319                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 320                 break;
 321         case PKT_TX_UDP_CKSUM:
 322                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 323                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 324                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 325                 break;
 326         default:
 327                 break;
 328         }
 329 }
 330
 331 /* Construct the tx flags */
 332 static inline uint64_t
 333 i40e_build_ctob(uint32_t td_cmd,
 334                 uint32_t td_offset,
 335                 unsigned int size,
 336                 uint32_t td_tag)
 337 {
 338         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 339                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 340                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 341                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 342                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 343 }
 344
 345 static inline int
 346 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 347 {
 348         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 349         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 350         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 351         uint16_t nb_tx_desc = txq->nb_tx_desc;
 352         uint16_t desc_to_clean_to;
 353         uint16_t nb_tx_to_clean;
 354
 355         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 356         if (desc_to_clean_to >= nb_tx_desc)
 357                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 358
 359         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 360         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 361                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 362                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 363                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 364                         "(port=%d queue=%d)", desc_to_clean_to,
 365                                 txq->port_id, txq->queue_id);
 366                 return -1;
 367         }
 368
 369         if (last_desc_cleaned > desc_to_clean_to)
 370                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 371                                                         desc_to_clean_to);
 372         else
 373                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 374                                         last_desc_cleaned);
 375
 376         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 377
 378         txq->last_desc_cleaned = desc_to_clean_to;
 379         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 380
 381         return 0;
 382 }
 383
 384 static inline int
 385 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 386 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 387 #else
 388 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 389 #endif
 390 {
 391         int ret = 0;
 392
 393 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 394         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 395                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 396                              "rxq->rx_free_thresh=%d, "
 397                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 398                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 399                 ret = -EINVAL;
 400         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 401                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 402                              "rxq->rx_free_thresh=%d, "
 403                              "rxq->nb_rx_desc=%d",
 404                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 405                 ret = -EINVAL;
 406         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 407                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 408                              "rxq->nb_rx_desc=%d, "
 409                              "rxq->rx_free_thresh=%d",
 410                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 411                 ret = -EINVAL;
 412         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 413                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 414                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 415                              "rxq->nb_rx_desc=%d, "
 416                              "I40E_MAX_RING_DESC=%d, "
 417                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 418                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 419                              RTE_PMD_I40E_RX_MAX_BURST);
 420                 ret = -EINVAL;
 421         }
 422 #else
 423         ret = -EINVAL;
 424 #endif
 425
 426         return ret;
 427 }
 428
 429 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 430 #define I40E_LOOK_AHEAD 8
 431 #if (I40E_LOOK_AHEAD != 8)
 432 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 433 #endif
 434 static inline int
 435 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 436 {
 437         volatile union i40e_rx_desc *rxdp;
 438         struct i40e_rx_entry *rxep;
 439         struct rte_mbuf *mb;
 440         uint16_t pkt_len;
 441         uint64_t qword1;
 442         uint32_t rx_status;
 443         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 444         int32_t i, j, nb_rx = 0;
 445         uint64_t pkt_flags;
 446
 447         rxdp = &rxq->rx_ring[rxq->rx_tail];
 448         rxep = &rxq->sw_ring[rxq->rx_tail];
 449
 450         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 451         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 452                                 I40E_RXD_QW1_STATUS_SHIFT;
 453
 454         /* Make sure there is at least 1 packet to receive */
 455         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 456                 return 0;
 457
 458         /**
 459          * Scan LOOK_AHEAD descriptors at a time to determine which
 460          * descriptors reference packets that are ready to be received.
 461          */
 462         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 463                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 464                 /* Read desc statuses backwards to avoid race condition */
 465                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 466                         qword1 = rte_le_to_cpu_64(\
 467                                 rxdp[j].wb.qword1.status_error_len);
 468                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 469                                         I40E_RXD_QW1_STATUS_SHIFT;
 470                 }
 471
 472                 rte_smp_rmb();
 473
 474                 /* Compute how many status bits were set */
 475                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 476                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 477
 478                 nb_rx += nb_dd;
 479
 480                 /* Translate descriptor info to mbuf parameters */
 481                 for (j = 0; j < nb_dd; j++) {
 482                         mb = rxep[j].mbuf;
 483                         qword1 = rte_le_to_cpu_64(\
 484                                 rxdp[j].wb.qword1.status_error_len);
 485                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 486                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 487                         mb->data_len = pkt_len;
 488                         mb->pkt_len = pkt_len;
 489                         mb->ol_flags = 0;
 490                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 491                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 492                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 493                         mb->packet_type =
 494                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 495                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 496                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 497                         if (pkt_flags & PKT_RX_RSS_HASH)
 498                                 mb->hash.rss = rte_le_to_cpu_32(\
 499                                         rxdp[j].wb.qword0.hi_dword.rss);
 500                         if (pkt_flags & PKT_RX_FDIR)
 501                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 502
 503 #ifdef RTE_LIBRTE_IEEE1588
 504                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 505 #endif
 506                         mb->ol_flags |= pkt_flags;
 507
 508                 }
 509
 510                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 511                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 512
 513                 if (nb_dd != I40E_LOOK_AHEAD)
 514                         break;
 515         }
 516
 517         /* Clear software ring entries */
 518         for (i = 0; i < nb_rx; i++)
 519                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 520
 521         return nb_rx;
 522 }
 523
 524 static inline uint16_t
 525 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 526                         struct rte_mbuf **rx_pkts,
 527                         uint16_t nb_pkts)
 528 {
 529         uint16_t i;
 530         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 531
 532         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 533
 534         for (i = 0; i < nb_pkts; i++)
 535                 rx_pkts[i] = stage[i];
 536
 537         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 538         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 539
 540         return nb_pkts;
 541 }
 542
 543 static inline int
 544 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 545 {
 546         volatile union i40e_rx_desc *rxdp;
 547         struct i40e_rx_entry *rxep;
 548         struct rte_mbuf *mb;
 549         uint16_t alloc_idx, i;
 550         uint64_t dma_addr;
 551         int diag;
 552
 553         /* Allocate buffers in bulk */
 554         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 555                                 (rxq->rx_free_thresh - 1));
 556         rxep = &(rxq->sw_ring[alloc_idx]);
 557         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 558                                         rxq->rx_free_thresh);
 559         if (unlikely(diag != 0)) {
 560                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 561                 return -ENOMEM;
 562         }
 563
 564         rxdp = &rxq->rx_ring[alloc_idx];
 565         for (i = 0; i < rxq->rx_free_thresh; i++) {
 566                 if (likely(i < (rxq->rx_free_thresh - 1)))
 567                         /* Prefetch next mbuf */
 568                         rte_prefetch0(rxep[i + 1].mbuf);
 569
 570                 mb = rxep[i].mbuf;
 571                 rte_mbuf_refcnt_set(mb, 1);
 572                 mb->next = NULL;
 573                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 574                 mb->nb_segs = 1;
 575                 mb->port = rxq->port_id;
 576                 dma_addr = rte_cpu_to_le_64(\
 577                         rte_mbuf_data_dma_addr_default(mb));
 578                 rxdp[i].read.hdr_addr = 0;
 579                 rxdp[i].read.pkt_addr = dma_addr;
 580         }
 581
 582         /* Update rx tail regsiter */
 583         rte_wmb();
 584         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 585
 586         rxq->rx_free_trigger =
 587                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 588         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 589                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 590
 591         return 0;
 592 }
 593
 594 static inline uint16_t
 595 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 596 {
 597         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 598         uint16_t nb_rx = 0;
 599
 600         if (!nb_pkts)
 601                 return 0;
 602
 603         if (rxq->rx_nb_avail)
 604                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 605
 606         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 607         rxq->rx_next_avail = 0;
 608         rxq->rx_nb_avail = nb_rx;
 609         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 610
 611         if (rxq->rx_tail > rxq->rx_free_trigger) {
 612                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 613                         uint16_t i, j;
 614
 615                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 616                                    "port_id=%u, queue_id=%u",
 617                                    rxq->port_id, rxq->queue_id);
 618                         rxq->rx_nb_avail = 0;
 619                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 620                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 621                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 622
 623                         return 0;
 624                 }
 625         }
 626
 627         if (rxq->rx_tail >= rxq->nb_rx_desc)
 628                 rxq->rx_tail = 0;
 629
 630         if (rxq->rx_nb_avail)
 631                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 632
 633         return 0;
 634 }
 635
 636 static uint16_t
 637 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 638                           struct rte_mbuf **rx_pkts,
 639                           uint16_t nb_pkts)
 640 {
 641         uint16_t nb_rx = 0, n, count;
 642
 643         if (unlikely(nb_pkts == 0))
 644                 return 0;
 645
 646         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 647                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 648
 649         while (nb_pkts) {
 650                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 651                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 652                 nb_rx = (uint16_t)(nb_rx + count);
 653                 nb_pkts = (uint16_t)(nb_pkts - count);
 654                 if (count < n)
 655                         break;
 656         }
 657
 658         return nb_rx;
 659 }
 660 #else
 661 static uint16_t
 662 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 663                           struct rte_mbuf __rte_unused **rx_pkts,
 664                           uint16_t __rte_unused nb_pkts)
 665 {
 666         return 0;
 667 }
 668 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 669
 670 uint16_t
 671 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 672 {
 673         struct i40e_rx_queue *rxq;
 674         volatile union i40e_rx_desc *rx_ring;
 675         volatile union i40e_rx_desc *rxdp;
 676         union i40e_rx_desc rxd;
 677         struct i40e_rx_entry *sw_ring;
 678         struct i40e_rx_entry *rxe;
 679         struct rte_mbuf *rxm;
 680         struct rte_mbuf *nmb;
 681         uint16_t nb_rx;
 682         uint32_t rx_status;
 683         uint64_t qword1;
 684         uint16_t rx_packet_len;
 685         uint16_t rx_id, nb_hold;
 686         uint64_t dma_addr;
 687         uint64_t pkt_flags;
 688
 689         nb_rx = 0;
 690         nb_hold = 0;
 691         rxq = rx_queue;
 692         rx_id = rxq->rx_tail;
 693         rx_ring = rxq->rx_ring;
 694         sw_ring = rxq->sw_ring;
 695
 696         while (nb_rx < nb_pkts) {
 697                 rxdp = &rx_ring[rx_id];
 698                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 699                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 700                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 701
 702                 /* Check the DD bit first */
 703                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 704                         break;
 705
 706                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 707                 if (unlikely(!nmb))
 708                         break;
 709                 rxd = *rxdp;
 710
 711                 nb_hold++;
 712                 rxe = &sw_ring[rx_id];
 713                 rx_id++;
 714                 if (unlikely(rx_id == rxq->nb_rx_desc))
 715                         rx_id = 0;
 716
 717                 /* Prefetch next mbuf */
 718                 rte_prefetch0(sw_ring[rx_id].mbuf);
 719
 720                 /**
 721                  * When next RX descriptor is on a cache line boundary,
 722                  * prefetch the next 4 RX descriptors and next 8 pointers
 723                  * to mbufs.
 724                  */
 725                 if ((rx_id & 0x3) == 0) {
 726                         rte_prefetch0(&rx_ring[rx_id]);
 727                         rte_prefetch0(&sw_ring[rx_id]);
 728                 }
 729                 rxm = rxe->mbuf;
 730                 rxe->mbuf = nmb;
 731                 dma_addr =
 732                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 733                 rxdp->read.hdr_addr = 0;
 734                 rxdp->read.pkt_addr = dma_addr;
 735
 736                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 737                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 738
 739                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 740                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 741                 rxm->nb_segs = 1;
 742                 rxm->next = NULL;
 743                 rxm->pkt_len = rx_packet_len;
 744                 rxm->data_len = rx_packet_len;
 745                 rxm->port = rxq->port_id;
 746                 rxm->ol_flags = 0;
 747                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 748                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 749                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 750                 rxm->packet_type =
 751                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 752                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 753                 if (pkt_flags & PKT_RX_RSS_HASH)
 754                         rxm->hash.rss =
 755                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 756                 if (pkt_flags & PKT_RX_FDIR)
 757                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 758
 759 #ifdef RTE_LIBRTE_IEEE1588
 760                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 761 #endif
 762                 rxm->ol_flags |= pkt_flags;
 763
 764                 rx_pkts[nb_rx++] = rxm;
 765         }
 766         rxq->rx_tail = rx_id;
 767
 768         /**
 769          * If the number of free RX descriptors is greater than the RX free
 770          * threshold of the queue, advance the receive tail register of queue.
 771          * Update that register with the value of the last processed RX
 772          * descriptor minus 1.
 773          */
 774         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 775         if (nb_hold > rxq->rx_free_thresh) {
 776                 rx_id = (uint16_t) ((rx_id == 0) ?
 777                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 778                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 779                 nb_hold = 0;
 780         }
 781         rxq->nb_rx_hold = nb_hold;
 782
 783         return nb_rx;
 784 }
 785
 786 uint16_t
 787 i40e_recv_scattered_pkts(void *rx_queue,
 788                          struct rte_mbuf **rx_pkts,
 789                          uint16_t nb_pkts)
 790 {
 791         struct i40e_rx_queue *rxq = rx_queue;
 792         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 793         volatile union i40e_rx_desc *rxdp;
 794         union i40e_rx_desc rxd;
 795         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 796         struct i40e_rx_entry *rxe;
 797         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 798         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 799         struct rte_mbuf *nmb, *rxm;
 800         uint16_t rx_id = rxq->rx_tail;
 801         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 802         uint32_t rx_status;
 803         uint64_t qword1;
 804         uint64_t dma_addr;
 805         uint64_t pkt_flags;
 806
 807         while (nb_rx < nb_pkts) {
 808                 rxdp = &rx_ring[rx_id];
 809                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 810                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 811                                         I40E_RXD_QW1_STATUS_SHIFT;
 812
 813                 /* Check the DD bit */
 814                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 815                         break;
 816
 817                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 818                 if (unlikely(!nmb))
 819                         break;
 820                 rxd = *rxdp;
 821                 nb_hold++;
 822                 rxe = &sw_ring[rx_id];
 823                 rx_id++;
 824                 if (rx_id == rxq->nb_rx_desc)
 825                         rx_id = 0;
 826
 827                 /* Prefetch next mbuf */
 828                 rte_prefetch0(sw_ring[rx_id].mbuf);
 829
 830                 /**
 831                  * When next RX descriptor is on a cache line boundary,
 832                  * prefetch the next 4 RX descriptors and next 8 pointers
 833                  * to mbufs.
 834                  */
 835                 if ((rx_id & 0x3) == 0) {
 836                         rte_prefetch0(&rx_ring[rx_id]);
 837                         rte_prefetch0(&sw_ring[rx_id]);
 838                 }
 839
 840                 rxm = rxe->mbuf;
 841                 rxe->mbuf = nmb;
 842                 dma_addr =
 843                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 844
 845                 /* Set data buffer address and data length of the mbuf */
 846                 rxdp->read.hdr_addr = 0;
 847                 rxdp->read.pkt_addr = dma_addr;
 848                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 849                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 850                 rxm->data_len = rx_packet_len;
 851                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 852
 853                 /**
 854                  * If this is the first buffer of the received packet, set the
 855                  * pointer to the first mbuf of the packet and initialize its
 856                  * context. Otherwise, update the total length and the number
 857                  * of segments of the current scattered packet, and update the
 858                  * pointer to the last mbuf of the current packet.
 859                  */
 860                 if (!first_seg) {
 861                         first_seg = rxm;
 862                         first_seg->nb_segs = 1;
 863                         first_seg->pkt_len = rx_packet_len;
 864                 } else {
 865                         first_seg->pkt_len =
 866                                 (uint16_t)(first_seg->pkt_len +
 867                                                 rx_packet_len);
 868                         first_seg->nb_segs++;
 869                         last_seg->next = rxm;
 870                 }
 871
 872                 /**
 873                  * If this is not the last buffer of the received packet,
 874                  * update the pointer to the last mbuf of the current scattered
 875                  * packet and continue to parse the RX ring.
 876                  */
 877                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 878                         last_seg = rxm;
 879                         continue;
 880                 }
 881
 882                 /**
 883                  * This is the last buffer of the received packet. If the CRC
 884                  * is not stripped by the hardware:
 885                  *  - Subtract the CRC length from the total packet length.
 886                  *  - If the last buffer only contains the whole CRC or a part
 887                  *  of it, free the mbuf associated to the last buffer. If part
 888                  *  of the CRC is also contained in the previous mbuf, subtract
 889                  *  the length of that CRC part from the data length of the
 890                  *  previous mbuf.
 891                  */
 892                 rxm->next = NULL;
 893                 if (unlikely(rxq->crc_len > 0)) {
 894                         first_seg->pkt_len -= ETHER_CRC_LEN;
 895                         if (rx_packet_len <= ETHER_CRC_LEN) {
 896                                 rte_pktmbuf_free_seg(rxm);
 897                                 first_seg->nb_segs--;
 898                                 last_seg->data_len =
 899                                         (uint16_t)(last_seg->data_len -
 900                                         (ETHER_CRC_LEN - rx_packet_len));
 901                                 last_seg->next = NULL;
 902                         } else
 903                                 rxm->data_len = (uint16_t)(rx_packet_len -
 904                                                                 ETHER_CRC_LEN);
 905                 }
 906
 907                 first_seg->port = rxq->port_id;
 908                 first_seg->ol_flags = 0;
 909                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 910                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 911                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 912                 first_seg->packet_type =
 913                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 914                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 915                 if (pkt_flags & PKT_RX_RSS_HASH)
 916                         first_seg->hash.rss =
 917                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 918                 if (pkt_flags & PKT_RX_FDIR)
 919                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 920
 921 #ifdef RTE_LIBRTE_IEEE1588
 922                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 923 #endif
 924                 first_seg->ol_flags |= pkt_flags;
 925
 926                 /* Prefetch data of first segment, if configured to do so. */
 927                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 928                         first_seg->data_off));
 929                 rx_pkts[nb_rx++] = first_seg;
 930                 first_seg = NULL;
 931         }
 932
 933         /* Record index of the next RX descriptor to probe. */
 934         rxq->rx_tail = rx_id;
 935         rxq->pkt_first_seg = first_seg;
 936         rxq->pkt_last_seg = last_seg;
 937
 938         /**
 939          * If the number of free RX descriptors is greater than the RX free
 940          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 941          * register. Update the RDT with the value of the last processed RX
 942          * descriptor minus 1, to guarantee that the RDT register is never
 943          * equal to the RDH register, which creates a "full" ring situtation
 944          * from the hardware point of view.
 945          */
 946         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 947         if (nb_hold > rxq->rx_free_thresh) {
 948                 rx_id = (uint16_t)(rx_id == 0 ?
 949                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 950                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 951                 nb_hold = 0;
 952         }
 953         rxq->nb_rx_hold = nb_hold;
 954
 955         return nb_rx;
 956 }
 957
 958 /* Check if the context descriptor is needed for TX offloading */
 959 static inline uint16_t
 960 i40e_calc_context_desc(uint64_t flags)
 961 {
 962         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 963                 PKT_TX_TCP_SEG |
 964                 PKT_TX_QINQ_PKT |
 965                 PKT_TX_TUNNEL_MASK;
 966
 967 #ifdef RTE_LIBRTE_IEEE1588
 968         mask |= PKT_TX_IEEE1588_TMST;
 969 #endif
 970
 971         return (flags & mask) ? 1 : 0;
 972 }
 973
 974 /* set i40e TSO context descriptor */
 975 static inline uint64_t
 976 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 977 {
 978         uint64_t ctx_desc = 0;
 979         uint32_t cd_cmd, hdr_len, cd_tso_len;
 980
 981         if (!tx_offload.l4_len) {
 982                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 983                 return ctx_desc;
 984         }
 985
 986         /**
 987          * in case of non tunneling packet, the outer_l2_len and
 988          * outer_l3_len must be 0.
 989          */
 990         hdr_len = tx_offload.outer_l2_len +
 991                 tx_offload.outer_l3_len +
 992                 tx_offload.l2_len +
 993                 tx_offload.l3_len +
 994                 tx_offload.l4_len;
 995
 996         cd_cmd = I40E_TX_CTX_DESC_TSO;
 997         cd_tso_len = mbuf->pkt_len - hdr_len;
 998         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 999                 ((uint64_t)cd_tso_len <<
1000                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1001                 ((uint64_t)mbuf->tso_segsz <<
1002                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1003
1004         return ctx_desc;
1005 }
1006
1007 uint16_t
1008 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1009 {
1010         struct i40e_tx_queue *txq;
1011         struct i40e_tx_entry *sw_ring;
1012         struct i40e_tx_entry *txe, *txn;
1013         volatile struct i40e_tx_desc *txd;
1014         volatile struct i40e_tx_desc *txr;
1015         struct rte_mbuf *tx_pkt;
1016         struct rte_mbuf *m_seg;
1017         uint32_t cd_tunneling_params;
1018         uint16_t tx_id;
1019         uint16_t nb_tx;
1020         uint32_t td_cmd;
1021         uint32_t td_offset;
1022         uint32_t tx_flags;
1023         uint32_t td_tag;
1024         uint64_t ol_flags;
1025         uint16_t nb_used;
1026         uint16_t nb_ctx;
1027         uint16_t tx_last;
1028         uint16_t slen;
1029         uint64_t buf_dma_addr;
1030         union i40e_tx_offload tx_offload = {0};
1031
1032         txq = tx_queue;
1033         sw_ring = txq->sw_ring;
1034         txr = txq->tx_ring;
1035         tx_id = txq->tx_tail;
1036         txe = &sw_ring[tx_id];
1037
1038         /* Check if the descriptor ring needs to be cleaned. */
1039         if (txq->nb_tx_free < txq->tx_free_thresh)
1040                 i40e_xmit_cleanup(txq);
1041
1042         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1043                 td_cmd = 0;
1044                 td_tag = 0;
1045                 td_offset = 0;
1046                 tx_flags = 0;
1047
1048                 tx_pkt = *tx_pkts++;
1049                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1050
1051                 ol_flags = tx_pkt->ol_flags;
1052                 tx_offload.l2_len = tx_pkt->l2_len;
1053                 tx_offload.l3_len = tx_pkt->l3_len;
1054                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1055                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1056                 tx_offload.l4_len = tx_pkt->l4_len;
1057                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1058
1059                 /* Calculate the number of context descriptors needed. */
1060                 nb_ctx = i40e_calc_context_desc(ol_flags);
1061
1062                 /**
1063                  * The number of descriptors that must be allocated for
1064                  * a packet equals to the number of the segments of that
1065                  * packet plus 1 context descriptor if needed.
1066                  */
1067                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1068                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1069
1070                 /* Circular ring */
1071                 if (tx_last >= txq->nb_tx_desc)
1072                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1073
1074                 if (nb_used > txq->nb_tx_free) {
1075                         if (i40e_xmit_cleanup(txq) != 0) {
1076                                 if (nb_tx == 0)
1077                                         return 0;
1078                                 goto end_of_tx;
1079                         }
1080                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1081                                 while (nb_used > txq->nb_tx_free) {
1082                                         if (i40e_xmit_cleanup(txq) != 0) {
1083                                                 if (nb_tx == 0)
1084                                                         return 0;
1085                                                 goto end_of_tx;
1086                                         }
1087                                 }
1088                         }
1089                 }
1090
1091                 /* Descriptor based VLAN insertion */
1092                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1093                         tx_flags |= tx_pkt->vlan_tci <<
1094                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1095                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1096                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1097                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1098                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1099                 }
1100
1101                 /* Always enable CRC offload insertion */
1102                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1103
1104                 /* Fill in tunneling parameters if necessary */
1105                 cd_tunneling_params = 0;
1106                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1107                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1108                                                     &cd_tunneling_params);
1109                 /* Enable checksum offloading */
1110                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1111                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1112                                                  &td_offset, tx_offload);
1113
1114                 if (nb_ctx) {
1115                         /* Setup TX context descriptor if required */
1116                         volatile struct i40e_tx_context_desc *ctx_txd =
1117                                 (volatile struct i40e_tx_context_desc *)\
1118                                                         &txr[tx_id];
1119                         uint16_t cd_l2tag2 = 0;
1120                         uint64_t cd_type_cmd_tso_mss =
1121                                 I40E_TX_DESC_DTYPE_CONTEXT;
1122
1123                         txn = &sw_ring[txe->next_id];
1124                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1125                         if (txe->mbuf != NULL) {
1126                                 rte_pktmbuf_free_seg(txe->mbuf);
1127                                 txe->mbuf = NULL;
1128                         }
1129
1130                         /* TSO enabled means no timestamp */
1131                         if (ol_flags & PKT_TX_TCP_SEG)
1132                                 cd_type_cmd_tso_mss |=
1133                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1134                         else {
1135 #ifdef RTE_LIBRTE_IEEE1588
1136                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1137                                         cd_type_cmd_tso_mss |=
1138                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1139                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1140 #endif
1141                         }
1142
1143                         ctx_txd->tunneling_params =
1144                                 rte_cpu_to_le_32(cd_tunneling_params);
1145                         if (ol_flags & PKT_TX_QINQ_PKT) {
1146                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1147                                 cd_type_cmd_tso_mss |=
1148                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1149                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1150                         }
1151                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1152                         ctx_txd->type_cmd_tso_mss =
1153                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1154
1155                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1156                                 "tunneling_params: %#x;\n"
1157                                 "l2tag2: %#hx;\n"
1158                                 "rsvd: %#hx;\n"
1159                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1160                                 tx_pkt, tx_id,
1161                                 ctx_txd->tunneling_params,
1162                                 ctx_txd->l2tag2,
1163                                 ctx_txd->rsvd,
1164                                 ctx_txd->type_cmd_tso_mss);
1165
1166                         txe->last_id = tx_last;
1167                         tx_id = txe->next_id;
1168                         txe = txn;
1169                 }
1170
1171                 m_seg = tx_pkt;
1172                 do {
1173                         txd = &txr[tx_id];
1174                         txn = &sw_ring[txe->next_id];
1175
1176                         if (txe->mbuf)
1177                                 rte_pktmbuf_free_seg(txe->mbuf);
1178                         txe->mbuf = m_seg;
1179
1180                         /* Setup TX Descriptor */
1181                         slen = m_seg->data_len;
1182                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1183
1184                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1185                                 "buf_dma_addr: %#"PRIx64";\n"
1186                                 "td_cmd: %#x;\n"
1187                                 "td_offset: %#x;\n"
1188                                 "td_len: %u;\n"
1189                                 "td_tag: %#x;\n",
1190                                 tx_pkt, tx_id, buf_dma_addr,
1191                                 td_cmd, td_offset, slen, td_tag);
1192
1193                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1194                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1195                                                 td_offset, slen, td_tag);
1196                         txe->last_id = tx_last;
1197                         tx_id = txe->next_id;
1198                         txe = txn;
1199                         m_seg = m_seg->next;
1200                 } while (m_seg != NULL);
1201
1202                 /* The last packet data descriptor needs End Of Packet (EOP) */
1203                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1204                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1205                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1206
1207                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1208                         PMD_TX_FREE_LOG(DEBUG,
1209                                         "Setting RS bit on TXD id="
1210                                         "%4u (port=%d queue=%d)",
1211                                         tx_last, txq->port_id, txq->queue_id);
1212
1213                         td_cmd |= I40E_TX_DESC_CMD_RS;
1214
1215                         /* Update txq RS bit counters */
1216                         txq->nb_tx_used = 0;
1217                 }
1218
1219                 txd->cmd_type_offset_bsz |=
1220                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1221                                         I40E_TXD_QW1_CMD_SHIFT);
1222         }
1223
1224 end_of_tx:
1225         rte_wmb();
1226
1227         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1228                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1229                    (unsigned) tx_id, (unsigned) nb_tx);
1230
1231         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1232         txq->tx_tail = tx_id;
1233
1234         return nb_tx;
1235 }
1236
1237 static inline int __attribute__((always_inline))
1238 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1239 {
1240         struct i40e_tx_entry *txep;
1241         uint16_t i;
1242
1243         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1244                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1245                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1246                 return 0;
1247
1248         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1249
1250         for (i = 0; i < txq->tx_rs_thresh; i++)
1251                 rte_prefetch0((txep + i)->mbuf);
1252
1253         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1254                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1255                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1256                         txep->mbuf = NULL;
1257                 }
1258         } else {
1259                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1260                         rte_pktmbuf_free_seg(txep->mbuf);
1261                         txep->mbuf = NULL;
1262                 }
1263         }
1264
1265         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1266         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1267         if (txq->tx_next_dd >= txq->nb_tx_desc)
1268                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1269
1270         return txq->tx_rs_thresh;
1271 }
1272
1273 /* Populate 4 descriptors with data from 4 mbufs */
1274 static inline void
1275 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1276 {
1277         uint64_t dma_addr;
1278         uint32_t i;
1279
1280         for (i = 0; i < 4; i++, txdp++, pkts++) {
1281                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1282                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1283                 txdp->cmd_type_offset_bsz =
1284                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1285                                         (*pkts)->data_len, 0);
1286         }
1287 }
1288
1289 /* Populate 1 descriptor with data from 1 mbuf */
1290 static inline void
1291 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1292 {
1293         uint64_t dma_addr;
1294
1295         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1296         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1297         txdp->cmd_type_offset_bsz =
1298                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1299                                 (*pkts)->data_len, 0);
1300 }
1301
1302 /* Fill hardware descriptor ring with mbuf data */
1303 static inline void
1304 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1305                      struct rte_mbuf **pkts,
1306                      uint16_t nb_pkts)
1307 {
1308         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1309         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1310         const int N_PER_LOOP = 4;
1311         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1312         int mainpart, leftover;
1313         int i, j;
1314
1315         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1316         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1317         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1318                 for (j = 0; j < N_PER_LOOP; ++j) {
1319                         (txep + i + j)->mbuf = *(pkts + i + j);
1320                 }
1321                 tx4(txdp + i, pkts + i);
1322         }
1323         if (unlikely(leftover > 0)) {
1324                 for (i = 0; i < leftover; ++i) {
1325                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1326                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1327                 }
1328         }
1329 }
1330
1331 static inline uint16_t
1332 tx_xmit_pkts(struct i40e_tx_queue *txq,
1333              struct rte_mbuf **tx_pkts,
1334              uint16_t nb_pkts)
1335 {
1336         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1337         uint16_t n = 0;
1338
1339         /**
1340          * Begin scanning the H/W ring for done descriptors when the number
1341          * of available descriptors drops below tx_free_thresh. For each done
1342          * descriptor, free the associated buffer.
1343          */
1344         if (txq->nb_tx_free < txq->tx_free_thresh)
1345                 i40e_tx_free_bufs(txq);
1346
1347         /* Use available descriptor only */
1348         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1349         if (unlikely(!nb_pkts))
1350                 return 0;
1351
1352         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1353         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1354                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1355                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1356                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1357                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1358                                                 I40E_TXD_QW1_CMD_SHIFT);
1359                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1360                 txq->tx_tail = 0;
1361         }
1362
1363         /* Fill hardware descriptor ring with mbuf data */
1364         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1365         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1366
1367         /* Determin if RS bit needs to be set */
1368         if (txq->tx_tail > txq->tx_next_rs) {
1369                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1370                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1371                                                 I40E_TXD_QW1_CMD_SHIFT);
1372                 txq->tx_next_rs =
1373                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1374                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1375                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1376         }
1377
1378         if (txq->tx_tail >= txq->nb_tx_desc)
1379                 txq->tx_tail = 0;
1380
1381         /* Update the tx tail register */
1382         rte_wmb();
1383         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1384
1385         return nb_pkts;
1386 }
1387
1388 static uint16_t
1389 i40e_xmit_pkts_simple(void *tx_queue,
1390                       struct rte_mbuf **tx_pkts,
1391                       uint16_t nb_pkts)
1392 {
1393         uint16_t nb_tx = 0;
1394
1395         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1396                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1397                                                 tx_pkts, nb_pkts);
1398
1399         while (nb_pkts) {
1400                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1401                                                 I40E_TX_MAX_BURST);
1402
1403                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1404                                                 &tx_pkts[nb_tx], num);
1405                 nb_tx = (uint16_t)(nb_tx + ret);
1406                 nb_pkts = (uint16_t)(nb_pkts - ret);
1407                 if (ret < num)
1408                         break;
1409         }
1410
1411         return nb_tx;
1412 }
1413
1414 /*
1415  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1416  * application used, which assume having sequential ones. But from driver's
1417  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1418  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1419  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1420  * use queue_idx from 0 to 95 to access queues, while real queue would be
1421  * different. This function will do a queue mapping to find VSI the queue
1422  * belongs to.
1423  */
1424 static struct i40e_vsi*
1425 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1426 {
1427         /* the queue in MAIN VSI range */
1428         if (queue_idx < pf->main_vsi->nb_qps)
1429                 return pf->main_vsi;
1430
1431         queue_idx -= pf->main_vsi->nb_qps;
1432
1433         /* queue_idx is greater than VMDQ VSIs range */
1434         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1435                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1436                 return NULL;
1437         }
1438
1439         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1440 }
1441
1442 static uint16_t
1443 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1444 {
1445         /* the queue in MAIN VSI range */
1446         if (queue_idx < pf->main_vsi->nb_qps)
1447                 return queue_idx;
1448
1449         /* It's VMDQ queues */
1450         queue_idx -= pf->main_vsi->nb_qps;
1451
1452         if (pf->nb_cfg_vmdq_vsi)
1453                 return queue_idx % pf->vmdq_nb_qps;
1454         else {
1455                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1456                 return (uint16_t)(-1);
1457         }
1458 }
1459
1460 int
1461 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1462 {
1463         struct i40e_rx_queue *rxq;
1464         int err = -1;
1465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         if (rx_queue_id < dev->data->nb_rx_queues) {
1470                 rxq = dev->data->rx_queues[rx_queue_id];
1471
1472                 err = i40e_alloc_rx_queue_mbufs(rxq);
1473                 if (err) {
1474                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1475                         return err;
1476                 }
1477
1478                 rte_wmb();
1479
1480                 /* Init the RX tail regieter. */
1481                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1482
1483                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1484
1485                 if (err) {
1486                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1487                                     rx_queue_id);
1488
1489                         i40e_rx_queue_release_mbufs(rxq);
1490                         i40e_reset_rx_queue(rxq);
1491                 } else
1492                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1493         }
1494
1495         return err;
1496 }
1497
1498 int
1499 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1500 {
1501         struct i40e_rx_queue *rxq;
1502         int err;
1503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504
1505         if (rx_queue_id < dev->data->nb_rx_queues) {
1506                 rxq = dev->data->rx_queues[rx_queue_id];
1507
1508                 /*
1509                 * rx_queue_id is queue id aplication refers to, while
1510                 * rxq->reg_idx is the real queue index.
1511                 */
1512                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1513
1514                 if (err) {
1515                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1516                                     rx_queue_id);
1517                         return err;
1518                 }
1519                 i40e_rx_queue_release_mbufs(rxq);
1520                 i40e_reset_rx_queue(rxq);
1521                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1522         }
1523
1524         return 0;
1525 }
1526
1527 int
1528 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1529 {
1530         int err = -1;
1531         struct i40e_tx_queue *txq;
1532         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533
1534         PMD_INIT_FUNC_TRACE();
1535
1536         if (tx_queue_id < dev->data->nb_tx_queues) {
1537                 txq = dev->data->tx_queues[tx_queue_id];
1538
1539                 /*
1540                 * tx_queue_id is queue id aplication refers to, while
1541                 * rxq->reg_idx is the real queue index.
1542                 */
1543                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1544                 if (err)
1545                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1546                                     tx_queue_id);
1547                 else
1548                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1549         }
1550
1551         return err;
1552 }
1553
1554 int
1555 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1556 {
1557         struct i40e_tx_queue *txq;
1558         int err;
1559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560
1561         if (tx_queue_id < dev->data->nb_tx_queues) {
1562                 txq = dev->data->tx_queues[tx_queue_id];
1563
1564                 /*
1565                 * tx_queue_id is queue id aplication refers to, while
1566                 * txq->reg_idx is the real queue index.
1567                 */
1568                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1569
1570                 if (err) {
1571                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1572                                     tx_queue_id);
1573                         return err;
1574                 }
1575
1576                 i40e_tx_queue_release_mbufs(txq);
1577                 i40e_reset_tx_queue(txq);
1578                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1579         }
1580
1581         return 0;
1582 }
1583
1584 const uint32_t *
1585 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1586 {
1587         static const uint32_t ptypes[] = {
1588                 /* refers to i40e_rxd_pkt_type_mapping() */
1589                 RTE_PTYPE_L2_ETHER,
1590                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1591                 RTE_PTYPE_L2_ETHER_LLDP,
1592                 RTE_PTYPE_L2_ETHER_ARP,
1593                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1594                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1595                 RTE_PTYPE_L4_FRAG,
1596                 RTE_PTYPE_L4_ICMP,
1597                 RTE_PTYPE_L4_NONFRAG,
1598                 RTE_PTYPE_L4_SCTP,
1599                 RTE_PTYPE_L4_TCP,
1600                 RTE_PTYPE_L4_UDP,
1601                 RTE_PTYPE_TUNNEL_GRENAT,
1602                 RTE_PTYPE_TUNNEL_IP,
1603                 RTE_PTYPE_INNER_L2_ETHER,
1604                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1605                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1606                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1607                 RTE_PTYPE_INNER_L4_FRAG,
1608                 RTE_PTYPE_INNER_L4_ICMP,
1609                 RTE_PTYPE_INNER_L4_NONFRAG,
1610                 RTE_PTYPE_INNER_L4_SCTP,
1611                 RTE_PTYPE_INNER_L4_TCP,
1612                 RTE_PTYPE_INNER_L4_UDP,
1613                 RTE_PTYPE_UNKNOWN
1614         };
1615
1616         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1617 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1618             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1619 #endif
1620             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1621             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1622             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1623                 return ptypes;
1624         return NULL;
1625 }
1626
1627 int
1628 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1629                         uint16_t queue_idx,
1630                         uint16_t nb_desc,
1631                         unsigned int socket_id,
1632                         const struct rte_eth_rxconf *rx_conf,
1633                         struct rte_mempool *mp)
1634 {
1635         struct i40e_vsi *vsi;
1636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1638         struct i40e_adapter *ad =
1639                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1640         struct i40e_rx_queue *rxq;
1641         const struct rte_memzone *rz;
1642         uint32_t ring_size;
1643         uint16_t len, i;
1644         uint16_t base, bsf, tc_mapping;
1645         int use_def_burst_func = 1;
1646
1647         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1648                 struct i40e_vf *vf =
1649                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1650                 vsi = &vf->vsi;
1651         } else
1652                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1653
1654         if (vsi == NULL) {
1655                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1656                             "index exceeds the maximum");
1657                 return I40E_ERR_PARAM;
1658         }
1659         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1660                         (nb_desc > I40E_MAX_RING_DESC) ||
1661                         (nb_desc < I40E_MIN_RING_DESC)) {
1662                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1663                             "invalid", nb_desc);
1664                 return I40E_ERR_PARAM;
1665         }
1666
1667         /* Free memory if needed */
1668         if (dev->data->rx_queues[queue_idx]) {
1669                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1670                 dev->data->rx_queues[queue_idx] = NULL;
1671         }
1672
1673         /* Allocate the rx queue data structure */
1674         rxq = rte_zmalloc_socket("i40e rx queue",
1675                                  sizeof(struct i40e_rx_queue),
1676                                  RTE_CACHE_LINE_SIZE,
1677                                  socket_id);
1678         if (!rxq) {
1679                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1680                             "rx queue data structure");
1681                 return -ENOMEM;
1682         }
1683         rxq->mp = mp;
1684         rxq->nb_rx_desc = nb_desc;
1685         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1686         rxq->queue_id = queue_idx;
1687         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1688                 rxq->reg_idx = queue_idx;
1689         else /* PF device */
1690                 rxq->reg_idx = vsi->base_queue +
1691                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1692
1693         rxq->port_id = dev->data->port_id;
1694         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1695                                                         0 : ETHER_CRC_LEN);
1696         rxq->drop_en = rx_conf->rx_drop_en;
1697         rxq->vsi = vsi;
1698         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1699
1700         /* Allocate the maximun number of RX ring hardware descriptor. */
1701         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1702         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1703         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1704                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1705         if (!rz) {
1706                 i40e_dev_rx_queue_release(rxq);
1707                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1708                 return -ENOMEM;
1709         }
1710
1711         /* Zero all the descriptors in the ring. */
1712         memset(rz->addr, 0, ring_size);
1713
1714         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1715         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1716
1717 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1718         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1719 #else
1720         len = nb_desc;
1721 #endif
1722
1723         /* Allocate the software ring. */
1724         rxq->sw_ring =
1725                 rte_zmalloc_socket("i40e rx sw ring",
1726                                    sizeof(struct i40e_rx_entry) * len,
1727                                    RTE_CACHE_LINE_SIZE,
1728                                    socket_id);
1729         if (!rxq->sw_ring) {
1730                 i40e_dev_rx_queue_release(rxq);
1731                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1732                 return -ENOMEM;
1733         }
1734
1735         i40e_reset_rx_queue(rxq);
1736         rxq->q_set = TRUE;
1737         dev->data->rx_queues[queue_idx] = rxq;
1738
1739         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1740
1741         if (!use_def_burst_func) {
1742 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1743                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1744                              "satisfied. Rx Burst Bulk Alloc function will be "
1745                              "used on port=%d, queue=%d.",
1746                              rxq->port_id, rxq->queue_id);
1747 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1748         } else {
1749                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1750                              "not satisfied, Scattered Rx is requested, "
1751                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1752                              "not enabled on port=%d, queue=%d.",
1753                              rxq->port_id, rxq->queue_id);
1754                 ad->rx_bulk_alloc_allowed = false;
1755         }
1756
1757         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1758                 if (!(vsi->enabled_tc & (1 << i)))
1759                         continue;
1760                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1761                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1762                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1763                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1764                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1765
1766                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1767                         rxq->dcb_tc = i;
1768         }
1769
1770         return 0;
1771 }
1772
1773 void
1774 i40e_dev_rx_queue_release(void *rxq)
1775 {
1776         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1777
1778         if (!q) {
1779                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1780                 return;
1781         }
1782
1783         i40e_rx_queue_release_mbufs(q);
1784         rte_free(q->sw_ring);
1785         rte_free(q);
1786 }
1787
1788 uint32_t
1789 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1790 {
1791 #define I40E_RXQ_SCAN_INTERVAL 4
1792         volatile union i40e_rx_desc *rxdp;
1793         struct i40e_rx_queue *rxq;
1794         uint16_t desc = 0;
1795
1796         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1797                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1798                 return 0;
1799         }
1800
1801         rxq = dev->data->rx_queues[rx_queue_id];
1802         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1803         while ((desc < rxq->nb_rx_desc) &&
1804                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1805                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1806                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1807                 /**
1808                  * Check the DD bit of a rx descriptor of each 4 in a group,
1809                  * to avoid checking too frequently and downgrading performance
1810                  * too much.
1811                  */
1812                 desc += I40E_RXQ_SCAN_INTERVAL;
1813                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1814                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1815                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1816                                         desc - rxq->nb_rx_desc]);
1817         }
1818
1819         return desc;
1820 }
1821
1822 int
1823 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1824 {
1825         volatile union i40e_rx_desc *rxdp;
1826         struct i40e_rx_queue *rxq = rx_queue;
1827         uint16_t desc;
1828         int ret;
1829
1830         if (unlikely(offset >= rxq->nb_rx_desc)) {
1831                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1832                 return 0;
1833         }
1834
1835         desc = rxq->rx_tail + offset;
1836         if (desc >= rxq->nb_rx_desc)
1837                 desc -= rxq->nb_rx_desc;
1838
1839         rxdp = &(rxq->rx_ring[desc]);
1840
1841         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1842                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1843                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1844
1845         return ret;
1846 }
1847
1848 int
1849 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1850                         uint16_t queue_idx,
1851                         uint16_t nb_desc,
1852                         unsigned int socket_id,
1853                         const struct rte_eth_txconf *tx_conf)
1854 {
1855         struct i40e_vsi *vsi;
1856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1858         struct i40e_tx_queue *txq;
1859         const struct rte_memzone *tz;
1860         uint32_t ring_size;
1861         uint16_t tx_rs_thresh, tx_free_thresh;
1862         uint16_t i, base, bsf, tc_mapping;
1863
1864         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1865                 struct i40e_vf *vf =
1866                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1867                 vsi = &vf->vsi;
1868         } else
1869                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1870
1871         if (vsi == NULL) {
1872                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1873                             "exceeds the maximum", queue_idx);
1874                 return I40E_ERR_PARAM;
1875         }
1876
1877         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1878                         (nb_desc > I40E_MAX_RING_DESC) ||
1879                         (nb_desc < I40E_MIN_RING_DESC)) {
1880                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1881                             "invalid", nb_desc);
1882                 return I40E_ERR_PARAM;
1883         }
1884
1885         /**
1886          * The following two parameters control the setting of the RS bit on
1887          * transmit descriptors. TX descriptors will have their RS bit set
1888          * after txq->tx_rs_thresh descriptors have been used. The TX
1889          * descriptor ring will be cleaned after txq->tx_free_thresh
1890          * descriptors are used or if the number of descriptors required to
1891          * transmit a packet is greater than the number of free TX descriptors.
1892          *
1893          * The following constraints must be satisfied:
1894          *  - tx_rs_thresh must be greater than 0.
1895          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1896          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1897          *  - tx_rs_thresh must be a divisor of the ring size.
1898          *  - tx_free_thresh must be greater than 0.
1899          *  - tx_free_thresh must be less than the size of the ring minus 3.
1900          *
1901          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1902          * race condition, hence the maximum threshold constraints. When set
1903          * to zero use default values.
1904          */
1905         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1906                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1907         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1908                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1909         if (tx_rs_thresh >= (nb_desc - 2)) {
1910                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1911                              "number of TX descriptors minus 2. "
1912                              "(tx_rs_thresh=%u port=%d queue=%d)",
1913                              (unsigned int)tx_rs_thresh,
1914                              (int)dev->data->port_id,
1915                              (int)queue_idx);
1916                 return I40E_ERR_PARAM;
1917         }
1918         if (tx_free_thresh >= (nb_desc - 3)) {
1919                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1920                              "tx_free_thresh must be less than the "
1921                              "number of TX descriptors minus 3. "
1922                              "(tx_free_thresh=%u port=%d queue=%d)",
1923                              (unsigned int)tx_free_thresh,
1924                              (int)dev->data->port_id,
1925                              (int)queue_idx);
1926                 return I40E_ERR_PARAM;
1927         }
1928         if (tx_rs_thresh > tx_free_thresh) {
1929                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1930                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1931                              " tx_rs_thresh=%u port=%d queue=%d)",
1932                              (unsigned int)tx_free_thresh,
1933                              (unsigned int)tx_rs_thresh,
1934                              (int)dev->data->port_id,
1935                              (int)queue_idx);
1936                 return I40E_ERR_PARAM;
1937         }
1938         if ((nb_desc % tx_rs_thresh) != 0) {
1939                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1940                              "number of TX descriptors. (tx_rs_thresh=%u"
1941                              " port=%d queue=%d)",
1942                              (unsigned int)tx_rs_thresh,
1943                              (int)dev->data->port_id,
1944                              (int)queue_idx);
1945                 return I40E_ERR_PARAM;
1946         }
1947         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1948                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1949                              "tx_rs_thresh is greater than 1. "
1950                              "(tx_rs_thresh=%u port=%d queue=%d)",
1951                              (unsigned int)tx_rs_thresh,
1952                              (int)dev->data->port_id,
1953                              (int)queue_idx);
1954                 return I40E_ERR_PARAM;
1955         }
1956
1957         /* Free memory if needed. */
1958         if (dev->data->tx_queues[queue_idx]) {
1959                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1960                 dev->data->tx_queues[queue_idx] = NULL;
1961         }
1962
1963         /* Allocate the TX queue data structure. */
1964         txq = rte_zmalloc_socket("i40e tx queue",
1965                                   sizeof(struct i40e_tx_queue),
1966                                   RTE_CACHE_LINE_SIZE,
1967                                   socket_id);
1968         if (!txq) {
1969                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1970                             "tx queue structure");
1971                 return -ENOMEM;
1972         }
1973
1974         /* Allocate TX hardware ring descriptors. */
1975         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1976         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1977         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1978                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1979         if (!tz) {
1980                 i40e_dev_tx_queue_release(txq);
1981                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1982                 return -ENOMEM;
1983         }
1984
1985         txq->nb_tx_desc = nb_desc;
1986         txq->tx_rs_thresh = tx_rs_thresh;
1987         txq->tx_free_thresh = tx_free_thresh;
1988         txq->pthresh = tx_conf->tx_thresh.pthresh;
1989         txq->hthresh = tx_conf->tx_thresh.hthresh;
1990         txq->wthresh = tx_conf->tx_thresh.wthresh;
1991         txq->queue_id = queue_idx;
1992         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1993                 txq->reg_idx = queue_idx;
1994         else /* PF device */
1995                 txq->reg_idx = vsi->base_queue +
1996                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1997
1998         txq->port_id = dev->data->port_id;
1999         txq->txq_flags = tx_conf->txq_flags;
2000         txq->vsi = vsi;
2001         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2002
2003         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2004         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2005
2006         /* Allocate software ring */
2007         txq->sw_ring =
2008                 rte_zmalloc_socket("i40e tx sw ring",
2009                                    sizeof(struct i40e_tx_entry) * nb_desc,
2010                                    RTE_CACHE_LINE_SIZE,
2011                                    socket_id);
2012         if (!txq->sw_ring) {
2013                 i40e_dev_tx_queue_release(txq);
2014                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2015                 return -ENOMEM;
2016         }
2017
2018         i40e_reset_tx_queue(txq);
2019         txq->q_set = TRUE;
2020         dev->data->tx_queues[queue_idx] = txq;
2021
2022         /* Use a simple TX queue without offloads or multi segs if possible */
2023         i40e_set_tx_function_flag(dev, txq);
2024
2025         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2026                 if (!(vsi->enabled_tc & (1 << i)))
2027                         continue;
2028                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2029                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2030                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2031                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2032                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2033
2034                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2035                         txq->dcb_tc = i;
2036         }
2037
2038         return 0;
2039 }
2040
2041 void
2042 i40e_dev_tx_queue_release(void *txq)
2043 {
2044         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2045
2046         if (!q) {
2047                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2048                 return;
2049         }
2050
2051         i40e_tx_queue_release_mbufs(q);
2052         rte_free(q->sw_ring);
2053         rte_free(q);
2054 }
2055
2056 const struct rte_memzone *
2057 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2058 {
2059         const struct rte_memzone *mz;
2060
2061         mz = rte_memzone_lookup(name);
2062         if (mz)
2063                 return mz;
2064
2065         if (rte_xen_dom0_supported())
2066                 mz = rte_memzone_reserve_bounded(name, len,
2067                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2068         else
2069                 mz = rte_memzone_reserve_aligned(name, len,
2070                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2071         return mz;
2072 }
2073
2074 void
2075 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2076 {
2077         uint16_t i;
2078
2079         /* SSE Vector driver has a different way of releasing mbufs. */
2080         if (rxq->rx_using_sse) {
2081                 i40e_rx_queue_release_mbufs_vec(rxq);
2082                 return;
2083         }
2084
2085         if (!rxq->sw_ring) {
2086                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2087                 return;
2088         }
2089
2090         for (i = 0; i < rxq->nb_rx_desc; i++) {
2091                 if (rxq->sw_ring[i].mbuf) {
2092                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2093                         rxq->sw_ring[i].mbuf = NULL;
2094                 }
2095         }
2096 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2097         if (rxq->rx_nb_avail == 0)
2098                 return;
2099         for (i = 0; i < rxq->rx_nb_avail; i++) {
2100                 struct rte_mbuf *mbuf;
2101
2102                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2103                 rte_pktmbuf_free_seg(mbuf);
2104         }
2105         rxq->rx_nb_avail = 0;
2106 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2107 }
2108
2109 void
2110 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2111 {
2112         unsigned i;
2113         uint16_t len;
2114
2115         if (!rxq) {
2116                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2117                 return;
2118         }
2119
2120 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2121         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2122                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2123         else
2124 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2125                 len = rxq->nb_rx_desc;
2126
2127         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2128                 ((volatile char *)rxq->rx_ring)[i] = 0;
2129
2130 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2131         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2132         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2133                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2134
2135         rxq->rx_nb_avail = 0;
2136         rxq->rx_next_avail = 0;
2137         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2138 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2139         rxq->rx_tail = 0;
2140         rxq->nb_rx_hold = 0;
2141         rxq->pkt_first_seg = NULL;
2142         rxq->pkt_last_seg = NULL;
2143
2144         rxq->rxrearm_start = 0;
2145         rxq->rxrearm_nb = 0;
2146 }
2147
2148 void
2149 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2150 {
2151         uint16_t i;
2152
2153         if (!txq || !txq->sw_ring) {
2154                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2155                 return;
2156         }
2157
2158         for (i = 0; i < txq->nb_tx_desc; i++) {
2159                 if (txq->sw_ring[i].mbuf) {
2160                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2161                         txq->sw_ring[i].mbuf = NULL;
2162                 }
2163         }
2164 }
2165
2166 void
2167 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2168 {
2169         struct i40e_tx_entry *txe;
2170         uint16_t i, prev, size;
2171
2172         if (!txq) {
2173                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2174                 return;
2175         }
2176
2177         txe = txq->sw_ring;
2178         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2179         for (i = 0; i < size; i++)
2180                 ((volatile char *)txq->tx_ring)[i] = 0;
2181
2182         prev = (uint16_t)(txq->nb_tx_desc - 1);
2183         for (i = 0; i < txq->nb_tx_desc; i++) {
2184                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2185
2186                 txd->cmd_type_offset_bsz =
2187                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2188                 txe[i].mbuf =  NULL;
2189                 txe[i].last_id = i;
2190                 txe[prev].next_id = i;
2191                 prev = i;
2192         }
2193
2194         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2195         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2196
2197         txq->tx_tail = 0;
2198         txq->nb_tx_used = 0;
2199
2200         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2201         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2202 }
2203
2204 /* Init the TX queue in hardware */
2205 int
2206 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2207 {
2208         enum i40e_status_code err = I40E_SUCCESS;
2209         struct i40e_vsi *vsi = txq->vsi;
2210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2211         uint16_t pf_q = txq->reg_idx;
2212         struct i40e_hmc_obj_txq tx_ctx;
2213         uint32_t qtx_ctl;
2214
2215         /* clear the context structure first */
2216         memset(&tx_ctx, 0, sizeof(tx_ctx));
2217         tx_ctx.new_context = 1;
2218         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2219         tx_ctx.qlen = txq->nb_tx_desc;
2220
2221 #ifdef RTE_LIBRTE_IEEE1588
2222         tx_ctx.timesync_ena = 1;
2223 #endif
2224         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2225         if (vsi->type == I40E_VSI_FDIR)
2226                 tx_ctx.fd_ena = TRUE;
2227
2228         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2229         if (err != I40E_SUCCESS) {
2230                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2231                 return err;
2232         }
2233
2234         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2235         if (err != I40E_SUCCESS) {
2236                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2237                 return err;
2238         }
2239
2240         /* Now associate this queue with this PCI function */
2241         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2242         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2243                                         I40E_QTX_CTL_PF_INDX_MASK);
2244         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2245         I40E_WRITE_FLUSH(hw);
2246
2247         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2248
2249         return err;
2250 }
2251
2252 int
2253 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2254 {
2255         struct i40e_rx_entry *rxe = rxq->sw_ring;
2256         uint64_t dma_addr;
2257         uint16_t i;
2258
2259         for (i = 0; i < rxq->nb_rx_desc; i++) {
2260                 volatile union i40e_rx_desc *rxd;
2261                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2262
2263                 if (unlikely(!mbuf)) {
2264                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2265                         return -ENOMEM;
2266                 }
2267
2268                 rte_mbuf_refcnt_set(mbuf, 1);
2269                 mbuf->next = NULL;
2270                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2271                 mbuf->nb_segs = 1;
2272                 mbuf->port = rxq->port_id;
2273
2274                 dma_addr =
2275                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2276
2277                 rxd = &rxq->rx_ring[i];
2278                 rxd->read.pkt_addr = dma_addr;
2279                 rxd->read.hdr_addr = 0;
2280 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2281                 rxd->read.rsvd1 = 0;
2282                 rxd->read.rsvd2 = 0;
2283 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2284
2285                 rxe[i].mbuf = mbuf;
2286         }
2287
2288         return 0;
2289 }
2290
2291 /*
2292  * Calculate the buffer length, and check the jumbo frame
2293  * and maximum packet length.
2294  */
2295 static int
2296 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2297 {
2298         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2299         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2300         struct rte_eth_dev_data *data = pf->dev_data;
2301         uint16_t buf_size, len;
2302
2303         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2304                 RTE_PKTMBUF_HEADROOM);
2305
2306         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2307                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2308         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2309                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2310                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2311                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2312                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2313                 rxq->hs_mode = i40e_header_split_enabled;
2314                 break;
2315         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2316         default:
2317                 rxq->rx_hdr_len = 0;
2318                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2319                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2320                 rxq->hs_mode = i40e_header_split_none;
2321                 break;
2322         }
2323
2324         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2325         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2326         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2327                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2328                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2329                         PMD_DRV_LOG(ERR, "maximum packet length must "
2330                                     "be larger than %u and smaller than %u,"
2331                                     "as jumbo frame is enabled",
2332                                     (uint32_t)ETHER_MAX_LEN,
2333                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2334                         return I40E_ERR_CONFIG;
2335                 }
2336         } else {
2337                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2338                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2339                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2340                                     "larger than %u and smaller than %u, "
2341                                     "as jumbo frame is disabled",
2342                                     (uint32_t)ETHER_MIN_LEN,
2343                                     (uint32_t)ETHER_MAX_LEN);
2344                         return I40E_ERR_CONFIG;
2345                 }
2346         }
2347
2348         return 0;
2349 }
2350
2351 /* Init the RX queue in hardware */
2352 int
2353 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2354 {
2355         int err = I40E_SUCCESS;
2356         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2357         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2358         uint16_t pf_q = rxq->reg_idx;
2359         uint16_t buf_size;
2360         struct i40e_hmc_obj_rxq rx_ctx;
2361
2362         err = i40e_rx_queue_config(rxq);
2363         if (err < 0) {
2364                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2365                 return err;
2366         }
2367
2368         /* Clear the context structure first */
2369         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2370         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2371         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2372
2373         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2374         rx_ctx.qlen = rxq->nb_rx_desc;
2375 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2376         rx_ctx.dsize = 1;
2377 #endif
2378         rx_ctx.dtype = rxq->hs_mode;
2379         if (rxq->hs_mode)
2380                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2381         else
2382                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2383         rx_ctx.rxmax = rxq->max_pkt_len;
2384         rx_ctx.tphrdesc_ena = 1;
2385         rx_ctx.tphwdesc_ena = 1;
2386         rx_ctx.tphdata_ena = 1;
2387         rx_ctx.tphhead_ena = 1;
2388         rx_ctx.lrxqthresh = 2;
2389         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2390         rx_ctx.l2tsel = 1;
2391         /* showiv indicates if inner VLAN is stripped inside of tunnel
2392          * packet. When set it to 1, vlan information is stripped from
2393          * the inner header, but the hardware does not put it in the
2394          * descriptor. So set it zero by default.
2395          */
2396         rx_ctx.showiv = 0;
2397         rx_ctx.prefena = 1;
2398
2399         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2400         if (err != I40E_SUCCESS) {
2401                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2402                 return err;
2403         }
2404         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2405         if (err != I40E_SUCCESS) {
2406                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2407                 return err;
2408         }
2409
2410         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2411
2412         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2413                 RTE_PKTMBUF_HEADROOM);
2414
2415         /* Check if scattered RX needs to be used. */
2416         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2417                 dev_data->scattered_rx = 1;
2418         }
2419
2420         /* Init the RX tail regieter. */
2421         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2422
2423         return 0;
2424 }
2425
2426 void
2427 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2428 {
2429         uint16_t i;
2430
2431         PMD_INIT_FUNC_TRACE();
2432
2433         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2434                 if (!dev->data->tx_queues[i])
2435                         continue;
2436                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2437                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2438         }
2439
2440         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2441                 if (!dev->data->rx_queues[i])
2442                         continue;
2443                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2444                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2445         }
2446 }
2447
2448 void
2449 i40e_dev_free_queues(struct rte_eth_dev *dev)
2450 {
2451         uint16_t i;
2452
2453         PMD_INIT_FUNC_TRACE();
2454
2455         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2456                 if (!dev->data->rx_queues[i])
2457                         continue;
2458                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2459                 dev->data->rx_queues[i] = NULL;
2460         }
2461         dev->data->nb_rx_queues = 0;
2462
2463         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2464                 if (!dev->data->tx_queues[i])
2465                         continue;
2466                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2467                 dev->data->tx_queues[i] = NULL;
2468         }
2469         dev->data->nb_tx_queues = 0;
2470 }
2471
2472 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2473 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2474
2475 enum i40e_status_code
2476 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2477 {
2478         struct i40e_tx_queue *txq;
2479         const struct rte_memzone *tz = NULL;
2480         uint32_t ring_size;
2481         struct rte_eth_dev *dev;
2482
2483         if (!pf) {
2484                 PMD_DRV_LOG(ERR, "PF is not available");
2485                 return I40E_ERR_BAD_PTR;
2486         }
2487
2488         dev = pf->adapter->eth_dev;
2489
2490         /* Allocate the TX queue data structure. */
2491         txq = rte_zmalloc_socket("i40e fdir tx queue",
2492                                   sizeof(struct i40e_tx_queue),
2493                                   RTE_CACHE_LINE_SIZE,
2494                                   SOCKET_ID_ANY);
2495         if (!txq) {
2496                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2497                                         "tx queue structure.");
2498                 return I40E_ERR_NO_MEMORY;
2499         }
2500
2501         /* Allocate TX hardware ring descriptors. */
2502         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2503         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2504
2505         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2506                                       I40E_FDIR_QUEUE_ID, ring_size,
2507                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2508         if (!tz) {
2509                 i40e_dev_tx_queue_release(txq);
2510                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2511                 return I40E_ERR_NO_MEMORY;
2512         }
2513
2514         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2515         txq->queue_id = I40E_FDIR_QUEUE_ID;
2516         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2517         txq->vsi = pf->fdir.fdir_vsi;
2518
2519         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2520         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2521         /*
2522          * don't need to allocate software ring and reset for the fdir
2523          * program queue just set the queue has been configured.
2524          */
2525         txq->q_set = TRUE;
2526         pf->fdir.txq = txq;
2527
2528         return I40E_SUCCESS;
2529 }
2530
2531 enum i40e_status_code
2532 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2533 {
2534         struct i40e_rx_queue *rxq;
2535         const struct rte_memzone *rz = NULL;
2536         uint32_t ring_size;
2537         struct rte_eth_dev *dev;
2538
2539         if (!pf) {
2540                 PMD_DRV_LOG(ERR, "PF is not available");
2541                 return I40E_ERR_BAD_PTR;
2542         }
2543
2544         dev = pf->adapter->eth_dev;
2545
2546         /* Allocate the RX queue data structure. */
2547         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2548                                   sizeof(struct i40e_rx_queue),
2549                                   RTE_CACHE_LINE_SIZE,
2550                                   SOCKET_ID_ANY);
2551         if (!rxq) {
2552                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2553                                         "rx queue structure.");
2554                 return I40E_ERR_NO_MEMORY;
2555         }
2556
2557         /* Allocate RX hardware ring descriptors. */
2558         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2559         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2560
2561         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2562                                       I40E_FDIR_QUEUE_ID, ring_size,
2563                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2564         if (!rz) {
2565                 i40e_dev_rx_queue_release(rxq);
2566                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2567                 return I40E_ERR_NO_MEMORY;
2568         }
2569
2570         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2571         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2572         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2573         rxq->vsi = pf->fdir.fdir_vsi;
2574
2575         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2576         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2577
2578         /*
2579          * Don't need to allocate software ring and reset for the fdir
2580          * rx queue, just set the queue has been configured.
2581          */
2582         rxq->q_set = TRUE;
2583         pf->fdir.rxq = rxq;
2584
2585         return I40E_SUCCESS;
2586 }
2587
2588 void
2589 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2590         struct rte_eth_rxq_info *qinfo)
2591 {
2592         struct i40e_rx_queue *rxq;
2593
2594         rxq = dev->data->rx_queues[queue_id];
2595
2596         qinfo->mp = rxq->mp;
2597         qinfo->scattered_rx = dev->data->scattered_rx;
2598         qinfo->nb_desc = rxq->nb_rx_desc;
2599
2600         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2601         qinfo->conf.rx_drop_en = rxq->drop_en;
2602         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2603 }
2604
2605 void
2606 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2607         struct rte_eth_txq_info *qinfo)
2608 {
2609         struct i40e_tx_queue *txq;
2610
2611         txq = dev->data->tx_queues[queue_id];
2612
2613         qinfo->nb_desc = txq->nb_tx_desc;
2614
2615         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2616         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2617         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2618
2619         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2620         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2621         qinfo->conf.txq_flags = txq->txq_flags;
2622         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2623 }
2624
2625 void __attribute__((cold))
2626 i40e_set_rx_function(struct rte_eth_dev *dev)
2627 {
2628         struct i40e_adapter *ad =
2629                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2630         uint16_t rx_using_sse, i;
2631         /* In order to allow Vector Rx there are a few configuration
2632          * conditions to be met and Rx Bulk Allocation should be allowed.
2633          */
2634         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2635                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2636                     !ad->rx_bulk_alloc_allowed) {
2637                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2638                                      " Vector Rx preconditions",
2639                                      dev->data->port_id);
2640
2641                         ad->rx_vec_allowed = false;
2642                 }
2643                 if (ad->rx_vec_allowed) {
2644                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2645                                 struct i40e_rx_queue *rxq =
2646                                         dev->data->rx_queues[i];
2647
2648                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2649                                         ad->rx_vec_allowed = false;
2650                                         break;
2651                                 }
2652                         }
2653                 }
2654         }
2655
2656         if (dev->data->scattered_rx) {
2657                 /* Set the non-LRO scattered callback: there are Vector and
2658                  * single allocation versions.
2659                  */
2660                 if (ad->rx_vec_allowed) {
2661                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2662                                             "callback (port=%d).",
2663                                      dev->data->port_id);
2664
2665                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2666                 } else {
2667                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2668                                            "allocation callback (port=%d).",
2669                                      dev->data->port_id);
2670                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2671                 }
2672         /* If parameters allow we are going to choose between the following
2673          * callbacks:
2674          *    - Vector
2675          *    - Bulk Allocation
2676          *    - Single buffer allocation (the simplest one)
2677          */
2678         } else if (ad->rx_vec_allowed) {
2679                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2680                                     "burst size no less than %d (port=%d).",
2681                              RTE_I40E_DESCS_PER_LOOP,
2682                              dev->data->port_id);
2683
2684                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2685         } else if (ad->rx_bulk_alloc_allowed) {
2686                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2687                                     "satisfied. Rx Burst Bulk Alloc function "
2688                                     "will be used on port=%d.",
2689                              dev->data->port_id);
2690
2691                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2692         } else {
2693                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2694                                     "satisfied, or Scattered Rx is requested "
2695                                     "(port=%d).",
2696                              dev->data->port_id);
2697
2698                 dev->rx_pkt_burst = i40e_recv_pkts;
2699         }
2700
2701         /* Propagate information about RX function choice through all queues. */
2702         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2703                 rx_using_sse =
2704                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2705                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2706
2707                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2708                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2709
2710                         if (rxq)
2711                                 rxq->rx_using_sse = rx_using_sse;
2712                 }
2713         }
2714 }
2715
2716 void __attribute__((cold))
2717 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2718 {
2719         struct i40e_adapter *ad =
2720                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2721
2722         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2723         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2724                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2725                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2726                         PMD_INIT_LOG(DEBUG, "Vector tx"
2727                                      " can be enabled on this txq.");
2728
2729                 } else {
2730                         ad->tx_vec_allowed = false;
2731                 }
2732         } else {
2733                 ad->tx_simple_allowed = false;
2734         }
2735 }
2736
2737 void __attribute__((cold))
2738 i40e_set_tx_function(struct rte_eth_dev *dev)
2739 {
2740         struct i40e_adapter *ad =
2741                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2742         int i;
2743
2744         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2745                 if (ad->tx_vec_allowed) {
2746                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2747                                 struct i40e_tx_queue *txq =
2748                                         dev->data->tx_queues[i];
2749
2750                                 if (txq && i40e_txq_vec_setup(txq)) {
2751                                         ad->tx_vec_allowed = false;
2752                                         break;
2753                                 }
2754                         }
2755                 }
2756         }
2757
2758         if (ad->tx_simple_allowed) {
2759                 if (ad->tx_vec_allowed) {
2760                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2761                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2762                 } else {
2763                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2764                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2765                 }
2766         } else {
2767                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2768                 dev->tx_pkt_burst = i40e_xmit_pkts;
2769         }
2770 }
2771
2772 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2773 int __attribute__((weak))
2774 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2775 {
2776         return -1;
2777 }
2778
2779 uint16_t __attribute__((weak))
2780 i40e_recv_pkts_vec(
2781         void __rte_unused *rx_queue,
2782         struct rte_mbuf __rte_unused **rx_pkts,
2783         uint16_t __rte_unused nb_pkts)
2784 {
2785         return 0;
2786 }
2787
2788 uint16_t __attribute__((weak))
2789 i40e_recv_scattered_pkts_vec(
2790         void __rte_unused *rx_queue,
2791         struct rte_mbuf __rte_unused **rx_pkts,
2792         uint16_t __rte_unused nb_pkts)
2793 {
2794         return 0;
2795 }
2796
2797 int __attribute__((weak))
2798 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2799 {
2800         return -1;
2801 }
2802
2803 int __attribute__((weak))
2804 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2805 {
2806         return -1;
2807 }
2808
2809 void __attribute__((weak))
2810 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2811 {
2812         return;
2813 }
2814
2815 uint16_t __attribute__((weak))
2816 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2817                    struct rte_mbuf __rte_unused **tx_pkts,
2818                    uint16_t __rte_unused nb_pkts)
2819 {
2820         return 0;
2821 }