drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_OUTER_IPV4 |     \
  59                 PKT_TX_OUTER_IPV6 |     \
  60                 PKT_TX_IPV4 |           \
  61                 PKT_TX_IPV6 |           \
  62                 PKT_TX_IP_CKSUM |       \
  63                 PKT_TX_L4_MASK |        \
  64                 PKT_TX_OUTER_IP_CKSUM | \
  65                 PKT_TX_TCP_SEG |        \
  66                 PKT_TX_QINQ_PKT |       \
  67                 PKT_TX_VLAN_PKT |       \
  68                 PKT_TX_TUNNEL_MASK |    \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 ~(PKT_TX_OFFLOAD_MASK & I40E_TX_OFFLOAD_MASK)
  73
  74 static inline void
  75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  76 {
  77         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  78                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  79                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  80                 mb->vlan_tci =
  81                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  82                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  83                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  84         } else {
  85                 mb->vlan_tci = 0;
  86         }
  87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  88         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  89                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
  91                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
  92                 mb->vlan_tci_outer = mb->vlan_tci;
  93                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  96                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  97         } else {
  98                 mb->vlan_tci_outer = 0;
  99         }
 100 #endif
 101         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 102                    mb->vlan_tci, mb->vlan_tci_outer);
 103 }
 104
 105 /* Translate the rx descriptor status to pkt flags */
 106 static inline uint64_t
 107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 108 {
 109         uint64_t flags;
 110
 111         /* Check if RSS_HASH */
 112         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 113                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 114                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 115
 116         /* Check if FDIR Match */
 117         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 118                                                         PKT_RX_FDIR : 0);
 119
 120         return flags;
 121 }
 122
 123 static inline uint64_t
 124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 125 {
 126         uint64_t flags = 0;
 127         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 128
 129 #define I40E_RX_ERR_BITS 0x3f
 130         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 131                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 132                 return flags;
 133         }
 134
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 136                 flags |= PKT_RX_IP_CKSUM_BAD;
 137         else
 138                 flags |= PKT_RX_IP_CKSUM_GOOD;
 139
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 141                 flags |= PKT_RX_L4_CKSUM_BAD;
 142         else
 143                 flags |= PKT_RX_L4_CKSUM_GOOD;
 144
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 146                 flags |= PKT_RX_EIP_CKSUM_BAD;
 147
 148         return flags;
 149 }
 150
 151 /* Function to check and set the ieee1588 timesync index and get the
 152  * appropriate flags.
 153  */
 154 #ifdef RTE_LIBRTE_IEEE1588
 155 static inline uint64_t
 156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 157 {
 158         uint64_t pkt_flags = 0;
 159         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 160                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 161                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 162
 163         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 164                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 165                 pkt_flags = PKT_RX_IEEE1588_PTP;
 166         if (tsyn & 0x04) {
 167                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 168                 mb->timesync = tsyn & 0x03;
 169         }
 170
 171         return pkt_flags;
 172 }
 173 #endif
 174
 175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 176 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 177 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 178 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 179 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 180
 181 static inline uint64_t
 182 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 183 {
 184         uint64_t flags = 0;
 185 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 186         uint16_t flexbh, flexbl;
 187
 188         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 189                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 190                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 191         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 192                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 193                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 194
 195
 196         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 197                 mb->hash.fdir.hi =
 198                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 199                 flags |= PKT_RX_FDIR_ID;
 200         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 201                 mb->hash.fdir.hi =
 202                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 203                 flags |= PKT_RX_FDIR_FLX;
 204         }
 205         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 206                 mb->hash.fdir.lo =
 207                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 208                 flags |= PKT_RX_FDIR_FLX;
 209         }
 210 #else
 211         mb->hash.fdir.hi =
 212                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 213         flags |= PKT_RX_FDIR_ID;
 214 #endif
 215         return flags;
 216 }
 217
 218 static inline void
 219 i40e_parse_tunneling_params(uint64_t ol_flags,
 220                             union i40e_tx_offload tx_offload,
 221                             uint32_t *cd_tunneling)
 222 {
 223         /* EIPT: External (outer) IP header type */
 224         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 225                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 226         else if (ol_flags & PKT_TX_OUTER_IPV4)
 227                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 228         else if (ol_flags & PKT_TX_OUTER_IPV6)
 229                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 230
 231         /* EIPLEN: External (outer) IP header length, in DWords */
 232         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 233                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 234
 235         /* L4TUNT: L4 Tunneling Type */
 236         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 237         case PKT_TX_TUNNEL_IPIP:
 238                 /* for non UDP / GRE tunneling, set to 00b */
 239                 break;
 240         case PKT_TX_TUNNEL_VXLAN:
 241         case PKT_TX_TUNNEL_GENEVE:
 242                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 243                 break;
 244         case PKT_TX_TUNNEL_GRE:
 245                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 246                 break;
 247         default:
 248                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 249                 return;
 250         }
 251
 252         /* L4TUNLEN: L4 Tunneling Length, in Words
 253          *
 254          * We depend on app to set rte_mbuf.l2_len correctly.
 255          * For IP in GRE it should be set to the length of the GRE
 256          * header;
 257          * for MAC in GRE or MAC in UDP it should be set to the length
 258          * of the GRE or UDP headers plus the inner MAC up to including
 259          * its last Ethertype.
 260          */
 261         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 262                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 263 }
 264
 265 static inline void
 266 i40e_txd_enable_checksum(uint64_t ol_flags,
 267                         uint32_t *td_cmd,
 268                         uint32_t *td_offset,
 269                         union i40e_tx_offload tx_offload)
 270 {
 271         /* Set MACLEN */
 272         if (ol_flags & PKT_TX_TUNNEL_MASK)
 273                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 274                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 275         else
 276                 *td_offset |= (tx_offload.l2_len >> 1)
 277                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 278
 279         /* Enable L3 checksum offloads */
 280         if (ol_flags & PKT_TX_IP_CKSUM) {
 281                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 282                 *td_offset |= (tx_offload.l3_len >> 2)
 283                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 284         } else if (ol_flags & PKT_TX_IPV4) {
 285                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 286                 *td_offset |= (tx_offload.l3_len >> 2)
 287                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 288         } else if (ol_flags & PKT_TX_IPV6) {
 289                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 290                 *td_offset |= (tx_offload.l3_len >> 2)
 291                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 292         }
 293
 294         if (ol_flags & PKT_TX_TCP_SEG) {
 295                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 296                 *td_offset |= (tx_offload.l4_len >> 2)
 297                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 298                 return;
 299         }
 300
 301         /* Enable L4 checksum offloads */
 302         switch (ol_flags & PKT_TX_L4_MASK) {
 303         case PKT_TX_TCP_CKSUM:
 304                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 305                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 306                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 307                 break;
 308         case PKT_TX_SCTP_CKSUM:
 309                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 310                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 311                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 312                 break;
 313         case PKT_TX_UDP_CKSUM:
 314                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 315                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 316                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 317                 break;
 318         default:
 319                 break;
 320         }
 321 }
 322
 323 /* Construct the tx flags */
 324 static inline uint64_t
 325 i40e_build_ctob(uint32_t td_cmd,
 326                 uint32_t td_offset,
 327                 unsigned int size,
 328                 uint32_t td_tag)
 329 {
 330         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 331                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 332                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 333                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 334                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 335 }
 336
 337 static inline int
 338 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 339 {
 340         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 341         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 342         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 343         uint16_t nb_tx_desc = txq->nb_tx_desc;
 344         uint16_t desc_to_clean_to;
 345         uint16_t nb_tx_to_clean;
 346
 347         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 348         if (desc_to_clean_to >= nb_tx_desc)
 349                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 350
 351         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 352         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 353                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 354                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 355                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 356                         "(port=%d queue=%d)", desc_to_clean_to,
 357                                 txq->port_id, txq->queue_id);
 358                 return -1;
 359         }
 360
 361         if (last_desc_cleaned > desc_to_clean_to)
 362                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 363                                                         desc_to_clean_to);
 364         else
 365                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 366                                         last_desc_cleaned);
 367
 368         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 369
 370         txq->last_desc_cleaned = desc_to_clean_to;
 371         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 372
 373         return 0;
 374 }
 375
 376 static inline int
 377 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 378 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 379 #else
 380 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 381 #endif
 382 {
 383         int ret = 0;
 384
 385 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 386         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 387                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 388                              "rxq->rx_free_thresh=%d, "
 389                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 390                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 391                 ret = -EINVAL;
 392         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 393                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 394                              "rxq->rx_free_thresh=%d, "
 395                              "rxq->nb_rx_desc=%d",
 396                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 397                 ret = -EINVAL;
 398         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 399                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 400                              "rxq->nb_rx_desc=%d, "
 401                              "rxq->rx_free_thresh=%d",
 402                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 403                 ret = -EINVAL;
 404         }
 405 #else
 406         ret = -EINVAL;
 407 #endif
 408
 409         return ret;
 410 }
 411
 412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 413 #define I40E_LOOK_AHEAD 8
 414 #if (I40E_LOOK_AHEAD != 8)
 415 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 416 #endif
 417 static inline int
 418 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 419 {
 420         volatile union i40e_rx_desc *rxdp;
 421         struct i40e_rx_entry *rxep;
 422         struct rte_mbuf *mb;
 423         uint16_t pkt_len;
 424         uint64_t qword1;
 425         uint32_t rx_status;
 426         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 427         int32_t i, j, nb_rx = 0;
 428         uint64_t pkt_flags;
 429         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 430
 431         rxdp = &rxq->rx_ring[rxq->rx_tail];
 432         rxep = &rxq->sw_ring[rxq->rx_tail];
 433
 434         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 435         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 436                                 I40E_RXD_QW1_STATUS_SHIFT;
 437
 438         /* Make sure there is at least 1 packet to receive */
 439         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 440                 return 0;
 441
 442         /**
 443          * Scan LOOK_AHEAD descriptors at a time to determine which
 444          * descriptors reference packets that are ready to be received.
 445          */
 446         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 447                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 448                 /* Read desc statuses backwards to avoid race condition */
 449                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 450                         qword1 = rte_le_to_cpu_64(\
 451                                 rxdp[j].wb.qword1.status_error_len);
 452                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 453                                         I40E_RXD_QW1_STATUS_SHIFT;
 454                 }
 455
 456                 rte_smp_rmb();
 457
 458                 /* Compute how many status bits were set */
 459                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 460                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 461
 462                 nb_rx += nb_dd;
 463
 464                 /* Translate descriptor info to mbuf parameters */
 465                 for (j = 0; j < nb_dd; j++) {
 466                         mb = rxep[j].mbuf;
 467                         qword1 = rte_le_to_cpu_64(\
 468                                 rxdp[j].wb.qword1.status_error_len);
 469                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 470                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 471                         mb->data_len = pkt_len;
 472                         mb->pkt_len = pkt_len;
 473                         mb->ol_flags = 0;
 474                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 475                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 476                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 477                         mb->packet_type =
 478                                 ptype_tbl[(uint8_t)((qword1 &
 479                                 I40E_RXD_QW1_PTYPE_MASK) >>
 480                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 481                         if (pkt_flags & PKT_RX_RSS_HASH)
 482                                 mb->hash.rss = rte_le_to_cpu_32(\
 483                                         rxdp[j].wb.qword0.hi_dword.rss);
 484                         if (pkt_flags & PKT_RX_FDIR)
 485                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 486
 487 #ifdef RTE_LIBRTE_IEEE1588
 488                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 489 #endif
 490                         mb->ol_flags |= pkt_flags;
 491
 492                 }
 493
 494                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 495                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 496
 497                 if (nb_dd != I40E_LOOK_AHEAD)
 498                         break;
 499         }
 500
 501         /* Clear software ring entries */
 502         for (i = 0; i < nb_rx; i++)
 503                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 504
 505         return nb_rx;
 506 }
 507
 508 static inline uint16_t
 509 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 510                         struct rte_mbuf **rx_pkts,
 511                         uint16_t nb_pkts)
 512 {
 513         uint16_t i;
 514         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 515
 516         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 517
 518         for (i = 0; i < nb_pkts; i++)
 519                 rx_pkts[i] = stage[i];
 520
 521         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 522         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 523
 524         return nb_pkts;
 525 }
 526
 527 static inline int
 528 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 529 {
 530         volatile union i40e_rx_desc *rxdp;
 531         struct i40e_rx_entry *rxep;
 532         struct rte_mbuf *mb;
 533         uint16_t alloc_idx, i;
 534         uint64_t dma_addr;
 535         int diag;
 536
 537         /* Allocate buffers in bulk */
 538         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 539                                 (rxq->rx_free_thresh - 1));
 540         rxep = &(rxq->sw_ring[alloc_idx]);
 541         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 542                                         rxq->rx_free_thresh);
 543         if (unlikely(diag != 0)) {
 544                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 545                 return -ENOMEM;
 546         }
 547
 548         rxdp = &rxq->rx_ring[alloc_idx];
 549         for (i = 0; i < rxq->rx_free_thresh; i++) {
 550                 if (likely(i < (rxq->rx_free_thresh - 1)))
 551                         /* Prefetch next mbuf */
 552                         rte_prefetch0(rxep[i + 1].mbuf);
 553
 554                 mb = rxep[i].mbuf;
 555                 rte_mbuf_refcnt_set(mb, 1);
 556                 mb->next = NULL;
 557                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 558                 mb->nb_segs = 1;
 559                 mb->port = rxq->port_id;
 560                 dma_addr = rte_cpu_to_le_64(\
 561                         rte_mbuf_data_iova_default(mb));
 562                 rxdp[i].read.hdr_addr = 0;
 563                 rxdp[i].read.pkt_addr = dma_addr;
 564         }
 565
 566         /* Update rx tail regsiter */
 567         rte_wmb();
 568         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 569
 570         rxq->rx_free_trigger =
 571                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 572         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 573                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 574
 575         return 0;
 576 }
 577
 578 static inline uint16_t
 579 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 580 {
 581         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 582         struct rte_eth_dev *dev;
 583         uint16_t nb_rx = 0;
 584
 585         if (!nb_pkts)
 586                 return 0;
 587
 588         if (rxq->rx_nb_avail)
 589                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 590
 591         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 592         rxq->rx_next_avail = 0;
 593         rxq->rx_nb_avail = nb_rx;
 594         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 595
 596         if (rxq->rx_tail > rxq->rx_free_trigger) {
 597                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 598                         uint16_t i, j;
 599
 600                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 601                         dev->data->rx_mbuf_alloc_failed +=
 602                                 rxq->rx_free_thresh;
 603
 604                         rxq->rx_nb_avail = 0;
 605                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 606                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 607                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 608
 609                         return 0;
 610                 }
 611         }
 612
 613         if (rxq->rx_tail >= rxq->nb_rx_desc)
 614                 rxq->rx_tail = 0;
 615
 616         if (rxq->rx_nb_avail)
 617                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 618
 619         return 0;
 620 }
 621
 622 static uint16_t
 623 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 624                           struct rte_mbuf **rx_pkts,
 625                           uint16_t nb_pkts)
 626 {
 627         uint16_t nb_rx = 0, n, count;
 628
 629         if (unlikely(nb_pkts == 0))
 630                 return 0;
 631
 632         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 633                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 634
 635         while (nb_pkts) {
 636                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 637                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 638                 nb_rx = (uint16_t)(nb_rx + count);
 639                 nb_pkts = (uint16_t)(nb_pkts - count);
 640                 if (count < n)
 641                         break;
 642         }
 643
 644         return nb_rx;
 645 }
 646 #else
 647 static uint16_t
 648 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 649                           struct rte_mbuf __rte_unused **rx_pkts,
 650                           uint16_t __rte_unused nb_pkts)
 651 {
 652         return 0;
 653 }
 654 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 655
 656 uint16_t
 657 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 658 {
 659         struct i40e_rx_queue *rxq;
 660         volatile union i40e_rx_desc *rx_ring;
 661         volatile union i40e_rx_desc *rxdp;
 662         union i40e_rx_desc rxd;
 663         struct i40e_rx_entry *sw_ring;
 664         struct i40e_rx_entry *rxe;
 665         struct rte_eth_dev *dev;
 666         struct rte_mbuf *rxm;
 667         struct rte_mbuf *nmb;
 668         uint16_t nb_rx;
 669         uint32_t rx_status;
 670         uint64_t qword1;
 671         uint16_t rx_packet_len;
 672         uint16_t rx_id, nb_hold;
 673         uint64_t dma_addr;
 674         uint64_t pkt_flags;
 675         uint32_t *ptype_tbl;
 676
 677         nb_rx = 0;
 678         nb_hold = 0;
 679         rxq = rx_queue;
 680         rx_id = rxq->rx_tail;
 681         rx_ring = rxq->rx_ring;
 682         sw_ring = rxq->sw_ring;
 683         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 684
 685         while (nb_rx < nb_pkts) {
 686                 rxdp = &rx_ring[rx_id];
 687                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 688                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 689                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 690
 691                 /* Check the DD bit first */
 692                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 693                         break;
 694
 695                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 696                 if (unlikely(!nmb)) {
 697                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 698                         dev->data->rx_mbuf_alloc_failed++;
 699                         break;
 700                 }
 701
 702                 rxd = *rxdp;
 703                 nb_hold++;
 704                 rxe = &sw_ring[rx_id];
 705                 rx_id++;
 706                 if (unlikely(rx_id == rxq->nb_rx_desc))
 707                         rx_id = 0;
 708
 709                 /* Prefetch next mbuf */
 710                 rte_prefetch0(sw_ring[rx_id].mbuf);
 711
 712                 /**
 713                  * When next RX descriptor is on a cache line boundary,
 714                  * prefetch the next 4 RX descriptors and next 8 pointers
 715                  * to mbufs.
 716                  */
 717                 if ((rx_id & 0x3) == 0) {
 718                         rte_prefetch0(&rx_ring[rx_id]);
 719                         rte_prefetch0(&sw_ring[rx_id]);
 720                 }
 721                 rxm = rxe->mbuf;
 722                 rxe->mbuf = nmb;
 723                 dma_addr =
 724                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 725                 rxdp->read.hdr_addr = 0;
 726                 rxdp->read.pkt_addr = dma_addr;
 727
 728                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 729                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 730
 731                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 732                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 733                 rxm->nb_segs = 1;
 734                 rxm->next = NULL;
 735                 rxm->pkt_len = rx_packet_len;
 736                 rxm->data_len = rx_packet_len;
 737                 rxm->port = rxq->port_id;
 738                 rxm->ol_flags = 0;
 739                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 740                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 741                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 742                 rxm->packet_type =
 743                         ptype_tbl[(uint8_t)((qword1 &
 744                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 745                 if (pkt_flags & PKT_RX_RSS_HASH)
 746                         rxm->hash.rss =
 747                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 748                 if (pkt_flags & PKT_RX_FDIR)
 749                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 750
 751 #ifdef RTE_LIBRTE_IEEE1588
 752                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 753 #endif
 754                 rxm->ol_flags |= pkt_flags;
 755
 756                 rx_pkts[nb_rx++] = rxm;
 757         }
 758         rxq->rx_tail = rx_id;
 759
 760         /**
 761          * If the number of free RX descriptors is greater than the RX free
 762          * threshold of the queue, advance the receive tail register of queue.
 763          * Update that register with the value of the last processed RX
 764          * descriptor minus 1.
 765          */
 766         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 767         if (nb_hold > rxq->rx_free_thresh) {
 768                 rx_id = (uint16_t) ((rx_id == 0) ?
 769                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 770                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 771                 nb_hold = 0;
 772         }
 773         rxq->nb_rx_hold = nb_hold;
 774
 775         return nb_rx;
 776 }
 777
 778 uint16_t
 779 i40e_recv_scattered_pkts(void *rx_queue,
 780                          struct rte_mbuf **rx_pkts,
 781                          uint16_t nb_pkts)
 782 {
 783         struct i40e_rx_queue *rxq = rx_queue;
 784         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 785         volatile union i40e_rx_desc *rxdp;
 786         union i40e_rx_desc rxd;
 787         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 788         struct i40e_rx_entry *rxe;
 789         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 790         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 791         struct rte_mbuf *nmb, *rxm;
 792         uint16_t rx_id = rxq->rx_tail;
 793         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 794         struct rte_eth_dev *dev;
 795         uint32_t rx_status;
 796         uint64_t qword1;
 797         uint64_t dma_addr;
 798         uint64_t pkt_flags;
 799         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 800
 801         while (nb_rx < nb_pkts) {
 802                 rxdp = &rx_ring[rx_id];
 803                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 804                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 805                                         I40E_RXD_QW1_STATUS_SHIFT;
 806
 807                 /* Check the DD bit */
 808                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 809                         break;
 810
 811                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 812                 if (unlikely(!nmb)) {
 813                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 814                         dev->data->rx_mbuf_alloc_failed++;
 815                         break;
 816                 }
 817
 818                 rxd = *rxdp;
 819                 nb_hold++;
 820                 rxe = &sw_ring[rx_id];
 821                 rx_id++;
 822                 if (rx_id == rxq->nb_rx_desc)
 823                         rx_id = 0;
 824
 825                 /* Prefetch next mbuf */
 826                 rte_prefetch0(sw_ring[rx_id].mbuf);
 827
 828                 /**
 829                  * When next RX descriptor is on a cache line boundary,
 830                  * prefetch the next 4 RX descriptors and next 8 pointers
 831                  * to mbufs.
 832                  */
 833                 if ((rx_id & 0x3) == 0) {
 834                         rte_prefetch0(&rx_ring[rx_id]);
 835                         rte_prefetch0(&sw_ring[rx_id]);
 836                 }
 837
 838                 rxm = rxe->mbuf;
 839                 rxe->mbuf = nmb;
 840                 dma_addr =
 841                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 842
 843                 /* Set data buffer address and data length of the mbuf */
 844                 rxdp->read.hdr_addr = 0;
 845                 rxdp->read.pkt_addr = dma_addr;
 846                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 847                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 848                 rxm->data_len = rx_packet_len;
 849                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 850
 851                 /**
 852                  * If this is the first buffer of the received packet, set the
 853                  * pointer to the first mbuf of the packet and initialize its
 854                  * context. Otherwise, update the total length and the number
 855                  * of segments of the current scattered packet, and update the
 856                  * pointer to the last mbuf of the current packet.
 857                  */
 858                 if (!first_seg) {
 859                         first_seg = rxm;
 860                         first_seg->nb_segs = 1;
 861                         first_seg->pkt_len = rx_packet_len;
 862                 } else {
 863                         first_seg->pkt_len =
 864                                 (uint16_t)(first_seg->pkt_len +
 865                                                 rx_packet_len);
 866                         first_seg->nb_segs++;
 867                         last_seg->next = rxm;
 868                 }
 869
 870                 /**
 871                  * If this is not the last buffer of the received packet,
 872                  * update the pointer to the last mbuf of the current scattered
 873                  * packet and continue to parse the RX ring.
 874                  */
 875                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 876                         last_seg = rxm;
 877                         continue;
 878                 }
 879
 880                 /**
 881                  * This is the last buffer of the received packet. If the CRC
 882                  * is not stripped by the hardware:
 883                  *  - Subtract the CRC length from the total packet length.
 884                  *  - If the last buffer only contains the whole CRC or a part
 885                  *  of it, free the mbuf associated to the last buffer. If part
 886                  *  of the CRC is also contained in the previous mbuf, subtract
 887                  *  the length of that CRC part from the data length of the
 888                  *  previous mbuf.
 889                  */
 890                 rxm->next = NULL;
 891                 if (unlikely(rxq->crc_len > 0)) {
 892                         first_seg->pkt_len -= ETHER_CRC_LEN;
 893                         if (rx_packet_len <= ETHER_CRC_LEN) {
 894                                 rte_pktmbuf_free_seg(rxm);
 895                                 first_seg->nb_segs--;
 896                                 last_seg->data_len =
 897                                         (uint16_t)(last_seg->data_len -
 898                                         (ETHER_CRC_LEN - rx_packet_len));
 899                                 last_seg->next = NULL;
 900                         } else
 901                                 rxm->data_len = (uint16_t)(rx_packet_len -
 902                                                                 ETHER_CRC_LEN);
 903                 }
 904
 905                 first_seg->port = rxq->port_id;
 906                 first_seg->ol_flags = 0;
 907                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 908                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 909                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 910                 first_seg->packet_type =
 911                         ptype_tbl[(uint8_t)((qword1 &
 912                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 913                 if (pkt_flags & PKT_RX_RSS_HASH)
 914                         first_seg->hash.rss =
 915                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 916                 if (pkt_flags & PKT_RX_FDIR)
 917                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 918
 919 #ifdef RTE_LIBRTE_IEEE1588
 920                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 921 #endif
 922                 first_seg->ol_flags |= pkt_flags;
 923
 924                 /* Prefetch data of first segment, if configured to do so. */
 925                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 926                         first_seg->data_off));
 927                 rx_pkts[nb_rx++] = first_seg;
 928                 first_seg = NULL;
 929         }
 930
 931         /* Record index of the next RX descriptor to probe. */
 932         rxq->rx_tail = rx_id;
 933         rxq->pkt_first_seg = first_seg;
 934         rxq->pkt_last_seg = last_seg;
 935
 936         /**
 937          * If the number of free RX descriptors is greater than the RX free
 938          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 939          * register. Update the RDT with the value of the last processed RX
 940          * descriptor minus 1, to guarantee that the RDT register is never
 941          * equal to the RDH register, which creates a "full" ring situtation
 942          * from the hardware point of view.
 943          */
 944         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 945         if (nb_hold > rxq->rx_free_thresh) {
 946                 rx_id = (uint16_t)(rx_id == 0 ?
 947                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 948                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 949                 nb_hold = 0;
 950         }
 951         rxq->nb_rx_hold = nb_hold;
 952
 953         return nb_rx;
 954 }
 955
 956 /* Check if the context descriptor is needed for TX offloading */
 957 static inline uint16_t
 958 i40e_calc_context_desc(uint64_t flags)
 959 {
 960         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 961                 PKT_TX_TCP_SEG |
 962                 PKT_TX_QINQ_PKT |
 963                 PKT_TX_TUNNEL_MASK;
 964
 965 #ifdef RTE_LIBRTE_IEEE1588
 966         mask |= PKT_TX_IEEE1588_TMST;
 967 #endif
 968
 969         return (flags & mask) ? 1 : 0;
 970 }
 971
 972 /* set i40e TSO context descriptor */
 973 static inline uint64_t
 974 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 975 {
 976         uint64_t ctx_desc = 0;
 977         uint32_t cd_cmd, hdr_len, cd_tso_len;
 978
 979         if (!tx_offload.l4_len) {
 980                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 981                 return ctx_desc;
 982         }
 983
 984         /**
 985          * in case of non tunneling packet, the outer_l2_len and
 986          * outer_l3_len must be 0.
 987          */
 988         hdr_len = tx_offload.outer_l2_len +
 989                 tx_offload.outer_l3_len +
 990                 tx_offload.l2_len +
 991                 tx_offload.l3_len +
 992                 tx_offload.l4_len;
 993
 994         cd_cmd = I40E_TX_CTX_DESC_TSO;
 995         cd_tso_len = mbuf->pkt_len - hdr_len;
 996         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 997                 ((uint64_t)cd_tso_len <<
 998                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 999                 ((uint64_t)mbuf->tso_segsz <<
1000                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1001
1002         return ctx_desc;
1003 }
1004
1005 uint16_t
1006 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1007 {
1008         struct i40e_tx_queue *txq;
1009         struct i40e_tx_entry *sw_ring;
1010         struct i40e_tx_entry *txe, *txn;
1011         volatile struct i40e_tx_desc *txd;
1012         volatile struct i40e_tx_desc *txr;
1013         struct rte_mbuf *tx_pkt;
1014         struct rte_mbuf *m_seg;
1015         uint32_t cd_tunneling_params;
1016         uint16_t tx_id;
1017         uint16_t nb_tx;
1018         uint32_t td_cmd;
1019         uint32_t td_offset;
1020         uint32_t td_tag;
1021         uint64_t ol_flags;
1022         uint16_t nb_used;
1023         uint16_t nb_ctx;
1024         uint16_t tx_last;
1025         uint16_t slen;
1026         uint64_t buf_dma_addr;
1027         union i40e_tx_offload tx_offload = {0};
1028
1029         txq = tx_queue;
1030         sw_ring = txq->sw_ring;
1031         txr = txq->tx_ring;
1032         tx_id = txq->tx_tail;
1033         txe = &sw_ring[tx_id];
1034
1035         /* Check if the descriptor ring needs to be cleaned. */
1036         if (txq->nb_tx_free < txq->tx_free_thresh)
1037                 i40e_xmit_cleanup(txq);
1038
1039         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1040                 td_cmd = 0;
1041                 td_tag = 0;
1042                 td_offset = 0;
1043
1044                 tx_pkt = *tx_pkts++;
1045                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1046
1047                 ol_flags = tx_pkt->ol_flags;
1048                 tx_offload.l2_len = tx_pkt->l2_len;
1049                 tx_offload.l3_len = tx_pkt->l3_len;
1050                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1051                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1052                 tx_offload.l4_len = tx_pkt->l4_len;
1053                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1054
1055                 /* Calculate the number of context descriptors needed. */
1056                 nb_ctx = i40e_calc_context_desc(ol_flags);
1057
1058                 /**
1059                  * The number of descriptors that must be allocated for
1060                  * a packet equals to the number of the segments of that
1061                  * packet plus 1 context descriptor if needed.
1062                  */
1063                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1064                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1065
1066                 /* Circular ring */
1067                 if (tx_last >= txq->nb_tx_desc)
1068                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1069
1070                 if (nb_used > txq->nb_tx_free) {
1071                         if (i40e_xmit_cleanup(txq) != 0) {
1072                                 if (nb_tx == 0)
1073                                         return 0;
1074                                 goto end_of_tx;
1075                         }
1076                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1077                                 while (nb_used > txq->nb_tx_free) {
1078                                         if (i40e_xmit_cleanup(txq) != 0) {
1079                                                 if (nb_tx == 0)
1080                                                         return 0;
1081                                                 goto end_of_tx;
1082                                         }
1083                                 }
1084                         }
1085                 }
1086
1087                 /* Descriptor based VLAN insertion */
1088                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1089                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1090                         td_tag = tx_pkt->vlan_tci;
1091                 }
1092
1093                 /* Always enable CRC offload insertion */
1094                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1095
1096                 /* Fill in tunneling parameters if necessary */
1097                 cd_tunneling_params = 0;
1098                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1099                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1100                                                     &cd_tunneling_params);
1101                 /* Enable checksum offloading */
1102                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1103                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1104                                                  &td_offset, tx_offload);
1105
1106                 if (nb_ctx) {
1107                         /* Setup TX context descriptor if required */
1108                         volatile struct i40e_tx_context_desc *ctx_txd =
1109                                 (volatile struct i40e_tx_context_desc *)\
1110                                                         &txr[tx_id];
1111                         uint16_t cd_l2tag2 = 0;
1112                         uint64_t cd_type_cmd_tso_mss =
1113                                 I40E_TX_DESC_DTYPE_CONTEXT;
1114
1115                         txn = &sw_ring[txe->next_id];
1116                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1117                         if (txe->mbuf != NULL) {
1118                                 rte_pktmbuf_free_seg(txe->mbuf);
1119                                 txe->mbuf = NULL;
1120                         }
1121
1122                         /* TSO enabled means no timestamp */
1123                         if (ol_flags & PKT_TX_TCP_SEG)
1124                                 cd_type_cmd_tso_mss |=
1125                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1126                         else {
1127 #ifdef RTE_LIBRTE_IEEE1588
1128                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1129                                         cd_type_cmd_tso_mss |=
1130                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1131                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1132 #endif
1133                         }
1134
1135                         ctx_txd->tunneling_params =
1136                                 rte_cpu_to_le_32(cd_tunneling_params);
1137                         if (ol_flags & PKT_TX_QINQ_PKT) {
1138                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1139                                 cd_type_cmd_tso_mss |=
1140                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1141                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1142                         }
1143                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1144                         ctx_txd->type_cmd_tso_mss =
1145                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1146
1147                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1148                                 "tunneling_params: %#x;\n"
1149                                 "l2tag2: %#hx;\n"
1150                                 "rsvd: %#hx;\n"
1151                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1152                                 tx_pkt, tx_id,
1153                                 ctx_txd->tunneling_params,
1154                                 ctx_txd->l2tag2,
1155                                 ctx_txd->rsvd,
1156                                 ctx_txd->type_cmd_tso_mss);
1157
1158                         txe->last_id = tx_last;
1159                         tx_id = txe->next_id;
1160                         txe = txn;
1161                 }
1162
1163                 m_seg = tx_pkt;
1164                 do {
1165                         txd = &txr[tx_id];
1166                         txn = &sw_ring[txe->next_id];
1167
1168                         if (txe->mbuf)
1169                                 rte_pktmbuf_free_seg(txe->mbuf);
1170                         txe->mbuf = m_seg;
1171
1172                         /* Setup TX Descriptor */
1173                         slen = m_seg->data_len;
1174                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1175
1176                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1177                                 "buf_dma_addr: %#"PRIx64";\n"
1178                                 "td_cmd: %#x;\n"
1179                                 "td_offset: %#x;\n"
1180                                 "td_len: %u;\n"
1181                                 "td_tag: %#x;\n",
1182                                 tx_pkt, tx_id, buf_dma_addr,
1183                                 td_cmd, td_offset, slen, td_tag);
1184
1185                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1186                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1187                                                 td_offset, slen, td_tag);
1188                         txe->last_id = tx_last;
1189                         tx_id = txe->next_id;
1190                         txe = txn;
1191                         m_seg = m_seg->next;
1192                 } while (m_seg != NULL);
1193
1194                 /* The last packet data descriptor needs End Of Packet (EOP) */
1195                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1196                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1197                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1198
1199                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1200                         PMD_TX_FREE_LOG(DEBUG,
1201                                         "Setting RS bit on TXD id="
1202                                         "%4u (port=%d queue=%d)",
1203                                         tx_last, txq->port_id, txq->queue_id);
1204
1205                         td_cmd |= I40E_TX_DESC_CMD_RS;
1206
1207                         /* Update txq RS bit counters */
1208                         txq->nb_tx_used = 0;
1209                 }
1210
1211                 txd->cmd_type_offset_bsz |=
1212                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1213                                         I40E_TXD_QW1_CMD_SHIFT);
1214         }
1215
1216 end_of_tx:
1217         rte_wmb();
1218
1219         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1220                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1221                    (unsigned) tx_id, (unsigned) nb_tx);
1222
1223         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1224         txq->tx_tail = tx_id;
1225
1226         return nb_tx;
1227 }
1228
1229 static __rte_always_inline int
1230 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1231 {
1232         struct i40e_tx_entry *txep;
1233         uint16_t i;
1234
1235         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1236                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1237                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1238                 return 0;
1239
1240         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1241
1242         for (i = 0; i < txq->tx_rs_thresh; i++)
1243                 rte_prefetch0((txep + i)->mbuf);
1244
1245         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1246                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1247                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1248                         txep->mbuf = NULL;
1249                 }
1250         } else {
1251                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1252                         rte_pktmbuf_free_seg(txep->mbuf);
1253                         txep->mbuf = NULL;
1254                 }
1255         }
1256
1257         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1258         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1259         if (txq->tx_next_dd >= txq->nb_tx_desc)
1260                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1261
1262         return txq->tx_rs_thresh;
1263 }
1264
1265 /* Populate 4 descriptors with data from 4 mbufs */
1266 static inline void
1267 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1268 {
1269         uint64_t dma_addr;
1270         uint32_t i;
1271
1272         for (i = 0; i < 4; i++, txdp++, pkts++) {
1273                 dma_addr = rte_mbuf_data_iova(*pkts);
1274                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1275                 txdp->cmd_type_offset_bsz =
1276                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1277                                         (*pkts)->data_len, 0);
1278         }
1279 }
1280
1281 /* Populate 1 descriptor with data from 1 mbuf */
1282 static inline void
1283 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1284 {
1285         uint64_t dma_addr;
1286
1287         dma_addr = rte_mbuf_data_iova(*pkts);
1288         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1289         txdp->cmd_type_offset_bsz =
1290                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1291                                 (*pkts)->data_len, 0);
1292 }
1293
1294 /* Fill hardware descriptor ring with mbuf data */
1295 static inline void
1296 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1297                      struct rte_mbuf **pkts,
1298                      uint16_t nb_pkts)
1299 {
1300         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1301         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1302         const int N_PER_LOOP = 4;
1303         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1304         int mainpart, leftover;
1305         int i, j;
1306
1307         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1308         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1309         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1310                 for (j = 0; j < N_PER_LOOP; ++j) {
1311                         (txep + i + j)->mbuf = *(pkts + i + j);
1312                 }
1313                 tx4(txdp + i, pkts + i);
1314         }
1315         if (unlikely(leftover > 0)) {
1316                 for (i = 0; i < leftover; ++i) {
1317                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1318                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1319                 }
1320         }
1321 }
1322
1323 static inline uint16_t
1324 tx_xmit_pkts(struct i40e_tx_queue *txq,
1325              struct rte_mbuf **tx_pkts,
1326              uint16_t nb_pkts)
1327 {
1328         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1329         uint16_t n = 0;
1330
1331         /**
1332          * Begin scanning the H/W ring for done descriptors when the number
1333          * of available descriptors drops below tx_free_thresh. For each done
1334          * descriptor, free the associated buffer.
1335          */
1336         if (txq->nb_tx_free < txq->tx_free_thresh)
1337                 i40e_tx_free_bufs(txq);
1338
1339         /* Use available descriptor only */
1340         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1341         if (unlikely(!nb_pkts))
1342                 return 0;
1343
1344         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1345         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1346                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1347                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1348                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1349                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1350                                                 I40E_TXD_QW1_CMD_SHIFT);
1351                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1352                 txq->tx_tail = 0;
1353         }
1354
1355         /* Fill hardware descriptor ring with mbuf data */
1356         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1357         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1358
1359         /* Determin if RS bit needs to be set */
1360         if (txq->tx_tail > txq->tx_next_rs) {
1361                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1362                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1363                                                 I40E_TXD_QW1_CMD_SHIFT);
1364                 txq->tx_next_rs =
1365                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1366                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1367                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1368         }
1369
1370         if (txq->tx_tail >= txq->nb_tx_desc)
1371                 txq->tx_tail = 0;
1372
1373         /* Update the tx tail register */
1374         rte_wmb();
1375         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1376
1377         return nb_pkts;
1378 }
1379
1380 static uint16_t
1381 i40e_xmit_pkts_simple(void *tx_queue,
1382                       struct rte_mbuf **tx_pkts,
1383                       uint16_t nb_pkts)
1384 {
1385         uint16_t nb_tx = 0;
1386
1387         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1388                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1389                                                 tx_pkts, nb_pkts);
1390
1391         while (nb_pkts) {
1392                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1393                                                 I40E_TX_MAX_BURST);
1394
1395                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1396                                                 &tx_pkts[nb_tx], num);
1397                 nb_tx = (uint16_t)(nb_tx + ret);
1398                 nb_pkts = (uint16_t)(nb_pkts - ret);
1399                 if (ret < num)
1400                         break;
1401         }
1402
1403         return nb_tx;
1404 }
1405
1406 static uint16_t
1407 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1408                    uint16_t nb_pkts)
1409 {
1410         uint16_t nb_tx = 0;
1411         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1412
1413         while (nb_pkts) {
1414                 uint16_t ret, num;
1415
1416                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1417                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1418                                                 num);
1419                 nb_tx += ret;
1420                 nb_pkts -= ret;
1421                 if (ret < num)
1422                         break;
1423         }
1424
1425         return nb_tx;
1426 }
1427
1428 /*********************************************************************
1429  *
1430  *  TX prep functions
1431  *
1432  **********************************************************************/
1433 uint16_t
1434 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1435                 uint16_t nb_pkts)
1436 {
1437         int i, ret;
1438         uint64_t ol_flags;
1439         struct rte_mbuf *m;
1440
1441         for (i = 0; i < nb_pkts; i++) {
1442                 m = tx_pkts[i];
1443                 ol_flags = m->ol_flags;
1444
1445                 /* Check for m->nb_segs to not exceed the limits. */
1446                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1447                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1448                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1449                                 rte_errno = -EINVAL;
1450                                 return i;
1451                         }
1452                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1453                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1454                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1455                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1456                         /* MSS outside the range (256B - 9674B) are considered
1457                          * malicious
1458                          */
1459                         rte_errno = -EINVAL;
1460                         return i;
1461                 }
1462
1463                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1464                         rte_errno = -ENOTSUP;
1465                         return i;
1466                 }
1467
1468                 /* check the size of packet */
1469                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1470                         rte_errno = -EINVAL;
1471                         return i;
1472                 }
1473
1474 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1475                 ret = rte_validate_tx_offload(m);
1476                 if (ret != 0) {
1477                         rte_errno = ret;
1478                         return i;
1479                 }
1480 #endif
1481                 ret = rte_net_intel_cksum_prepare(m);
1482                 if (ret != 0) {
1483                         rte_errno = ret;
1484                         return i;
1485                 }
1486         }
1487         return i;
1488 }
1489
1490 /*
1491  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1492  * application used, which assume having sequential ones. But from driver's
1493  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1494  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1495  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1496  * use queue_idx from 0 to 95 to access queues, while real queue would be
1497  * different. This function will do a queue mapping to find VSI the queue
1498  * belongs to.
1499  */
1500 static struct i40e_vsi*
1501 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1502 {
1503         /* the queue in MAIN VSI range */
1504         if (queue_idx < pf->main_vsi->nb_qps)
1505                 return pf->main_vsi;
1506
1507         queue_idx -= pf->main_vsi->nb_qps;
1508
1509         /* queue_idx is greater than VMDQ VSIs range */
1510         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1511                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1512                 return NULL;
1513         }
1514
1515         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1516 }
1517
1518 static uint16_t
1519 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1520 {
1521         /* the queue in MAIN VSI range */
1522         if (queue_idx < pf->main_vsi->nb_qps)
1523                 return queue_idx;
1524
1525         /* It's VMDQ queues */
1526         queue_idx -= pf->main_vsi->nb_qps;
1527
1528         if (pf->nb_cfg_vmdq_vsi)
1529                 return queue_idx % pf->vmdq_nb_qps;
1530         else {
1531                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1532                 return (uint16_t)(-1);
1533         }
1534 }
1535
1536 int
1537 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1538 {
1539         struct i40e_rx_queue *rxq;
1540         int err;
1541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542
1543         PMD_INIT_FUNC_TRACE();
1544
1545         rxq = dev->data->rx_queues[rx_queue_id];
1546
1547         err = i40e_alloc_rx_queue_mbufs(rxq);
1548         if (err) {
1549                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1550                 return err;
1551         }
1552
1553         rte_wmb();
1554
1555         /* Init the RX tail regieter. */
1556         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1557
1558         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1559         if (err) {
1560                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1561                             rx_queue_id);
1562
1563                 i40e_rx_queue_release_mbufs(rxq);
1564                 i40e_reset_rx_queue(rxq);
1565                 return err;
1566         }
1567         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1568
1569         return 0;
1570 }
1571
1572 int
1573 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1574 {
1575         struct i40e_rx_queue *rxq;
1576         int err;
1577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578
1579         rxq = dev->data->rx_queues[rx_queue_id];
1580
1581         /*
1582          * rx_queue_id is queue id application refers to, while
1583          * rxq->reg_idx is the real queue index.
1584          */
1585         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1586         if (err) {
1587                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1588                             rx_queue_id);
1589                 return err;
1590         }
1591         i40e_rx_queue_release_mbufs(rxq);
1592         i40e_reset_rx_queue(rxq);
1593         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1594
1595         return 0;
1596 }
1597
1598 int
1599 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1600 {
1601         int err;
1602         struct i40e_tx_queue *txq;
1603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604
1605         PMD_INIT_FUNC_TRACE();
1606
1607         txq = dev->data->tx_queues[tx_queue_id];
1608
1609         /*
1610          * tx_queue_id is queue id application refers to, while
1611          * rxq->reg_idx is the real queue index.
1612          */
1613         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1614         if (err) {
1615                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1616                             tx_queue_id);
1617                 return err;
1618         }
1619         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1620
1621         return 0;
1622 }
1623
1624 int
1625 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1626 {
1627         struct i40e_tx_queue *txq;
1628         int err;
1629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630
1631         txq = dev->data->tx_queues[tx_queue_id];
1632
1633         /*
1634          * tx_queue_id is queue id application refers to, while
1635          * txq->reg_idx is the real queue index.
1636          */
1637         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1638         if (err) {
1639                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1640                             tx_queue_id);
1641                 return err;
1642         }
1643
1644         i40e_tx_queue_release_mbufs(txq);
1645         i40e_reset_tx_queue(txq);
1646         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1647
1648         return 0;
1649 }
1650
1651 const uint32_t *
1652 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1653 {
1654         static const uint32_t ptypes[] = {
1655                 /* refers to i40e_rxd_pkt_type_mapping() */
1656                 RTE_PTYPE_L2_ETHER,
1657                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1658                 RTE_PTYPE_L2_ETHER_LLDP,
1659                 RTE_PTYPE_L2_ETHER_ARP,
1660                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1661                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1662                 RTE_PTYPE_L4_FRAG,
1663                 RTE_PTYPE_L4_ICMP,
1664                 RTE_PTYPE_L4_NONFRAG,
1665                 RTE_PTYPE_L4_SCTP,
1666                 RTE_PTYPE_L4_TCP,
1667                 RTE_PTYPE_L4_UDP,
1668                 RTE_PTYPE_TUNNEL_GRENAT,
1669                 RTE_PTYPE_TUNNEL_IP,
1670                 RTE_PTYPE_INNER_L2_ETHER,
1671                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1672                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1673                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1674                 RTE_PTYPE_INNER_L4_FRAG,
1675                 RTE_PTYPE_INNER_L4_ICMP,
1676                 RTE_PTYPE_INNER_L4_NONFRAG,
1677                 RTE_PTYPE_INNER_L4_SCTP,
1678                 RTE_PTYPE_INNER_L4_TCP,
1679                 RTE_PTYPE_INNER_L4_UDP,
1680                 RTE_PTYPE_UNKNOWN
1681         };
1682
1683         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1684 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1685             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1686 #endif
1687             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1688             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1689             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1690             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1691             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1692                 return ptypes;
1693         return NULL;
1694 }
1695
1696 static int
1697 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1698 {
1699         uint16_t i;
1700
1701         for (i = 0; i < num; i++) {
1702                 if (i != idx && queues[i])
1703                         return 0;
1704         }
1705
1706         return 1;
1707 }
1708
1709 static int
1710 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1711                                 struct i40e_rx_queue *rxq)
1712 {
1713         struct i40e_adapter *ad =
1714                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1715         int use_def_burst_func =
1716                 check_rx_burst_bulk_alloc_preconditions(rxq);
1717         uint16_t buf_size =
1718                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1719                            RTE_PKTMBUF_HEADROOM);
1720         int use_scattered_rx =
1721                 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1722
1723         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1724                 PMD_DRV_LOG(ERR,
1725                             "Failed to do RX queue initialization");
1726                 return -EINVAL;
1727         }
1728
1729         if (i40e_dev_first_queue(rxq->queue_id,
1730                                  dev->data->rx_queues,
1731                                  dev->data->nb_rx_queues)) {
1732                 /**
1733                  * If it is the first queue to setup,
1734                  * set all flags to default and call
1735                  * i40e_set_rx_function.
1736                  */
1737                 ad->rx_bulk_alloc_allowed = true;
1738                 ad->rx_vec_allowed = true;
1739                 dev->data->scattered_rx = use_scattered_rx;
1740                 if (use_def_burst_func)
1741                         ad->rx_bulk_alloc_allowed = false;
1742                 i40e_set_rx_function(dev);
1743                 return 0;
1744         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1745                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1746                             " number %d of queue %d isn't power of 2",
1747                             rxq->nb_rx_desc, rxq->queue_id);
1748                 return -EINVAL;
1749         }
1750
1751         /* check bulk alloc conflict */
1752         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1753                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1754                 return -EINVAL;
1755         }
1756         /* check scatterred conflict */
1757         if (!dev->data->scattered_rx && use_scattered_rx) {
1758                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1759                 return -EINVAL;
1760         }
1761         /* check vector conflict */
1762         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1763                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1764                 return -EINVAL;
1765         }
1766
1767         return 0;
1768 }
1769
1770 int
1771 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1772                         uint16_t queue_idx,
1773                         uint16_t nb_desc,
1774                         unsigned int socket_id,
1775                         const struct rte_eth_rxconf *rx_conf,
1776                         struct rte_mempool *mp)
1777 {
1778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779         struct i40e_adapter *ad =
1780                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1781         struct i40e_vsi *vsi;
1782         struct i40e_pf *pf = NULL;
1783         struct i40e_vf *vf = NULL;
1784         struct i40e_rx_queue *rxq;
1785         const struct rte_memzone *rz;
1786         uint32_t ring_size;
1787         uint16_t len, i;
1788         uint16_t reg_idx, base, bsf, tc_mapping;
1789         int q_offset, use_def_burst_func = 1;
1790         uint64_t offloads;
1791
1792         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1793
1794         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1795                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1796                 vsi = &vf->vsi;
1797                 if (!vsi)
1798                         return -EINVAL;
1799                 reg_idx = queue_idx;
1800         } else {
1801                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1802                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1803                 if (!vsi)
1804                         return -EINVAL;
1805                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1806                 if (q_offset < 0)
1807                         return -EINVAL;
1808                 reg_idx = vsi->base_queue + q_offset;
1809         }
1810
1811         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1812             (nb_desc > I40E_MAX_RING_DESC) ||
1813             (nb_desc < I40E_MIN_RING_DESC)) {
1814                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1815                             "invalid", nb_desc);
1816                 return -EINVAL;
1817         }
1818
1819         /* Free memory if needed */
1820         if (dev->data->rx_queues[queue_idx]) {
1821                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1822                 dev->data->rx_queues[queue_idx] = NULL;
1823         }
1824
1825         /* Allocate the rx queue data structure */
1826         rxq = rte_zmalloc_socket("i40e rx queue",
1827                                  sizeof(struct i40e_rx_queue),
1828                                  RTE_CACHE_LINE_SIZE,
1829                                  socket_id);
1830         if (!rxq) {
1831                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1832                             "rx queue data structure");
1833                 return -ENOMEM;
1834         }
1835         rxq->mp = mp;
1836         rxq->nb_rx_desc = nb_desc;
1837         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1838         rxq->queue_id = queue_idx;
1839         rxq->reg_idx = reg_idx;
1840         rxq->port_id = dev->data->port_id;
1841         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1842                 rxq->crc_len = ETHER_CRC_LEN;
1843         else
1844                 rxq->crc_len = 0;
1845         rxq->drop_en = rx_conf->rx_drop_en;
1846         rxq->vsi = vsi;
1847         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1848         rxq->offloads = offloads;
1849
1850         /* Allocate the maximun number of RX ring hardware descriptor. */
1851         len = I40E_MAX_RING_DESC;
1852
1853         /**
1854          * Allocating a little more memory because vectorized/bulk_alloc Rx
1855          * functions doesn't check boundaries each time.
1856          */
1857         len += RTE_PMD_I40E_RX_MAX_BURST;
1858
1859         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1860                               I40E_DMA_MEM_ALIGN);
1861
1862         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1863                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1864         if (!rz) {
1865                 i40e_dev_rx_queue_release(rxq);
1866                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1867                 return -ENOMEM;
1868         }
1869
1870         /* Zero all the descriptors in the ring. */
1871         memset(rz->addr, 0, ring_size);
1872
1873         rxq->rx_ring_phys_addr = rz->iova;
1874         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1875
1876         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1877
1878         /* Allocate the software ring. */
1879         rxq->sw_ring =
1880                 rte_zmalloc_socket("i40e rx sw ring",
1881                                    sizeof(struct i40e_rx_entry) * len,
1882                                    RTE_CACHE_LINE_SIZE,
1883                                    socket_id);
1884         if (!rxq->sw_ring) {
1885                 i40e_dev_rx_queue_release(rxq);
1886                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1887                 return -ENOMEM;
1888         }
1889
1890         i40e_reset_rx_queue(rxq);
1891         rxq->q_set = TRUE;
1892
1893         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1894                 if (!(vsi->enabled_tc & (1 << i)))
1895                         continue;
1896                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1897                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1898                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1899                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1900                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1901
1902                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1903                         rxq->dcb_tc = i;
1904         }
1905
1906         if (dev->data->dev_started) {
1907                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1908                         i40e_dev_rx_queue_release(rxq);
1909                         return -EINVAL;
1910                 }
1911         } else {
1912                 use_def_burst_func =
1913                         check_rx_burst_bulk_alloc_preconditions(rxq);
1914                 if (!use_def_burst_func) {
1915 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1916                         PMD_INIT_LOG(DEBUG,
1917                           "Rx Burst Bulk Alloc Preconditions are "
1918                           "satisfied. Rx Burst Bulk Alloc function will be "
1919                           "used on port=%d, queue=%d.",
1920                           rxq->port_id, rxq->queue_id);
1921 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1922                 } else {
1923                         PMD_INIT_LOG(DEBUG,
1924                           "Rx Burst Bulk Alloc Preconditions are "
1925                           "not satisfied, Scattered Rx is requested, "
1926                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1927                           "not enabled on port=%d, queue=%d.",
1928                           rxq->port_id, rxq->queue_id);
1929                         ad->rx_bulk_alloc_allowed = false;
1930                 }
1931         }
1932
1933         dev->data->rx_queues[queue_idx] = rxq;
1934         return 0;
1935 }
1936
1937 void
1938 i40e_dev_rx_queue_release(void *rxq)
1939 {
1940         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1941
1942         if (!q) {
1943                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1944                 return;
1945         }
1946
1947         i40e_rx_queue_release_mbufs(q);
1948         rte_free(q->sw_ring);
1949         rte_free(q);
1950 }
1951
1952 uint32_t
1953 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1954 {
1955 #define I40E_RXQ_SCAN_INTERVAL 4
1956         volatile union i40e_rx_desc *rxdp;
1957         struct i40e_rx_queue *rxq;
1958         uint16_t desc = 0;
1959
1960         rxq = dev->data->rx_queues[rx_queue_id];
1961         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1962         while ((desc < rxq->nb_rx_desc) &&
1963                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1964                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1965                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1966                 /**
1967                  * Check the DD bit of a rx descriptor of each 4 in a group,
1968                  * to avoid checking too frequently and downgrading performance
1969                  * too much.
1970                  */
1971                 desc += I40E_RXQ_SCAN_INTERVAL;
1972                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1973                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1974                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1975                                         desc - rxq->nb_rx_desc]);
1976         }
1977
1978         return desc;
1979 }
1980
1981 int
1982 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1983 {
1984         volatile union i40e_rx_desc *rxdp;
1985         struct i40e_rx_queue *rxq = rx_queue;
1986         uint16_t desc;
1987         int ret;
1988
1989         if (unlikely(offset >= rxq->nb_rx_desc)) {
1990                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1991                 return 0;
1992         }
1993
1994         desc = rxq->rx_tail + offset;
1995         if (desc >= rxq->nb_rx_desc)
1996                 desc -= rxq->nb_rx_desc;
1997
1998         rxdp = &(rxq->rx_ring[desc]);
1999
2000         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2001                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2002                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2003
2004         return ret;
2005 }
2006
2007 int
2008 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2009 {
2010         struct i40e_rx_queue *rxq = rx_queue;
2011         volatile uint64_t *status;
2012         uint64_t mask;
2013         uint32_t desc;
2014
2015         if (unlikely(offset >= rxq->nb_rx_desc))
2016                 return -EINVAL;
2017
2018         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2019                 return RTE_ETH_RX_DESC_UNAVAIL;
2020
2021         desc = rxq->rx_tail + offset;
2022         if (desc >= rxq->nb_rx_desc)
2023                 desc -= rxq->nb_rx_desc;
2024
2025         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2026         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2027                 << I40E_RXD_QW1_STATUS_SHIFT);
2028         if (*status & mask)
2029                 return RTE_ETH_RX_DESC_DONE;
2030
2031         return RTE_ETH_RX_DESC_AVAIL;
2032 }
2033
2034 int
2035 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2036 {
2037         struct i40e_tx_queue *txq = tx_queue;
2038         volatile uint64_t *status;
2039         uint64_t mask, expect;
2040         uint32_t desc;
2041
2042         if (unlikely(offset >= txq->nb_tx_desc))
2043                 return -EINVAL;
2044
2045         desc = txq->tx_tail + offset;
2046         /* go to next desc that has the RS bit */
2047         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2048                 txq->tx_rs_thresh;
2049         if (desc >= txq->nb_tx_desc) {
2050                 desc -= txq->nb_tx_desc;
2051                 if (desc >= txq->nb_tx_desc)
2052                         desc -= txq->nb_tx_desc;
2053         }
2054
2055         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2056         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2057         expect = rte_cpu_to_le_64(
2058                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2059         if ((*status & mask) == expect)
2060                 return RTE_ETH_TX_DESC_DONE;
2061
2062         return RTE_ETH_TX_DESC_FULL;
2063 }
2064
2065 static int
2066 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2067                                 struct i40e_tx_queue *txq)
2068 {
2069         struct i40e_adapter *ad =
2070                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2071
2072         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2073                 PMD_DRV_LOG(ERR,
2074                             "Failed to do TX queue initialization");
2075                 return -EINVAL;
2076         }
2077
2078         if (i40e_dev_first_queue(txq->queue_id,
2079                                  dev->data->tx_queues,
2080                                  dev->data->nb_tx_queues)) {
2081                 /**
2082                  * If it is the first queue to setup,
2083                  * set all flags and call
2084                  * i40e_set_tx_function.
2085                  */
2086                 i40e_set_tx_function_flag(dev, txq);
2087                 i40e_set_tx_function(dev);
2088                 return 0;
2089         }
2090
2091         /* check vector conflict */
2092         if (ad->tx_vec_allowed) {
2093                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2094                     i40e_txq_vec_setup(txq)) {
2095                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2096                         return -EINVAL;
2097                 }
2098         }
2099         /* check simple tx conflict */
2100         if (ad->tx_simple_allowed) {
2101                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2102                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2103                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2104                         return -EINVAL;
2105                 }
2106         }
2107
2108         return 0;
2109 }
2110
2111 int
2112 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2113                         uint16_t queue_idx,
2114                         uint16_t nb_desc,
2115                         unsigned int socket_id,
2116                         const struct rte_eth_txconf *tx_conf)
2117 {
2118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119         struct i40e_vsi *vsi;
2120         struct i40e_pf *pf = NULL;
2121         struct i40e_vf *vf = NULL;
2122         struct i40e_tx_queue *txq;
2123         const struct rte_memzone *tz;
2124         uint32_t ring_size;
2125         uint16_t tx_rs_thresh, tx_free_thresh;
2126         uint16_t reg_idx, i, base, bsf, tc_mapping;
2127         int q_offset;
2128         uint64_t offloads;
2129
2130         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2131
2132         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2133                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2134                 vsi = &vf->vsi;
2135                 if (!vsi)
2136                         return -EINVAL;
2137                 reg_idx = queue_idx;
2138         } else {
2139                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2140                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2141                 if (!vsi)
2142                         return -EINVAL;
2143                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2144                 if (q_offset < 0)
2145                         return -EINVAL;
2146                 reg_idx = vsi->base_queue + q_offset;
2147         }
2148
2149         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2150             (nb_desc > I40E_MAX_RING_DESC) ||
2151             (nb_desc < I40E_MIN_RING_DESC)) {
2152                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2153                             "invalid", nb_desc);
2154                 return -EINVAL;
2155         }
2156
2157         /**
2158          * The following two parameters control the setting of the RS bit on
2159          * transmit descriptors. TX descriptors will have their RS bit set
2160          * after txq->tx_rs_thresh descriptors have been used. The TX
2161          * descriptor ring will be cleaned after txq->tx_free_thresh
2162          * descriptors are used or if the number of descriptors required to
2163          * transmit a packet is greater than the number of free TX descriptors.
2164          *
2165          * The following constraints must be satisfied:
2166          *  - tx_rs_thresh must be greater than 0.
2167          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2168          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2169          *  - tx_rs_thresh must be a divisor of the ring size.
2170          *  - tx_free_thresh must be greater than 0.
2171          *  - tx_free_thresh must be less than the size of the ring minus 3.
2172          *
2173          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2174          * race condition, hence the maximum threshold constraints. When set
2175          * to zero use default values.
2176          */
2177         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2178                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2179         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2180                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2181         if (tx_rs_thresh >= (nb_desc - 2)) {
2182                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2183                              "number of TX descriptors minus 2. "
2184                              "(tx_rs_thresh=%u port=%d queue=%d)",
2185                              (unsigned int)tx_rs_thresh,
2186                              (int)dev->data->port_id,
2187                              (int)queue_idx);
2188                 return I40E_ERR_PARAM;
2189         }
2190         if (tx_free_thresh >= (nb_desc - 3)) {
2191                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2192                              "number of TX descriptors minus 3. "
2193                              "(tx_free_thresh=%u port=%d queue=%d)",
2194                              (unsigned int)tx_free_thresh,
2195                              (int)dev->data->port_id,
2196                              (int)queue_idx);
2197                 return I40E_ERR_PARAM;
2198         }
2199         if (tx_rs_thresh > tx_free_thresh) {
2200                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2201                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2202                              " tx_rs_thresh=%u port=%d queue=%d)",
2203                              (unsigned int)tx_free_thresh,
2204                              (unsigned int)tx_rs_thresh,
2205                              (int)dev->data->port_id,
2206                              (int)queue_idx);
2207                 return I40E_ERR_PARAM;
2208         }
2209         if ((nb_desc % tx_rs_thresh) != 0) {
2210                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2211                              "number of TX descriptors. (tx_rs_thresh=%u"
2212                              " port=%d queue=%d)",
2213                              (unsigned int)tx_rs_thresh,
2214                              (int)dev->data->port_id,
2215                              (int)queue_idx);
2216                 return I40E_ERR_PARAM;
2217         }
2218         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2219                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2220                              "tx_rs_thresh is greater than 1. "
2221                              "(tx_rs_thresh=%u port=%d queue=%d)",
2222                              (unsigned int)tx_rs_thresh,
2223                              (int)dev->data->port_id,
2224                              (int)queue_idx);
2225                 return I40E_ERR_PARAM;
2226         }
2227
2228         /* Free memory if needed. */
2229         if (dev->data->tx_queues[queue_idx]) {
2230                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2231                 dev->data->tx_queues[queue_idx] = NULL;
2232         }
2233
2234         /* Allocate the TX queue data structure. */
2235         txq = rte_zmalloc_socket("i40e tx queue",
2236                                   sizeof(struct i40e_tx_queue),
2237                                   RTE_CACHE_LINE_SIZE,
2238                                   socket_id);
2239         if (!txq) {
2240                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2241                             "tx queue structure");
2242                 return -ENOMEM;
2243         }
2244
2245         /* Allocate TX hardware ring descriptors. */
2246         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2247         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2248         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2249                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2250         if (!tz) {
2251                 i40e_dev_tx_queue_release(txq);
2252                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2253                 return -ENOMEM;
2254         }
2255
2256         txq->nb_tx_desc = nb_desc;
2257         txq->tx_rs_thresh = tx_rs_thresh;
2258         txq->tx_free_thresh = tx_free_thresh;
2259         txq->pthresh = tx_conf->tx_thresh.pthresh;
2260         txq->hthresh = tx_conf->tx_thresh.hthresh;
2261         txq->wthresh = tx_conf->tx_thresh.wthresh;
2262         txq->queue_id = queue_idx;
2263         txq->reg_idx = reg_idx;
2264         txq->port_id = dev->data->port_id;
2265         txq->offloads = offloads;
2266         txq->vsi = vsi;
2267         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2268
2269         txq->tx_ring_phys_addr = tz->iova;
2270         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2271
2272         /* Allocate software ring */
2273         txq->sw_ring =
2274                 rte_zmalloc_socket("i40e tx sw ring",
2275                                    sizeof(struct i40e_tx_entry) * nb_desc,
2276                                    RTE_CACHE_LINE_SIZE,
2277                                    socket_id);
2278         if (!txq->sw_ring) {
2279                 i40e_dev_tx_queue_release(txq);
2280                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2281                 return -ENOMEM;
2282         }
2283
2284         i40e_reset_tx_queue(txq);
2285         txq->q_set = TRUE;
2286
2287         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2288                 if (!(vsi->enabled_tc & (1 << i)))
2289                         continue;
2290                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2291                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2292                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2293                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2294                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2295
2296                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2297                         txq->dcb_tc = i;
2298         }
2299
2300         if (dev->data->dev_started) {
2301                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2302                         i40e_dev_tx_queue_release(txq);
2303                         return -EINVAL;
2304                 }
2305         } else {
2306                 /**
2307                  * Use a simple TX queue without offloads or
2308                  * multi segs if possible
2309                  */
2310                 i40e_set_tx_function_flag(dev, txq);
2311         }
2312         dev->data->tx_queues[queue_idx] = txq;
2313
2314         return 0;
2315 }
2316
2317 void
2318 i40e_dev_tx_queue_release(void *txq)
2319 {
2320         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2321
2322         if (!q) {
2323                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2324                 return;
2325         }
2326
2327         i40e_tx_queue_release_mbufs(q);
2328         rte_free(q->sw_ring);
2329         rte_free(q);
2330 }
2331
2332 const struct rte_memzone *
2333 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2334 {
2335         const struct rte_memzone *mz;
2336
2337         mz = rte_memzone_lookup(name);
2338         if (mz)
2339                 return mz;
2340
2341         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2342                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2343         return mz;
2344 }
2345
2346 void
2347 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2348 {
2349         uint16_t i;
2350
2351         /* SSE Vector driver has a different way of releasing mbufs. */
2352         if (rxq->rx_using_sse) {
2353                 i40e_rx_queue_release_mbufs_vec(rxq);
2354                 return;
2355         }
2356
2357         if (!rxq->sw_ring) {
2358                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2359                 return;
2360         }
2361
2362         for (i = 0; i < rxq->nb_rx_desc; i++) {
2363                 if (rxq->sw_ring[i].mbuf) {
2364                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2365                         rxq->sw_ring[i].mbuf = NULL;
2366                 }
2367         }
2368 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2369         if (rxq->rx_nb_avail == 0)
2370                 return;
2371         for (i = 0; i < rxq->rx_nb_avail; i++) {
2372                 struct rte_mbuf *mbuf;
2373
2374                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2375                 rte_pktmbuf_free_seg(mbuf);
2376         }
2377         rxq->rx_nb_avail = 0;
2378 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2379 }
2380
2381 void
2382 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2383 {
2384         unsigned i;
2385         uint16_t len;
2386
2387         if (!rxq) {
2388                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2389                 return;
2390         }
2391
2392 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2393         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2394                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2395         else
2396 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2397                 len = rxq->nb_rx_desc;
2398
2399         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2400                 ((volatile char *)rxq->rx_ring)[i] = 0;
2401
2402         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2403         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2404                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2405
2406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2407         rxq->rx_nb_avail = 0;
2408         rxq->rx_next_avail = 0;
2409         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2410 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2411         rxq->rx_tail = 0;
2412         rxq->nb_rx_hold = 0;
2413         rxq->pkt_first_seg = NULL;
2414         rxq->pkt_last_seg = NULL;
2415
2416         rxq->rxrearm_start = 0;
2417         rxq->rxrearm_nb = 0;
2418 }
2419
2420 void
2421 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2422 {
2423         struct rte_eth_dev *dev;
2424         uint16_t i;
2425
2426         dev = &rte_eth_devices[txq->port_id];
2427
2428         if (!txq || !txq->sw_ring) {
2429                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2430                 return;
2431         }
2432
2433         /**
2434          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2435          *  so need to free remains more carefully.
2436          */
2437         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2438                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2439                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2440                 if (txq->tx_tail < i) {
2441                         for (; i < txq->nb_tx_desc; i++) {
2442                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2443                                 txq->sw_ring[i].mbuf = NULL;
2444                         }
2445                         i = 0;
2446                 }
2447                 for (; i < txq->tx_tail; i++) {
2448                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2449                         txq->sw_ring[i].mbuf = NULL;
2450                 }
2451         } else {
2452                 for (i = 0; i < txq->nb_tx_desc; i++) {
2453                         if (txq->sw_ring[i].mbuf) {
2454                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2455                                 txq->sw_ring[i].mbuf = NULL;
2456                         }
2457                 }
2458         }
2459 }
2460
2461 void
2462 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2463 {
2464         struct i40e_tx_entry *txe;
2465         uint16_t i, prev, size;
2466
2467         if (!txq) {
2468                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2469                 return;
2470         }
2471
2472         txe = txq->sw_ring;
2473         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2474         for (i = 0; i < size; i++)
2475                 ((volatile char *)txq->tx_ring)[i] = 0;
2476
2477         prev = (uint16_t)(txq->nb_tx_desc - 1);
2478         for (i = 0; i < txq->nb_tx_desc; i++) {
2479                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2480
2481                 txd->cmd_type_offset_bsz =
2482                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2483                 txe[i].mbuf =  NULL;
2484                 txe[i].last_id = i;
2485                 txe[prev].next_id = i;
2486                 prev = i;
2487         }
2488
2489         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2490         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2491
2492         txq->tx_tail = 0;
2493         txq->nb_tx_used = 0;
2494
2495         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2496         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2497 }
2498
2499 /* Init the TX queue in hardware */
2500 int
2501 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2502 {
2503         enum i40e_status_code err = I40E_SUCCESS;
2504         struct i40e_vsi *vsi = txq->vsi;
2505         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2506         uint16_t pf_q = txq->reg_idx;
2507         struct i40e_hmc_obj_txq tx_ctx;
2508         uint32_t qtx_ctl;
2509
2510         /* clear the context structure first */
2511         memset(&tx_ctx, 0, sizeof(tx_ctx));
2512         tx_ctx.new_context = 1;
2513         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2514         tx_ctx.qlen = txq->nb_tx_desc;
2515
2516 #ifdef RTE_LIBRTE_IEEE1588
2517         tx_ctx.timesync_ena = 1;
2518 #endif
2519         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2520         if (vsi->type == I40E_VSI_FDIR)
2521                 tx_ctx.fd_ena = TRUE;
2522
2523         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2524         if (err != I40E_SUCCESS) {
2525                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2526                 return err;
2527         }
2528
2529         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2530         if (err != I40E_SUCCESS) {
2531                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2532                 return err;
2533         }
2534
2535         /* Now associate this queue with this PCI function */
2536         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2537         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2538                                         I40E_QTX_CTL_PF_INDX_MASK);
2539         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2540         I40E_WRITE_FLUSH(hw);
2541
2542         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2543
2544         return err;
2545 }
2546
2547 int
2548 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2549 {
2550         struct i40e_rx_entry *rxe = rxq->sw_ring;
2551         uint64_t dma_addr;
2552         uint16_t i;
2553
2554         for (i = 0; i < rxq->nb_rx_desc; i++) {
2555                 volatile union i40e_rx_desc *rxd;
2556                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2557
2558                 if (unlikely(!mbuf)) {
2559                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2560                         return -ENOMEM;
2561                 }
2562
2563                 rte_mbuf_refcnt_set(mbuf, 1);
2564                 mbuf->next = NULL;
2565                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2566                 mbuf->nb_segs = 1;
2567                 mbuf->port = rxq->port_id;
2568
2569                 dma_addr =
2570                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2571
2572                 rxd = &rxq->rx_ring[i];
2573                 rxd->read.pkt_addr = dma_addr;
2574                 rxd->read.hdr_addr = 0;
2575 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2576                 rxd->read.rsvd1 = 0;
2577                 rxd->read.rsvd2 = 0;
2578 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2579
2580                 rxe[i].mbuf = mbuf;
2581         }
2582
2583         return 0;
2584 }
2585
2586 /*
2587  * Calculate the buffer length, and check the jumbo frame
2588  * and maximum packet length.
2589  */
2590 static int
2591 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2592 {
2593         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2594         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2595         struct rte_eth_dev_data *data = pf->dev_data;
2596         uint16_t buf_size, len;
2597
2598         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2599                 RTE_PKTMBUF_HEADROOM);
2600
2601         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2602                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2603         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2604                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2605                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2606                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2607                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2608                 rxq->hs_mode = i40e_header_split_enabled;
2609                 break;
2610         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2611         default:
2612                 rxq->rx_hdr_len = 0;
2613                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2614                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2615                 rxq->hs_mode = i40e_header_split_none;
2616                 break;
2617         }
2618
2619         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2620         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2621         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2622                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2623                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2624                         PMD_DRV_LOG(ERR, "maximum packet length must "
2625                                     "be larger than %u and smaller than %u,"
2626                                     "as jumbo frame is enabled",
2627                                     (uint32_t)ETHER_MAX_LEN,
2628                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2629                         return I40E_ERR_CONFIG;
2630                 }
2631         } else {
2632                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2633                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2634                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2635                                     "larger than %u and smaller than %u, "
2636                                     "as jumbo frame is disabled",
2637                                     (uint32_t)ETHER_MIN_LEN,
2638                                     (uint32_t)ETHER_MAX_LEN);
2639                         return I40E_ERR_CONFIG;
2640                 }
2641         }
2642
2643         return 0;
2644 }
2645
2646 /* Init the RX queue in hardware */
2647 int
2648 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2649 {
2650         int err = I40E_SUCCESS;
2651         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2652         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2653         uint16_t pf_q = rxq->reg_idx;
2654         uint16_t buf_size;
2655         struct i40e_hmc_obj_rxq rx_ctx;
2656
2657         err = i40e_rx_queue_config(rxq);
2658         if (err < 0) {
2659                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2660                 return err;
2661         }
2662
2663         /* Clear the context structure first */
2664         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2665         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2666         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2667
2668         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2669         rx_ctx.qlen = rxq->nb_rx_desc;
2670 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2671         rx_ctx.dsize = 1;
2672 #endif
2673         rx_ctx.dtype = rxq->hs_mode;
2674         if (rxq->hs_mode)
2675                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2676         else
2677                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2678         rx_ctx.rxmax = rxq->max_pkt_len;
2679         rx_ctx.tphrdesc_ena = 1;
2680         rx_ctx.tphwdesc_ena = 1;
2681         rx_ctx.tphdata_ena = 1;
2682         rx_ctx.tphhead_ena = 1;
2683         rx_ctx.lrxqthresh = 2;
2684         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2685         rx_ctx.l2tsel = 1;
2686         /* showiv indicates if inner VLAN is stripped inside of tunnel
2687          * packet. When set it to 1, vlan information is stripped from
2688          * the inner header, but the hardware does not put it in the
2689          * descriptor. So set it zero by default.
2690          */
2691         rx_ctx.showiv = 0;
2692         rx_ctx.prefena = 1;
2693
2694         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2695         if (err != I40E_SUCCESS) {
2696                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2697                 return err;
2698         }
2699         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2700         if (err != I40E_SUCCESS) {
2701                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2702                 return err;
2703         }
2704
2705         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2706
2707         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2708                 RTE_PKTMBUF_HEADROOM);
2709
2710         /* Check if scattered RX needs to be used. */
2711         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2712                 dev_data->scattered_rx = 1;
2713         }
2714
2715         /* Init the RX tail regieter. */
2716         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2717
2718         return 0;
2719 }
2720
2721 void
2722 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2723 {
2724         uint16_t i;
2725
2726         PMD_INIT_FUNC_TRACE();
2727
2728         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2729                 if (!dev->data->tx_queues[i])
2730                         continue;
2731                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2732                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2733         }
2734
2735         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2736                 if (!dev->data->rx_queues[i])
2737                         continue;
2738                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2739                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2740         }
2741 }
2742
2743 void
2744 i40e_dev_free_queues(struct rte_eth_dev *dev)
2745 {
2746         uint16_t i;
2747
2748         PMD_INIT_FUNC_TRACE();
2749
2750         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2751                 if (!dev->data->rx_queues[i])
2752                         continue;
2753                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2754                 dev->data->rx_queues[i] = NULL;
2755         }
2756         dev->data->nb_rx_queues = 0;
2757
2758         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2759                 if (!dev->data->tx_queues[i])
2760                         continue;
2761                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2762                 dev->data->tx_queues[i] = NULL;
2763         }
2764         dev->data->nb_tx_queues = 0;
2765 }
2766
2767 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2768 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2769
2770 enum i40e_status_code
2771 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2772 {
2773         struct i40e_tx_queue *txq;
2774         const struct rte_memzone *tz = NULL;
2775         uint32_t ring_size;
2776         struct rte_eth_dev *dev;
2777
2778         if (!pf) {
2779                 PMD_DRV_LOG(ERR, "PF is not available");
2780                 return I40E_ERR_BAD_PTR;
2781         }
2782
2783         dev = pf->adapter->eth_dev;
2784
2785         /* Allocate the TX queue data structure. */
2786         txq = rte_zmalloc_socket("i40e fdir tx queue",
2787                                   sizeof(struct i40e_tx_queue),
2788                                   RTE_CACHE_LINE_SIZE,
2789                                   SOCKET_ID_ANY);
2790         if (!txq) {
2791                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2792                                         "tx queue structure.");
2793                 return I40E_ERR_NO_MEMORY;
2794         }
2795
2796         /* Allocate TX hardware ring descriptors. */
2797         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2798         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2799
2800         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2801                                       I40E_FDIR_QUEUE_ID, ring_size,
2802                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2803         if (!tz) {
2804                 i40e_dev_tx_queue_release(txq);
2805                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2806                 return I40E_ERR_NO_MEMORY;
2807         }
2808
2809         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2810         txq->queue_id = I40E_FDIR_QUEUE_ID;
2811         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2812         txq->vsi = pf->fdir.fdir_vsi;
2813
2814         txq->tx_ring_phys_addr = tz->iova;
2815         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2816         /*
2817          * don't need to allocate software ring and reset for the fdir
2818          * program queue just set the queue has been configured.
2819          */
2820         txq->q_set = TRUE;
2821         pf->fdir.txq = txq;
2822
2823         return I40E_SUCCESS;
2824 }
2825
2826 enum i40e_status_code
2827 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2828 {
2829         struct i40e_rx_queue *rxq;
2830         const struct rte_memzone *rz = NULL;
2831         uint32_t ring_size;
2832         struct rte_eth_dev *dev;
2833
2834         if (!pf) {
2835                 PMD_DRV_LOG(ERR, "PF is not available");
2836                 return I40E_ERR_BAD_PTR;
2837         }
2838
2839         dev = pf->adapter->eth_dev;
2840
2841         /* Allocate the RX queue data structure. */
2842         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2843                                   sizeof(struct i40e_rx_queue),
2844                                   RTE_CACHE_LINE_SIZE,
2845                                   SOCKET_ID_ANY);
2846         if (!rxq) {
2847                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2848                                         "rx queue structure.");
2849                 return I40E_ERR_NO_MEMORY;
2850         }
2851
2852         /* Allocate RX hardware ring descriptors. */
2853         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2854         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2855
2856         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2857                                       I40E_FDIR_QUEUE_ID, ring_size,
2858                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2859         if (!rz) {
2860                 i40e_dev_rx_queue_release(rxq);
2861                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2862                 return I40E_ERR_NO_MEMORY;
2863         }
2864
2865         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2866         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2867         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2868         rxq->vsi = pf->fdir.fdir_vsi;
2869
2870         rxq->rx_ring_phys_addr = rz->iova;
2871         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2872         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2873
2874         /*
2875          * Don't need to allocate software ring and reset for the fdir
2876          * rx queue, just set the queue has been configured.
2877          */
2878         rxq->q_set = TRUE;
2879         pf->fdir.rxq = rxq;
2880
2881         return I40E_SUCCESS;
2882 }
2883
2884 void
2885 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2886         struct rte_eth_rxq_info *qinfo)
2887 {
2888         struct i40e_rx_queue *rxq;
2889
2890         rxq = dev->data->rx_queues[queue_id];
2891
2892         qinfo->mp = rxq->mp;
2893         qinfo->scattered_rx = dev->data->scattered_rx;
2894         qinfo->nb_desc = rxq->nb_rx_desc;
2895
2896         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2897         qinfo->conf.rx_drop_en = rxq->drop_en;
2898         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2899         qinfo->conf.offloads = rxq->offloads;
2900 }
2901
2902 void
2903 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2904         struct rte_eth_txq_info *qinfo)
2905 {
2906         struct i40e_tx_queue *txq;
2907
2908         txq = dev->data->tx_queues[queue_id];
2909
2910         qinfo->nb_desc = txq->nb_tx_desc;
2911
2912         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2913         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2914         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2915
2916         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2917         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2918         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2919         qinfo->conf.offloads = txq->offloads;
2920 }
2921
2922 static eth_rx_burst_t
2923 i40e_get_latest_rx_vec(bool scatter)
2924 {
2925 #ifdef RTE_ARCH_X86
2926         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2927                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2928                                  i40e_recv_pkts_vec_avx2;
2929 #endif
2930         return scatter ? i40e_recv_scattered_pkts_vec :
2931                          i40e_recv_pkts_vec;
2932 }
2933
2934 static eth_rx_burst_t
2935 i40e_get_recommend_rx_vec(bool scatter)
2936 {
2937 #ifdef RTE_ARCH_X86
2938         /*
2939          * since AVX frequency can be different to base frequency, limit
2940          * use of AVX2 version to later plaforms, not all those that could
2941          * theoretically run it.
2942          */
2943         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2944                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2945                                  i40e_recv_pkts_vec_avx2;
2946 #endif
2947         return scatter ? i40e_recv_scattered_pkts_vec :
2948                          i40e_recv_pkts_vec;
2949 }
2950
2951 void __attribute__((cold))
2952 i40e_set_rx_function(struct rte_eth_dev *dev)
2953 {
2954         struct i40e_adapter *ad =
2955                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2956         uint16_t rx_using_sse, i;
2957         /* In order to allow Vector Rx there are a few configuration
2958          * conditions to be met and Rx Bulk Allocation should be allowed.
2959          */
2960         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2961                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2962                     !ad->rx_bulk_alloc_allowed) {
2963                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2964                                      " Vector Rx preconditions",
2965                                      dev->data->port_id);
2966
2967                         ad->rx_vec_allowed = false;
2968                 }
2969                 if (ad->rx_vec_allowed) {
2970                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2971                                 struct i40e_rx_queue *rxq =
2972                                         dev->data->rx_queues[i];
2973
2974                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2975                                         ad->rx_vec_allowed = false;
2976                                         break;
2977                                 }
2978                         }
2979                 }
2980         }
2981
2982         if (ad->rx_vec_allowed) {
2983                 /* Vec Rx path */
2984                 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2985                                 dev->data->port_id);
2986                 if (ad->use_latest_vec)
2987                         dev->rx_pkt_burst =
2988                         i40e_get_latest_rx_vec(dev->data->scattered_rx);
2989                 else
2990                         dev->rx_pkt_burst =
2991                         i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2992         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2993                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2994                                     "satisfied. Rx Burst Bulk Alloc function "
2995                                     "will be used on port=%d.",
2996                              dev->data->port_id);
2997
2998                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2999         } else {
3000                 /* Simple Rx Path. */
3001                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3002                              dev->data->port_id);
3003                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3004                                         i40e_recv_scattered_pkts :
3005                                         i40e_recv_pkts;
3006         }
3007
3008         /* Propagate information about RX function choice through all queues. */
3009         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3010                 rx_using_sse =
3011                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3012                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3013                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3014                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3015
3016                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3017                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3018
3019                         if (rxq)
3020                                 rxq->rx_using_sse = rx_using_sse;
3021                 }
3022         }
3023 }
3024
3025 void __attribute__((cold))
3026 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3027 {
3028         struct i40e_adapter *ad =
3029                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3030
3031         /* Use a simple Tx queue if possible (only fast free is allowed) */
3032         ad->tx_simple_allowed =
3033                 (txq->offloads ==
3034                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3035                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3036         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3037                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3038
3039         if (ad->tx_vec_allowed)
3040                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3041                                 txq->queue_id);
3042         else if (ad->tx_simple_allowed)
3043                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3044                                 txq->queue_id);
3045         else
3046                 PMD_INIT_LOG(DEBUG,
3047                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3048                                 txq->queue_id);
3049 }
3050
3051 static eth_tx_burst_t
3052 i40e_get_latest_tx_vec(void)
3053 {
3054 #ifdef RTE_ARCH_X86
3055         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3056                 return i40e_xmit_pkts_vec_avx2;
3057 #endif
3058         return i40e_xmit_pkts_vec;
3059 }
3060
3061 static eth_tx_burst_t
3062 i40e_get_recommend_tx_vec(void)
3063 {
3064 #ifdef RTE_ARCH_X86
3065         /*
3066          * since AVX frequency can be different to base frequency, limit
3067          * use of AVX2 version to later plaforms, not all those that could
3068          * theoretically run it.
3069          */
3070         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3071                 return i40e_xmit_pkts_vec_avx2;
3072 #endif
3073         return i40e_xmit_pkts_vec;
3074 }
3075
3076 void __attribute__((cold))
3077 i40e_set_tx_function(struct rte_eth_dev *dev)
3078 {
3079         struct i40e_adapter *ad =
3080                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3081         int i;
3082
3083         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3084                 if (ad->tx_vec_allowed) {
3085                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3086                                 struct i40e_tx_queue *txq =
3087                                         dev->data->tx_queues[i];
3088
3089                                 if (txq && i40e_txq_vec_setup(txq)) {
3090                                         ad->tx_vec_allowed = false;
3091                                         break;
3092                                 }
3093                         }
3094                 }
3095         }
3096
3097         if (ad->tx_simple_allowed) {
3098                 if (ad->tx_vec_allowed) {
3099                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3100                         if (ad->use_latest_vec)
3101                                 dev->tx_pkt_burst =
3102                                         i40e_get_latest_tx_vec();
3103                         else
3104                                 dev->tx_pkt_burst =
3105                                         i40e_get_recommend_tx_vec();
3106                 } else {
3107                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3108                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3109                 }
3110                 dev->tx_pkt_prepare = NULL;
3111         } else {
3112                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3113                 dev->tx_pkt_burst = i40e_xmit_pkts;
3114                 dev->tx_pkt_prepare = i40e_prep_pkts;
3115         }
3116 }
3117
3118 void __attribute__((cold))
3119 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3120 {
3121         struct i40e_adapter *ad =
3122                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3123         int i;
3124
3125         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3126                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3127 }
3128
3129 void __attribute__((cold))
3130 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3131 {
3132         struct i40e_adapter *ad =
3133                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         int i;
3136
3137         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3138                 ad->pctypes_tbl[i] = 0ULL;
3139         ad->flow_types_mask = 0ULL;
3140         ad->pctypes_mask = 0ULL;
3141
3142         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3143                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3144         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3145                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3146         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3147                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3148         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3149                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3150         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3151                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3152         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3153                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3154         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3155                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3156         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3157                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3158         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3159                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3160         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3161                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3162         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3163                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3164
3165         if (hw->mac.type == I40E_MAC_X722) {
3166                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3167                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3168                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3169                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3170                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3171                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3172                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3173                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3174                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3175                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3176                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3177                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3178         }
3179
3180         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3181                 if (ad->pctypes_tbl[i])
3182                         ad->flow_types_mask |= (1ULL << i);
3183                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3184         }
3185 }
3186
3187 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3188 __rte_weak int
3189 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3190 {
3191         return -1;
3192 }
3193
3194 __rte_weak uint16_t
3195 i40e_recv_pkts_vec(
3196         void __rte_unused *rx_queue,
3197         struct rte_mbuf __rte_unused **rx_pkts,
3198         uint16_t __rte_unused nb_pkts)
3199 {
3200         return 0;
3201 }
3202
3203 __rte_weak uint16_t
3204 i40e_recv_scattered_pkts_vec(
3205         void __rte_unused *rx_queue,
3206         struct rte_mbuf __rte_unused **rx_pkts,
3207         uint16_t __rte_unused nb_pkts)
3208 {
3209         return 0;
3210 }
3211
3212 __rte_weak uint16_t
3213 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3214                         struct rte_mbuf __rte_unused **rx_pkts,
3215                         uint16_t __rte_unused nb_pkts)
3216 {
3217         return 0;
3218 }
3219
3220 __rte_weak uint16_t
3221 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3222                         struct rte_mbuf __rte_unused **rx_pkts,
3223                         uint16_t __rte_unused nb_pkts)
3224 {
3225         return 0;
3226 }
3227
3228 __rte_weak int
3229 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3230 {
3231         return -1;
3232 }
3233
3234 __rte_weak int
3235 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3236 {
3237         return -1;
3238 }
3239
3240 __rte_weak void
3241 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3242 {
3243         return;
3244 }
3245
3246 __rte_weak uint16_t
3247 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3248                           struct rte_mbuf __rte_unused **tx_pkts,
3249                           uint16_t __rte_unused nb_pkts)
3250 {
3251         return 0;
3252 }
3253
3254 __rte_weak uint16_t
3255 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3256                           struct rte_mbuf __rte_unused **tx_pkts,
3257                           uint16_t __rte_unused nb_pkts)
3258 {
3259         return 0;
3260 }