drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64
  65 #define I40E_TX_MAX_BURST  32
  66
  67 #define I40E_DMA_MEM_ALIGN 4096
  68
  69 /* Base address of the HW descriptor ring should be 128B aligned. */
  70 #define I40E_RING_BASE_ALIGN    128
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #ifdef RTE_LIBRTE_IEEE1588
  78 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  79 #else
  80 #define I40E_TX_IEEE1588_TMST 0
  81 #endif
  82
  83 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  84                 PKT_TX_IP_CKSUM |                \
  85                 PKT_TX_L4_MASK |                 \
  86                 PKT_TX_TCP_SEG |                 \
  87                 PKT_TX_OUTER_IP_CKSUM)
  88
  89 #define I40E_TX_OFFLOAD_MASK (  \
  90                 PKT_TX_OUTER_IPV4 |     \
  91                 PKT_TX_OUTER_IPV6 |     \
  92                 PKT_TX_IPV4 |           \
  93                 PKT_TX_IPV6 |           \
  94                 PKT_TX_IP_CKSUM |       \
  95                 PKT_TX_L4_MASK |        \
  96                 PKT_TX_OUTER_IP_CKSUM | \
  97                 PKT_TX_TCP_SEG |        \
  98                 PKT_TX_QINQ_PKT |       \
  99                 PKT_TX_VLAN_PKT |       \
 100                 PKT_TX_TUNNEL_MASK |    \
 101                 I40E_TX_IEEE1588_TMST)
 102
 103 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
 104                 ~(PKT_TX_OFFLOAD_MASK & I40E_TX_OFFLOAD_MASK)
 105
 106 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
 107                                       struct rte_mbuf **tx_pkts,
 108                                       uint16_t nb_pkts);
 109
 110 static inline void
 111 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 112 {
 113         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 114                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 115                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 116                 mb->vlan_tci =
 117                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 118                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 119                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 120         } else {
 121                 mb->vlan_tci = 0;
 122         }
 123 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 124         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 125                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 126                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 127                 mb->vlan_tci_outer = mb->vlan_tci;
 128                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 129                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 130                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 131                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 132         } else {
 133                 mb->vlan_tci_outer = 0;
 134         }
 135 #endif
 136         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 137                    mb->vlan_tci, mb->vlan_tci_outer);
 138 }
 139
 140 /* Translate the rx descriptor status to pkt flags */
 141 static inline uint64_t
 142 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 143 {
 144         uint64_t flags;
 145
 146         /* Check if RSS_HASH */
 147         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 148                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 149                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 150
 151         /* Check if FDIR Match */
 152         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 153                                                         PKT_RX_FDIR : 0);
 154
 155         return flags;
 156 }
 157
 158 static inline uint64_t
 159 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 160 {
 161         uint64_t flags = 0;
 162         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 163
 164 #define I40E_RX_ERR_BITS 0x3f
 165         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 166                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 167                 return flags;
 168         }
 169
 170         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 171                 flags |= PKT_RX_IP_CKSUM_BAD;
 172         else
 173                 flags |= PKT_RX_IP_CKSUM_GOOD;
 174
 175         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 176                 flags |= PKT_RX_L4_CKSUM_BAD;
 177         else
 178                 flags |= PKT_RX_L4_CKSUM_GOOD;
 179
 180         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 181                 flags |= PKT_RX_EIP_CKSUM_BAD;
 182
 183         return flags;
 184 }
 185
 186 /* Function to check and set the ieee1588 timesync index and get the
 187  * appropriate flags.
 188  */
 189 #ifdef RTE_LIBRTE_IEEE1588
 190 static inline uint64_t
 191 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 192 {
 193         uint64_t pkt_flags = 0;
 194         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 195                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 196                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 197
 198         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 199                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 200                 pkt_flags = PKT_RX_IEEE1588_PTP;
 201         if (tsyn & 0x04) {
 202                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 203                 mb->timesync = tsyn & 0x03;
 204         }
 205
 206         return pkt_flags;
 207 }
 208 #endif
 209
 210 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 211 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 212 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 213 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 214 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 215
 216 static inline uint64_t
 217 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 218 {
 219         uint64_t flags = 0;
 220 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 221         uint16_t flexbh, flexbl;
 222
 223         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 225                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 226         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 227                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 228                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 229
 230
 231         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 232                 mb->hash.fdir.hi =
 233                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 234                 flags |= PKT_RX_FDIR_ID;
 235         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 236                 mb->hash.fdir.hi =
 237                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 238                 flags |= PKT_RX_FDIR_FLX;
 239         }
 240         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 241                 mb->hash.fdir.lo =
 242                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 243                 flags |= PKT_RX_FDIR_FLX;
 244         }
 245 #else
 246         mb->hash.fdir.hi =
 247                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 248         flags |= PKT_RX_FDIR_ID;
 249 #endif
 250         return flags;
 251 }
 252
 253 static inline void
 254 i40e_parse_tunneling_params(uint64_t ol_flags,
 255                             union i40e_tx_offload tx_offload,
 256                             uint32_t *cd_tunneling)
 257 {
 258         /* EIPT: External (outer) IP header type */
 259         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 260                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 261         else if (ol_flags & PKT_TX_OUTER_IPV4)
 262                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 263         else if (ol_flags & PKT_TX_OUTER_IPV6)
 264                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 265
 266         /* EIPLEN: External (outer) IP header length, in DWords */
 267         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 268                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 269
 270         /* L4TUNT: L4 Tunneling Type */
 271         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 272         case PKT_TX_TUNNEL_IPIP:
 273                 /* for non UDP / GRE tunneling, set to 00b */
 274                 break;
 275         case PKT_TX_TUNNEL_VXLAN:
 276         case PKT_TX_TUNNEL_GENEVE:
 277                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 278                 break;
 279         case PKT_TX_TUNNEL_GRE:
 280                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 281                 break;
 282         default:
 283                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 284                 return;
 285         }
 286
 287         /* L4TUNLEN: L4 Tunneling Length, in Words
 288          *
 289          * We depend on app to set rte_mbuf.l2_len correctly.
 290          * For IP in GRE it should be set to the length of the GRE
 291          * header;
 292          * for MAC in GRE or MAC in UDP it should be set to the length
 293          * of the GRE or UDP headers plus the inner MAC up to including
 294          * its last Ethertype.
 295          */
 296         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 297                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 298 }
 299
 300 static inline void
 301 i40e_txd_enable_checksum(uint64_t ol_flags,
 302                         uint32_t *td_cmd,
 303                         uint32_t *td_offset,
 304                         union i40e_tx_offload tx_offload)
 305 {
 306         /* Set MACLEN */
 307         if (ol_flags & PKT_TX_TUNNEL_MASK)
 308                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 309                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 310         else
 311                 *td_offset |= (tx_offload.l2_len >> 1)
 312                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 313
 314         /* Enable L3 checksum offloads */
 315         if (ol_flags & PKT_TX_IP_CKSUM) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 317                 *td_offset |= (tx_offload.l3_len >> 2)
 318                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 319         } else if (ol_flags & PKT_TX_IPV4) {
 320                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 321                 *td_offset |= (tx_offload.l3_len >> 2)
 322                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 323         } else if (ol_flags & PKT_TX_IPV6) {
 324                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 325                 *td_offset |= (tx_offload.l3_len >> 2)
 326                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 327         }
 328
 329         if (ol_flags & PKT_TX_TCP_SEG) {
 330                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 331                 *td_offset |= (tx_offload.l4_len >> 2)
 332                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 333                 return;
 334         }
 335
 336         /* Enable L4 checksum offloads */
 337         switch (ol_flags & PKT_TX_L4_MASK) {
 338         case PKT_TX_TCP_CKSUM:
 339                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 340                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 341                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 342                 break;
 343         case PKT_TX_SCTP_CKSUM:
 344                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 345                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 346                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 347                 break;
 348         case PKT_TX_UDP_CKSUM:
 349                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 350                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 351                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 352                 break;
 353         default:
 354                 break;
 355         }
 356 }
 357
 358 /* Construct the tx flags */
 359 static inline uint64_t
 360 i40e_build_ctob(uint32_t td_cmd,
 361                 uint32_t td_offset,
 362                 unsigned int size,
 363                 uint32_t td_tag)
 364 {
 365         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 366                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 367                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 368                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 369                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 370 }
 371
 372 static inline int
 373 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 374 {
 375         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 376         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 377         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 378         uint16_t nb_tx_desc = txq->nb_tx_desc;
 379         uint16_t desc_to_clean_to;
 380         uint16_t nb_tx_to_clean;
 381
 382         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 383         if (desc_to_clean_to >= nb_tx_desc)
 384                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 385
 386         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 387         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 388                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 389                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 390                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 391                         "(port=%d queue=%d)", desc_to_clean_to,
 392                                 txq->port_id, txq->queue_id);
 393                 return -1;
 394         }
 395
 396         if (last_desc_cleaned > desc_to_clean_to)
 397                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 398                                                         desc_to_clean_to);
 399         else
 400                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 401                                         last_desc_cleaned);
 402
 403         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 404
 405         txq->last_desc_cleaned = desc_to_clean_to;
 406         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 407
 408         return 0;
 409 }
 410
 411 static inline int
 412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 413 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 414 #else
 415 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 416 #endif
 417 {
 418         int ret = 0;
 419
 420 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 421         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 422                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 423                              "rxq->rx_free_thresh=%d, "
 424                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 425                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 426                 ret = -EINVAL;
 427         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 428                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 429                              "rxq->rx_free_thresh=%d, "
 430                              "rxq->nb_rx_desc=%d",
 431                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 432                 ret = -EINVAL;
 433         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 434                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 435                              "rxq->nb_rx_desc=%d, "
 436                              "rxq->rx_free_thresh=%d",
 437                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 438                 ret = -EINVAL;
 439         }
 440 #else
 441         ret = -EINVAL;
 442 #endif
 443
 444         return ret;
 445 }
 446
 447 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 448 #define I40E_LOOK_AHEAD 8
 449 #if (I40E_LOOK_AHEAD != 8)
 450 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 451 #endif
 452 static inline int
 453 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 454 {
 455         volatile union i40e_rx_desc *rxdp;
 456         struct i40e_rx_entry *rxep;
 457         struct rte_mbuf *mb;
 458         uint16_t pkt_len;
 459         uint64_t qword1;
 460         uint32_t rx_status;
 461         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 462         int32_t i, j, nb_rx = 0;
 463         uint64_t pkt_flags;
 464         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 465
 466         rxdp = &rxq->rx_ring[rxq->rx_tail];
 467         rxep = &rxq->sw_ring[rxq->rx_tail];
 468
 469         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 470         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 471                                 I40E_RXD_QW1_STATUS_SHIFT;
 472
 473         /* Make sure there is at least 1 packet to receive */
 474         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 475                 return 0;
 476
 477         /**
 478          * Scan LOOK_AHEAD descriptors at a time to determine which
 479          * descriptors reference packets that are ready to be received.
 480          */
 481         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 482                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 483                 /* Read desc statuses backwards to avoid race condition */
 484                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 485                         qword1 = rte_le_to_cpu_64(\
 486                                 rxdp[j].wb.qword1.status_error_len);
 487                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 488                                         I40E_RXD_QW1_STATUS_SHIFT;
 489                 }
 490
 491                 rte_smp_rmb();
 492
 493                 /* Compute how many status bits were set */
 494                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 495                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 496
 497                 nb_rx += nb_dd;
 498
 499                 /* Translate descriptor info to mbuf parameters */
 500                 for (j = 0; j < nb_dd; j++) {
 501                         mb = rxep[j].mbuf;
 502                         qword1 = rte_le_to_cpu_64(\
 503                                 rxdp[j].wb.qword1.status_error_len);
 504                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 505                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 506                         mb->data_len = pkt_len;
 507                         mb->pkt_len = pkt_len;
 508                         mb->ol_flags = 0;
 509                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 510                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 511                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 512                         mb->packet_type =
 513                                 ptype_tbl[(uint8_t)((qword1 &
 514                                 I40E_RXD_QW1_PTYPE_MASK) >>
 515                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 516                         if (pkt_flags & PKT_RX_RSS_HASH)
 517                                 mb->hash.rss = rte_le_to_cpu_32(\
 518                                         rxdp[j].wb.qword0.hi_dword.rss);
 519                         if (pkt_flags & PKT_RX_FDIR)
 520                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 521
 522 #ifdef RTE_LIBRTE_IEEE1588
 523                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 524 #endif
 525                         mb->ol_flags |= pkt_flags;
 526
 527                 }
 528
 529                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 530                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 531
 532                 if (nb_dd != I40E_LOOK_AHEAD)
 533                         break;
 534         }
 535
 536         /* Clear software ring entries */
 537         for (i = 0; i < nb_rx; i++)
 538                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 539
 540         return nb_rx;
 541 }
 542
 543 static inline uint16_t
 544 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 545                         struct rte_mbuf **rx_pkts,
 546                         uint16_t nb_pkts)
 547 {
 548         uint16_t i;
 549         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 550
 551         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 552
 553         for (i = 0; i < nb_pkts; i++)
 554                 rx_pkts[i] = stage[i];
 555
 556         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 557         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 558
 559         return nb_pkts;
 560 }
 561
 562 static inline int
 563 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 564 {
 565         volatile union i40e_rx_desc *rxdp;
 566         struct i40e_rx_entry *rxep;
 567         struct rte_mbuf *mb;
 568         uint16_t alloc_idx, i;
 569         uint64_t dma_addr;
 570         int diag;
 571
 572         /* Allocate buffers in bulk */
 573         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 574                                 (rxq->rx_free_thresh - 1));
 575         rxep = &(rxq->sw_ring[alloc_idx]);
 576         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 577                                         rxq->rx_free_thresh);
 578         if (unlikely(diag != 0)) {
 579                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 580                 return -ENOMEM;
 581         }
 582
 583         rxdp = &rxq->rx_ring[alloc_idx];
 584         for (i = 0; i < rxq->rx_free_thresh; i++) {
 585                 if (likely(i < (rxq->rx_free_thresh - 1)))
 586                         /* Prefetch next mbuf */
 587                         rte_prefetch0(rxep[i + 1].mbuf);
 588
 589                 mb = rxep[i].mbuf;
 590                 rte_mbuf_refcnt_set(mb, 1);
 591                 mb->next = NULL;
 592                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 593                 mb->nb_segs = 1;
 594                 mb->port = rxq->port_id;
 595                 dma_addr = rte_cpu_to_le_64(\
 596                         rte_mbuf_data_iova_default(mb));
 597                 rxdp[i].read.hdr_addr = 0;
 598                 rxdp[i].read.pkt_addr = dma_addr;
 599         }
 600
 601         /* Update rx tail regsiter */
 602         rte_wmb();
 603         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 604
 605         rxq->rx_free_trigger =
 606                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 607         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 608                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 609
 610         return 0;
 611 }
 612
 613 static inline uint16_t
 614 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 615 {
 616         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 617         struct rte_eth_dev *dev;
 618         uint16_t nb_rx = 0;
 619
 620         if (!nb_pkts)
 621                 return 0;
 622
 623         if (rxq->rx_nb_avail)
 624                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 625
 626         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 627         rxq->rx_next_avail = 0;
 628         rxq->rx_nb_avail = nb_rx;
 629         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 630
 631         if (rxq->rx_tail > rxq->rx_free_trigger) {
 632                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 633                         uint16_t i, j;
 634
 635                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 636                         dev->data->rx_mbuf_alloc_failed +=
 637                                 rxq->rx_free_thresh;
 638
 639                         rxq->rx_nb_avail = 0;
 640                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 641                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 642                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 643
 644                         return 0;
 645                 }
 646         }
 647
 648         if (rxq->rx_tail >= rxq->nb_rx_desc)
 649                 rxq->rx_tail = 0;
 650
 651         if (rxq->rx_nb_avail)
 652                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 653
 654         return 0;
 655 }
 656
 657 static uint16_t
 658 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 659                           struct rte_mbuf **rx_pkts,
 660                           uint16_t nb_pkts)
 661 {
 662         uint16_t nb_rx = 0, n, count;
 663
 664         if (unlikely(nb_pkts == 0))
 665                 return 0;
 666
 667         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 668                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 669
 670         while (nb_pkts) {
 671                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 672                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 673                 nb_rx = (uint16_t)(nb_rx + count);
 674                 nb_pkts = (uint16_t)(nb_pkts - count);
 675                 if (count < n)
 676                         break;
 677         }
 678
 679         return nb_rx;
 680 }
 681 #else
 682 static uint16_t
 683 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 684                           struct rte_mbuf __rte_unused **rx_pkts,
 685                           uint16_t __rte_unused nb_pkts)
 686 {
 687         return 0;
 688 }
 689 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 690
 691 uint16_t
 692 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 693 {
 694         struct i40e_rx_queue *rxq;
 695         volatile union i40e_rx_desc *rx_ring;
 696         volatile union i40e_rx_desc *rxdp;
 697         union i40e_rx_desc rxd;
 698         struct i40e_rx_entry *sw_ring;
 699         struct i40e_rx_entry *rxe;
 700         struct rte_eth_dev *dev;
 701         struct rte_mbuf *rxm;
 702         struct rte_mbuf *nmb;
 703         uint16_t nb_rx;
 704         uint32_t rx_status;
 705         uint64_t qword1;
 706         uint16_t rx_packet_len;
 707         uint16_t rx_id, nb_hold;
 708         uint64_t dma_addr;
 709         uint64_t pkt_flags;
 710         uint32_t *ptype_tbl;
 711
 712         nb_rx = 0;
 713         nb_hold = 0;
 714         rxq = rx_queue;
 715         rx_id = rxq->rx_tail;
 716         rx_ring = rxq->rx_ring;
 717         sw_ring = rxq->sw_ring;
 718         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 719
 720         while (nb_rx < nb_pkts) {
 721                 rxdp = &rx_ring[rx_id];
 722                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 723                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 724                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 725
 726                 /* Check the DD bit first */
 727                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 728                         break;
 729
 730                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 731                 if (unlikely(!nmb)) {
 732                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 733                         dev->data->rx_mbuf_alloc_failed++;
 734                         break;
 735                 }
 736
 737                 rxd = *rxdp;
 738                 nb_hold++;
 739                 rxe = &sw_ring[rx_id];
 740                 rx_id++;
 741                 if (unlikely(rx_id == rxq->nb_rx_desc))
 742                         rx_id = 0;
 743
 744                 /* Prefetch next mbuf */
 745                 rte_prefetch0(sw_ring[rx_id].mbuf);
 746
 747                 /**
 748                  * When next RX descriptor is on a cache line boundary,
 749                  * prefetch the next 4 RX descriptors and next 8 pointers
 750                  * to mbufs.
 751                  */
 752                 if ((rx_id & 0x3) == 0) {
 753                         rte_prefetch0(&rx_ring[rx_id]);
 754                         rte_prefetch0(&sw_ring[rx_id]);
 755                 }
 756                 rxm = rxe->mbuf;
 757                 rxe->mbuf = nmb;
 758                 dma_addr =
 759                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 760                 rxdp->read.hdr_addr = 0;
 761                 rxdp->read.pkt_addr = dma_addr;
 762
 763                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 764                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 765
 766                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 767                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 768                 rxm->nb_segs = 1;
 769                 rxm->next = NULL;
 770                 rxm->pkt_len = rx_packet_len;
 771                 rxm->data_len = rx_packet_len;
 772                 rxm->port = rxq->port_id;
 773                 rxm->ol_flags = 0;
 774                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 775                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 776                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 777                 rxm->packet_type =
 778                         ptype_tbl[(uint8_t)((qword1 &
 779                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 780                 if (pkt_flags & PKT_RX_RSS_HASH)
 781                         rxm->hash.rss =
 782                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 783                 if (pkt_flags & PKT_RX_FDIR)
 784                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 785
 786 #ifdef RTE_LIBRTE_IEEE1588
 787                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 788 #endif
 789                 rxm->ol_flags |= pkt_flags;
 790
 791                 rx_pkts[nb_rx++] = rxm;
 792         }
 793         rxq->rx_tail = rx_id;
 794
 795         /**
 796          * If the number of free RX descriptors is greater than the RX free
 797          * threshold of the queue, advance the receive tail register of queue.
 798          * Update that register with the value of the last processed RX
 799          * descriptor minus 1.
 800          */
 801         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 802         if (nb_hold > rxq->rx_free_thresh) {
 803                 rx_id = (uint16_t) ((rx_id == 0) ?
 804                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 805                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 806                 nb_hold = 0;
 807         }
 808         rxq->nb_rx_hold = nb_hold;
 809
 810         return nb_rx;
 811 }
 812
 813 uint16_t
 814 i40e_recv_scattered_pkts(void *rx_queue,
 815                          struct rte_mbuf **rx_pkts,
 816                          uint16_t nb_pkts)
 817 {
 818         struct i40e_rx_queue *rxq = rx_queue;
 819         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 820         volatile union i40e_rx_desc *rxdp;
 821         union i40e_rx_desc rxd;
 822         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 823         struct i40e_rx_entry *rxe;
 824         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 825         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 826         struct rte_mbuf *nmb, *rxm;
 827         uint16_t rx_id = rxq->rx_tail;
 828         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 829         struct rte_eth_dev *dev;
 830         uint32_t rx_status;
 831         uint64_t qword1;
 832         uint64_t dma_addr;
 833         uint64_t pkt_flags;
 834         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 835
 836         while (nb_rx < nb_pkts) {
 837                 rxdp = &rx_ring[rx_id];
 838                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 839                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 840                                         I40E_RXD_QW1_STATUS_SHIFT;
 841
 842                 /* Check the DD bit */
 843                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 844                         break;
 845
 846                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 847                 if (unlikely(!nmb)) {
 848                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 849                         dev->data->rx_mbuf_alloc_failed++;
 850                         break;
 851                 }
 852
 853                 rxd = *rxdp;
 854                 nb_hold++;
 855                 rxe = &sw_ring[rx_id];
 856                 rx_id++;
 857                 if (rx_id == rxq->nb_rx_desc)
 858                         rx_id = 0;
 859
 860                 /* Prefetch next mbuf */
 861                 rte_prefetch0(sw_ring[rx_id].mbuf);
 862
 863                 /**
 864                  * When next RX descriptor is on a cache line boundary,
 865                  * prefetch the next 4 RX descriptors and next 8 pointers
 866                  * to mbufs.
 867                  */
 868                 if ((rx_id & 0x3) == 0) {
 869                         rte_prefetch0(&rx_ring[rx_id]);
 870                         rte_prefetch0(&sw_ring[rx_id]);
 871                 }
 872
 873                 rxm = rxe->mbuf;
 874                 rxe->mbuf = nmb;
 875                 dma_addr =
 876                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 877
 878                 /* Set data buffer address and data length of the mbuf */
 879                 rxdp->read.hdr_addr = 0;
 880                 rxdp->read.pkt_addr = dma_addr;
 881                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 882                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 883                 rxm->data_len = rx_packet_len;
 884                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 885
 886                 /**
 887                  * If this is the first buffer of the received packet, set the
 888                  * pointer to the first mbuf of the packet and initialize its
 889                  * context. Otherwise, update the total length and the number
 890                  * of segments of the current scattered packet, and update the
 891                  * pointer to the last mbuf of the current packet.
 892                  */
 893                 if (!first_seg) {
 894                         first_seg = rxm;
 895                         first_seg->nb_segs = 1;
 896                         first_seg->pkt_len = rx_packet_len;
 897                 } else {
 898                         first_seg->pkt_len =
 899                                 (uint16_t)(first_seg->pkt_len +
 900                                                 rx_packet_len);
 901                         first_seg->nb_segs++;
 902                         last_seg->next = rxm;
 903                 }
 904
 905                 /**
 906                  * If this is not the last buffer of the received packet,
 907                  * update the pointer to the last mbuf of the current scattered
 908                  * packet and continue to parse the RX ring.
 909                  */
 910                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 911                         last_seg = rxm;
 912                         continue;
 913                 }
 914
 915                 /**
 916                  * This is the last buffer of the received packet. If the CRC
 917                  * is not stripped by the hardware:
 918                  *  - Subtract the CRC length from the total packet length.
 919                  *  - If the last buffer only contains the whole CRC or a part
 920                  *  of it, free the mbuf associated to the last buffer. If part
 921                  *  of the CRC is also contained in the previous mbuf, subtract
 922                  *  the length of that CRC part from the data length of the
 923                  *  previous mbuf.
 924                  */
 925                 rxm->next = NULL;
 926                 if (unlikely(rxq->crc_len > 0)) {
 927                         first_seg->pkt_len -= ETHER_CRC_LEN;
 928                         if (rx_packet_len <= ETHER_CRC_LEN) {
 929                                 rte_pktmbuf_free_seg(rxm);
 930                                 first_seg->nb_segs--;
 931                                 last_seg->data_len =
 932                                         (uint16_t)(last_seg->data_len -
 933                                         (ETHER_CRC_LEN - rx_packet_len));
 934                                 last_seg->next = NULL;
 935                         } else
 936                                 rxm->data_len = (uint16_t)(rx_packet_len -
 937                                                                 ETHER_CRC_LEN);
 938                 }
 939
 940                 first_seg->port = rxq->port_id;
 941                 first_seg->ol_flags = 0;
 942                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 943                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 944                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 945                 first_seg->packet_type =
 946                         ptype_tbl[(uint8_t)((qword1 &
 947                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 948                 if (pkt_flags & PKT_RX_RSS_HASH)
 949                         first_seg->hash.rss =
 950                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 951                 if (pkt_flags & PKT_RX_FDIR)
 952                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 953
 954 #ifdef RTE_LIBRTE_IEEE1588
 955                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 956 #endif
 957                 first_seg->ol_flags |= pkt_flags;
 958
 959                 /* Prefetch data of first segment, if configured to do so. */
 960                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 961                         first_seg->data_off));
 962                 rx_pkts[nb_rx++] = first_seg;
 963                 first_seg = NULL;
 964         }
 965
 966         /* Record index of the next RX descriptor to probe. */
 967         rxq->rx_tail = rx_id;
 968         rxq->pkt_first_seg = first_seg;
 969         rxq->pkt_last_seg = last_seg;
 970
 971         /**
 972          * If the number of free RX descriptors is greater than the RX free
 973          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 974          * register. Update the RDT with the value of the last processed RX
 975          * descriptor minus 1, to guarantee that the RDT register is never
 976          * equal to the RDH register, which creates a "full" ring situtation
 977          * from the hardware point of view.
 978          */
 979         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 980         if (nb_hold > rxq->rx_free_thresh) {
 981                 rx_id = (uint16_t)(rx_id == 0 ?
 982                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 983                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 984                 nb_hold = 0;
 985         }
 986         rxq->nb_rx_hold = nb_hold;
 987
 988         return nb_rx;
 989 }
 990
 991 /* Check if the context descriptor is needed for TX offloading */
 992 static inline uint16_t
 993 i40e_calc_context_desc(uint64_t flags)
 994 {
 995         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 996                 PKT_TX_TCP_SEG |
 997                 PKT_TX_QINQ_PKT |
 998                 PKT_TX_TUNNEL_MASK;
 999
1000 #ifdef RTE_LIBRTE_IEEE1588
1001         mask |= PKT_TX_IEEE1588_TMST;
1002 #endif
1003
1004         return (flags & mask) ? 1 : 0;
1005 }
1006
1007 /* set i40e TSO context descriptor */
1008 static inline uint64_t
1009 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1010 {
1011         uint64_t ctx_desc = 0;
1012         uint32_t cd_cmd, hdr_len, cd_tso_len;
1013
1014         if (!tx_offload.l4_len) {
1015                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1016                 return ctx_desc;
1017         }
1018
1019         /**
1020          * in case of non tunneling packet, the outer_l2_len and
1021          * outer_l3_len must be 0.
1022          */
1023         hdr_len = tx_offload.outer_l2_len +
1024                 tx_offload.outer_l3_len +
1025                 tx_offload.l2_len +
1026                 tx_offload.l3_len +
1027                 tx_offload.l4_len;
1028
1029         cd_cmd = I40E_TX_CTX_DESC_TSO;
1030         cd_tso_len = mbuf->pkt_len - hdr_len;
1031         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1032                 ((uint64_t)cd_tso_len <<
1033                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1034                 ((uint64_t)mbuf->tso_segsz <<
1035                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1036
1037         return ctx_desc;
1038 }
1039
1040 uint16_t
1041 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1042 {
1043         struct i40e_tx_queue *txq;
1044         struct i40e_tx_entry *sw_ring;
1045         struct i40e_tx_entry *txe, *txn;
1046         volatile struct i40e_tx_desc *txd;
1047         volatile struct i40e_tx_desc *txr;
1048         struct rte_mbuf *tx_pkt;
1049         struct rte_mbuf *m_seg;
1050         uint32_t cd_tunneling_params;
1051         uint16_t tx_id;
1052         uint16_t nb_tx;
1053         uint32_t td_cmd;
1054         uint32_t td_offset;
1055         uint32_t td_tag;
1056         uint64_t ol_flags;
1057         uint16_t nb_used;
1058         uint16_t nb_ctx;
1059         uint16_t tx_last;
1060         uint16_t slen;
1061         uint64_t buf_dma_addr;
1062         union i40e_tx_offload tx_offload = {0};
1063
1064         txq = tx_queue;
1065         sw_ring = txq->sw_ring;
1066         txr = txq->tx_ring;
1067         tx_id = txq->tx_tail;
1068         txe = &sw_ring[tx_id];
1069
1070         /* Check if the descriptor ring needs to be cleaned. */
1071         if (txq->nb_tx_free < txq->tx_free_thresh)
1072                 i40e_xmit_cleanup(txq);
1073
1074         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1075                 td_cmd = 0;
1076                 td_tag = 0;
1077                 td_offset = 0;
1078
1079                 tx_pkt = *tx_pkts++;
1080                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1081
1082                 ol_flags = tx_pkt->ol_flags;
1083                 tx_offload.l2_len = tx_pkt->l2_len;
1084                 tx_offload.l3_len = tx_pkt->l3_len;
1085                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1086                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1087                 tx_offload.l4_len = tx_pkt->l4_len;
1088                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1089
1090                 /* Calculate the number of context descriptors needed. */
1091                 nb_ctx = i40e_calc_context_desc(ol_flags);
1092
1093                 /**
1094                  * The number of descriptors that must be allocated for
1095                  * a packet equals to the number of the segments of that
1096                  * packet plus 1 context descriptor if needed.
1097                  */
1098                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1099                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1100
1101                 /* Circular ring */
1102                 if (tx_last >= txq->nb_tx_desc)
1103                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1104
1105                 if (nb_used > txq->nb_tx_free) {
1106                         if (i40e_xmit_cleanup(txq) != 0) {
1107                                 if (nb_tx == 0)
1108                                         return 0;
1109                                 goto end_of_tx;
1110                         }
1111                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1112                                 while (nb_used > txq->nb_tx_free) {
1113                                         if (i40e_xmit_cleanup(txq) != 0) {
1114                                                 if (nb_tx == 0)
1115                                                         return 0;
1116                                                 goto end_of_tx;
1117                                         }
1118                                 }
1119                         }
1120                 }
1121
1122                 /* Descriptor based VLAN insertion */
1123                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1124                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1125                         td_tag = tx_pkt->vlan_tci;
1126                 }
1127
1128                 /* Always enable CRC offload insertion */
1129                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1130
1131                 /* Fill in tunneling parameters if necessary */
1132                 cd_tunneling_params = 0;
1133                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1134                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1135                                                     &cd_tunneling_params);
1136                 /* Enable checksum offloading */
1137                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1138                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1139                                                  &td_offset, tx_offload);
1140
1141                 if (nb_ctx) {
1142                         /* Setup TX context descriptor if required */
1143                         volatile struct i40e_tx_context_desc *ctx_txd =
1144                                 (volatile struct i40e_tx_context_desc *)\
1145                                                         &txr[tx_id];
1146                         uint16_t cd_l2tag2 = 0;
1147                         uint64_t cd_type_cmd_tso_mss =
1148                                 I40E_TX_DESC_DTYPE_CONTEXT;
1149
1150                         txn = &sw_ring[txe->next_id];
1151                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1152                         if (txe->mbuf != NULL) {
1153                                 rte_pktmbuf_free_seg(txe->mbuf);
1154                                 txe->mbuf = NULL;
1155                         }
1156
1157                         /* TSO enabled means no timestamp */
1158                         if (ol_flags & PKT_TX_TCP_SEG)
1159                                 cd_type_cmd_tso_mss |=
1160                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1161                         else {
1162 #ifdef RTE_LIBRTE_IEEE1588
1163                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1164                                         cd_type_cmd_tso_mss |=
1165                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1166                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1167 #endif
1168                         }
1169
1170                         ctx_txd->tunneling_params =
1171                                 rte_cpu_to_le_32(cd_tunneling_params);
1172                         if (ol_flags & PKT_TX_QINQ_PKT) {
1173                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1174                                 cd_type_cmd_tso_mss |=
1175                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1176                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1177                         }
1178                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1179                         ctx_txd->type_cmd_tso_mss =
1180                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1181
1182                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1183                                 "tunneling_params: %#x;\n"
1184                                 "l2tag2: %#hx;\n"
1185                                 "rsvd: %#hx;\n"
1186                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1187                                 tx_pkt, tx_id,
1188                                 ctx_txd->tunneling_params,
1189                                 ctx_txd->l2tag2,
1190                                 ctx_txd->rsvd,
1191                                 ctx_txd->type_cmd_tso_mss);
1192
1193                         txe->last_id = tx_last;
1194                         tx_id = txe->next_id;
1195                         txe = txn;
1196                 }
1197
1198                 m_seg = tx_pkt;
1199                 do {
1200                         txd = &txr[tx_id];
1201                         txn = &sw_ring[txe->next_id];
1202
1203                         if (txe->mbuf)
1204                                 rte_pktmbuf_free_seg(txe->mbuf);
1205                         txe->mbuf = m_seg;
1206
1207                         /* Setup TX Descriptor */
1208                         slen = m_seg->data_len;
1209                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1210
1211                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1212                                 "buf_dma_addr: %#"PRIx64";\n"
1213                                 "td_cmd: %#x;\n"
1214                                 "td_offset: %#x;\n"
1215                                 "td_len: %u;\n"
1216                                 "td_tag: %#x;\n",
1217                                 tx_pkt, tx_id, buf_dma_addr,
1218                                 td_cmd, td_offset, slen, td_tag);
1219
1220                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1221                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1222                                                 td_offset, slen, td_tag);
1223                         txe->last_id = tx_last;
1224                         tx_id = txe->next_id;
1225                         txe = txn;
1226                         m_seg = m_seg->next;
1227                 } while (m_seg != NULL);
1228
1229                 /* The last packet data descriptor needs End Of Packet (EOP) */
1230                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1231                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1232                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1233
1234                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1235                         PMD_TX_FREE_LOG(DEBUG,
1236                                         "Setting RS bit on TXD id="
1237                                         "%4u (port=%d queue=%d)",
1238                                         tx_last, txq->port_id, txq->queue_id);
1239
1240                         td_cmd |= I40E_TX_DESC_CMD_RS;
1241
1242                         /* Update txq RS bit counters */
1243                         txq->nb_tx_used = 0;
1244                 }
1245
1246                 txd->cmd_type_offset_bsz |=
1247                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1248                                         I40E_TXD_QW1_CMD_SHIFT);
1249         }
1250
1251 end_of_tx:
1252         rte_wmb();
1253
1254         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1255                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1256                    (unsigned) tx_id, (unsigned) nb_tx);
1257
1258         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1259         txq->tx_tail = tx_id;
1260
1261         return nb_tx;
1262 }
1263
1264 static __rte_always_inline int
1265 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1266 {
1267         struct i40e_tx_entry *txep;
1268         uint16_t i;
1269
1270         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1271                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1272                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1273                 return 0;
1274
1275         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1276
1277         for (i = 0; i < txq->tx_rs_thresh; i++)
1278                 rte_prefetch0((txep + i)->mbuf);
1279
1280         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1281                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1282                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1283                         txep->mbuf = NULL;
1284                 }
1285         } else {
1286                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1287                         rte_pktmbuf_free_seg(txep->mbuf);
1288                         txep->mbuf = NULL;
1289                 }
1290         }
1291
1292         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1293         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1294         if (txq->tx_next_dd >= txq->nb_tx_desc)
1295                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1296
1297         return txq->tx_rs_thresh;
1298 }
1299
1300 /* Populate 4 descriptors with data from 4 mbufs */
1301 static inline void
1302 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1303 {
1304         uint64_t dma_addr;
1305         uint32_t i;
1306
1307         for (i = 0; i < 4; i++, txdp++, pkts++) {
1308                 dma_addr = rte_mbuf_data_iova(*pkts);
1309                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1310                 txdp->cmd_type_offset_bsz =
1311                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1312                                         (*pkts)->data_len, 0);
1313         }
1314 }
1315
1316 /* Populate 1 descriptor with data from 1 mbuf */
1317 static inline void
1318 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1319 {
1320         uint64_t dma_addr;
1321
1322         dma_addr = rte_mbuf_data_iova(*pkts);
1323         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1324         txdp->cmd_type_offset_bsz =
1325                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1326                                 (*pkts)->data_len, 0);
1327 }
1328
1329 /* Fill hardware descriptor ring with mbuf data */
1330 static inline void
1331 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1332                      struct rte_mbuf **pkts,
1333                      uint16_t nb_pkts)
1334 {
1335         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1336         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1337         const int N_PER_LOOP = 4;
1338         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1339         int mainpart, leftover;
1340         int i, j;
1341
1342         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1343         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1344         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1345                 for (j = 0; j < N_PER_LOOP; ++j) {
1346                         (txep + i + j)->mbuf = *(pkts + i + j);
1347                 }
1348                 tx4(txdp + i, pkts + i);
1349         }
1350         if (unlikely(leftover > 0)) {
1351                 for (i = 0; i < leftover; ++i) {
1352                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1353                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1354                 }
1355         }
1356 }
1357
1358 static inline uint16_t
1359 tx_xmit_pkts(struct i40e_tx_queue *txq,
1360              struct rte_mbuf **tx_pkts,
1361              uint16_t nb_pkts)
1362 {
1363         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1364         uint16_t n = 0;
1365
1366         /**
1367          * Begin scanning the H/W ring for done descriptors when the number
1368          * of available descriptors drops below tx_free_thresh. For each done
1369          * descriptor, free the associated buffer.
1370          */
1371         if (txq->nb_tx_free < txq->tx_free_thresh)
1372                 i40e_tx_free_bufs(txq);
1373
1374         /* Use available descriptor only */
1375         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1376         if (unlikely(!nb_pkts))
1377                 return 0;
1378
1379         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1380         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1381                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1382                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1383                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1384                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1385                                                 I40E_TXD_QW1_CMD_SHIFT);
1386                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1387                 txq->tx_tail = 0;
1388         }
1389
1390         /* Fill hardware descriptor ring with mbuf data */
1391         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1392         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1393
1394         /* Determin if RS bit needs to be set */
1395         if (txq->tx_tail > txq->tx_next_rs) {
1396                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1397                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1398                                                 I40E_TXD_QW1_CMD_SHIFT);
1399                 txq->tx_next_rs =
1400                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1401                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1402                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1403         }
1404
1405         if (txq->tx_tail >= txq->nb_tx_desc)
1406                 txq->tx_tail = 0;
1407
1408         /* Update the tx tail register */
1409         rte_wmb();
1410         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1411
1412         return nb_pkts;
1413 }
1414
1415 static uint16_t
1416 i40e_xmit_pkts_simple(void *tx_queue,
1417                       struct rte_mbuf **tx_pkts,
1418                       uint16_t nb_pkts)
1419 {
1420         uint16_t nb_tx = 0;
1421
1422         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1423                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1424                                                 tx_pkts, nb_pkts);
1425
1426         while (nb_pkts) {
1427                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1428                                                 I40E_TX_MAX_BURST);
1429
1430                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1431                                                 &tx_pkts[nb_tx], num);
1432                 nb_tx = (uint16_t)(nb_tx + ret);
1433                 nb_pkts = (uint16_t)(nb_pkts - ret);
1434                 if (ret < num)
1435                         break;
1436         }
1437
1438         return nb_tx;
1439 }
1440
1441 static uint16_t
1442 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1443                    uint16_t nb_pkts)
1444 {
1445         uint16_t nb_tx = 0;
1446         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1447
1448         while (nb_pkts) {
1449                 uint16_t ret, num;
1450
1451                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1452                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1453                                                 num);
1454                 nb_tx += ret;
1455                 nb_pkts -= ret;
1456                 if (ret < num)
1457                         break;
1458         }
1459
1460         return nb_tx;
1461 }
1462
1463 /*********************************************************************
1464  *
1465  *  TX prep functions
1466  *
1467  **********************************************************************/
1468 uint16_t
1469 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1470                 uint16_t nb_pkts)
1471 {
1472         int i, ret;
1473         uint64_t ol_flags;
1474         struct rte_mbuf *m;
1475
1476         for (i = 0; i < nb_pkts; i++) {
1477                 m = tx_pkts[i];
1478                 ol_flags = m->ol_flags;
1479
1480                 /* Check for m->nb_segs to not exceed the limits. */
1481                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1482                         if (m->nb_segs > I40E_TX_MAX_SEG ||
1483                             m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1484                                 rte_errno = -EINVAL;
1485                                 return i;
1486                         }
1487                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1488                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1489                         /* MSS outside the range (256B - 9674B) are considered
1490                          * malicious
1491                          */
1492                         rte_errno = -EINVAL;
1493                         return i;
1494                 }
1495
1496                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1497                         rte_errno = -ENOTSUP;
1498                         return i;
1499                 }
1500
1501 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1502                 ret = rte_validate_tx_offload(m);
1503                 if (ret != 0) {
1504                         rte_errno = ret;
1505                         return i;
1506                 }
1507 #endif
1508                 ret = rte_net_intel_cksum_prepare(m);
1509                 if (ret != 0) {
1510                         rte_errno = ret;
1511                         return i;
1512                 }
1513         }
1514         return i;
1515 }
1516
1517 /*
1518  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1519  * application used, which assume having sequential ones. But from driver's
1520  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1521  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1522  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1523  * use queue_idx from 0 to 95 to access queues, while real queue would be
1524  * different. This function will do a queue mapping to find VSI the queue
1525  * belongs to.
1526  */
1527 static struct i40e_vsi*
1528 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1529 {
1530         /* the queue in MAIN VSI range */
1531         if (queue_idx < pf->main_vsi->nb_qps)
1532                 return pf->main_vsi;
1533
1534         queue_idx -= pf->main_vsi->nb_qps;
1535
1536         /* queue_idx is greater than VMDQ VSIs range */
1537         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1538                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1539                 return NULL;
1540         }
1541
1542         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1543 }
1544
1545 static uint16_t
1546 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1547 {
1548         /* the queue in MAIN VSI range */
1549         if (queue_idx < pf->main_vsi->nb_qps)
1550                 return queue_idx;
1551
1552         /* It's VMDQ queues */
1553         queue_idx -= pf->main_vsi->nb_qps;
1554
1555         if (pf->nb_cfg_vmdq_vsi)
1556                 return queue_idx % pf->vmdq_nb_qps;
1557         else {
1558                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1559                 return (uint16_t)(-1);
1560         }
1561 }
1562
1563 int
1564 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1565 {
1566         struct i40e_rx_queue *rxq;
1567         int err = -1;
1568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         if (rx_queue_id < dev->data->nb_rx_queues) {
1573                 rxq = dev->data->rx_queues[rx_queue_id];
1574
1575                 err = i40e_alloc_rx_queue_mbufs(rxq);
1576                 if (err) {
1577                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1578                         return err;
1579                 }
1580
1581                 rte_wmb();
1582
1583                 /* Init the RX tail regieter. */
1584                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1585
1586                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1587
1588                 if (err) {
1589                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1590                                     rx_queue_id);
1591
1592                         i40e_rx_queue_release_mbufs(rxq);
1593                         i40e_reset_rx_queue(rxq);
1594                 } else
1595                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1596         }
1597
1598         return err;
1599 }
1600
1601 int
1602 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1603 {
1604         struct i40e_rx_queue *rxq;
1605         int err;
1606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607
1608         if (rx_queue_id < dev->data->nb_rx_queues) {
1609                 rxq = dev->data->rx_queues[rx_queue_id];
1610
1611                 /*
1612                 * rx_queue_id is queue id application refers to, while
1613                 * rxq->reg_idx is the real queue index.
1614                 */
1615                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1616
1617                 if (err) {
1618                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1619                                     rx_queue_id);
1620                         return err;
1621                 }
1622                 i40e_rx_queue_release_mbufs(rxq);
1623                 i40e_reset_rx_queue(rxq);
1624                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1625         }
1626
1627         return 0;
1628 }
1629
1630 int
1631 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1632 {
1633         int err = -1;
1634         struct i40e_tx_queue *txq;
1635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636
1637         PMD_INIT_FUNC_TRACE();
1638
1639         if (tx_queue_id < dev->data->nb_tx_queues) {
1640                 txq = dev->data->tx_queues[tx_queue_id];
1641
1642                 /*
1643                 * tx_queue_id is queue id application refers to, while
1644                 * rxq->reg_idx is the real queue index.
1645                 */
1646                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1647                 if (err)
1648                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1649                                     tx_queue_id);
1650                 else
1651                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1652         }
1653
1654         return err;
1655 }
1656
1657 int
1658 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1659 {
1660         struct i40e_tx_queue *txq;
1661         int err;
1662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663
1664         if (tx_queue_id < dev->data->nb_tx_queues) {
1665                 txq = dev->data->tx_queues[tx_queue_id];
1666
1667                 /*
1668                 * tx_queue_id is queue id application refers to, while
1669                 * txq->reg_idx is the real queue index.
1670                 */
1671                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1672
1673                 if (err) {
1674                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1675                                     tx_queue_id);
1676                         return err;
1677                 }
1678
1679                 i40e_tx_queue_release_mbufs(txq);
1680                 i40e_reset_tx_queue(txq);
1681                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1682         }
1683
1684         return 0;
1685 }
1686
1687 const uint32_t *
1688 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1689 {
1690         static const uint32_t ptypes[] = {
1691                 /* refers to i40e_rxd_pkt_type_mapping() */
1692                 RTE_PTYPE_L2_ETHER,
1693                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1694                 RTE_PTYPE_L2_ETHER_LLDP,
1695                 RTE_PTYPE_L2_ETHER_ARP,
1696                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1697                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1698                 RTE_PTYPE_L4_FRAG,
1699                 RTE_PTYPE_L4_ICMP,
1700                 RTE_PTYPE_L4_NONFRAG,
1701                 RTE_PTYPE_L4_SCTP,
1702                 RTE_PTYPE_L4_TCP,
1703                 RTE_PTYPE_L4_UDP,
1704                 RTE_PTYPE_TUNNEL_GRENAT,
1705                 RTE_PTYPE_TUNNEL_IP,
1706                 RTE_PTYPE_INNER_L2_ETHER,
1707                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1708                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1709                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1710                 RTE_PTYPE_INNER_L4_FRAG,
1711                 RTE_PTYPE_INNER_L4_ICMP,
1712                 RTE_PTYPE_INNER_L4_NONFRAG,
1713                 RTE_PTYPE_INNER_L4_SCTP,
1714                 RTE_PTYPE_INNER_L4_TCP,
1715                 RTE_PTYPE_INNER_L4_UDP,
1716                 RTE_PTYPE_UNKNOWN
1717         };
1718
1719         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1720 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1721             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1722 #endif
1723             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1724             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1725             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1726                 return ptypes;
1727         return NULL;
1728 }
1729
1730 int
1731 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1732                         uint16_t queue_idx,
1733                         uint16_t nb_desc,
1734                         unsigned int socket_id,
1735                         const struct rte_eth_rxconf *rx_conf,
1736                         struct rte_mempool *mp)
1737 {
1738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739         struct i40e_adapter *ad =
1740                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1741         struct i40e_vsi *vsi;
1742         struct i40e_pf *pf = NULL;
1743         struct i40e_vf *vf = NULL;
1744         struct i40e_rx_queue *rxq;
1745         const struct rte_memzone *rz;
1746         uint32_t ring_size;
1747         uint16_t len, i;
1748         uint16_t reg_idx, base, bsf, tc_mapping;
1749         int q_offset, use_def_burst_func = 1;
1750
1751         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1752                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1753                 vsi = &vf->vsi;
1754                 if (!vsi)
1755                         return -EINVAL;
1756                 reg_idx = queue_idx;
1757         } else {
1758                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1759                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1760                 if (!vsi)
1761                         return -EINVAL;
1762                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1763                 if (q_offset < 0)
1764                         return -EINVAL;
1765                 reg_idx = vsi->base_queue + q_offset;
1766         }
1767
1768         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1769             (nb_desc > I40E_MAX_RING_DESC) ||
1770             (nb_desc < I40E_MIN_RING_DESC)) {
1771                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1772                             "invalid", nb_desc);
1773                 return -EINVAL;
1774         }
1775
1776         /* Free memory if needed */
1777         if (dev->data->rx_queues[queue_idx]) {
1778                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1779                 dev->data->rx_queues[queue_idx] = NULL;
1780         }
1781
1782         /* Allocate the rx queue data structure */
1783         rxq = rte_zmalloc_socket("i40e rx queue",
1784                                  sizeof(struct i40e_rx_queue),
1785                                  RTE_CACHE_LINE_SIZE,
1786                                  socket_id);
1787         if (!rxq) {
1788                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1789                             "rx queue data structure");
1790                 return -ENOMEM;
1791         }
1792         rxq->mp = mp;
1793         rxq->nb_rx_desc = nb_desc;
1794         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1795         rxq->queue_id = queue_idx;
1796         rxq->reg_idx = reg_idx;
1797         rxq->port_id = dev->data->port_id;
1798         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1799                                                         0 : ETHER_CRC_LEN);
1800         rxq->drop_en = rx_conf->rx_drop_en;
1801         rxq->vsi = vsi;
1802         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1803
1804         /* Allocate the maximun number of RX ring hardware descriptor. */
1805         len = I40E_MAX_RING_DESC;
1806
1807         /**
1808          * Allocating a little more memory because vectorized/bulk_alloc Rx
1809          * functions doesn't check boundaries each time.
1810          */
1811         len += RTE_PMD_I40E_RX_MAX_BURST;
1812
1813         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1814                               I40E_DMA_MEM_ALIGN);
1815
1816         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1817                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1818         if (!rz) {
1819                 i40e_dev_rx_queue_release(rxq);
1820                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1821                 return -ENOMEM;
1822         }
1823
1824         /* Zero all the descriptors in the ring. */
1825         memset(rz->addr, 0, ring_size);
1826
1827         rxq->rx_ring_phys_addr = rz->iova;
1828         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1829
1830         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1831
1832         /* Allocate the software ring. */
1833         rxq->sw_ring =
1834                 rte_zmalloc_socket("i40e rx sw ring",
1835                                    sizeof(struct i40e_rx_entry) * len,
1836                                    RTE_CACHE_LINE_SIZE,
1837                                    socket_id);
1838         if (!rxq->sw_ring) {
1839                 i40e_dev_rx_queue_release(rxq);
1840                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1841                 return -ENOMEM;
1842         }
1843
1844         i40e_reset_rx_queue(rxq);
1845         rxq->q_set = TRUE;
1846         dev->data->rx_queues[queue_idx] = rxq;
1847
1848         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1849
1850         if (!use_def_burst_func) {
1851 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1852                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1853                              "satisfied. Rx Burst Bulk Alloc function will be "
1854                              "used on port=%d, queue=%d.",
1855                              rxq->port_id, rxq->queue_id);
1856 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1857         } else {
1858                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1859                              "not satisfied, Scattered Rx is requested, "
1860                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1861                              "not enabled on port=%d, queue=%d.",
1862                              rxq->port_id, rxq->queue_id);
1863                 ad->rx_bulk_alloc_allowed = false;
1864         }
1865
1866         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1867                 if (!(vsi->enabled_tc & (1 << i)))
1868                         continue;
1869                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1870                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1871                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1872                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1873                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1874
1875                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1876                         rxq->dcb_tc = i;
1877         }
1878
1879         return 0;
1880 }
1881
1882 void
1883 i40e_dev_rx_queue_release(void *rxq)
1884 {
1885         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1886
1887         if (!q) {
1888                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1889                 return;
1890         }
1891
1892         i40e_rx_queue_release_mbufs(q);
1893         rte_free(q->sw_ring);
1894         rte_free(q);
1895 }
1896
1897 uint32_t
1898 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1899 {
1900 #define I40E_RXQ_SCAN_INTERVAL 4
1901         volatile union i40e_rx_desc *rxdp;
1902         struct i40e_rx_queue *rxq;
1903         uint16_t desc = 0;
1904
1905         rxq = dev->data->rx_queues[rx_queue_id];
1906         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1907         while ((desc < rxq->nb_rx_desc) &&
1908                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1909                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1910                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1911                 /**
1912                  * Check the DD bit of a rx descriptor of each 4 in a group,
1913                  * to avoid checking too frequently and downgrading performance
1914                  * too much.
1915                  */
1916                 desc += I40E_RXQ_SCAN_INTERVAL;
1917                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1918                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1919                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1920                                         desc - rxq->nb_rx_desc]);
1921         }
1922
1923         return desc;
1924 }
1925
1926 int
1927 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1928 {
1929         volatile union i40e_rx_desc *rxdp;
1930         struct i40e_rx_queue *rxq = rx_queue;
1931         uint16_t desc;
1932         int ret;
1933
1934         if (unlikely(offset >= rxq->nb_rx_desc)) {
1935                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1936                 return 0;
1937         }
1938
1939         desc = rxq->rx_tail + offset;
1940         if (desc >= rxq->nb_rx_desc)
1941                 desc -= rxq->nb_rx_desc;
1942
1943         rxdp = &(rxq->rx_ring[desc]);
1944
1945         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1946                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1947                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1948
1949         return ret;
1950 }
1951
1952 int
1953 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1954 {
1955         struct i40e_rx_queue *rxq = rx_queue;
1956         volatile uint64_t *status;
1957         uint64_t mask;
1958         uint32_t desc;
1959
1960         if (unlikely(offset >= rxq->nb_rx_desc))
1961                 return -EINVAL;
1962
1963         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1964                 return RTE_ETH_RX_DESC_UNAVAIL;
1965
1966         desc = rxq->rx_tail + offset;
1967         if (desc >= rxq->nb_rx_desc)
1968                 desc -= rxq->nb_rx_desc;
1969
1970         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1971         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1972                 << I40E_RXD_QW1_STATUS_SHIFT);
1973         if (*status & mask)
1974                 return RTE_ETH_RX_DESC_DONE;
1975
1976         return RTE_ETH_RX_DESC_AVAIL;
1977 }
1978
1979 int
1980 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1981 {
1982         struct i40e_tx_queue *txq = tx_queue;
1983         volatile uint64_t *status;
1984         uint64_t mask, expect;
1985         uint32_t desc;
1986
1987         if (unlikely(offset >= txq->nb_tx_desc))
1988                 return -EINVAL;
1989
1990         desc = txq->tx_tail + offset;
1991         /* go to next desc that has the RS bit */
1992         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1993                 txq->tx_rs_thresh;
1994         if (desc >= txq->nb_tx_desc) {
1995                 desc -= txq->nb_tx_desc;
1996                 if (desc >= txq->nb_tx_desc)
1997                         desc -= txq->nb_tx_desc;
1998         }
1999
2000         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2001         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2002         expect = rte_cpu_to_le_64(
2003                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2004         if ((*status & mask) == expect)
2005                 return RTE_ETH_TX_DESC_DONE;
2006
2007         return RTE_ETH_TX_DESC_FULL;
2008 }
2009
2010 int
2011 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2012                         uint16_t queue_idx,
2013                         uint16_t nb_desc,
2014                         unsigned int socket_id,
2015                         const struct rte_eth_txconf *tx_conf)
2016 {
2017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct i40e_vsi *vsi;
2019         struct i40e_pf *pf = NULL;
2020         struct i40e_vf *vf = NULL;
2021         struct i40e_tx_queue *txq;
2022         const struct rte_memzone *tz;
2023         uint32_t ring_size;
2024         uint16_t tx_rs_thresh, tx_free_thresh;
2025         uint16_t reg_idx, i, base, bsf, tc_mapping;
2026         int q_offset;
2027
2028         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2029                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2030                 vsi = &vf->vsi;
2031                 if (!vsi)
2032                         return -EINVAL;
2033                 reg_idx = queue_idx;
2034         } else {
2035                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2036                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2037                 if (!vsi)
2038                         return -EINVAL;
2039                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2040                 if (q_offset < 0)
2041                         return -EINVAL;
2042                 reg_idx = vsi->base_queue + q_offset;
2043         }
2044
2045         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2046             (nb_desc > I40E_MAX_RING_DESC) ||
2047             (nb_desc < I40E_MIN_RING_DESC)) {
2048                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2049                             "invalid", nb_desc);
2050                 return -EINVAL;
2051         }
2052
2053         /**
2054          * The following two parameters control the setting of the RS bit on
2055          * transmit descriptors. TX descriptors will have their RS bit set
2056          * after txq->tx_rs_thresh descriptors have been used. The TX
2057          * descriptor ring will be cleaned after txq->tx_free_thresh
2058          * descriptors are used or if the number of descriptors required to
2059          * transmit a packet is greater than the number of free TX descriptors.
2060          *
2061          * The following constraints must be satisfied:
2062          *  - tx_rs_thresh must be greater than 0.
2063          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2064          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2065          *  - tx_rs_thresh must be a divisor of the ring size.
2066          *  - tx_free_thresh must be greater than 0.
2067          *  - tx_free_thresh must be less than the size of the ring minus 3.
2068          *
2069          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2070          * race condition, hence the maximum threshold constraints. When set
2071          * to zero use default values.
2072          */
2073         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2074                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2075         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2076                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2077         if (tx_rs_thresh >= (nb_desc - 2)) {
2078                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2079                              "number of TX descriptors minus 2. "
2080                              "(tx_rs_thresh=%u port=%d queue=%d)",
2081                              (unsigned int)tx_rs_thresh,
2082                              (int)dev->data->port_id,
2083                              (int)queue_idx);
2084                 return I40E_ERR_PARAM;
2085         }
2086         if (tx_free_thresh >= (nb_desc - 3)) {
2087                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2088                              "number of TX descriptors minus 3. "
2089                              "(tx_free_thresh=%u port=%d queue=%d)",
2090                              (unsigned int)tx_free_thresh,
2091                              (int)dev->data->port_id,
2092                              (int)queue_idx);
2093                 return I40E_ERR_PARAM;
2094         }
2095         if (tx_rs_thresh > tx_free_thresh) {
2096                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2097                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2098                              " tx_rs_thresh=%u port=%d queue=%d)",
2099                              (unsigned int)tx_free_thresh,
2100                              (unsigned int)tx_rs_thresh,
2101                              (int)dev->data->port_id,
2102                              (int)queue_idx);
2103                 return I40E_ERR_PARAM;
2104         }
2105         if ((nb_desc % tx_rs_thresh) != 0) {
2106                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2107                              "number of TX descriptors. (tx_rs_thresh=%u"
2108                              " port=%d queue=%d)",
2109                              (unsigned int)tx_rs_thresh,
2110                              (int)dev->data->port_id,
2111                              (int)queue_idx);
2112                 return I40E_ERR_PARAM;
2113         }
2114         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2115                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2116                              "tx_rs_thresh is greater than 1. "
2117                              "(tx_rs_thresh=%u port=%d queue=%d)",
2118                              (unsigned int)tx_rs_thresh,
2119                              (int)dev->data->port_id,
2120                              (int)queue_idx);
2121                 return I40E_ERR_PARAM;
2122         }
2123
2124         /* Free memory if needed. */
2125         if (dev->data->tx_queues[queue_idx]) {
2126                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2127                 dev->data->tx_queues[queue_idx] = NULL;
2128         }
2129
2130         /* Allocate the TX queue data structure. */
2131         txq = rte_zmalloc_socket("i40e tx queue",
2132                                   sizeof(struct i40e_tx_queue),
2133                                   RTE_CACHE_LINE_SIZE,
2134                                   socket_id);
2135         if (!txq) {
2136                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2137                             "tx queue structure");
2138                 return -ENOMEM;
2139         }
2140
2141         /* Allocate TX hardware ring descriptors. */
2142         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2143         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2144         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2145                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2146         if (!tz) {
2147                 i40e_dev_tx_queue_release(txq);
2148                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2149                 return -ENOMEM;
2150         }
2151
2152         txq->nb_tx_desc = nb_desc;
2153         txq->tx_rs_thresh = tx_rs_thresh;
2154         txq->tx_free_thresh = tx_free_thresh;
2155         txq->pthresh = tx_conf->tx_thresh.pthresh;
2156         txq->hthresh = tx_conf->tx_thresh.hthresh;
2157         txq->wthresh = tx_conf->tx_thresh.wthresh;
2158         txq->queue_id = queue_idx;
2159         txq->reg_idx = reg_idx;
2160         txq->port_id = dev->data->port_id;
2161         txq->txq_flags = tx_conf->txq_flags;
2162         txq->vsi = vsi;
2163         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2164
2165         txq->tx_ring_phys_addr = tz->iova;
2166         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2167
2168         /* Allocate software ring */
2169         txq->sw_ring =
2170                 rte_zmalloc_socket("i40e tx sw ring",
2171                                    sizeof(struct i40e_tx_entry) * nb_desc,
2172                                    RTE_CACHE_LINE_SIZE,
2173                                    socket_id);
2174         if (!txq->sw_ring) {
2175                 i40e_dev_tx_queue_release(txq);
2176                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2177                 return -ENOMEM;
2178         }
2179
2180         i40e_reset_tx_queue(txq);
2181         txq->q_set = TRUE;
2182         dev->data->tx_queues[queue_idx] = txq;
2183
2184         /* Use a simple TX queue without offloads or multi segs if possible */
2185         i40e_set_tx_function_flag(dev, txq);
2186
2187         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2188                 if (!(vsi->enabled_tc & (1 << i)))
2189                         continue;
2190                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2191                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2192                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2193                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2194                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2195
2196                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2197                         txq->dcb_tc = i;
2198         }
2199
2200         return 0;
2201 }
2202
2203 void
2204 i40e_dev_tx_queue_release(void *txq)
2205 {
2206         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2207
2208         if (!q) {
2209                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2210                 return;
2211         }
2212
2213         i40e_tx_queue_release_mbufs(q);
2214         rte_free(q->sw_ring);
2215         rte_free(q);
2216 }
2217
2218 const struct rte_memzone *
2219 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2220 {
2221         const struct rte_memzone *mz;
2222
2223         mz = rte_memzone_lookup(name);
2224         if (mz)
2225                 return mz;
2226
2227         mz = rte_memzone_reserve_aligned(name, len,
2228                                          socket_id, 0, I40E_RING_BASE_ALIGN);
2229         return mz;
2230 }
2231
2232 void
2233 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2234 {
2235         uint16_t i;
2236
2237         /* SSE Vector driver has a different way of releasing mbufs. */
2238         if (rxq->rx_using_sse) {
2239                 i40e_rx_queue_release_mbufs_vec(rxq);
2240                 return;
2241         }
2242
2243         if (!rxq->sw_ring) {
2244                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2245                 return;
2246         }
2247
2248         for (i = 0; i < rxq->nb_rx_desc; i++) {
2249                 if (rxq->sw_ring[i].mbuf) {
2250                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2251                         rxq->sw_ring[i].mbuf = NULL;
2252                 }
2253         }
2254 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2255         if (rxq->rx_nb_avail == 0)
2256                 return;
2257         for (i = 0; i < rxq->rx_nb_avail; i++) {
2258                 struct rte_mbuf *mbuf;
2259
2260                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2261                 rte_pktmbuf_free_seg(mbuf);
2262         }
2263         rxq->rx_nb_avail = 0;
2264 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2265 }
2266
2267 void
2268 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2269 {
2270         unsigned i;
2271         uint16_t len;
2272
2273         if (!rxq) {
2274                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2275                 return;
2276         }
2277
2278 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2279         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2280                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2281         else
2282 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2283                 len = rxq->nb_rx_desc;
2284
2285         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2286                 ((volatile char *)rxq->rx_ring)[i] = 0;
2287
2288         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2289         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2290                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2291
2292 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2293         rxq->rx_nb_avail = 0;
2294         rxq->rx_next_avail = 0;
2295         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2296 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2297         rxq->rx_tail = 0;
2298         rxq->nb_rx_hold = 0;
2299         rxq->pkt_first_seg = NULL;
2300         rxq->pkt_last_seg = NULL;
2301
2302         rxq->rxrearm_start = 0;
2303         rxq->rxrearm_nb = 0;
2304 }
2305
2306 void
2307 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2308 {
2309         struct rte_eth_dev *dev;
2310         uint16_t i;
2311
2312         dev = &rte_eth_devices[txq->port_id];
2313
2314         if (!txq || !txq->sw_ring) {
2315                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2316                 return;
2317         }
2318
2319         /**
2320          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2321          *  so need to free remains more carefully.
2322          */
2323         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2324                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2325                 if (txq->tx_tail < i) {
2326                         for (; i < txq->nb_tx_desc; i++) {
2327                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2328                                 txq->sw_ring[i].mbuf = NULL;
2329                         }
2330                         i = 0;
2331                 }
2332                 for (; i < txq->tx_tail; i++) {
2333                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2334                         txq->sw_ring[i].mbuf = NULL;
2335                 }
2336         } else {
2337                 for (i = 0; i < txq->nb_tx_desc; i++) {
2338                         if (txq->sw_ring[i].mbuf) {
2339                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2340                                 txq->sw_ring[i].mbuf = NULL;
2341                         }
2342                 }
2343         }
2344 }
2345
2346 void
2347 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2348 {
2349         struct i40e_tx_entry *txe;
2350         uint16_t i, prev, size;
2351
2352         if (!txq) {
2353                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2354                 return;
2355         }
2356
2357         txe = txq->sw_ring;
2358         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2359         for (i = 0; i < size; i++)
2360                 ((volatile char *)txq->tx_ring)[i] = 0;
2361
2362         prev = (uint16_t)(txq->nb_tx_desc - 1);
2363         for (i = 0; i < txq->nb_tx_desc; i++) {
2364                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2365
2366                 txd->cmd_type_offset_bsz =
2367                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2368                 txe[i].mbuf =  NULL;
2369                 txe[i].last_id = i;
2370                 txe[prev].next_id = i;
2371                 prev = i;
2372         }
2373
2374         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2375         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2376
2377         txq->tx_tail = 0;
2378         txq->nb_tx_used = 0;
2379
2380         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2381         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2382 }
2383
2384 /* Init the TX queue in hardware */
2385 int
2386 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2387 {
2388         enum i40e_status_code err = I40E_SUCCESS;
2389         struct i40e_vsi *vsi = txq->vsi;
2390         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2391         uint16_t pf_q = txq->reg_idx;
2392         struct i40e_hmc_obj_txq tx_ctx;
2393         uint32_t qtx_ctl;
2394
2395         /* clear the context structure first */
2396         memset(&tx_ctx, 0, sizeof(tx_ctx));
2397         tx_ctx.new_context = 1;
2398         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2399         tx_ctx.qlen = txq->nb_tx_desc;
2400
2401 #ifdef RTE_LIBRTE_IEEE1588
2402         tx_ctx.timesync_ena = 1;
2403 #endif
2404         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2405         if (vsi->type == I40E_VSI_FDIR)
2406                 tx_ctx.fd_ena = TRUE;
2407
2408         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2409         if (err != I40E_SUCCESS) {
2410                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2411                 return err;
2412         }
2413
2414         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2415         if (err != I40E_SUCCESS) {
2416                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2417                 return err;
2418         }
2419
2420         /* Now associate this queue with this PCI function */
2421         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2422         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2423                                         I40E_QTX_CTL_PF_INDX_MASK);
2424         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2425         I40E_WRITE_FLUSH(hw);
2426
2427         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2428
2429         return err;
2430 }
2431
2432 int
2433 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2434 {
2435         struct i40e_rx_entry *rxe = rxq->sw_ring;
2436         uint64_t dma_addr;
2437         uint16_t i;
2438
2439         for (i = 0; i < rxq->nb_rx_desc; i++) {
2440                 volatile union i40e_rx_desc *rxd;
2441                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2442
2443                 if (unlikely(!mbuf)) {
2444                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2445                         return -ENOMEM;
2446                 }
2447
2448                 rte_mbuf_refcnt_set(mbuf, 1);
2449                 mbuf->next = NULL;
2450                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2451                 mbuf->nb_segs = 1;
2452                 mbuf->port = rxq->port_id;
2453
2454                 dma_addr =
2455                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2456
2457                 rxd = &rxq->rx_ring[i];
2458                 rxd->read.pkt_addr = dma_addr;
2459                 rxd->read.hdr_addr = 0;
2460 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2461                 rxd->read.rsvd1 = 0;
2462                 rxd->read.rsvd2 = 0;
2463 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2464
2465                 rxe[i].mbuf = mbuf;
2466         }
2467
2468         return 0;
2469 }
2470
2471 /*
2472  * Calculate the buffer length, and check the jumbo frame
2473  * and maximum packet length.
2474  */
2475 static int
2476 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2477 {
2478         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2479         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2480         struct rte_eth_dev_data *data = pf->dev_data;
2481         uint16_t buf_size, len;
2482
2483         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2484                 RTE_PKTMBUF_HEADROOM);
2485
2486         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2487                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2488         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2489                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2490                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2491                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2492                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2493                 rxq->hs_mode = i40e_header_split_enabled;
2494                 break;
2495         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2496         default:
2497                 rxq->rx_hdr_len = 0;
2498                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2499                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2500                 rxq->hs_mode = i40e_header_split_none;
2501                 break;
2502         }
2503
2504         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2505         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2506         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2507                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2508                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2509                         PMD_DRV_LOG(ERR, "maximum packet length must "
2510                                     "be larger than %u and smaller than %u,"
2511                                     "as jumbo frame is enabled",
2512                                     (uint32_t)ETHER_MAX_LEN,
2513                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2514                         return I40E_ERR_CONFIG;
2515                 }
2516         } else {
2517                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2518                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2519                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2520                                     "larger than %u and smaller than %u, "
2521                                     "as jumbo frame is disabled",
2522                                     (uint32_t)ETHER_MIN_LEN,
2523                                     (uint32_t)ETHER_MAX_LEN);
2524                         return I40E_ERR_CONFIG;
2525                 }
2526         }
2527
2528         return 0;
2529 }
2530
2531 /* Init the RX queue in hardware */
2532 int
2533 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2534 {
2535         int err = I40E_SUCCESS;
2536         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2537         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2538         uint16_t pf_q = rxq->reg_idx;
2539         uint16_t buf_size;
2540         struct i40e_hmc_obj_rxq rx_ctx;
2541
2542         err = i40e_rx_queue_config(rxq);
2543         if (err < 0) {
2544                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2545                 return err;
2546         }
2547
2548         /* Clear the context structure first */
2549         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2550         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2551         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2552
2553         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2554         rx_ctx.qlen = rxq->nb_rx_desc;
2555 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2556         rx_ctx.dsize = 1;
2557 #endif
2558         rx_ctx.dtype = rxq->hs_mode;
2559         if (rxq->hs_mode)
2560                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2561         else
2562                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2563         rx_ctx.rxmax = rxq->max_pkt_len;
2564         rx_ctx.tphrdesc_ena = 1;
2565         rx_ctx.tphwdesc_ena = 1;
2566         rx_ctx.tphdata_ena = 1;
2567         rx_ctx.tphhead_ena = 1;
2568         rx_ctx.lrxqthresh = 2;
2569         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2570         rx_ctx.l2tsel = 1;
2571         /* showiv indicates if inner VLAN is stripped inside of tunnel
2572          * packet. When set it to 1, vlan information is stripped from
2573          * the inner header, but the hardware does not put it in the
2574          * descriptor. So set it zero by default.
2575          */
2576         rx_ctx.showiv = 0;
2577         rx_ctx.prefena = 1;
2578
2579         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2580         if (err != I40E_SUCCESS) {
2581                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2582                 return err;
2583         }
2584         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2585         if (err != I40E_SUCCESS) {
2586                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2587                 return err;
2588         }
2589
2590         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2591
2592         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2593                 RTE_PKTMBUF_HEADROOM);
2594
2595         /* Check if scattered RX needs to be used. */
2596         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2597                 dev_data->scattered_rx = 1;
2598         }
2599
2600         /* Init the RX tail regieter. */
2601         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2602
2603         return 0;
2604 }
2605
2606 void
2607 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2608 {
2609         uint16_t i;
2610
2611         PMD_INIT_FUNC_TRACE();
2612
2613         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2614                 if (!dev->data->tx_queues[i])
2615                         continue;
2616                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2617                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2618         }
2619
2620         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2621                 if (!dev->data->rx_queues[i])
2622                         continue;
2623                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2624                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2625         }
2626 }
2627
2628 void
2629 i40e_dev_free_queues(struct rte_eth_dev *dev)
2630 {
2631         uint16_t i;
2632
2633         PMD_INIT_FUNC_TRACE();
2634
2635         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2636                 if (!dev->data->rx_queues[i])
2637                         continue;
2638                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2639                 dev->data->rx_queues[i] = NULL;
2640         }
2641         dev->data->nb_rx_queues = 0;
2642
2643         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2644                 if (!dev->data->tx_queues[i])
2645                         continue;
2646                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2647                 dev->data->tx_queues[i] = NULL;
2648         }
2649         dev->data->nb_tx_queues = 0;
2650 }
2651
2652 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2653 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2654
2655 enum i40e_status_code
2656 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2657 {
2658         struct i40e_tx_queue *txq;
2659         const struct rte_memzone *tz = NULL;
2660         uint32_t ring_size;
2661         struct rte_eth_dev *dev;
2662
2663         if (!pf) {
2664                 PMD_DRV_LOG(ERR, "PF is not available");
2665                 return I40E_ERR_BAD_PTR;
2666         }
2667
2668         dev = pf->adapter->eth_dev;
2669
2670         /* Allocate the TX queue data structure. */
2671         txq = rte_zmalloc_socket("i40e fdir tx queue",
2672                                   sizeof(struct i40e_tx_queue),
2673                                   RTE_CACHE_LINE_SIZE,
2674                                   SOCKET_ID_ANY);
2675         if (!txq) {
2676                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2677                                         "tx queue structure.");
2678                 return I40E_ERR_NO_MEMORY;
2679         }
2680
2681         /* Allocate TX hardware ring descriptors. */
2682         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2683         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2684
2685         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2686                                       I40E_FDIR_QUEUE_ID, ring_size,
2687                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2688         if (!tz) {
2689                 i40e_dev_tx_queue_release(txq);
2690                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2691                 return I40E_ERR_NO_MEMORY;
2692         }
2693
2694         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2695         txq->queue_id = I40E_FDIR_QUEUE_ID;
2696         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2697         txq->vsi = pf->fdir.fdir_vsi;
2698
2699         txq->tx_ring_phys_addr = tz->iova;
2700         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2701         /*
2702          * don't need to allocate software ring and reset for the fdir
2703          * program queue just set the queue has been configured.
2704          */
2705         txq->q_set = TRUE;
2706         pf->fdir.txq = txq;
2707
2708         return I40E_SUCCESS;
2709 }
2710
2711 enum i40e_status_code
2712 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2713 {
2714         struct i40e_rx_queue *rxq;
2715         const struct rte_memzone *rz = NULL;
2716         uint32_t ring_size;
2717         struct rte_eth_dev *dev;
2718
2719         if (!pf) {
2720                 PMD_DRV_LOG(ERR, "PF is not available");
2721                 return I40E_ERR_BAD_PTR;
2722         }
2723
2724         dev = pf->adapter->eth_dev;
2725
2726         /* Allocate the RX queue data structure. */
2727         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2728                                   sizeof(struct i40e_rx_queue),
2729                                   RTE_CACHE_LINE_SIZE,
2730                                   SOCKET_ID_ANY);
2731         if (!rxq) {
2732                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2733                                         "rx queue structure.");
2734                 return I40E_ERR_NO_MEMORY;
2735         }
2736
2737         /* Allocate RX hardware ring descriptors. */
2738         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2739         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2740
2741         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2742                                       I40E_FDIR_QUEUE_ID, ring_size,
2743                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2744         if (!rz) {
2745                 i40e_dev_rx_queue_release(rxq);
2746                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2747                 return I40E_ERR_NO_MEMORY;
2748         }
2749
2750         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2751         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2752         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2753         rxq->vsi = pf->fdir.fdir_vsi;
2754
2755         rxq->rx_ring_phys_addr = rz->iova;
2756         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2757         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2758
2759         /*
2760          * Don't need to allocate software ring and reset for the fdir
2761          * rx queue, just set the queue has been configured.
2762          */
2763         rxq->q_set = TRUE;
2764         pf->fdir.rxq = rxq;
2765
2766         return I40E_SUCCESS;
2767 }
2768
2769 void
2770 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2771         struct rte_eth_rxq_info *qinfo)
2772 {
2773         struct i40e_rx_queue *rxq;
2774
2775         rxq = dev->data->rx_queues[queue_id];
2776
2777         qinfo->mp = rxq->mp;
2778         qinfo->scattered_rx = dev->data->scattered_rx;
2779         qinfo->nb_desc = rxq->nb_rx_desc;
2780
2781         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2782         qinfo->conf.rx_drop_en = rxq->drop_en;
2783         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2784 }
2785
2786 void
2787 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2788         struct rte_eth_txq_info *qinfo)
2789 {
2790         struct i40e_tx_queue *txq;
2791
2792         txq = dev->data->tx_queues[queue_id];
2793
2794         qinfo->nb_desc = txq->nb_tx_desc;
2795
2796         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2797         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2798         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2799
2800         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2801         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2802         qinfo->conf.txq_flags = txq->txq_flags;
2803         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2804 }
2805
2806 void __attribute__((cold))
2807 i40e_set_rx_function(struct rte_eth_dev *dev)
2808 {
2809         struct i40e_adapter *ad =
2810                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2811         uint16_t rx_using_sse, i;
2812         /* In order to allow Vector Rx there are a few configuration
2813          * conditions to be met and Rx Bulk Allocation should be allowed.
2814          */
2815         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2816                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2817                     !ad->rx_bulk_alloc_allowed) {
2818                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2819                                      " Vector Rx preconditions",
2820                                      dev->data->port_id);
2821
2822                         ad->rx_vec_allowed = false;
2823                 }
2824                 if (ad->rx_vec_allowed) {
2825                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2826                                 struct i40e_rx_queue *rxq =
2827                                         dev->data->rx_queues[i];
2828
2829                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2830                                         ad->rx_vec_allowed = false;
2831                                         break;
2832                                 }
2833                         }
2834                 }
2835         }
2836
2837         if (dev->data->scattered_rx) {
2838                 /* Set the non-LRO scattered callback: there are Vector and
2839                  * single allocation versions.
2840                  */
2841                 if (ad->rx_vec_allowed) {
2842                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2843                                             "callback (port=%d).",
2844                                      dev->data->port_id);
2845
2846                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2847                 } else {
2848                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2849                                            "allocation callback (port=%d).",
2850                                      dev->data->port_id);
2851                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2852                 }
2853         /* If parameters allow we are going to choose between the following
2854          * callbacks:
2855          *    - Vector
2856          *    - Bulk Allocation
2857          *    - Single buffer allocation (the simplest one)
2858          */
2859         } else if (ad->rx_vec_allowed) {
2860                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2861                                     "burst size no less than %d (port=%d).",
2862                              RTE_I40E_DESCS_PER_LOOP,
2863                              dev->data->port_id);
2864
2865                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2866         } else if (ad->rx_bulk_alloc_allowed) {
2867                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2868                                     "satisfied. Rx Burst Bulk Alloc function "
2869                                     "will be used on port=%d.",
2870                              dev->data->port_id);
2871
2872                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2873         } else {
2874                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2875                                     "satisfied, or Scattered Rx is requested "
2876                                     "(port=%d).",
2877                              dev->data->port_id);
2878
2879                 dev->rx_pkt_burst = i40e_recv_pkts;
2880         }
2881
2882         /* Propagate information about RX function choice through all queues. */
2883         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2884                 rx_using_sse =
2885                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2886                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2887
2888                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2889                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2890
2891                         if (rxq)
2892                                 rxq->rx_using_sse = rx_using_sse;
2893                 }
2894         }
2895 }
2896
2897 void __attribute__((cold))
2898 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2899 {
2900         struct i40e_adapter *ad =
2901                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2902
2903         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2904         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2905                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2906                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2907                         PMD_INIT_LOG(DEBUG, "Vector tx"
2908                                      " can be enabled on this txq.");
2909
2910                 } else {
2911                         ad->tx_vec_allowed = false;
2912                 }
2913         } else {
2914                 ad->tx_simple_allowed = false;
2915         }
2916 }
2917
2918 void __attribute__((cold))
2919 i40e_set_tx_function(struct rte_eth_dev *dev)
2920 {
2921         struct i40e_adapter *ad =
2922                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2923         int i;
2924
2925         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2926                 if (ad->tx_vec_allowed) {
2927                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2928                                 struct i40e_tx_queue *txq =
2929                                         dev->data->tx_queues[i];
2930
2931                                 if (txq && i40e_txq_vec_setup(txq)) {
2932                                         ad->tx_vec_allowed = false;
2933                                         break;
2934                                 }
2935                         }
2936                 }
2937         }
2938
2939         if (ad->tx_simple_allowed) {
2940                 if (ad->tx_vec_allowed) {
2941                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2942                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2943                 } else {
2944                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2945                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2946                 }
2947                 dev->tx_pkt_prepare = NULL;
2948         } else {
2949                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2950                 dev->tx_pkt_burst = i40e_xmit_pkts;
2951                 dev->tx_pkt_prepare = i40e_prep_pkts;
2952         }
2953 }
2954
2955 void __attribute__((cold))
2956 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
2957 {
2958         struct i40e_adapter *ad =
2959                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2960         int i;
2961
2962         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
2963                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
2964 }
2965
2966 void __attribute__((cold))
2967 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
2968 {
2969         struct i40e_adapter *ad =
2970                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         int i;
2973
2974         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
2975                 ad->pctypes_tbl[i] = 0ULL;
2976         ad->flow_types_mask = 0ULL;
2977         ad->pctypes_mask = 0ULL;
2978
2979         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
2980                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
2981         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
2982                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
2983         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
2984                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
2985         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
2986                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
2987         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
2988                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
2989         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
2990                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
2991         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
2992                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
2993         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
2994                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
2995         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
2996                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
2997         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
2998                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
2999         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3000                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3001
3002         if (hw->mac.type == I40E_MAC_X722) {
3003                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3004                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3005                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3006                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3007                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3008                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3009                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3010                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3011                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3012                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3013                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3014                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3015         }
3016
3017         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3018                 if (ad->pctypes_tbl[i])
3019                         ad->flow_types_mask |= (1ULL << i);
3020                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3021         }
3022 }
3023
3024 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3025 int __attribute__((weak))
3026 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3027 {
3028         return -1;
3029 }
3030
3031 uint16_t __attribute__((weak))
3032 i40e_recv_pkts_vec(
3033         void __rte_unused *rx_queue,
3034         struct rte_mbuf __rte_unused **rx_pkts,
3035         uint16_t __rte_unused nb_pkts)
3036 {
3037         return 0;
3038 }
3039
3040 uint16_t __attribute__((weak))
3041 i40e_recv_scattered_pkts_vec(
3042         void __rte_unused *rx_queue,
3043         struct rte_mbuf __rte_unused **rx_pkts,
3044         uint16_t __rte_unused nb_pkts)
3045 {
3046         return 0;
3047 }
3048
3049 int __attribute__((weak))
3050 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3051 {
3052         return -1;
3053 }
3054
3055 int __attribute__((weak))
3056 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3057 {
3058         return -1;
3059 }
3060
3061 void __attribute__((weak))
3062 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3063 {
3064         return;
3065 }
3066
3067 uint16_t __attribute__((weak))
3068 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3069                           struct rte_mbuf __rte_unused **tx_pkts,
3070                           uint16_t __rte_unused nb_pkts)
3071 {
3072         return 0;
3073 }