drivers/net/i40e/i40e_rxtx_vec_sse.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <stdint.h>
   6 #include <rte_ethdev_driver.h>
   7 #include <rte_malloc.h>
   8
   9 #include "base/i40e_prototype.h"
  10 #include "base/i40e_type.h"
  11 #include "i40e_ethdev.h"
  12 #include "i40e_rxtx.h"
  13 #include "i40e_rxtx_vec_common.h"
  14
  15 #include <tmmintrin.h>
  16
  17 #ifndef __INTEL_COMPILER
  18 #pragma GCC diagnostic ignored "-Wcast-qual"
  19 #endif
  20
  21 static inline void
  22 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
  23 {
  24         int i;
  25         uint16_t rx_id;
  26         volatile union i40e_rx_desc *rxdp;
  27         struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  28         struct rte_mbuf *mb0, *mb1;
  29         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  30                         RTE_PKTMBUF_HEADROOM);
  31         __m128i dma_addr0, dma_addr1;
  32
  33         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  34
  35         /* Pull 'n' more MBUFs into the software ring */
  36         if (rte_mempool_get_bulk(rxq->mp,
  37                                  (void *)rxep,
  38                                  RTE_I40E_RXQ_REARM_THRESH) < 0) {
  39                 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
  40                     rxq->nb_rx_desc) {
  41                         dma_addr0 = _mm_setzero_si128();
  42                         for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
  43                                 rxep[i].mbuf = &rxq->fake_mbuf;
  44                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  45                                                 dma_addr0);
  46                         }
  47                 }
  48                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  49                         RTE_I40E_RXQ_REARM_THRESH;
  50                 return;
  51         }
  52
  53         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  54         for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  55                 __m128i vaddr0, vaddr1;
  56
  57                 mb0 = rxep[0].mbuf;
  58                 mb1 = rxep[1].mbuf;
  59
  60                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  61                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  62                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  63                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  64                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  65
  66                 /* convert pa to dma_addr hdr/data */
  67                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  68                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  69
  70                 /* add headroom to pa values */
  71                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  72                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  73
  74                 /* flush desc with pa dma_addr */
  75                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  76                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  77         }
  78
  79         rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
  80         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
  81                 rxq->rxrearm_start = 0;
  82
  83         rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
  84
  85         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
  86                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
  87
  88         /* Update the tail pointer on the NIC */
  89         I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
  90 }
  91
  92 static inline void
  93 desc_to_olflags_v(struct i40e_rx_queue *rxq, __m128i descs[4],
  94         struct rte_mbuf **rx_pkts)
  95 {
  96         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
  97         __m128i rearm0, rearm1, rearm2, rearm3;
  98
  99         __m128i vlan0, vlan1, rss, l3_l4e;
 100
 101         /* mask everything except RSS, flow director and VLAN flags
 102          * bit2 is for VLAN tag, bit11 for flow director indication
 103          * bit13:12 for RSS indication.
 104          */
 105         const __m128i rss_vlan_msk = _mm_set_epi32(
 106                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
 107
 108         const __m128i cksum_mask = _mm_set_epi32(
 109                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 110                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 111                         PKT_RX_EIP_CKSUM_BAD,
 112                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 113                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 114                         PKT_RX_EIP_CKSUM_BAD,
 115                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 116                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 117                         PKT_RX_EIP_CKSUM_BAD,
 118                         PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 119                         PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 120                         PKT_RX_EIP_CKSUM_BAD);
 121
 122         /* map rss and vlan type to rss hash and vlan flag */
 123         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 124                         0, 0, 0, 0,
 125                         0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 126                         0, 0, 0, 0);
 127
 128         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 129                         0, 0, 0, 0,
 130                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 131                         0, 0, PKT_RX_FDIR, 0);
 132
 133         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 134                         /* shift right 1 bit to make sure it not exceed 255 */
 135                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 136                          PKT_RX_IP_CKSUM_BAD) >> 1,
 137                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 138                          PKT_RX_L4_CKSUM_BAD) >> 1,
 139                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 140                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 141                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 142                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 143                         PKT_RX_IP_CKSUM_BAD >> 1,
 144                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 145
 146         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
 147         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
 148         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
 149
 150         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 151         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 152
 153         rss = _mm_srli_epi32(vlan1, 11);
 154         rss = _mm_shuffle_epi8(rss_flags, rss);
 155
 156         l3_l4e = _mm_srli_epi32(vlan1, 22);
 157         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
 158         /* then we shift left 1 bit */
 159         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
 160         /* we need to mask out the reduntant bits */
 161         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
 162
 163         vlan0 = _mm_or_si128(vlan0, rss);
 164         vlan0 = _mm_or_si128(vlan0, l3_l4e);
 165
 166         /*
 167          * At this point, we have the 4 sets of flags in the low 16-bits
 168          * of each 32-bit value in vlan0.
 169          * We want to extract these, and merge them with the mbuf init data
 170          * so we can do a single 16-byte write to the mbuf to set the flags
 171          * and all the other initialization fields. Extracting the
 172          * appropriate flags means that we have to do a shift and blend for
 173          * each mbuf before we do the write.
 174          */
 175         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
 176         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
 177         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
 178         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
 179
 180         /* write the rearm data and the olflags in one write */
 181         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 182                         offsetof(struct rte_mbuf, rearm_data) + 8);
 183         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 184                         RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 185         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 186         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 187         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 188         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 189 }
 190
 191 #define PKTLEN_SHIFT     10
 192
 193 static inline void
 194 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
 195                 uint32_t *ptype_tbl)
 196 {
 197         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 198         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 199
 200         ptype0 = _mm_srli_epi64(ptype0, 30);
 201         ptype1 = _mm_srli_epi64(ptype1, 30);
 202
 203         rx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 0)];
 204         rx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 8)];
 205         rx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 0)];
 206         rx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 8)];
 207 }
 208
 209  /*
 210  * Notice:
 211  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 212  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 213  *   numbers of DD bits
 214  */
 215 static inline uint16_t
 216 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 217                    uint16_t nb_pkts, uint8_t *split_packet)
 218 {
 219         volatile union i40e_rx_desc *rxdp;
 220         struct i40e_rx_entry *sw_ring;
 221         uint16_t nb_pkts_recd;
 222         int pos;
 223         uint64_t var;
 224         __m128i shuf_msk;
 225         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 226
 227         __m128i crc_adjust = _mm_set_epi16(
 228                                 0, 0, 0,    /* ignore non-length fields */
 229                                 -rxq->crc_len, /* sub crc on data_len */
 230                                 0,          /* ignore high-16bits of pkt_len */
 231                                 -rxq->crc_len, /* sub crc on pkt_len */
 232                                 0, 0            /* ignore pkt_type field */
 233                         );
 234         /*
 235          * compile-time check the above crc_adjust layout is correct.
 236          * NOTE: the first field (lowest address) is given last in set_epi16
 237          * call above.
 238          */
 239         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 240                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 241         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 242                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 243         __m128i dd_check, eop_check;
 244
 245         /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
 246         nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
 247
 248         /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
 249         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
 250
 251         /* Just the act of getting into the function from the application is
 252          * going to cost about 7 cycles
 253          */
 254         rxdp = rxq->rx_ring + rxq->rx_tail;
 255
 256         rte_prefetch0(rxdp);
 257
 258         /* See if we need to rearm the RX queue - gives the prefetch a bit
 259          * of time to act
 260          */
 261         if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
 262                 i40e_rxq_rearm(rxq);
 263
 264         /* Before we start moving massive data around, check to see if
 265          * there is actually a packet available
 266          */
 267         if (!(rxdp->wb.qword1.status_error_len &
 268                         rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 269                 return 0;
 270
 271         /* 4 packets DD mask */
 272         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 273
 274         /* 4 packets EOP mask */
 275         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 276
 277         /* mask to shuffle from desc. to mbuf */
 278         shuf_msk = _mm_set_epi8(
 279                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 280                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 281                 15, 14,      /* octet 15~14, 16 bits data_len */
 282                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 283                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 284                 0xFF, 0xFF,  /* pkt_type set as unknown */
 285                 0xFF, 0xFF  /*pkt_type set as unknown */
 286                 );
 287         /*
 288          * Compile-time verify the shuffle mask
 289          * NOTE: some field positions already verified above, but duplicated
 290          * here for completeness in case of future modifications.
 291          */
 292         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 293                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 294         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 295                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 296         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 297                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 298         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 299                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 300
 301         /* Cache is empty -> need to scan the buffer rings, but first move
 302          * the next 'n' mbufs into the cache
 303          */
 304         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 305
 306         /* A. load 4 packet in one loop
 307          * [A*. mask out 4 unused dirty field in desc]
 308          * B. copy 4 mbuf point from swring to rx_pkts
 309          * C. calc the number of DD bits among the 4 packets
 310          * [C*. extract the end-of-packet bit, if requested]
 311          * D. fill info. from desc to mbuf
 312          */
 313
 314         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 315                         pos += RTE_I40E_DESCS_PER_LOOP,
 316                         rxdp += RTE_I40E_DESCS_PER_LOOP) {
 317                 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
 318                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 319                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 320                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 321                 __m128i mbp1;
 322 #if defined(RTE_ARCH_X86_64)
 323                 __m128i mbp2;
 324 #endif
 325
 326                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 327                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 328                 /* Read desc statuses backwards to avoid race condition */
 329                 /* A.1 load 4 pkts desc */
 330                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 331                 rte_compiler_barrier();
 332
 333                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 334                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 335
 336 #if defined(RTE_ARCH_X86_64)
 337                 /* B.1 load 2 64 bit mbuf points */
 338                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 339 #endif
 340
 341                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 342                 rte_compiler_barrier();
 343                 /* B.1 load 2 mbuf point */
 344                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 345                 rte_compiler_barrier();
 346                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 347
 348 #if defined(RTE_ARCH_X86_64)
 349                 /* B.2 copy 2 mbuf point into rx_pkts  */
 350                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 351 #endif
 352
 353                 if (split_packet) {
 354                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 355                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 356                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 357                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 358                 }
 359
 360                 /* avoid compiler reorder optimization */
 361                 rte_compiler_barrier();
 362
 363                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 364                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 365                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 366
 367                 /* merge the now-aligned packet length fields back in */
 368                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 369                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 370
 371                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 372                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 373                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 374
 375                 /* C.1 4=>2 filter staterr info only */
 376                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 377                 /* C.1 4=>2 filter staterr info only */
 378                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 379
 380                 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 381
 382                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 383                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 384                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 385
 386                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 387                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 388                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 389
 390                 /* merge the now-aligned packet length fields back in */
 391                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 392                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 393
 394                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 395                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 396                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 397
 398                 /* C.2 get 4 pkts staterr value  */
 399                 zero = _mm_xor_si128(dd_check, dd_check);
 400                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 401
 402                 /* D.3 copy final 3,4 data to rx_pkts */
 403                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 404                                  pkt_mb4);
 405                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 406                                  pkt_mb3);
 407
 408                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 409                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 410                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 411
 412                 /* C* extract and record EOP bit */
 413                 if (split_packet) {
 414                         __m128i eop_shuf_mask = _mm_set_epi8(
 415                                         0xFF, 0xFF, 0xFF, 0xFF,
 416                                         0xFF, 0xFF, 0xFF, 0xFF,
 417                                         0xFF, 0xFF, 0xFF, 0xFF,
 418                                         0x04, 0x0C, 0x00, 0x08
 419                                         );
 420
 421                         /* and with mask to extract bits, flipping 1-0 */
 422                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 423                         /* the staterr values are not in order, as the count
 424                          * count of dd bits doesn't care. However, for end of
 425                          * packet tracking, we do care, so shuffle. This also
 426                          * compresses the 32-bit values to 8-bit
 427                          */
 428                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 429                         /* store the resulting 32-bit value */
 430                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 431                         split_packet += RTE_I40E_DESCS_PER_LOOP;
 432                 }
 433
 434                 /* C.3 calc available number of desc */
 435                 staterr = _mm_and_si128(staterr, dd_check);
 436                 staterr = _mm_packs_epi32(staterr, zero);
 437
 438                 /* D.3 copy final 1,2 data to rx_pkts */
 439                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 440                                  pkt_mb2);
 441                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 442                                  pkt_mb1);
 443                 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 444                 /* C.4 calc avaialbe number of desc */
 445                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 446                 nb_pkts_recd += var;
 447                 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
 448                         break;
 449         }
 450
 451         /* Update our internal tail pointer */
 452         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 453         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 454         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 455
 456         return nb_pkts_recd;
 457 }
 458
 459  /*
 460  * Notice:
 461  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 462  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 463  *   numbers of DD bits
 464  */
 465 uint16_t
 466 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 467                    uint16_t nb_pkts)
 468 {
 469         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 470 }
 471
 472  /* vPMD receive routine that reassembles scattered packets
 473  * Notice:
 474  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 475  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 476  *   numbers of DD bits
 477  */
 478 uint16_t
 479 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 480                              uint16_t nb_pkts)
 481 {
 482
 483         struct i40e_rx_queue *rxq = rx_queue;
 484         uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
 485
 486         /* get some new buffers */
 487         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 488                         split_flags);
 489         if (nb_bufs == 0)
 490                 return 0;
 491
 492         /* happy day case, full burst + no packets to be joined */
 493         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 494
 495         if (rxq->pkt_first_seg == NULL &&
 496                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 497                         split_fl64[2] == 0 && split_fl64[3] == 0)
 498                 return nb_bufs;
 499
 500         /* reassemble any packets that need reassembly*/
 501         unsigned i = 0;
 502
 503         if (rxq->pkt_first_seg == NULL) {
 504                 /* find the first split flag, and only reassemble then*/
 505                 while (i < nb_bufs && !split_flags[i])
 506                         i++;
 507                 if (i == nb_bufs)
 508                         return nb_bufs;
 509         }
 510         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 511                 &split_flags[i]);
 512 }
 513
 514 static inline void
 515 vtx1(volatile struct i40e_tx_desc *txdp,
 516                 struct rte_mbuf *pkt, uint64_t flags)
 517 {
 518         uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
 519                         ((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
 520                         ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
 521
 522         __m128i descriptor = _mm_set_epi64x(high_qw,
 523                                 pkt->buf_iova + pkt->data_off);
 524         _mm_store_si128((__m128i *)txdp, descriptor);
 525 }
 526
 527 static inline void
 528 vtx(volatile struct i40e_tx_desc *txdp,
 529                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 530 {
 531         int i;
 532
 533         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 534                 vtx1(txdp, *pkt, flags);
 535 }
 536
 537 uint16_t
 538 i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 539                           uint16_t nb_pkts)
 540 {
 541         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
 542         volatile struct i40e_tx_desc *txdp;
 543         struct i40e_tx_entry *txep;
 544         uint16_t n, nb_commit, tx_id;
 545         uint64_t flags = I40E_TD_CMD;
 546         uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
 547         int i;
 548
 549         /* cross rx_thresh boundary is not allowed */
 550         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 551
 552         if (txq->nb_tx_free < txq->tx_free_thresh)
 553                 i40e_tx_free_bufs(txq);
 554
 555         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 556         if (unlikely(nb_pkts == 0))
 557                 return 0;
 558
 559         tx_id = txq->tx_tail;
 560         txdp = &txq->tx_ring[tx_id];
 561         txep = &txq->sw_ring[tx_id];
 562
 563         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 564
 565         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 566         if (nb_commit >= n) {
 567                 tx_backlog_entry(txep, tx_pkts, n);
 568
 569                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 570                         vtx1(txdp, *tx_pkts, flags);
 571
 572                 vtx1(txdp, *tx_pkts++, rs);
 573
 574                 nb_commit = (uint16_t)(nb_commit - n);
 575
 576                 tx_id = 0;
 577                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 578
 579                 /* avoid reach the end of ring */
 580                 txdp = &txq->tx_ring[tx_id];
 581                 txep = &txq->sw_ring[tx_id];
 582         }
 583
 584         tx_backlog_entry(txep, tx_pkts, nb_commit);
 585
 586         vtx(txdp, tx_pkts, nb_commit, flags);
 587
 588         tx_id = (uint16_t)(tx_id + nb_commit);
 589         if (tx_id > txq->tx_next_rs) {
 590                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 591                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
 592                                                 I40E_TXD_QW1_CMD_SHIFT);
 593                 txq->tx_next_rs =
 594                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 595         }
 596
 597         txq->tx_tail = tx_id;
 598
 599         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 600
 601         return nb_pkts;
 602 }
 603
 604 void __attribute__((cold))
 605 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
 606 {
 607         _i40e_rx_queue_release_mbufs_vec(rxq);
 608 }
 609
 610 int __attribute__((cold))
 611 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
 612 {
 613         return i40e_rxq_vec_setup_default(rxq);
 614 }
 615
 616 int __attribute__((cold))
 617 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
 618 {
 619         return 0;
 620 }
 621
 622 int __attribute__((cold))
 623 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 624 {
 625         return i40e_rx_vec_dev_conf_condition_check_default(dev);
 626 }