drivers/net/i40e/i40e_rxtx_vec_sse.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdint.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_malloc.h>
  37
  38 #include "base/i40e_prototype.h"
  39 #include "base/i40e_type.h"
  40 #include "i40e_ethdev.h"
  41 #include "i40e_rxtx.h"
  42 #include "i40e_rxtx_vec_common.h"
  43
  44 #include <tmmintrin.h>
  45
  46 #ifndef __INTEL_COMPILER
  47 #pragma GCC diagnostic ignored "-Wcast-qual"
  48 #endif
  49
  50 static inline void
  51 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
  52 {
  53         int i;
  54         uint16_t rx_id;
  55         volatile union i40e_rx_desc *rxdp;
  56         struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  57         struct rte_mbuf *mb0, *mb1;
  58         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  59                         RTE_PKTMBUF_HEADROOM);
  60         __m128i dma_addr0, dma_addr1;
  61
  62         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  63
  64         /* Pull 'n' more MBUFs into the software ring */
  65         if (rte_mempool_get_bulk(rxq->mp,
  66                                  (void *)rxep,
  67                                  RTE_I40E_RXQ_REARM_THRESH) < 0) {
  68                 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
  69                     rxq->nb_rx_desc) {
  70                         dma_addr0 = _mm_setzero_si128();
  71                         for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
  72                                 rxep[i].mbuf = &rxq->fake_mbuf;
  73                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  74                                                 dma_addr0);
  75                         }
  76                 }
  77                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  78                         RTE_I40E_RXQ_REARM_THRESH;
  79                 return;
  80         }
  81
  82         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  83         for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  84                 __m128i vaddr0, vaddr1;
  85                 uintptr_t p0, p1;
  86
  87                 mb0 = rxep[0].mbuf;
  88                 mb1 = rxep[1].mbuf;
  89
  90                  /* Flush mbuf with pkt template.
  91                  * Data to be rearmed is 6 bytes long.
  92                  * Though, RX will overwrite ol_flags that are coming next
  93                  * anyway. So overwrite whole 8 bytes with one load:
  94                  * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
  95                  */
  96                 p0 = (uintptr_t)&mb0->rearm_data;
  97                 *(uint64_t *)p0 = rxq->mbuf_initializer;
  98                 p1 = (uintptr_t)&mb1->rearm_data;
  99                 *(uint64_t *)p1 = rxq->mbuf_initializer;
 100
 101                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
 102                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 103                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 104
 105                 /* convert pa to dma_addr hdr/data */
 106                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 107                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 108
 109                 /* add headroom to pa values */
 110                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
 111                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 112
 113                 /* flush desc with pa dma_addr */
 114                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 115                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 116         }
 117
 118         rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
 119         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 120                 rxq->rxrearm_start = 0;
 121
 122         rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
 123
 124         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 125                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 126
 127         /* Update the tail pointer on the NIC */
 128         I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 129 }
 130
 131 /* Handling the offload flags (olflags) field takes computation
 132  * time when receiving packets. Therefore we provide a flag to disable
 133  * the processing of the olflags field when they are not needed. This
 134  * gives improved performance, at the cost of losing the offload info
 135  * in the received packet
 136  */
 137 #ifdef RTE_LIBRTE_I40E_RX_OLFLAGS_ENABLE
 138
 139 static inline void
 140 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 141 {
 142         __m128i vlan0, vlan1, rss, l3_l4e;
 143
 144         /* mask everything except RSS, flow director and VLAN flags
 145          * bit2 is for VLAN tag, bit11 for flow director indication
 146          * bit13:12 for RSS indication.
 147          */
 148         const __m128i rss_vlan_msk = _mm_set_epi32(
 149                         0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
 150
 151         /* map rss and vlan type to rss hash and vlan flag */
 152         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 153                         0, 0, 0, 0,
 154                         0, 0, 0, PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
 155                         0, 0, 0, 0);
 156
 157         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
 158                         0, 0, 0, 0,
 159                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
 160                         0, 0, PKT_RX_FDIR, 0);
 161
 162         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 163                         PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
 164                         PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
 165                         PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
 166                         PKT_RX_EIP_CKSUM_BAD,
 167                         PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD,
 168                         PKT_RX_L4_CKSUM_BAD,
 169                         PKT_RX_IP_CKSUM_BAD,
 170                         0);
 171
 172         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
 173         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
 174         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
 175
 176         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
 177         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
 178
 179         rss = _mm_srli_epi32(vlan1, 11);
 180         rss = _mm_shuffle_epi8(rss_flags, rss);
 181
 182         l3_l4e = _mm_srli_epi32(vlan1, 22);
 183         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
 184
 185         vlan0 = _mm_or_si128(vlan0, rss);
 186         vlan0 = _mm_or_si128(vlan0, l3_l4e);
 187
 188         rx_pkts[0]->ol_flags = _mm_extract_epi16(vlan0, 0);
 189         rx_pkts[1]->ol_flags = _mm_extract_epi16(vlan0, 2);
 190         rx_pkts[2]->ol_flags = _mm_extract_epi16(vlan0, 4);
 191         rx_pkts[3]->ol_flags = _mm_extract_epi16(vlan0, 6);
 192 }
 193 #else
 194 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 195 #endif
 196
 197 #define PKTLEN_SHIFT     10
 198
 199 static inline void
 200 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 201 {
 202         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
 203         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
 204
 205         ptype0 = _mm_srli_epi64(ptype0, 30);
 206         ptype1 = _mm_srli_epi64(ptype1, 30);
 207
 208         rx_pkts[0]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 0));
 209         rx_pkts[1]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype0, 8));
 210         rx_pkts[2]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 0));
 211         rx_pkts[3]->packet_type = i40e_rxd_pkt_type_mapping(_mm_extract_epi8(ptype1, 8));
 212 }
 213
 214  /*
 215  * Notice:
 216  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 217  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 218  *   numbers of DD bits
 219  */
 220 static inline uint16_t
 221 _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 222                    uint16_t nb_pkts, uint8_t *split_packet)
 223 {
 224         volatile union i40e_rx_desc *rxdp;
 225         struct i40e_rx_entry *sw_ring;
 226         uint16_t nb_pkts_recd;
 227         int pos;
 228         uint64_t var;
 229         __m128i shuf_msk;
 230
 231         __m128i crc_adjust = _mm_set_epi16(
 232                                 0, 0, 0,    /* ignore non-length fields */
 233                                 -rxq->crc_len, /* sub crc on data_len */
 234                                 0,          /* ignore high-16bits of pkt_len */
 235                                 -rxq->crc_len, /* sub crc on pkt_len */
 236                                 0, 0            /* ignore pkt_type field */
 237                         );
 238         __m128i dd_check, eop_check;
 239
 240         /* nb_pkts shall be less equal than RTE_I40E_MAX_RX_BURST */
 241         nb_pkts = RTE_MIN(nb_pkts, RTE_I40E_MAX_RX_BURST);
 242
 243         /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
 244         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
 245
 246         /* Just the act of getting into the function from the application is
 247          * going to cost about 7 cycles
 248          */
 249         rxdp = rxq->rx_ring + rxq->rx_tail;
 250
 251         rte_prefetch0(rxdp);
 252
 253         /* See if we need to rearm the RX queue - gives the prefetch a bit
 254          * of time to act
 255          */
 256         if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
 257                 i40e_rxq_rearm(rxq);
 258
 259         /* Before we start moving massive data around, check to see if
 260          * there is actually a packet available
 261          */
 262         if (!(rxdp->wb.qword1.status_error_len &
 263                         rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 264                 return 0;
 265
 266         /* 4 packets DD mask */
 267         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 268
 269         /* 4 packets EOP mask */
 270         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 271
 272         /* mask to shuffle from desc. to mbuf */
 273         shuf_msk = _mm_set_epi8(
 274                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 275                 3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 276                 15, 14,      /* octet 15~14, 16 bits data_len */
 277                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 278                 15, 14,      /* octet 15~14, low 16 bits pkt_len */
 279                 0xFF, 0xFF,  /* pkt_type set as unknown */
 280                 0xFF, 0xFF  /*pkt_type set as unknown */
 281                 );
 282
 283         /* Cache is empty -> need to scan the buffer rings, but first move
 284          * the next 'n' mbufs into the cache
 285          */
 286         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 287
 288         /* A. load 4 packet in one loop
 289          * [A*. mask out 4 unused dirty field in desc]
 290          * B. copy 4 mbuf point from swring to rx_pkts
 291          * C. calc the number of DD bits among the 4 packets
 292          * [C*. extract the end-of-packet bit, if requested]
 293          * D. fill info. from desc to mbuf
 294          */
 295
 296         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 297                         pos += RTE_I40E_DESCS_PER_LOOP,
 298                         rxdp += RTE_I40E_DESCS_PER_LOOP) {
 299                 __m128i descs[RTE_I40E_DESCS_PER_LOOP];
 300                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 301                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 302                 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 303
 304                 /* B.1 load 1 mbuf point */
 305                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 306                 /* Read desc statuses backwards to avoid race condition */
 307                 /* A.1 load 4 pkts desc */
 308                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 309                 rte_compiler_barrier();
 310
 311                 /* B.2 copy 2 mbuf point into rx_pkts  */
 312                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 313
 314                 /* B.1 load 1 mbuf point */
 315                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 316
 317                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 318                 rte_compiler_barrier();
 319                 /* B.1 load 2 mbuf point */
 320                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 321                 rte_compiler_barrier();
 322                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 323
 324                 /* B.2 copy 2 mbuf point into rx_pkts  */
 325                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 326
 327                 if (split_packet) {
 328                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 329                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 330                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 331                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 332                 }
 333
 334                 /* avoid compiler reorder optimization */
 335                 rte_compiler_barrier();
 336
 337                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
 338                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
 339                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
 340
 341                 /* merge the now-aligned packet length fields back in */
 342                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
 343                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
 344
 345                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 346                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 347                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 348
 349                 /* C.1 4=>2 filter staterr info only */
 350                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 351                 /* C.1 4=>2 filter staterr info only */
 352                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 353
 354                 desc_to_olflags_v(descs, &rx_pkts[pos]);
 355
 356                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 357                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 358                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 359
 360                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
 361                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
 362                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
 363
 364                 /* merge the now-aligned packet length fields back in */
 365                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
 366                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
 367
 368                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 369                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 370                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 371
 372                 /* C.2 get 4 pkts staterr value  */
 373                 zero = _mm_xor_si128(dd_check, dd_check);
 374                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 375
 376                 /* D.3 copy final 3,4 data to rx_pkts */
 377                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 378                                  pkt_mb4);
 379                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 380                                  pkt_mb3);
 381
 382                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 383                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 384                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 385
 386                 /* C* extract and record EOP bit */
 387                 if (split_packet) {
 388                         __m128i eop_shuf_mask = _mm_set_epi8(
 389                                         0xFF, 0xFF, 0xFF, 0xFF,
 390                                         0xFF, 0xFF, 0xFF, 0xFF,
 391                                         0xFF, 0xFF, 0xFF, 0xFF,
 392                                         0x04, 0x0C, 0x00, 0x08
 393                                         );
 394
 395                         /* and with mask to extract bits, flipping 1-0 */
 396                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 397                         /* the staterr values are not in order, as the count
 398                          * count of dd bits doesn't care. However, for end of
 399                          * packet tracking, we do care, so shuffle. This also
 400                          * compresses the 32-bit values to 8-bit
 401                          */
 402                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 403                         /* store the resulting 32-bit value */
 404                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 405                         split_packet += RTE_I40E_DESCS_PER_LOOP;
 406
 407                         /* zero-out next pointers */
 408                         rx_pkts[pos]->next = NULL;
 409                         rx_pkts[pos + 1]->next = NULL;
 410                         rx_pkts[pos + 2]->next = NULL;
 411                         rx_pkts[pos + 3]->next = NULL;
 412                 }
 413
 414                 /* C.3 calc available number of desc */
 415                 staterr = _mm_and_si128(staterr, dd_check);
 416                 staterr = _mm_packs_epi32(staterr, zero);
 417
 418                 /* D.3 copy final 1,2 data to rx_pkts */
 419                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 420                                  pkt_mb2);
 421                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 422                                  pkt_mb1);
 423                 desc_to_ptype_v(descs, &rx_pkts[pos]);
 424                 /* C.4 calc avaialbe number of desc */
 425                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 426                 nb_pkts_recd += var;
 427                 if (likely(var != RTE_I40E_DESCS_PER_LOOP))
 428                         break;
 429         }
 430
 431         /* Update our internal tail pointer */
 432         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 433         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 434         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 435
 436         return nb_pkts_recd;
 437 }
 438
 439  /*
 440  * Notice:
 441  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 442  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 443  *   numbers of DD bits
 444  */
 445 uint16_t
 446 i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 447                    uint16_t nb_pkts)
 448 {
 449         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 450 }
 451
 452  /* vPMD receive routine that reassembles scattered packets
 453  * Notice:
 454  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
 455  * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
 456  *   numbers of DD bits
 457  */
 458 uint16_t
 459 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 460                              uint16_t nb_pkts)
 461 {
 462
 463         struct i40e_rx_queue *rxq = rx_queue;
 464         uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
 465
 466         /* get some new buffers */
 467         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 468                         split_flags);
 469         if (nb_bufs == 0)
 470                 return 0;
 471
 472         /* happy day case, full burst + no packets to be joined */
 473         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 474
 475         if (rxq->pkt_first_seg == NULL &&
 476                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 477                         split_fl64[2] == 0 && split_fl64[3] == 0)
 478                 return nb_bufs;
 479
 480         /* reassemble any packets that need reassembly*/
 481         unsigned i = 0;
 482
 483         if (rxq->pkt_first_seg == NULL) {
 484                 /* find the first split flag, and only reassemble then*/
 485                 while (i < nb_bufs && !split_flags[i])
 486                         i++;
 487                 if (i == nb_bufs)
 488                         return nb_bufs;
 489         }
 490         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 491                 &split_flags[i]);
 492 }
 493
 494 static inline void
 495 vtx1(volatile struct i40e_tx_desc *txdp,
 496                 struct rte_mbuf *pkt, uint64_t flags)
 497 {
 498         uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
 499                         ((uint64_t)flags  << I40E_TXD_QW1_CMD_SHIFT) |
 500                         ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
 501
 502         __m128i descriptor = _mm_set_epi64x(high_qw,
 503                                 pkt->buf_physaddr + pkt->data_off);
 504         _mm_store_si128((__m128i *)txdp, descriptor);
 505 }
 506
 507 static inline void
 508 vtx(volatile struct i40e_tx_desc *txdp,
 509                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 510 {
 511         int i;
 512
 513         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 514                 vtx1(txdp, *pkt, flags);
 515 }
 516
 517 uint16_t
 518 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 519                    uint16_t nb_pkts)
 520 {
 521         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
 522         volatile struct i40e_tx_desc *txdp;
 523         struct i40e_tx_entry *txep;
 524         uint16_t n, nb_commit, tx_id;
 525         uint64_t flags = I40E_TD_CMD;
 526         uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
 527         int i;
 528
 529         /* cross rx_thresh boundary is not allowed */
 530         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 531
 532         if (txq->nb_tx_free < txq->tx_free_thresh)
 533                 i40e_tx_free_bufs(txq);
 534
 535         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 536         if (unlikely(nb_pkts == 0))
 537                 return 0;
 538
 539         tx_id = txq->tx_tail;
 540         txdp = &txq->tx_ring[tx_id];
 541         txep = &txq->sw_ring[tx_id];
 542
 543         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 544
 545         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 546         if (nb_commit >= n) {
 547                 tx_backlog_entry(txep, tx_pkts, n);
 548
 549                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 550                         vtx1(txdp, *tx_pkts, flags);
 551
 552                 vtx1(txdp, *tx_pkts++, rs);
 553
 554                 nb_commit = (uint16_t)(nb_commit - n);
 555
 556                 tx_id = 0;
 557                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 558
 559                 /* avoid reach the end of ring */
 560                 txdp = &txq->tx_ring[tx_id];
 561                 txep = &txq->sw_ring[tx_id];
 562         }
 563
 564         tx_backlog_entry(txep, tx_pkts, nb_commit);
 565
 566         vtx(txdp, tx_pkts, nb_commit, flags);
 567
 568         tx_id = (uint16_t)(tx_id + nb_commit);
 569         if (tx_id > txq->tx_next_rs) {
 570                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 571                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
 572                                                 I40E_TXD_QW1_CMD_SHIFT);
 573                 txq->tx_next_rs =
 574                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 575         }
 576
 577         txq->tx_tail = tx_id;
 578
 579         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 580
 581         return nb_pkts;
 582 }
 583
 584 void __attribute__((cold))
 585 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
 586 {
 587         _i40e_rx_queue_release_mbufs_vec(rxq);
 588 }
 589
 590 int __attribute__((cold))
 591 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
 592 {
 593         return i40e_rxq_vec_setup_default(rxq);
 594 }
 595
 596 int __attribute__((cold))
 597 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
 598 {
 599         return 0;
 600 }
 601
 602 int __attribute__((cold))
 603 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 604 {
 605 #ifndef RTE_LIBRTE_IEEE1588
 606         /* need SSE4.1 support */
 607         if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
 608                 return -1;
 609 #endif
 610
 611         return i40e_rx_vec_dev_conf_condition_check_default(dev);
 612 }