1 /*******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_82599_MAX_TX_QUEUES 128
41 #define IXGBE_82599_MAX_RX_QUEUES 128
42 #define IXGBE_82599_RAR_ENTRIES 128
43 #define IXGBE_82599_MC_TBL_SIZE 128
44 #define IXGBE_82599_VFT_TBL_SIZE 128
45 #define IXGBE_82599_RX_PB_SIZE 512
47 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
51 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
52 u16 offset, u16 *data);
53 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
54 u16 words, u16 *data);
55 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
56 u8 dev_addr, u8 *data);
57 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
58 u8 dev_addr, u8 data);
60 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
62 struct ixgbe_mac_info *mac = &hw->mac;
64 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
67 * enable the laser control functions for SFP+ fiber
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
71 !ixgbe_mng_enabled(hw)) {
72 mac->ops.disable_tx_laser =
73 ixgbe_disable_tx_laser_multispeed_fiber;
74 mac->ops.enable_tx_laser =
75 ixgbe_enable_tx_laser_multispeed_fiber;
76 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
87 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
88 mac->ops.set_rate_select_speed =
89 ixgbe_set_hard_rate_select_speed;
90 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
91 mac->ops.set_rate_select_speed =
92 ixgbe_set_soft_rate_select_speed;
94 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
95 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
96 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
97 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
98 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
100 mac->ops.setup_link = ixgbe_setup_mac_link_82599;
106 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
107 * @hw: pointer to hardware structure
109 * Initialize any function pointers that were not able to be
110 * set during init_shared_code because the PHY/SFP type was
111 * not known. Perform the SFP init if necessary.
114 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
116 struct ixgbe_mac_info *mac = &hw->mac;
117 struct ixgbe_phy_info *phy = &hw->phy;
118 s32 ret_val = IXGBE_SUCCESS;
121 DEBUGFUNC("ixgbe_init_phy_ops_82599");
123 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
124 /* Store flag indicating I2C bus access control unit. */
125 hw->phy.qsfp_shared_i2c_bus = TRUE;
127 /* Initialize access to QSFP+ I2C bus */
128 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
129 esdp |= IXGBE_ESDP_SDP0_DIR;
130 esdp &= ~IXGBE_ESDP_SDP1_DIR;
131 esdp &= ~IXGBE_ESDP_SDP0;
132 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
133 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
134 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
135 IXGBE_WRITE_FLUSH(hw);
137 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
138 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
140 /* Identify the PHY or SFP module */
141 ret_val = phy->ops.identify(hw);
142 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
143 goto init_phy_ops_out;
145 /* Setup function pointers based on detected SFP module and speeds */
146 ixgbe_init_mac_link_ops_82599(hw);
147 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
148 hw->phy.ops.reset = NULL;
150 /* If copper media, overwrite with copper function pointers */
151 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
152 mac->ops.setup_link = ixgbe_setup_copper_link_82599;
153 mac->ops.get_link_capabilities =
154 ixgbe_get_copper_link_capabilities_generic;
157 /* Set necessary function pointers based on PHY type */
158 switch (hw->phy.type) {
160 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
161 phy->ops.check_link = ixgbe_check_phy_link_tnx;
162 phy->ops.get_firmware_version =
163 ixgbe_get_phy_firmware_version_tnx;
172 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
174 s32 ret_val = IXGBE_SUCCESS;
175 u16 list_offset, data_offset, data_value;
177 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
179 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
180 ixgbe_init_mac_link_ops_82599(hw);
182 hw->phy.ops.reset = NULL;
184 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
186 if (ret_val != IXGBE_SUCCESS)
189 /* PHY config will finish before releasing the semaphore */
190 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
191 IXGBE_GSSR_MAC_CSR_SM);
192 if (ret_val != IXGBE_SUCCESS) {
193 ret_val = IXGBE_ERR_SWFW_SYNC;
197 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
199 while (data_value != 0xffff) {
200 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
201 IXGBE_WRITE_FLUSH(hw);
202 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
206 /* Release the semaphore */
207 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
208 /* Delay obtaining semaphore again to allow FW access
209 * prot_autoc_write uses the semaphore too.
211 msec_delay(hw->eeprom.semaphore_delay);
213 /* Restart DSP and set SFI mode */
214 ret_val = hw->mac.ops.prot_autoc_write(hw,
215 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
219 DEBUGOUT("sfp module setup not complete\n");
220 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
230 /* Release the semaphore */
231 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
232 /* Delay obtaining semaphore again to allow FW access */
233 msec_delay(hw->eeprom.semaphore_delay);
234 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
235 "eeprom read at offset %d failed", data_offset);
236 return IXGBE_ERR_PHY;
240 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
241 * @hw: pointer to hardware structure
242 * @locked: Return the if we locked for this read.
243 * @reg_val: Value we read from AUTOC
245 * For this part (82599) we need to wrap read-modify-writes with a possible
246 * FW/SW lock. It is assumed this lock will be freed with the next
247 * prot_autoc_write_82599().
249 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
254 /* If LESM is on then we need to hold the SW/FW semaphore. */
255 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
256 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
257 IXGBE_GSSR_MAC_CSR_SM);
258 if (ret_val != IXGBE_SUCCESS)
259 return IXGBE_ERR_SWFW_SYNC;
264 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
265 return IXGBE_SUCCESS;
269 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
270 * @hw: pointer to hardware structure
271 * @reg_val: value to write to AUTOC
272 * @locked: bool to indicate whether the SW/FW lock was already taken by
273 * previous proc_autoc_read_82599.
275 * This part (82599) may need to hold the SW/FW lock around all writes to
276 * AUTOC. Likewise after a write we need to do a pipeline reset.
278 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
280 s32 ret_val = IXGBE_SUCCESS;
282 /* Blocked by MNG FW so bail */
283 if (ixgbe_check_reset_blocked(hw))
286 /* We only need to get the lock if:
287 * - We didn't do it already (in the read part of a read-modify-write)
290 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
291 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
292 IXGBE_GSSR_MAC_CSR_SM);
293 if (ret_val != IXGBE_SUCCESS)
294 return IXGBE_ERR_SWFW_SYNC;
299 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
300 ret_val = ixgbe_reset_pipeline_82599(hw);
303 /* Free the SW/FW semaphore as we either grabbed it here or
304 * already had it when this function was called.
307 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
313 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
314 * @hw: pointer to hardware structure
316 * Initialize the function pointers and assign the MAC type for 82599.
317 * Does not touch the hardware.
320 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
322 struct ixgbe_mac_info *mac = &hw->mac;
323 struct ixgbe_phy_info *phy = &hw->phy;
324 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
327 DEBUGFUNC("ixgbe_init_ops_82599");
329 ixgbe_init_phy_ops_generic(hw);
330 ret_val = ixgbe_init_ops_generic(hw);
333 phy->ops.identify = ixgbe_identify_phy_82599;
334 phy->ops.init = ixgbe_init_phy_ops_82599;
337 mac->ops.reset_hw = ixgbe_reset_hw_82599;
338 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;
339 mac->ops.get_media_type = ixgbe_get_media_type_82599;
340 mac->ops.get_supported_physical_layer =
341 ixgbe_get_supported_physical_layer_82599;
342 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
343 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
344 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
345 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
346 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
347 mac->ops.start_hw = ixgbe_start_hw_82599;
348 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;
349 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;
350 mac->ops.get_device_caps = ixgbe_get_device_caps_generic;
351 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;
352 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;
353 mac->ops.prot_autoc_read = prot_autoc_read_82599;
354 mac->ops.prot_autoc_write = prot_autoc_write_82599;
356 /* RAR, Multicast, VLAN */
357 mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
358 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;
359 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
360 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
361 mac->rar_highwater = 1;
362 mac->ops.set_vfta = ixgbe_set_vfta_generic;
363 mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
364 mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
365 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
366 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
367 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;
368 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;
371 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
372 mac->ops.check_link = ixgbe_check_mac_link_generic;
373 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic;
374 ixgbe_init_mac_link_ops_82599(hw);
376 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
377 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
378 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
379 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
380 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
381 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
382 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
384 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
385 & IXGBE_FWSM_MODE_MASK);
387 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
390 eeprom->ops.read = ixgbe_read_eeprom_82599;
391 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;
393 /* Manageability interface */
394 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;
396 mac->ops.get_thermal_sensor_data =
397 ixgbe_get_thermal_sensor_data_generic;
398 mac->ops.init_thermal_sensor_thresh =
399 ixgbe_init_thermal_sensor_thresh_generic;
401 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
407 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
408 * @hw: pointer to hardware structure
409 * @speed: pointer to link speed
410 * @autoneg: true when autoneg or autotry is enabled
412 * Determines the link capabilities by reading the AUTOC register.
414 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
415 ixgbe_link_speed *speed,
418 s32 status = IXGBE_SUCCESS;
421 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
424 /* Check if 1G SFP module. */
425 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
426 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
427 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
428 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
429 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
430 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
431 *speed = IXGBE_LINK_SPEED_1GB_FULL;
437 * Determine link capabilities based on the stored value of AUTOC,
438 * which represents EEPROM defaults. If AUTOC value has not
439 * been stored, use the current register values.
441 if (hw->mac.orig_link_settings_stored)
442 autoc = hw->mac.orig_autoc;
444 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
446 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
447 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
448 *speed = IXGBE_LINK_SPEED_1GB_FULL;
452 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
453 *speed = IXGBE_LINK_SPEED_10GB_FULL;
457 case IXGBE_AUTOC_LMS_1G_AN:
458 *speed = IXGBE_LINK_SPEED_1GB_FULL;
462 case IXGBE_AUTOC_LMS_10G_SERIAL:
463 *speed = IXGBE_LINK_SPEED_10GB_FULL;
467 case IXGBE_AUTOC_LMS_KX4_KX_KR:
468 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
469 *speed = IXGBE_LINK_SPEED_UNKNOWN;
470 if (autoc & IXGBE_AUTOC_KR_SUPP)
471 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
472 if (autoc & IXGBE_AUTOC_KX4_SUPP)
473 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
474 if (autoc & IXGBE_AUTOC_KX_SUPP)
475 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
479 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
480 *speed = IXGBE_LINK_SPEED_100_FULL;
481 if (autoc & IXGBE_AUTOC_KR_SUPP)
482 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
483 if (autoc & IXGBE_AUTOC_KX4_SUPP)
484 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
485 if (autoc & IXGBE_AUTOC_KX_SUPP)
486 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
490 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
491 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
496 status = IXGBE_ERR_LINK_SETUP;
501 if (hw->phy.multispeed_fiber) {
502 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
503 IXGBE_LINK_SPEED_1GB_FULL;
505 /* QSFP must not enable full auto-negotiation
506 * Limited autoneg is enabled at 1G
508 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
519 * ixgbe_get_media_type_82599 - Get media type
520 * @hw: pointer to hardware structure
522 * Returns the media type (fiber, copper, backplane)
524 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
526 enum ixgbe_media_type media_type;
528 DEBUGFUNC("ixgbe_get_media_type_82599");
530 /* Detect if there is a copper PHY attached. */
531 switch (hw->phy.type) {
532 case ixgbe_phy_cu_unknown:
534 media_type = ixgbe_media_type_copper;
540 switch (hw->device_id) {
541 case IXGBE_DEV_ID_82599_KX4:
542 case IXGBE_DEV_ID_82599_KX4_MEZZ:
543 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
544 case IXGBE_DEV_ID_82599_KR:
545 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
546 case IXGBE_DEV_ID_82599_XAUI_LOM:
547 /* Default device ID is mezzanine card KX/KX4 */
548 media_type = ixgbe_media_type_backplane;
550 case IXGBE_DEV_ID_82599_SFP:
551 case IXGBE_DEV_ID_82599_SFP_FCOE:
552 case IXGBE_DEV_ID_82599_SFP_EM:
553 case IXGBE_DEV_ID_82599_SFP_SF2:
554 case IXGBE_DEV_ID_82599_SFP_SF_QP:
555 case IXGBE_DEV_ID_82599EN_SFP:
556 media_type = ixgbe_media_type_fiber;
558 case IXGBE_DEV_ID_82599_CX4:
559 media_type = ixgbe_media_type_cx4;
561 case IXGBE_DEV_ID_82599_T3_LOM:
562 media_type = ixgbe_media_type_copper;
564 case IXGBE_DEV_ID_82599_LS:
565 media_type = ixgbe_media_type_fiber_lco;
567 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
568 media_type = ixgbe_media_type_fiber_qsfp;
570 case IXGBE_DEV_ID_82599_BYPASS:
571 media_type = ixgbe_media_type_fiber_fixed;
572 hw->phy.multispeed_fiber = true;
575 media_type = ixgbe_media_type_unknown;
583 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
584 * @hw: pointer to hardware structure
586 * Disables link during D3 power down sequence.
589 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
594 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
595 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
597 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
598 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
599 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
600 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
601 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
606 * ixgbe_start_mac_link_82599 - Setup MAC link settings
607 * @hw: pointer to hardware structure
608 * @autoneg_wait_to_complete: true when waiting for completion is needed
610 * Configures link settings based on values in the ixgbe_hw struct.
611 * Restarts the link. Performs autonegotiation if needed.
613 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
614 bool autoneg_wait_to_complete)
619 s32 status = IXGBE_SUCCESS;
620 bool got_lock = false;
622 DEBUGFUNC("ixgbe_start_mac_link_82599");
625 /* reset_pipeline requires us to hold this lock as it writes to
628 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
629 status = hw->mac.ops.acquire_swfw_sync(hw,
630 IXGBE_GSSR_MAC_CSR_SM);
631 if (status != IXGBE_SUCCESS)
638 ixgbe_reset_pipeline_82599(hw);
641 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
643 /* Only poll for autoneg to complete if specified to do so */
644 if (autoneg_wait_to_complete) {
645 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
646 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
647 IXGBE_AUTOC_LMS_KX4_KX_KR ||
648 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
649 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
650 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
651 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
652 links_reg = 0; /* Just in case Autoneg time = 0 */
653 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
654 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
655 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
659 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
660 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
661 DEBUGOUT("Autoneg did not complete.\n");
666 /* Add delay to filter out noises during initial link setup */
674 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
675 * @hw: pointer to hardware structure
677 * The base drivers may require better control over SFP+ module
678 * PHY states. This includes selectively shutting down the Tx
679 * laser on the PHY, effectively halting physical link.
681 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
683 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
685 /* Blocked by MNG FW so bail */
686 if (ixgbe_check_reset_blocked(hw))
689 /* Disable Tx laser; allow 100us to go dark per spec */
690 esdp_reg |= IXGBE_ESDP_SDP3;
691 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
692 IXGBE_WRITE_FLUSH(hw);
697 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
698 * @hw: pointer to hardware structure
700 * The base drivers may require better control over SFP+ module
701 * PHY states. This includes selectively turning on the Tx
702 * laser on the PHY, effectively starting physical link.
704 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
706 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
708 /* Enable Tx laser; allow 100ms to light up */
709 esdp_reg &= ~IXGBE_ESDP_SDP3;
710 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
711 IXGBE_WRITE_FLUSH(hw);
716 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
717 * @hw: pointer to hardware structure
719 * When the driver changes the link speeds that it can support,
720 * it sets autotry_restart to true to indicate that we need to
721 * initiate a new autotry session with the link partner. To do
722 * so, we set the speed then disable and re-enable the Tx laser, to
723 * alert the link partner that it also needs to restart autotry on its
724 * end. This is consistent with true clause 37 autoneg, which also
725 * involves a loss of signal.
727 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
729 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
731 /* Blocked by MNG FW so bail */
732 if (ixgbe_check_reset_blocked(hw))
735 if (hw->mac.autotry_restart) {
736 ixgbe_disable_tx_laser_multispeed_fiber(hw);
737 ixgbe_enable_tx_laser_multispeed_fiber(hw);
738 hw->mac.autotry_restart = false;
743 * ixgbe_set_hard_rate_select_speed - Set module link speed
744 * @hw: pointer to hardware structure
745 * @speed: link speed to set
747 * Set module link speed via RS0/RS1 rate select pins.
749 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
750 ixgbe_link_speed speed)
752 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
755 case IXGBE_LINK_SPEED_10GB_FULL:
756 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
758 case IXGBE_LINK_SPEED_1GB_FULL:
759 esdp_reg &= ~IXGBE_ESDP_SDP5;
760 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
763 DEBUGOUT("Invalid fixed module speed\n");
767 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
768 IXGBE_WRITE_FLUSH(hw);
772 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
773 * @hw: pointer to hardware structure
774 * @speed: new link speed
775 * @autoneg_wait_to_complete: true when waiting for completion is needed
777 * Implements the Intel SmartSpeed algorithm.
779 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
780 ixgbe_link_speed speed,
781 bool autoneg_wait_to_complete)
783 s32 status = IXGBE_SUCCESS;
784 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
786 bool link_up = false;
787 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
789 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
791 /* Set autoneg_advertised value based on input link speed */
792 hw->phy.autoneg_advertised = 0;
794 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
797 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
798 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
800 if (speed & IXGBE_LINK_SPEED_100_FULL)
801 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
804 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
805 * autoneg advertisement if link is unable to be established at the
806 * highest negotiated rate. This can sometimes happen due to integrity
807 * issues with the physical media connection.
810 /* First, try to get link with full advertisement */
811 hw->phy.smart_speed_active = false;
812 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
813 status = ixgbe_setup_mac_link_82599(hw, speed,
814 autoneg_wait_to_complete);
815 if (status != IXGBE_SUCCESS)
819 * Wait for the controller to acquire link. Per IEEE 802.3ap,
820 * Section 73.10.2, we may have to wait up to 500ms if KR is
821 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
822 * Table 9 in the AN MAS.
824 for (i = 0; i < 5; i++) {
827 /* If we have link, just jump out */
828 status = ixgbe_check_link(hw, &link_speed, &link_up,
830 if (status != IXGBE_SUCCESS)
839 * We didn't get link. If we advertised KR plus one of KX4/KX
840 * (or BX4/BX), then disable KR and try again.
842 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
843 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
846 /* Turn SmartSpeed on to disable KR support */
847 hw->phy.smart_speed_active = true;
848 status = ixgbe_setup_mac_link_82599(hw, speed,
849 autoneg_wait_to_complete);
850 if (status != IXGBE_SUCCESS)
854 * Wait for the controller to acquire link. 600ms will allow for
855 * the AN link_fail_inhibit_timer as well for multiple cycles of
856 * parallel detect, both 10g and 1g. This allows for the maximum
857 * connect attempts as defined in the AN MAS table 73-7.
859 for (i = 0; i < 6; i++) {
862 /* If we have link, just jump out */
863 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
864 if (status != IXGBE_SUCCESS)
871 /* We didn't get link. Turn SmartSpeed back off. */
872 hw->phy.smart_speed_active = false;
873 status = ixgbe_setup_mac_link_82599(hw, speed,
874 autoneg_wait_to_complete);
877 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
878 DEBUGOUT("Smartspeed has downgraded the link speed "
879 "from the maximum advertised\n");
884 * ixgbe_setup_mac_link_82599 - Set MAC link speed
885 * @hw: pointer to hardware structure
886 * @speed: new link speed
887 * @autoneg_wait_to_complete: true when waiting for completion is needed
889 * Set the link speed in the AUTOC register and restarts link.
891 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
892 ixgbe_link_speed speed,
893 bool autoneg_wait_to_complete)
895 bool autoneg = false;
896 s32 status = IXGBE_SUCCESS;
897 u32 pma_pmd_1g, link_mode;
898 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
899 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
900 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
901 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
902 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
905 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
907 DEBUGFUNC("ixgbe_setup_mac_link_82599");
909 /* Check to see if speed passed in is supported. */
910 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
914 speed &= link_capabilities;
916 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
917 status = IXGBE_ERR_LINK_SETUP;
921 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
922 if (hw->mac.orig_link_settings_stored)
923 orig_autoc = hw->mac.orig_autoc;
927 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
928 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
930 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
931 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
932 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
933 /* Set KX4/KX/KR support according to speed requested */
934 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
935 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
936 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
937 autoc |= IXGBE_AUTOC_KX4_SUPP;
938 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
939 (hw->phy.smart_speed_active == false))
940 autoc |= IXGBE_AUTOC_KR_SUPP;
942 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
943 autoc |= IXGBE_AUTOC_KX_SUPP;
944 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
945 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
946 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
947 /* Switch from 1G SFI to 10G SFI if requested */
948 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
949 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
950 autoc &= ~IXGBE_AUTOC_LMS_MASK;
951 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
953 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
954 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
955 /* Switch from 10G SFI to 1G SFI if requested */
956 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
957 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
958 autoc &= ~IXGBE_AUTOC_LMS_MASK;
959 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
960 autoc |= IXGBE_AUTOC_LMS_1G_AN;
962 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
966 if (autoc != current_autoc) {
968 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
969 if (status != IXGBE_SUCCESS)
972 /* Only poll for autoneg to complete if specified to do so */
973 if (autoneg_wait_to_complete) {
974 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
975 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
976 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
977 links_reg = 0; /*Just in case Autoneg time=0*/
978 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
980 IXGBE_READ_REG(hw, IXGBE_LINKS);
981 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
985 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
987 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
988 DEBUGOUT("Autoneg did not complete.\n");
993 /* Add delay to filter out noises during initial link setup */
1002 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1003 * @hw: pointer to hardware structure
1004 * @speed: new link speed
1005 * @autoneg_wait_to_complete: true if waiting is needed to complete
1007 * Restarts link on PHY and MAC based on settings passed in.
1009 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1010 ixgbe_link_speed speed,
1011 bool autoneg_wait_to_complete)
1015 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1017 /* Setup the PHY according to input speed */
1018 status = hw->phy.ops.setup_link_speed(hw, speed,
1019 autoneg_wait_to_complete);
1021 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1027 * ixgbe_reset_hw_82599 - Perform hardware reset
1028 * @hw: pointer to hardware structure
1030 * Resets the hardware by resetting the transmit and receive units, masks
1031 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1034 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1036 ixgbe_link_speed link_speed;
1039 u32 i, autoc, autoc2;
1041 bool link_up = false;
1043 DEBUGFUNC("ixgbe_reset_hw_82599");
1045 /* Call adapter stop to disable tx/rx and clear interrupts */
1046 status = hw->mac.ops.stop_adapter(hw);
1047 if (status != IXGBE_SUCCESS)
1050 /* flush pending Tx transactions */
1051 ixgbe_clear_tx_pending(hw);
1053 /* PHY ops must be identified and initialized prior to reset */
1055 /* Identify PHY and related function pointers */
1056 status = hw->phy.ops.init(hw);
1058 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1061 /* Setup SFP module if there is one present. */
1062 if (hw->phy.sfp_setup_needed) {
1063 status = hw->mac.ops.setup_sfp(hw);
1064 hw->phy.sfp_setup_needed = false;
1067 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1071 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1072 hw->phy.ops.reset(hw);
1074 /* remember AUTOC from before we reset */
1075 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1079 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1080 * If link reset is used when link is up, it might reset the PHY when
1081 * mng is using it. If link is down or the flag to force full link
1082 * reset is set, then perform link reset.
1084 ctrl = IXGBE_CTRL_LNK_RST;
1085 if (!hw->force_full_reset) {
1086 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1088 ctrl = IXGBE_CTRL_RST;
1091 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1092 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1093 IXGBE_WRITE_FLUSH(hw);
1095 /* Poll for reset bit to self-clear meaning reset is complete */
1096 for (i = 0; i < 10; i++) {
1098 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1099 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1103 if (ctrl & IXGBE_CTRL_RST_MASK) {
1104 status = IXGBE_ERR_RESET_FAILED;
1105 DEBUGOUT("Reset polling failed to complete.\n");
1111 * Double resets are required for recovery from certain error
1112 * conditions. Between resets, it is necessary to stall to
1113 * allow time for any pending HW events to complete.
1115 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1116 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1121 * Store the original AUTOC/AUTOC2 values if they have not been
1122 * stored off yet. Otherwise restore the stored original
1123 * values since the reset operation sets back to defaults.
1125 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1126 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1128 /* Enable link if disabled in NVM */
1129 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1130 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1131 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1132 IXGBE_WRITE_FLUSH(hw);
1135 if (hw->mac.orig_link_settings_stored == false) {
1136 hw->mac.orig_autoc = autoc;
1137 hw->mac.orig_autoc2 = autoc2;
1138 hw->mac.orig_link_settings_stored = true;
1141 /* If MNG FW is running on a multi-speed device that
1142 * doesn't autoneg with out driver support we need to
1143 * leave LMS in the state it was before we MAC reset.
1144 * Likewise if we support WoL we don't want change the
1147 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1149 hw->mac.orig_autoc =
1150 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1153 if (autoc != hw->mac.orig_autoc) {
1154 status = hw->mac.ops.prot_autoc_write(hw,
1157 if (status != IXGBE_SUCCESS)
1161 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1162 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1163 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1164 autoc2 |= (hw->mac.orig_autoc2 &
1165 IXGBE_AUTOC2_UPPER_MASK);
1166 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1170 /* Store the permanent mac address */
1171 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1174 * Store MAC address from RAR0, clear receive address registers, and
1175 * clear the multicast table. Also reset num_rar_entries to 128,
1176 * since we modify this value when programming the SAN MAC address.
1178 hw->mac.num_rar_entries = 128;
1179 hw->mac.ops.init_rx_addrs(hw);
1181 /* Store the permanent SAN mac address */
1182 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1184 /* Add the SAN MAC address to the RAR only if it's a valid address */
1185 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1186 /* Save the SAN MAC RAR index */
1187 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1189 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1190 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1192 /* clear VMDq pool/queue selection for this RAR */
1193 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1194 IXGBE_CLEAR_VMDQ_ALL);
1196 /* Reserve the last RAR for the SAN MAC address */
1197 hw->mac.num_rar_entries--;
1200 /* Store the alternative WWNN/WWPN prefix */
1201 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1202 &hw->mac.wwpn_prefix);
1209 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1210 * @hw: pointer to hardware structure
1211 * @fdircmd: current value of FDIRCMD register
1213 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1217 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1218 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1219 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1220 return IXGBE_SUCCESS;
1224 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1228 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1229 * @hw: pointer to hardware structure
1231 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1235 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1237 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1239 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1242 * Before starting reinitialization process,
1243 * FDIRCMD.CMD must be zero.
1245 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1247 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1251 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1252 IXGBE_WRITE_FLUSH(hw);
1254 * 82599 adapters flow director init flow cannot be restarted,
1255 * Workaround 82599 silicon errata by performing the following steps
1256 * before re-writing the FDIRCTRL control register with the same value.
1257 * - write 1 to bit 8 of FDIRCMD register &
1258 * - write 0 to bit 8 of FDIRCMD register
1260 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1261 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1262 IXGBE_FDIRCMD_CLEARHT));
1263 IXGBE_WRITE_FLUSH(hw);
1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1265 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1266 ~IXGBE_FDIRCMD_CLEARHT));
1267 IXGBE_WRITE_FLUSH(hw);
1269 * Clear FDIR Hash register to clear any leftover hashes
1270 * waiting to be programmed.
1272 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1273 IXGBE_WRITE_FLUSH(hw);
1275 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1276 IXGBE_WRITE_FLUSH(hw);
1278 /* Poll init-done after we write FDIRCTRL register */
1279 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1280 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1281 IXGBE_FDIRCTRL_INIT_DONE)
1285 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1286 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1287 return IXGBE_ERR_FDIR_REINIT_FAILED;
1290 /* Clear FDIR statistics registers (read to clear) */
1291 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1292 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1293 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1294 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1295 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1297 return IXGBE_SUCCESS;
1301 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1302 * @hw: pointer to hardware structure
1303 * @fdirctrl: value to write to flow director control register
1305 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1309 DEBUGFUNC("ixgbe_fdir_enable_82599");
1311 /* Prime the keys for hashing */
1312 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1313 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1316 * Poll init-done after we write the register. Estimated times:
1317 * 10G: PBALLOC = 11b, timing is 60us
1318 * 1G: PBALLOC = 11b, timing is 600us
1319 * 100M: PBALLOC = 11b, timing is 6ms
1321 * Multiple these timings by 4 if under full Rx load
1323 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1324 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1325 * this might not finish in our poll time, but we can live with that
1328 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1329 IXGBE_WRITE_FLUSH(hw);
1330 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1331 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1332 IXGBE_FDIRCTRL_INIT_DONE)
1337 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1338 DEBUGOUT("Flow Director poll time exceeded!\n");
1342 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1343 * @hw: pointer to hardware structure
1344 * @fdirctrl: value to write to flow director control register, initially
1345 * contains just the value of the Rx packet buffer allocation
1347 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1349 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1352 * Continue setup of fdirctrl register bits:
1353 * Move the flexible bytes to use the ethertype - shift 6 words
1354 * Set the maximum length per hash bucket to 0xA filters
1355 * Send interrupt when 64 filters are left
1357 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1358 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1359 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1361 /* write hashes and fdirctrl register, poll for completion */
1362 ixgbe_fdir_enable_82599(hw, fdirctrl);
1364 return IXGBE_SUCCESS;
1368 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1369 * @hw: pointer to hardware structure
1370 * @fdirctrl: value to write to flow director control register, initially
1371 * contains just the value of the Rx packet buffer allocation
1372 * @cloud_mode: true - cloud mode, false - other mode
1374 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1377 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1380 * Continue setup of fdirctrl register bits:
1381 * Turn perfect match filtering on
1382 * Report hash in RSS field of Rx wb descriptor
1383 * Initialize the drop queue to queue 127
1384 * Move the flexible bytes to use the ethertype - shift 6 words
1385 * Set the maximum length per hash bucket to 0xA filters
1386 * Send interrupt when 64 (0x4 * 16) filters are left
1388 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1389 IXGBE_FDIRCTRL_REPORT_STATUS |
1390 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1391 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1392 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1393 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1396 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1397 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1399 /* write hashes and fdirctrl register, poll for completion */
1400 ixgbe_fdir_enable_82599(hw, fdirctrl);
1402 return IXGBE_SUCCESS;
1406 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1407 * @hw: pointer to hardware structure
1408 * @dropqueue: Rx queue index used for the dropped packets
1410 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
1414 DEBUGFUNC("ixgbe_set_fdir_drop_queue_82599");
1415 /* Clear init done bit and drop queue field */
1416 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1417 fdirctrl &= ~(IXGBE_FDIRCTRL_DROP_Q_MASK | IXGBE_FDIRCTRL_INIT_DONE);
1419 /* Set drop queue */
1420 fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1421 if ((hw->mac.type == ixgbe_mac_X550) ||
1422 (hw->mac.type == ixgbe_mac_X550EM_x) ||
1423 (hw->mac.type == ixgbe_mac_X550EM_a))
1424 fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
1426 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1427 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1428 IXGBE_FDIRCMD_CLEARHT));
1429 IXGBE_WRITE_FLUSH(hw);
1430 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1431 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1432 ~IXGBE_FDIRCMD_CLEARHT));
1433 IXGBE_WRITE_FLUSH(hw);
1435 /* write hashes and fdirctrl register, poll for completion */
1436 ixgbe_fdir_enable_82599(hw, fdirctrl);
1440 * These defines allow us to quickly generate all of the necessary instructions
1441 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1442 * for values 0 through 15
1444 #define IXGBE_ATR_COMMON_HASH_KEY \
1445 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1446 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1449 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1450 common_hash ^= lo_hash_dword >> n; \
1451 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1452 bucket_hash ^= lo_hash_dword >> n; \
1453 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1454 sig_hash ^= lo_hash_dword << (16 - n); \
1455 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1456 common_hash ^= hi_hash_dword >> n; \
1457 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1458 bucket_hash ^= hi_hash_dword >> n; \
1459 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1460 sig_hash ^= hi_hash_dword << (16 - n); \
1464 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1465 * @stream: input bitstream to compute the hash on
1467 * This function is almost identical to the function above but contains
1468 * several optimizations such as unwinding all of the loops, letting the
1469 * compiler work out all of the conditional ifs since the keys are static
1470 * defines, and computing two keys at once since the hashed dword stream
1471 * will be the same for both keys.
1473 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1474 union ixgbe_atr_hash_dword common)
1476 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1477 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1479 /* record the flow_vm_vlan bits as they are a key part to the hash */
1480 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1482 /* generate common hash dword */
1483 hi_hash_dword = IXGBE_NTOHL(common.dword);
1485 /* low dword is word swapped version of common */
1486 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1488 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1489 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1491 /* Process bits 0 and 16 */
1492 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1495 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1496 * delay this because bit 0 of the stream should not be processed
1497 * so we do not add the VLAN until after bit 0 was processed
1499 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1501 /* Process remaining 30 bit of the key */
1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1510 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1518 /* combine common_hash result with signature and bucket hashes */
1519 bucket_hash ^= common_hash;
1520 bucket_hash &= IXGBE_ATR_HASH_MASK;
1522 sig_hash ^= common_hash << 16;
1523 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1525 /* return completed signature hash */
1526 return sig_hash ^ bucket_hash;
1530 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1531 * @hw: pointer to hardware structure
1532 * @input: unique input dword
1533 * @common: compressed common input dword
1534 * @queue: queue index to direct traffic to
1536 * Note that the tunnel bit in input must not be set when the hardware
1537 * tunneling support does not exist.
1539 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1540 union ixgbe_atr_hash_dword input,
1541 union ixgbe_atr_hash_dword common,
1549 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1552 * Get the flow_type in order to program FDIRCMD properly
1553 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1554 * fifth is FDIRCMD.TUNNEL_FILTER
1556 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1557 flow_type = input.formatted.flow_type &
1558 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1559 switch (flow_type) {
1560 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1561 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1562 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1563 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1564 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1565 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1568 DEBUGOUT(" Error on flow type input\n");
1572 /* configure FDIRCMD register */
1573 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1574 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1575 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1576 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1578 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1581 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1582 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1584 fdirhashcmd = (u64)fdircmd << 32;
1585 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1586 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1588 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1593 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1596 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1597 bucket_hash ^= lo_hash_dword >> n; \
1598 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1599 bucket_hash ^= hi_hash_dword >> n; \
1603 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1604 * @atr_input: input bitstream to compute the hash on
1605 * @input_mask: mask for the input bitstream
1607 * This function serves two main purposes. First it applies the input_mask
1608 * to the atr_input resulting in a cleaned up atr_input data stream.
1609 * Secondly it computes the hash and stores it in the bkt_hash field at
1610 * the end of the input byte stream. This way it will be available for
1611 * future use without needing to recompute the hash.
1613 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1614 union ixgbe_atr_input *input_mask)
1617 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1618 u32 bucket_hash = 0;
1622 /* Apply masks to input data */
1623 for (i = 0; i < 14; i++)
1624 input->dword_stream[i] &= input_mask->dword_stream[i];
1626 /* record the flow_vm_vlan bits as they are a key part to the hash */
1627 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1629 /* generate common hash dword */
1630 for (i = 1; i <= 13; i++)
1631 hi_dword ^= input->dword_stream[i];
1632 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1634 /* low dword is word swapped version of common */
1635 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1637 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1638 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1640 /* Process bits 0 and 16 */
1641 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1644 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1645 * delay this because bit 0 of the stream should not be processed
1646 * so we do not add the VLAN until after bit 0 was processed
1648 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1650 /* Process remaining 30 bit of the key */
1651 for (i = 1; i <= 15; i++)
1652 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1655 * Limit hash to 13 bits since max bucket count is 8K.
1656 * Store result at the end of the input stream.
1658 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1662 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1663 * @input_mask: mask to be bit swapped
1665 * The source and destination port masks for flow director are bit swapped
1666 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1667 * generate a correctly swapped value we need to bit swap the mask and that
1668 * is what is accomplished by this function.
1670 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1672 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1673 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1674 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1675 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1676 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1677 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1678 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1682 * These two macros are meant to address the fact that we have registers
1683 * that are either all or in part big-endian. As a result on big-endian
1684 * systems we will end up byte swapping the value to little-endian before
1685 * it is byte swapped again and written to the hardware in the original
1686 * big-endian format.
1688 #define IXGBE_STORE_AS_BE32(_value) \
1689 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1690 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1692 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1693 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1695 #define IXGBE_STORE_AS_BE16(_value) \
1696 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1698 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1699 union ixgbe_atr_input *input_mask, bool cloud_mode)
1701 /* mask IPv6 since it is currently not supported */
1702 u32 fdirm = IXGBE_FDIRM_DIPv6;
1705 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1708 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1709 * are zero, then assume a full mask for that field. Also assume that
1710 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1711 * cannot be masked out in this implementation.
1713 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1717 /* verify bucket hash is cleared on hash generation */
1718 if (input_mask->formatted.bkt_hash)
1719 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1721 /* Program FDIRM and verify partial masks */
1722 switch (input_mask->formatted.vm_pool & 0x7F) {
1724 fdirm |= IXGBE_FDIRM_POOL;
1728 DEBUGOUT(" Error on vm pool mask\n");
1729 return IXGBE_ERR_CONFIG;
1732 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1734 fdirm |= IXGBE_FDIRM_L4P;
1735 if (input_mask->formatted.dst_port ||
1736 input_mask->formatted.src_port) {
1737 DEBUGOUT(" Error on src/dst port mask\n");
1738 return IXGBE_ERR_CONFIG;
1740 case IXGBE_ATR_L4TYPE_MASK:
1743 DEBUGOUT(" Error on flow type mask\n");
1744 return IXGBE_ERR_CONFIG;
1747 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1749 /* mask VLAN ID, fall through to mask VLAN priority */
1750 fdirm |= IXGBE_FDIRM_VLANID;
1752 /* mask VLAN priority */
1753 fdirm |= IXGBE_FDIRM_VLANP;
1756 /* mask VLAN ID only, fall through */
1757 fdirm |= IXGBE_FDIRM_VLANID;
1759 /* no VLAN fields masked */
1762 DEBUGOUT(" Error on VLAN mask\n");
1763 return IXGBE_ERR_CONFIG;
1766 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1768 /* Mask Flex Bytes, fall through */
1769 fdirm |= IXGBE_FDIRM_FLEX;
1773 DEBUGOUT(" Error on flexible byte mask\n");
1774 return IXGBE_ERR_CONFIG;
1778 fdirm |= IXGBE_FDIRM_L3P;
1779 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1780 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1782 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1784 /* Mask inner MAC, fall through */
1785 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1789 DEBUGOUT(" Error on inner_mac byte mask\n");
1790 return IXGBE_ERR_CONFIG;
1793 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1796 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1799 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1804 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1805 return IXGBE_ERR_CONFIG;
1808 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1810 /* Mask turnnel type, fall through */
1811 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1815 DEBUGOUT(" Error on tunnel type byte mask\n");
1816 return IXGBE_ERR_CONFIG;
1818 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1820 /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
1821 * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
1822 * L3/L3 packets to tunnel.
1824 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
1825 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
1826 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
1827 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
1828 switch (hw->mac.type) {
1829 case ixgbe_mac_X550:
1830 case ixgbe_mac_X550EM_x:
1831 case ixgbe_mac_X550EM_a:
1832 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
1839 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1840 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1843 /* store the TCP/UDP port masks, bit reversed from port
1845 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1847 /* write both the same so that UDP and TCP use the same mask */
1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1849 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1850 /* also use it for SCTP */
1851 switch (hw->mac.type) {
1852 case ixgbe_mac_X550:
1853 case ixgbe_mac_X550EM_x:
1854 case ixgbe_mac_X550EM_a:
1855 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1861 /* store source and destination IP masks (big-enian) */
1862 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1863 ~input_mask->formatted.src_ip[0]);
1864 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1865 ~input_mask->formatted.dst_ip[0]);
1867 return IXGBE_SUCCESS;
1870 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1871 union ixgbe_atr_input *input,
1872 u16 soft_id, u8 queue, bool cloud_mode)
1874 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1875 u32 addr_low, addr_high;
1879 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1881 /* currently IPv6 is not supported, must be programmed with 0 */
1882 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1883 input->formatted.src_ip[0]);
1884 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1885 input->formatted.src_ip[1]);
1886 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1887 input->formatted.src_ip[2]);
1889 /* record the source address (big-endian) */
1890 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,
1891 input->formatted.src_ip[0]);
1893 /* record the first 32 bits of the destination address
1895 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,
1896 input->formatted.dst_ip[0]);
1898 /* record source and destination port (little-endian)*/
1899 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1900 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1901 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1902 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1905 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1906 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1907 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1908 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1909 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1912 if (input->formatted.tunnel_type != 0)
1913 cloud_type = 0x80000000;
1915 addr_low = ((u32)input->formatted.inner_mac[0] |
1916 ((u32)input->formatted.inner_mac[1] << 8) |
1917 ((u32)input->formatted.inner_mac[2] << 16) |
1918 ((u32)input->formatted.inner_mac[3] << 24));
1919 addr_high = ((u32)input->formatted.inner_mac[4] |
1920 ((u32)input->formatted.inner_mac[5] << 8));
1921 cloud_type |= addr_high;
1922 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1923 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1924 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1927 /* configure FDIRHASH register */
1928 fdirhash = input->formatted.bkt_hash;
1929 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1930 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1933 * flush all previous writes to make certain registers are
1934 * programmed prior to issuing the command
1936 IXGBE_WRITE_FLUSH(hw);
1938 /* configure FDIRCMD register */
1939 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1940 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1941 if (queue == IXGBE_FDIR_DROP_QUEUE)
1942 fdircmd |= IXGBE_FDIRCMD_DROP;
1943 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1944 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1945 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1946 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1947 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1949 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1950 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1952 DEBUGOUT("Flow Director command did not complete!\n");
1956 return IXGBE_SUCCESS;
1959 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1960 union ixgbe_atr_input *input,
1967 /* configure FDIRHASH register */
1968 fdirhash = input->formatted.bkt_hash;
1969 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1970 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1972 /* flush hash to HW */
1973 IXGBE_WRITE_FLUSH(hw);
1975 /* Query if filter is present */
1976 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1978 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1980 DEBUGOUT("Flow Director command did not complete!\n");
1984 /* if filter exists in hardware then remove it */
1985 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1986 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1987 IXGBE_WRITE_FLUSH(hw);
1988 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1989 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1992 return IXGBE_SUCCESS;
1996 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1997 * @hw: pointer to hardware structure
1998 * @input: input bitstream
1999 * @input_mask: mask for the input bitstream
2000 * @soft_id: software index for the filters
2001 * @queue: queue index to direct traffic to
2003 * Note that the caller to this function must lock before calling, since the
2004 * hardware writes must be protected from one another.
2006 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2007 union ixgbe_atr_input *input,
2008 union ixgbe_atr_input *input_mask,
2009 u16 soft_id, u8 queue, bool cloud_mode)
2011 s32 err = IXGBE_ERR_CONFIG;
2013 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
2016 * Check flow_type formatting, and bail out before we touch the hardware
2017 * if there's a configuration issue
2019 switch (input->formatted.flow_type) {
2020 case IXGBE_ATR_FLOW_TYPE_IPV4:
2021 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2022 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2023 if (input->formatted.dst_port || input->formatted.src_port) {
2024 DEBUGOUT(" Error on src/dst port\n");
2025 return IXGBE_ERR_CONFIG;
2028 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2029 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2030 if (input->formatted.dst_port || input->formatted.src_port) {
2031 DEBUGOUT(" Error on src/dst port\n");
2032 return IXGBE_ERR_CONFIG;
2034 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2035 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2036 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2037 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2038 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2039 IXGBE_ATR_L4TYPE_MASK;
2042 DEBUGOUT(" Error on flow type input\n");
2046 /* program input mask into the HW */
2047 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2051 /* apply mask and compute/store hash */
2052 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2054 /* program filters to filter memory */
2055 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2056 soft_id, queue, cloud_mode);
2060 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2061 * @hw: pointer to hardware structure
2062 * @reg: analog register to read
2065 * Performs read operation to Omer analog register specified.
2067 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2071 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2073 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2075 IXGBE_WRITE_FLUSH(hw);
2077 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2078 *val = (u8)core_ctl;
2080 return IXGBE_SUCCESS;
2084 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2085 * @hw: pointer to hardware structure
2086 * @reg: atlas register to write
2087 * @val: value to write
2089 * Performs write operation to Omer analog register specified.
2091 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2095 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2097 core_ctl = (reg << 8) | val;
2098 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2099 IXGBE_WRITE_FLUSH(hw);
2102 return IXGBE_SUCCESS;
2106 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2107 * @hw: pointer to hardware structure
2109 * Starts the hardware using the generic start_hw function
2110 * and the generation start_hw function.
2111 * Then performs revision-specific operations, if any.
2113 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2115 s32 ret_val = IXGBE_SUCCESS;
2117 DEBUGFUNC("ixgbe_start_hw_82599");
2119 ret_val = ixgbe_start_hw_generic(hw);
2120 if (ret_val != IXGBE_SUCCESS)
2123 ret_val = ixgbe_start_hw_gen2(hw);
2124 if (ret_val != IXGBE_SUCCESS)
2127 /* We need to run link autotry after the driver loads */
2128 hw->mac.autotry_restart = true;
2130 if (ret_val == IXGBE_SUCCESS)
2131 ret_val = ixgbe_verify_fw_version_82599(hw);
2137 * ixgbe_identify_phy_82599 - Get physical layer module
2138 * @hw: pointer to hardware structure
2140 * Determines the physical layer module found on the current adapter.
2141 * If PHY already detected, maintains current PHY type in hw struct,
2142 * otherwise executes the PHY detection routine.
2144 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2148 DEBUGFUNC("ixgbe_identify_phy_82599");
2150 /* Detect PHY if not unknown - returns success if already detected. */
2151 status = ixgbe_identify_phy_generic(hw);
2152 if (status != IXGBE_SUCCESS) {
2153 /* 82599 10GBASE-T requires an external PHY */
2154 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2157 status = ixgbe_identify_module_generic(hw);
2160 /* Set PHY type none if no PHY detected */
2161 if (hw->phy.type == ixgbe_phy_unknown) {
2162 hw->phy.type = ixgbe_phy_none;
2163 return IXGBE_SUCCESS;
2166 /* Return error if SFP module has been detected but is not supported */
2167 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2168 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2174 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2175 * @hw: pointer to hardware structure
2177 * Determines physical layer capabilities of the current configuration.
2179 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2181 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2182 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2183 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2184 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2185 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2186 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2187 u16 ext_ability = 0;
2189 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2191 hw->phy.ops.identify(hw);
2193 switch (hw->phy.type) {
2195 case ixgbe_phy_cu_unknown:
2196 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2197 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2198 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2199 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2200 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2201 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2202 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2203 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2209 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2210 case IXGBE_AUTOC_LMS_1G_AN:
2211 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2212 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2213 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2214 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2217 /* SFI mode so read SFP module */
2220 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2221 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2222 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2223 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2224 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2225 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2226 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2229 case IXGBE_AUTOC_LMS_10G_SERIAL:
2230 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2231 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2233 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2236 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2237 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2238 if (autoc & IXGBE_AUTOC_KX_SUPP)
2239 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2240 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2241 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2242 if (autoc & IXGBE_AUTOC_KR_SUPP)
2243 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2252 /* SFP check must be done last since DA modules are sometimes used to
2253 * test KR mode - we need to id KR mode correctly before SFP module.
2254 * Call identify_sfp because the pluggable module may have changed */
2255 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2257 return physical_layer;
2261 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2262 * @hw: pointer to hardware structure
2263 * @regval: register value to write to RXCTRL
2265 * Enables the Rx DMA unit for 82599
2267 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2270 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2273 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2274 * If traffic is incoming before we enable the Rx unit, it could hang
2275 * the Rx DMA unit. Therefore, make sure the security engine is
2276 * completely disabled prior to enabling the Rx unit.
2279 hw->mac.ops.disable_sec_rx_path(hw);
2281 if (regval & IXGBE_RXCTRL_RXEN)
2282 ixgbe_enable_rx(hw);
2284 ixgbe_disable_rx(hw);
2286 hw->mac.ops.enable_sec_rx_path(hw);
2288 return IXGBE_SUCCESS;
2292 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2293 * @hw: pointer to hardware structure
2295 * Verifies that installed the firmware version is 0.6 or higher
2296 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2298 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2299 * if the FW version is not supported.
2301 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2303 s32 status = IXGBE_ERR_EEPROM_VERSION;
2304 u16 fw_offset, fw_ptp_cfg_offset;
2307 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2309 /* firmware check is only necessary for SFI devices */
2310 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2311 status = IXGBE_SUCCESS;
2312 goto fw_version_out;
2315 /* get the offset to the Firmware Module block */
2316 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2317 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2318 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2319 return IXGBE_ERR_EEPROM_VERSION;
2322 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2323 goto fw_version_out;
2325 /* get the offset to the Pass Through Patch Configuration block */
2326 if (hw->eeprom.ops.read(hw, (fw_offset +
2327 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2328 &fw_ptp_cfg_offset)) {
2329 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2330 "eeprom read at offset %d failed",
2332 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2333 return IXGBE_ERR_EEPROM_VERSION;
2336 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2337 goto fw_version_out;
2339 /* get the firmware version */
2340 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2341 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2342 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2343 "eeprom read at offset %d failed",
2344 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2345 return IXGBE_ERR_EEPROM_VERSION;
2348 if (fw_version > 0x5)
2349 status = IXGBE_SUCCESS;
2356 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2357 * @hw: pointer to hardware structure
2359 * Returns true if the LESM FW module is present and enabled. Otherwise
2360 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2362 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2364 bool lesm_enabled = false;
2365 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2368 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2370 /* get the offset to the Firmware Module block */
2371 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2373 if ((status != IXGBE_SUCCESS) ||
2374 (fw_offset == 0) || (fw_offset == 0xFFFF))
2377 /* get the offset to the LESM Parameters block */
2378 status = hw->eeprom.ops.read(hw, (fw_offset +
2379 IXGBE_FW_LESM_PARAMETERS_PTR),
2380 &fw_lesm_param_offset);
2382 if ((status != IXGBE_SUCCESS) ||
2383 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2386 /* get the LESM state word */
2387 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2388 IXGBE_FW_LESM_STATE_1),
2391 if ((status == IXGBE_SUCCESS) &&
2392 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2393 lesm_enabled = true;
2396 return lesm_enabled;
2400 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2401 * fastest available method
2403 * @hw: pointer to hardware structure
2404 * @offset: offset of word in EEPROM to read
2405 * @words: number of words
2406 * @data: word(s) read from the EEPROM
2408 * Retrieves 16 bit word(s) read from EEPROM
2410 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2411 u16 words, u16 *data)
2413 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2414 s32 ret_val = IXGBE_ERR_CONFIG;
2416 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2419 * If EEPROM is detected and can be addressed using 14 bits,
2420 * use EERD otherwise use bit bang
2422 if ((eeprom->type == ixgbe_eeprom_spi) &&
2423 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2424 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2427 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2435 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2436 * fastest available method
2438 * @hw: pointer to hardware structure
2439 * @offset: offset of word in the EEPROM to read
2440 * @data: word read from the EEPROM
2442 * Reads a 16 bit word from the EEPROM
2444 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2445 u16 offset, u16 *data)
2447 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2448 s32 ret_val = IXGBE_ERR_CONFIG;
2450 DEBUGFUNC("ixgbe_read_eeprom_82599");
2453 * If EEPROM is detected and can be addressed using 14 bits,
2454 * use EERD otherwise use bit bang
2456 if ((eeprom->type == ixgbe_eeprom_spi) &&
2457 (offset <= IXGBE_EERD_MAX_ADDR))
2458 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2460 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2466 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2468 * @hw: pointer to hardware structure
2470 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2471 * full pipeline reset. This function assumes the SW/FW lock is held.
2473 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2477 u32 i, autoc_reg, autoc2_reg;
2479 /* Enable link if disabled in NVM */
2480 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2481 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2482 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2483 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2484 IXGBE_WRITE_FLUSH(hw);
2487 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2488 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2489 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2490 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2491 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2492 /* Wait for AN to leave state 0 */
2493 for (i = 0; i < 10; i++) {
2495 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2496 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2500 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2501 DEBUGOUT("auto negotiation not completed\n");
2502 ret_val = IXGBE_ERR_RESET_FAILED;
2503 goto reset_pipeline_out;
2506 ret_val = IXGBE_SUCCESS;
2509 /* Write AUTOC register with original LMS field and Restart_AN */
2510 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2511 IXGBE_WRITE_FLUSH(hw);
2517 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2518 * @hw: pointer to hardware structure
2519 * @byte_offset: byte offset to read
2522 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2523 * a specified device address.
2525 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2526 u8 dev_addr, u8 *data)
2532 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2534 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2535 /* Acquire I2C bus ownership. */
2536 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2537 esdp |= IXGBE_ESDP_SDP0;
2538 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2539 IXGBE_WRITE_FLUSH(hw);
2542 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2543 if (esdp & IXGBE_ESDP_SDP1)
2551 DEBUGOUT("Driver can't access resource,"
2552 " acquiring I2C bus timeout.\n");
2553 status = IXGBE_ERR_I2C;
2554 goto release_i2c_access;
2558 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2562 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2563 /* Release I2C bus ownership. */
2564 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2565 esdp &= ~IXGBE_ESDP_SDP0;
2566 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2567 IXGBE_WRITE_FLUSH(hw);
2574 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2575 * @hw: pointer to hardware structure
2576 * @byte_offset: byte offset to write
2577 * @data: value to write
2579 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2580 * a specified device address.
2582 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2583 u8 dev_addr, u8 data)
2589 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2591 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2592 /* Acquire I2C bus ownership. */
2593 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2594 esdp |= IXGBE_ESDP_SDP0;
2595 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2596 IXGBE_WRITE_FLUSH(hw);
2599 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2600 if (esdp & IXGBE_ESDP_SDP1)
2608 DEBUGOUT("Driver can't access resource,"
2609 " acquiring I2C bus timeout.\n");
2610 status = IXGBE_ERR_I2C;
2611 goto release_i2c_access;
2615 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2619 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2620 /* Release I2C bus ownership. */
2621 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2622 esdp &= ~IXGBE_ESDP_SDP0;
2623 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2624 IXGBE_WRITE_FLUSH(hw);