drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  *  ixgbe_identify_phy_generic - Get physical layer module
 287  *  @hw: pointer to hardware structure
 288  *
 289  *  Determines the physical layer module found on the current adapter.
 290  **/
 291 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 292 {
 293         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 294         u32 phy_addr;
 295         u16 ext_ability = 0;
 296
 297         DEBUGFUNC("ixgbe_identify_phy_generic");
 298
 299         if (!hw->phy.phy_semaphore_mask) {
 300                 if (hw->bus.lan_id)
 301                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 302                 else
 303                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 304         }
 305
 306         if (hw->phy.type == ixgbe_phy_unknown) {
 307                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 308                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 309                                 hw->phy.addr = phy_addr;
 310                                 ixgbe_get_phy_id(hw);
 311                                 hw->phy.type =
 312                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 313
 314                                 if (hw->phy.type == ixgbe_phy_unknown) {
 315                                         hw->phy.ops.read_reg(hw,
 316                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 317                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 318                                                   &ext_ability);
 319                                         if (ext_ability &
 320                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 321                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 322                                                 hw->phy.type =
 323                                                          ixgbe_phy_cu_unknown;
 324                                         else
 325                                                 hw->phy.type =
 326                                                          ixgbe_phy_generic;
 327                                 }
 328
 329                                 status = IXGBE_SUCCESS;
 330                                 break;
 331                         }
 332                 }
 333
 334                 /* Certain media types do not have a phy so an address will not
 335                  * be found and the code will take this path.  Caller has to
 336                  * decide if it is an error or not.
 337                  */
 338                 if (status != IXGBE_SUCCESS) {
 339                         hw->phy.addr = 0;
 340                 }
 341         } else {
 342                 status = IXGBE_SUCCESS;
 343         }
 344
 345         return status;
 346 }
 347
 348 /**
 349  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 350  * @hw: pointer to the hardware structure
 351  *
 352  * This function checks the MMNGC.MNG_VETO bit to see if there are
 353  * any constraints on link from manageability.  For MAC's that don't
 354  * have this bit just return faluse since the link can not be blocked
 355  * via this method.
 356  **/
 357 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 358 {
 359         u32 mmngc;
 360
 361         DEBUGFUNC("ixgbe_check_reset_blocked");
 362
 363         /* If we don't have this bit, it can't be blocking */
 364         if (hw->mac.type == ixgbe_mac_82598EB)
 365                 return false;
 366
 367         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 368         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 369                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 370                               "MNG_VETO bit detected.\n");
 371                 return true;
 372         }
 373
 374         return false;
 375 }
 376
 377 /**
 378  *  ixgbe_validate_phy_addr - Determines phy address is valid
 379  *  @hw: pointer to hardware structure
 380  *
 381  **/
 382 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 383 {
 384         u16 phy_id = 0;
 385         bool valid = false;
 386
 387         DEBUGFUNC("ixgbe_validate_phy_addr");
 388
 389         hw->phy.addr = phy_addr;
 390         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 391                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 392
 393         if (phy_id != 0xFFFF && phy_id != 0x0)
 394                 valid = true;
 395
 396         return valid;
 397 }
 398
 399 /**
 400  *  ixgbe_get_phy_id - Get the phy type
 401  *  @hw: pointer to hardware structure
 402  *
 403  **/
 404 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 405 {
 406         u32 status;
 407         u16 phy_id_high = 0;
 408         u16 phy_id_low = 0;
 409
 410         DEBUGFUNC("ixgbe_get_phy_id");
 411
 412         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 413                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 414                                       &phy_id_high);
 415
 416         if (status == IXGBE_SUCCESS) {
 417                 hw->phy.id = (u32)(phy_id_high << 16);
 418                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 419                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 420                                               &phy_id_low);
 421                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 422                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 423         }
 424         return status;
 425 }
 426
 427 /**
 428  *  ixgbe_get_phy_type_from_id - Get the phy type
 429  *  @phy_id: PHY ID information
 430  *
 431  **/
 432 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 433 {
 434         enum ixgbe_phy_type phy_type;
 435
 436         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 437
 438         switch (phy_id) {
 439         case TN1010_PHY_ID:
 440                 phy_type = ixgbe_phy_tn;
 441                 break;
 442         case X550_PHY_ID1:
 443         case X550_PHY_ID2:
 444         case X550_PHY_ID3:
 445         case X540_PHY_ID:
 446                 phy_type = ixgbe_phy_aq;
 447                 break;
 448         case QT2022_PHY_ID:
 449                 phy_type = ixgbe_phy_qt;
 450                 break;
 451         case ATH_PHY_ID:
 452                 phy_type = ixgbe_phy_nl;
 453                 break;
 454         case X557_PHY_ID:
 455                 phy_type = ixgbe_phy_x550em_ext_t;
 456                 break;
 457         default:
 458                 phy_type = ixgbe_phy_unknown;
 459                 break;
 460         }
 461         return phy_type;
 462 }
 463
 464 /**
 465  *  ixgbe_reset_phy_generic - Performs a PHY reset
 466  *  @hw: pointer to hardware structure
 467  **/
 468 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 469 {
 470         u32 i;
 471         u16 ctrl = 0;
 472         s32 status = IXGBE_SUCCESS;
 473
 474         DEBUGFUNC("ixgbe_reset_phy_generic");
 475
 476         if (hw->phy.type == ixgbe_phy_unknown)
 477                 status = ixgbe_identify_phy_generic(hw);
 478
 479         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 480                 goto out;
 481
 482         /* Don't reset PHY if it's shut down due to overtemp. */
 483         if (!hw->phy.reset_if_overtemp &&
 484             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 485                 goto out;
 486
 487         /* Blocked by MNG FW so bail */
 488         if (ixgbe_check_reset_blocked(hw))
 489                 goto out;
 490
 491         /*
 492          * Perform soft PHY reset to the PHY_XS.
 493          * This will cause a soft reset to the PHY
 494          */
 495         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 496                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 497                               IXGBE_MDIO_PHY_XS_RESET);
 498
 499         /*
 500          * Poll for reset bit to self-clear indicating reset is complete.
 501          * Some PHYs could take up to 3 seconds to complete and need about
 502          * 1.7 usec delay after the reset is complete.
 503          */
 504         for (i = 0; i < 30; i++) {
 505                 msec_delay(100);
 506                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 507                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 508                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 509                         usec_delay(2);
 510                         break;
 511                 }
 512         }
 513
 514         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 515                 status = IXGBE_ERR_RESET_FAILED;
 516                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 517                              "PHY reset polling failed to complete.\n");
 518         }
 519
 520 out:
 521         return status;
 522 }
 523
 524 /**
 525  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 526  *  the SWFW lock
 527  *  @hw: pointer to hardware structure
 528  *  @reg_addr: 32 bit address of PHY register to read
 529  *  @phy_data: Pointer to read data from PHY register
 530  **/
 531 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 532                        u16 *phy_data)
 533 {
 534         u32 i, data, command;
 535
 536         /* Setup and write the address cycle command */
 537         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 538                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 539                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 540                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 541
 542         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 543
 544         /*
 545          * Check every 10 usec to see if the address cycle completed.
 546          * The MDI Command bit will clear when the operation is
 547          * complete
 548          */
 549         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 550                 usec_delay(10);
 551
 552                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 553                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 554                                 break;
 555         }
 556
 557
 558         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 559                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 560                 return IXGBE_ERR_PHY;
 561         }
 562
 563         /*
 564          * Address cycle complete, setup and write the read
 565          * command
 566          */
 567         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 568                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 569                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 570                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 571
 572         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 573
 574         /*
 575          * Check every 10 usec to see if the address cycle
 576          * completed. The MDI Command bit will clear when the
 577          * operation is complete
 578          */
 579         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 580                 usec_delay(10);
 581
 582                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 583                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 584                         break;
 585         }
 586
 587         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 588                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 589                 return IXGBE_ERR_PHY;
 590         }
 591
 592         /*
 593          * Read operation is complete.  Get the data
 594          * from MSRWD
 595          */
 596         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 597         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 598         *phy_data = (u16)(data);
 599
 600         return IXGBE_SUCCESS;
 601 }
 602
 603 /**
 604  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 605  *  using the SWFW lock - this function is needed in most cases
 606  *  @hw: pointer to hardware structure
 607  *  @reg_addr: 32 bit address of PHY register to read
 608  *  @phy_data: Pointer to read data from PHY register
 609  **/
 610 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 611                                u32 device_type, u16 *phy_data)
 612 {
 613         s32 status;
 614         u32 gssr = hw->phy.phy_semaphore_mask;
 615
 616         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 617
 618         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 619                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 620                                                 phy_data);
 621                 hw->mac.ops.release_swfw_sync(hw, gssr);
 622         } else {
 623                 status = IXGBE_ERR_SWFW_SYNC;
 624         }
 625
 626         return status;
 627 }
 628
 629 /**
 630  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 631  *  without SWFW lock
 632  *  @hw: pointer to hardware structure
 633  *  @reg_addr: 32 bit PHY register to write
 634  *  @device_type: 5 bit device type
 635  *  @phy_data: Data to write to the PHY register
 636  **/
 637 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 638                                 u32 device_type, u16 phy_data)
 639 {
 640         u32 i, command;
 641
 642         /* Put the data in the MDI single read and write data register*/
 643         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 644
 645         /* Setup and write the address cycle command */
 646         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 647                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 648                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 649                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 650
 651         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 652
 653         /*
 654          * Check every 10 usec to see if the address cycle completed.
 655          * The MDI Command bit will clear when the operation is
 656          * complete
 657          */
 658         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 659                 usec_delay(10);
 660
 661                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 662                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 663                         break;
 664         }
 665
 666         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 667                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 668                 return IXGBE_ERR_PHY;
 669         }
 670
 671         /*
 672          * Address cycle complete, setup and write the write
 673          * command
 674          */
 675         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 676                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 677                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 678                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 679
 680         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 681
 682         /*
 683          * Check every 10 usec to see if the address cycle
 684          * completed. The MDI Command bit will clear when the
 685          * operation is complete
 686          */
 687         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 688                 usec_delay(10);
 689
 690                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 691                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 692                         break;
 693         }
 694
 695         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 696                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 697                 return IXGBE_ERR_PHY;
 698         }
 699
 700         return IXGBE_SUCCESS;
 701 }
 702
 703 /**
 704  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 705  *  using SWFW lock- this function is needed in most cases
 706  *  @hw: pointer to hardware structure
 707  *  @reg_addr: 32 bit PHY register to write
 708  *  @device_type: 5 bit device type
 709  *  @phy_data: Data to write to the PHY register
 710  **/
 711 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 712                                 u32 device_type, u16 phy_data)
 713 {
 714         s32 status;
 715         u32 gssr = hw->phy.phy_semaphore_mask;
 716
 717         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 718
 719         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 720                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 721                                                  phy_data);
 722                 hw->mac.ops.release_swfw_sync(hw, gssr);
 723         } else {
 724                 status = IXGBE_ERR_SWFW_SYNC;
 725         }
 726
 727         return status;
 728 }
 729
 730 /**
 731  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 732  *  @hw: pointer to hardware structure
 733  *
 734  *  Restart auto-negotiation and PHY and waits for completion.
 735  **/
 736 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 737 {
 738         s32 status = IXGBE_SUCCESS;
 739         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 740         bool autoneg = false;
 741         ixgbe_link_speed speed;
 742
 743         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 744
 745         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 746
 747         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 748                 /* Set or unset auto-negotiation 10G advertisement */
 749                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 750                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 751                                      &autoneg_reg);
 752
 753                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 754                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 755                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 756
 757                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 758                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 759                                       autoneg_reg);
 760         }
 761
 762         if (hw->mac.type == ixgbe_mac_X550) {
 763                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 764                         /* Set or unset auto-negotiation 5G advertisement */
 765                         hw->phy.ops.read_reg(hw,
 766                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 767                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 768                                 &autoneg_reg);
 769
 770                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 771                         if (hw->phy.autoneg_advertised &
 772                              IXGBE_LINK_SPEED_5GB_FULL)
 773                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 774
 775                         hw->phy.ops.write_reg(hw,
 776                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 777                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 778                                 autoneg_reg);
 779                 }
 780
 781                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 782                         /* Set or unset auto-negotiation 2.5G advertisement */
 783                         hw->phy.ops.read_reg(hw,
 784                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 785                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 786                                 &autoneg_reg);
 787
 788                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 789                         if (hw->phy.autoneg_advertised &
 790                             IXGBE_LINK_SPEED_2_5GB_FULL)
 791                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 792
 793                         hw->phy.ops.write_reg(hw,
 794                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 795                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 796                                 autoneg_reg);
 797                 }
 798         }
 799
 800         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 801                 /* Set or unset auto-negotiation 1G advertisement */
 802                 hw->phy.ops.read_reg(hw,
 803                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 804                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 805                                      &autoneg_reg);
 806
 807                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 808                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 809                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 810
 811                 hw->phy.ops.write_reg(hw,
 812                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 813                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 814                                       autoneg_reg);
 815         }
 816
 817         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 818                 /* Set or unset auto-negotiation 100M advertisement */
 819                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 820                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 821                                      &autoneg_reg);
 822
 823                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 824                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 825                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 826                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 827
 828                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 829                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 830                                       autoneg_reg);
 831         }
 832
 833         /* Blocked by MNG FW so don't reset PHY */
 834         if (ixgbe_check_reset_blocked(hw))
 835                 return status;
 836
 837         /* Restart PHY auto-negotiation. */
 838         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 839                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 840
 841         autoneg_reg |= IXGBE_MII_RESTART;
 842
 843         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 844                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 845
 846         return status;
 847 }
 848
 849 /**
 850  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 851  *  @hw: pointer to hardware structure
 852  *  @speed: new link speed
 853  **/
 854 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 855                                        ixgbe_link_speed speed,
 856                                        bool autoneg_wait_to_complete)
 857 {
 858         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 859
 860         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 861
 862         /*
 863          * Clear autoneg_advertised and set new values based on input link
 864          * speed.
 865          */
 866         hw->phy.autoneg_advertised = 0;
 867
 868         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 869                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 870
 871         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 872                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 873
 874         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 875                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 876
 877         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 878                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 879
 880         if (speed & IXGBE_LINK_SPEED_100_FULL)
 881                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 882
 883         /* Setup link based on the new speed settings */
 884         ixgbe_setup_phy_link(hw);
 885
 886         return IXGBE_SUCCESS;
 887 }
 888
 889 /**
 890  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 891  * @hw: pointer to hardware structure
 892  *
 893  * Determines the supported link capabilities by reading the PHY auto
 894  * negotiation register.
 895  **/
 896 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 897 {
 898         s32 status;
 899         u16 speed_ability;
 900
 901         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 902                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 903                                       &speed_ability);
 904         if (status)
 905                 return status;
 906
 907         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 908                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 909         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 910                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 911         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 912                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 913
 914         switch (hw->mac.type) {
 915         case ixgbe_mac_X550:
 916                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 917                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 918                 break;
 919         case ixgbe_mac_X550EM_x:
 920                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 921                 break;
 922         default:
 923                 break;
 924         }
 925
 926         return status;
 927 }
 928
 929 /**
 930  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 931  *  @hw: pointer to hardware structure
 932  *  @speed: pointer to link speed
 933  *  @autoneg: boolean auto-negotiation value
 934  **/
 935 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 936                                                ixgbe_link_speed *speed,
 937                                                bool *autoneg)
 938 {
 939         s32 status = IXGBE_SUCCESS;
 940
 941         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 942
 943         *autoneg = true;
 944         if (!hw->phy.speeds_supported)
 945                 status = ixgbe_get_copper_speeds_supported(hw);
 946
 947         *speed = hw->phy.speeds_supported;
 948         return status;
 949 }
 950
 951 /**
 952  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 953  *  @hw: pointer to hardware structure
 954  *
 955  *  Reads the VS1 register to determine if link is up and the current speed for
 956  *  the PHY.
 957  **/
 958 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 959                              bool *link_up)
 960 {
 961         s32 status = IXGBE_SUCCESS;
 962         u32 time_out;
 963         u32 max_time_out = 10;
 964         u16 phy_link = 0;
 965         u16 phy_speed = 0;
 966         u16 phy_data = 0;
 967
 968         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 969
 970         /* Initialize speed and link to default case */
 971         *link_up = false;
 972         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 973
 974         /*
 975          * Check current speed and link status of the PHY register.
 976          * This is a vendor specific register and may have to
 977          * be changed for other copper PHYs.
 978          */
 979         for (time_out = 0; time_out < max_time_out; time_out++) {
 980                 usec_delay(10);
 981                 status = hw->phy.ops.read_reg(hw,
 982                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 983                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 984                                         &phy_data);
 985                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 986                 phy_speed = phy_data &
 987                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 988                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 989                         *link_up = true;
 990                         if (phy_speed ==
 991                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 992                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 993                         break;
 994                 }
 995         }
 996
 997         return status;
 998 }
 999
1000 /**
1001  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1002  *      @hw: pointer to hardware structure
1003  *
1004  *      Restart auto-negotiation and PHY and waits for completion.
1005  **/
1006 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1007 {
1008         s32 status = IXGBE_SUCCESS;
1009         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1010         bool autoneg = false;
1011         ixgbe_link_speed speed;
1012
1013         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1014
1015         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1016
1017         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1018                 /* Set or unset auto-negotiation 10G advertisement */
1019                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1020                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1021                                      &autoneg_reg);
1022
1023                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1024                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1025                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1026
1027                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1028                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1029                                       autoneg_reg);
1030         }
1031
1032         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1033                 /* Set or unset auto-negotiation 1G advertisement */
1034                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1035                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1036                                      &autoneg_reg);
1037
1038                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1039                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1040                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1041
1042                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1043                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1044                                       autoneg_reg);
1045         }
1046
1047         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1048                 /* Set or unset auto-negotiation 100M advertisement */
1049                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1050                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1051                                      &autoneg_reg);
1052
1053                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1054                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1055                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1056
1057                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1058                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1059                                       autoneg_reg);
1060         }
1061
1062         /* Blocked by MNG FW so don't reset PHY */
1063         if (ixgbe_check_reset_blocked(hw))
1064                 return status;
1065
1066         /* Restart PHY auto-negotiation. */
1067         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1068                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1069
1070         autoneg_reg |= IXGBE_MII_RESTART;
1071
1072         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1073                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1074
1075         return status;
1076 }
1077
1078 /**
1079  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1080  *  @hw: pointer to hardware structure
1081  *  @firmware_version: pointer to the PHY Firmware Version
1082  **/
1083 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1084                                        u16 *firmware_version)
1085 {
1086         s32 status;
1087
1088         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1089
1090         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1091                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1092                                       firmware_version);
1093
1094         return status;
1095 }
1096
1097 /**
1098  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1099  *  @hw: pointer to hardware structure
1100  *  @firmware_version: pointer to the PHY Firmware Version
1101  **/
1102 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1103                                            u16 *firmware_version)
1104 {
1105         s32 status;
1106
1107         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1108
1109         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1110                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1111                                       firmware_version);
1112
1113         return status;
1114 }
1115
1116 /**
1117  *  ixgbe_reset_phy_nl - Performs a PHY reset
1118  *  @hw: pointer to hardware structure
1119  **/
1120 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1121 {
1122         u16 phy_offset, control, eword, edata, block_crc;
1123         bool end_data = false;
1124         u16 list_offset, data_offset;
1125         u16 phy_data = 0;
1126         s32 ret_val = IXGBE_SUCCESS;
1127         u32 i;
1128
1129         DEBUGFUNC("ixgbe_reset_phy_nl");
1130
1131         /* Blocked by MNG FW so bail */
1132         if (ixgbe_check_reset_blocked(hw))
1133                 goto out;
1134
1135         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1136                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1137
1138         /* reset the PHY and poll for completion */
1139         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1140                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1141                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1142
1143         for (i = 0; i < 100; i++) {
1144                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1145                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1146                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1147                         break;
1148                 msec_delay(10);
1149         }
1150
1151         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1152                 DEBUGOUT("PHY reset did not complete.\n");
1153                 ret_val = IXGBE_ERR_PHY;
1154                 goto out;
1155         }
1156
1157         /* Get init offsets */
1158         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1159                                                       &data_offset);
1160         if (ret_val != IXGBE_SUCCESS)
1161                 goto out;
1162
1163         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1164         data_offset++;
1165         while (!end_data) {
1166                 /*
1167                  * Read control word from PHY init contents offset
1168                  */
1169                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1170                 if (ret_val)
1171                         goto err_eeprom;
1172                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1173                            IXGBE_CONTROL_SHIFT_NL;
1174                 edata = eword & IXGBE_DATA_MASK_NL;
1175                 switch (control) {
1176                 case IXGBE_DELAY_NL:
1177                         data_offset++;
1178                         DEBUGOUT1("DELAY: %d MS\n", edata);
1179                         msec_delay(edata);
1180                         break;
1181                 case IXGBE_DATA_NL:
1182                         DEBUGOUT("DATA:\n");
1183                         data_offset++;
1184                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1185                                                       &phy_offset);
1186                         if (ret_val)
1187                                 goto err_eeprom;
1188                         data_offset++;
1189                         for (i = 0; i < edata; i++) {
1190                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1191                                                               &eword);
1192                                 if (ret_val)
1193                                         goto err_eeprom;
1194                                 hw->phy.ops.write_reg(hw, phy_offset,
1195                                                       IXGBE_TWINAX_DEV, eword);
1196                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1197                                           phy_offset);
1198                                 data_offset++;
1199                                 phy_offset++;
1200                         }
1201                         break;
1202                 case IXGBE_CONTROL_NL:
1203                         data_offset++;
1204                         DEBUGOUT("CONTROL:\n");
1205                         if (edata == IXGBE_CONTROL_EOL_NL) {
1206                                 DEBUGOUT("EOL\n");
1207                                 end_data = true;
1208                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1209                                 DEBUGOUT("SOL\n");
1210                         } else {
1211                                 DEBUGOUT("Bad control value\n");
1212                                 ret_val = IXGBE_ERR_PHY;
1213                                 goto out;
1214                         }
1215                         break;
1216                 default:
1217                         DEBUGOUT("Bad control type\n");
1218                         ret_val = IXGBE_ERR_PHY;
1219                         goto out;
1220                 }
1221         }
1222
1223 out:
1224         return ret_val;
1225
1226 err_eeprom:
1227         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1228                       "eeprom read at offset %d failed", data_offset);
1229         return IXGBE_ERR_PHY;
1230 }
1231
1232 /**
1233  *  ixgbe_identify_module_generic - Identifies module type
1234  *  @hw: pointer to hardware structure
1235  *
1236  *  Determines HW type and calls appropriate function.
1237  **/
1238 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1239 {
1240         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1241
1242         DEBUGFUNC("ixgbe_identify_module_generic");
1243
1244         switch (hw->mac.ops.get_media_type(hw)) {
1245         case ixgbe_media_type_fiber:
1246                 status = ixgbe_identify_sfp_module_generic(hw);
1247                 break;
1248
1249         case ixgbe_media_type_fiber_qsfp:
1250                 status = ixgbe_identify_qsfp_module_generic(hw);
1251                 break;
1252
1253         default:
1254                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1255                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1256                 break;
1257         }
1258
1259         return status;
1260 }
1261
1262 /**
1263  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1264  *  @hw: pointer to hardware structure
1265  *
1266  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1267  **/
1268 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1269 {
1270         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1271         u32 vendor_oui = 0;
1272         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1273         u8 identifier = 0;
1274         u8 comp_codes_1g = 0;
1275         u8 comp_codes_10g = 0;
1276         u8 oui_bytes[3] = {0, 0, 0};
1277         u8 cable_tech = 0;
1278         u8 cable_spec = 0;
1279         u16 enforce_sfp = 0;
1280
1281         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1282
1283         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1284                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1285                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1286                 goto out;
1287         }
1288
1289         /* LAN ID is needed for I2C access */
1290         hw->mac.ops.set_lan_id(hw);
1291
1292         status = hw->phy.ops.read_i2c_eeprom(hw,
1293                                              IXGBE_SFF_IDENTIFIER,
1294                                              &identifier);
1295
1296         if (status != IXGBE_SUCCESS)
1297                 goto err_read_i2c_eeprom;
1298
1299         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1300                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1301                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1302         } else {
1303                 status = hw->phy.ops.read_i2c_eeprom(hw,
1304                                                      IXGBE_SFF_1GBE_COMP_CODES,
1305                                                      &comp_codes_1g);
1306
1307                 if (status != IXGBE_SUCCESS)
1308                         goto err_read_i2c_eeprom;
1309
1310                 status = hw->phy.ops.read_i2c_eeprom(hw,
1311                                                      IXGBE_SFF_10GBE_COMP_CODES,
1312                                                      &comp_codes_10g);
1313
1314                 if (status != IXGBE_SUCCESS)
1315                         goto err_read_i2c_eeprom;
1316                 status = hw->phy.ops.read_i2c_eeprom(hw,
1317                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1318                                                      &cable_tech);
1319
1320                 if (status != IXGBE_SUCCESS)
1321                         goto err_read_i2c_eeprom;
1322
1323                  /* ID Module
1324                   * =========
1325                   * 0   SFP_DA_CU
1326                   * 1   SFP_SR
1327                   * 2   SFP_LR
1328                   * 3   SFP_DA_CORE0 - 82599-specific
1329                   * 4   SFP_DA_CORE1 - 82599-specific
1330                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1331                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1332                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1333                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1334                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1335                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1336                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1337                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1338                   */
1339                 if (hw->mac.type == ixgbe_mac_82598EB) {
1340                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1341                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1342                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1343                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1344                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1345                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1346                         else
1347                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1348                 } else {
1349                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1350                                 if (hw->bus.lan_id == 0)
1351                                         hw->phy.sfp_type =
1352                                                      ixgbe_sfp_type_da_cu_core0;
1353                                 else
1354                                         hw->phy.sfp_type =
1355                                                      ixgbe_sfp_type_da_cu_core1;
1356                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1357                                 hw->phy.ops.read_i2c_eeprom(
1358                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1359                                                 &cable_spec);
1360                                 if (cable_spec &
1361                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1362                                         if (hw->bus.lan_id == 0)
1363                                                 hw->phy.sfp_type =
1364                                                 ixgbe_sfp_type_da_act_lmt_core0;
1365                                         else
1366                                                 hw->phy.sfp_type =
1367                                                 ixgbe_sfp_type_da_act_lmt_core1;
1368                                 } else {
1369                                         hw->phy.sfp_type =
1370                                                         ixgbe_sfp_type_unknown;
1371                                 }
1372                         } else if (comp_codes_10g &
1373                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1374                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1375                                 if (hw->bus.lan_id == 0)
1376                                         hw->phy.sfp_type =
1377                                                       ixgbe_sfp_type_srlr_core0;
1378                                 else
1379                                         hw->phy.sfp_type =
1380                                                       ixgbe_sfp_type_srlr_core1;
1381                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1382                                 if (hw->bus.lan_id == 0)
1383                                         hw->phy.sfp_type =
1384                                                 ixgbe_sfp_type_1g_cu_core0;
1385                                 else
1386                                         hw->phy.sfp_type =
1387                                                 ixgbe_sfp_type_1g_cu_core1;
1388                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1389                                 if (hw->bus.lan_id == 0)
1390                                         hw->phy.sfp_type =
1391                                                 ixgbe_sfp_type_1g_sx_core0;
1392                                 else
1393                                         hw->phy.sfp_type =
1394                                                 ixgbe_sfp_type_1g_sx_core1;
1395                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1396                                 if (hw->bus.lan_id == 0)
1397                                         hw->phy.sfp_type =
1398                                                 ixgbe_sfp_type_1g_lx_core0;
1399                                 else
1400                                         hw->phy.sfp_type =
1401                                                 ixgbe_sfp_type_1g_lx_core1;
1402                         } else {
1403                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1404                         }
1405                 }
1406
1407                 if (hw->phy.sfp_type != stored_sfp_type)
1408                         hw->phy.sfp_setup_needed = true;
1409
1410                 /* Determine if the SFP+ PHY is dual speed or not. */
1411                 hw->phy.multispeed_fiber = false;
1412                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1413                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1414                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1415                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1416                         hw->phy.multispeed_fiber = true;
1417
1418                 /* Determine PHY vendor */
1419                 if (hw->phy.type != ixgbe_phy_nl) {
1420                         hw->phy.id = identifier;
1421                         status = hw->phy.ops.read_i2c_eeprom(hw,
1422                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1423                                                     &oui_bytes[0]);
1424
1425                         if (status != IXGBE_SUCCESS)
1426                                 goto err_read_i2c_eeprom;
1427
1428                         status = hw->phy.ops.read_i2c_eeprom(hw,
1429                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1430                                                     &oui_bytes[1]);
1431
1432                         if (status != IXGBE_SUCCESS)
1433                                 goto err_read_i2c_eeprom;
1434
1435                         status = hw->phy.ops.read_i2c_eeprom(hw,
1436                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1437                                                     &oui_bytes[2]);
1438
1439                         if (status != IXGBE_SUCCESS)
1440                                 goto err_read_i2c_eeprom;
1441
1442                         vendor_oui =
1443                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1444                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1445                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1446
1447                         switch (vendor_oui) {
1448                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1449                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1450                                         hw->phy.type =
1451                                                     ixgbe_phy_sfp_passive_tyco;
1452                                 break;
1453                         case IXGBE_SFF_VENDOR_OUI_FTL:
1454                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1455                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1456                                 else
1457                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1458                                 break;
1459                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1460                                 hw->phy.type = ixgbe_phy_sfp_avago;
1461                                 break;
1462                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1463                                 hw->phy.type = ixgbe_phy_sfp_intel;
1464                                 break;
1465                         default:
1466                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1467                                         hw->phy.type =
1468                                                  ixgbe_phy_sfp_passive_unknown;
1469                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1470                                         hw->phy.type =
1471                                                 ixgbe_phy_sfp_active_unknown;
1472                                 else
1473                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1474                                 break;
1475                         }
1476                 }
1477
1478                 /* Allow any DA cable vendor */
1479                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1480                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1481                         status = IXGBE_SUCCESS;
1482                         goto out;
1483                 }
1484
1485                 /* Verify supported 1G SFP modules */
1486                 if (comp_codes_10g == 0 &&
1487                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1488                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1489                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1490                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1491                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1492                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1493                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1494                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1495                         goto out;
1496                 }
1497
1498                 /* Anything else 82598-based is supported */
1499                 if (hw->mac.type == ixgbe_mac_82598EB) {
1500                         status = IXGBE_SUCCESS;
1501                         goto out;
1502                 }
1503
1504                 ixgbe_get_device_caps(hw, &enforce_sfp);
1505                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1506                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1507                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1508                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1509                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1512                         /* Make sure we're a supported PHY type */
1513                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1514                                 status = IXGBE_SUCCESS;
1515                         } else {
1516                                 if (hw->allow_unsupported_sfp == true) {
1517                                         EWARN(hw, "WARNING: Intel (R) Network "
1518                                               "Connections are quality tested "
1519                                               "using Intel (R) Ethernet Optics."
1520                                               " Using untested modules is not "
1521                                               "supported and may cause unstable"
1522                                               " operation or damage to the "
1523                                               "module or the adapter. Intel "
1524                                               "Corporation is not responsible "
1525                                               "for any harm caused by using "
1526                                               "untested modules.\n", status);
1527                                         status = IXGBE_SUCCESS;
1528                                 } else {
1529                                         DEBUGOUT("SFP+ module not supported\n");
1530                                         hw->phy.type =
1531                                                 ixgbe_phy_sfp_unsupported;
1532                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1533                                 }
1534                         }
1535                 } else {
1536                         status = IXGBE_SUCCESS;
1537                 }
1538         }
1539
1540 out:
1541         return status;
1542
1543 err_read_i2c_eeprom:
1544         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1545         if (hw->phy.type != ixgbe_phy_nl) {
1546                 hw->phy.id = 0;
1547                 hw->phy.type = ixgbe_phy_unknown;
1548         }
1549         return IXGBE_ERR_SFP_NOT_PRESENT;
1550 }
1551
1552 /**
1553  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1554  *  @hw: pointer to hardware structure
1555  *
1556  *  Determines physical layer capabilities of the current SFP.
1557  */
1558 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1559 {
1560         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1561         u8 comp_codes_10g = 0;
1562         u8 comp_codes_1g = 0;
1563
1564         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1565
1566         hw->phy.ops.identify_sfp(hw);
1567         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1568                 return physical_layer;
1569
1570         switch (hw->phy.type) {
1571         case ixgbe_phy_sfp_passive_tyco:
1572         case ixgbe_phy_sfp_passive_unknown:
1573         case ixgbe_phy_qsfp_passive_unknown:
1574                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1575                 break;
1576         case ixgbe_phy_sfp_ftl_active:
1577         case ixgbe_phy_sfp_active_unknown:
1578         case ixgbe_phy_qsfp_active_unknown:
1579                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1580                 break;
1581         case ixgbe_phy_sfp_avago:
1582         case ixgbe_phy_sfp_ftl:
1583         case ixgbe_phy_sfp_intel:
1584         case ixgbe_phy_sfp_unknown:
1585                 hw->phy.ops.read_i2c_eeprom(hw,
1586                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1587                 hw->phy.ops.read_i2c_eeprom(hw,
1588                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1589                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1590                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1591                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1592                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1593                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1594                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1595                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1596                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1597                 break;
1598         case ixgbe_phy_qsfp_intel:
1599         case ixgbe_phy_qsfp_unknown:
1600                 hw->phy.ops.read_i2c_eeprom(hw,
1601                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1602                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1603                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1604                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1605                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1606                 break;
1607         default:
1608                 break;
1609         }
1610
1611         return physical_layer;
1612 }
1613
1614 /**
1615  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1616  *  @hw: pointer to hardware structure
1617  *
1618  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1619  **/
1620 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1621 {
1622         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1623         u32 vendor_oui = 0;
1624         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1625         u8 identifier = 0;
1626         u8 comp_codes_1g = 0;
1627         u8 comp_codes_10g = 0;
1628         u8 oui_bytes[3] = {0, 0, 0};
1629         u16 enforce_sfp = 0;
1630         u8 connector = 0;
1631         u8 cable_length = 0;
1632         u8 device_tech = 0;
1633         bool active_cable = false;
1634
1635         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1636
1637         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1638                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1639                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1640                 goto out;
1641         }
1642
1643         /* LAN ID is needed for I2C access */
1644         hw->mac.ops.set_lan_id(hw);
1645
1646         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1647                                              &identifier);
1648
1649         if (status != IXGBE_SUCCESS)
1650                 goto err_read_i2c_eeprom;
1651
1652         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1653                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1654                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1655                 goto out;
1656         }
1657
1658         hw->phy.id = identifier;
1659
1660         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1661                                              &comp_codes_10g);
1662
1663         if (status != IXGBE_SUCCESS)
1664                 goto err_read_i2c_eeprom;
1665
1666         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1667                                              &comp_codes_1g);
1668
1669         if (status != IXGBE_SUCCESS)
1670                 goto err_read_i2c_eeprom;
1671
1672         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1673                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1674                 if (hw->bus.lan_id == 0)
1675                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1676                 else
1677                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1678         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1679                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1680                 if (hw->bus.lan_id == 0)
1681                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1682                 else
1683                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1684         } else {
1685                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1686                         active_cable = true;
1687
1688                 if (!active_cable) {
1689                         /* check for active DA cables that pre-date
1690                          * SFF-8436 v3.6 */
1691                         hw->phy.ops.read_i2c_eeprom(hw,
1692                                         IXGBE_SFF_QSFP_CONNECTOR,
1693                                         &connector);
1694
1695                         hw->phy.ops.read_i2c_eeprom(hw,
1696                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1697                                         &cable_length);
1698
1699                         hw->phy.ops.read_i2c_eeprom(hw,
1700                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1701                                         &device_tech);
1702
1703                         if ((connector ==
1704                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1705                             (cable_length > 0) &&
1706                             ((device_tech >> 4) ==
1707                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1708                                 active_cable = true;
1709                 }
1710
1711                 if (active_cable) {
1712                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1713                         if (hw->bus.lan_id == 0)
1714                                 hw->phy.sfp_type =
1715                                                 ixgbe_sfp_type_da_act_lmt_core0;
1716                         else
1717                                 hw->phy.sfp_type =
1718                                                 ixgbe_sfp_type_da_act_lmt_core1;
1719                 } else {
1720                         /* unsupported module type */
1721                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1722                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1723                         goto out;
1724                 }
1725         }
1726
1727         if (hw->phy.sfp_type != stored_sfp_type)
1728                 hw->phy.sfp_setup_needed = true;
1729
1730         /* Determine if the QSFP+ PHY is dual speed or not. */
1731         hw->phy.multispeed_fiber = false;
1732         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1733            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1734            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1735            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1736                 hw->phy.multispeed_fiber = true;
1737
1738         /* Determine PHY vendor for optical modules */
1739         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1740                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1741                 status = hw->phy.ops.read_i2c_eeprom(hw,
1742                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1743                                             &oui_bytes[0]);
1744
1745                 if (status != IXGBE_SUCCESS)
1746                         goto err_read_i2c_eeprom;
1747
1748                 status = hw->phy.ops.read_i2c_eeprom(hw,
1749                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1750                                             &oui_bytes[1]);
1751
1752                 if (status != IXGBE_SUCCESS)
1753                         goto err_read_i2c_eeprom;
1754
1755                 status = hw->phy.ops.read_i2c_eeprom(hw,
1756                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1757                                             &oui_bytes[2]);
1758
1759                 if (status != IXGBE_SUCCESS)
1760                         goto err_read_i2c_eeprom;
1761
1762                 vendor_oui =
1763                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1764                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1765                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1766
1767                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1768                         hw->phy.type = ixgbe_phy_qsfp_intel;
1769                 else
1770                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1771
1772                 ixgbe_get_device_caps(hw, &enforce_sfp);
1773                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1774                         /* Make sure we're a supported PHY type */
1775                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1776                                 status = IXGBE_SUCCESS;
1777                         } else {
1778                                 if (hw->allow_unsupported_sfp == true) {
1779                                         EWARN(hw, "WARNING: Intel (R) Network "
1780                                               "Connections are quality tested "
1781                                               "using Intel (R) Ethernet Optics."
1782                                               " Using untested modules is not "
1783                                               "supported and may cause unstable"
1784                                               " operation or damage to the "
1785                                               "module or the adapter. Intel "
1786                                               "Corporation is not responsible "
1787                                               "for any harm caused by using "
1788                                               "untested modules.\n", status);
1789                                         status = IXGBE_SUCCESS;
1790                                 } else {
1791                                         DEBUGOUT("QSFP module not supported\n");
1792                                         hw->phy.type =
1793                                                 ixgbe_phy_sfp_unsupported;
1794                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1795                                 }
1796                         }
1797                 } else {
1798                         status = IXGBE_SUCCESS;
1799                 }
1800         }
1801
1802 out:
1803         return status;
1804
1805 err_read_i2c_eeprom:
1806         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1807         hw->phy.id = 0;
1808         hw->phy.type = ixgbe_phy_unknown;
1809
1810         return IXGBE_ERR_SFP_NOT_PRESENT;
1811 }
1812
1813
1814 /**
1815  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1816  *  @hw: pointer to hardware structure
1817  *  @list_offset: offset to the SFP ID list
1818  *  @data_offset: offset to the SFP data block
1819  *
1820  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1821  *  so it returns the offsets to the phy init sequence block.
1822  **/
1823 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1824                                         u16 *list_offset,
1825                                         u16 *data_offset)
1826 {
1827         u16 sfp_id;
1828         u16 sfp_type = hw->phy.sfp_type;
1829
1830         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1831
1832         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1833                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1834
1835         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1836                 return IXGBE_ERR_SFP_NOT_PRESENT;
1837
1838         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1839             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1840                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1841
1842         /*
1843          * Limiting active cables and 1G Phys must be initialized as
1844          * SR modules
1845          */
1846         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1847             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1848             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1849             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1850                 sfp_type = ixgbe_sfp_type_srlr_core0;
1851         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1852                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1853                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1854                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1855                 sfp_type = ixgbe_sfp_type_srlr_core1;
1856
1857         /* Read offset to PHY init contents */
1858         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1859                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1860                               "eeprom read at offset %d failed",
1861                               IXGBE_PHY_INIT_OFFSET_NL);
1862                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1863         }
1864
1865         if ((!*list_offset) || (*list_offset == 0xFFFF))
1866                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1867
1868         /* Shift offset to first ID word */
1869         (*list_offset)++;
1870
1871         /*
1872          * Find the matching SFP ID in the EEPROM
1873          * and program the init sequence
1874          */
1875         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1876                 goto err_phy;
1877
1878         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1879                 if (sfp_id == sfp_type) {
1880                         (*list_offset)++;
1881                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1882                                 goto err_phy;
1883                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1884                                 DEBUGOUT("SFP+ module not supported\n");
1885                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1886                         } else {
1887                                 break;
1888                         }
1889                 } else {
1890                         (*list_offset) += 2;
1891                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1892                                 goto err_phy;
1893                 }
1894         }
1895
1896         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1897                 DEBUGOUT("No matching SFP+ module found\n");
1898                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1899         }
1900
1901         return IXGBE_SUCCESS;
1902
1903 err_phy:
1904         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1905                       "eeprom read at offset %d failed", *list_offset);
1906         return IXGBE_ERR_PHY;
1907 }
1908
1909 /**
1910  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1911  *  @hw: pointer to hardware structure
1912  *  @byte_offset: EEPROM byte offset to read
1913  *  @eeprom_data: value read
1914  *
1915  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1916  **/
1917 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1918                                   u8 *eeprom_data)
1919 {
1920         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1921
1922         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1923                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1924                                          eeprom_data);
1925 }
1926
1927 /**
1928  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1929  *  @hw: pointer to hardware structure
1930  *  @byte_offset: byte offset at address 0xA2
1931  *  @eeprom_data: value read
1932  *
1933  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1934  **/
1935 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1936                                           u8 *sff8472_data)
1937 {
1938         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1939                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1940                                          sff8472_data);
1941 }
1942
1943 /**
1944  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1945  *  @hw: pointer to hardware structure
1946  *  @byte_offset: EEPROM byte offset to write
1947  *  @eeprom_data: value to write
1948  *
1949  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1950  **/
1951 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1952                                    u8 eeprom_data)
1953 {
1954         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1955
1956         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1957                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1958                                           eeprom_data);
1959 }
1960
1961 /**
1962  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1963  * @hw: pointer to hardware structure
1964  * @offset: eeprom offset to be read
1965  * @addr: I2C address to be read
1966  */
1967 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1968 {
1969         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1970             offset == IXGBE_SFF_IDENTIFIER &&
1971             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1972                 return true;
1973         return false;
1974 }
1975
1976 /**
1977  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1978  *  @hw: pointer to hardware structure
1979  *  @byte_offset: byte offset to read
1980  *  @data: value read
1981  *  @lock: true if to take and release semaphore
1982  *
1983  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1984  *  a specified device address.
1985  **/
1986 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1987                                            u8 dev_addr, u8 *data, bool lock)
1988 {
1989         s32 status;
1990         u32 max_retry = 10;
1991         u32 retry = 0;
1992         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1993         bool nack = 1;
1994         *data = 0;
1995
1996         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1997
1998         if (hw->mac.type >= ixgbe_mac_X550)
1999                 max_retry = 3;
2000         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2001                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2002
2003         do {
2004                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2005                         return IXGBE_ERR_SWFW_SYNC;
2006
2007                 ixgbe_i2c_start(hw);
2008
2009                 /* Device Address and write indication */
2010                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2011                 if (status != IXGBE_SUCCESS)
2012                         goto fail;
2013
2014                 status = ixgbe_get_i2c_ack(hw);
2015                 if (status != IXGBE_SUCCESS)
2016                         goto fail;
2017
2018                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2019                 if (status != IXGBE_SUCCESS)
2020                         goto fail;
2021
2022                 status = ixgbe_get_i2c_ack(hw);
2023                 if (status != IXGBE_SUCCESS)
2024                         goto fail;
2025
2026                 ixgbe_i2c_start(hw);
2027
2028                 /* Device Address and read indication */
2029                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2030                 if (status != IXGBE_SUCCESS)
2031                         goto fail;
2032
2033                 status = ixgbe_get_i2c_ack(hw);
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_clock_in_i2c_byte(hw, data);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2042                 if (status != IXGBE_SUCCESS)
2043                         goto fail;
2044
2045                 ixgbe_i2c_stop(hw);
2046                 if (lock)
2047                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2048                 return IXGBE_SUCCESS;
2049
2050 fail:
2051                 ixgbe_i2c_bus_clear(hw);
2052                 if (lock) {
2053                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2054                         msec_delay(100);
2055                 }
2056                 retry++;
2057                 if (retry < max_retry)
2058                         DEBUGOUT("I2C byte read error - Retrying.\n");
2059                 else
2060                         DEBUGOUT("I2C byte read error.\n");
2061
2062         } while (retry < max_retry);
2063
2064         return status;
2065 }
2066
2067 /**
2068  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2069  *  @hw: pointer to hardware structure
2070  *  @byte_offset: byte offset to read
2071  *  @data: value read
2072  *
2073  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2074  *  a specified device address.
2075  **/
2076 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2077                                 u8 dev_addr, u8 *data)
2078 {
2079         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2080                                                data, true);
2081 }
2082
2083 /**
2084  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2085  *  @hw: pointer to hardware structure
2086  *  @byte_offset: byte offset to read
2087  *  @data: value read
2088  *
2089  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2090  *  a specified device address.
2091  **/
2092 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2093                                          u8 dev_addr, u8 *data)
2094 {
2095         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2096                                                data, false);
2097 }
2098
2099 /**
2100  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2101  *  @hw: pointer to hardware structure
2102  *  @byte_offset: byte offset to write
2103  *  @data: value to write
2104  *  @lock: true if to take and release semaphore
2105  *
2106  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2107  *  a specified device address.
2108  **/
2109 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2110                                             u8 dev_addr, u8 data, bool lock)
2111 {
2112         s32 status;
2113         u32 max_retry = 1;
2114         u32 retry = 0;
2115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2116
2117         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2118
2119         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2120             IXGBE_SUCCESS)
2121                 return IXGBE_ERR_SWFW_SYNC;
2122
2123         do {
2124                 ixgbe_i2c_start(hw);
2125
2126                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2127                 if (status != IXGBE_SUCCESS)
2128                         goto fail;
2129
2130                 status = ixgbe_get_i2c_ack(hw);
2131                 if (status != IXGBE_SUCCESS)
2132                         goto fail;
2133
2134                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2135                 if (status != IXGBE_SUCCESS)
2136                         goto fail;
2137
2138                 status = ixgbe_get_i2c_ack(hw);
2139                 if (status != IXGBE_SUCCESS)
2140                         goto fail;
2141
2142                 status = ixgbe_clock_out_i2c_byte(hw, data);
2143                 if (status != IXGBE_SUCCESS)
2144                         goto fail;
2145
2146                 status = ixgbe_get_i2c_ack(hw);
2147                 if (status != IXGBE_SUCCESS)
2148                         goto fail;
2149
2150                 ixgbe_i2c_stop(hw);
2151                 if (lock)
2152                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2153                 return IXGBE_SUCCESS;
2154
2155 fail:
2156                 ixgbe_i2c_bus_clear(hw);
2157                 retry++;
2158                 if (retry < max_retry)
2159                         DEBUGOUT("I2C byte write error - Retrying.\n");
2160                 else
2161                         DEBUGOUT("I2C byte write error.\n");
2162         } while (retry < max_retry);
2163
2164         if (lock)
2165                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2166
2167         return status;
2168 }
2169
2170 /**
2171  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2172  *  @hw: pointer to hardware structure
2173  *  @byte_offset: byte offset to write
2174  *  @data: value to write
2175  *
2176  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2177  *  a specified device address.
2178  **/
2179 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2180                                  u8 dev_addr, u8 data)
2181 {
2182         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2183                                                 data, true);
2184 }
2185
2186 /**
2187  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2188  *  @hw: pointer to hardware structure
2189  *  @byte_offset: byte offset to write
2190  *  @data: value to write
2191  *
2192  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2193  *  a specified device address.
2194  **/
2195 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2196                                           u8 dev_addr, u8 data)
2197 {
2198         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2199                                                 data, false);
2200 }
2201
2202 /**
2203  *  ixgbe_i2c_start - Sets I2C start condition
2204  *  @hw: pointer to hardware structure
2205  *
2206  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2207  *  Set bit-bang mode on X550 hardware.
2208  **/
2209 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2210 {
2211         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2212
2213         DEBUGFUNC("ixgbe_i2c_start");
2214
2215         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2216
2217         /* Start condition must begin with data and clock high */
2218         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2219         ixgbe_raise_i2c_clk(hw, &i2cctl);
2220
2221         /* Setup time for start condition (4.7us) */
2222         usec_delay(IXGBE_I2C_T_SU_STA);
2223
2224         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2225
2226         /* Hold time for start condition (4us) */
2227         usec_delay(IXGBE_I2C_T_HD_STA);
2228
2229         ixgbe_lower_i2c_clk(hw, &i2cctl);
2230
2231         /* Minimum low period of clock is 4.7 us */
2232         usec_delay(IXGBE_I2C_T_LOW);
2233
2234 }
2235
2236 /**
2237  *  ixgbe_i2c_stop - Sets I2C stop condition
2238  *  @hw: pointer to hardware structure
2239  *
2240  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2241  *  Disables bit-bang mode and negates data output enable on X550
2242  *  hardware.
2243  **/
2244 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2245 {
2246         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2247         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2248         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2249         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2250
2251         DEBUGFUNC("ixgbe_i2c_stop");
2252
2253         /* Stop condition must begin with data low and clock high */
2254         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2255         ixgbe_raise_i2c_clk(hw, &i2cctl);
2256
2257         /* Setup time for stop condition (4us) */
2258         usec_delay(IXGBE_I2C_T_SU_STO);
2259
2260         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2261
2262         /* bus free time between stop and start (4.7us)*/
2263         usec_delay(IXGBE_I2C_T_BUF);
2264
2265         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2266                 i2cctl &= ~bb_en_bit;
2267                 i2cctl |= data_oe_bit | clk_oe_bit;
2268                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2269                 IXGBE_WRITE_FLUSH(hw);
2270         }
2271 }
2272
2273 /**
2274  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2275  *  @hw: pointer to hardware structure
2276  *  @data: data byte to clock in
2277  *
2278  *  Clocks in one byte data via I2C data/clock
2279  **/
2280 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2281 {
2282         s32 i;
2283         bool bit = 0;
2284
2285         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2286
2287         *data = 0;
2288         for (i = 7; i >= 0; i--) {
2289                 ixgbe_clock_in_i2c_bit(hw, &bit);
2290                 *data |= bit << i;
2291         }
2292
2293         return IXGBE_SUCCESS;
2294 }
2295
2296 /**
2297  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2298  *  @hw: pointer to hardware structure
2299  *  @data: data byte clocked out
2300  *
2301  *  Clocks out one byte data via I2C data/clock
2302  **/
2303 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2304 {
2305         s32 status = IXGBE_SUCCESS;
2306         s32 i;
2307         u32 i2cctl;
2308         bool bit;
2309
2310         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2311
2312         for (i = 7; i >= 0; i--) {
2313                 bit = (data >> i) & 0x1;
2314                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2315
2316                 if (status != IXGBE_SUCCESS)
2317                         break;
2318         }
2319
2320         /* Release SDA line (set high) */
2321         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2322         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2323         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2324         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2325         IXGBE_WRITE_FLUSH(hw);
2326
2327         return status;
2328 }
2329
2330 /**
2331  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2332  *  @hw: pointer to hardware structure
2333  *
2334  *  Clocks in/out one bit via I2C data/clock
2335  **/
2336 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2337 {
2338         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2339         s32 status = IXGBE_SUCCESS;
2340         u32 i = 0;
2341         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2342         u32 timeout = 10;
2343         bool ack = 1;
2344
2345         DEBUGFUNC("ixgbe_get_i2c_ack");
2346
2347         if (data_oe_bit) {
2348                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2349                 i2cctl |= data_oe_bit;
2350                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2351                 IXGBE_WRITE_FLUSH(hw);
2352         }
2353         ixgbe_raise_i2c_clk(hw, &i2cctl);
2354
2355         /* Minimum high period of clock is 4us */
2356         usec_delay(IXGBE_I2C_T_HIGH);
2357
2358         /* Poll for ACK.  Note that ACK in I2C spec is
2359          * transition from 1 to 0 */
2360         for (i = 0; i < timeout; i++) {
2361                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2362                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2363
2364                 usec_delay(1);
2365                 if (!ack)
2366                         break;
2367         }
2368
2369         if (ack) {
2370                 DEBUGOUT("I2C ack was not received.\n");
2371                 status = IXGBE_ERR_I2C;
2372         }
2373
2374         ixgbe_lower_i2c_clk(hw, &i2cctl);
2375
2376         /* Minimum low period of clock is 4.7 us */
2377         usec_delay(IXGBE_I2C_T_LOW);
2378
2379         return status;
2380 }
2381
2382 /**
2383  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2384  *  @hw: pointer to hardware structure
2385  *  @data: read data value
2386  *
2387  *  Clocks in one bit via I2C data/clock
2388  **/
2389 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2390 {
2391         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2392         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2393
2394         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2395
2396         if (data_oe_bit) {
2397                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2398                 i2cctl |= data_oe_bit;
2399                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2400                 IXGBE_WRITE_FLUSH(hw);
2401         }
2402         ixgbe_raise_i2c_clk(hw, &i2cctl);
2403
2404         /* Minimum high period of clock is 4us */
2405         usec_delay(IXGBE_I2C_T_HIGH);
2406
2407         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2408         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2409
2410         ixgbe_lower_i2c_clk(hw, &i2cctl);
2411
2412         /* Minimum low period of clock is 4.7 us */
2413         usec_delay(IXGBE_I2C_T_LOW);
2414
2415         return IXGBE_SUCCESS;
2416 }
2417
2418 /**
2419  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2420  *  @hw: pointer to hardware structure
2421  *  @data: data value to write
2422  *
2423  *  Clocks out one bit via I2C data/clock
2424  **/
2425 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2426 {
2427         s32 status;
2428         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2429
2430         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2431
2432         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2433         if (status == IXGBE_SUCCESS) {
2434                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2435
2436                 /* Minimum high period of clock is 4us */
2437                 usec_delay(IXGBE_I2C_T_HIGH);
2438
2439                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2440
2441                 /* Minimum low period of clock is 4.7 us.
2442                  * This also takes care of the data hold time.
2443                  */
2444                 usec_delay(IXGBE_I2C_T_LOW);
2445         } else {
2446                 status = IXGBE_ERR_I2C;
2447                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2448                              "I2C data was not set to %X\n", data);
2449         }
2450
2451         return status;
2452 }
2453
2454 /**
2455  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2456  *  @hw: pointer to hardware structure
2457  *  @i2cctl: Current value of I2CCTL register
2458  *
2459  *  Raises the I2C clock line '0'->'1'
2460  *  Negates the I2C clock output enable on X550 hardware.
2461  **/
2462 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2463 {
2464         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2465         u32 i = 0;
2466         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2467         u32 i2cctl_r = 0;
2468
2469         DEBUGFUNC("ixgbe_raise_i2c_clk");
2470
2471         if (clk_oe_bit) {
2472                 *i2cctl |= clk_oe_bit;
2473                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2474         }
2475
2476         for (i = 0; i < timeout; i++) {
2477                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2478
2479                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2480                 IXGBE_WRITE_FLUSH(hw);
2481                 /* SCL rise time (1000ns) */
2482                 usec_delay(IXGBE_I2C_T_RISE);
2483
2484                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2485                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2486                         break;
2487         }
2488 }
2489
2490 /**
2491  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2492  *  @hw: pointer to hardware structure
2493  *  @i2cctl: Current value of I2CCTL register
2494  *
2495  *  Lowers the I2C clock line '1'->'0'
2496  *  Asserts the I2C clock output enable on X550 hardware.
2497  **/
2498 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2499 {
2500         DEBUGFUNC("ixgbe_lower_i2c_clk");
2501
2502         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2503         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2504
2505         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2506         IXGBE_WRITE_FLUSH(hw);
2507
2508         /* SCL fall time (300ns) */
2509         usec_delay(IXGBE_I2C_T_FALL);
2510 }
2511
2512 /**
2513  *  ixgbe_set_i2c_data - Sets the I2C data bit
2514  *  @hw: pointer to hardware structure
2515  *  @i2cctl: Current value of I2CCTL register
2516  *  @data: I2C data value (0 or 1) to set
2517  *
2518  *  Sets the I2C data bit
2519  *  Asserts the I2C data output enable on X550 hardware.
2520  **/
2521 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2522 {
2523         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2524         s32 status = IXGBE_SUCCESS;
2525
2526         DEBUGFUNC("ixgbe_set_i2c_data");
2527
2528         if (data)
2529                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2530         else
2531                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2532         *i2cctl &= ~data_oe_bit;
2533
2534         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2535         IXGBE_WRITE_FLUSH(hw);
2536
2537         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2538         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2539
2540         if (!data)      /* Can't verify data in this case */
2541                 return IXGBE_SUCCESS;
2542         if (data_oe_bit) {
2543                 *i2cctl |= data_oe_bit;
2544                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2545                 IXGBE_WRITE_FLUSH(hw);
2546         }
2547
2548         /* Verify data was set correctly */
2549         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2550         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2551                 status = IXGBE_ERR_I2C;
2552                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2553                              "Error - I2C data was not set to %X.\n",
2554                              data);
2555         }
2556
2557         return status;
2558 }
2559
2560 /**
2561  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2562  *  @hw: pointer to hardware structure
2563  *  @i2cctl: Current value of I2CCTL register
2564  *
2565  *  Returns the I2C data bit value
2566  *  Negates the I2C data output enable on X550 hardware.
2567  **/
2568 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2569 {
2570         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2571         bool data;
2572
2573         DEBUGFUNC("ixgbe_get_i2c_data");
2574
2575         if (data_oe_bit) {
2576                 *i2cctl |= data_oe_bit;
2577                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2578                 IXGBE_WRITE_FLUSH(hw);
2579                 usec_delay(IXGBE_I2C_T_FALL);
2580         }
2581
2582         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2583                 data = 1;
2584         else
2585                 data = 0;
2586
2587         return data;
2588 }
2589
2590 /**
2591  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2592  *  @hw: pointer to hardware structure
2593  *
2594  *  Clears the I2C bus by sending nine clock pulses.
2595  *  Used when data line is stuck low.
2596  **/
2597 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2598 {
2599         u32 i2cctl;
2600         u32 i;
2601
2602         DEBUGFUNC("ixgbe_i2c_bus_clear");
2603
2604         ixgbe_i2c_start(hw);
2605         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2606
2607         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2608
2609         for (i = 0; i < 9; i++) {
2610                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2611
2612                 /* Min high period of clock is 4us */
2613                 usec_delay(IXGBE_I2C_T_HIGH);
2614
2615                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2616
2617                 /* Min low period of clock is 4.7us*/
2618                 usec_delay(IXGBE_I2C_T_LOW);
2619         }
2620
2621         ixgbe_i2c_start(hw);
2622
2623         /* Put the i2c bus back to default state */
2624         ixgbe_i2c_stop(hw);
2625 }
2626
2627 /**
2628  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2629  *  @hw: pointer to hardware structure
2630  *
2631  *  Checks if the LASI temp alarm status was triggered due to overtemp
2632  **/
2633 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2634 {
2635         s32 status = IXGBE_SUCCESS;
2636         u16 phy_data = 0;
2637
2638         DEBUGFUNC("ixgbe_tn_check_overtemp");
2639
2640         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2641                 goto out;
2642
2643         /* Check that the LASI temp alarm status was triggered */
2644         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2645                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2646
2647         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2648                 goto out;
2649
2650         status = IXGBE_ERR_OVERTEMP;
2651         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2652 out:
2653         return status;
2654 }
2655
2656 /**
2657  * ixgbe_set_copper_phy_power - Control power for copper phy
2658  * @hw: pointer to hardware structure
2659  * @on: true for on, false for off
2660  */
2661 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2662 {
2663         u32 status;
2664         u16 reg;
2665
2666         if (!on && ixgbe_mng_present(hw))
2667                 return 0;
2668
2669         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2670                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2671                                       &reg);
2672         if (status)
2673                 return status;
2674
2675         if (on) {
2676                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2677         } else {
2678                 if (ixgbe_check_reset_blocked(hw))
2679                         return 0;
2680                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2681         }
2682
2683         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2684                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2685                                        reg);
2686         return status;
2687 }