drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns true if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr))
 297                 return false;
 298
 299         if (ixgbe_get_phy_id(hw))
 300                 return false;
 301
 302         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 303
 304         if (hw->phy.type == ixgbe_phy_unknown) {
 305                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 307                 if (ext_ability &
 308                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 309                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 310                         hw->phy.type = ixgbe_phy_cu_unknown;
 311                 else
 312                         hw->phy.type = ixgbe_phy_generic;
 313         }
 314
 315         return true;
 316 }
 317
 318 /**
 319  *  ixgbe_identify_phy_generic - Get physical layer module
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Determines the physical layer module found on the current adapter.
 323  **/
 324 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 325 {
 326         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 327         u16 phy_addr;
 328
 329         DEBUGFUNC("ixgbe_identify_phy_generic");
 330
 331         if (!hw->phy.phy_semaphore_mask) {
 332                 if (hw->bus.lan_id)
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 334                 else
 335                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 336         }
 337
 338         if (hw->phy.type != ixgbe_phy_unknown)
 339                 return IXGBE_SUCCESS;
 340
 341         if (hw->phy.nw_mng_if_sel) {
 342                 phy_addr = (hw->phy.nw_mng_if_sel &
 343                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 344                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 345                 if (ixgbe_probe_phy(hw, phy_addr))
 346                         return IXGBE_SUCCESS;
 347                 else
 348                         return IXGBE_ERR_PHY_ADDR_INVALID;
 349         }
 350
 351         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 352                 if (ixgbe_probe_phy(hw, phy_addr)) {
 353                         status = IXGBE_SUCCESS;
 354                         break;
 355                 }
 356         }
 357
 358         /* Certain media types do not have a phy so an address will not
 359          * be found and the code will take this path.  Caller has to
 360          * decide if it is an error or not.
 361          */
 362         if (status != IXGBE_SUCCESS)
 363                 hw->phy.addr = 0;
 364
 365         return status;
 366 }
 367
 368 /**
 369  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 370  * @hw: pointer to the hardware structure
 371  *
 372  * This function checks the MMNGC.MNG_VETO bit to see if there are
 373  * any constraints on link from manageability.  For MAC's that don't
 374  * have this bit just return faluse since the link can not be blocked
 375  * via this method.
 376  **/
 377 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 378 {
 379         u32 mmngc;
 380
 381         DEBUGFUNC("ixgbe_check_reset_blocked");
 382
 383         /* If we don't have this bit, it can't be blocking */
 384         if (hw->mac.type == ixgbe_mac_82598EB)
 385                 return false;
 386
 387         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 388         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 389                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 390                               "MNG_VETO bit detected.\n");
 391                 return true;
 392         }
 393
 394         return false;
 395 }
 396
 397 /**
 398  *  ixgbe_validate_phy_addr - Determines phy address is valid
 399  *  @hw: pointer to hardware structure
 400  *
 401  **/
 402 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 403 {
 404         u16 phy_id = 0;
 405         bool valid = false;
 406
 407         DEBUGFUNC("ixgbe_validate_phy_addr");
 408
 409         hw->phy.addr = phy_addr;
 410         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 411                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 412
 413         if (phy_id != 0xFFFF && phy_id != 0x0)
 414                 valid = true;
 415
 416         return valid;
 417 }
 418
 419 /**
 420  *  ixgbe_get_phy_id - Get the phy type
 421  *  @hw: pointer to hardware structure
 422  *
 423  **/
 424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 425 {
 426         u32 status;
 427         u16 phy_id_high = 0;
 428         u16 phy_id_low = 0;
 429
 430         DEBUGFUNC("ixgbe_get_phy_id");
 431
 432         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 433                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 434                                       &phy_id_high);
 435
 436         if (status == IXGBE_SUCCESS) {
 437                 hw->phy.id = (u32)(phy_id_high << 16);
 438                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 439                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 440                                               &phy_id_low);
 441                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 442                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 443         }
 444         return status;
 445 }
 446
 447 /**
 448  *  ixgbe_get_phy_type_from_id - Get the phy type
 449  *  @phy_id: PHY ID information
 450  *
 451  **/
 452 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 453 {
 454         enum ixgbe_phy_type phy_type;
 455
 456         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 457
 458         switch (phy_id) {
 459         case TN1010_PHY_ID:
 460                 phy_type = ixgbe_phy_tn;
 461                 break;
 462         case X550_PHY_ID1:
 463         case X550_PHY_ID2:
 464         case X550_PHY_ID3:
 465         case X540_PHY_ID:
 466                 phy_type = ixgbe_phy_aq;
 467                 break;
 468         case QT2022_PHY_ID:
 469                 phy_type = ixgbe_phy_qt;
 470                 break;
 471         case ATH_PHY_ID:
 472                 phy_type = ixgbe_phy_nl;
 473                 break;
 474         case X557_PHY_ID:
 475         case X557_PHY_ID2:
 476                 phy_type = ixgbe_phy_x550em_ext_t;
 477                 break;
 478         case IXGBE_M88E1500_E_PHY_ID:
 479         case IXGBE_M88E1543_E_PHY_ID:
 480                 phy_type = ixgbe_phy_m88;
 481                 break;
 482         default:
 483                 phy_type = ixgbe_phy_unknown;
 484                 break;
 485         }
 486         return phy_type;
 487 }
 488
 489 /**
 490  *  ixgbe_reset_phy_generic - Performs a PHY reset
 491  *  @hw: pointer to hardware structure
 492  **/
 493 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 494 {
 495         u32 i;
 496         u16 ctrl = 0;
 497         s32 status = IXGBE_SUCCESS;
 498
 499         DEBUGFUNC("ixgbe_reset_phy_generic");
 500
 501         if (hw->phy.type == ixgbe_phy_unknown)
 502                 status = ixgbe_identify_phy_generic(hw);
 503
 504         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 505                 goto out;
 506
 507         /* Don't reset PHY if it's shut down due to overtemp. */
 508         if (!hw->phy.reset_if_overtemp &&
 509             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 510                 goto out;
 511
 512         /* Blocked by MNG FW so bail */
 513         if (ixgbe_check_reset_blocked(hw))
 514                 goto out;
 515
 516         /*
 517          * Perform soft PHY reset to the PHY_XS.
 518          * This will cause a soft reset to the PHY
 519          */
 520         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 521                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 522                               IXGBE_MDIO_PHY_XS_RESET);
 523
 524         /*
 525          * Poll for reset bit to self-clear indicating reset is complete.
 526          * Some PHYs could take up to 3 seconds to complete and need about
 527          * 1.7 usec delay after the reset is complete.
 528          */
 529         for (i = 0; i < 30; i++) {
 530                 msec_delay(100);
 531                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 532                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 533                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 534                         usec_delay(2);
 535                         break;
 536                 }
 537         }
 538
 539         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 540                 status = IXGBE_ERR_RESET_FAILED;
 541                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 542                              "PHY reset polling failed to complete.\n");
 543         }
 544
 545 out:
 546         return status;
 547 }
 548
 549 /**
 550  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 551  *  the SWFW lock
 552  *  @hw: pointer to hardware structure
 553  *  @reg_addr: 32 bit address of PHY register to read
 554  *  @phy_data: Pointer to read data from PHY register
 555  **/
 556 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 557                        u16 *phy_data)
 558 {
 559         u32 i, data, command;
 560
 561         /* Setup and write the address cycle command */
 562         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 563                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 564                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 565                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 566
 567         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 568
 569         /*
 570          * Check every 10 usec to see if the address cycle completed.
 571          * The MDI Command bit will clear when the operation is
 572          * complete
 573          */
 574         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 575                 usec_delay(10);
 576
 577                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 578                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 579                                 break;
 580         }
 581
 582
 583         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 584                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 585                 return IXGBE_ERR_PHY;
 586         }
 587
 588         /*
 589          * Address cycle complete, setup and write the read
 590          * command
 591          */
 592         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 593                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 594                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 595                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 596
 597         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 598
 599         /*
 600          * Check every 10 usec to see if the address cycle
 601          * completed. The MDI Command bit will clear when the
 602          * operation is complete
 603          */
 604         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 605                 usec_delay(10);
 606
 607                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 608                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 609                         break;
 610         }
 611
 612         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 613                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 614                 return IXGBE_ERR_PHY;
 615         }
 616
 617         /*
 618          * Read operation is complete.  Get the data
 619          * from MSRWD
 620          */
 621         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 622         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 623         *phy_data = (u16)(data);
 624
 625         return IXGBE_SUCCESS;
 626 }
 627
 628 /**
 629  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 630  *  using the SWFW lock - this function is needed in most cases
 631  *  @hw: pointer to hardware structure
 632  *  @reg_addr: 32 bit address of PHY register to read
 633  *  @phy_data: Pointer to read data from PHY register
 634  **/
 635 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 636                                u32 device_type, u16 *phy_data)
 637 {
 638         s32 status;
 639         u32 gssr = hw->phy.phy_semaphore_mask;
 640
 641         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 642
 643         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 644                 return IXGBE_ERR_SWFW_SYNC;
 645
 646         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 647
 648         hw->mac.ops.release_swfw_sync(hw, gssr);
 649
 650         return status;
 651 }
 652
 653 /**
 654  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 655  *  without SWFW lock
 656  *  @hw: pointer to hardware structure
 657  *  @reg_addr: 32 bit PHY register to write
 658  *  @device_type: 5 bit device type
 659  *  @phy_data: Data to write to the PHY register
 660  **/
 661 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 662                                 u32 device_type, u16 phy_data)
 663 {
 664         u32 i, command;
 665
 666         /* Put the data in the MDI single read and write data register*/
 667         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 668
 669         /* Setup and write the address cycle command */
 670         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 671                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 672                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 673                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 674
 675         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 676
 677         /*
 678          * Check every 10 usec to see if the address cycle completed.
 679          * The MDI Command bit will clear when the operation is
 680          * complete
 681          */
 682         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 683                 usec_delay(10);
 684
 685                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 686                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 687                         break;
 688         }
 689
 690         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 691                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 692                 return IXGBE_ERR_PHY;
 693         }
 694
 695         /*
 696          * Address cycle complete, setup and write the write
 697          * command
 698          */
 699         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 700                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 701                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 702                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 703
 704         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 705
 706         /*
 707          * Check every 10 usec to see if the address cycle
 708          * completed. The MDI Command bit will clear when the
 709          * operation is complete
 710          */
 711         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 712                 usec_delay(10);
 713
 714                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 715                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 716                         break;
 717         }
 718
 719         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 720                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 721                 return IXGBE_ERR_PHY;
 722         }
 723
 724         return IXGBE_SUCCESS;
 725 }
 726
 727 /**
 728  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 729  *  using SWFW lock- this function is needed in most cases
 730  *  @hw: pointer to hardware structure
 731  *  @reg_addr: 32 bit PHY register to write
 732  *  @device_type: 5 bit device type
 733  *  @phy_data: Data to write to the PHY register
 734  **/
 735 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 736                                 u32 device_type, u16 phy_data)
 737 {
 738         s32 status;
 739         u32 gssr = hw->phy.phy_semaphore_mask;
 740
 741         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 742
 743         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 744                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 745                                                  phy_data);
 746                 hw->mac.ops.release_swfw_sync(hw, gssr);
 747         } else {
 748                 status = IXGBE_ERR_SWFW_SYNC;
 749         }
 750
 751         return status;
 752 }
 753
 754 /**
 755  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 756  *  @hw: pointer to hardware structure
 757  *
 758  *  Restart auto-negotiation and PHY and waits for completion.
 759  **/
 760 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 761 {
 762         s32 status = IXGBE_SUCCESS;
 763         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 764         bool autoneg = false;
 765         ixgbe_link_speed speed;
 766
 767         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 768
 769         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 770
 771         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 772                 /* Set or unset auto-negotiation 10G advertisement */
 773                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 774                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 775                                      &autoneg_reg);
 776
 777                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 778                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 779                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 780
 781                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 782                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 783                                       autoneg_reg);
 784         }
 785
 786         if (hw->mac.type == ixgbe_mac_X550) {
 787                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 788                         /* Set or unset auto-negotiation 5G advertisement */
 789                         hw->phy.ops.read_reg(hw,
 790                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 791                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 792                                 &autoneg_reg);
 793
 794                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 795                         if (hw->phy.autoneg_advertised &
 796                              IXGBE_LINK_SPEED_5GB_FULL)
 797                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 798
 799                         hw->phy.ops.write_reg(hw,
 800                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 801                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                                 autoneg_reg);
 803                 }
 804
 805                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 806                         /* Set or unset auto-negotiation 2.5G advertisement */
 807                         hw->phy.ops.read_reg(hw,
 808                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 809                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 810                                 &autoneg_reg);
 811
 812                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 813                         if (hw->phy.autoneg_advertised &
 814                             IXGBE_LINK_SPEED_2_5GB_FULL)
 815                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 816
 817                         hw->phy.ops.write_reg(hw,
 818                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 819                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 820                                 autoneg_reg);
 821                 }
 822         }
 823
 824         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 825                 /* Set or unset auto-negotiation 1G advertisement */
 826                 hw->phy.ops.read_reg(hw,
 827                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 828                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                                      &autoneg_reg);
 830
 831                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 832                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 833                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 834
 835                 hw->phy.ops.write_reg(hw,
 836                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 837                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 838                                       autoneg_reg);
 839         }
 840
 841         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 842                 /* Set or unset auto-negotiation 100M advertisement */
 843                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 844                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 845                                      &autoneg_reg);
 846
 847                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 848                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 849                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 850                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 851
 852                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 853                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 854                                       autoneg_reg);
 855         }
 856
 857         /* Blocked by MNG FW so don't reset PHY */
 858         if (ixgbe_check_reset_blocked(hw))
 859                 return status;
 860
 861         /* Restart PHY auto-negotiation. */
 862         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 863                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 864
 865         autoneg_reg |= IXGBE_MII_RESTART;
 866
 867         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 868                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 869
 870         return status;
 871 }
 872
 873 /**
 874  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 875  *  @hw: pointer to hardware structure
 876  *  @speed: new link speed
 877  **/
 878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 879                                        ixgbe_link_speed speed,
 880                                        bool autoneg_wait_to_complete)
 881 {
 882         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 883
 884         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 885
 886         /*
 887          * Clear autoneg_advertised and set new values based on input link
 888          * speed.
 889          */
 890         hw->phy.autoneg_advertised = 0;
 891
 892         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 894
 895         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 896                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 897
 898         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 899                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 900
 901         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 902                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 903
 904         if (speed & IXGBE_LINK_SPEED_100_FULL)
 905                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 906
 907         if (speed & IXGBE_LINK_SPEED_10_FULL)
 908                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 909
 910         /* Setup link based on the new speed settings */
 911         ixgbe_setup_phy_link(hw);
 912
 913         return IXGBE_SUCCESS;
 914 }
 915
 916 /**
 917  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 918  * @hw: pointer to hardware structure
 919  *
 920  * Determines the supported link capabilities by reading the PHY auto
 921  * negotiation register.
 922  **/
 923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 924 {
 925         s32 status;
 926         u16 speed_ability;
 927
 928         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 929                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 930                                       &speed_ability);
 931         if (status)
 932                 return status;
 933
 934         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 935                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 936         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 937                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 938         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 939                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 940
 941         switch (hw->mac.type) {
 942         case ixgbe_mac_X550:
 943                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 944                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 945                 break;
 946         case ixgbe_mac_X550EM_x:
 947         case ixgbe_mac_X550EM_a:
 948                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 949                 break;
 950         default:
 951                 break;
 952         }
 953
 954         return status;
 955 }
 956
 957 /**
 958  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 959  *  @hw: pointer to hardware structure
 960  *  @speed: pointer to link speed
 961  *  @autoneg: boolean auto-negotiation value
 962  **/
 963 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 964                                                ixgbe_link_speed *speed,
 965                                                bool *autoneg)
 966 {
 967         s32 status = IXGBE_SUCCESS;
 968
 969         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 970
 971         *autoneg = true;
 972         if (!hw->phy.speeds_supported)
 973                 status = ixgbe_get_copper_speeds_supported(hw);
 974
 975         *speed = hw->phy.speeds_supported;
 976         return status;
 977 }
 978
 979 /**
 980  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 981  *  @hw: pointer to hardware structure
 982  *
 983  *  Reads the VS1 register to determine if link is up and the current speed for
 984  *  the PHY.
 985  **/
 986 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 987                              bool *link_up)
 988 {
 989         s32 status = IXGBE_SUCCESS;
 990         u32 time_out;
 991         u32 max_time_out = 10;
 992         u16 phy_link = 0;
 993         u16 phy_speed = 0;
 994         u16 phy_data = 0;
 995
 996         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 997
 998         /* Initialize speed and link to default case */
 999         *link_up = false;
1000         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1001
1002         /*
1003          * Check current speed and link status of the PHY register.
1004          * This is a vendor specific register and may have to
1005          * be changed for other copper PHYs.
1006          */
1007         for (time_out = 0; time_out < max_time_out; time_out++) {
1008                 usec_delay(10);
1009                 status = hw->phy.ops.read_reg(hw,
1010                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1011                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1012                                         &phy_data);
1013                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1014                 phy_speed = phy_data &
1015                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1016                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1017                         *link_up = true;
1018                         if (phy_speed ==
1019                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1020                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1021                         break;
1022                 }
1023         }
1024
1025         return status;
1026 }
1027
1028 /**
1029  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1030  *      @hw: pointer to hardware structure
1031  *
1032  *      Restart auto-negotiation and PHY and waits for completion.
1033  **/
1034 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1035 {
1036         s32 status = IXGBE_SUCCESS;
1037         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1038         bool autoneg = false;
1039         ixgbe_link_speed speed;
1040
1041         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1042
1043         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1044
1045         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1046                 /* Set or unset auto-negotiation 10G advertisement */
1047                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1048                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049                                      &autoneg_reg);
1050
1051                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1052                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1053                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1054
1055                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1056                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057                                       autoneg_reg);
1058         }
1059
1060         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1061                 /* Set or unset auto-negotiation 1G advertisement */
1062                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1063                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064                                      &autoneg_reg);
1065
1066                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1068                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1069
1070                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1071                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072                                       autoneg_reg);
1073         }
1074
1075         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1076                 /* Set or unset auto-negotiation 100M advertisement */
1077                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1078                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079                                      &autoneg_reg);
1080
1081                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1082                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1083                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1084
1085                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1086                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1087                                       autoneg_reg);
1088         }
1089
1090         /* Blocked by MNG FW so don't reset PHY */
1091         if (ixgbe_check_reset_blocked(hw))
1092                 return status;
1093
1094         /* Restart PHY auto-negotiation. */
1095         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1097
1098         autoneg_reg |= IXGBE_MII_RESTART;
1099
1100         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1101                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1102
1103         return status;
1104 }
1105
1106 /**
1107  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1108  *  @hw: pointer to hardware structure
1109  *  @firmware_version: pointer to the PHY Firmware Version
1110  **/
1111 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1112                                        u16 *firmware_version)
1113 {
1114         s32 status;
1115
1116         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1117
1118         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1119                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1120                                       firmware_version);
1121
1122         return status;
1123 }
1124
1125 /**
1126  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1127  *  @hw: pointer to hardware structure
1128  *  @firmware_version: pointer to the PHY Firmware Version
1129  **/
1130 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1131                                            u16 *firmware_version)
1132 {
1133         s32 status;
1134
1135         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1136
1137         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1138                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1139                                       firmware_version);
1140
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_reset_phy_nl - Performs a PHY reset
1146  *  @hw: pointer to hardware structure
1147  **/
1148 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1149 {
1150         u16 phy_offset, control, eword, edata, block_crc;
1151         bool end_data = false;
1152         u16 list_offset, data_offset;
1153         u16 phy_data = 0;
1154         s32 ret_val = IXGBE_SUCCESS;
1155         u32 i;
1156
1157         DEBUGFUNC("ixgbe_reset_phy_nl");
1158
1159         /* Blocked by MNG FW so bail */
1160         if (ixgbe_check_reset_blocked(hw))
1161                 goto out;
1162
1163         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165
1166         /* reset the PHY and poll for completion */
1167         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1169                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1170
1171         for (i = 0; i < 100; i++) {
1172                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1174                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1175                         break;
1176                 msec_delay(10);
1177         }
1178
1179         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1180                 DEBUGOUT("PHY reset did not complete.\n");
1181                 ret_val = IXGBE_ERR_PHY;
1182                 goto out;
1183         }
1184
1185         /* Get init offsets */
1186         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1187                                                       &data_offset);
1188         if (ret_val != IXGBE_SUCCESS)
1189                 goto out;
1190
1191         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192         data_offset++;
1193         while (!end_data) {
1194                 /*
1195                  * Read control word from PHY init contents offset
1196                  */
1197                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1198                 if (ret_val)
1199                         goto err_eeprom;
1200                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1201                            IXGBE_CONTROL_SHIFT_NL;
1202                 edata = eword & IXGBE_DATA_MASK_NL;
1203                 switch (control) {
1204                 case IXGBE_DELAY_NL:
1205                         data_offset++;
1206                         DEBUGOUT1("DELAY: %d MS\n", edata);
1207                         msec_delay(edata);
1208                         break;
1209                 case IXGBE_DATA_NL:
1210                         DEBUGOUT("DATA:\n");
1211                         data_offset++;
1212                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1213                                                       &phy_offset);
1214                         if (ret_val)
1215                                 goto err_eeprom;
1216                         data_offset++;
1217                         for (i = 0; i < edata; i++) {
1218                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1219                                                               &eword);
1220                                 if (ret_val)
1221                                         goto err_eeprom;
1222                                 hw->phy.ops.write_reg(hw, phy_offset,
1223                                                       IXGBE_TWINAX_DEV, eword);
1224                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1225                                           phy_offset);
1226                                 data_offset++;
1227                                 phy_offset++;
1228                         }
1229                         break;
1230                 case IXGBE_CONTROL_NL:
1231                         data_offset++;
1232                         DEBUGOUT("CONTROL:\n");
1233                         if (edata == IXGBE_CONTROL_EOL_NL) {
1234                                 DEBUGOUT("EOL\n");
1235                                 end_data = true;
1236                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1237                                 DEBUGOUT("SOL\n");
1238                         } else {
1239                                 DEBUGOUT("Bad control value\n");
1240                                 ret_val = IXGBE_ERR_PHY;
1241                                 goto out;
1242                         }
1243                         break;
1244                 default:
1245                         DEBUGOUT("Bad control type\n");
1246                         ret_val = IXGBE_ERR_PHY;
1247                         goto out;
1248                 }
1249         }
1250
1251 out:
1252         return ret_val;
1253
1254 err_eeprom:
1255         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1256                       "eeprom read at offset %d failed", data_offset);
1257         return IXGBE_ERR_PHY;
1258 }
1259
1260 /**
1261  *  ixgbe_identify_module_generic - Identifies module type
1262  *  @hw: pointer to hardware structure
1263  *
1264  *  Determines HW type and calls appropriate function.
1265  **/
1266 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1267 {
1268         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1269
1270         DEBUGFUNC("ixgbe_identify_module_generic");
1271
1272         switch (hw->mac.ops.get_media_type(hw)) {
1273         case ixgbe_media_type_fiber:
1274                 status = ixgbe_identify_sfp_module_generic(hw);
1275                 break;
1276
1277         case ixgbe_media_type_fiber_qsfp:
1278                 status = ixgbe_identify_qsfp_module_generic(hw);
1279                 break;
1280
1281         default:
1282                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1283                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1284                 break;
1285         }
1286
1287         return status;
1288 }
1289
1290 /**
1291  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1292  *  @hw: pointer to hardware structure
1293  *
1294  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1295  **/
1296 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1297 {
1298         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1299         u32 vendor_oui = 0;
1300         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1301         u8 identifier = 0;
1302         u8 comp_codes_1g = 0;
1303         u8 comp_codes_10g = 0;
1304         u8 oui_bytes[3] = {0, 0, 0};
1305         u8 cable_tech = 0;
1306         u8 cable_spec = 0;
1307         u16 enforce_sfp = 0;
1308
1309         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1310
1311         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1312                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1313                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1314                 goto out;
1315         }
1316
1317         /* LAN ID is needed for I2C access */
1318         hw->mac.ops.set_lan_id(hw);
1319
1320         status = hw->phy.ops.read_i2c_eeprom(hw,
1321                                              IXGBE_SFF_IDENTIFIER,
1322                                              &identifier);
1323
1324         if (status != IXGBE_SUCCESS)
1325                 goto err_read_i2c_eeprom;
1326
1327         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1328                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1329                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1330         } else {
1331                 status = hw->phy.ops.read_i2c_eeprom(hw,
1332                                                      IXGBE_SFF_1GBE_COMP_CODES,
1333                                                      &comp_codes_1g);
1334
1335                 if (status != IXGBE_SUCCESS)
1336                         goto err_read_i2c_eeprom;
1337
1338                 status = hw->phy.ops.read_i2c_eeprom(hw,
1339                                                      IXGBE_SFF_10GBE_COMP_CODES,
1340                                                      &comp_codes_10g);
1341
1342                 if (status != IXGBE_SUCCESS)
1343                         goto err_read_i2c_eeprom;
1344                 status = hw->phy.ops.read_i2c_eeprom(hw,
1345                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1346                                                      &cable_tech);
1347
1348                 if (status != IXGBE_SUCCESS)
1349                         goto err_read_i2c_eeprom;
1350
1351                  /* ID Module
1352                   * =========
1353                   * 0   SFP_DA_CU
1354                   * 1   SFP_SR
1355                   * 2   SFP_LR
1356                   * 3   SFP_DA_CORE0 - 82599-specific
1357                   * 4   SFP_DA_CORE1 - 82599-specific
1358                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1359                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1360                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1361                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1362                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1363                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1364                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1365                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1366                   */
1367                 if (hw->mac.type == ixgbe_mac_82598EB) {
1368                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1369                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1371                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1373                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1374                         else
1375                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1376                 } else {
1377                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1378                                 if (hw->bus.lan_id == 0)
1379                                         hw->phy.sfp_type =
1380                                                      ixgbe_sfp_type_da_cu_core0;
1381                                 else
1382                                         hw->phy.sfp_type =
1383                                                      ixgbe_sfp_type_da_cu_core1;
1384                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1385                                 hw->phy.ops.read_i2c_eeprom(
1386                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1387                                                 &cable_spec);
1388                                 if (cable_spec &
1389                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1390                                         if (hw->bus.lan_id == 0)
1391                                                 hw->phy.sfp_type =
1392                                                 ixgbe_sfp_type_da_act_lmt_core0;
1393                                         else
1394                                                 hw->phy.sfp_type =
1395                                                 ixgbe_sfp_type_da_act_lmt_core1;
1396                                 } else {
1397                                         hw->phy.sfp_type =
1398                                                         ixgbe_sfp_type_unknown;
1399                                 }
1400                         } else if (comp_codes_10g &
1401                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1402                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1403                                 if (hw->bus.lan_id == 0)
1404                                         hw->phy.sfp_type =
1405                                                       ixgbe_sfp_type_srlr_core0;
1406                                 else
1407                                         hw->phy.sfp_type =
1408                                                       ixgbe_sfp_type_srlr_core1;
1409                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1410                                 if (hw->bus.lan_id == 0)
1411                                         hw->phy.sfp_type =
1412                                                 ixgbe_sfp_type_1g_cu_core0;
1413                                 else
1414                                         hw->phy.sfp_type =
1415                                                 ixgbe_sfp_type_1g_cu_core1;
1416                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1417                                 if (hw->bus.lan_id == 0)
1418                                         hw->phy.sfp_type =
1419                                                 ixgbe_sfp_type_1g_sx_core0;
1420                                 else
1421                                         hw->phy.sfp_type =
1422                                                 ixgbe_sfp_type_1g_sx_core1;
1423                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1424                                 if (hw->bus.lan_id == 0)
1425                                         hw->phy.sfp_type =
1426                                                 ixgbe_sfp_type_1g_lx_core0;
1427                                 else
1428                                         hw->phy.sfp_type =
1429                                                 ixgbe_sfp_type_1g_lx_core1;
1430                         } else {
1431                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1432                         }
1433                 }
1434
1435                 if (hw->phy.sfp_type != stored_sfp_type)
1436                         hw->phy.sfp_setup_needed = true;
1437
1438                 /* Determine if the SFP+ PHY is dual speed or not. */
1439                 hw->phy.multispeed_fiber = false;
1440                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1441                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1442                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1443                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1444                         hw->phy.multispeed_fiber = true;
1445
1446                 /* Determine PHY vendor */
1447                 if (hw->phy.type != ixgbe_phy_nl) {
1448                         hw->phy.id = identifier;
1449                         status = hw->phy.ops.read_i2c_eeprom(hw,
1450                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1451                                                     &oui_bytes[0]);
1452
1453                         if (status != IXGBE_SUCCESS)
1454                                 goto err_read_i2c_eeprom;
1455
1456                         status = hw->phy.ops.read_i2c_eeprom(hw,
1457                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1458                                                     &oui_bytes[1]);
1459
1460                         if (status != IXGBE_SUCCESS)
1461                                 goto err_read_i2c_eeprom;
1462
1463                         status = hw->phy.ops.read_i2c_eeprom(hw,
1464                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1465                                                     &oui_bytes[2]);
1466
1467                         if (status != IXGBE_SUCCESS)
1468                                 goto err_read_i2c_eeprom;
1469
1470                         vendor_oui =
1471                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1472                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1473                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1474
1475                         switch (vendor_oui) {
1476                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1477                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1478                                         hw->phy.type =
1479                                                     ixgbe_phy_sfp_passive_tyco;
1480                                 break;
1481                         case IXGBE_SFF_VENDOR_OUI_FTL:
1482                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1484                                 else
1485                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1486                                 break;
1487                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1488                                 hw->phy.type = ixgbe_phy_sfp_avago;
1489                                 break;
1490                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1491                                 hw->phy.type = ixgbe_phy_sfp_intel;
1492                                 break;
1493                         default:
1494                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1495                                         hw->phy.type =
1496                                                  ixgbe_phy_sfp_passive_unknown;
1497                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1498                                         hw->phy.type =
1499                                                 ixgbe_phy_sfp_active_unknown;
1500                                 else
1501                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1502                                 break;
1503                         }
1504                 }
1505
1506                 /* Allow any DA cable vendor */
1507                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1508                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1509                         status = IXGBE_SUCCESS;
1510                         goto out;
1511                 }
1512
1513                 /* Verify supported 1G SFP modules */
1514                 if (comp_codes_10g == 0 &&
1515                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1517                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1518                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1519                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1520                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1521                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1522                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1523                         goto out;
1524                 }
1525
1526                 /* Anything else 82598-based is supported */
1527                 if (hw->mac.type == ixgbe_mac_82598EB) {
1528                         status = IXGBE_SUCCESS;
1529                         goto out;
1530                 }
1531
1532                 ixgbe_get_device_caps(hw, &enforce_sfp);
1533                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1534                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1537                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1539                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540                         /* Make sure we're a supported PHY type */
1541                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1542                                 status = IXGBE_SUCCESS;
1543                         } else {
1544                                 if (hw->allow_unsupported_sfp == true) {
1545                                         EWARN(hw,
1546                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1547                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1548                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1549                                         status = IXGBE_SUCCESS;
1550                                 } else {
1551                                         DEBUGOUT("SFP+ module not supported\n");
1552                                         hw->phy.type =
1553                                                 ixgbe_phy_sfp_unsupported;
1554                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1555                                 }
1556                         }
1557                 } else {
1558                         status = IXGBE_SUCCESS;
1559                 }
1560         }
1561
1562 out:
1563         return status;
1564
1565 err_read_i2c_eeprom:
1566         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1567         if (hw->phy.type != ixgbe_phy_nl) {
1568                 hw->phy.id = 0;
1569                 hw->phy.type = ixgbe_phy_unknown;
1570         }
1571         return IXGBE_ERR_SFP_NOT_PRESENT;
1572 }
1573
1574 /**
1575  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1576  *  @hw: pointer to hardware structure
1577  *
1578  *  Determines physical layer capabilities of the current SFP.
1579  */
1580 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1581 {
1582         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1583         u8 comp_codes_10g = 0;
1584         u8 comp_codes_1g = 0;
1585
1586         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1587
1588         hw->phy.ops.identify_sfp(hw);
1589         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1590                 return physical_layer;
1591
1592         switch (hw->phy.type) {
1593         case ixgbe_phy_sfp_passive_tyco:
1594         case ixgbe_phy_sfp_passive_unknown:
1595         case ixgbe_phy_qsfp_passive_unknown:
1596                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1597                 break;
1598         case ixgbe_phy_sfp_ftl_active:
1599         case ixgbe_phy_sfp_active_unknown:
1600         case ixgbe_phy_qsfp_active_unknown:
1601                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1602                 break;
1603         case ixgbe_phy_sfp_avago:
1604         case ixgbe_phy_sfp_ftl:
1605         case ixgbe_phy_sfp_intel:
1606         case ixgbe_phy_sfp_unknown:
1607                 hw->phy.ops.read_i2c_eeprom(hw,
1608                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1609                 hw->phy.ops.read_i2c_eeprom(hw,
1610                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1611                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1612                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1613                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1614                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1615                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1616                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1617                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1618                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1619                 break;
1620         case ixgbe_phy_qsfp_intel:
1621         case ixgbe_phy_qsfp_unknown:
1622                 hw->phy.ops.read_i2c_eeprom(hw,
1623                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1624                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1625                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1626                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1627                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1628                 break;
1629         default:
1630                 break;
1631         }
1632
1633         return physical_layer;
1634 }
1635
1636 /**
1637  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1638  *  @hw: pointer to hardware structure
1639  *
1640  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1641  **/
1642 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1643 {
1644         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1645         u32 vendor_oui = 0;
1646         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1647         u8 identifier = 0;
1648         u8 comp_codes_1g = 0;
1649         u8 comp_codes_10g = 0;
1650         u8 oui_bytes[3] = {0, 0, 0};
1651         u16 enforce_sfp = 0;
1652         u8 connector = 0;
1653         u8 cable_length = 0;
1654         u8 device_tech = 0;
1655         bool active_cable = false;
1656
1657         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1658
1659         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1660                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1661                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1662                 goto out;
1663         }
1664
1665         /* LAN ID is needed for I2C access */
1666         hw->mac.ops.set_lan_id(hw);
1667
1668         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1669                                              &identifier);
1670
1671         if (status != IXGBE_SUCCESS)
1672                 goto err_read_i2c_eeprom;
1673
1674         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1675                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1676                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1677                 goto out;
1678         }
1679
1680         hw->phy.id = identifier;
1681
1682         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1683                                              &comp_codes_10g);
1684
1685         if (status != IXGBE_SUCCESS)
1686                 goto err_read_i2c_eeprom;
1687
1688         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1689                                              &comp_codes_1g);
1690
1691         if (status != IXGBE_SUCCESS)
1692                 goto err_read_i2c_eeprom;
1693
1694         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1695                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1696                 if (hw->bus.lan_id == 0)
1697                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1698                 else
1699                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1700         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1701                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1702                 if (hw->bus.lan_id == 0)
1703                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1704                 else
1705                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1706         } else {
1707                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1708                         active_cable = true;
1709
1710                 if (!active_cable) {
1711                         /* check for active DA cables that pre-date
1712                          * SFF-8436 v3.6 */
1713                         hw->phy.ops.read_i2c_eeprom(hw,
1714                                         IXGBE_SFF_QSFP_CONNECTOR,
1715                                         &connector);
1716
1717                         hw->phy.ops.read_i2c_eeprom(hw,
1718                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1719                                         &cable_length);
1720
1721                         hw->phy.ops.read_i2c_eeprom(hw,
1722                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1723                                         &device_tech);
1724
1725                         if ((connector ==
1726                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1727                             (cable_length > 0) &&
1728                             ((device_tech >> 4) ==
1729                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1730                                 active_cable = true;
1731                 }
1732
1733                 if (active_cable) {
1734                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1735                         if (hw->bus.lan_id == 0)
1736                                 hw->phy.sfp_type =
1737                                                 ixgbe_sfp_type_da_act_lmt_core0;
1738                         else
1739                                 hw->phy.sfp_type =
1740                                                 ixgbe_sfp_type_da_act_lmt_core1;
1741                 } else {
1742                         /* unsupported module type */
1743                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1744                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1745                         goto out;
1746                 }
1747         }
1748
1749         if (hw->phy.sfp_type != stored_sfp_type)
1750                 hw->phy.sfp_setup_needed = true;
1751
1752         /* Determine if the QSFP+ PHY is dual speed or not. */
1753         hw->phy.multispeed_fiber = false;
1754         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1755            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1756            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1757            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1758                 hw->phy.multispeed_fiber = true;
1759
1760         /* Determine PHY vendor for optical modules */
1761         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1762                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1763                 status = hw->phy.ops.read_i2c_eeprom(hw,
1764                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1765                                             &oui_bytes[0]);
1766
1767                 if (status != IXGBE_SUCCESS)
1768                         goto err_read_i2c_eeprom;
1769
1770                 status = hw->phy.ops.read_i2c_eeprom(hw,
1771                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1772                                             &oui_bytes[1]);
1773
1774                 if (status != IXGBE_SUCCESS)
1775                         goto err_read_i2c_eeprom;
1776
1777                 status = hw->phy.ops.read_i2c_eeprom(hw,
1778                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1779                                             &oui_bytes[2]);
1780
1781                 if (status != IXGBE_SUCCESS)
1782                         goto err_read_i2c_eeprom;
1783
1784                 vendor_oui =
1785                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1786                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1787                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1788
1789                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1790                         hw->phy.type = ixgbe_phy_qsfp_intel;
1791                 else
1792                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1793
1794                 ixgbe_get_device_caps(hw, &enforce_sfp);
1795                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1796                         /* Make sure we're a supported PHY type */
1797                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1798                                 status = IXGBE_SUCCESS;
1799                         } else {
1800                                 if (hw->allow_unsupported_sfp == true) {
1801                                         EWARN(hw,
1802                                                 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1803                                                 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1804                                                 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1805                                         status = IXGBE_SUCCESS;
1806                                 } else {
1807                                         DEBUGOUT("QSFP module not supported\n");
1808                                         hw->phy.type =
1809                                                 ixgbe_phy_sfp_unsupported;
1810                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1811                                 }
1812                         }
1813                 } else {
1814                         status = IXGBE_SUCCESS;
1815                 }
1816         }
1817
1818 out:
1819         return status;
1820
1821 err_read_i2c_eeprom:
1822         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1823         hw->phy.id = 0;
1824         hw->phy.type = ixgbe_phy_unknown;
1825
1826         return IXGBE_ERR_SFP_NOT_PRESENT;
1827 }
1828
1829 /**
1830  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1831  *  @hw: pointer to hardware structure
1832  *  @list_offset: offset to the SFP ID list
1833  *  @data_offset: offset to the SFP data block
1834  *
1835  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1836  *  so it returns the offsets to the phy init sequence block.
1837  **/
1838 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1839                                         u16 *list_offset,
1840                                         u16 *data_offset)
1841 {
1842         u16 sfp_id;
1843         u16 sfp_type = hw->phy.sfp_type;
1844
1845         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1846
1847         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1848                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1849
1850         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1851                 return IXGBE_ERR_SFP_NOT_PRESENT;
1852
1853         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1854             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1855                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1856
1857         /*
1858          * Limiting active cables and 1G Phys must be initialized as
1859          * SR modules
1860          */
1861         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1862             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1863             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1864             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1865                 sfp_type = ixgbe_sfp_type_srlr_core0;
1866         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1867                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1868                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1869                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1870                 sfp_type = ixgbe_sfp_type_srlr_core1;
1871
1872         /* Read offset to PHY init contents */
1873         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1874                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1875                               "eeprom read at offset %d failed",
1876                               IXGBE_PHY_INIT_OFFSET_NL);
1877                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1878         }
1879
1880         if ((!*list_offset) || (*list_offset == 0xFFFF))
1881                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1882
1883         /* Shift offset to first ID word */
1884         (*list_offset)++;
1885
1886         /*
1887          * Find the matching SFP ID in the EEPROM
1888          * and program the init sequence
1889          */
1890         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1891                 goto err_phy;
1892
1893         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1894                 if (sfp_id == sfp_type) {
1895                         (*list_offset)++;
1896                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1897                                 goto err_phy;
1898                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1899                                 DEBUGOUT("SFP+ module not supported\n");
1900                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1901                         } else {
1902                                 break;
1903                         }
1904                 } else {
1905                         (*list_offset) += 2;
1906                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1907                                 goto err_phy;
1908                 }
1909         }
1910
1911         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1912                 DEBUGOUT("No matching SFP+ module found\n");
1913                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1914         }
1915
1916         return IXGBE_SUCCESS;
1917
1918 err_phy:
1919         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1920                       "eeprom read at offset %d failed", *list_offset);
1921         return IXGBE_ERR_PHY;
1922 }
1923
1924 /**
1925  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1926  *  @hw: pointer to hardware structure
1927  *  @byte_offset: EEPROM byte offset to read
1928  *  @eeprom_data: value read
1929  *
1930  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1931  **/
1932 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1933                                   u8 *eeprom_data)
1934 {
1935         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1936
1937         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1938                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1939                                          eeprom_data);
1940 }
1941
1942 /**
1943  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1944  *  @hw: pointer to hardware structure
1945  *  @byte_offset: byte offset at address 0xA2
1946  *  @eeprom_data: value read
1947  *
1948  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1949  **/
1950 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1951                                           u8 *sff8472_data)
1952 {
1953         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1954                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1955                                          sff8472_data);
1956 }
1957
1958 /**
1959  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1960  *  @hw: pointer to hardware structure
1961  *  @byte_offset: EEPROM byte offset to write
1962  *  @eeprom_data: value to write
1963  *
1964  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1965  **/
1966 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1967                                    u8 eeprom_data)
1968 {
1969         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1970
1971         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1972                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1973                                           eeprom_data);
1974 }
1975
1976 /**
1977  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1978  * @hw: pointer to hardware structure
1979  * @offset: eeprom offset to be read
1980  * @addr: I2C address to be read
1981  */
1982 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1983 {
1984         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1985             offset == IXGBE_SFF_IDENTIFIER &&
1986             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1987                 return true;
1988         return false;
1989 }
1990
1991 /**
1992  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1993  *  @hw: pointer to hardware structure
1994  *  @byte_offset: byte offset to read
1995  *  @data: value read
1996  *  @lock: true if to take and release semaphore
1997  *
1998  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1999  *  a specified device address.
2000  **/
2001 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2002                                            u8 dev_addr, u8 *data, bool lock)
2003 {
2004         s32 status;
2005         u32 max_retry = 10;
2006         u32 retry = 0;
2007         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2008         bool nack = 1;
2009         *data = 0;
2010
2011         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2012
2013         if (hw->mac.type >= ixgbe_mac_X550)
2014                 max_retry = 3;
2015         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2016                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2017
2018         do {
2019                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2020                         return IXGBE_ERR_SWFW_SYNC;
2021
2022                 ixgbe_i2c_start(hw);
2023
2024                 /* Device Address and write indication */
2025                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2026                 if (status != IXGBE_SUCCESS)
2027                         goto fail;
2028
2029                 status = ixgbe_get_i2c_ack(hw);
2030                 if (status != IXGBE_SUCCESS)
2031                         goto fail;
2032
2033                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_get_i2c_ack(hw);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 ixgbe_i2c_start(hw);
2042
2043                 /* Device Address and read indication */
2044                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2045                 if (status != IXGBE_SUCCESS)
2046                         goto fail;
2047
2048                 status = ixgbe_get_i2c_ack(hw);
2049                 if (status != IXGBE_SUCCESS)
2050                         goto fail;
2051
2052                 status = ixgbe_clock_in_i2c_byte(hw, data);
2053                 if (status != IXGBE_SUCCESS)
2054                         goto fail;
2055
2056                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2057                 if (status != IXGBE_SUCCESS)
2058                         goto fail;
2059
2060                 ixgbe_i2c_stop(hw);
2061                 if (lock)
2062                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063                 return IXGBE_SUCCESS;
2064
2065 fail:
2066                 ixgbe_i2c_bus_clear(hw);
2067                 if (lock) {
2068                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2069                         msec_delay(100);
2070                 }
2071                 retry++;
2072                 if (retry < max_retry)
2073                         DEBUGOUT("I2C byte read error - Retrying.\n");
2074                 else
2075                         DEBUGOUT("I2C byte read error.\n");
2076
2077         } while (retry < max_retry);
2078
2079         return status;
2080 }
2081
2082 /**
2083  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2084  *  @hw: pointer to hardware structure
2085  *  @byte_offset: byte offset to read
2086  *  @data: value read
2087  *
2088  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2089  *  a specified device address.
2090  **/
2091 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2092                                 u8 dev_addr, u8 *data)
2093 {
2094         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2095                                                data, true);
2096 }
2097
2098 /**
2099  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2100  *  @hw: pointer to hardware structure
2101  *  @byte_offset: byte offset to read
2102  *  @data: value read
2103  *
2104  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2105  *  a specified device address.
2106  **/
2107 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2108                                          u8 dev_addr, u8 *data)
2109 {
2110         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111                                                data, false);
2112 }
2113
2114 /**
2115  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2116  *  @hw: pointer to hardware structure
2117  *  @byte_offset: byte offset to write
2118  *  @data: value to write
2119  *  @lock: true if to take and release semaphore
2120  *
2121  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2122  *  a specified device address.
2123  **/
2124 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2125                                             u8 dev_addr, u8 data, bool lock)
2126 {
2127         s32 status;
2128         u32 max_retry = 1;
2129         u32 retry = 0;
2130         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2131
2132         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2133
2134         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2135             IXGBE_SUCCESS)
2136                 return IXGBE_ERR_SWFW_SYNC;
2137
2138         do {
2139                 ixgbe_i2c_start(hw);
2140
2141                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2142                 if (status != IXGBE_SUCCESS)
2143                         goto fail;
2144
2145                 status = ixgbe_get_i2c_ack(hw);
2146                 if (status != IXGBE_SUCCESS)
2147                         goto fail;
2148
2149                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2150                 if (status != IXGBE_SUCCESS)
2151                         goto fail;
2152
2153                 status = ixgbe_get_i2c_ack(hw);
2154                 if (status != IXGBE_SUCCESS)
2155                         goto fail;
2156
2157                 status = ixgbe_clock_out_i2c_byte(hw, data);
2158                 if (status != IXGBE_SUCCESS)
2159                         goto fail;
2160
2161                 status = ixgbe_get_i2c_ack(hw);
2162                 if (status != IXGBE_SUCCESS)
2163                         goto fail;
2164
2165                 ixgbe_i2c_stop(hw);
2166                 if (lock)
2167                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2168                 return IXGBE_SUCCESS;
2169
2170 fail:
2171                 ixgbe_i2c_bus_clear(hw);
2172                 retry++;
2173                 if (retry < max_retry)
2174                         DEBUGOUT("I2C byte write error - Retrying.\n");
2175                 else
2176                         DEBUGOUT("I2C byte write error.\n");
2177         } while (retry < max_retry);
2178
2179         if (lock)
2180                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2181
2182         return status;
2183 }
2184
2185 /**
2186  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2187  *  @hw: pointer to hardware structure
2188  *  @byte_offset: byte offset to write
2189  *  @data: value to write
2190  *
2191  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2192  *  a specified device address.
2193  **/
2194 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2195                                  u8 dev_addr, u8 data)
2196 {
2197         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2198                                                 data, true);
2199 }
2200
2201 /**
2202  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2203  *  @hw: pointer to hardware structure
2204  *  @byte_offset: byte offset to write
2205  *  @data: value to write
2206  *
2207  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2208  *  a specified device address.
2209  **/
2210 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2211                                           u8 dev_addr, u8 data)
2212 {
2213         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2214                                                 data, false);
2215 }
2216
2217 /**
2218  *  ixgbe_i2c_start - Sets I2C start condition
2219  *  @hw: pointer to hardware structure
2220  *
2221  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2222  *  Set bit-bang mode on X550 hardware.
2223  **/
2224 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2225 {
2226         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2227
2228         DEBUGFUNC("ixgbe_i2c_start");
2229
2230         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2231
2232         /* Start condition must begin with data and clock high */
2233         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2234         ixgbe_raise_i2c_clk(hw, &i2cctl);
2235
2236         /* Setup time for start condition (4.7us) */
2237         usec_delay(IXGBE_I2C_T_SU_STA);
2238
2239         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2240
2241         /* Hold time for start condition (4us) */
2242         usec_delay(IXGBE_I2C_T_HD_STA);
2243
2244         ixgbe_lower_i2c_clk(hw, &i2cctl);
2245
2246         /* Minimum low period of clock is 4.7 us */
2247         usec_delay(IXGBE_I2C_T_LOW);
2248
2249 }
2250
2251 /**
2252  *  ixgbe_i2c_stop - Sets I2C stop condition
2253  *  @hw: pointer to hardware structure
2254  *
2255  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2256  *  Disables bit-bang mode and negates data output enable on X550
2257  *  hardware.
2258  **/
2259 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2260 {
2261         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2262         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2263         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2264         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2265
2266         DEBUGFUNC("ixgbe_i2c_stop");
2267
2268         /* Stop condition must begin with data low and clock high */
2269         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2270         ixgbe_raise_i2c_clk(hw, &i2cctl);
2271
2272         /* Setup time for stop condition (4us) */
2273         usec_delay(IXGBE_I2C_T_SU_STO);
2274
2275         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2276
2277         /* bus free time between stop and start (4.7us)*/
2278         usec_delay(IXGBE_I2C_T_BUF);
2279
2280         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2281                 i2cctl &= ~bb_en_bit;
2282                 i2cctl |= data_oe_bit | clk_oe_bit;
2283                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2284                 IXGBE_WRITE_FLUSH(hw);
2285         }
2286 }
2287
2288 /**
2289  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2290  *  @hw: pointer to hardware structure
2291  *  @data: data byte to clock in
2292  *
2293  *  Clocks in one byte data via I2C data/clock
2294  **/
2295 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2296 {
2297         s32 i;
2298         bool bit = 0;
2299
2300         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2301
2302         *data = 0;
2303         for (i = 7; i >= 0; i--) {
2304                 ixgbe_clock_in_i2c_bit(hw, &bit);
2305                 *data |= bit << i;
2306         }
2307
2308         return IXGBE_SUCCESS;
2309 }
2310
2311 /**
2312  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2313  *  @hw: pointer to hardware structure
2314  *  @data: data byte clocked out
2315  *
2316  *  Clocks out one byte data via I2C data/clock
2317  **/
2318 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2319 {
2320         s32 status = IXGBE_SUCCESS;
2321         s32 i;
2322         u32 i2cctl;
2323         bool bit;
2324
2325         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2326
2327         for (i = 7; i >= 0; i--) {
2328                 bit = (data >> i) & 0x1;
2329                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2330
2331                 if (status != IXGBE_SUCCESS)
2332                         break;
2333         }
2334
2335         /* Release SDA line (set high) */
2336         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2337         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2338         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2339         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2340         IXGBE_WRITE_FLUSH(hw);
2341
2342         return status;
2343 }
2344
2345 /**
2346  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2347  *  @hw: pointer to hardware structure
2348  *
2349  *  Clocks in/out one bit via I2C data/clock
2350  **/
2351 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2352 {
2353         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2354         s32 status = IXGBE_SUCCESS;
2355         u32 i = 0;
2356         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2357         u32 timeout = 10;
2358         bool ack = 1;
2359
2360         DEBUGFUNC("ixgbe_get_i2c_ack");
2361
2362         if (data_oe_bit) {
2363                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2364                 i2cctl |= data_oe_bit;
2365                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2366                 IXGBE_WRITE_FLUSH(hw);
2367         }
2368         ixgbe_raise_i2c_clk(hw, &i2cctl);
2369
2370         /* Minimum high period of clock is 4us */
2371         usec_delay(IXGBE_I2C_T_HIGH);
2372
2373         /* Poll for ACK.  Note that ACK in I2C spec is
2374          * transition from 1 to 0 */
2375         for (i = 0; i < timeout; i++) {
2376                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2377                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2378
2379                 usec_delay(1);
2380                 if (!ack)
2381                         break;
2382         }
2383
2384         if (ack) {
2385                 DEBUGOUT("I2C ack was not received.\n");
2386                 status = IXGBE_ERR_I2C;
2387         }
2388
2389         ixgbe_lower_i2c_clk(hw, &i2cctl);
2390
2391         /* Minimum low period of clock is 4.7 us */
2392         usec_delay(IXGBE_I2C_T_LOW);
2393
2394         return status;
2395 }
2396
2397 /**
2398  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2399  *  @hw: pointer to hardware structure
2400  *  @data: read data value
2401  *
2402  *  Clocks in one bit via I2C data/clock
2403  **/
2404 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2405 {
2406         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2407         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2408
2409         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2410
2411         if (data_oe_bit) {
2412                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2413                 i2cctl |= data_oe_bit;
2414                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2415                 IXGBE_WRITE_FLUSH(hw);
2416         }
2417         ixgbe_raise_i2c_clk(hw, &i2cctl);
2418
2419         /* Minimum high period of clock is 4us */
2420         usec_delay(IXGBE_I2C_T_HIGH);
2421
2422         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2423         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2424
2425         ixgbe_lower_i2c_clk(hw, &i2cctl);
2426
2427         /* Minimum low period of clock is 4.7 us */
2428         usec_delay(IXGBE_I2C_T_LOW);
2429
2430         return IXGBE_SUCCESS;
2431 }
2432
2433 /**
2434  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2435  *  @hw: pointer to hardware structure
2436  *  @data: data value to write
2437  *
2438  *  Clocks out one bit via I2C data/clock
2439  **/
2440 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2441 {
2442         s32 status;
2443         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2444
2445         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2446
2447         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2448         if (status == IXGBE_SUCCESS) {
2449                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2450
2451                 /* Minimum high period of clock is 4us */
2452                 usec_delay(IXGBE_I2C_T_HIGH);
2453
2454                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2455
2456                 /* Minimum low period of clock is 4.7 us.
2457                  * This also takes care of the data hold time.
2458                  */
2459                 usec_delay(IXGBE_I2C_T_LOW);
2460         } else {
2461                 status = IXGBE_ERR_I2C;
2462                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2463                              "I2C data was not set to %X\n", data);
2464         }
2465
2466         return status;
2467 }
2468
2469 /**
2470  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2471  *  @hw: pointer to hardware structure
2472  *  @i2cctl: Current value of I2CCTL register
2473  *
2474  *  Raises the I2C clock line '0'->'1'
2475  *  Negates the I2C clock output enable on X550 hardware.
2476  **/
2477 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2478 {
2479         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2480         u32 i = 0;
2481         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2482         u32 i2cctl_r = 0;
2483
2484         DEBUGFUNC("ixgbe_raise_i2c_clk");
2485
2486         if (clk_oe_bit) {
2487                 *i2cctl |= clk_oe_bit;
2488                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2489         }
2490
2491         for (i = 0; i < timeout; i++) {
2492                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2493
2494                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2495                 IXGBE_WRITE_FLUSH(hw);
2496                 /* SCL rise time (1000ns) */
2497                 usec_delay(IXGBE_I2C_T_RISE);
2498
2499                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2500                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2501                         break;
2502         }
2503 }
2504
2505 /**
2506  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2507  *  @hw: pointer to hardware structure
2508  *  @i2cctl: Current value of I2CCTL register
2509  *
2510  *  Lowers the I2C clock line '1'->'0'
2511  *  Asserts the I2C clock output enable on X550 hardware.
2512  **/
2513 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2514 {
2515         DEBUGFUNC("ixgbe_lower_i2c_clk");
2516
2517         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2518         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2519
2520         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2521         IXGBE_WRITE_FLUSH(hw);
2522
2523         /* SCL fall time (300ns) */
2524         usec_delay(IXGBE_I2C_T_FALL);
2525 }
2526
2527 /**
2528  *  ixgbe_set_i2c_data - Sets the I2C data bit
2529  *  @hw: pointer to hardware structure
2530  *  @i2cctl: Current value of I2CCTL register
2531  *  @data: I2C data value (0 or 1) to set
2532  *
2533  *  Sets the I2C data bit
2534  *  Asserts the I2C data output enable on X550 hardware.
2535  **/
2536 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2537 {
2538         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2539         s32 status = IXGBE_SUCCESS;
2540
2541         DEBUGFUNC("ixgbe_set_i2c_data");
2542
2543         if (data)
2544                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2545         else
2546                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2547         *i2cctl &= ~data_oe_bit;
2548
2549         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2550         IXGBE_WRITE_FLUSH(hw);
2551
2552         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2553         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2554
2555         if (!data)      /* Can't verify data in this case */
2556                 return IXGBE_SUCCESS;
2557         if (data_oe_bit) {
2558                 *i2cctl |= data_oe_bit;
2559                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2560                 IXGBE_WRITE_FLUSH(hw);
2561         }
2562
2563         /* Verify data was set correctly */
2564         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2565         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2566                 status = IXGBE_ERR_I2C;
2567                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2568                              "Error - I2C data was not set to %X.\n",
2569                              data);
2570         }
2571
2572         return status;
2573 }
2574
2575 /**
2576  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2577  *  @hw: pointer to hardware structure
2578  *  @i2cctl: Current value of I2CCTL register
2579  *
2580  *  Returns the I2C data bit value
2581  *  Negates the I2C data output enable on X550 hardware.
2582  **/
2583 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2584 {
2585         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2586         bool data;
2587
2588         DEBUGFUNC("ixgbe_get_i2c_data");
2589
2590         if (data_oe_bit) {
2591                 *i2cctl |= data_oe_bit;
2592                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2593                 IXGBE_WRITE_FLUSH(hw);
2594                 usec_delay(IXGBE_I2C_T_FALL);
2595         }
2596
2597         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2598                 data = 1;
2599         else
2600                 data = 0;
2601
2602         return data;
2603 }
2604
2605 /**
2606  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2607  *  @hw: pointer to hardware structure
2608  *
2609  *  Clears the I2C bus by sending nine clock pulses.
2610  *  Used when data line is stuck low.
2611  **/
2612 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2613 {
2614         u32 i2cctl;
2615         u32 i;
2616
2617         DEBUGFUNC("ixgbe_i2c_bus_clear");
2618
2619         ixgbe_i2c_start(hw);
2620         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2621
2622         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2623
2624         for (i = 0; i < 9; i++) {
2625                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2626
2627                 /* Min high period of clock is 4us */
2628                 usec_delay(IXGBE_I2C_T_HIGH);
2629
2630                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2631
2632                 /* Min low period of clock is 4.7us*/
2633                 usec_delay(IXGBE_I2C_T_LOW);
2634         }
2635
2636         ixgbe_i2c_start(hw);
2637
2638         /* Put the i2c bus back to default state */
2639         ixgbe_i2c_stop(hw);
2640 }
2641
2642 /**
2643  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2644  *  @hw: pointer to hardware structure
2645  *
2646  *  Checks if the LASI temp alarm status was triggered due to overtemp
2647  **/
2648 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2649 {
2650         s32 status = IXGBE_SUCCESS;
2651         u16 phy_data = 0;
2652
2653         DEBUGFUNC("ixgbe_tn_check_overtemp");
2654
2655         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2656                 goto out;
2657
2658         /* Check that the LASI temp alarm status was triggered */
2659         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2660                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2661
2662         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2663                 goto out;
2664
2665         status = IXGBE_ERR_OVERTEMP;
2666         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2667 out:
2668         return status;
2669 }
2670
2671 /**
2672  * ixgbe_set_copper_phy_power - Control power for copper phy
2673  * @hw: pointer to hardware structure
2674  * @on: true for on, false for off
2675  */
2676 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2677 {
2678         u32 status;
2679         u16 reg;
2680
2681         if (!on && ixgbe_mng_present(hw))
2682                 return 0;
2683
2684         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2685                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2686                                       &reg);
2687         if (status)
2688                 return status;
2689
2690         if (on) {
2691                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2692         } else {
2693                 if (ixgbe_check_reset_blocked(hw))
2694                         return 0;
2695                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2696         }
2697
2698         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2699                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2700                                        reg);
2701         return status;
2702 }