drivers/net/ixgbe/base/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  * @lock: true if to take and release semaphore
 109  *
 110  * Returns an error code on error.
 111  */
 112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 113                                         u16 *val, bool lock)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         if (hw->mac.type >= ixgbe_mac_X550)
 125                 max_retry = 3;
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, false))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: true if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  *  ixgbe_identify_phy_generic - Get physical layer module
 287  *  @hw: pointer to hardware structure
 288  *
 289  *  Determines the physical layer module found on the current adapter.
 290  **/
 291 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 292 {
 293         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 294         u32 phy_addr;
 295         u16 ext_ability = 0;
 296
 297         DEBUGFUNC("ixgbe_identify_phy_generic");
 298
 299         if (!hw->phy.phy_semaphore_mask) {
 300                 if (hw->bus.lan_id)
 301                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 302                 else
 303                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 304         }
 305
 306         if (hw->phy.type == ixgbe_phy_unknown) {
 307                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 308                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 309                                 hw->phy.addr = phy_addr;
 310                                 ixgbe_get_phy_id(hw);
 311                                 hw->phy.type =
 312                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 313
 314                                 if (hw->phy.type == ixgbe_phy_unknown) {
 315                                         hw->phy.ops.read_reg(hw,
 316                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 317                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 318                                                   &ext_ability);
 319                                         if (ext_ability &
 320                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 321                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 322                                                 hw->phy.type =
 323                                                          ixgbe_phy_cu_unknown;
 324                                         else
 325                                                 hw->phy.type =
 326                                                          ixgbe_phy_generic;
 327                                 }
 328
 329                                 status = IXGBE_SUCCESS;
 330                                 break;
 331                         }
 332                 }
 333
 334                 /* Certain media types do not have a phy so an address will not
 335                  * be found and the code will take this path.  Caller has to
 336                  * decide if it is an error or not.
 337                  */
 338                 if (status != IXGBE_SUCCESS) {
 339                         hw->phy.addr = 0;
 340                 }
 341         } else {
 342                 status = IXGBE_SUCCESS;
 343         }
 344
 345         return status;
 346 }
 347
 348 /**
 349  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 350  * @hw: pointer to the hardware structure
 351  *
 352  * This function checks the MMNGC.MNG_VETO bit to see if there are
 353  * any constraints on link from manageability.  For MAC's that don't
 354  * have this bit just return faluse since the link can not be blocked
 355  * via this method.
 356  **/
 357 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 358 {
 359         u32 mmngc;
 360
 361         DEBUGFUNC("ixgbe_check_reset_blocked");
 362
 363         /* If we don't have this bit, it can't be blocking */
 364         if (hw->mac.type == ixgbe_mac_82598EB)
 365                 return false;
 366
 367         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 368         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 369                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 370                               "MNG_VETO bit detected.\n");
 371                 return true;
 372         }
 373
 374         return false;
 375 }
 376
 377 /**
 378  *  ixgbe_validate_phy_addr - Determines phy address is valid
 379  *  @hw: pointer to hardware structure
 380  *
 381  **/
 382 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 383 {
 384         u16 phy_id = 0;
 385         bool valid = false;
 386
 387         DEBUGFUNC("ixgbe_validate_phy_addr");
 388
 389         hw->phy.addr = phy_addr;
 390         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 391                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 392
 393         if (phy_id != 0xFFFF && phy_id != 0x0)
 394                 valid = true;
 395
 396         return valid;
 397 }
 398
 399 /**
 400  *  ixgbe_get_phy_id - Get the phy type
 401  *  @hw: pointer to hardware structure
 402  *
 403  **/
 404 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 405 {
 406         u32 status;
 407         u16 phy_id_high = 0;
 408         u16 phy_id_low = 0;
 409
 410         DEBUGFUNC("ixgbe_get_phy_id");
 411
 412         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 413                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 414                                       &phy_id_high);
 415
 416         if (status == IXGBE_SUCCESS) {
 417                 hw->phy.id = (u32)(phy_id_high << 16);
 418                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 419                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 420                                               &phy_id_low);
 421                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 422                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 423         }
 424         return status;
 425 }
 426
 427 /**
 428  *  ixgbe_get_phy_type_from_id - Get the phy type
 429  *  @phy_id: PHY ID information
 430  *
 431  **/
 432 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 433 {
 434         enum ixgbe_phy_type phy_type;
 435
 436         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 437
 438         switch (phy_id) {
 439         case TN1010_PHY_ID:
 440                 phy_type = ixgbe_phy_tn;
 441                 break;
 442         case X550_PHY_ID1:
 443         case X550_PHY_ID2:
 444         case X550_PHY_ID3:
 445         case X540_PHY_ID:
 446                 phy_type = ixgbe_phy_aq;
 447                 break;
 448         case QT2022_PHY_ID:
 449                 phy_type = ixgbe_phy_qt;
 450                 break;
 451         case ATH_PHY_ID:
 452                 phy_type = ixgbe_phy_nl;
 453                 break;
 454         case X557_PHY_ID:
 455                 phy_type = ixgbe_phy_x550em_ext_t;
 456                 break;
 457         case IXGBE_M88E1500_E_PHY_ID:
 458                 phy_type = ixgbe_phy_m88;
 459                 break;
 460         default:
 461                 phy_type = ixgbe_phy_unknown;
 462                 break;
 463         }
 464         return phy_type;
 465 }
 466
 467 /**
 468  *  ixgbe_reset_phy_generic - Performs a PHY reset
 469  *  @hw: pointer to hardware structure
 470  **/
 471 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 472 {
 473         u32 i;
 474         u16 ctrl = 0;
 475         s32 status = IXGBE_SUCCESS;
 476
 477         DEBUGFUNC("ixgbe_reset_phy_generic");
 478
 479         if (hw->phy.type == ixgbe_phy_unknown)
 480                 status = ixgbe_identify_phy_generic(hw);
 481
 482         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 483                 goto out;
 484
 485         /* Don't reset PHY if it's shut down due to overtemp. */
 486         if (!hw->phy.reset_if_overtemp &&
 487             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 488                 goto out;
 489
 490         /* Blocked by MNG FW so bail */
 491         if (ixgbe_check_reset_blocked(hw))
 492                 goto out;
 493
 494         /*
 495          * Perform soft PHY reset to the PHY_XS.
 496          * This will cause a soft reset to the PHY
 497          */
 498         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 499                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 500                               IXGBE_MDIO_PHY_XS_RESET);
 501
 502         /*
 503          * Poll for reset bit to self-clear indicating reset is complete.
 504          * Some PHYs could take up to 3 seconds to complete and need about
 505          * 1.7 usec delay after the reset is complete.
 506          */
 507         for (i = 0; i < 30; i++) {
 508                 msec_delay(100);
 509                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 510                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 511                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 512                         usec_delay(2);
 513                         break;
 514                 }
 515         }
 516
 517         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 518                 status = IXGBE_ERR_RESET_FAILED;
 519                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 520                              "PHY reset polling failed to complete.\n");
 521         }
 522
 523 out:
 524         return status;
 525 }
 526
 527 /**
 528  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 529  *  the SWFW lock
 530  *  @hw: pointer to hardware structure
 531  *  @reg_addr: 32 bit address of PHY register to read
 532  *  @phy_data: Pointer to read data from PHY register
 533  **/
 534 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 535                        u16 *phy_data)
 536 {
 537         u32 i, data, command;
 538
 539         /* Setup and write the address cycle command */
 540         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 541                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 542                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 543                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 544
 545         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 546
 547         /*
 548          * Check every 10 usec to see if the address cycle completed.
 549          * The MDI Command bit will clear when the operation is
 550          * complete
 551          */
 552         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 553                 usec_delay(10);
 554
 555                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 556                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 557                                 break;
 558         }
 559
 560
 561         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 562                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 563                 return IXGBE_ERR_PHY;
 564         }
 565
 566         /*
 567          * Address cycle complete, setup and write the read
 568          * command
 569          */
 570         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 571                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 572                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 573                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 574
 575         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 576
 577         /*
 578          * Check every 10 usec to see if the address cycle
 579          * completed. The MDI Command bit will clear when the
 580          * operation is complete
 581          */
 582         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 583                 usec_delay(10);
 584
 585                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 586                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 587                         break;
 588         }
 589
 590         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 591                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 592                 return IXGBE_ERR_PHY;
 593         }
 594
 595         /*
 596          * Read operation is complete.  Get the data
 597          * from MSRWD
 598          */
 599         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 600         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 601         *phy_data = (u16)(data);
 602
 603         return IXGBE_SUCCESS;
 604 }
 605
 606 /**
 607  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 608  *  using the SWFW lock - this function is needed in most cases
 609  *  @hw: pointer to hardware structure
 610  *  @reg_addr: 32 bit address of PHY register to read
 611  *  @phy_data: Pointer to read data from PHY register
 612  **/
 613 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 614                                u32 device_type, u16 *phy_data)
 615 {
 616         s32 status;
 617         u32 gssr = hw->phy.phy_semaphore_mask;
 618
 619         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 620
 621         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 622                 return IXGBE_ERR_SWFW_SYNC;
 623
 624         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 625
 626         hw->mac.ops.release_swfw_sync(hw, gssr);
 627
 628         return status;
 629 }
 630
 631 /**
 632  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 633  *  without SWFW lock
 634  *  @hw: pointer to hardware structure
 635  *  @reg_addr: 32 bit PHY register to write
 636  *  @device_type: 5 bit device type
 637  *  @phy_data: Data to write to the PHY register
 638  **/
 639 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 640                                 u32 device_type, u16 phy_data)
 641 {
 642         u32 i, command;
 643
 644         /* Put the data in the MDI single read and write data register*/
 645         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 646
 647         /* Setup and write the address cycle command */
 648         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 649                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 650                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 651                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 652
 653         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 654
 655         /*
 656          * Check every 10 usec to see if the address cycle completed.
 657          * The MDI Command bit will clear when the operation is
 658          * complete
 659          */
 660         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 661                 usec_delay(10);
 662
 663                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 664                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 665                         break;
 666         }
 667
 668         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 669                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 670                 return IXGBE_ERR_PHY;
 671         }
 672
 673         /*
 674          * Address cycle complete, setup and write the write
 675          * command
 676          */
 677         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 678                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 679                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 680                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 681
 682         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 683
 684         /*
 685          * Check every 10 usec to see if the address cycle
 686          * completed. The MDI Command bit will clear when the
 687          * operation is complete
 688          */
 689         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 690                 usec_delay(10);
 691
 692                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 693                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 694                         break;
 695         }
 696
 697         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 698                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 699                 return IXGBE_ERR_PHY;
 700         }
 701
 702         return IXGBE_SUCCESS;
 703 }
 704
 705 /**
 706  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 707  *  using SWFW lock- this function is needed in most cases
 708  *  @hw: pointer to hardware structure
 709  *  @reg_addr: 32 bit PHY register to write
 710  *  @device_type: 5 bit device type
 711  *  @phy_data: Data to write to the PHY register
 712  **/
 713 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 714                                 u32 device_type, u16 phy_data)
 715 {
 716         s32 status;
 717         u32 gssr = hw->phy.phy_semaphore_mask;
 718
 719         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 720
 721         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 722                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 723                                                  phy_data);
 724                 hw->mac.ops.release_swfw_sync(hw, gssr);
 725         } else {
 726                 status = IXGBE_ERR_SWFW_SYNC;
 727         }
 728
 729         return status;
 730 }
 731
 732 /**
 733  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 734  *  @hw: pointer to hardware structure
 735  *
 736  *  Restart auto-negotiation and PHY and waits for completion.
 737  **/
 738 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 739 {
 740         s32 status = IXGBE_SUCCESS;
 741         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 742         bool autoneg = false;
 743         ixgbe_link_speed speed;
 744
 745         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 746
 747         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 748
 749         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 750                 /* Set or unset auto-negotiation 10G advertisement */
 751                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 752                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 753                                      &autoneg_reg);
 754
 755                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 756                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 757                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 758
 759                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 760                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 761                                       autoneg_reg);
 762         }
 763
 764         if (hw->mac.type == ixgbe_mac_X550) {
 765                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 766                         /* Set or unset auto-negotiation 5G advertisement */
 767                         hw->phy.ops.read_reg(hw,
 768                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 769                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 770                                 &autoneg_reg);
 771
 772                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 773                         if (hw->phy.autoneg_advertised &
 774                              IXGBE_LINK_SPEED_5GB_FULL)
 775                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 776
 777                         hw->phy.ops.write_reg(hw,
 778                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 779                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 780                                 autoneg_reg);
 781                 }
 782
 783                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 784                         /* Set or unset auto-negotiation 2.5G advertisement */
 785                         hw->phy.ops.read_reg(hw,
 786                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 787                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 788                                 &autoneg_reg);
 789
 790                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 791                         if (hw->phy.autoneg_advertised &
 792                             IXGBE_LINK_SPEED_2_5GB_FULL)
 793                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 794
 795                         hw->phy.ops.write_reg(hw,
 796                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 797                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 798                                 autoneg_reg);
 799                 }
 800         }
 801
 802         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 803                 /* Set or unset auto-negotiation 1G advertisement */
 804                 hw->phy.ops.read_reg(hw,
 805                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 806                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 807                                      &autoneg_reg);
 808
 809                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 810                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 811                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 812
 813                 hw->phy.ops.write_reg(hw,
 814                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 815                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 816                                       autoneg_reg);
 817         }
 818
 819         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 820                 /* Set or unset auto-negotiation 100M advertisement */
 821                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 822                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 823                                      &autoneg_reg);
 824
 825                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 826                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 827                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 828                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 829
 830                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 831                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 832                                       autoneg_reg);
 833         }
 834
 835         /* Blocked by MNG FW so don't reset PHY */
 836         if (ixgbe_check_reset_blocked(hw))
 837                 return status;
 838
 839         /* Restart PHY auto-negotiation. */
 840         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 841                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 842
 843         autoneg_reg |= IXGBE_MII_RESTART;
 844
 845         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 846                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 847
 848         return status;
 849 }
 850
 851 /**
 852  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 853  *  @hw: pointer to hardware structure
 854  *  @speed: new link speed
 855  **/
 856 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 857                                        ixgbe_link_speed speed,
 858                                        bool autoneg_wait_to_complete)
 859 {
 860         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 861
 862         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 863
 864         /*
 865          * Clear autoneg_advertised and set new values based on input link
 866          * speed.
 867          */
 868         hw->phy.autoneg_advertised = 0;
 869
 870         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 871                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 872
 873         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 874                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 875
 876         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 877                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 878
 879         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 880                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 881
 882         if (speed & IXGBE_LINK_SPEED_100_FULL)
 883                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 884
 885         /* Setup link based on the new speed settings */
 886         ixgbe_setup_phy_link(hw);
 887
 888         return IXGBE_SUCCESS;
 889 }
 890
 891 /**
 892  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 893  * @hw: pointer to hardware structure
 894  *
 895  * Determines the supported link capabilities by reading the PHY auto
 896  * negotiation register.
 897  **/
 898 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 899 {
 900         s32 status;
 901         u16 speed_ability;
 902
 903         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 904                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 905                                       &speed_ability);
 906         if (status)
 907                 return status;
 908
 909         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 910                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 911         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 912                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 913         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 914                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 915
 916         switch (hw->mac.type) {
 917         case ixgbe_mac_X550:
 918                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 919                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 920                 break;
 921         case ixgbe_mac_X550EM_x:
 922                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 923                 break;
 924         default:
 925                 break;
 926         }
 927
 928         return status;
 929 }
 930
 931 /**
 932  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 933  *  @hw: pointer to hardware structure
 934  *  @speed: pointer to link speed
 935  *  @autoneg: boolean auto-negotiation value
 936  **/
 937 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 938                                                ixgbe_link_speed *speed,
 939                                                bool *autoneg)
 940 {
 941         s32 status = IXGBE_SUCCESS;
 942
 943         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 944
 945         *autoneg = true;
 946         if (!hw->phy.speeds_supported)
 947                 status = ixgbe_get_copper_speeds_supported(hw);
 948
 949         *speed = hw->phy.speeds_supported;
 950         return status;
 951 }
 952
 953 /**
 954  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 955  *  @hw: pointer to hardware structure
 956  *
 957  *  Reads the VS1 register to determine if link is up and the current speed for
 958  *  the PHY.
 959  **/
 960 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 961                              bool *link_up)
 962 {
 963         s32 status = IXGBE_SUCCESS;
 964         u32 time_out;
 965         u32 max_time_out = 10;
 966         u16 phy_link = 0;
 967         u16 phy_speed = 0;
 968         u16 phy_data = 0;
 969
 970         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 971
 972         /* Initialize speed and link to default case */
 973         *link_up = false;
 974         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 975
 976         /*
 977          * Check current speed and link status of the PHY register.
 978          * This is a vendor specific register and may have to
 979          * be changed for other copper PHYs.
 980          */
 981         for (time_out = 0; time_out < max_time_out; time_out++) {
 982                 usec_delay(10);
 983                 status = hw->phy.ops.read_reg(hw,
 984                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 985                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 986                                         &phy_data);
 987                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 988                 phy_speed = phy_data &
 989                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 990                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 991                         *link_up = true;
 992                         if (phy_speed ==
 993                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 994                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 995                         break;
 996                 }
 997         }
 998
 999         return status;
1000 }
1001
1002 /**
1003  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1004  *      @hw: pointer to hardware structure
1005  *
1006  *      Restart auto-negotiation and PHY and waits for completion.
1007  **/
1008 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1009 {
1010         s32 status = IXGBE_SUCCESS;
1011         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1012         bool autoneg = false;
1013         ixgbe_link_speed speed;
1014
1015         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1016
1017         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1018
1019         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1020                 /* Set or unset auto-negotiation 10G advertisement */
1021                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1022                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1023                                      &autoneg_reg);
1024
1025                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1026                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1027                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1028
1029                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1030                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1031                                       autoneg_reg);
1032         }
1033
1034         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1035                 /* Set or unset auto-negotiation 1G advertisement */
1036                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1037                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1038                                      &autoneg_reg);
1039
1040                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1041                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1042                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1043
1044                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1045                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1046                                       autoneg_reg);
1047         }
1048
1049         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1050                 /* Set or unset auto-negotiation 100M advertisement */
1051                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1052                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1053                                      &autoneg_reg);
1054
1055                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1056                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1057                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1058
1059                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1060                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1061                                       autoneg_reg);
1062         }
1063
1064         /* Blocked by MNG FW so don't reset PHY */
1065         if (ixgbe_check_reset_blocked(hw))
1066                 return status;
1067
1068         /* Restart PHY auto-negotiation. */
1069         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1070                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1071
1072         autoneg_reg |= IXGBE_MII_RESTART;
1073
1074         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1075                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1076
1077         return status;
1078 }
1079
1080 /**
1081  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1082  *  @hw: pointer to hardware structure
1083  *  @firmware_version: pointer to the PHY Firmware Version
1084  **/
1085 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1086                                        u16 *firmware_version)
1087 {
1088         s32 status;
1089
1090         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1091
1092         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1093                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1094                                       firmware_version);
1095
1096         return status;
1097 }
1098
1099 /**
1100  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1101  *  @hw: pointer to hardware structure
1102  *  @firmware_version: pointer to the PHY Firmware Version
1103  **/
1104 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1105                                            u16 *firmware_version)
1106 {
1107         s32 status;
1108
1109         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1110
1111         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1112                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1113                                       firmware_version);
1114
1115         return status;
1116 }
1117
1118 /**
1119  *  ixgbe_reset_phy_nl - Performs a PHY reset
1120  *  @hw: pointer to hardware structure
1121  **/
1122 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1123 {
1124         u16 phy_offset, control, eword, edata, block_crc;
1125         bool end_data = false;
1126         u16 list_offset, data_offset;
1127         u16 phy_data = 0;
1128         s32 ret_val = IXGBE_SUCCESS;
1129         u32 i;
1130
1131         DEBUGFUNC("ixgbe_reset_phy_nl");
1132
1133         /* Blocked by MNG FW so bail */
1134         if (ixgbe_check_reset_blocked(hw))
1135                 goto out;
1136
1137         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1138                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1139
1140         /* reset the PHY and poll for completion */
1141         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1142                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1143                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1144
1145         for (i = 0; i < 100; i++) {
1146                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1147                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1148                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1149                         break;
1150                 msec_delay(10);
1151         }
1152
1153         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1154                 DEBUGOUT("PHY reset did not complete.\n");
1155                 ret_val = IXGBE_ERR_PHY;
1156                 goto out;
1157         }
1158
1159         /* Get init offsets */
1160         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1161                                                       &data_offset);
1162         if (ret_val != IXGBE_SUCCESS)
1163                 goto out;
1164
1165         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1166         data_offset++;
1167         while (!end_data) {
1168                 /*
1169                  * Read control word from PHY init contents offset
1170                  */
1171                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1172                 if (ret_val)
1173                         goto err_eeprom;
1174                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1175                            IXGBE_CONTROL_SHIFT_NL;
1176                 edata = eword & IXGBE_DATA_MASK_NL;
1177                 switch (control) {
1178                 case IXGBE_DELAY_NL:
1179                         data_offset++;
1180                         DEBUGOUT1("DELAY: %d MS\n", edata);
1181                         msec_delay(edata);
1182                         break;
1183                 case IXGBE_DATA_NL:
1184                         DEBUGOUT("DATA:\n");
1185                         data_offset++;
1186                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1187                                                       &phy_offset);
1188                         if (ret_val)
1189                                 goto err_eeprom;
1190                         data_offset++;
1191                         for (i = 0; i < edata; i++) {
1192                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1193                                                               &eword);
1194                                 if (ret_val)
1195                                         goto err_eeprom;
1196                                 hw->phy.ops.write_reg(hw, phy_offset,
1197                                                       IXGBE_TWINAX_DEV, eword);
1198                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1199                                           phy_offset);
1200                                 data_offset++;
1201                                 phy_offset++;
1202                         }
1203                         break;
1204                 case IXGBE_CONTROL_NL:
1205                         data_offset++;
1206                         DEBUGOUT("CONTROL:\n");
1207                         if (edata == IXGBE_CONTROL_EOL_NL) {
1208                                 DEBUGOUT("EOL\n");
1209                                 end_data = true;
1210                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1211                                 DEBUGOUT("SOL\n");
1212                         } else {
1213                                 DEBUGOUT("Bad control value\n");
1214                                 ret_val = IXGBE_ERR_PHY;
1215                                 goto out;
1216                         }
1217                         break;
1218                 default:
1219                         DEBUGOUT("Bad control type\n");
1220                         ret_val = IXGBE_ERR_PHY;
1221                         goto out;
1222                 }
1223         }
1224
1225 out:
1226         return ret_val;
1227
1228 err_eeprom:
1229         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1230                       "eeprom read at offset %d failed", data_offset);
1231         return IXGBE_ERR_PHY;
1232 }
1233
1234 /**
1235  *  ixgbe_identify_module_generic - Identifies module type
1236  *  @hw: pointer to hardware structure
1237  *
1238  *  Determines HW type and calls appropriate function.
1239  **/
1240 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1241 {
1242         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1243
1244         DEBUGFUNC("ixgbe_identify_module_generic");
1245
1246         switch (hw->mac.ops.get_media_type(hw)) {
1247         case ixgbe_media_type_fiber:
1248                 status = ixgbe_identify_sfp_module_generic(hw);
1249                 break;
1250
1251         case ixgbe_media_type_fiber_qsfp:
1252                 status = ixgbe_identify_qsfp_module_generic(hw);
1253                 break;
1254
1255         default:
1256                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1257                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1258                 break;
1259         }
1260
1261         return status;
1262 }
1263
1264 /**
1265  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1266  *  @hw: pointer to hardware structure
1267  *
1268  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1269  **/
1270 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1271 {
1272         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1273         u32 vendor_oui = 0;
1274         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1275         u8 identifier = 0;
1276         u8 comp_codes_1g = 0;
1277         u8 comp_codes_10g = 0;
1278         u8 oui_bytes[3] = {0, 0, 0};
1279         u8 cable_tech = 0;
1280         u8 cable_spec = 0;
1281         u16 enforce_sfp = 0;
1282
1283         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1284
1285         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1286                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1287                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288                 goto out;
1289         }
1290
1291         /* LAN ID is needed for I2C access */
1292         hw->mac.ops.set_lan_id(hw);
1293
1294         status = hw->phy.ops.read_i2c_eeprom(hw,
1295                                              IXGBE_SFF_IDENTIFIER,
1296                                              &identifier);
1297
1298         if (status != IXGBE_SUCCESS)
1299                 goto err_read_i2c_eeprom;
1300
1301         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1302                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1303                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1304         } else {
1305                 status = hw->phy.ops.read_i2c_eeprom(hw,
1306                                                      IXGBE_SFF_1GBE_COMP_CODES,
1307                                                      &comp_codes_1g);
1308
1309                 if (status != IXGBE_SUCCESS)
1310                         goto err_read_i2c_eeprom;
1311
1312                 status = hw->phy.ops.read_i2c_eeprom(hw,
1313                                                      IXGBE_SFF_10GBE_COMP_CODES,
1314                                                      &comp_codes_10g);
1315
1316                 if (status != IXGBE_SUCCESS)
1317                         goto err_read_i2c_eeprom;
1318                 status = hw->phy.ops.read_i2c_eeprom(hw,
1319                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1320                                                      &cable_tech);
1321
1322                 if (status != IXGBE_SUCCESS)
1323                         goto err_read_i2c_eeprom;
1324
1325                  /* ID Module
1326                   * =========
1327                   * 0   SFP_DA_CU
1328                   * 1   SFP_SR
1329                   * 2   SFP_LR
1330                   * 3   SFP_DA_CORE0 - 82599-specific
1331                   * 4   SFP_DA_CORE1 - 82599-specific
1332                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1333                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1334                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1335                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1336                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1337                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1338                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1339                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1340                   */
1341                 if (hw->mac.type == ixgbe_mac_82598EB) {
1342                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1343                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1344                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1345                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1346                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1347                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1348                         else
1349                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1350                 } else {
1351                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1352                                 if (hw->bus.lan_id == 0)
1353                                         hw->phy.sfp_type =
1354                                                      ixgbe_sfp_type_da_cu_core0;
1355                                 else
1356                                         hw->phy.sfp_type =
1357                                                      ixgbe_sfp_type_da_cu_core1;
1358                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1359                                 hw->phy.ops.read_i2c_eeprom(
1360                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1361                                                 &cable_spec);
1362                                 if (cable_spec &
1363                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1364                                         if (hw->bus.lan_id == 0)
1365                                                 hw->phy.sfp_type =
1366                                                 ixgbe_sfp_type_da_act_lmt_core0;
1367                                         else
1368                                                 hw->phy.sfp_type =
1369                                                 ixgbe_sfp_type_da_act_lmt_core1;
1370                                 } else {
1371                                         hw->phy.sfp_type =
1372                                                         ixgbe_sfp_type_unknown;
1373                                 }
1374                         } else if (comp_codes_10g &
1375                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1376                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1377                                 if (hw->bus.lan_id == 0)
1378                                         hw->phy.sfp_type =
1379                                                       ixgbe_sfp_type_srlr_core0;
1380                                 else
1381                                         hw->phy.sfp_type =
1382                                                       ixgbe_sfp_type_srlr_core1;
1383                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1384                                 if (hw->bus.lan_id == 0)
1385                                         hw->phy.sfp_type =
1386                                                 ixgbe_sfp_type_1g_cu_core0;
1387                                 else
1388                                         hw->phy.sfp_type =
1389                                                 ixgbe_sfp_type_1g_cu_core1;
1390                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1391                                 if (hw->bus.lan_id == 0)
1392                                         hw->phy.sfp_type =
1393                                                 ixgbe_sfp_type_1g_sx_core0;
1394                                 else
1395                                         hw->phy.sfp_type =
1396                                                 ixgbe_sfp_type_1g_sx_core1;
1397                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1398                                 if (hw->bus.lan_id == 0)
1399                                         hw->phy.sfp_type =
1400                                                 ixgbe_sfp_type_1g_lx_core0;
1401                                 else
1402                                         hw->phy.sfp_type =
1403                                                 ixgbe_sfp_type_1g_lx_core1;
1404                         } else {
1405                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1406                         }
1407                 }
1408
1409                 if (hw->phy.sfp_type != stored_sfp_type)
1410                         hw->phy.sfp_setup_needed = true;
1411
1412                 /* Determine if the SFP+ PHY is dual speed or not. */
1413                 hw->phy.multispeed_fiber = false;
1414                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1415                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1416                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1417                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1418                         hw->phy.multispeed_fiber = true;
1419
1420                 /* Determine PHY vendor */
1421                 if (hw->phy.type != ixgbe_phy_nl) {
1422                         hw->phy.id = identifier;
1423                         status = hw->phy.ops.read_i2c_eeprom(hw,
1424                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1425                                                     &oui_bytes[0]);
1426
1427                         if (status != IXGBE_SUCCESS)
1428                                 goto err_read_i2c_eeprom;
1429
1430                         status = hw->phy.ops.read_i2c_eeprom(hw,
1431                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1432                                                     &oui_bytes[1]);
1433
1434                         if (status != IXGBE_SUCCESS)
1435                                 goto err_read_i2c_eeprom;
1436
1437                         status = hw->phy.ops.read_i2c_eeprom(hw,
1438                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1439                                                     &oui_bytes[2]);
1440
1441                         if (status != IXGBE_SUCCESS)
1442                                 goto err_read_i2c_eeprom;
1443
1444                         vendor_oui =
1445                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1446                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1447                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1448
1449                         switch (vendor_oui) {
1450                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1451                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1452                                         hw->phy.type =
1453                                                     ixgbe_phy_sfp_passive_tyco;
1454                                 break;
1455                         case IXGBE_SFF_VENDOR_OUI_FTL:
1456                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1457                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1458                                 else
1459                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1460                                 break;
1461                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1462                                 hw->phy.type = ixgbe_phy_sfp_avago;
1463                                 break;
1464                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1465                                 hw->phy.type = ixgbe_phy_sfp_intel;
1466                                 break;
1467                         default:
1468                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1469                                         hw->phy.type =
1470                                                  ixgbe_phy_sfp_passive_unknown;
1471                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1472                                         hw->phy.type =
1473                                                 ixgbe_phy_sfp_active_unknown;
1474                                 else
1475                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1476                                 break;
1477                         }
1478                 }
1479
1480                 /* Allow any DA cable vendor */
1481                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1482                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1483                         status = IXGBE_SUCCESS;
1484                         goto out;
1485                 }
1486
1487                 /* Verify supported 1G SFP modules */
1488                 if (comp_codes_10g == 0 &&
1489                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1490                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1491                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1492                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1493                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1494                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1495                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1496                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1497                         goto out;
1498                 }
1499
1500                 /* Anything else 82598-based is supported */
1501                 if (hw->mac.type == ixgbe_mac_82598EB) {
1502                         status = IXGBE_SUCCESS;
1503                         goto out;
1504                 }
1505
1506                 ixgbe_get_device_caps(hw, &enforce_sfp);
1507                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1508                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1509                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1512                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1514                         /* Make sure we're a supported PHY type */
1515                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1516                                 status = IXGBE_SUCCESS;
1517                         } else {
1518                                 if (hw->allow_unsupported_sfp == true) {
1519                                         EWARN(hw, "WARNING: Intel (R) Network "
1520                                               "Connections are quality tested "
1521                                               "using Intel (R) Ethernet Optics."
1522                                               " Using untested modules is not "
1523                                               "supported and may cause unstable"
1524                                               " operation or damage to the "
1525                                               "module or the adapter. Intel "
1526                                               "Corporation is not responsible "
1527                                               "for any harm caused by using "
1528                                               "untested modules.\n", status);
1529                                         status = IXGBE_SUCCESS;
1530                                 } else {
1531                                         DEBUGOUT("SFP+ module not supported\n");
1532                                         hw->phy.type =
1533                                                 ixgbe_phy_sfp_unsupported;
1534                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1535                                 }
1536                         }
1537                 } else {
1538                         status = IXGBE_SUCCESS;
1539                 }
1540         }
1541
1542 out:
1543         return status;
1544
1545 err_read_i2c_eeprom:
1546         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1547         if (hw->phy.type != ixgbe_phy_nl) {
1548                 hw->phy.id = 0;
1549                 hw->phy.type = ixgbe_phy_unknown;
1550         }
1551         return IXGBE_ERR_SFP_NOT_PRESENT;
1552 }
1553
1554 /**
1555  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1556  *  @hw: pointer to hardware structure
1557  *
1558  *  Determines physical layer capabilities of the current SFP.
1559  */
1560 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1561 {
1562         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1563         u8 comp_codes_10g = 0;
1564         u8 comp_codes_1g = 0;
1565
1566         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1567
1568         hw->phy.ops.identify_sfp(hw);
1569         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1570                 return physical_layer;
1571
1572         switch (hw->phy.type) {
1573         case ixgbe_phy_sfp_passive_tyco:
1574         case ixgbe_phy_sfp_passive_unknown:
1575         case ixgbe_phy_qsfp_passive_unknown:
1576                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1577                 break;
1578         case ixgbe_phy_sfp_ftl_active:
1579         case ixgbe_phy_sfp_active_unknown:
1580         case ixgbe_phy_qsfp_active_unknown:
1581                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1582                 break;
1583         case ixgbe_phy_sfp_avago:
1584         case ixgbe_phy_sfp_ftl:
1585         case ixgbe_phy_sfp_intel:
1586         case ixgbe_phy_sfp_unknown:
1587                 hw->phy.ops.read_i2c_eeprom(hw,
1588                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1589                 hw->phy.ops.read_i2c_eeprom(hw,
1590                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1591                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1592                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1593                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1594                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1595                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1596                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1597                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1598                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1599                 break;
1600         case ixgbe_phy_qsfp_intel:
1601         case ixgbe_phy_qsfp_unknown:
1602                 hw->phy.ops.read_i2c_eeprom(hw,
1603                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1604                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1605                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1606                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1607                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1608                 break;
1609         default:
1610                 break;
1611         }
1612
1613         return physical_layer;
1614 }
1615
1616 /**
1617  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1618  *  @hw: pointer to hardware structure
1619  *
1620  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1621  **/
1622 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1623 {
1624         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1625         u32 vendor_oui = 0;
1626         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1627         u8 identifier = 0;
1628         u8 comp_codes_1g = 0;
1629         u8 comp_codes_10g = 0;
1630         u8 oui_bytes[3] = {0, 0, 0};
1631         u16 enforce_sfp = 0;
1632         u8 connector = 0;
1633         u8 cable_length = 0;
1634         u8 device_tech = 0;
1635         bool active_cable = false;
1636
1637         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1638
1639         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1640                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1641                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1642                 goto out;
1643         }
1644
1645         /* LAN ID is needed for I2C access */
1646         hw->mac.ops.set_lan_id(hw);
1647
1648         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1649                                              &identifier);
1650
1651         if (status != IXGBE_SUCCESS)
1652                 goto err_read_i2c_eeprom;
1653
1654         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1655                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1656                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1657                 goto out;
1658         }
1659
1660         hw->phy.id = identifier;
1661
1662         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1663                                              &comp_codes_10g);
1664
1665         if (status != IXGBE_SUCCESS)
1666                 goto err_read_i2c_eeprom;
1667
1668         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1669                                              &comp_codes_1g);
1670
1671         if (status != IXGBE_SUCCESS)
1672                 goto err_read_i2c_eeprom;
1673
1674         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1675                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1676                 if (hw->bus.lan_id == 0)
1677                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1678                 else
1679                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1680         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1681                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1682                 if (hw->bus.lan_id == 0)
1683                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1684                 else
1685                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1686         } else {
1687                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1688                         active_cable = true;
1689
1690                 if (!active_cable) {
1691                         /* check for active DA cables that pre-date
1692                          * SFF-8436 v3.6 */
1693                         hw->phy.ops.read_i2c_eeprom(hw,
1694                                         IXGBE_SFF_QSFP_CONNECTOR,
1695                                         &connector);
1696
1697                         hw->phy.ops.read_i2c_eeprom(hw,
1698                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1699                                         &cable_length);
1700
1701                         hw->phy.ops.read_i2c_eeprom(hw,
1702                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1703                                         &device_tech);
1704
1705                         if ((connector ==
1706                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1707                             (cable_length > 0) &&
1708                             ((device_tech >> 4) ==
1709                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1710                                 active_cable = true;
1711                 }
1712
1713                 if (active_cable) {
1714                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1715                         if (hw->bus.lan_id == 0)
1716                                 hw->phy.sfp_type =
1717                                                 ixgbe_sfp_type_da_act_lmt_core0;
1718                         else
1719                                 hw->phy.sfp_type =
1720                                                 ixgbe_sfp_type_da_act_lmt_core1;
1721                 } else {
1722                         /* unsupported module type */
1723                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1724                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1725                         goto out;
1726                 }
1727         }
1728
1729         if (hw->phy.sfp_type != stored_sfp_type)
1730                 hw->phy.sfp_setup_needed = true;
1731
1732         /* Determine if the QSFP+ PHY is dual speed or not. */
1733         hw->phy.multispeed_fiber = false;
1734         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1735            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1736            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1737            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1738                 hw->phy.multispeed_fiber = true;
1739
1740         /* Determine PHY vendor for optical modules */
1741         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1742                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1743                 status = hw->phy.ops.read_i2c_eeprom(hw,
1744                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1745                                             &oui_bytes[0]);
1746
1747                 if (status != IXGBE_SUCCESS)
1748                         goto err_read_i2c_eeprom;
1749
1750                 status = hw->phy.ops.read_i2c_eeprom(hw,
1751                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1752                                             &oui_bytes[1]);
1753
1754                 if (status != IXGBE_SUCCESS)
1755                         goto err_read_i2c_eeprom;
1756
1757                 status = hw->phy.ops.read_i2c_eeprom(hw,
1758                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1759                                             &oui_bytes[2]);
1760
1761                 if (status != IXGBE_SUCCESS)
1762                         goto err_read_i2c_eeprom;
1763
1764                 vendor_oui =
1765                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1766                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1767                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1768
1769                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1770                         hw->phy.type = ixgbe_phy_qsfp_intel;
1771                 else
1772                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1773
1774                 ixgbe_get_device_caps(hw, &enforce_sfp);
1775                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1776                         /* Make sure we're a supported PHY type */
1777                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1778                                 status = IXGBE_SUCCESS;
1779                         } else {
1780                                 if (hw->allow_unsupported_sfp == true) {
1781                                         EWARN(hw, "WARNING: Intel (R) Network "
1782                                               "Connections are quality tested "
1783                                               "using Intel (R) Ethernet Optics."
1784                                               " Using untested modules is not "
1785                                               "supported and may cause unstable"
1786                                               " operation or damage to the "
1787                                               "module or the adapter. Intel "
1788                                               "Corporation is not responsible "
1789                                               "for any harm caused by using "
1790                                               "untested modules.\n", status);
1791                                         status = IXGBE_SUCCESS;
1792                                 } else {
1793                                         DEBUGOUT("QSFP module not supported\n");
1794                                         hw->phy.type =
1795                                                 ixgbe_phy_sfp_unsupported;
1796                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1797                                 }
1798                         }
1799                 } else {
1800                         status = IXGBE_SUCCESS;
1801                 }
1802         }
1803
1804 out:
1805         return status;
1806
1807 err_read_i2c_eeprom:
1808         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1809         hw->phy.id = 0;
1810         hw->phy.type = ixgbe_phy_unknown;
1811
1812         return IXGBE_ERR_SFP_NOT_PRESENT;
1813 }
1814
1815
1816 /**
1817  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1818  *  @hw: pointer to hardware structure
1819  *  @list_offset: offset to the SFP ID list
1820  *  @data_offset: offset to the SFP data block
1821  *
1822  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1823  *  so it returns the offsets to the phy init sequence block.
1824  **/
1825 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1826                                         u16 *list_offset,
1827                                         u16 *data_offset)
1828 {
1829         u16 sfp_id;
1830         u16 sfp_type = hw->phy.sfp_type;
1831
1832         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1833
1834         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1835                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1836
1837         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1838                 return IXGBE_ERR_SFP_NOT_PRESENT;
1839
1840         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1841             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1842                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1843
1844         /*
1845          * Limiting active cables and 1G Phys must be initialized as
1846          * SR modules
1847          */
1848         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1849             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1850             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1851             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1852                 sfp_type = ixgbe_sfp_type_srlr_core0;
1853         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1854                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1855                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1856                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1857                 sfp_type = ixgbe_sfp_type_srlr_core1;
1858
1859         /* Read offset to PHY init contents */
1860         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1861                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1862                               "eeprom read at offset %d failed",
1863                               IXGBE_PHY_INIT_OFFSET_NL);
1864                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1865         }
1866
1867         if ((!*list_offset) || (*list_offset == 0xFFFF))
1868                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1869
1870         /* Shift offset to first ID word */
1871         (*list_offset)++;
1872
1873         /*
1874          * Find the matching SFP ID in the EEPROM
1875          * and program the init sequence
1876          */
1877         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1878                 goto err_phy;
1879
1880         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1881                 if (sfp_id == sfp_type) {
1882                         (*list_offset)++;
1883                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1884                                 goto err_phy;
1885                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1886                                 DEBUGOUT("SFP+ module not supported\n");
1887                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1888                         } else {
1889                                 break;
1890                         }
1891                 } else {
1892                         (*list_offset) += 2;
1893                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1894                                 goto err_phy;
1895                 }
1896         }
1897
1898         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1899                 DEBUGOUT("No matching SFP+ module found\n");
1900                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1901         }
1902
1903         return IXGBE_SUCCESS;
1904
1905 err_phy:
1906         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1907                       "eeprom read at offset %d failed", *list_offset);
1908         return IXGBE_ERR_PHY;
1909 }
1910
1911 /**
1912  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1913  *  @hw: pointer to hardware structure
1914  *  @byte_offset: EEPROM byte offset to read
1915  *  @eeprom_data: value read
1916  *
1917  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1918  **/
1919 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1920                                   u8 *eeprom_data)
1921 {
1922         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1923
1924         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1925                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1926                                          eeprom_data);
1927 }
1928
1929 /**
1930  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1931  *  @hw: pointer to hardware structure
1932  *  @byte_offset: byte offset at address 0xA2
1933  *  @eeprom_data: value read
1934  *
1935  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1936  **/
1937 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1938                                           u8 *sff8472_data)
1939 {
1940         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1941                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1942                                          sff8472_data);
1943 }
1944
1945 /**
1946  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1947  *  @hw: pointer to hardware structure
1948  *  @byte_offset: EEPROM byte offset to write
1949  *  @eeprom_data: value to write
1950  *
1951  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1952  **/
1953 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1954                                    u8 eeprom_data)
1955 {
1956         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1957
1958         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1959                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1960                                           eeprom_data);
1961 }
1962
1963 /**
1964  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1965  * @hw: pointer to hardware structure
1966  * @offset: eeprom offset to be read
1967  * @addr: I2C address to be read
1968  */
1969 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1970 {
1971         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1972             offset == IXGBE_SFF_IDENTIFIER &&
1973             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1974                 return true;
1975         return false;
1976 }
1977
1978 /**
1979  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1980  *  @hw: pointer to hardware structure
1981  *  @byte_offset: byte offset to read
1982  *  @data: value read
1983  *  @lock: true if to take and release semaphore
1984  *
1985  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1986  *  a specified device address.
1987  **/
1988 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1989                                            u8 dev_addr, u8 *data, bool lock)
1990 {
1991         s32 status;
1992         u32 max_retry = 10;
1993         u32 retry = 0;
1994         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1995         bool nack = 1;
1996         *data = 0;
1997
1998         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1999
2000         if (hw->mac.type >= ixgbe_mac_X550)
2001                 max_retry = 3;
2002         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2003                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2004
2005         do {
2006                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2007                         return IXGBE_ERR_SWFW_SYNC;
2008
2009                 ixgbe_i2c_start(hw);
2010
2011                 /* Device Address and write indication */
2012                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2013                 if (status != IXGBE_SUCCESS)
2014                         goto fail;
2015
2016                 status = ixgbe_get_i2c_ack(hw);
2017                 if (status != IXGBE_SUCCESS)
2018                         goto fail;
2019
2020                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2021                 if (status != IXGBE_SUCCESS)
2022                         goto fail;
2023
2024                 status = ixgbe_get_i2c_ack(hw);
2025                 if (status != IXGBE_SUCCESS)
2026                         goto fail;
2027
2028                 ixgbe_i2c_start(hw);
2029
2030                 /* Device Address and read indication */
2031                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2032                 if (status != IXGBE_SUCCESS)
2033                         goto fail;
2034
2035                 status = ixgbe_get_i2c_ack(hw);
2036                 if (status != IXGBE_SUCCESS)
2037                         goto fail;
2038
2039                 status = ixgbe_clock_in_i2c_byte(hw, data);
2040                 if (status != IXGBE_SUCCESS)
2041                         goto fail;
2042
2043                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2044                 if (status != IXGBE_SUCCESS)
2045                         goto fail;
2046
2047                 ixgbe_i2c_stop(hw);
2048                 if (lock)
2049                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2050                 return IXGBE_SUCCESS;
2051
2052 fail:
2053                 ixgbe_i2c_bus_clear(hw);
2054                 if (lock) {
2055                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2056                         msec_delay(100);
2057                 }
2058                 retry++;
2059                 if (retry < max_retry)
2060                         DEBUGOUT("I2C byte read error - Retrying.\n");
2061                 else
2062                         DEBUGOUT("I2C byte read error.\n");
2063
2064         } while (retry < max_retry);
2065
2066         return status;
2067 }
2068
2069 /**
2070  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2071  *  @hw: pointer to hardware structure
2072  *  @byte_offset: byte offset to read
2073  *  @data: value read
2074  *
2075  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2076  *  a specified device address.
2077  **/
2078 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2079                                 u8 dev_addr, u8 *data)
2080 {
2081         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2082                                                data, true);
2083 }
2084
2085 /**
2086  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2087  *  @hw: pointer to hardware structure
2088  *  @byte_offset: byte offset to read
2089  *  @data: value read
2090  *
2091  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2092  *  a specified device address.
2093  **/
2094 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2095                                          u8 dev_addr, u8 *data)
2096 {
2097         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2098                                                data, false);
2099 }
2100
2101 /**
2102  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2103  *  @hw: pointer to hardware structure
2104  *  @byte_offset: byte offset to write
2105  *  @data: value to write
2106  *  @lock: true if to take and release semaphore
2107  *
2108  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2109  *  a specified device address.
2110  **/
2111 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2112                                             u8 dev_addr, u8 data, bool lock)
2113 {
2114         s32 status;
2115         u32 max_retry = 1;
2116         u32 retry = 0;
2117         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2118
2119         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2120
2121         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2122             IXGBE_SUCCESS)
2123                 return IXGBE_ERR_SWFW_SYNC;
2124
2125         do {
2126                 ixgbe_i2c_start(hw);
2127
2128                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2129                 if (status != IXGBE_SUCCESS)
2130                         goto fail;
2131
2132                 status = ixgbe_get_i2c_ack(hw);
2133                 if (status != IXGBE_SUCCESS)
2134                         goto fail;
2135
2136                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2137                 if (status != IXGBE_SUCCESS)
2138                         goto fail;
2139
2140                 status = ixgbe_get_i2c_ack(hw);
2141                 if (status != IXGBE_SUCCESS)
2142                         goto fail;
2143
2144                 status = ixgbe_clock_out_i2c_byte(hw, data);
2145                 if (status != IXGBE_SUCCESS)
2146                         goto fail;
2147
2148                 status = ixgbe_get_i2c_ack(hw);
2149                 if (status != IXGBE_SUCCESS)
2150                         goto fail;
2151
2152                 ixgbe_i2c_stop(hw);
2153                 if (lock)
2154                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2155                 return IXGBE_SUCCESS;
2156
2157 fail:
2158                 ixgbe_i2c_bus_clear(hw);
2159                 retry++;
2160                 if (retry < max_retry)
2161                         DEBUGOUT("I2C byte write error - Retrying.\n");
2162                 else
2163                         DEBUGOUT("I2C byte write error.\n");
2164         } while (retry < max_retry);
2165
2166         if (lock)
2167                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2168
2169         return status;
2170 }
2171
2172 /**
2173  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2174  *  @hw: pointer to hardware structure
2175  *  @byte_offset: byte offset to write
2176  *  @data: value to write
2177  *
2178  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2179  *  a specified device address.
2180  **/
2181 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2182                                  u8 dev_addr, u8 data)
2183 {
2184         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2185                                                 data, true);
2186 }
2187
2188 /**
2189  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2190  *  @hw: pointer to hardware structure
2191  *  @byte_offset: byte offset to write
2192  *  @data: value to write
2193  *
2194  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2195  *  a specified device address.
2196  **/
2197 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2198                                           u8 dev_addr, u8 data)
2199 {
2200         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2201                                                 data, false);
2202 }
2203
2204 /**
2205  *  ixgbe_i2c_start - Sets I2C start condition
2206  *  @hw: pointer to hardware structure
2207  *
2208  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2209  *  Set bit-bang mode on X550 hardware.
2210  **/
2211 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2212 {
2213         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2214
2215         DEBUGFUNC("ixgbe_i2c_start");
2216
2217         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2218
2219         /* Start condition must begin with data and clock high */
2220         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2221         ixgbe_raise_i2c_clk(hw, &i2cctl);
2222
2223         /* Setup time for start condition (4.7us) */
2224         usec_delay(IXGBE_I2C_T_SU_STA);
2225
2226         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2227
2228         /* Hold time for start condition (4us) */
2229         usec_delay(IXGBE_I2C_T_HD_STA);
2230
2231         ixgbe_lower_i2c_clk(hw, &i2cctl);
2232
2233         /* Minimum low period of clock is 4.7 us */
2234         usec_delay(IXGBE_I2C_T_LOW);
2235
2236 }
2237
2238 /**
2239  *  ixgbe_i2c_stop - Sets I2C stop condition
2240  *  @hw: pointer to hardware structure
2241  *
2242  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2243  *  Disables bit-bang mode and negates data output enable on X550
2244  *  hardware.
2245  **/
2246 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2247 {
2248         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2249         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2250         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2251         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2252
2253         DEBUGFUNC("ixgbe_i2c_stop");
2254
2255         /* Stop condition must begin with data low and clock high */
2256         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2257         ixgbe_raise_i2c_clk(hw, &i2cctl);
2258
2259         /* Setup time for stop condition (4us) */
2260         usec_delay(IXGBE_I2C_T_SU_STO);
2261
2262         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2263
2264         /* bus free time between stop and start (4.7us)*/
2265         usec_delay(IXGBE_I2C_T_BUF);
2266
2267         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2268                 i2cctl &= ~bb_en_bit;
2269                 i2cctl |= data_oe_bit | clk_oe_bit;
2270                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2271                 IXGBE_WRITE_FLUSH(hw);
2272         }
2273 }
2274
2275 /**
2276  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2277  *  @hw: pointer to hardware structure
2278  *  @data: data byte to clock in
2279  *
2280  *  Clocks in one byte data via I2C data/clock
2281  **/
2282 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2283 {
2284         s32 i;
2285         bool bit = 0;
2286
2287         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2288
2289         *data = 0;
2290         for (i = 7; i >= 0; i--) {
2291                 ixgbe_clock_in_i2c_bit(hw, &bit);
2292                 *data |= bit << i;
2293         }
2294
2295         return IXGBE_SUCCESS;
2296 }
2297
2298 /**
2299  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2300  *  @hw: pointer to hardware structure
2301  *  @data: data byte clocked out
2302  *
2303  *  Clocks out one byte data via I2C data/clock
2304  **/
2305 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2306 {
2307         s32 status = IXGBE_SUCCESS;
2308         s32 i;
2309         u32 i2cctl;
2310         bool bit;
2311
2312         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2313
2314         for (i = 7; i >= 0; i--) {
2315                 bit = (data >> i) & 0x1;
2316                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2317
2318                 if (status != IXGBE_SUCCESS)
2319                         break;
2320         }
2321
2322         /* Release SDA line (set high) */
2323         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2324         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2325         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2326         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2327         IXGBE_WRITE_FLUSH(hw);
2328
2329         return status;
2330 }
2331
2332 /**
2333  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2334  *  @hw: pointer to hardware structure
2335  *
2336  *  Clocks in/out one bit via I2C data/clock
2337  **/
2338 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2339 {
2340         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2341         s32 status = IXGBE_SUCCESS;
2342         u32 i = 0;
2343         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2344         u32 timeout = 10;
2345         bool ack = 1;
2346
2347         DEBUGFUNC("ixgbe_get_i2c_ack");
2348
2349         if (data_oe_bit) {
2350                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2351                 i2cctl |= data_oe_bit;
2352                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2353                 IXGBE_WRITE_FLUSH(hw);
2354         }
2355         ixgbe_raise_i2c_clk(hw, &i2cctl);
2356
2357         /* Minimum high period of clock is 4us */
2358         usec_delay(IXGBE_I2C_T_HIGH);
2359
2360         /* Poll for ACK.  Note that ACK in I2C spec is
2361          * transition from 1 to 0 */
2362         for (i = 0; i < timeout; i++) {
2363                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2364                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2365
2366                 usec_delay(1);
2367                 if (!ack)
2368                         break;
2369         }
2370
2371         if (ack) {
2372                 DEBUGOUT("I2C ack was not received.\n");
2373                 status = IXGBE_ERR_I2C;
2374         }
2375
2376         ixgbe_lower_i2c_clk(hw, &i2cctl);
2377
2378         /* Minimum low period of clock is 4.7 us */
2379         usec_delay(IXGBE_I2C_T_LOW);
2380
2381         return status;
2382 }
2383
2384 /**
2385  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2386  *  @hw: pointer to hardware structure
2387  *  @data: read data value
2388  *
2389  *  Clocks in one bit via I2C data/clock
2390  **/
2391 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2392 {
2393         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2394         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2395
2396         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2397
2398         if (data_oe_bit) {
2399                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2400                 i2cctl |= data_oe_bit;
2401                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2402                 IXGBE_WRITE_FLUSH(hw);
2403         }
2404         ixgbe_raise_i2c_clk(hw, &i2cctl);
2405
2406         /* Minimum high period of clock is 4us */
2407         usec_delay(IXGBE_I2C_T_HIGH);
2408
2409         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2410         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2411
2412         ixgbe_lower_i2c_clk(hw, &i2cctl);
2413
2414         /* Minimum low period of clock is 4.7 us */
2415         usec_delay(IXGBE_I2C_T_LOW);
2416
2417         return IXGBE_SUCCESS;
2418 }
2419
2420 /**
2421  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2422  *  @hw: pointer to hardware structure
2423  *  @data: data value to write
2424  *
2425  *  Clocks out one bit via I2C data/clock
2426  **/
2427 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2428 {
2429         s32 status;
2430         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2431
2432         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2433
2434         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2435         if (status == IXGBE_SUCCESS) {
2436                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2437
2438                 /* Minimum high period of clock is 4us */
2439                 usec_delay(IXGBE_I2C_T_HIGH);
2440
2441                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2442
2443                 /* Minimum low period of clock is 4.7 us.
2444                  * This also takes care of the data hold time.
2445                  */
2446                 usec_delay(IXGBE_I2C_T_LOW);
2447         } else {
2448                 status = IXGBE_ERR_I2C;
2449                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2450                              "I2C data was not set to %X\n", data);
2451         }
2452
2453         return status;
2454 }
2455
2456 /**
2457  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2458  *  @hw: pointer to hardware structure
2459  *  @i2cctl: Current value of I2CCTL register
2460  *
2461  *  Raises the I2C clock line '0'->'1'
2462  *  Negates the I2C clock output enable on X550 hardware.
2463  **/
2464 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2465 {
2466         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2467         u32 i = 0;
2468         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2469         u32 i2cctl_r = 0;
2470
2471         DEBUGFUNC("ixgbe_raise_i2c_clk");
2472
2473         if (clk_oe_bit) {
2474                 *i2cctl |= clk_oe_bit;
2475                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2476         }
2477
2478         for (i = 0; i < timeout; i++) {
2479                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2480
2481                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2482                 IXGBE_WRITE_FLUSH(hw);
2483                 /* SCL rise time (1000ns) */
2484                 usec_delay(IXGBE_I2C_T_RISE);
2485
2486                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2487                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2488                         break;
2489         }
2490 }
2491
2492 /**
2493  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2494  *  @hw: pointer to hardware structure
2495  *  @i2cctl: Current value of I2CCTL register
2496  *
2497  *  Lowers the I2C clock line '1'->'0'
2498  *  Asserts the I2C clock output enable on X550 hardware.
2499  **/
2500 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2501 {
2502         DEBUGFUNC("ixgbe_lower_i2c_clk");
2503
2504         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2505         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2506
2507         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2508         IXGBE_WRITE_FLUSH(hw);
2509
2510         /* SCL fall time (300ns) */
2511         usec_delay(IXGBE_I2C_T_FALL);
2512 }
2513
2514 /**
2515  *  ixgbe_set_i2c_data - Sets the I2C data bit
2516  *  @hw: pointer to hardware structure
2517  *  @i2cctl: Current value of I2CCTL register
2518  *  @data: I2C data value (0 or 1) to set
2519  *
2520  *  Sets the I2C data bit
2521  *  Asserts the I2C data output enable on X550 hardware.
2522  **/
2523 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2524 {
2525         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2526         s32 status = IXGBE_SUCCESS;
2527
2528         DEBUGFUNC("ixgbe_set_i2c_data");
2529
2530         if (data)
2531                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2532         else
2533                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2534         *i2cctl &= ~data_oe_bit;
2535
2536         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2537         IXGBE_WRITE_FLUSH(hw);
2538
2539         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2540         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2541
2542         if (!data)      /* Can't verify data in this case */
2543                 return IXGBE_SUCCESS;
2544         if (data_oe_bit) {
2545                 *i2cctl |= data_oe_bit;
2546                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2547                 IXGBE_WRITE_FLUSH(hw);
2548         }
2549
2550         /* Verify data was set correctly */
2551         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2552         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2553                 status = IXGBE_ERR_I2C;
2554                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2555                              "Error - I2C data was not set to %X.\n",
2556                              data);
2557         }
2558
2559         return status;
2560 }
2561
2562 /**
2563  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2564  *  @hw: pointer to hardware structure
2565  *  @i2cctl: Current value of I2CCTL register
2566  *
2567  *  Returns the I2C data bit value
2568  *  Negates the I2C data output enable on X550 hardware.
2569  **/
2570 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2571 {
2572         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2573         bool data;
2574
2575         DEBUGFUNC("ixgbe_get_i2c_data");
2576
2577         if (data_oe_bit) {
2578                 *i2cctl |= data_oe_bit;
2579                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2580                 IXGBE_WRITE_FLUSH(hw);
2581                 usec_delay(IXGBE_I2C_T_FALL);
2582         }
2583
2584         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2585                 data = 1;
2586         else
2587                 data = 0;
2588
2589         return data;
2590 }
2591
2592 /**
2593  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2594  *  @hw: pointer to hardware structure
2595  *
2596  *  Clears the I2C bus by sending nine clock pulses.
2597  *  Used when data line is stuck low.
2598  **/
2599 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2600 {
2601         u32 i2cctl;
2602         u32 i;
2603
2604         DEBUGFUNC("ixgbe_i2c_bus_clear");
2605
2606         ixgbe_i2c_start(hw);
2607         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2608
2609         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2610
2611         for (i = 0; i < 9; i++) {
2612                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2613
2614                 /* Min high period of clock is 4us */
2615                 usec_delay(IXGBE_I2C_T_HIGH);
2616
2617                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2618
2619                 /* Min low period of clock is 4.7us*/
2620                 usec_delay(IXGBE_I2C_T_LOW);
2621         }
2622
2623         ixgbe_i2c_start(hw);
2624
2625         /* Put the i2c bus back to default state */
2626         ixgbe_i2c_stop(hw);
2627 }
2628
2629 /**
2630  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2631  *  @hw: pointer to hardware structure
2632  *
2633  *  Checks if the LASI temp alarm status was triggered due to overtemp
2634  **/
2635 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2636 {
2637         s32 status = IXGBE_SUCCESS;
2638         u16 phy_data = 0;
2639
2640         DEBUGFUNC("ixgbe_tn_check_overtemp");
2641
2642         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2643                 goto out;
2644
2645         /* Check that the LASI temp alarm status was triggered */
2646         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2647                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2648
2649         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2650                 goto out;
2651
2652         status = IXGBE_ERR_OVERTEMP;
2653         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2654 out:
2655         return status;
2656 }
2657
2658 /**
2659  * ixgbe_set_copper_phy_power - Control power for copper phy
2660  * @hw: pointer to hardware structure
2661  * @on: true for on, false for off
2662  */
2663 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2664 {
2665         u32 status;
2666         u16 reg;
2667
2668         if (!on && ixgbe_mng_present(hw))
2669                 return 0;
2670
2671         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2672                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2673                                       &reg);
2674         if (status)
2675                 return status;
2676
2677         if (on) {
2678                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2679         } else {
2680                 if (ixgbe_check_reset_blocked(hw))
2681                         return 0;
2682                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2683         }
2684
2685         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2686                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2687                                        reg);
2688         return status;
2689 }