drivers/net/ixgbe/base/ixgbe_phy.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _IXGBE_PHY_H_
  35 #define _IXGBE_PHY_H_
  36
  37 #include "ixgbe_type.h"
  38 #define IXGBE_I2C_EEPROM_DEV_ADDR       0xA0
  39 #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
  40 #define IXGBE_I2C_EEPROM_BANK_LEN       0xFF
  41
  42 /* EEPROM byte offsets */
  43 #define IXGBE_SFF_IDENTIFIER            0x0
  44 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  45 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  46 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  47 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  48 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  49 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  50 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  51 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  52 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
  53 #define IXGBE_SFF_SFF_8472_COMP         0x5E
  54 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
  55 #define IXGBE_SFF_SFF_8472_ESCB         0x76
  56 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
  57 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
  58 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
  59 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
  60 #define IXGBE_SFF_QSFP_CONNECTOR        0x82
  61 #define IXGBE_SFF_QSFP_10GBE_COMP       0x83
  62 #define IXGBE_SFF_QSFP_1GBE_COMP        0x86
  63 #define IXGBE_SFF_QSFP_CABLE_LENGTH     0x92
  64 #define IXGBE_SFF_QSFP_DEVICE_TECH      0x93
  65
  66 /* Bitmasks */
  67 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  68 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  69 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
  70 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  71 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  72 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  73 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  74 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
  75 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
  76 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
  77 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  78 #define IXGBE_SFF_ADDRESSING_MODE       0x4
  79 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE  0x1
  80 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
  81 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE  0x23
  82 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL   0x0
  83 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  84 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  85 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  86 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  87 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
  88 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
  89
  90 #define IXGBE_CS4227                    0xBE    /* CS4227 address */
  91 #define IXGBE_CS4227_GLOBAL_ID_LSB      0
  92 #define IXGBE_CS4227_SCRATCH            2
  93 #define IXGBE_CS4227_GLOBAL_ID_VALUE    0x03E5
  94 #define IXGBE_CS4227_RESET_PENDING      0x1357
  95 #define IXGBE_CS4227_RESET_COMPLETE     0x5AA5
  96 #define IXGBE_CS4227_RETRIES            15
  97 #define IXGBE_CS4227_EFUSE_STATUS       0x0181
  98 #define IXGBE_CS4227_LINE_SPARE22_MSB   0x12AD  /* Reg to program speed */
  99 #define IXGBE_CS4227_LINE_SPARE24_LSB   0x12B0  /* Reg to program EDC */
 100 #define IXGBE_CS4227_HOST_SPARE22_MSB   0x1AAD  /* Reg to program speed */
 101 #define IXGBE_CS4227_HOST_SPARE24_LSB   0x1AB0  /* Reg to program EDC */
 102 #define IXGBE_CS4227_EEPROM_STATUS      0x5001
 103 #define IXGBE_CS4227_EEPROM_LOAD_OK     0x0001
 104 #define IXGBE_CS4227_SPEED_1G           0x8000
 105 #define IXGBE_CS4227_SPEED_10G          0
 106 #define IXGBE_CS4227_EDC_MODE_CX1       0x0002
 107 #define IXGBE_CS4227_EDC_MODE_SR        0x0004
 108 #define IXGBE_CS4227_EDC_MODE_DIAG      0x0008
 109 #define IXGBE_CS4227_RESET_HOLD         500     /* microseconds */
 110 #define IXGBE_CS4227_RESET_DELAY        450     /* milliseconds */
 111 #define IXGBE_CS4227_CHECK_DELAY        30      /* milliseconds */
 112 #define IXGBE_PE                        0xE0    /* Port expander address */
 113 #define IXGBE_PE_OUTPUT                 1       /* Output register offset */
 114 #define IXGBE_PE_CONFIG                 3       /* Config register offset */
 115 #define IXGBE_PE_BIT1                   (1 << 1)
 116
 117 /* Flow control defines */
 118 #define IXGBE_TAF_SYM_PAUSE             0x400
 119 #define IXGBE_TAF_ASM_PAUSE             0x800
 120
 121 /* Bit-shift macros */
 122 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
 123 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
 124 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
 125
 126 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
 127 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
 128 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
 129 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
 130 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
 131
 132 /* I2C SDA and SCL timing parameters for standard mode */
 133 #define IXGBE_I2C_T_HD_STA      4
 134 #define IXGBE_I2C_T_LOW         5
 135 #define IXGBE_I2C_T_HIGH        4
 136 #define IXGBE_I2C_T_SU_STA      5
 137 #define IXGBE_I2C_T_HD_DATA     5
 138 #define IXGBE_I2C_T_SU_DATA     1
 139 #define IXGBE_I2C_T_RISE        1
 140 #define IXGBE_I2C_T_FALL        1
 141 #define IXGBE_I2C_T_SU_STO      4
 142 #define IXGBE_I2C_T_BUF         5
 143
 144 #ifndef IXGBE_SFP_DETECT_RETRIES
 145 #define IXGBE_SFP_DETECT_RETRIES        10
 146
 147 #endif /* IXGBE_SFP_DETECT_RETRIES */
 148 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 149 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 150
 151 /* SFP+ SFF-8472 Compliance */
 152 #define IXGBE_SFF_SFF_8472_UNSUP        0x00
 153
 154 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 155 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
 156 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 157 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
 158 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 159 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 160 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 161                            u16 *phy_data);
 162 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 163                             u16 phy_data);
 164 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 165                                u32 device_type, u16 *phy_data);
 166 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 167                                 u32 device_type, u16 phy_data);
 168 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 169 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 170                                        ixgbe_link_speed speed,
 171                                        bool autoneg_wait_to_complete);
 172 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 173                                                ixgbe_link_speed *speed,
 174                                                bool *autoneg);
 175 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
 176
 177 /* PHY specific */
 178 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 179                              ixgbe_link_speed *speed,
 180                              bool *link_up);
 181 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 182 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 183                                        u16 *firmware_version);
 184 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 185                                            u16 *firmware_version);
 186
 187 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 188 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
 189 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 190 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 191 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
 192 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 193 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 194                                         u16 *list_offset,
 195                                         u16 *data_offset);
 196 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 197 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 198                                 u8 dev_addr, u8 *data);
 199 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
 200                                          u8 dev_addr, u8 *data);
 201 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 202                                  u8 dev_addr, u8 data);
 203 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
 204                                           u8 dev_addr, u8 data);
 205 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 206                                   u8 *eeprom_data);
 207 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 208                                    u8 eeprom_data);
 209 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 210 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
 211                                         u16 *val, bool lock);
 212 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
 213                                          u16 val, bool lock);
 214 #endif /* _IXGBE_PHY_H_ */