drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 333  * @hw: pointer to hardware structure
 334  *
 335  * Returns error code
 336  */
 337 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 338 {
 339         switch (hw->device_id) {
 340         case IXGBE_DEV_ID_X550EM_A_SFP:
 341                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_TOKEN_SM;
 342                 if (hw->bus.lan_id)
 343                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 344                 else
 345                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 346                 return ixgbe_identify_module_generic(hw);
 347         case IXGBE_DEV_ID_X550EM_X_SFP:
 348                 /* set up for CS4227 usage */
 349                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 350                 ixgbe_setup_mux_ctl(hw);
 351                 ixgbe_check_cs4227(hw);
 352                 /* Fallthrough */
 353
 354         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 355                 return ixgbe_identify_module_generic(hw);
 356                 break;
 357         case IXGBE_DEV_ID_X550EM_X_KX4:
 358                 hw->phy.type = ixgbe_phy_x550em_kx4;
 359                 break;
 360         case IXGBE_DEV_ID_X550EM_X_KR:
 361         case IXGBE_DEV_ID_X550EM_A_KR:
 362         case IXGBE_DEV_ID_X550EM_A_KR_L:
 363                 hw->phy.type = ixgbe_phy_x550em_kr;
 364                 break;
 365         case IXGBE_DEV_ID_X550EM_X_1G_T:
 366         case IXGBE_DEV_ID_X550EM_X_10G_T:
 367         case IXGBE_DEV_ID_X550EM_A_1G_T:
 368         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 369         case IXGBE_DEV_ID_X550EM_A_10G_T:
 370                 return ixgbe_identify_phy_generic(hw);
 371         default:
 372                 break;
 373         }
 374         return IXGBE_SUCCESS;
 375 }
 376
 377 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 378                                      u32 device_type, u16 *phy_data)
 379 {
 380         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 381         return IXGBE_NOT_IMPLEMENTED;
 382 }
 383
 384 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 385                                       u32 device_type, u16 phy_data)
 386 {
 387         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 388         return IXGBE_NOT_IMPLEMENTED;
 389 }
 390
 391 /**
 392  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 393  * @hw: pointer to the hardware structure
 394  * @addr: I2C bus address to read from
 395  * @reg: I2C device register to read from
 396  * @val: pointer to location to receive read value
 397  *
 398  * Returns an error code on error.
 399  **/
 400 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 401                                            u16 reg, u16 *val)
 402 {
 403         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 404 }
 405
 406 /**
 407  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 408  * @hw: pointer to the hardware structure
 409  * @addr: I2C bus address to read from
 410  * @reg: I2C device register to read from
 411  * @val: pointer to location to receive read value
 412  *
 413  * Returns an error code on error.
 414  **/
 415 static s32
 416 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 417                                          u16 reg, u16 *val)
 418 {
 419         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 420 }
 421
 422 /**
 423  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 424  * @hw: pointer to the hardware structure
 425  * @addr: I2C bus address to write to
 426  * @reg: I2C device register to write to
 427  * @val: value to write
 428  *
 429  * Returns an error code on error.
 430  **/
 431 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 432                                             u8 addr, u16 reg, u16 val)
 433 {
 434         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 435 }
 436
 437 /**
 438  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 439  * @hw: pointer to the hardware structure
 440  * @addr: I2C bus address to write to
 441  * @reg: I2C device register to write to
 442  * @val: value to write
 443  *
 444  * Returns an error code on error.
 445  **/
 446 static s32
 447 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 448                                           u8 addr, u16 reg, u16 val)
 449 {
 450         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 451 }
 452
 453 /**
 454 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 455 *  @hw: pointer to hardware structure
 456 *
 457 *  Initialize the function pointers and for MAC type X550EM.
 458 *  Does not touch the hardware.
 459 **/
 460 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 461 {
 462         struct ixgbe_mac_info *mac = &hw->mac;
 463         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 464         struct ixgbe_phy_info *phy = &hw->phy;
 465         struct ixgbe_link_info *link = &hw->link;
 466         s32 ret_val;
 467
 468         DEBUGFUNC("ixgbe_init_ops_X550EM");
 469
 470         /* Similar to X550 so start there. */
 471         ret_val = ixgbe_init_ops_X550(hw);
 472
 473         /* Since this function eventually calls
 474          * ixgbe_init_ops_540 by design, we are setting
 475          * the pointers to NULL explicitly here to overwrite
 476          * the values being set in the x540 function.
 477          */
 478         /* Thermal sensor not supported in x550EM */
 479         mac->ops.get_thermal_sensor_data = NULL;
 480         mac->ops.init_thermal_sensor_thresh = NULL;
 481         mac->thermal_sensor_enabled = false;
 482
 483         /* FCOE not supported in x550EM */
 484         mac->ops.get_san_mac_addr = NULL;
 485         mac->ops.set_san_mac_addr = NULL;
 486         mac->ops.get_wwn_prefix = NULL;
 487         mac->ops.get_fcoe_boot_status = NULL;
 488
 489         /* IPsec not supported in x550EM */
 490         mac->ops.disable_sec_rx_path = NULL;
 491         mac->ops.enable_sec_rx_path = NULL;
 492
 493         /* AUTOC register is not present in x550EM. */
 494         mac->ops.prot_autoc_read = NULL;
 495         mac->ops.prot_autoc_write = NULL;
 496
 497         /* X550EM bus type is internal*/
 498         hw->bus.type = ixgbe_bus_type_internal;
 499         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 500
 501         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 502                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 503                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 504                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 505                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 506                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 507                 link->ops.read_link_unlocked =
 508                                 ixgbe_read_i2c_combined_generic_unlocked;
 509                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 510                 link->ops.write_link_unlocked =
 511                                 ixgbe_write_i2c_combined_generic_unlocked;
 512                 link->addr = IXGBE_CS4227;
 513         }
 514         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 515                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a;
 516                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a;
 517                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 518                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 519         }
 520
 521         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 522         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 523         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 524         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 525         mac->ops.get_supported_physical_layer =
 526                                     ixgbe_get_supported_physical_layer_X550em;
 527
 528         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 529                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 530         else
 531                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 532
 533
 534         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)
 535                 mac->ops.setup_eee = NULL;
 536
 537         /* PHY */
 538         phy->ops.init = ixgbe_init_phy_ops_X550em;
 539         phy->ops.identify = ixgbe_identify_phy_x550em;
 540         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 541                 phy->ops.set_phy_power = NULL;
 542
 543
 544         /* EEPROM */
 545         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 546         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 547         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 548         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 549         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 550         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 551         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 552         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 553
 554         return ret_val;
 555 }
 556
 557 /**
 558  *  ixgbe_dmac_config_X550
 559  *  @hw: pointer to hardware structure
 560  *
 561  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 562  *  When disabling dmac, dmac enable dmac bit is cleared.
 563  **/
 564 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 565 {
 566         u32 reg, high_pri_tc;
 567
 568         DEBUGFUNC("ixgbe_dmac_config_X550");
 569
 570         /* Disable DMA coalescing before configuring */
 571         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 572         reg &= ~IXGBE_DMACR_DMAC_EN;
 573         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 574
 575         /* Disable DMA Coalescing if the watchdog timer is 0 */
 576         if (!hw->mac.dmac_config.watchdog_timer)
 577                 goto out;
 578
 579         ixgbe_dmac_config_tcs_X550(hw);
 580
 581         /* Configure DMA Coalescing Control Register */
 582         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 583
 584         /* Set the watchdog timer in units of 40.96 usec */
 585         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 586         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 587
 588         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 589         /* If fcoe is enabled, set high priority traffic class */
 590         if (hw->mac.dmac_config.fcoe_en) {
 591                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 592                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 593                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 594         }
 595         reg |= IXGBE_DMACR_EN_MNG_IND;
 596
 597         /* Enable DMA coalescing after configuration */
 598         reg |= IXGBE_DMACR_DMAC_EN;
 599         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 600
 601 out:
 602         return IXGBE_SUCCESS;
 603 }
 604
 605 /**
 606  *  ixgbe_dmac_config_tcs_X550
 607  *  @hw: pointer to hardware structure
 608  *
 609  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 610  *  be cleared before configuring.
 611  **/
 612 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 613 {
 614         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 615
 616         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 617
 618         /* Configure DMA coalescing enabled */
 619         switch (hw->mac.dmac_config.link_speed) {
 620         case IXGBE_LINK_SPEED_100_FULL:
 621                 pb_headroom = IXGBE_DMACRXT_100M;
 622                 break;
 623         case IXGBE_LINK_SPEED_1GB_FULL:
 624                 pb_headroom = IXGBE_DMACRXT_1G;
 625                 break;
 626         default:
 627                 pb_headroom = IXGBE_DMACRXT_10G;
 628                 break;
 629         }
 630
 631         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 632                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 633
 634         /* Set the per Rx packet buffer receive threshold */
 635         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 636                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 637                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 638
 639                 if (tc < hw->mac.dmac_config.num_tcs) {
 640                         /* Get Rx PB size */
 641                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 642                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 643                                 IXGBE_RXPBSIZE_SHIFT;
 644
 645                         /* Calculate receive buffer threshold in kilobytes */
 646                         if (rx_pb_size > pb_headroom)
 647                                 rx_pb_size = rx_pb_size - pb_headroom;
 648                         else
 649                                 rx_pb_size = 0;
 650
 651                         /* Minimum of MFS shall be set for DMCTH */
 652                         reg |= (rx_pb_size > maxframe_size_kb) ?
 653                                 rx_pb_size : maxframe_size_kb;
 654                 }
 655                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 656         }
 657         return IXGBE_SUCCESS;
 658 }
 659
 660 /**
 661  *  ixgbe_dmac_update_tcs_X550
 662  *  @hw: pointer to hardware structure
 663  *
 664  *  Disables dmac, updates per TC settings, and then enables dmac.
 665  **/
 666 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 667 {
 668         u32 reg;
 669
 670         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 671
 672         /* Disable DMA coalescing before configuring */
 673         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 674         reg &= ~IXGBE_DMACR_DMAC_EN;
 675         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 676
 677         ixgbe_dmac_config_tcs_X550(hw);
 678
 679         /* Enable DMA coalescing after configuration */
 680         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 681         reg |= IXGBE_DMACR_DMAC_EN;
 682         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 683
 684         return IXGBE_SUCCESS;
 685 }
 686
 687 /**
 688  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 689  *  @hw: pointer to hardware structure
 690  *
 691  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 692  *  ixgbe_hw struct in order to set up EEPROM access.
 693  **/
 694 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 695 {
 696         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 697         u32 eec;
 698         u16 eeprom_size;
 699
 700         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 701
 702         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 703                 eeprom->semaphore_delay = 10;
 704                 eeprom->type = ixgbe_flash;
 705
 706                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 707                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 708                                     IXGBE_EEC_SIZE_SHIFT);
 709                 eeprom->word_size = 1 << (eeprom_size +
 710                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 711
 712                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 713                           eeprom->type, eeprom->word_size);
 714         }
 715
 716         return IXGBE_SUCCESS;
 717 }
 718
 719 /**
 720  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 721  *  @hw: pointer to the HW structure
 722  *  @enable_eee: boolean flag to enable EEE
 723  *
 724  *  Enable/disable EEE based on enable_eee flag.
 725  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 726  *  are modified.
 727  *
 728  **/
 729 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 730 {
 731         u32 eeer;
 732         u16 autoneg_eee_reg;
 733         u32 link_reg;
 734         s32 status;
 735
 736         DEBUGFUNC("ixgbe_setup_eee_X550");
 737
 738         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 739         /* Enable or disable EEE per flag */
 740         if (enable_eee) {
 741                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 742
 743                 if (hw->mac.type == ixgbe_mac_X550) {
 744                         /* Advertise EEE capability */
 745                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 746                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 747
 748                         autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 749                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 750                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 751
 752                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 753                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 754                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 755                         /* Not supported on first revision of X550EM_x. */
 756                         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
 757                             !(IXGBE_FUSES0_REV_MASK &
 758                               IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
 759                                 return IXGBE_SUCCESS;
 760
 761                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 762                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 763                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 764                         if (status != IXGBE_SUCCESS)
 765                                 return status;
 766
 767                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 768                                     IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 769
 770                         /* Don't advertise FEC capability when EEE enabled. */
 771                         link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 772
 773                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 774                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 775                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 776                         if (status != IXGBE_SUCCESS)
 777                                 return status;
 778                 }
 779         } else {
 780                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 781
 782                 if (hw->mac.type == ixgbe_mac_X550) {
 783                         /* Disable advertised EEE capability */
 784                         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 785                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);
 786
 787                         autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 788                                 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 789                                 IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 790
 791                         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 792                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);
 793                 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
 794                         status = ixgbe_read_iosf_sb_reg_x550(hw,
 795                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 796                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 797                         if (status != IXGBE_SUCCESS)
 798                                 return status;
 799
 800                         link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 801                                 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 802
 803                         /* Advertise FEC capability when EEE is disabled. */
 804                         link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 805
 806                         status = ixgbe_write_iosf_sb_reg_x550(hw,
 807                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 808                                 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 809                         if (status != IXGBE_SUCCESS)
 810                                 return status;
 811                 }
 812         }
 813         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
 814
 815         return IXGBE_SUCCESS;
 816 }
 817
 818 /**
 819  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
 820  * @hw: pointer to hardware structure
 821  * @enable: enable or disable source address pruning
 822  * @pool: Rx pool to set source address pruning for
 823  **/
 824 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
 825                                            unsigned int pool)
 826 {
 827         u64 pfflp;
 828
 829         /* max rx pool is 63 */
 830         if (pool > 63)
 831                 return;
 832
 833         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
 834         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
 835
 836         if (enable)
 837                 pfflp |= (1ULL << pool);
 838         else
 839                 pfflp &= ~(1ULL << pool);
 840
 841         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
 842         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
 843 }
 844
 845 /**
 846  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
 847  *  @hw: pointer to hardware structure
 848  *  @enable: enable or disable switch for Ethertype anti-spoofing
 849  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
 850  *
 851  **/
 852 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
 853                 bool enable, int vf)
 854 {
 855         int vf_target_reg = vf >> 3;
 856         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
 857         u32 pfvfspoof;
 858
 859         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
 860
 861         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 862         if (enable)
 863                 pfvfspoof |= (1 << vf_target_shift);
 864         else
 865                 pfvfspoof &= ~(1 << vf_target_shift);
 866
 867         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 868 }
 869
 870 /**
 871  * ixgbe_iosf_wait - Wait for IOSF command completion
 872  * @hw: pointer to hardware structure
 873  * @ctrl: pointer to location to receive final IOSF control value
 874  *
 875  * Returns failing status on timeout
 876  *
 877  * Note: ctrl can be NULL if the IOSF control register value is not needed
 878  **/
 879 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 880 {
 881         u32 i, command = 0;
 882
 883         /* Check every 10 usec to see if the address cycle completed.
 884          * The SB IOSF BUSY bit will clear when the operation is
 885          * complete
 886          */
 887         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 888                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 889                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
 890                         break;
 891                 usec_delay(10);
 892         }
 893         if (ctrl)
 894                 *ctrl = command;
 895         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 896                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
 897                 return IXGBE_ERR_PHY;
 898         }
 899
 900         return IXGBE_SUCCESS;
 901 }
 902
 903 /**
 904  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 905  *  device
 906  *  @hw: pointer to hardware structure
 907  *  @reg_addr: 32 bit PHY register to write
 908  *  @device_type: 3 bit device type
 909  *  @data: Data to write to the register
 910  **/
 911 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 912                             u32 device_type, u32 data)
 913 {
 914         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 915         u32 command, error;
 916         s32 ret;
 917
 918         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 919         if (ret != IXGBE_SUCCESS)
 920                 return ret;
 921
 922         ret = ixgbe_iosf_wait(hw, NULL);
 923         if (ret != IXGBE_SUCCESS)
 924                 goto out;
 925
 926         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 927                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 928
 929         /* Write IOSF control register */
 930         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 931
 932         /* Write IOSF data register */
 933         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
 934
 935         ret = ixgbe_iosf_wait(hw, &command);
 936
 937         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 938                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 939                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 940                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 941                               "Failed to write, error %x\n", error);
 942                 ret = IXGBE_ERR_PHY;
 943         }
 944
 945 out:
 946         ixgbe_release_swfw_semaphore(hw, gssr);
 947         return ret;
 948 }
 949
 950 /**
 951  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
 952  *  device
 953  *  @hw: pointer to hardware structure
 954  *  @reg_addr: 32 bit PHY register to write
 955  *  @device_type: 3 bit device type
 956  *  @phy_data: Pointer to read data from the register
 957  **/
 958 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 959                            u32 device_type, u32 *data)
 960 {
 961         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 962         u32 command, error;
 963         s32 ret;
 964
 965         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
 966         if (ret != IXGBE_SUCCESS)
 967                 return ret;
 968
 969         ret = ixgbe_iosf_wait(hw, NULL);
 970         if (ret != IXGBE_SUCCESS)
 971                 goto out;
 972
 973         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 974                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 975
 976         /* Write IOSF control register */
 977         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 978
 979         ret = ixgbe_iosf_wait(hw, &command);
 980
 981         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 982                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 983                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 984                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
 985                                 "Failed to read, error %x\n", error);
 986                 ret = IXGBE_ERR_PHY;
 987         }
 988
 989         if (ret == IXGBE_SUCCESS)
 990                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 991
 992 out:
 993         ixgbe_release_swfw_semaphore(hw, gssr);
 994         return ret;
 995 }
 996
 997 /**
 998  * ixgbe_get_phy_token - Get the token for shared phy access
 999  * @hw: Pointer to hardware structure
1000  */
1001
1002 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1003 {
1004         struct ixgbe_hic_phy_token_req token_cmd;
1005         s32 status;
1006
1007         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1008         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1009         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1010         token_cmd.port_number = hw->bus.lan_id;
1011         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1012         token_cmd.pad = 0;
1013         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1014                                               sizeof(token_cmd),
1015                                               IXGBE_HI_COMMAND_TIMEOUT,
1016                                               true);
1017         if (status)
1018                 return status;
1019         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1020                 return IXGBE_SUCCESS;
1021         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1022                 return IXGBE_ERR_FW_RESP_INVALID;
1023
1024         return IXGBE_ERR_TOKEN_RETRY;
1025 }
1026
1027 /**
1028  * ixgbe_put_phy_token - Put the token for shared phy access
1029  * @hw: Pointer to hardware structure
1030  */
1031
1032 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1033 {
1034         struct ixgbe_hic_phy_token_req token_cmd;
1035         s32 status;
1036
1037         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1038         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1039         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1040         token_cmd.port_number = hw->bus.lan_id;
1041         token_cmd.command_type = FW_PHY_TOKEN_REL;
1042         token_cmd.pad = 0;
1043         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1044                                               sizeof(token_cmd),
1045                                               IXGBE_HI_COMMAND_TIMEOUT,
1046                                               true);
1047         if (status)
1048                 return status;
1049         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1050                 return IXGBE_SUCCESS;
1051         return IXGBE_ERR_FW_RESP_INVALID;
1052 }
1053
1054 /**
1055  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1056  *  of the IOSF device
1057  *  @hw: pointer to hardware structure
1058  *  @reg_addr: 32 bit PHY register to write
1059  *  @device_type: 3 bit device type
1060  *  @data: Data to write to the register
1061  **/
1062 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1063         u32 device_type, u32 data)
1064 {
1065         struct ixgbe_hic_internal_phy_req write_cmd;
1066         s32 status;
1067         UNREFERENCED_1PARAMETER(device_type);
1068
1069         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1070         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1071         write_cmd.port_number = hw->bus.lan_id;
1072         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1073         write_cmd.address = (u16)reg_addr;
1074         write_cmd.rsv1 = 0;
1075         write_cmd.write_data = data;
1076         write_cmd.pad = 0;
1077
1078         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1079                 sizeof(write_cmd), IXGBE_HI_COMMAND_TIMEOUT, false);
1080
1081         return status;
1082 }
1083
1084 /**
1085  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1086  *  of the IOSF device.
1087  *  @hw: pointer to hardware structure
1088  *  @reg_addr: 32 bit PHY register to write
1089  *  @device_type: 3 bit device type
1090  *  @data: Pointer to read data from the register
1091  **/
1092 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1093         u32 device_type, u32 *data)
1094 {
1095         struct ixgbe_hic_internal_phy_req read_cmd;
1096         s32 status;
1097         UNREFERENCED_1PARAMETER(device_type);
1098
1099         read_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1100         read_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1101         read_cmd.port_number = hw->bus.lan_id;
1102         read_cmd.command_type = FW_INT_PHY_REQ_READ;
1103         read_cmd.address = (u16)reg_addr;
1104         read_cmd.rsv1 = 0;
1105         read_cmd.write_data = 0;
1106         read_cmd.pad = 0;
1107
1108         status = ixgbe_host_interface_command(hw, (u32 *)&read_cmd,
1109                 sizeof(read_cmd), IXGBE_HI_COMMAND_TIMEOUT, true);
1110
1111         /* Extract the register value from the response. */
1112         *data = ((struct ixgbe_hic_internal_phy_resp *)&read_cmd)->read_data;
1113
1114         return status;
1115 }
1116
1117 /**
1118  *  ixgbe_disable_mdd_X550
1119  *  @hw: pointer to hardware structure
1120  *
1121  *  Disable malicious driver detection
1122  **/
1123 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1124 {
1125         u32 reg;
1126
1127         DEBUGFUNC("ixgbe_disable_mdd_X550");
1128
1129         /* Disable MDD for TX DMA and interrupt */
1130         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1131         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1132         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1133
1134         /* Disable MDD for RX and interrupt */
1135         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1136         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1137         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1138 }
1139
1140 /**
1141  *  ixgbe_enable_mdd_X550
1142  *  @hw: pointer to hardware structure
1143  *
1144  *  Enable malicious driver detection
1145  **/
1146 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1147 {
1148         u32 reg;
1149
1150         DEBUGFUNC("ixgbe_enable_mdd_X550");
1151
1152         /* Enable MDD for TX DMA and interrupt */
1153         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1154         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1155         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1156
1157         /* Enable MDD for RX and interrupt */
1158         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1159         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1160         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1161 }
1162
1163 /**
1164  *  ixgbe_restore_mdd_vf_X550
1165  *  @hw: pointer to hardware structure
1166  *  @vf: vf index
1167  *
1168  *  Restore VF that was disabled during malicious driver detection event
1169  **/
1170 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1171 {
1172         u32 idx, reg, num_qs, start_q, bitmask;
1173
1174         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1175
1176         /* Map VF to queues */
1177         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1178         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1179         case IXGBE_MRQC_VMDQRT8TCEN:
1180                 num_qs = 8;  /* 16 VFs / pools */
1181                 bitmask = 0x000000FF;
1182                 break;
1183         case IXGBE_MRQC_VMDQRSS32EN:
1184         case IXGBE_MRQC_VMDQRT4TCEN:
1185                 num_qs = 4;  /* 32 VFs / pools */
1186                 bitmask = 0x0000000F;
1187                 break;
1188         default:            /* 64 VFs / pools */
1189                 num_qs = 2;
1190                 bitmask = 0x00000003;
1191                 break;
1192         }
1193         start_q = vf * num_qs;
1194
1195         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1196         idx = start_q / 32;
1197         reg = 0;
1198         reg |= (bitmask << (start_q % 32));
1199         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1200         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1201 }
1202
1203 /**
1204  *  ixgbe_mdd_event_X550
1205  *  @hw: pointer to hardware structure
1206  *  @vf_bitmap: vf bitmap of malicious vfs
1207  *
1208  *  Handle malicious driver detection event.
1209  **/
1210 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1211 {
1212         u32 wqbr;
1213         u32 i, j, reg, q, shift, vf, idx;
1214
1215         DEBUGFUNC("ixgbe_mdd_event_X550");
1216
1217         /* figure out pool size for mapping to vf's */
1218         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1219         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1220         case IXGBE_MRQC_VMDQRT8TCEN:
1221                 shift = 3;  /* 16 VFs / pools */
1222                 break;
1223         case IXGBE_MRQC_VMDQRSS32EN:
1224         case IXGBE_MRQC_VMDQRT4TCEN:
1225                 shift = 2;  /* 32 VFs / pools */
1226                 break;
1227         default:
1228                 shift = 1;  /* 64 VFs / pools */
1229                 break;
1230         }
1231
1232         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1233         for (i = 0; i < 4; i++) {
1234                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1235                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1236
1237                 if (!wqbr)
1238                         continue;
1239
1240                 /* Get malicious queue */
1241                 for (j = 0; j < 32 && wqbr; j++) {
1242
1243                         if (!(wqbr & (1 << j)))
1244                                 continue;
1245
1246                         /* Get queue from bitmask */
1247                         q = j + (i * 32);
1248
1249                         /* Map queue to vf */
1250                         vf = (q >> shift);
1251
1252                         /* Set vf bit in vf_bitmap */
1253                         idx = vf / 32;
1254                         vf_bitmap[idx] |= (1 << (vf % 32));
1255                         wqbr &= ~(1 << j);
1256                 }
1257         }
1258 }
1259
1260 /**
1261  *  ixgbe_get_media_type_X550em - Get media type
1262  *  @hw: pointer to hardware structure
1263  *
1264  *  Returns the media type (fiber, copper, backplane)
1265  */
1266 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1267 {
1268         enum ixgbe_media_type media_type;
1269
1270         DEBUGFUNC("ixgbe_get_media_type_X550em");
1271
1272         /* Detect if there is a copper PHY attached. */
1273         switch (hw->device_id) {
1274         case IXGBE_DEV_ID_X550EM_X_KR:
1275         case IXGBE_DEV_ID_X550EM_X_KX4:
1276         case IXGBE_DEV_ID_X550EM_A_KR:
1277         case IXGBE_DEV_ID_X550EM_A_KR_L:
1278                 media_type = ixgbe_media_type_backplane;
1279                 break;
1280         case IXGBE_DEV_ID_X550EM_X_SFP:
1281         case IXGBE_DEV_ID_X550EM_A_SFP:
1282         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1283         case IXGBE_DEV_ID_X550EM_A_QSFP:
1284         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1285                 media_type = ixgbe_media_type_fiber;
1286                 break;
1287         case IXGBE_DEV_ID_X550EM_X_1G_T:
1288         case IXGBE_DEV_ID_X550EM_X_10G_T:
1289         case IXGBE_DEV_ID_X550EM_A_1G_T:
1290         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1291         case IXGBE_DEV_ID_X550EM_A_10G_T:
1292                 media_type = ixgbe_media_type_copper;
1293                 break;
1294         default:
1295                 media_type = ixgbe_media_type_unknown;
1296                 break;
1297         }
1298         return media_type;
1299 }
1300
1301 /**
1302  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1303  *  @hw: pointer to hardware structure
1304  *  @linear: true if SFP module is linear
1305  */
1306 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1307 {
1308         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1309
1310         switch (hw->phy.sfp_type) {
1311         case ixgbe_sfp_type_not_present:
1312                 return IXGBE_ERR_SFP_NOT_PRESENT;
1313         case ixgbe_sfp_type_da_cu_core0:
1314         case ixgbe_sfp_type_da_cu_core1:
1315                 *linear = true;
1316                 break;
1317         case ixgbe_sfp_type_srlr_core0:
1318         case ixgbe_sfp_type_srlr_core1:
1319         case ixgbe_sfp_type_da_act_lmt_core0:
1320         case ixgbe_sfp_type_da_act_lmt_core1:
1321         case ixgbe_sfp_type_1g_sx_core0:
1322         case ixgbe_sfp_type_1g_sx_core1:
1323         case ixgbe_sfp_type_1g_lx_core0:
1324         case ixgbe_sfp_type_1g_lx_core1:
1325                 *linear = false;
1326                 break;
1327         case ixgbe_sfp_type_unknown:
1328         case ixgbe_sfp_type_1g_cu_core0:
1329         case ixgbe_sfp_type_1g_cu_core1:
1330         default:
1331                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1332         }
1333
1334         return IXGBE_SUCCESS;
1335 }
1336
1337 /**
1338  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1339  *  @hw: pointer to hardware structure
1340  *
1341  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1342  **/
1343 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1344 {
1345         s32 status;
1346         bool linear;
1347
1348         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1349
1350         status = ixgbe_identify_module_generic(hw);
1351
1352         if (status != IXGBE_SUCCESS)
1353                 return status;
1354
1355         /* Check if SFP module is supported */
1356         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1357
1358         return status;
1359 }
1360
1361 /**
1362  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1363  *  @hw: pointer to hardware structure
1364  */
1365 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1366 {
1367         s32 status;
1368         bool linear;
1369
1370         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1371
1372         /* Check if SFP module is supported */
1373         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1374
1375         if (status != IXGBE_SUCCESS)
1376                 return status;
1377
1378         ixgbe_init_mac_link_ops_X550em(hw);
1379         hw->phy.ops.reset = NULL;
1380
1381         return IXGBE_SUCCESS;
1382 }
1383
1384 /**
1385  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1386  *  @hw: pointer to hardware structure
1387  */
1388 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1389 {
1390         struct ixgbe_mac_info *mac = &hw->mac;
1391
1392         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1393
1394          switch (hw->mac.ops.get_media_type(hw)) {
1395          case ixgbe_media_type_fiber:
1396                 /* CS4227 does not support autoneg, so disable the laser control
1397                  * functions for SFP+ fiber
1398                  */
1399                 mac->ops.disable_tx_laser = NULL;
1400                 mac->ops.enable_tx_laser = NULL;
1401                 mac->ops.flap_tx_laser = NULL;
1402                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1403                 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;
1404                 mac->ops.set_rate_select_speed =
1405                                         ixgbe_set_soft_rate_select_speed;
1406                 break;
1407         case ixgbe_media_type_copper:
1408                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1409                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1410                 break;
1411         default:
1412                 break;
1413          }
1414 }
1415
1416 /**
1417  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1418  *  @hw: pointer to hardware structure
1419  *  @speed: pointer to link speed
1420  *  @autoneg: true when autoneg or autotry is enabled
1421  */
1422 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1423                                        ixgbe_link_speed *speed,
1424                                        bool *autoneg)
1425 {
1426         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1427
1428         /* SFP */
1429         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1430
1431                 /* CS4227 SFP must not enable auto-negotiation */
1432                 *autoneg = false;
1433
1434                 /* Check if 1G SFP module. */
1435                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1436                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1437                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1438                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1439                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1440                         return IXGBE_SUCCESS;
1441                 }
1442
1443                 /* Link capabilities are based on SFP */
1444                 if (hw->phy.multispeed_fiber)
1445                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1446                                  IXGBE_LINK_SPEED_1GB_FULL;
1447                 else
1448                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1449         } else {
1450                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1451                          IXGBE_LINK_SPEED_1GB_FULL;
1452                 *autoneg = true;
1453         }
1454
1455         return IXGBE_SUCCESS;
1456 }
1457
1458 /**
1459  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1460  * @hw: pointer to hardware structure
1461  * @lsc: pointer to boolean flag which indicates whether external Base T
1462  *       PHY interrupt is lsc
1463  *
1464  * Determime if external Base T PHY interrupt cause is high temperature
1465  * failure alarm or link status change.
1466  *
1467  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1468  * failure alarm, else return PHY access status.
1469  */
1470 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1471 {
1472         u32 status;
1473         u16 reg;
1474
1475         *lsc = false;
1476
1477         /* Vendor alarm triggered */
1478         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1479                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1480                                       &reg);
1481
1482         if (status != IXGBE_SUCCESS ||
1483             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1484                 return status;
1485
1486         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1487         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1488                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1489                                       &reg);
1490
1491         if (status != IXGBE_SUCCESS ||
1492             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1493             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1494                 return status;
1495
1496         /* Global alarm triggered */
1497         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1498                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1499                                       &reg);
1500
1501         if (status != IXGBE_SUCCESS)
1502                 return status;
1503
1504         /* If high temperature failure, then return over temp error and exit */
1505         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1506                 /* power down the PHY in case the PHY FW didn't already */
1507                 ixgbe_set_copper_phy_power(hw, false);
1508                 return IXGBE_ERR_OVERTEMP;
1509         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1510                 /*  device fault alarm triggered */
1511                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1512                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1513                                           &reg);
1514
1515                 if (status != IXGBE_SUCCESS)
1516                         return status;
1517
1518                 /* if device fault was due to high temp alarm handle and exit */
1519                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1520                         /* power down the PHY in case the PHY FW didn't */
1521                         ixgbe_set_copper_phy_power(hw, false);
1522                         return IXGBE_ERR_OVERTEMP;
1523                 }
1524         }
1525
1526         /* Vendor alarm 2 triggered */
1527         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1528                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1529
1530         if (status != IXGBE_SUCCESS ||
1531             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1532                 return status;
1533
1534         /* link connect/disconnect event occurred */
1535         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1536                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1537
1538         if (status != IXGBE_SUCCESS)
1539                 return status;
1540
1541         /* Indicate LSC */
1542         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1543                 *lsc = true;
1544
1545         return IXGBE_SUCCESS;
1546 }
1547
1548 /**
1549  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1550  * @hw: pointer to hardware structure
1551  *
1552  * Enable link status change and temperature failure alarm for the external
1553  * Base T PHY
1554  *
1555  * Returns PHY access status
1556  */
1557 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1558 {
1559         u32 status;
1560         u16 reg;
1561         bool lsc;
1562
1563         /* Clear interrupt flags */
1564         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1565
1566         /* Enable link status change alarm */
1567         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1568                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1569
1570         if (status != IXGBE_SUCCESS)
1571                 return status;
1572
1573         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1574
1575         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1576                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1577
1578         if (status != IXGBE_SUCCESS)
1579                 return status;
1580
1581         /* Enable high temperature failure and global fault alarms */
1582         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1583                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1584                                       &reg);
1585
1586         if (status != IXGBE_SUCCESS)
1587                 return status;
1588
1589         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1590                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1591
1592         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1593                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1594                                        reg);
1595
1596         if (status != IXGBE_SUCCESS)
1597                 return status;
1598
1599         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1600         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1601                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1602                                       &reg);
1603
1604         if (status != IXGBE_SUCCESS)
1605                 return status;
1606
1607         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1608                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1609
1610         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1611                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1612                                        reg);
1613
1614         if (status != IXGBE_SUCCESS)
1615                 return status;
1616
1617         /* Enable chip-wide vendor alarm */
1618         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1619                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1620                                       &reg);
1621
1622         if (status != IXGBE_SUCCESS)
1623                 return status;
1624
1625         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1626
1627         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1628                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1629                                        reg);
1630
1631         return status;
1632 }
1633
1634 /**
1635  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1636  *  @hw: pointer to hardware structure
1637  *  @speed: link speed
1638  *
1639  *  Configures the integrated KR PHY.
1640  **/
1641 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1642                                        ixgbe_link_speed speed)
1643 {
1644         s32 status;
1645         u32 reg_val;
1646
1647         status = ixgbe_read_iosf_sb_reg_x550(hw,
1648                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1649                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1650         if (status)
1651                 return status;
1652
1653         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1654         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1655                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1656
1657         /* Advertise 10G support. */
1658         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1659                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1660
1661         /* Advertise 1G support. */
1662         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1663                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1664
1665         /* Restart auto-negotiation. */
1666         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1667         status = ixgbe_write_iosf_sb_reg_x550(hw,
1668                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1669                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1670
1671         return status;
1672 }
1673
1674 /**
1675  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1676  *  @hw: pointer to hardware structure
1677  *
1678  *  Initialize any function pointers that were not able to be
1679  *  set during init_shared_code because the PHY/SFP type was
1680  *  not known.  Perform the SFP init if necessary.
1681  */
1682 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
1683 {
1684         struct ixgbe_phy_info *phy = &hw->phy;
1685         s32 ret_val;
1686
1687         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
1688
1689         hw->mac.ops.set_lan_id(hw);
1690
1691         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
1692                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
1693                 ixgbe_setup_mux_ctl(hw);
1694
1695                 /* Save NW management interface connected on board. This is used
1696                  * to determine internal PHY mode.
1697                  */
1698                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1699                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
1700         }
1701
1702         /* Identify the PHY or SFP module */
1703         ret_val = phy->ops.identify(hw);
1704         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
1705                 return ret_val;
1706
1707         /* Setup function pointers based on detected hardware */
1708         ixgbe_init_mac_link_ops_X550em(hw);
1709         if (phy->sfp_type != ixgbe_sfp_type_unknown)
1710                 phy->ops.reset = NULL;
1711
1712         /* Set functions pointers based on phy type */
1713         switch (hw->phy.type) {
1714         case ixgbe_phy_x550em_kx4:
1715                 phy->ops.setup_link = NULL;
1716                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1717                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1718                 break;
1719         case ixgbe_phy_x550em_kr:
1720                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
1721                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
1722                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
1723                 break;
1724         case ixgbe_phy_x550em_ext_t:
1725                 /* Save NW management interface connected on board. This is used
1726                  * to determine internal PHY mode
1727                  */
1728                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
1729
1730                 /* If internal link mode is XFI, then setup iXFI internal link,
1731                  * else setup KR now.
1732                  */
1733                 phy->ops.setup_internal_link =
1734                                               ixgbe_setup_internal_phy_t_x550em;
1735
1736                 /* setup SW LPLU only for first revision of X550EM_x */
1737                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1738                     !(IXGBE_FUSES0_REV_MASK &
1739                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1740                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
1741
1742                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
1743                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
1744                 break;
1745         default:
1746                 break;
1747         }
1748         return ret_val;
1749 }
1750
1751 /**
1752  * ixgbe_set_mdio_speed - Set MDIO clock speed
1753  *  @hw: pointer to hardware structure
1754  */
1755 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
1756 {
1757         u32 hlreg0;
1758
1759         switch (hw->device_id) {
1760         case IXGBE_DEV_ID_X550EM_X_10G_T:
1761         case IXGBE_DEV_ID_X550EM_A_1G_T:
1762         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1763         case IXGBE_DEV_ID_X550EM_A_10G_T:
1764         case IXGBE_DEV_ID_X550EM_A_SFP:
1765         case IXGBE_DEV_ID_X550EM_A_QSFP:
1766                 /* Config MDIO clock speed before the first MDIO PHY access */
1767                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1768                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
1769                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1770                 break;
1771         default:
1772                 break;
1773         }
1774 }
1775
1776 /**
1777  *  ixgbe_reset_hw_X550em - Perform hardware reset
1778  *  @hw: pointer to hardware structure
1779  *
1780  *  Resets the hardware by resetting the transmit and receive units, masks
1781  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1782  *  reset.
1783  */
1784 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
1785 {
1786         ixgbe_link_speed link_speed;
1787         s32 status;
1788         u32 ctrl = 0;
1789         u32 i;
1790         bool link_up = false;
1791
1792         DEBUGFUNC("ixgbe_reset_hw_X550em");
1793
1794         /* Call adapter stop to disable Tx/Rx and clear interrupts */
1795         status = hw->mac.ops.stop_adapter(hw);
1796         if (status != IXGBE_SUCCESS)
1797                 return status;
1798
1799         /* flush pending Tx transactions */
1800         ixgbe_clear_tx_pending(hw);
1801
1802         ixgbe_set_mdio_speed(hw);
1803
1804         /* PHY ops must be identified and initialized prior to reset */
1805         status = hw->phy.ops.init(hw);
1806
1807         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1808                 return status;
1809
1810         /* start the external PHY */
1811         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
1812                 status = ixgbe_init_ext_t_x550em(hw);
1813                 if (status)
1814                         return status;
1815         }
1816
1817         /* Setup SFP module if there is one present. */
1818         if (hw->phy.sfp_setup_needed) {
1819                 status = hw->mac.ops.setup_sfp(hw);
1820                 hw->phy.sfp_setup_needed = false;
1821         }
1822
1823         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1824                 return status;
1825
1826         /* Reset PHY */
1827         if (!hw->phy.reset_disable && hw->phy.ops.reset)
1828                 hw->phy.ops.reset(hw);
1829
1830 mac_reset_top:
1831         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
1832          * If link reset is used when link is up, it might reset the PHY when
1833          * mng is using it.  If link is down or the flag to force full link
1834          * reset is set, then perform link reset.
1835          */
1836         ctrl = IXGBE_CTRL_LNK_RST;
1837         if (!hw->force_full_reset) {
1838                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1839                 if (link_up)
1840                         ctrl = IXGBE_CTRL_RST;
1841         }
1842
1843         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1844         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1845         IXGBE_WRITE_FLUSH(hw);
1846
1847         /* Poll for reset bit to self-clear meaning reset is complete */
1848         for (i = 0; i < 10; i++) {
1849                 usec_delay(1);
1850                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1851                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1852                         break;
1853         }
1854
1855         if (ctrl & IXGBE_CTRL_RST_MASK) {
1856                 status = IXGBE_ERR_RESET_FAILED;
1857                 DEBUGOUT("Reset polling failed to complete.\n");
1858         }
1859
1860         msec_delay(50);
1861
1862         /* Double resets are required for recovery from certain error
1863          * conditions.  Between resets, it is necessary to stall to
1864          * allow time for any pending HW events to complete.
1865          */
1866         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1867                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1868                 goto mac_reset_top;
1869         }
1870
1871         /* Store the permanent mac address */
1872         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1873
1874         /* Store MAC address from RAR0, clear receive address registers, and
1875          * clear the multicast table.  Also reset num_rar_entries to 128,
1876          * since we modify this value when programming the SAN MAC address.
1877          */
1878         hw->mac.num_rar_entries = 128;
1879         hw->mac.ops.init_rx_addrs(hw);
1880
1881         ixgbe_set_mdio_speed(hw);
1882
1883         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
1884                 ixgbe_setup_mux_ctl(hw);
1885
1886         return status;
1887 }
1888
1889 /**
1890  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1891  * @hw: pointer to hardware structure
1892  */
1893 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
1894 {
1895         u32 status;
1896         u16 reg;
1897
1898         status = hw->phy.ops.read_reg(hw,
1899                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
1900                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1901                                       &reg);
1902
1903         if (status != IXGBE_SUCCESS)
1904                 return status;
1905
1906         /* If PHY FW reset completed bit is set then this is the first
1907          * SW instance after a power on so the PHY FW must be un-stalled.
1908          */
1909         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
1910                 status = hw->phy.ops.read_reg(hw,
1911                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1912                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1913                                         &reg);
1914
1915                 if (status != IXGBE_SUCCESS)
1916                         return status;
1917
1918                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
1919
1920                 status = hw->phy.ops.write_reg(hw,
1921                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
1922                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1923                                         reg);
1924
1925                 if (status != IXGBE_SUCCESS)
1926                         return status;
1927         }
1928
1929         return status;
1930 }
1931
1932 /**
1933  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
1934  *  @hw: pointer to hardware structure
1935  *
1936  *  Configures the integrated KR PHY.
1937  **/
1938 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1939 {
1940         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
1941 }
1942
1943 /**
1944  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
1945  *  @hw: pointer to hardware structure
1946  *
1947  *  Configure the external PHY and the integrated KR PHY for SFP support.
1948  **/
1949 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1950                                     ixgbe_link_speed speed,
1951                                     bool autoneg_wait_to_complete)
1952 {
1953         s32 ret_val;
1954         u16 reg_slice, reg_val;
1955         bool setup_linear = false;
1956         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
1957
1958         /* Check if SFP module is supported and linear */
1959         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1960
1961         /* If no SFP module present, then return success. Return success since
1962          * there is no reason to configure CS4227 and SFP not present error is
1963          * not excepted in the setup MAC link flow.
1964          */
1965         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1966                 return IXGBE_SUCCESS;
1967
1968         if (ret_val != IXGBE_SUCCESS)
1969                 return ret_val;
1970
1971         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1972                 /* Configure CS4227 LINE side to 10G SR. */
1973                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
1974                             (hw->bus.lan_id << 12);
1975                 reg_val = IXGBE_CS4227_SPEED_10G;
1976                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1977                                                   reg_val);
1978
1979                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
1980                             (hw->bus.lan_id << 12);
1981                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1982                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1983                                                   reg_val);
1984
1985                 /* Configure CS4227 for HOST connection rate then type. */
1986                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
1987                             (hw->bus.lan_id << 12);
1988                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
1989                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1990                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1991                                                   reg_val);
1992
1993                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
1994                             (hw->bus.lan_id << 12);
1995                 if (setup_linear)
1996                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1997                 else
1998                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1999                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2000                                                   reg_val);
2001
2002                 /* Setup XFI internal link. */
2003                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2004         } else {
2005                 /* Configure internal PHY for KR/KX. */
2006                 ixgbe_setup_kr_speed_x550em(hw, speed);
2007
2008                 /* Configure CS4227 LINE side to proper mode. */
2009                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2010                             (hw->bus.lan_id << 12);
2011                 if (setup_linear)
2012                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2013                 else
2014                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2015                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2016                                                   reg_val);
2017         }
2018         return ret_val;
2019 }
2020
2021 /**
2022  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2023  *  @hw: pointer to hardware structure
2024  *
2025  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2026  **/
2027 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2028 {
2029         s32 status;
2030         u32 reg_val;
2031
2032         /* Disable training protocol FSM. */
2033         status = ixgbe_read_iosf_sb_reg_x550(hw,
2034                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2035                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2036         if (status != IXGBE_SUCCESS)
2037                 return status;
2038         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2039         status = ixgbe_write_iosf_sb_reg_x550(hw,
2040                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2041                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2042         if (status != IXGBE_SUCCESS)
2043                 return status;
2044
2045         /* Disable Flex from training TXFFE. */
2046         status = ixgbe_read_iosf_sb_reg_x550(hw,
2047                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2048                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2049         if (status != IXGBE_SUCCESS)
2050                 return status;
2051         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2052         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2053         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2054         status = ixgbe_write_iosf_sb_reg_x550(hw,
2055                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2056                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2057         if (status != IXGBE_SUCCESS)
2058                 return status;
2059         status = ixgbe_read_iosf_sb_reg_x550(hw,
2060                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2061                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2062         if (status != IXGBE_SUCCESS)
2063                 return status;
2064         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2065         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2066         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2067         status = ixgbe_write_iosf_sb_reg_x550(hw,
2068                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2069                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2070         if (status != IXGBE_SUCCESS)
2071                 return status;
2072
2073         /* Enable override for coefficients. */
2074         status = ixgbe_read_iosf_sb_reg_x550(hw,
2075                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2076                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2077         if (status != IXGBE_SUCCESS)
2078                 return status;
2079         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2080         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2081         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2082         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2083         status = ixgbe_write_iosf_sb_reg_x550(hw,
2084                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2085                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2086         return status;
2087 }
2088
2089 /**
2090  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2091  *  @hw: pointer to hardware structure
2092  *  @speed: the link speed to force
2093  *
2094  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2095  *  internal and external PHY at a specific speed, without autonegotiation.
2096  **/
2097 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2098 {
2099         s32 status;
2100         u32 reg_val;
2101
2102         /* Disable AN and force speed to 10G Serial. */
2103         status = ixgbe_read_iosf_sb_reg_x550(hw,
2104                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2105                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2106         if (status != IXGBE_SUCCESS)
2107                 return status;
2108
2109         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2110         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2111
2112         /* Select forced link speed for internal PHY. */
2113         switch (*speed) {
2114         case IXGBE_LINK_SPEED_10GB_FULL:
2115                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2116                 break;
2117         case IXGBE_LINK_SPEED_1GB_FULL:
2118                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2119                 break;
2120         default:
2121                 /* Other link speeds are not supported by internal KR PHY. */
2122                 return IXGBE_ERR_LINK_SETUP;
2123         }
2124
2125         status = ixgbe_write_iosf_sb_reg_x550(hw,
2126                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2127                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2128         if (status != IXGBE_SUCCESS)
2129                 return status;
2130
2131         /* Additional configuration needed for x550em_x */
2132         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2133                 status = ixgbe_setup_ixfi_x550em_x(hw);
2134                 if (status != IXGBE_SUCCESS)
2135                         return status;
2136         }
2137
2138         /* Toggle port SW reset by AN reset. */
2139         status = ixgbe_read_iosf_sb_reg_x550(hw,
2140                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2141                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2142         if (status != IXGBE_SUCCESS)
2143                 return status;
2144         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2145         status = ixgbe_write_iosf_sb_reg_x550(hw,
2146                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2147                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2148
2149         return status;
2150 }
2151
2152 /**
2153  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2154  * @hw: address of hardware structure
2155  * @link_up: address of boolean to indicate link status
2156  *
2157  * Returns error code if unable to get link status.
2158  */
2159 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2160 {
2161         u32 ret;
2162         u16 autoneg_status;
2163
2164         *link_up = false;
2165
2166         /* read this twice back to back to indicate current status */
2167         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2168                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2169                                    &autoneg_status);
2170         if (ret != IXGBE_SUCCESS)
2171                 return ret;
2172
2173         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2174                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2175                                    &autoneg_status);
2176         if (ret != IXGBE_SUCCESS)
2177                 return ret;
2178
2179         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2180
2181         return IXGBE_SUCCESS;
2182 }
2183
2184 /**
2185  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2186  * @hw: point to hardware structure
2187  *
2188  * Configures the link between the integrated KR PHY and the external X557 PHY
2189  * The driver will call this function when it gets a link status change
2190  * interrupt from the X557 PHY. This function configures the link speed
2191  * between the PHYs to match the link speed of the BASE-T link.
2192  *
2193  * A return of a non-zero value indicates an error, and the base driver should
2194  * not report link up.
2195  */
2196 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2197 {
2198         ixgbe_link_speed force_speed;
2199         bool link_up;
2200         u32 status;
2201         u16 speed;
2202
2203         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2204                 return IXGBE_ERR_CONFIG;
2205
2206         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2207                 /* If link is down, there is no setup necessary so return  */
2208                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2209                 if (status != IXGBE_SUCCESS)
2210                         return status;
2211
2212                 if (!link_up)
2213                         return IXGBE_SUCCESS;
2214
2215                 status = hw->phy.ops.read_reg(hw,
2216                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2217                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2218                                               &speed);
2219                 if (status != IXGBE_SUCCESS)
2220                         return status;
2221
2222                 /* If link is still down - no setup is required so return */
2223                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2224                 if (status != IXGBE_SUCCESS)
2225                         return status;
2226                 if (!link_up)
2227                         return IXGBE_SUCCESS;
2228
2229                 /* clear everything but the speed and duplex bits */
2230                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2231
2232                 switch (speed) {
2233                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2234                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2235                         break;
2236                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2237                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2238                         break;
2239                 default:
2240                         /* Internal PHY does not support anything else */
2241                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2242                 }
2243
2244                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2245         } else {
2246                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2247                         IXGBE_LINK_SPEED_1GB_FULL;
2248                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2249         }
2250 }
2251
2252 /**
2253  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2254  *  @hw: pointer to hardware structure
2255  *
2256  *  Configures the integrated KR PHY to use internal loopback mode.
2257  **/
2258 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2259 {
2260         s32 status;
2261         u32 reg_val;
2262
2263         /* Disable AN and force speed to 10G Serial. */
2264         status = ixgbe_read_iosf_sb_reg_x550(hw,
2265                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2266                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2267         if (status != IXGBE_SUCCESS)
2268                 return status;
2269         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2270         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2271         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2272         status = ixgbe_write_iosf_sb_reg_x550(hw,
2273                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2274                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2275         if (status != IXGBE_SUCCESS)
2276                 return status;
2277
2278         /* Set near-end loopback clocks. */
2279         status = ixgbe_read_iosf_sb_reg_x550(hw,
2280                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2281                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2282         if (status != IXGBE_SUCCESS)
2283                 return status;
2284         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2285         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2286         status = ixgbe_write_iosf_sb_reg_x550(hw,
2287                 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2288                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2289         if (status != IXGBE_SUCCESS)
2290                 return status;
2291
2292         /* Set loopback enable. */
2293         status = ixgbe_read_iosf_sb_reg_x550(hw,
2294                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2295                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2296         if (status != IXGBE_SUCCESS)
2297                 return status;
2298         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2299         status = ixgbe_write_iosf_sb_reg_x550(hw,
2300                 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2301                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2302         if (status != IXGBE_SUCCESS)
2303                 return status;
2304
2305         /* Training bypass. */
2306         status = ixgbe_read_iosf_sb_reg_x550(hw,
2307                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2308                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2309         if (status != IXGBE_SUCCESS)
2310                 return status;
2311         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2312         status = ixgbe_write_iosf_sb_reg_x550(hw,
2313                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2314                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2315
2316         return status;
2317 }
2318
2319 /**
2320  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2321  *  assuming that the semaphore is already obtained.
2322  *  @hw: pointer to hardware structure
2323  *  @offset: offset of  word in the EEPROM to read
2324  *  @data: word read from the EEPROM
2325  *
2326  *  Reads a 16 bit word from the EEPROM using the hostif.
2327  **/
2328 s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2329                                    u16 *data)
2330 {
2331         s32 status;
2332         struct ixgbe_hic_read_shadow_ram buffer;
2333
2334         DEBUGFUNC("ixgbe_read_ee_hostif_data_X550");
2335         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2336         buffer.hdr.req.buf_lenh = 0;
2337         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2338         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2339
2340         /* convert offset from words to bytes */
2341         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2342         /* one word */
2343         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2344
2345         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2346                                               sizeof(buffer),
2347                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2348
2349         if (status)
2350                 return status;
2351
2352         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2353                                           FW_NVM_DATA_OFFSET);
2354
2355         return 0;
2356 }
2357
2358 /**
2359  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2360  *  @hw: pointer to hardware structure
2361  *  @offset: offset of  word in the EEPROM to read
2362  *  @data: word read from the EEPROM
2363  *
2364  *  Reads a 16 bit word from the EEPROM using the hostif.
2365  **/
2366 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2367                               u16 *data)
2368 {
2369         s32 status = IXGBE_SUCCESS;
2370
2371         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2372
2373         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2374             IXGBE_SUCCESS) {
2375                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
2376                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2377         } else {
2378                 status = IXGBE_ERR_SWFW_SYNC;
2379         }
2380
2381         return status;
2382 }
2383
2384 /**
2385  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2386  *  @hw: pointer to hardware structure
2387  *  @offset: offset of  word in the EEPROM to read
2388  *  @words: number of words
2389  *  @data: word(s) read from the EEPROM
2390  *
2391  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2392  **/
2393 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2394                                      u16 offset, u16 words, u16 *data)
2395 {
2396         struct ixgbe_hic_read_shadow_ram buffer;
2397         u32 current_word = 0;
2398         u16 words_to_read;
2399         s32 status;
2400         u32 i;
2401
2402         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2403
2404         /* Take semaphore for the entire operation. */
2405         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2406         if (status) {
2407                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2408                 return status;
2409         }
2410         while (words) {
2411                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2412                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2413                 else
2414                         words_to_read = words;
2415
2416                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2417                 buffer.hdr.req.buf_lenh = 0;
2418                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2419                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2420
2421                 /* convert offset from words to bytes */
2422                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2423                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2424
2425                 status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2426                                                       sizeof(buffer),
2427                                                       IXGBE_HI_COMMAND_TIMEOUT,
2428                                                       false);
2429
2430                 if (status) {
2431                         DEBUGOUT("Host interface command failed\n");
2432                         goto out;
2433                 }
2434
2435                 for (i = 0; i < words_to_read; i++) {
2436                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2437                                   2 * i;
2438                         u32 value = IXGBE_READ_REG(hw, reg);
2439
2440                         data[current_word] = (u16)(value & 0xffff);
2441                         current_word++;
2442                         i++;
2443                         if (i < words_to_read) {
2444                                 value >>= 16;
2445                                 data[current_word] = (u16)(value & 0xffff);
2446                                 current_word++;
2447                         }
2448                 }
2449                 words -= words_to_read;
2450         }
2451
2452 out:
2453         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2454         return status;
2455 }
2456
2457 /**
2458  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2459  *  @hw: pointer to hardware structure
2460  *  @offset: offset of  word in the EEPROM to write
2461  *  @data: word write to the EEPROM
2462  *
2463  *  Write a 16 bit word to the EEPROM using the hostif.
2464  **/
2465 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
2466                                     u16 data)
2467 {
2468         s32 status;
2469         struct ixgbe_hic_write_shadow_ram buffer;
2470
2471         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
2472
2473         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
2474         buffer.hdr.req.buf_lenh = 0;
2475         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
2476         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2477
2478          /* one word */
2479         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2480         buffer.data = data;
2481         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2482
2483         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2484                                               sizeof(buffer),
2485                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2486
2487         return status;
2488 }
2489
2490 /**
2491  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
2492  *  @hw: pointer to hardware structure
2493  *  @offset: offset of  word in the EEPROM to write
2494  *  @data: word write to the EEPROM
2495  *
2496  *  Write a 16 bit word to the EEPROM using the hostif.
2497  **/
2498 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
2499                                u16 data)
2500 {
2501         s32 status = IXGBE_SUCCESS;
2502
2503         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
2504
2505         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
2506             IXGBE_SUCCESS) {
2507                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
2508                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2509         } else {
2510                 DEBUGOUT("write ee hostif failed to get semaphore");
2511                 status = IXGBE_ERR_SWFW_SYNC;
2512         }
2513
2514         return status;
2515 }
2516
2517 /**
2518  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
2519  *  @hw: pointer to hardware structure
2520  *  @offset: offset of  word in the EEPROM to write
2521  *  @words: number of words
2522  *  @data: word(s) write to the EEPROM
2523  *
2524  *  Write a 16 bit word(s) to the EEPROM using the hostif.
2525  **/
2526 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2527                                       u16 offset, u16 words, u16 *data)
2528 {
2529         s32 status = IXGBE_SUCCESS;
2530         u32 i = 0;
2531
2532         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
2533
2534         /* Take semaphore for the entire operation. */
2535         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2536         if (status != IXGBE_SUCCESS) {
2537                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
2538                 goto out;
2539         }
2540
2541         for (i = 0; i < words; i++) {
2542                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
2543                                                          data[i]);
2544
2545                 if (status != IXGBE_SUCCESS) {
2546                         DEBUGOUT("Eeprom buffered write failed\n");
2547                         break;
2548                 }
2549         }
2550
2551         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2552 out:
2553
2554         return status;
2555 }
2556
2557 /**
2558  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
2559  * @hw: pointer to hardware structure
2560  * @ptr: pointer offset in eeprom
2561  * @size: size of section pointed by ptr, if 0 first word will be used as size
2562  * @csum: address of checksum to update
2563  *
2564  * Returns error status for any failure
2565  */
2566 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
2567                                    u16 size, u16 *csum, u16 *buffer,
2568                                    u32 buffer_size)
2569 {
2570         u16 buf[256];
2571         s32 status;
2572         u16 length, bufsz, i, start;
2573         u16 *local_buffer;
2574
2575         bufsz = sizeof(buf) / sizeof(buf[0]);
2576
2577         /* Read a chunk at the pointer location */
2578         if (!buffer) {
2579                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
2580                 if (status) {
2581                         DEBUGOUT("Failed to read EEPROM image\n");
2582                         return status;
2583                 }
2584                 local_buffer = buf;
2585         } else {
2586                 if (buffer_size < ptr)
2587                         return  IXGBE_ERR_PARAM;
2588                 local_buffer = &buffer[ptr];
2589         }
2590
2591         if (size) {
2592                 start = 0;
2593                 length = size;
2594         } else {
2595                 start = 1;
2596                 length = local_buffer[0];
2597
2598                 /* Skip pointer section if length is invalid. */
2599                 if (length == 0xFFFF || length == 0 ||
2600                     (ptr + length) >= hw->eeprom.word_size)
2601                         return IXGBE_SUCCESS;
2602         }
2603
2604         if (buffer && ((u32)start + (u32)length > buffer_size))
2605                 return IXGBE_ERR_PARAM;
2606
2607         for (i = start; length; i++, length--) {
2608                 if (i == bufsz && !buffer) {
2609                         ptr += bufsz;
2610                         i = 0;
2611                         if (length < bufsz)
2612                                 bufsz = length;
2613
2614                         /* Read a chunk at the pointer location */
2615                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
2616                                                                   bufsz, buf);
2617                         if (status) {
2618                                 DEBUGOUT("Failed to read EEPROM image\n");
2619                                 return status;
2620                         }
2621                 }
2622                 *csum += local_buffer[i];
2623         }
2624         return IXGBE_SUCCESS;
2625 }
2626
2627 /**
2628  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
2629  *  @hw: pointer to hardware structure
2630  *  @buffer: pointer to buffer containing calculated checksum
2631  *  @buffer_size: size of buffer
2632  *
2633  *  Returns a negative error code on error, or the 16-bit checksum
2634  **/
2635 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
2636 {
2637         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
2638         u16 *local_buffer;
2639         s32 status;
2640         u16 checksum = 0;
2641         u16 pointer, i, size;
2642
2643         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
2644
2645         hw->eeprom.ops.init_params(hw);
2646
2647         if (!buffer) {
2648                 /* Read pointer area */
2649                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
2650                                                      IXGBE_EEPROM_LAST_WORD + 1,
2651                                                      eeprom_ptrs);
2652                 if (status) {
2653                         DEBUGOUT("Failed to read EEPROM image\n");
2654                         return status;
2655                 }
2656                 local_buffer = eeprom_ptrs;
2657         } else {
2658                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
2659                         return IXGBE_ERR_PARAM;
2660                 local_buffer = buffer;
2661         }
2662
2663         /*
2664          * For X550 hardware include 0x0-0x41 in the checksum, skip the
2665          * checksum word itself
2666          */
2667         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
2668                 if (i != IXGBE_EEPROM_CHECKSUM)
2669                         checksum += local_buffer[i];
2670
2671         /*
2672          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
2673          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
2674          */
2675         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
2676                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
2677                         continue;
2678
2679                 pointer = local_buffer[i];
2680
2681                 /* Skip pointer section if the pointer is invalid. */
2682                 if (pointer == 0xFFFF || pointer == 0 ||
2683                     pointer >= hw->eeprom.word_size)
2684                         continue;
2685
2686                 switch (i) {
2687                 case IXGBE_PCIE_GENERAL_PTR:
2688                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
2689                         break;
2690                 case IXGBE_PCIE_CONFIG0_PTR:
2691                 case IXGBE_PCIE_CONFIG1_PTR:
2692                         size = IXGBE_PCIE_CONFIG_SIZE;
2693                         break;
2694                 default:
2695                         size = 0;
2696                         break;
2697                 }
2698
2699                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
2700                                                 buffer, buffer_size);
2701                 if (status)
2702                         return status;
2703         }
2704
2705         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2706
2707         return (s32)checksum;
2708 }
2709
2710 /**
2711  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
2712  *  @hw: pointer to hardware structure
2713  *
2714  *  Returns a negative error code on error, or the 16-bit checksum
2715  **/
2716 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
2717 {
2718         return ixgbe_calc_checksum_X550(hw, NULL, 0);
2719 }
2720
2721 /**
2722  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
2723  *  @hw: pointer to hardware structure
2724  *  @checksum_val: calculated checksum
2725  *
2726  *  Performs checksum calculation and validates the EEPROM checksum.  If the
2727  *  caller does not need checksum_val, the value can be NULL.
2728  **/
2729 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
2730 {
2731         s32 status;
2732         u16 checksum;
2733         u16 read_checksum = 0;
2734
2735         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
2736
2737         /* Read the first word from the EEPROM. If this times out or fails, do
2738          * not continue or we could be in for a very long wait while every
2739          * EEPROM read fails
2740          */
2741         status = hw->eeprom.ops.read(hw, 0, &checksum);
2742         if (status) {
2743                 DEBUGOUT("EEPROM read failed\n");
2744                 return status;
2745         }
2746
2747         status = hw->eeprom.ops.calc_checksum(hw);
2748         if (status < 0)
2749                 return status;
2750
2751         checksum = (u16)(status & 0xffff);
2752
2753         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2754                                            &read_checksum);
2755         if (status)
2756                 return status;
2757
2758         /* Verify read checksum from EEPROM is the same as
2759          * calculated checksum
2760          */
2761         if (read_checksum != checksum) {
2762                 status = IXGBE_ERR_EEPROM_CHECKSUM;
2763                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
2764                              "Invalid EEPROM checksum");
2765         }
2766
2767         /* If the user cares, return the calculated checksum */
2768         if (checksum_val)
2769                 *checksum_val = checksum;
2770
2771         return status;
2772 }
2773
2774 /**
2775  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
2776  * @hw: pointer to hardware structure
2777  *
2778  * After writing EEPROM to shadow RAM using EEWR register, software calculates
2779  * checksum and updates the EEPROM and instructs the hardware to update
2780  * the flash.
2781  **/
2782 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
2783 {
2784         s32 status;
2785         u16 checksum = 0;
2786
2787         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
2788
2789         /* Read the first word from the EEPROM. If this times out or fails, do
2790          * not continue or we could be in for a very long wait while every
2791          * EEPROM read fails
2792          */
2793         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
2794         if (status) {
2795                 DEBUGOUT("EEPROM read failed\n");
2796                 return status;
2797         }
2798
2799         status = ixgbe_calc_eeprom_checksum_X550(hw);
2800         if (status < 0)
2801                 return status;
2802
2803         checksum = (u16)(status & 0xffff);
2804
2805         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
2806                                             checksum);
2807         if (status)
2808                 return status;
2809
2810         status = ixgbe_update_flash_X550(hw);
2811
2812         return status;
2813 }
2814
2815 /**
2816  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
2817  *  @hw: pointer to hardware structure
2818  *
2819  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
2820  **/
2821 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
2822 {
2823         s32 status = IXGBE_SUCCESS;
2824         union ixgbe_hic_hdr2 buffer;
2825
2826         DEBUGFUNC("ixgbe_update_flash_X550");
2827
2828         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
2829         buffer.req.buf_lenh = 0;
2830         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
2831         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
2832
2833         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
2834                                               sizeof(buffer),
2835                                               IXGBE_HI_COMMAND_TIMEOUT, false);
2836
2837         return status;
2838 }
2839
2840 /**
2841  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
2842  *  @hw: pointer to hardware structure
2843  *
2844  *  Determines physical layer capabilities of the current configuration.
2845  **/
2846 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
2847 {
2848         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2849         u16 ext_ability = 0;
2850
2851         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
2852
2853         hw->phy.ops.identify(hw);
2854
2855         switch (hw->phy.type) {
2856         case ixgbe_phy_x550em_kr:
2857                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
2858                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2859                 break;
2860         case ixgbe_phy_x550em_kx4:
2861                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2862                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2863                 break;
2864         case ixgbe_phy_x550em_ext_t:
2865                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2866                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2867                                      &ext_ability);
2868                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2869                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2870                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2871                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2872                 break;
2873         default:
2874                 break;
2875         }
2876
2877         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
2878                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2879
2880         return physical_layer;
2881 }
2882
2883 /**
2884  * ixgbe_get_bus_info_x550em - Set PCI bus info
2885  * @hw: pointer to hardware structure
2886  *
2887  * Sets bus link width and speed to unknown because X550em is
2888  * not a PCI device.
2889  **/
2890 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
2891 {
2892
2893         DEBUGFUNC("ixgbe_get_bus_info_x550em");
2894
2895         hw->bus.width = ixgbe_bus_width_unknown;
2896         hw->bus.speed = ixgbe_bus_speed_unknown;
2897
2898         hw->mac.ops.set_lan_id(hw);
2899
2900         return IXGBE_SUCCESS;
2901 }
2902
2903 /**
2904  * ixgbe_disable_rx_x550 - Disable RX unit
2905  *
2906  * Enables the Rx DMA unit for x550
2907  **/
2908 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
2909 {
2910         u32 rxctrl, pfdtxgswc;
2911         s32 status;
2912         struct ixgbe_hic_disable_rxen fw_cmd;
2913
2914         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
2915
2916         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2917         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2918                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
2919                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
2920                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
2921                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
2922                         hw->mac.set_lben = true;
2923                 } else {
2924                         hw->mac.set_lben = false;
2925                 }
2926
2927                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
2928                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
2929                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
2930                 fw_cmd.port_number = (u8)hw->bus.lan_id;
2931
2932                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2933                                         sizeof(struct ixgbe_hic_disable_rxen),
2934                                         IXGBE_HI_COMMAND_TIMEOUT, true);
2935
2936                 /* If we fail - disable RX using register write */
2937                 if (status) {
2938                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2939                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
2940                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
2941                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
2942                         }
2943                 }
2944         }
2945 }
2946
2947 /**
2948  * ixgbe_enter_lplu_x550em - Transition to low power states
2949  *  @hw: pointer to hardware structure
2950  *
2951  * Configures Low Power Link Up on transition to low power states
2952  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
2953  * X557 PHY immediately prior to entering LPLU.
2954  **/
2955 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2956 {
2957         u16 an_10g_cntl_reg, autoneg_reg, speed;
2958         s32 status;
2959         ixgbe_link_speed lcd_speed;
2960         u32 save_autoneg;
2961         bool link_up;
2962
2963         /* SW LPLU not required on later HW revisions. */
2964         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2965             (IXGBE_FUSES0_REV_MASK &
2966              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2967                 return IXGBE_SUCCESS;
2968
2969         /* If blocked by MNG FW, then don't restart AN */
2970         if (ixgbe_check_reset_blocked(hw))
2971                 return IXGBE_SUCCESS;
2972
2973         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2974         if (status != IXGBE_SUCCESS)
2975                 return status;
2976
2977         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
2978
2979         if (status != IXGBE_SUCCESS)
2980                 return status;
2981
2982         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
2983          * disabled, then force link down by entering low power mode.
2984          */
2985         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2986             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2987                 return ixgbe_set_copper_phy_power(hw, FALSE);
2988
2989         /* Determine LCD */
2990         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2991
2992         if (status != IXGBE_SUCCESS)
2993                 return status;
2994
2995         /* If no valid LCD link speed, then force link down and exit. */
2996         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2997                 return ixgbe_set_copper_phy_power(hw, FALSE);
2998
2999         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3000                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3001                                       &speed);
3002
3003         if (status != IXGBE_SUCCESS)
3004                 return status;
3005
3006         /* If no link now, speed is invalid so take link down */
3007         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3008         if (status != IXGBE_SUCCESS)
3009                 return ixgbe_set_copper_phy_power(hw, false);
3010
3011         /* clear everything but the speed bits */
3012         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3013
3014         /* If current speed is already LCD, then exit. */
3015         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3016              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3017             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3018              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3019                 return status;
3020
3021         /* Clear AN completed indication */
3022         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3023                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3024                                       &autoneg_reg);
3025
3026         if (status != IXGBE_SUCCESS)
3027                 return status;
3028
3029         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3030                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3031                              &an_10g_cntl_reg);
3032
3033         if (status != IXGBE_SUCCESS)
3034                 return status;
3035
3036         status = hw->phy.ops.read_reg(hw,
3037                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3038                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3039                              &autoneg_reg);
3040
3041         if (status != IXGBE_SUCCESS)
3042                 return status;
3043
3044         save_autoneg = hw->phy.autoneg_advertised;
3045
3046         /* Setup link at least common link speed */
3047         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3048
3049         /* restore autoneg from before setting lplu speed */
3050         hw->phy.autoneg_advertised = save_autoneg;
3051
3052         return status;
3053 }
3054
3055 /**
3056  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3057  *  @hw: pointer to hardware structure
3058  *  @lcd_speed: pointer to lowest common link speed
3059  *
3060  * Determine lowest common link speed with link partner.
3061  **/
3062 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3063 {
3064         u16 an_lp_status;
3065         s32 status;
3066         u16 word = hw->eeprom.ctrl_word_3;
3067
3068         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3069
3070         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3071                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3072                                       &an_lp_status);
3073
3074         if (status != IXGBE_SUCCESS)
3075                 return status;
3076
3077         /* If link partner advertised 1G, return 1G */
3078         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3079                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3080                 return status;
3081         }
3082
3083         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3084         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3085             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3086                 return status;
3087
3088         /* Link partner not capable of lower speeds, return 10G */
3089         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3090         return status;
3091 }
3092
3093 /**
3094  *  ixgbe_setup_fc_X550em - Set up flow control
3095  *  @hw: pointer to hardware structure
3096  *
3097  *  Called at init time to set up flow control.
3098  **/
3099 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3100 {
3101         s32 ret_val = IXGBE_SUCCESS;
3102         u32 pause, asm_dir, reg_val;
3103
3104         DEBUGFUNC("ixgbe_setup_fc_X550em");
3105
3106         /* Validate the requested mode */
3107         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3108                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3109                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3110                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3111                 goto out;
3112         }
3113
3114         /* 10gig parts do not have a word in the EEPROM to determine the
3115          * default flow control setting, so we explicitly set it to full.
3116          */
3117         if (hw->fc.requested_mode == ixgbe_fc_default)
3118                 hw->fc.requested_mode = ixgbe_fc_full;
3119
3120         /* Determine PAUSE and ASM_DIR bits. */
3121         switch (hw->fc.requested_mode) {
3122         case ixgbe_fc_none:
3123                 pause = 0;
3124                 asm_dir = 0;
3125                 break;
3126         case ixgbe_fc_tx_pause:
3127                 pause = 0;
3128                 asm_dir = 1;
3129                 break;
3130         case ixgbe_fc_rx_pause:
3131                 /* Rx Flow control is enabled and Tx Flow control is
3132                  * disabled by software override. Since there really
3133                  * isn't a way to advertise that we are capable of RX
3134                  * Pause ONLY, we will advertise that we support both
3135                  * symmetric and asymmetric Rx PAUSE, as such we fall
3136                  * through to the fc_full statement.  Later, we will
3137                  * disable the adapter's ability to send PAUSE frames.
3138                  */
3139         case ixgbe_fc_full:
3140                 pause = 1;
3141                 asm_dir = 1;
3142                 break;
3143         default:
3144                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3145                         "Flow control param set incorrectly\n");
3146                 ret_val = IXGBE_ERR_CONFIG;
3147                 goto out;
3148         }
3149
3150         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {
3151                 ret_val = ixgbe_read_iosf_sb_reg_x550(hw,
3152                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3153                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3154                 if (ret_val != IXGBE_SUCCESS)
3155                         goto out;
3156                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3157                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3158                 if (pause)
3159                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3160                 if (asm_dir)
3161                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3162                 ret_val = ixgbe_write_iosf_sb_reg_x550(hw,
3163                         IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3164                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3165
3166                 /* This device does not fully support AN. */
3167                 hw->fc.disable_fc_autoneg = true;
3168         }
3169
3170 out:
3171         return ret_val;
3172 }
3173
3174 /**
3175  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3176  * @hw: pointer to hardware structure
3177  * @state: set mux if 1, clear if 0
3178  */
3179 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3180 {
3181         u32 esdp;
3182
3183         if (!hw->bus.lan_id)
3184                 return;
3185         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3186         if (state)
3187                 esdp |= IXGBE_ESDP_SDP1;
3188         else
3189                 esdp &= ~IXGBE_ESDP_SDP1;
3190         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3191         IXGBE_WRITE_FLUSH(hw);
3192 }
3193
3194 /**
3195  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3196  *  @hw: pointer to hardware structure
3197  *  @mask: Mask to specify which semaphore to acquire
3198  *
3199  *  Acquires the SWFW semaphore and sets the I2C MUX
3200  **/
3201 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3202 {
3203         s32 status;
3204
3205         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3206
3207         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3208         if (status)
3209                 return status;
3210
3211         if (mask & IXGBE_GSSR_I2C_MASK)
3212                 ixgbe_set_mux(hw, 1);
3213
3214         return IXGBE_SUCCESS;
3215 }
3216
3217 /**
3218  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3219  *  @hw: pointer to hardware structure
3220  *  @mask: Mask to specify which semaphore to release
3221  *
3222  *  Releases the SWFW semaphore and sets the I2C MUX
3223  **/
3224 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3225 {
3226         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3227
3228         if (mask & IXGBE_GSSR_I2C_MASK)
3229                 ixgbe_set_mux(hw, 0);
3230
3231         ixgbe_release_swfw_sync_X540(hw, mask);
3232 }
3233
3234 /**
3235  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3236  *  @hw: pointer to hardware structure
3237  *  @mask: Mask to specify which semaphore to acquire
3238  *
3239  *  Acquires the SWFW semaphore and get the shared phy token as needed
3240  */
3241 static s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3242 {
3243         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3244         int retries = FW_PHY_TOKEN_RETRIES;
3245         s32 status = IXGBE_SUCCESS;
3246
3247         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3248
3249         while (--retries) {
3250                 if (hmask)
3251                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3252                 if (status)
3253                         break;
3254                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3255                         break;
3256                 status = ixgbe_get_phy_token(hw);
3257                 if (status != IXGBE_ERR_TOKEN_RETRY)
3258                         break;
3259                 if (hmask)
3260                         ixgbe_release_swfw_sync_X540(hw, hmask);
3261                 msec_delay(FW_PHY_TOKEN_DELAY);
3262         }
3263
3264         return status;
3265 }
3266
3267 /**
3268  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
3269  *  @hw: pointer to hardware structure
3270  *  @mask: Mask to specify which semaphore to release
3271  *
3272  *  Releases the SWFW semaphore and puts the shared phy token as needed
3273  */
3274 static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3275 {
3276         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3277
3278         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
3279
3280         if (mask & IXGBE_GSSR_TOKEN_SM)
3281                 ixgbe_put_phy_token(hw);
3282
3283         if (hmask)
3284                 ixgbe_release_swfw_sync_X540(hw, hmask);
3285 }
3286
3287 /**
3288  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
3289  * @hw: pointer to hardware structure
3290  *
3291  * Handle external Base T PHY interrupt. If high temperature
3292  * failure alarm then return error, else if link status change
3293  * then setup internal/external PHY link
3294  *
3295  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
3296  * failure alarm, else return PHY access status.
3297  */
3298 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
3299 {
3300         bool lsc;
3301         u32 status;
3302
3303         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
3304
3305         if (status != IXGBE_SUCCESS)
3306                 return status;
3307
3308         if (lsc)
3309                 return ixgbe_setup_internal_phy(hw);
3310
3311         return IXGBE_SUCCESS;
3312 }
3313
3314 /**
3315  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
3316  * @hw: pointer to hardware structure
3317  * @speed: new link speed
3318  * @autoneg_wait_to_complete: true when waiting for completion is needed
3319  *
3320  * Setup internal/external PHY link speed based on link speed, then set
3321  * external PHY auto advertised link speed.
3322  *
3323  * Returns error status for any failure
3324  **/
3325 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
3326                                   ixgbe_link_speed speed,
3327                                   bool autoneg_wait_to_complete)
3328 {
3329         s32 status;
3330         ixgbe_link_speed force_speed;
3331
3332         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
3333
3334         /* Setup internal/external PHY link speed to iXFI (10G), unless
3335          * only 1G is auto advertised then setup KX link.
3336          */
3337         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
3338                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
3339         else
3340                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
3341
3342         /* If internal link mode is XFI, then setup XFI internal link. */
3343         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
3344                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
3345
3346                 if (status != IXGBE_SUCCESS)
3347                         return status;
3348         }
3349
3350         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
3351 }
3352
3353 /**
3354  * ixgbe_check_link_t_X550em - Determine link and speed status
3355  * @hw: pointer to hardware structure
3356  * @speed: pointer to link speed
3357  * @link_up: true when link is up
3358  * @link_up_wait_to_complete: bool used to wait for link up or not
3359  *
3360  * Check that both the MAC and X557 external PHY have link.
3361  **/
3362 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3363                               bool *link_up, bool link_up_wait_to_complete)
3364 {
3365         u32 status;
3366         u16 autoneg_status;
3367
3368         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
3369                 return IXGBE_ERR_CONFIG;
3370
3371         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
3372                                               link_up_wait_to_complete);
3373
3374         /* If check link fails or MAC link is not up, then return */
3375         if (status != IXGBE_SUCCESS || !(*link_up))
3376                 return status;
3377
3378         /* MAC link is up, so check external PHY link.
3379          * Read this twice back to back to indicate current status.
3380          */
3381         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3382                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3383                                       &autoneg_status);
3384
3385         if (status != IXGBE_SUCCESS)
3386                 return status;
3387
3388         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
3389                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3390                                       &autoneg_status);
3391
3392         if (status != IXGBE_SUCCESS)
3393                 return status;
3394
3395         /* If external PHY link is not up, then indicate link not up */
3396         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
3397                 *link_up = false;
3398
3399         return IXGBE_SUCCESS;
3400 }
3401
3402 /**
3403  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
3404  *  @hw: pointer to hardware structure
3405  **/
3406 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
3407 {
3408         s32 status;
3409
3410         status = ixgbe_reset_phy_generic(hw);
3411
3412         if (status != IXGBE_SUCCESS)
3413                 return status;
3414
3415         /* Configure Link Status Alarm and Temperature Threshold interrupts */
3416         return ixgbe_enable_lasi_ext_t_x550em(hw);
3417 }
3418
3419 /**
3420  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
3421  *  @hw: pointer to hardware structure
3422  *  @led_idx: led number to turn on
3423  **/
3424 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3425 {
3426         u16 phy_data;
3427
3428         DEBUGFUNC("ixgbe_led_on_t_X550em");
3429
3430         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3431                 return IXGBE_ERR_PARAM;
3432
3433         /* To turn on the LED, set mode to ON. */
3434         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3435                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3436         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
3437         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3438                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3439
3440         return IXGBE_SUCCESS;
3441 }
3442
3443 /**
3444  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
3445  *  @hw: pointer to hardware structure
3446  *  @led_idx: led number to turn off
3447  **/
3448 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
3449 {
3450         u16 phy_data;
3451
3452         DEBUGFUNC("ixgbe_led_off_t_X550em");
3453
3454         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
3455                 return IXGBE_ERR_PARAM;
3456
3457         /* To turn on the LED, set mode to ON. */
3458         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3459                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
3460         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
3461         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
3462                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
3463
3464         return IXGBE_SUCCESS;
3465 }
3466