drivers/net/ixgbe/base/ixgbe_x550.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_x550.h"
  35 #include "ixgbe_x540.h"
  36 #include "ixgbe_type.h"
  37 #include "ixgbe_api.h"
  38 #include "ixgbe_common.h"
  39 #include "ixgbe_phy.h"
  40
  41 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);
  42 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  43 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *, u32 mask);
  44
  45 /**
  46  *  ixgbe_init_ops_X550 - Inits func ptrs and MAC type
  47  *  @hw: pointer to hardware structure
  48  *
  49  *  Initialize the function pointers and assign the MAC type for X550.
  50  *  Does not touch the hardware.
  51  **/
  52 s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)
  53 {
  54         struct ixgbe_mac_info *mac = &hw->mac;
  55         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  56         s32 ret_val;
  57
  58         DEBUGFUNC("ixgbe_init_ops_X550");
  59
  60         ret_val = ixgbe_init_ops_X540(hw);
  61         mac->ops.dmac_config = ixgbe_dmac_config_X550;
  62         mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;
  63         mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;
  64         mac->ops.setup_eee = ixgbe_setup_eee_X550;
  65         mac->ops.set_source_address_pruning =
  66                         ixgbe_set_source_address_pruning_X550;
  67         mac->ops.set_ethertype_anti_spoofing =
  68                         ixgbe_set_ethertype_anti_spoofing_X550;
  69
  70         mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;
  71         eeprom->ops.init_params = ixgbe_init_eeprom_params_X550;
  72         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
  73         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
  74         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
  75         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
  76         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
  77         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
  78         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
  79
  80         mac->ops.disable_mdd = ixgbe_disable_mdd_X550;
  81         mac->ops.enable_mdd = ixgbe_enable_mdd_X550;
  82         mac->ops.mdd_event = ixgbe_mdd_event_X550;
  83         mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;
  84         mac->ops.disable_rx = ixgbe_disable_rx_x550;
  85         switch (hw->device_id) {
  86         case IXGBE_DEV_ID_X550EM_X_10G_T:
  87         case IXGBE_DEV_ID_X550EM_A_10G_T:
  88                 hw->mac.ops.led_on = ixgbe_led_on_t_X550em;
  89                 hw->mac.ops.led_off = ixgbe_led_off_t_X550em;
  90                 break;
  91         default:
  92                 break;
  93         }
  94         return ret_val;
  95 }
  96
  97 /**
  98  * ixgbe_read_cs4227 - Read CS4227 register
  99  * @hw: pointer to hardware structure
 100  * @reg: register number to write
 101  * @value: pointer to receive value read
 102  *
 103  * Returns status code
 104  **/
 105 STATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
 106 {
 107         return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
 108 }
 109
 110 /**
 111  * ixgbe_write_cs4227 - Write CS4227 register
 112  * @hw: pointer to hardware structure
 113  * @reg: register number to write
 114  * @value: value to write to register
 115  *
 116  * Returns status code
 117  **/
 118 STATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
 119 {
 120         return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
 121 }
 122
 123 /**
 124  * ixgbe_read_pe - Read register from port expander
 125  * @hw: pointer to hardware structure
 126  * @reg: register number to read
 127  * @value: pointer to receive read value
 128  *
 129  * Returns status code
 130  **/
 131 STATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
 132 {
 133         s32 status;
 134
 135         status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 136         if (status != IXGBE_SUCCESS)
 137                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 138                               "port expander access failed with %d\n", status);
 139         return status;
 140 }
 141
 142 /**
 143  * ixgbe_write_pe - Write register to port expander
 144  * @hw: pointer to hardware structure
 145  * @reg: register number to write
 146  * @value: value to write
 147  *
 148  * Returns status code
 149  **/
 150 STATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 151 {
 152         s32 status;
 153
 154         status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);
 155         if (status != IXGBE_SUCCESS)
 156                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 157                               "port expander access failed with %d\n", status);
 158         return status;
 159 }
 160
 161 /**
 162  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 163  * @hw: pointer to hardware structure
 164  *
 165  * This function assumes that the caller has acquired the proper semaphore.
 166  * Returns error code
 167  **/
 168 STATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 169 {
 170         s32 status;
 171         u32 retry;
 172         u16 value;
 173         u8 reg;
 174
 175         /* Trigger hard reset. */
 176         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 177         if (status != IXGBE_SUCCESS)
 178                 return status;
 179         reg |= IXGBE_PE_BIT1;
 180         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 181         if (status != IXGBE_SUCCESS)
 182                 return status;
 183
 184         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 185         if (status != IXGBE_SUCCESS)
 186                 return status;
 187         reg &= ~IXGBE_PE_BIT1;
 188         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 189         if (status != IXGBE_SUCCESS)
 190                 return status;
 191
 192         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 193         if (status != IXGBE_SUCCESS)
 194                 return status;
 195         reg &= ~IXGBE_PE_BIT1;
 196         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 197         if (status != IXGBE_SUCCESS)
 198                 return status;
 199
 200         usec_delay(IXGBE_CS4227_RESET_HOLD);
 201
 202         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 203         if (status != IXGBE_SUCCESS)
 204                 return status;
 205         reg |= IXGBE_PE_BIT1;
 206         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 207         if (status != IXGBE_SUCCESS)
 208                 return status;
 209
 210         /* Wait for the reset to complete. */
 211         msec_delay(IXGBE_CS4227_RESET_DELAY);
 212         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 213                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 214                                            &value);
 215                 if (status == IXGBE_SUCCESS &&
 216                     value == IXGBE_CS4227_EEPROM_LOAD_OK)
 217                         break;
 218                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 219         }
 220         if (retry == IXGBE_CS4227_RETRIES) {
 221                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 222                         "CS4227 reset did not complete.");
 223                 return IXGBE_ERR_PHY;
 224         }
 225
 226         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 227         if (status != IXGBE_SUCCESS ||
 228             !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 229                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
 230                         "CS4227 EEPROM did not load successfully.");
 231                 return IXGBE_ERR_PHY;
 232         }
 233
 234         return IXGBE_SUCCESS;
 235 }
 236
 237 /**
 238  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 239  * @hw: pointer to hardware structure
 240  **/
 241 STATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 242 {
 243         s32 status = IXGBE_SUCCESS;
 244         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 245         u16 value = 0;
 246         u8 retry;
 247
 248         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 249                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 250                 if (status != IXGBE_SUCCESS) {
 251                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 252                                 "semaphore failed with %d", status);
 253                         msec_delay(IXGBE_CS4227_CHECK_DELAY);
 254                         continue;
 255                 }
 256
 257                 /* Get status of reset flow. */
 258                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 259
 260                 if (status == IXGBE_SUCCESS &&
 261                     value == IXGBE_CS4227_RESET_COMPLETE)
 262                         goto out;
 263
 264                 if (status != IXGBE_SUCCESS ||
 265                     value != IXGBE_CS4227_RESET_PENDING)
 266                         break;
 267
 268                 /* Reset is pending. Wait and check again. */
 269                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 270                 msec_delay(IXGBE_CS4227_CHECK_DELAY);
 271         }
 272
 273         /* If still pending, assume other instance failed. */
 274         if (retry == IXGBE_CS4227_RETRIES) {
 275                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 276                 if (status != IXGBE_SUCCESS) {
 277                         ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 278                                       "semaphore failed with %d", status);
 279                         return;
 280                 }
 281         }
 282
 283         /* Reset the CS4227. */
 284         status = ixgbe_reset_cs4227(hw);
 285         if (status != IXGBE_SUCCESS) {
 286                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 287                         "CS4227 reset failed: %d", status);
 288                 goto out;
 289         }
 290
 291         /* Reset takes so long, temporarily release semaphore in case the
 292          * other driver instance is waiting for the reset indication.
 293          */
 294         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 295                            IXGBE_CS4227_RESET_PENDING);
 296         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 297         msec_delay(10);
 298         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 299         if (status != IXGBE_SUCCESS) {
 300                 ERROR_REPORT2(IXGBE_ERROR_CAUTION,
 301                         "semaphore failed with %d", status);
 302                 return;
 303         }
 304
 305         /* Record completion for next time. */
 306         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 307                 IXGBE_CS4227_RESET_COMPLETE);
 308
 309 out:
 310         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 311         msec_delay(hw->eeprom.semaphore_delay);
 312 }
 313
 314 /**
 315  * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
 316  * @hw: pointer to hardware structure
 317  **/
 318 STATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
 319 {
 320         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 321
 322         if (hw->bus.lan_id) {
 323                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
 324                 esdp |= IXGBE_ESDP_SDP1_DIR;
 325         }
 326         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
 327         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 328         IXGBE_WRITE_FLUSH(hw);
 329 }
 330
 331 /**
 332  * ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock
 333  * @hw: pointer to hardware structure
 334  * @reg_addr: 32 bit address of PHY register to read
 335  * @dev_type: always unused
 336  * @phy_data: Pointer to read data from PHY register
 337  */
 338 STATIC s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 339                                      u32 dev_type, u16 *phy_data)
 340 {
 341         u32 i, data, command;
 342         UNREFERENCED_1PARAMETER(dev_type);
 343
 344         /* Setup and write the read command */
 345         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 346                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 347                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 348                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ |
 349                 IXGBE_MSCA_MDI_COMMAND;
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 352
 353         /* Check every 10 usec to see if the access completed.
 354          * The MDI Command bit will clear when the operation is
 355          * complete
 356          */
 357         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 358                 usec_delay(10);
 359
 360                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 361                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 362                         break;
 363         }
 364
 365         if (command & IXGBE_MSCA_MDI_COMMAND) {
 366                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 367                               "PHY read command did not complete.\n");
 368                 return IXGBE_ERR_PHY;
 369         }
 370
 371         /* Read operation is complete.  Get the data from MSRWD */
 372         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 373         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 374         *phy_data = (u16)data;
 375
 376         return IXGBE_SUCCESS;
 377 }
 378
 379 /**
 380  * ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock
 381  * @hw: pointer to hardware structure
 382  * @reg_addr: 32 bit PHY register to write
 383  * @dev_type: always unused
 384  * @phy_data: Data to write to the PHY register
 385  */
 386 STATIC s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr,
 387                                       u32 dev_type, u16 phy_data)
 388 {
 389         u32 i, command;
 390         UNREFERENCED_1PARAMETER(dev_type);
 391
 392         /* Put the data in the MDI single read and write data register*/
 393         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 394
 395         /* Setup and write the write command */
 396         command = (reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 397                 (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 398                 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 399                 IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
 400                 IXGBE_MSCA_MDI_COMMAND;
 401
 402         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 403
 404         /* Check every 10 usec to see if the access completed.
 405          * The MDI Command bit will clear when the operation is
 406          * complete
 407          */
 408         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 409                 usec_delay(10);
 410
 411                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 412                 if (!(command & IXGBE_MSCA_MDI_COMMAND))
 413                         break;
 414         }
 415
 416         if (command & IXGBE_MSCA_MDI_COMMAND) {
 417                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 418                               "PHY write cmd didn't complete\n");
 419                 return IXGBE_ERR_PHY;
 420         }
 421
 422         return IXGBE_SUCCESS;
 423 }
 424
 425 /**
 426  * ixgbe_identify_phy_1g - Get 1g PHY type based on device id
 427  * @hw: pointer to hardware structure
 428  *
 429  * Returns error code
 430  */
 431 STATIC s32 ixgbe_identify_phy_1g(struct ixgbe_hw *hw)
 432 {
 433         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 434         u16 phy_id_high;
 435         u16 phy_id_low;
 436         s32 rc;
 437
 438         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 439         if (rc)
 440                 return rc;
 441
 442         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_HIGH, 0,
 443                                        &phy_id_high);
 444         if (rc)
 445                 goto rel_out;
 446
 447         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_MDIO_PHY_ID_LOW, 0,
 448                                        &phy_id_low);
 449         if (rc)
 450                 goto rel_out;
 451
 452         hw->phy.id = (u32)phy_id_high << 16;
 453         hw->phy.id |= phy_id_low & IXGBE_PHY_REVISION_MASK;
 454         hw->phy.revision = (u32)phy_id_low & ~IXGBE_PHY_REVISION_MASK;
 455
 456 rel_out:
 457         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 458
 459         return rc;
 460 }
 461
 462 /**
 463  * ixgbe_identify_phy_x550em - Get PHY type based on device id
 464  * @hw: pointer to hardware structure
 465  *
 466  * Returns error code
 467  */
 468 STATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 469 {
 470         switch (hw->device_id) {
 471         case IXGBE_DEV_ID_X550EM_A_SFP:
 472                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 473                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 474                 if (hw->bus.lan_id)
 475                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 476                 else
 477                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 478                 return ixgbe_identify_module_generic(hw);
 479         case IXGBE_DEV_ID_X550EM_X_SFP:
 480                 /* set up for CS4227 usage */
 481                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 482                 ixgbe_setup_mux_ctl(hw);
 483                 ixgbe_check_cs4227(hw);
 484                 /* Fallthrough */
 485
 486         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 487                 return ixgbe_identify_module_generic(hw);
 488                 break;
 489         case IXGBE_DEV_ID_X550EM_X_KX4:
 490                 hw->phy.type = ixgbe_phy_x550em_kx4;
 491                 break;
 492         case IXGBE_DEV_ID_X550EM_X_KR:
 493         case IXGBE_DEV_ID_X550EM_A_KR:
 494         case IXGBE_DEV_ID_X550EM_A_KR_L:
 495                 hw->phy.type = ixgbe_phy_x550em_kr;
 496                 break;
 497         case IXGBE_DEV_ID_X550EM_X_1G_T:
 498         case IXGBE_DEV_ID_X550EM_X_10G_T:
 499         case IXGBE_DEV_ID_X550EM_A_10G_T:
 500                 return ixgbe_identify_phy_generic(hw);
 501         case IXGBE_DEV_ID_X550EM_A_1G_T:
 502         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
 503                 hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a;
 504                 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a;
 505                 if (hw->bus.lan_id)
 506                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
 507                 else
 508                         hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
 509                 return ixgbe_identify_phy_1g(hw);
 510         default:
 511                 break;
 512         }
 513         return IXGBE_SUCCESS;
 514 }
 515
 516 STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 517                                      u32 device_type, u16 *phy_data)
 518 {
 519         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);
 520         return IXGBE_NOT_IMPLEMENTED;
 521 }
 522
 523 STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 524                                       u32 device_type, u16 phy_data)
 525 {
 526         UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);
 527         return IXGBE_NOT_IMPLEMENTED;
 528 }
 529
 530 /**
 531  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 532  * @hw: pointer to the hardware structure
 533  * @addr: I2C bus address to read from
 534  * @reg: I2C device register to read from
 535  * @val: pointer to location to receive read value
 536  *
 537  * Returns an error code on error.
 538  **/
 539 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 540                                            u16 reg, u16 *val)
 541 {
 542         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
 543 }
 544
 545 /**
 546  * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
 547  * @hw: pointer to the hardware structure
 548  * @addr: I2C bus address to read from
 549  * @reg: I2C device register to read from
 550  * @val: pointer to location to receive read value
 551  *
 552  * Returns an error code on error.
 553  **/
 554 STATIC s32
 555 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
 556                                          u16 reg, u16 *val)
 557 {
 558         return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
 559 }
 560
 561 /**
 562  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 563  * @hw: pointer to the hardware structure
 564  * @addr: I2C bus address to write to
 565  * @reg: I2C device register to write to
 566  * @val: value to write
 567  *
 568  * Returns an error code on error.
 569  **/
 570 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 571                                             u8 addr, u16 reg, u16 val)
 572 {
 573         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
 574 }
 575
 576 /**
 577  * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
 578  * @hw: pointer to the hardware structure
 579  * @addr: I2C bus address to write to
 580  * @reg: I2C device register to write to
 581  * @val: value to write
 582  *
 583  * Returns an error code on error.
 584  **/
 585 STATIC s32
 586 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
 587                                           u8 addr, u16 reg, u16 val)
 588 {
 589         return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 590 }
 591
 592 /**
 593 *  ixgbe_init_ops_X550EM - Inits func ptrs and MAC type
 594 *  @hw: pointer to hardware structure
 595 *
 596 *  Initialize the function pointers and for MAC type X550EM.
 597 *  Does not touch the hardware.
 598 **/
 599 s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)
 600 {
 601         struct ixgbe_mac_info *mac = &hw->mac;
 602         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 603         struct ixgbe_phy_info *phy = &hw->phy;
 604         struct ixgbe_link_info *link = &hw->link;
 605         s32 ret_val;
 606
 607         DEBUGFUNC("ixgbe_init_ops_X550EM");
 608
 609         /* Similar to X550 so start there. */
 610         ret_val = ixgbe_init_ops_X550(hw);
 611
 612         /* Since this function eventually calls
 613          * ixgbe_init_ops_540 by design, we are setting
 614          * the pointers to NULL explicitly here to overwrite
 615          * the values being set in the x540 function.
 616          */
 617         /* Thermal sensor not supported in x550EM */
 618         mac->ops.get_thermal_sensor_data = NULL;
 619         mac->ops.init_thermal_sensor_thresh = NULL;
 620         mac->thermal_sensor_enabled = false;
 621
 622         /* FCOE not supported in x550EM */
 623         mac->ops.get_san_mac_addr = NULL;
 624         mac->ops.set_san_mac_addr = NULL;
 625         mac->ops.get_wwn_prefix = NULL;
 626         mac->ops.get_fcoe_boot_status = NULL;
 627
 628         /* IPsec not supported in x550EM */
 629         mac->ops.disable_sec_rx_path = NULL;
 630         mac->ops.enable_sec_rx_path = NULL;
 631
 632         /* AUTOC register is not present in x550EM. */
 633         mac->ops.prot_autoc_read = NULL;
 634         mac->ops.prot_autoc_write = NULL;
 635
 636         /* X550EM bus type is internal*/
 637         hw->bus.type = ixgbe_bus_type_internal;
 638         mac->ops.get_bus_info = ixgbe_get_bus_info_X550em;
 639
 640         if (hw->mac.type == ixgbe_mac_X550EM_x) {
 641                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 642                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 643                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;
 644                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;
 645                 link->ops.read_link = ixgbe_read_i2c_combined_generic;
 646                 link->ops.read_link_unlocked =
 647                                 ixgbe_read_i2c_combined_generic_unlocked;
 648                 link->ops.write_link = ixgbe_write_i2c_combined_generic;
 649                 link->ops.write_link_unlocked =
 650                                 ixgbe_write_i2c_combined_generic_unlocked;
 651                 link->addr = IXGBE_CS4227;
 652         }
 653         if (hw->mac.type == ixgbe_mac_X550EM_a) {
 654                 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;
 655                 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;
 656                 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550a;
 657                 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550a;
 658         }
 659
 660         mac->ops.get_media_type = ixgbe_get_media_type_X550em;
 661         mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;
 662         mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;
 663         mac->ops.reset_hw = ixgbe_reset_hw_X550em;
 664         mac->ops.get_supported_physical_layer =
 665                                     ixgbe_get_supported_physical_layer_X550em;
 666
 667         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)
 668                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
 669         else if (hw->mac.type == ixgbe_mac_X550EM_a) {
 670                 mac->ops.setup_fc = ixgbe_setup_fc_x550a;
 671                 mac->ops.fc_autoneg = ixgbe_fc_autoneg_x550a;
 672         }
 673         else
 674                 mac->ops.setup_fc = ixgbe_setup_fc_X550em;
 675
 676         switch (hw->device_id) {
 677         case IXGBE_DEV_ID_X550EM_X_KR:
 678         case IXGBE_DEV_ID_X550EM_A_KR:
 679         case IXGBE_DEV_ID_X550EM_A_KR_L:
 680                 break;
 681         default:
 682                 mac->ops.setup_eee = NULL;
 683         }
 684
 685         /* PHY */
 686         phy->ops.init = ixgbe_init_phy_ops_X550em;
 687         phy->ops.identify = ixgbe_identify_phy_x550em;
 688         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
 689                 phy->ops.set_phy_power = NULL;
 690
 691
 692         /* EEPROM */
 693         eeprom->ops.init_params = ixgbe_init_eeprom_params_X540;
 694         eeprom->ops.read = ixgbe_read_ee_hostif_X550;
 695         eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;
 696         eeprom->ops.write = ixgbe_write_ee_hostif_X550;
 697         eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;
 698         eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;
 699         eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;
 700         eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;
 701
 702         return ret_val;
 703 }
 704
 705 /**
 706  *  ixgbe_dmac_config_X550
 707  *  @hw: pointer to hardware structure
 708  *
 709  *  Configure DMA coalescing. If enabling dmac, dmac is activated.
 710  *  When disabling dmac, dmac enable dmac bit is cleared.
 711  **/
 712 s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)
 713 {
 714         u32 reg, high_pri_tc;
 715
 716         DEBUGFUNC("ixgbe_dmac_config_X550");
 717
 718         /* Disable DMA coalescing before configuring */
 719         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 720         reg &= ~IXGBE_DMACR_DMAC_EN;
 721         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 722
 723         /* Disable DMA Coalescing if the watchdog timer is 0 */
 724         if (!hw->mac.dmac_config.watchdog_timer)
 725                 goto out;
 726
 727         ixgbe_dmac_config_tcs_X550(hw);
 728
 729         /* Configure DMA Coalescing Control Register */
 730         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 731
 732         /* Set the watchdog timer in units of 40.96 usec */
 733         reg &= ~IXGBE_DMACR_DMACWT_MASK;
 734         reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;
 735
 736         reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;
 737         /* If fcoe is enabled, set high priority traffic class */
 738         if (hw->mac.dmac_config.fcoe_en) {
 739                 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;
 740                 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &
 741                         IXGBE_DMACR_HIGH_PRI_TC_MASK);
 742         }
 743         reg |= IXGBE_DMACR_EN_MNG_IND;
 744
 745         /* Enable DMA coalescing after configuration */
 746         reg |= IXGBE_DMACR_DMAC_EN;
 747         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 748
 749 out:
 750         return IXGBE_SUCCESS;
 751 }
 752
 753 /**
 754  *  ixgbe_dmac_config_tcs_X550
 755  *  @hw: pointer to hardware structure
 756  *
 757  *  Configure DMA coalescing threshold per TC. The dmac enable bit must
 758  *  be cleared before configuring.
 759  **/
 760 s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)
 761 {
 762         u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;
 763
 764         DEBUGFUNC("ixgbe_dmac_config_tcs_X550");
 765
 766         /* Configure DMA coalescing enabled */
 767         switch (hw->mac.dmac_config.link_speed) {
 768         case IXGBE_LINK_SPEED_100_FULL:
 769                 pb_headroom = IXGBE_DMACRXT_100M;
 770                 break;
 771         case IXGBE_LINK_SPEED_1GB_FULL:
 772                 pb_headroom = IXGBE_DMACRXT_1G;
 773                 break;
 774         default:
 775                 pb_headroom = IXGBE_DMACRXT_10G;
 776                 break;
 777         }
 778
 779         maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>
 780                              IXGBE_MHADD_MFS_SHIFT) / 1024);
 781
 782         /* Set the per Rx packet buffer receive threshold */
 783         for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {
 784                 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));
 785                 reg &= ~IXGBE_DMCTH_DMACRXT_MASK;
 786
 787                 if (tc < hw->mac.dmac_config.num_tcs) {
 788                         /* Get Rx PB size */
 789                         rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));
 790                         rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>
 791                                 IXGBE_RXPBSIZE_SHIFT;
 792
 793                         /* Calculate receive buffer threshold in kilobytes */
 794                         if (rx_pb_size > pb_headroom)
 795                                 rx_pb_size = rx_pb_size - pb_headroom;
 796                         else
 797                                 rx_pb_size = 0;
 798
 799                         /* Minimum of MFS shall be set for DMCTH */
 800                         reg |= (rx_pb_size > maxframe_size_kb) ?
 801                                 rx_pb_size : maxframe_size_kb;
 802                 }
 803                 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);
 804         }
 805         return IXGBE_SUCCESS;
 806 }
 807
 808 /**
 809  *  ixgbe_dmac_update_tcs_X550
 810  *  @hw: pointer to hardware structure
 811  *
 812  *  Disables dmac, updates per TC settings, and then enables dmac.
 813  **/
 814 s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)
 815 {
 816         u32 reg;
 817
 818         DEBUGFUNC("ixgbe_dmac_update_tcs_X550");
 819
 820         /* Disable DMA coalescing before configuring */
 821         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 822         reg &= ~IXGBE_DMACR_DMAC_EN;
 823         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 824
 825         ixgbe_dmac_config_tcs_X550(hw);
 826
 827         /* Enable DMA coalescing after configuration */
 828         reg = IXGBE_READ_REG(hw, IXGBE_DMACR);
 829         reg |= IXGBE_DMACR_DMAC_EN;
 830         IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);
 831
 832         return IXGBE_SUCCESS;
 833 }
 834
 835 /**
 836  *  ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 837  *  @hw: pointer to hardware structure
 838  *
 839  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 840  *  ixgbe_hw struct in order to set up EEPROM access.
 841  **/
 842 s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 843 {
 844         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 845         u32 eec;
 846         u16 eeprom_size;
 847
 848         DEBUGFUNC("ixgbe_init_eeprom_params_X550");
 849
 850         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 851                 eeprom->semaphore_delay = 10;
 852                 eeprom->type = ixgbe_flash;
 853
 854                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 855                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 856                                     IXGBE_EEC_SIZE_SHIFT);
 857                 eeprom->word_size = 1 << (eeprom_size +
 858                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 859
 860                 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
 861                           eeprom->type, eeprom->word_size);
 862         }
 863
 864         return IXGBE_SUCCESS;
 865 }
 866
 867 /**
 868  * ixgbe_enable_eee_x550 - Enable EEE support
 869  * @hw: pointer to hardware structure
 870  */
 871 STATIC s32 ixgbe_enable_eee_x550(struct ixgbe_hw *hw)
 872 {
 873         u16 autoneg_eee_reg;
 874         u32 link_reg;
 875         s32 status;
 876
 877         if (hw->mac.type == ixgbe_mac_X550) {
 878                 /* Advertise EEE capability */
 879                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 880                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 881                                      &autoneg_eee_reg);
 882
 883                 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 884                                     IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 885                                     IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 886
 887                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 888                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 889                                       autoneg_eee_reg);
 890                 return IXGBE_SUCCESS;
 891         }
 892
 893         switch (hw->device_id) {
 894         case IXGBE_DEV_ID_X550EM_X_KR:
 895         case IXGBE_DEV_ID_X550EM_A_KR:
 896         case IXGBE_DEV_ID_X550EM_A_KR_L:
 897                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 898                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 899                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 900                 if (status != IXGBE_SUCCESS)
 901                         return status;
 902
 903                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 904                         IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;
 905
 906                 /* Don't advertise FEC capability when EEE enabled. */
 907                 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 908
 909                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 910                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 911                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 912                 if (status != IXGBE_SUCCESS)
 913                         return status;
 914                 break;
 915         default:
 916                 break;
 917         }
 918
 919         return IXGBE_SUCCESS;
 920 }
 921
 922 /**
 923  * ixgbe_disable_eee_x550 - Disable EEE support
 924  * @hw: pointer to hardware structure
 925  */
 926 STATIC s32 ixgbe_disable_eee_x550(struct ixgbe_hw *hw)
 927 {
 928         u16 autoneg_eee_reg;
 929         u32 link_reg;
 930         s32 status;
 931
 932         if (hw->mac.type == ixgbe_mac_X550) {
 933                 /* Disable advertised EEE capability */
 934                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 935                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 936                                      &autoneg_eee_reg);
 937
 938                 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |
 939                                      IXGBE_AUTO_NEG_1000BASE_EEE_ADVT |
 940                                      IXGBE_AUTO_NEG_100BASE_EEE_ADVT);
 941
 942                 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,
 943                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 944                                       autoneg_eee_reg);
 945                 return IXGBE_SUCCESS;
 946         }
 947
 948         switch (hw->device_id) {
 949         case IXGBE_DEV_ID_X550EM_X_KR:
 950         case IXGBE_DEV_ID_X550EM_A_KR:
 951         case IXGBE_DEV_ID_X550EM_A_KR_L:
 952                 status = hw->mac.ops.read_iosf_sb_reg(hw,
 953                                      IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 954                                      IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);
 955                 if (status != IXGBE_SUCCESS)
 956                         return status;
 957
 958                 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |
 959                               IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);
 960
 961                 /* Advertise FEC capability when EEE is disabled. */
 962                 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;
 963
 964                 status = hw->mac.ops.write_iosf_sb_reg(hw,
 965                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
 966                                       IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);
 967                 if (status != IXGBE_SUCCESS)
 968                         return status;
 969                 break;
 970         default:
 971                 break;
 972         }
 973
 974         return IXGBE_SUCCESS;
 975 }
 976
 977 /**
 978  *  ixgbe_setup_eee_X550 - Enable/disable EEE support
 979  *  @hw: pointer to the HW structure
 980  *  @enable_eee: boolean flag to enable EEE
 981  *
 982  *  Enable/disable EEE based on enable_eee flag.
 983  *  Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
 984  *  are modified.
 985  *
 986  **/
 987 s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)
 988 {
 989         s32 status;
 990         u32 eeer;
 991
 992         DEBUGFUNC("ixgbe_setup_eee_X550");
 993
 994         eeer = IXGBE_READ_REG(hw, IXGBE_EEER);
 995         /* Enable or disable EEE per flag */
 996         if (enable_eee) {
 997                 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
 998
 999                 /* Not supported on first revision of X550EM_x. */
1000                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
1001                     !(IXGBE_FUSES0_REV_MASK &
1002                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
1003                         return IXGBE_SUCCESS;
1004                 status = ixgbe_enable_eee_x550(hw);
1005                 if (status)
1006                         return status;
1007         } else {
1008                 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);
1009
1010                 status = ixgbe_disable_eee_x550(hw);
1011                 if (status)
1012                         return status;
1013         }
1014         IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);
1015
1016         return IXGBE_SUCCESS;
1017 }
1018
1019 /**
1020  * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning
1021  * @hw: pointer to hardware structure
1022  * @enable: enable or disable source address pruning
1023  * @pool: Rx pool to set source address pruning for
1024  **/
1025 void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,
1026                                            unsigned int pool)
1027 {
1028         u64 pfflp;
1029
1030         /* max rx pool is 63 */
1031         if (pool > 63)
1032                 return;
1033
1034         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
1035         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
1036
1037         if (enable)
1038                 pfflp |= (1ULL << pool);
1039         else
1040                 pfflp &= ~(1ULL << pool);
1041
1042         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
1043         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
1044 }
1045
1046 /**
1047  *  ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing
1048  *  @hw: pointer to hardware structure
1049  *  @enable: enable or disable switch for Ethertype anti-spoofing
1050  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1051  *
1052  **/
1053 void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
1054                 bool enable, int vf)
1055 {
1056         int vf_target_reg = vf >> 3;
1057         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
1058         u32 pfvfspoof;
1059
1060         DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550");
1061
1062         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
1063         if (enable)
1064                 pfvfspoof |= (1 << vf_target_shift);
1065         else
1066                 pfvfspoof &= ~(1 << vf_target_shift);
1067
1068         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
1069 }
1070
1071 /**
1072  * ixgbe_iosf_wait - Wait for IOSF command completion
1073  * @hw: pointer to hardware structure
1074  * @ctrl: pointer to location to receive final IOSF control value
1075  *
1076  * Returns failing status on timeout
1077  *
1078  * Note: ctrl can be NULL if the IOSF control register value is not needed
1079  **/
1080 STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
1081 {
1082         u32 i, command = 0;
1083
1084         /* Check every 10 usec to see if the address cycle completed.
1085          * The SB IOSF BUSY bit will clear when the operation is
1086          * complete
1087          */
1088         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
1089                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
1090                 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)
1091                         break;
1092                 usec_delay(10);
1093         }
1094         if (ctrl)
1095                 *ctrl = command;
1096         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
1097                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n");
1098                 return IXGBE_ERR_PHY;
1099         }
1100
1101         return IXGBE_SUCCESS;
1102 }
1103
1104 /**
1105  *  ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1106  *  device
1107  *  @hw: pointer to hardware structure
1108  *  @reg_addr: 32 bit PHY register to write
1109  *  @device_type: 3 bit device type
1110  *  @data: Data to write to the register
1111  **/
1112 s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1113                             u32 device_type, u32 data)
1114 {
1115         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1116         u32 command, error;
1117         s32 ret;
1118
1119         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1120         if (ret != IXGBE_SUCCESS)
1121                 return ret;
1122
1123         ret = ixgbe_iosf_wait(hw, NULL);
1124         if (ret != IXGBE_SUCCESS)
1125                 goto out;
1126
1127         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1128                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1129
1130         /* Write IOSF control register */
1131         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1132
1133         /* Write IOSF data register */
1134         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1135
1136         ret = ixgbe_iosf_wait(hw, &command);
1137
1138         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1139                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1140                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1141                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1142                               "Failed to write, error %x\n", error);
1143                 ret = IXGBE_ERR_PHY;
1144         }
1145
1146 out:
1147         ixgbe_release_swfw_semaphore(hw, gssr);
1148         return ret;
1149 }
1150
1151 /**
1152  *  ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF
1153  *  device
1154  *  @hw: pointer to hardware structure
1155  *  @reg_addr: 32 bit PHY register to write
1156  *  @device_type: 3 bit device type
1157  *  @phy_data: Pointer to read data from the register
1158  **/
1159 s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1160                            u32 device_type, u32 *data)
1161 {
1162         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1163         u32 command, error;
1164         s32 ret;
1165
1166         ret = ixgbe_acquire_swfw_semaphore(hw, gssr);
1167         if (ret != IXGBE_SUCCESS)
1168                 return ret;
1169
1170         ret = ixgbe_iosf_wait(hw, NULL);
1171         if (ret != IXGBE_SUCCESS)
1172                 goto out;
1173
1174         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1175                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1176
1177         /* Write IOSF control register */
1178         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1179
1180         ret = ixgbe_iosf_wait(hw, &command);
1181
1182         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1183                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1184                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1185                 ERROR_REPORT2(IXGBE_ERROR_POLLING,
1186                                 "Failed to read, error %x\n", error);
1187                 ret = IXGBE_ERR_PHY;
1188         }
1189
1190         if (ret == IXGBE_SUCCESS)
1191                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
1192
1193 out:
1194         ixgbe_release_swfw_semaphore(hw, gssr);
1195         return ret;
1196 }
1197
1198 /**
1199  * ixgbe_get_phy_token - Get the token for shared phy access
1200  * @hw: Pointer to hardware structure
1201  */
1202
1203 s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
1204 {
1205         struct ixgbe_hic_phy_token_req token_cmd;
1206         s32 status;
1207
1208         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1209         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1210         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1211         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1212         token_cmd.port_number = hw->bus.lan_id;
1213         token_cmd.command_type = FW_PHY_TOKEN_REQ;
1214         token_cmd.pad = 0;
1215         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1216                                               sizeof(token_cmd),
1217                                               IXGBE_HI_COMMAND_TIMEOUT,
1218                                               true);
1219         if (status)
1220                 return status;
1221         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1222                 return IXGBE_SUCCESS;
1223         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
1224                 return IXGBE_ERR_FW_RESP_INVALID;
1225
1226         return IXGBE_ERR_TOKEN_RETRY;
1227 }
1228
1229 /**
1230  * ixgbe_put_phy_token - Put the token for shared phy access
1231  * @hw: Pointer to hardware structure
1232  */
1233
1234 s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
1235 {
1236         struct ixgbe_hic_phy_token_req token_cmd;
1237         s32 status;
1238
1239         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
1240         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
1241         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
1242         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1243         token_cmd.port_number = hw->bus.lan_id;
1244         token_cmd.command_type = FW_PHY_TOKEN_REL;
1245         token_cmd.pad = 0;
1246         status = ixgbe_host_interface_command(hw, (u32 *)&token_cmd,
1247                                               sizeof(token_cmd),
1248                                               IXGBE_HI_COMMAND_TIMEOUT,
1249                                               true);
1250         if (status)
1251                 return status;
1252         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
1253                 return IXGBE_SUCCESS;
1254
1255         DEBUGOUT("Put PHY Token host interface command failed");
1256         return IXGBE_ERR_FW_RESP_INVALID;
1257 }
1258
1259 /**
1260  *  ixgbe_write_iosf_sb_reg_x550a - Writes a value to specified register
1261  *  of the IOSF device
1262  *  @hw: pointer to hardware structure
1263  *  @reg_addr: 32 bit PHY register to write
1264  *  @device_type: 3 bit device type
1265  *  @data: Data to write to the register
1266  **/
1267 s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1268                                   u32 device_type, u32 data)
1269 {
1270         struct ixgbe_hic_internal_phy_req write_cmd;
1271         s32 status;
1272         UNREFERENCED_1PARAMETER(device_type);
1273
1274         memset(&write_cmd, 0, sizeof(write_cmd));
1275         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1276         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1277         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1278         write_cmd.port_number = hw->bus.lan_id;
1279         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
1280         write_cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1281         write_cmd.write_data = IXGBE_CPU_TO_LE32(data);
1282
1283         status = ixgbe_host_interface_command(hw, (u32 *)&write_cmd,
1284                                               sizeof(write_cmd),
1285                                               IXGBE_HI_COMMAND_TIMEOUT, false);
1286
1287         return status;
1288 }
1289
1290 /**
1291  *  ixgbe_read_iosf_sb_reg_x550a - Writes a value to specified register
1292  *  of the IOSF device.
1293  *  @hw: pointer to hardware structure
1294  *  @reg_addr: 32 bit PHY register to write
1295  *  @device_type: 3 bit device type
1296  *  @data: Pointer to read data from the register
1297  **/
1298 s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
1299                                  u32 device_type, u32 *data)
1300 {
1301         union {
1302                 struct ixgbe_hic_internal_phy_req cmd;
1303                 struct ixgbe_hic_internal_phy_resp rsp;
1304         } hic;
1305         s32 status;
1306         UNREFERENCED_1PARAMETER(device_type);
1307
1308         memset(&hic, 0, sizeof(hic));
1309         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
1310         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
1311         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1312         hic.cmd.port_number = hw->bus.lan_id;
1313         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
1314         hic.cmd.address = IXGBE_CPU_TO_BE16(reg_addr);
1315
1316         status = ixgbe_host_interface_command(hw, (u32 *)&hic.cmd,
1317                                               sizeof(hic.cmd),
1318                                               IXGBE_HI_COMMAND_TIMEOUT, true);
1319
1320         /* Extract the register value from the response. */
1321         *data = IXGBE_LE32_TO_CPU(hic.rsp.read_data);
1322
1323         return status;
1324 }
1325
1326 /**
1327  *  ixgbe_disable_mdd_X550
1328  *  @hw: pointer to hardware structure
1329  *
1330  *  Disable malicious driver detection
1331  **/
1332 void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)
1333 {
1334         u32 reg;
1335
1336         DEBUGFUNC("ixgbe_disable_mdd_X550");
1337
1338         /* Disable MDD for TX DMA and interrupt */
1339         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1340         reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1341         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1342
1343         /* Disable MDD for RX and interrupt */
1344         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1345         reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1346         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1347 }
1348
1349 /**
1350  *  ixgbe_enable_mdd_X550
1351  *  @hw: pointer to hardware structure
1352  *
1353  *  Enable malicious driver detection
1354  **/
1355 void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)
1356 {
1357         u32 reg;
1358
1359         DEBUGFUNC("ixgbe_enable_mdd_X550");
1360
1361         /* Enable MDD for TX DMA and interrupt */
1362         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1363         reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);
1364         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1365
1366         /* Enable MDD for RX and interrupt */
1367         reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1368         reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);
1369         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
1370 }
1371
1372 /**
1373  *  ixgbe_restore_mdd_vf_X550
1374  *  @hw: pointer to hardware structure
1375  *  @vf: vf index
1376  *
1377  *  Restore VF that was disabled during malicious driver detection event
1378  **/
1379 void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)
1380 {
1381         u32 idx, reg, num_qs, start_q, bitmask;
1382
1383         DEBUGFUNC("ixgbe_restore_mdd_vf_X550");
1384
1385         /* Map VF to queues */
1386         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1387         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1388         case IXGBE_MRQC_VMDQRT8TCEN:
1389                 num_qs = 8;  /* 16 VFs / pools */
1390                 bitmask = 0x000000FF;
1391                 break;
1392         case IXGBE_MRQC_VMDQRSS32EN:
1393         case IXGBE_MRQC_VMDQRT4TCEN:
1394                 num_qs = 4;  /* 32 VFs / pools */
1395                 bitmask = 0x0000000F;
1396                 break;
1397         default:            /* 64 VFs / pools */
1398                 num_qs = 2;
1399                 bitmask = 0x00000003;
1400                 break;
1401         }
1402         start_q = vf * num_qs;
1403
1404         /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */
1405         idx = start_q / 32;
1406         reg = 0;
1407         reg |= (bitmask << (start_q % 32));
1408         IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);
1409         IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);
1410 }
1411
1412 /**
1413  *  ixgbe_mdd_event_X550
1414  *  @hw: pointer to hardware structure
1415  *  @vf_bitmap: vf bitmap of malicious vfs
1416  *
1417  *  Handle malicious driver detection event.
1418  **/
1419 void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)
1420 {
1421         u32 wqbr;
1422         u32 i, j, reg, q, shift, vf, idx;
1423
1424         DEBUGFUNC("ixgbe_mdd_event_X550");
1425
1426         /* figure out pool size for mapping to vf's */
1427         reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
1428         switch (reg & IXGBE_MRQC_MRQE_MASK) {
1429         case IXGBE_MRQC_VMDQRT8TCEN:
1430                 shift = 3;  /* 16 VFs / pools */
1431                 break;
1432         case IXGBE_MRQC_VMDQRSS32EN:
1433         case IXGBE_MRQC_VMDQRT4TCEN:
1434                 shift = 2;  /* 32 VFs / pools */
1435                 break;
1436         default:
1437                 shift = 1;  /* 64 VFs / pools */
1438                 break;
1439         }
1440
1441         /* Read WQBR_TX and WQBR_RX and check for malicious queues */
1442         for (i = 0; i < 4; i++) {
1443                 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));
1444                 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));
1445
1446                 if (!wqbr)
1447                         continue;
1448
1449                 /* Get malicious queue */
1450                 for (j = 0; j < 32 && wqbr; j++) {
1451
1452                         if (!(wqbr & (1 << j)))
1453                                 continue;
1454
1455                         /* Get queue from bitmask */
1456                         q = j + (i * 32);
1457
1458                         /* Map queue to vf */
1459                         vf = (q >> shift);
1460
1461                         /* Set vf bit in vf_bitmap */
1462                         idx = vf / 32;
1463                         vf_bitmap[idx] |= (1 << (vf % 32));
1464                         wqbr &= ~(1 << j);
1465                 }
1466         }
1467 }
1468
1469 /**
1470  *  ixgbe_get_media_type_X550em - Get media type
1471  *  @hw: pointer to hardware structure
1472  *
1473  *  Returns the media type (fiber, copper, backplane)
1474  */
1475 enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
1476 {
1477         enum ixgbe_media_type media_type;
1478
1479         DEBUGFUNC("ixgbe_get_media_type_X550em");
1480
1481         /* Detect if there is a copper PHY attached. */
1482         switch (hw->device_id) {
1483         case IXGBE_DEV_ID_X550EM_X_KR:
1484         case IXGBE_DEV_ID_X550EM_X_KX4:
1485         case IXGBE_DEV_ID_X550EM_A_KR:
1486         case IXGBE_DEV_ID_X550EM_A_KR_L:
1487                 media_type = ixgbe_media_type_backplane;
1488                 break;
1489         case IXGBE_DEV_ID_X550EM_X_SFP:
1490         case IXGBE_DEV_ID_X550EM_A_SFP:
1491         case IXGBE_DEV_ID_X550EM_A_SFP_N:
1492         case IXGBE_DEV_ID_X550EM_A_QSFP:
1493         case IXGBE_DEV_ID_X550EM_A_QSFP_N:
1494                 media_type = ixgbe_media_type_fiber;
1495                 break;
1496         case IXGBE_DEV_ID_X550EM_X_1G_T:
1497         case IXGBE_DEV_ID_X550EM_X_10G_T:
1498         case IXGBE_DEV_ID_X550EM_A_10G_T:
1499                 media_type = ixgbe_media_type_copper;
1500                 break;
1501         case IXGBE_DEV_ID_X550EM_A_SGMII:
1502         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1503                 media_type = ixgbe_media_type_backplane;
1504                 hw->phy.type = ixgbe_phy_sgmii;
1505                 break;
1506         case IXGBE_DEV_ID_X550EM_A_1G_T:
1507         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1508                 media_type = ixgbe_media_type_copper;
1509                 hw->phy.type = ixgbe_phy_m88;
1510                 break;
1511         default:
1512                 media_type = ixgbe_media_type_unknown;
1513                 break;
1514         }
1515         return media_type;
1516 }
1517
1518 /**
1519  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1520  *  @hw: pointer to hardware structure
1521  *  @linear: true if SFP module is linear
1522  */
1523 STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1524 {
1525         DEBUGFUNC("ixgbe_supported_sfp_modules_X550em");
1526
1527         switch (hw->phy.sfp_type) {
1528         case ixgbe_sfp_type_not_present:
1529                 return IXGBE_ERR_SFP_NOT_PRESENT;
1530         case ixgbe_sfp_type_da_cu_core0:
1531         case ixgbe_sfp_type_da_cu_core1:
1532                 *linear = true;
1533                 break;
1534         case ixgbe_sfp_type_srlr_core0:
1535         case ixgbe_sfp_type_srlr_core1:
1536         case ixgbe_sfp_type_da_act_lmt_core0:
1537         case ixgbe_sfp_type_da_act_lmt_core1:
1538         case ixgbe_sfp_type_1g_sx_core0:
1539         case ixgbe_sfp_type_1g_sx_core1:
1540         case ixgbe_sfp_type_1g_lx_core0:
1541         case ixgbe_sfp_type_1g_lx_core1:
1542                 *linear = false;
1543                 break;
1544         case ixgbe_sfp_type_unknown:
1545         case ixgbe_sfp_type_1g_cu_core0:
1546         case ixgbe_sfp_type_1g_cu_core1:
1547         default:
1548                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1549         }
1550
1551         return IXGBE_SUCCESS;
1552 }
1553
1554 /**
1555  *  ixgbe_identify_sfp_module_X550em - Identifies SFP modules
1556  *  @hw: pointer to hardware structure
1557  *
1558  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1559  **/
1560 s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)
1561 {
1562         s32 status;
1563         bool linear;
1564
1565         DEBUGFUNC("ixgbe_identify_sfp_module_X550em");
1566
1567         status = ixgbe_identify_module_generic(hw);
1568
1569         if (status != IXGBE_SUCCESS)
1570                 return status;
1571
1572         /* Check if SFP module is supported */
1573         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1574
1575         return status;
1576 }
1577
1578 /**
1579  *  ixgbe_setup_sfp_modules_X550em - Setup MAC link ops
1580  *  @hw: pointer to hardware structure
1581  */
1582 s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1583 {
1584         s32 status;
1585         bool linear;
1586
1587         DEBUGFUNC("ixgbe_setup_sfp_modules_X550em");
1588
1589         /* Check if SFP module is supported */
1590         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1591
1592         if (status != IXGBE_SUCCESS)
1593                 return status;
1594
1595         ixgbe_init_mac_link_ops_X550em(hw);
1596         hw->phy.ops.reset = NULL;
1597
1598         return IXGBE_SUCCESS;
1599 }
1600
1601 /**
1602  * ixgbe_setup_sgmii - Set up link for sgmii
1603  * @hw: pointer to hardware structure
1604  */
1605 STATIC s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1606                              bool autoneg_wait_to_complete)
1607 {
1608         struct ixgbe_mac_info *mac = &hw->mac;
1609         u32 lval, sval;
1610         s32 rc;
1611         UNREFERENCED_2PARAMETER(speed, autoneg_wait_to_complete);
1612
1613         rc = mac->ops.read_iosf_sb_reg(hw,
1614                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1615                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1616         if (rc)
1617                 return rc;
1618
1619         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1620         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1621         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1622         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1623         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1624         rc = mac->ops.write_iosf_sb_reg(hw,
1625                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1626                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1627         if (rc)
1628                 return rc;
1629
1630         rc = mac->ops.read_iosf_sb_reg(hw,
1631                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1632                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1633         if (rc)
1634                 return rc;
1635
1636         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1637         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1638         rc = mac->ops.write_iosf_sb_reg(hw,
1639                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1640                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1641         if (rc)
1642                 return rc;
1643
1644         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1645         rc = mac->ops.write_iosf_sb_reg(hw,
1646                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1647                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1648
1649         return rc;
1650 }
1651
1652 /**
1653  *  ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1654  *  @hw: pointer to hardware structure
1655  */
1656 void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1657 {
1658         struct ixgbe_mac_info *mac = &hw->mac;
1659
1660         DEBUGFUNC("ixgbe_init_mac_link_ops_X550em");
1661
1662         switch (hw->mac.ops.get_media_type(hw)) {
1663         case ixgbe_media_type_fiber:
1664                 /* CS4227 does not support autoneg, so disable the laser control
1665                  * functions for SFP+ fiber
1666                  */
1667                 mac->ops.disable_tx_laser = NULL;
1668                 mac->ops.enable_tx_laser = NULL;
1669                 mac->ops.flap_tx_laser = NULL;
1670                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1671                 mac->ops.set_rate_select_speed =
1672                                         ixgbe_set_soft_rate_select_speed;
1673                 if ((hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) ||
1674                     (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP))
1675                         mac->ops.setup_mac_link =
1676                                 ixgbe_setup_mac_link_sfp_x550a;
1677                 else
1678                         mac->ops.setup_mac_link =
1679                                 ixgbe_setup_mac_link_sfp_x550em;
1680                 break;
1681         case ixgbe_media_type_copper:
1682                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1683                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1684                 break;
1685         case ixgbe_media_type_backplane:
1686                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1687                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1688                         mac->ops.setup_link = ixgbe_setup_sgmii;
1689                 break;
1690         default:
1691                 break;
1692         }
1693 }
1694
1695 /**
1696  *  ixgbe_get_link_capabilities_x550em - Determines link capabilities
1697  *  @hw: pointer to hardware structure
1698  *  @speed: pointer to link speed
1699  *  @autoneg: true when autoneg or autotry is enabled
1700  */
1701 s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1702                                        ixgbe_link_speed *speed,
1703                                        bool *autoneg)
1704 {
1705         DEBUGFUNC("ixgbe_get_link_capabilities_X550em");
1706
1707         /* SFP */
1708         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1709
1710                 /* CS4227 SFP must not enable auto-negotiation */
1711                 *autoneg = false;
1712
1713                 /* Check if 1G SFP module. */
1714                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1715                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1
1716                     || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1717                     hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
1718                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1719                         return IXGBE_SUCCESS;
1720                 }
1721
1722                 /* Link capabilities are based on SFP */
1723                 if (hw->phy.multispeed_fiber)
1724                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1725                                  IXGBE_LINK_SPEED_1GB_FULL;
1726                 else
1727                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1728         } else {
1729                 switch (hw->phy.type) {
1730                 case ixgbe_phy_m88:
1731                         *speed = IXGBE_LINK_SPEED_100_FULL |
1732                                  IXGBE_LINK_SPEED_1GB_FULL;
1733                         break;
1734                 case ixgbe_phy_sgmii:
1735                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1736                         break;
1737                 default:
1738                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1739                                  IXGBE_LINK_SPEED_1GB_FULL;
1740                         break;
1741                 }
1742                 *autoneg = true;
1743         }
1744
1745         return IXGBE_SUCCESS;
1746 }
1747
1748 /**
1749  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1750  * @hw: pointer to hardware structure
1751  * @lsc: pointer to boolean flag which indicates whether external Base T
1752  *       PHY interrupt is lsc
1753  *
1754  * Determime if external Base T PHY interrupt cause is high temperature
1755  * failure alarm or link status change.
1756  *
1757  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1758  * failure alarm, else return PHY access status.
1759  */
1760 STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1761 {
1762         u32 status;
1763         u16 reg;
1764
1765         *lsc = false;
1766
1767         /* Vendor alarm triggered */
1768         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1769                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1770                                       &reg);
1771
1772         if (status != IXGBE_SUCCESS ||
1773             !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1774                 return status;
1775
1776         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1777         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1778                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1779                                       &reg);
1780
1781         if (status != IXGBE_SUCCESS ||
1782             !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1783             IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1784                 return status;
1785
1786         /* Global alarm triggered */
1787         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1788                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1789                                       &reg);
1790
1791         if (status != IXGBE_SUCCESS)
1792                 return status;
1793
1794         /* If high temperature failure, then return over temp error and exit */
1795         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1796                 /* power down the PHY in case the PHY FW didn't already */
1797                 ixgbe_set_copper_phy_power(hw, false);
1798                 return IXGBE_ERR_OVERTEMP;
1799         } else if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1800                 /*  device fault alarm triggered */
1801                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1802                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1803                                           &reg);
1804
1805                 if (status != IXGBE_SUCCESS)
1806                         return status;
1807
1808                 /* if device fault was due to high temp alarm handle and exit */
1809                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1810                         /* power down the PHY in case the PHY FW didn't */
1811                         ixgbe_set_copper_phy_power(hw, false);
1812                         return IXGBE_ERR_OVERTEMP;
1813                 }
1814         }
1815
1816         /* Vendor alarm 2 triggered */
1817         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1818                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1819
1820         if (status != IXGBE_SUCCESS ||
1821             !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1822                 return status;
1823
1824         /* link connect/disconnect event occurred */
1825         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1826                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1827
1828         if (status != IXGBE_SUCCESS)
1829                 return status;
1830
1831         /* Indicate LSC */
1832         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1833                 *lsc = true;
1834
1835         return IXGBE_SUCCESS;
1836 }
1837
1838 /**
1839  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1840  * @hw: pointer to hardware structure
1841  *
1842  * Enable link status change and temperature failure alarm for the external
1843  * Base T PHY
1844  *
1845  * Returns PHY access status
1846  */
1847 STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1848 {
1849         u32 status;
1850         u16 reg;
1851         bool lsc;
1852
1853         /* Clear interrupt flags */
1854         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1855
1856         /* Enable link status change alarm */
1857         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1858                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1859
1860         if (status != IXGBE_SUCCESS)
1861                 return status;
1862
1863         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1864
1865         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1866                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1867
1868         if (status != IXGBE_SUCCESS)
1869                 return status;
1870
1871         /* Enable high temperature failure and global fault alarms */
1872         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1873                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1874                                       &reg);
1875
1876         if (status != IXGBE_SUCCESS)
1877                 return status;
1878
1879         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1880                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1881
1882         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1883                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1884                                        reg);
1885
1886         if (status != IXGBE_SUCCESS)
1887                 return status;
1888
1889         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1890         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1891                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1892                                       &reg);
1893
1894         if (status != IXGBE_SUCCESS)
1895                 return status;
1896
1897         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1898                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1899
1900         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1901                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1902                                        reg);
1903
1904         if (status != IXGBE_SUCCESS)
1905                 return status;
1906
1907         /* Enable chip-wide vendor alarm */
1908         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1909                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1910                                       &reg);
1911
1912         if (status != IXGBE_SUCCESS)
1913                 return status;
1914
1915         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1916
1917         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1918                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1919                                        reg);
1920
1921         return status;
1922 }
1923
1924 /**
1925  *  ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1926  *  @hw: pointer to hardware structure
1927  *  @speed: link speed
1928  *
1929  *  Configures the integrated KR PHY.
1930  **/
1931 STATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1932                                        ixgbe_link_speed speed)
1933 {
1934         s32 status;
1935         u32 reg_val;
1936
1937         status = hw->mac.ops.read_iosf_sb_reg(hw,
1938                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1939                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1940         if (status)
1941                 return status;
1942
1943         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1944         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1945                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1946
1947         /* Advertise 10G support. */
1948         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1949                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1950
1951         /* Advertise 1G support. */
1952         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1953                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1954
1955         /* Restart auto-negotiation. */
1956         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1957         status = hw->mac.ops.write_iosf_sb_reg(hw,
1958                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1959                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1960
1961         return status;
1962 }
1963
1964 /**
1965  * ixgbe_set_master_slave_mode - Set up PHY for master/slave mode
1966  * @hw: pointer to hardware structure
1967  *
1968  * Must be called while holding the PHY semaphore and token
1969  */
1970 STATIC s32 ixgbe_set_master_slave_mode(struct ixgbe_hw *hw)
1971 {
1972         u16 phy_data;
1973         s32 rc;
1974
1975         /* Resolve master/slave mode */
1976         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
1977                                        &phy_data);
1978         if (rc)
1979                 return rc;
1980
1981         /* load defaults for future use */
1982         if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_ENABLE) {
1983                 if (phy_data & IXGBE_M88E1500_1000T_CTRL_MS_VALUE)
1984                         hw->phy.original_ms_type = ixgbe_ms_force_master;
1985                 else
1986                         hw->phy.original_ms_type = ixgbe_ms_force_slave;
1987         } else {
1988                 hw->phy.original_ms_type = ixgbe_ms_auto;
1989         }
1990
1991         switch (hw->phy.ms_type) {
1992         case ixgbe_ms_force_master:
1993                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1994                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1995                 break;
1996         case ixgbe_ms_force_slave:
1997                 phy_data |= IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
1998                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_VALUE;
1999                 break;
2000         case ixgbe_ms_auto:
2001                 phy_data &= ~IXGBE_M88E1500_1000T_CTRL_MS_ENABLE;
2002                 break;
2003         default:
2004                 break;
2005         }
2006
2007         return ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_1000T_CTRL, 0,
2008                                           phy_data);
2009 }
2010
2011 /**
2012  * ixgbe_reset_phy_m88_nolock - Reset m88 PHY without locking
2013  * @hw: pointer to hardware structure
2014  *
2015  * Must be called while holding the PHY semaphore and token
2016  */
2017 STATIC s32 ixgbe_reset_phy_m88_nolock(struct ixgbe_hw *hw)
2018 {
2019         s32 rc;
2020
2021         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 1);
2022         if (rc)
2023                 return rc;
2024
2025         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_FIBER_CTRL, 0,
2026                                         IXGBE_M88E1500_FIBER_CTRL_RESET |
2027                                         IXGBE_M88E1500_FIBER_CTRL_DUPLEX_FULL |
2028                                         IXGBE_M88E1500_FIBER_CTRL_SPEED_MSB);
2029         if (rc)
2030                 goto res_out;
2031
2032         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 18);
2033         if (rc)
2034                 goto res_out;
2035
2036         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_GEN_CTRL, 0,
2037                                         IXGBE_M88E1500_GEN_CTRL_RESET |
2038                                         IXGBE_M88E1500_GEN_CTRL_SGMII_COPPER);
2039         if (rc)
2040                 goto res_out;
2041
2042         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2043         if (rc)
2044                 goto res_out;
2045
2046         rc = ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_COPPER_CTRL, 0,
2047                                         IXGBE_M88E1500_COPPER_CTRL_RESET |
2048                                         IXGBE_M88E1500_COPPER_CTRL_AN_EN |
2049                                         IXGBE_M88E1500_COPPER_CTRL_RESTART_AN |
2050                                         IXGBE_M88E1500_COPPER_CTRL_FULL_DUPLEX |
2051                                         IXGBE_M88E1500_COPPER_CTRL_SPEED_MSB);
2052
2053 res_out:
2054         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2055         return rc;
2056 }
2057
2058 /**
2059  * ixgbe_reset_phy_m88 - Reset m88 PHY
2060  * @hw: pointer to hardware structure
2061  */
2062 STATIC s32 ixgbe_reset_phy_m88(struct ixgbe_hw *hw)
2063 {
2064         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2065         s32 rc;
2066
2067         if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
2068                 return IXGBE_SUCCESS;
2069
2070         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2071         if (rc)
2072                 return rc;
2073
2074         rc = ixgbe_reset_phy_m88_nolock(hw);
2075
2076         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2077         return rc;
2078 }
2079
2080 /**
2081  * ixgbe_setup_m88 - setup m88 PHY
2082  * @hw: pointer to hardware structure
2083  */
2084 STATIC s32 ixgbe_setup_m88(struct ixgbe_hw *hw)
2085 {
2086         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2087         struct ixgbe_phy_info *phy = &hw->phy;
2088         u16 phy_data;
2089         s32 rc;
2090
2091         if (phy->reset_disable || ixgbe_check_reset_blocked(hw))
2092                 return IXGBE_SUCCESS;
2093
2094         rc = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
2095         if (rc)
2096                 return rc;
2097
2098         rc = ixgbe_read_phy_reg_mdi_22(hw, IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2099                                        &phy_data);
2100         if (rc)
2101                 goto rel_out;
2102
2103         /* Enable downshift and setting it to X6 */
2104         phy_data &= ~IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2105         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_6X;
2106         phy_data |= IXGBE_M88E1500_PSCR_DOWNSHIFT_ENABLE;
2107         rc = ixgbe_write_phy_reg_mdi_22(hw,
2108                                         IXGBE_M88E1500_PHY_SPEC_CTRL, 0,
2109                                         phy_data);
2110         if (rc)
2111                 goto rel_out;
2112
2113         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2114
2115         /* Commit the changes */
2116         rc = ixgbe_reset_phy_m88_nolock(hw);
2117         if (rc) {
2118                 DEBUGOUT("Error committing the PHY changes\n");
2119                 goto rel_out;
2120         }
2121
2122         rc = ixgbe_set_master_slave_mode(hw);
2123
2124         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2125         return rc;
2126
2127 rel_out:
2128         ixgbe_write_phy_reg_mdi_22(hw, IXGBE_M88E1500_PAGE_ADDR, 0, 0);
2129         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2130         return rc;
2131 }
2132
2133 /**
2134  *  ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2135  *  @hw: pointer to hardware structure
2136  *
2137  *  Read NW_MNG_IF_SEL register and save field values, and check for valid field
2138  *  values.
2139  **/
2140 STATIC s32 ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2141 {
2142         /* Save NW management interface connected on board. This is used
2143          * to determine internal PHY mode.
2144          */
2145         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2146
2147         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2148          * PHY address. This register field was has only been used for X552.
2149          */
2150         if (hw->mac.type == ixgbe_mac_X550EM_a &&
2151             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2152                 hw->phy.addr = (hw->phy.nw_mng_if_sel &
2153                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2154                                 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2155         }
2156
2157         return IXGBE_SUCCESS;
2158 }
2159
2160 /**
2161  *  ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2162  *  @hw: pointer to hardware structure
2163  *
2164  *  Initialize any function pointers that were not able to be
2165  *  set during init_shared_code because the PHY/SFP type was
2166  *  not known.  Perform the SFP init if necessary.
2167  */
2168 s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2169 {
2170         struct ixgbe_phy_info *phy = &hw->phy;
2171         s32 ret_val;
2172
2173         DEBUGFUNC("ixgbe_init_phy_ops_X550em");
2174
2175         hw->mac.ops.set_lan_id(hw);
2176
2177         ixgbe_read_mng_if_sel_x550em(hw);
2178
2179         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2180                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2181                 ixgbe_setup_mux_ctl(hw);
2182                 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;
2183         }
2184
2185         /* Identify the PHY or SFP module */
2186         ret_val = phy->ops.identify(hw);
2187         if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
2188                 return ret_val;
2189
2190         /* Setup function pointers based on detected hardware */
2191         ixgbe_init_mac_link_ops_X550em(hw);
2192         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2193                 phy->ops.reset = NULL;
2194
2195         /* Set functions pointers based on phy type */
2196         switch (hw->phy.type) {
2197         case ixgbe_phy_x550em_kx4:
2198                 phy->ops.setup_link = NULL;
2199                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2200                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2201                 break;
2202         case ixgbe_phy_x550em_kr:
2203                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2204                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2205                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2206                 break;
2207         case ixgbe_phy_x550em_ext_t:
2208                 /* If internal link mode is XFI, then setup iXFI internal link,
2209                  * else setup KR now.
2210                  */
2211                 phy->ops.setup_internal_link =
2212                                               ixgbe_setup_internal_phy_t_x550em;
2213
2214                 /* setup SW LPLU only for first revision of X550EM_x */
2215                 if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
2216                     !(IXGBE_FUSES0_REV_MASK &
2217                       IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
2218                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2219
2220                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2221                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2222                 break;
2223         case ixgbe_phy_sgmii:
2224                 phy->ops.setup_link = NULL;
2225                 break;
2226         case ixgbe_phy_m88:
2227                 phy->ops.setup_link = ixgbe_setup_m88;
2228                 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22;
2229                 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22;
2230                 phy->ops.reset = ixgbe_reset_phy_m88;
2231                 break;
2232         default:
2233                 break;
2234         }
2235         return ret_val;
2236 }
2237
2238 /**
2239  * ixgbe_set_mdio_speed - Set MDIO clock speed
2240  *  @hw: pointer to hardware structure
2241  */
2242 STATIC void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2243 {
2244         u32 hlreg0;
2245
2246         switch (hw->device_id) {
2247         case IXGBE_DEV_ID_X550EM_X_10G_T:
2248         case IXGBE_DEV_ID_X550EM_A_SGMII:
2249         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2250         case IXGBE_DEV_ID_X550EM_A_1G_T:
2251         case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2252         case IXGBE_DEV_ID_X550EM_A_10G_T:
2253         case IXGBE_DEV_ID_X550EM_A_SFP:
2254         case IXGBE_DEV_ID_X550EM_A_QSFP:
2255                 /* Config MDIO clock speed before the first MDIO PHY access */
2256                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2257                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2258                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2259                 break;
2260         default:
2261                 break;
2262         }
2263 }
2264
2265 /**
2266  *  ixgbe_reset_hw_X550em - Perform hardware reset
2267  *  @hw: pointer to hardware structure
2268  *
2269  *  Resets the hardware by resetting the transmit and receive units, masks
2270  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2271  *  reset.
2272  */
2273 s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2274 {
2275         ixgbe_link_speed link_speed;
2276         s32 status;
2277         u32 ctrl = 0;
2278         u32 i;
2279         bool link_up = false;
2280
2281         DEBUGFUNC("ixgbe_reset_hw_X550em");
2282
2283         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2284         status = hw->mac.ops.stop_adapter(hw);
2285         if (status != IXGBE_SUCCESS)
2286                 return status;
2287
2288         /* flush pending Tx transactions */
2289         ixgbe_clear_tx_pending(hw);
2290
2291         ixgbe_set_mdio_speed(hw);
2292
2293         /* PHY ops must be identified and initialized prior to reset */
2294         status = hw->phy.ops.init(hw);
2295
2296         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2297                 return status;
2298
2299         /* start the external PHY */
2300         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2301                 status = ixgbe_init_ext_t_x550em(hw);
2302                 if (status)
2303                         return status;
2304         }
2305
2306         /* Setup SFP module if there is one present. */
2307         if (hw->phy.sfp_setup_needed) {
2308                 status = hw->mac.ops.setup_sfp(hw);
2309                 hw->phy.sfp_setup_needed = false;
2310         }
2311
2312         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
2313                 return status;
2314
2315         /* Reset PHY */
2316         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2317                 hw->phy.ops.reset(hw);
2318
2319 mac_reset_top:
2320         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2321          * If link reset is used when link is up, it might reset the PHY when
2322          * mng is using it.  If link is down or the flag to force full link
2323          * reset is set, then perform link reset.
2324          */
2325         ctrl = IXGBE_CTRL_LNK_RST;
2326         if (!hw->force_full_reset) {
2327                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2328                 if (link_up)
2329                         ctrl = IXGBE_CTRL_RST;
2330         }
2331
2332         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2333         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2334         IXGBE_WRITE_FLUSH(hw);
2335
2336         /* Poll for reset bit to self-clear meaning reset is complete */
2337         for (i = 0; i < 10; i++) {
2338                 usec_delay(1);
2339                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2340                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2341                         break;
2342         }
2343
2344         if (ctrl & IXGBE_CTRL_RST_MASK) {
2345                 status = IXGBE_ERR_RESET_FAILED;
2346                 DEBUGOUT("Reset polling failed to complete.\n");
2347         }
2348
2349         msec_delay(50);
2350
2351         /* Double resets are required for recovery from certain error
2352          * conditions.  Between resets, it is necessary to stall to
2353          * allow time for any pending HW events to complete.
2354          */
2355         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2356                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2357                 goto mac_reset_top;
2358         }
2359
2360         /* Store the permanent mac address */
2361         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2362
2363         /* Store MAC address from RAR0, clear receive address registers, and
2364          * clear the multicast table.  Also reset num_rar_entries to 128,
2365          * since we modify this value when programming the SAN MAC address.
2366          */
2367         hw->mac.num_rar_entries = 128;
2368         hw->mac.ops.init_rx_addrs(hw);
2369
2370         ixgbe_set_mdio_speed(hw);
2371
2372         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2373                 ixgbe_setup_mux_ctl(hw);
2374
2375         return status;
2376 }
2377
2378 /**
2379  * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2380  * @hw: pointer to hardware structure
2381  */
2382 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2383 {
2384         u32 status;
2385         u16 reg;
2386
2387         status = hw->phy.ops.read_reg(hw,
2388                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2389                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2390                                       &reg);
2391
2392         if (status != IXGBE_SUCCESS)
2393                 return status;
2394
2395         /* If PHY FW reset completed bit is set then this is the first
2396          * SW instance after a power on so the PHY FW must be un-stalled.
2397          */
2398         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2399                 status = hw->phy.ops.read_reg(hw,
2400                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2401                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2402                                         &reg);
2403
2404                 if (status != IXGBE_SUCCESS)
2405                         return status;
2406
2407                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2408
2409                 status = hw->phy.ops.write_reg(hw,
2410                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2411                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2412                                         reg);
2413
2414                 if (status != IXGBE_SUCCESS)
2415                         return status;
2416         }
2417
2418         return status;
2419 }
2420
2421 /**
2422  *  ixgbe_setup_kr_x550em - Configure the KR PHY.
2423  *  @hw: pointer to hardware structure
2424  *
2425  *  Configures the integrated KR PHY for X550EM_x.
2426  **/
2427 s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2428 {
2429         if (hw->mac.type != ixgbe_mac_X550EM_x)
2430                 return IXGBE_SUCCESS;
2431
2432         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2433 }
2434
2435 /**
2436  *  ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP
2437  *  @hw: pointer to hardware structure
2438  *
2439  *  Configure the external PHY and the integrated KR PHY for SFP support.
2440  **/
2441 s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
2442                                     ixgbe_link_speed speed,
2443                                     bool autoneg_wait_to_complete)
2444 {
2445         s32 ret_val;
2446         u16 reg_slice, reg_val;
2447         bool setup_linear = false;
2448         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2449
2450         /* Check if SFP module is supported and linear */
2451         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2452
2453         /* If no SFP module present, then return success. Return success since
2454          * there is no reason to configure CS4227 and SFP not present error is
2455          * not excepted in the setup MAC link flow.
2456          */
2457         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2458                 return IXGBE_SUCCESS;
2459
2460         if (ret_val != IXGBE_SUCCESS)
2461                 return ret_val;
2462
2463         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2464                 /* Configure CS4227 LINE side to 10G SR. */
2465                 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB +
2466                             (hw->bus.lan_id << 12);
2467                 reg_val = IXGBE_CS4227_SPEED_10G;
2468                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2469                                                   reg_val);
2470
2471                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2472                             (hw->bus.lan_id << 12);
2473                 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2474                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2475                                                   reg_val);
2476
2477                 /* Configure CS4227 for HOST connection rate then type. */
2478                 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB +
2479                             (hw->bus.lan_id << 12);
2480                 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?
2481                 IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
2482                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2483                                                   reg_val);
2484
2485                 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB +
2486                             (hw->bus.lan_id << 12);
2487                 if (setup_linear)
2488                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2489                 else
2490                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2491                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2492                                                   reg_val);
2493
2494                 /* Setup XFI internal link. */
2495                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2496         } else {
2497                 /* Configure internal PHY for KR/KX. */
2498                 ixgbe_setup_kr_speed_x550em(hw, speed);
2499
2500                 /* Configure CS4227 LINE side to proper mode. */
2501                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB +
2502                             (hw->bus.lan_id << 12);
2503                 if (setup_linear)
2504                         reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2505                 else
2506                         reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2507                 ret_val = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
2508                                                   reg_val);
2509         }
2510         return ret_val;
2511 }
2512
2513 /**
2514  *  ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
2515  *  @hw: pointer to hardware structure
2516  *
2517  *  Configure the the integrated PHY for SFP support.
2518  **/
2519 s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw,
2520                                    ixgbe_link_speed speed,
2521                                    bool autoneg_wait_to_complete)
2522 {
2523         s32 ret_val;
2524         u16 reg_phy_ext;
2525         bool setup_linear = false;
2526         u32 reg_slice, reg_phy_int, slice_offset;
2527
2528         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
2529
2530         /* Check if SFP module is supported and linear */
2531         ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
2532
2533         /* If no SFP module present, then return success. Return success since
2534          * SFP not present error is not excepted in the setup MAC link flow.
2535          */
2536         if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
2537                 return IXGBE_SUCCESS;
2538
2539         if (ret_val != IXGBE_SUCCESS)
2540                 return ret_val;
2541
2542         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) {
2543                 /* Configure internal PHY for native SFI */
2544                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
2545                                IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2546                                IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_phy_int);
2547
2548                 if (ret_val != IXGBE_SUCCESS)
2549                         return ret_val;
2550
2551                 if (setup_linear) {
2552                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
2553                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
2554                 } else {
2555                         reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
2556                         reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
2557                 }
2558
2559                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
2560                                 IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
2561                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
2562
2563                 if (ret_val != IXGBE_SUCCESS)
2564                         return ret_val;
2565
2566                 /* Setup XFI/SFI internal link. */
2567                 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed);
2568         } else {
2569                 /* Configure internal PHY for KR/KX. */
2570                 ixgbe_setup_kr_speed_x550em(hw, speed);
2571
2572                 if (hw->phy.addr == 0x0 || hw->phy.addr == 0xFFFF) {
2573                         /* Find Address */
2574                         DEBUGOUT("Invalid NW_MNG_IF_SEL.MDIO_PHY_ADD value\n");
2575                         return IXGBE_ERR_PHY_ADDR_INVALID;
2576                 }
2577
2578                 /* Get external PHY device id */
2579                 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
2580                                        IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
2581
2582                 if (ret_val != IXGBE_SUCCESS)
2583                         return ret_val;
2584
2585                 /* When configuring quad port CS4223, the MAC instance is part
2586                  * of the slice offset.
2587                  */
2588                 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
2589                         slice_offset = (hw->bus.lan_id +
2590                                         (hw->bus.instance_id << 1)) << 12;
2591                 else
2592                         slice_offset = hw->bus.lan_id << 12;
2593
2594                 /* Configure CS4227/CS4223 LINE side to proper mode. */
2595                 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
2596                 if (setup_linear)
2597                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2598                 else
2599                         reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2600                 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
2601                                         IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
2602         }
2603         return ret_val;
2604 }
2605
2606 /**
2607  *  ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
2608  *  @hw: pointer to hardware structure
2609  *
2610  *  iXfI configuration needed for ixgbe_mac_X550EM_x devices.
2611  **/
2612 STATIC s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
2613 {
2614         s32 status;
2615         u32 reg_val;
2616
2617         /* Disable training protocol FSM. */
2618         status = ixgbe_read_iosf_sb_reg_x550(hw,
2619                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2620                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2621         if (status != IXGBE_SUCCESS)
2622                 return status;
2623         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2624         status = ixgbe_write_iosf_sb_reg_x550(hw,
2625                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2626                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2627         if (status != IXGBE_SUCCESS)
2628                 return status;
2629
2630         /* Disable Flex from training TXFFE. */
2631         status = ixgbe_read_iosf_sb_reg_x550(hw,
2632                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2633                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2634         if (status != IXGBE_SUCCESS)
2635                 return status;
2636         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2637         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2638         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2639         status = ixgbe_write_iosf_sb_reg_x550(hw,
2640                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
2641                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2642         if (status != IXGBE_SUCCESS)
2643                 return status;
2644         status = ixgbe_read_iosf_sb_reg_x550(hw,
2645                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2646                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2647         if (status != IXGBE_SUCCESS)
2648                 return status;
2649         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2650         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2651         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2652         status = ixgbe_write_iosf_sb_reg_x550(hw,
2653                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
2654                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2655         if (status != IXGBE_SUCCESS)
2656                 return status;
2657
2658         /* Enable override for coefficients. */
2659         status = ixgbe_read_iosf_sb_reg_x550(hw,
2660                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2661                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2662         if (status != IXGBE_SUCCESS)
2663                 return status;
2664         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2665         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2666         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2667         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2668         status = ixgbe_write_iosf_sb_reg_x550(hw,
2669                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
2670                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2671         return status;
2672 }
2673
2674 /**
2675  *  ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
2676  *  @hw: pointer to hardware structure
2677  *  @speed: the link speed to force
2678  *
2679  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
2680  *  internal and external PHY at a specific speed, without autonegotiation.
2681  **/
2682 STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
2683 {
2684         s32 status;
2685         u32 reg_val;
2686
2687         /* Disable AN and force speed to 10G Serial. */
2688         status = ixgbe_read_iosf_sb_reg_x550(hw,
2689                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2690                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2691         if (status != IXGBE_SUCCESS)
2692                 return status;
2693
2694         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2695         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2696
2697         /* Select forced link speed for internal PHY. */
2698         switch (*speed) {
2699         case IXGBE_LINK_SPEED_10GB_FULL:
2700                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2701                 break;
2702         case IXGBE_LINK_SPEED_1GB_FULL:
2703                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2704                 break;
2705         default:
2706                 /* Other link speeds are not supported by internal KR PHY. */
2707                 return IXGBE_ERR_LINK_SETUP;
2708         }
2709
2710         status = ixgbe_write_iosf_sb_reg_x550(hw,
2711                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2712                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2713         if (status != IXGBE_SUCCESS)
2714                 return status;
2715
2716         /* Additional configuration needed for x550em_x */
2717         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2718                 status = ixgbe_setup_ixfi_x550em_x(hw);
2719                 if (status != IXGBE_SUCCESS)
2720                         return status;
2721         }
2722
2723         /* Toggle port SW reset by AN reset. */
2724         status = ixgbe_read_iosf_sb_reg_x550(hw,
2725                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2726                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2727         if (status != IXGBE_SUCCESS)
2728                 return status;
2729         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
2730         status = ixgbe_write_iosf_sb_reg_x550(hw,
2731                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2732                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2733
2734         return status;
2735 }
2736
2737 /**
2738  * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2739  * @hw: address of hardware structure
2740  * @link_up: address of boolean to indicate link status
2741  *
2742  * Returns error code if unable to get link status.
2743  */
2744 STATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2745 {
2746         u32 ret;
2747         u16 autoneg_status;
2748
2749         *link_up = false;
2750
2751         /* read this twice back to back to indicate current status */
2752         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2753                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2754                                    &autoneg_status);
2755         if (ret != IXGBE_SUCCESS)
2756                 return ret;
2757
2758         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2759                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2760                                    &autoneg_status);
2761         if (ret != IXGBE_SUCCESS)
2762                 return ret;
2763
2764         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2765
2766         return IXGBE_SUCCESS;
2767 }
2768
2769 /**
2770  * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2771  * @hw: point to hardware structure
2772  *
2773  * Configures the link between the integrated KR PHY and the external X557 PHY
2774  * The driver will call this function when it gets a link status change
2775  * interrupt from the X557 PHY. This function configures the link speed
2776  * between the PHYs to match the link speed of the BASE-T link.
2777  *
2778  * A return of a non-zero value indicates an error, and the base driver should
2779  * not report link up.
2780  */
2781 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2782 {
2783         ixgbe_link_speed force_speed;
2784         bool link_up;
2785         u32 status;
2786         u16 speed;
2787
2788         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2789                 return IXGBE_ERR_CONFIG;
2790
2791         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
2792                 /* If link is down, there is no setup necessary so return  */
2793                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2794                 if (status != IXGBE_SUCCESS)
2795                         return status;
2796
2797                 if (!link_up)
2798                         return IXGBE_SUCCESS;
2799
2800                 status = hw->phy.ops.read_reg(hw,
2801                                               IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2802                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2803                                               &speed);
2804                 if (status != IXGBE_SUCCESS)
2805                         return status;
2806
2807                 /* If link is still down - no setup is required so return */
2808                 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2809                 if (status != IXGBE_SUCCESS)
2810                         return status;
2811                 if (!link_up)
2812                         return IXGBE_SUCCESS;
2813
2814                 /* clear everything but the speed and duplex bits */
2815                 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2816
2817                 switch (speed) {
2818                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2819                         force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2820                         break;
2821                 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2822                         force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2823                         break;
2824                 default:
2825                         /* Internal PHY does not support anything else */
2826                         return IXGBE_ERR_INVALID_LINK_SETTINGS;
2827                 }
2828
2829                 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2830         } else {
2831                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2832                         IXGBE_LINK_SPEED_1GB_FULL;
2833                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2834         }
2835 }
2836
2837 /**
2838  *  ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.
2839  *  @hw: pointer to hardware structure
2840  *
2841  *  Configures the integrated KR PHY to use internal loopback mode.
2842  **/
2843 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)
2844 {
2845         s32 status;
2846         u32 reg_val;
2847
2848         /* Disable AN and force speed to 10G Serial. */
2849         status = hw->mac.ops.read_iosf_sb_reg(hw,
2850                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2851                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2852         if (status != IXGBE_SUCCESS)
2853                 return status;
2854         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2855         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2856         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2857         status = hw->mac.ops.write_iosf_sb_reg(hw,
2858                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2859                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2860         if (status != IXGBE_SUCCESS)
2861                 return status;
2862
2863         /* Set near-end loopback clocks. */
2864         status = hw->mac.ops.read_iosf_sb_reg(hw,
2865                       IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2866                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2867         if (status != IXGBE_SUCCESS)
2868                 return status;
2869         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2870         reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2871         status = hw->mac.ops.write_iosf_sb_reg(hw,
2872                        IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),
2873                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2874         if (status != IXGBE_SUCCESS)
2875                 return status;
2876
2877         /* Set loopback enable. */
2878         status = hw->mac.ops.read_iosf_sb_reg(hw,
2879                       IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2880                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2881         if (status != IXGBE_SUCCESS)
2882                 return status;
2883         reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2884         status = hw->mac.ops.write_iosf_sb_reg(hw,
2885                        IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),
2886                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2887         if (status != IXGBE_SUCCESS)
2888                 return status;
2889
2890         /* Training bypass. */
2891         status = hw->mac.ops.read_iosf_sb_reg(hw,
2892                       IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2893                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
2894         if (status != IXGBE_SUCCESS)
2895                 return status;
2896         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2897         status = hw->mac.ops.write_iosf_sb_reg(hw,
2898                        IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
2899                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2900
2901         return status;
2902 }
2903
2904 /**
2905  *  ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
2906  *  assuming that the semaphore is already obtained.
2907  *  @hw: pointer to hardware structure
2908  *  @offset: offset of  word in the EEPROM to read
2909  *  @data: word read from the EEPROM
2910  *
2911  *  Reads a 16 bit word from the EEPROM using the hostif.
2912  **/
2913 s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
2914 {
2915         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2916         struct ixgbe_hic_read_shadow_ram buffer;
2917         s32 status;
2918
2919         DEBUGFUNC("ixgbe_read_ee_hostif_X550");
2920         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2921         buffer.hdr.req.buf_lenh = 0;
2922         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2923         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2924
2925         /* convert offset from words to bytes */
2926         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
2927         /* one word */
2928         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
2929
2930         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2931         if (status)
2932                 return status;
2933
2934         status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
2935                                     IXGBE_HI_COMMAND_TIMEOUT);
2936         if (!status) {
2937                 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
2938                                                   FW_NVM_DATA_OFFSET);
2939         }
2940
2941         hw->mac.ops.release_swfw_sync(hw, mask);
2942         return status;
2943 }
2944
2945 /**
2946  *  ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
2947  *  @hw: pointer to hardware structure
2948  *  @offset: offset of  word in the EEPROM to read
2949  *  @words: number of words
2950  *  @data: word(s) read from the EEPROM
2951  *
2952  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
2953  **/
2954 s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
2955                                      u16 offset, u16 words, u16 *data)
2956 {
2957         const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
2958         struct ixgbe_hic_read_shadow_ram buffer;
2959         u32 current_word = 0;
2960         u16 words_to_read;
2961         s32 status;
2962         u32 i;
2963
2964         DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550");
2965
2966         /* Take semaphore for the entire operation. */
2967         status = hw->mac.ops.acquire_swfw_sync(hw, mask);
2968         if (status) {
2969                 DEBUGOUT("EEPROM read buffer - semaphore failed\n");
2970                 return status;
2971         }
2972         while (words) {
2973                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
2974                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
2975                 else
2976                         words_to_read = words;
2977
2978                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
2979                 buffer.hdr.req.buf_lenh = 0;
2980                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
2981                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
2982
2983                 /* convert offset from words to bytes */
2984                 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);
2985                 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);
2986
2987                 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
2988                                             IXGBE_HI_COMMAND_TIMEOUT);
2989
2990                 if (status) {
2991                         DEBUGOUT("Host interface command failed\n");
2992                         goto out;
2993                 }
2994
2995                 for (i = 0; i < words_to_read; i++) {
2996                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
2997                                   2 * i;
2998                         u32 value = IXGBE_READ_REG(hw, reg);
2999
3000                         data[current_word] = (u16)(value & 0xffff);
3001                         current_word++;
3002                         i++;
3003                         if (i < words_to_read) {
3004                                 value >>= 16;
3005                                 data[current_word] = (u16)(value & 0xffff);
3006                                 current_word++;
3007                         }
3008                 }
3009                 words -= words_to_read;
3010         }
3011
3012 out:
3013         hw->mac.ops.release_swfw_sync(hw, mask);
3014         return status;
3015 }
3016
3017 /**
3018  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3019  *  @hw: pointer to hardware structure
3020  *  @offset: offset of  word in the EEPROM to write
3021  *  @data: word write to the EEPROM
3022  *
3023  *  Write a 16 bit word to the EEPROM using the hostif.
3024  **/
3025 s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
3026                                     u16 data)
3027 {
3028         s32 status;
3029         struct ixgbe_hic_write_shadow_ram buffer;
3030
3031         DEBUGFUNC("ixgbe_write_ee_hostif_data_X550");
3032
3033         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
3034         buffer.hdr.req.buf_lenh = 0;
3035         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
3036         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
3037
3038          /* one word */
3039         buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));
3040         buffer.data = data;
3041         buffer.address = IXGBE_CPU_TO_BE32(offset * 2);
3042
3043         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3044                                               sizeof(buffer),
3045                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3046
3047         return status;
3048 }
3049
3050 /**
3051  *  ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
3052  *  @hw: pointer to hardware structure
3053  *  @offset: offset of  word in the EEPROM to write
3054  *  @data: word write to the EEPROM
3055  *
3056  *  Write a 16 bit word to the EEPROM using the hostif.
3057  **/
3058 s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,
3059                                u16 data)
3060 {
3061         s32 status = IXGBE_SUCCESS;
3062
3063         DEBUGFUNC("ixgbe_write_ee_hostif_X550");
3064
3065         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
3066             IXGBE_SUCCESS) {
3067                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
3068                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3069         } else {
3070                 DEBUGOUT("write ee hostif failed to get semaphore");
3071                 status = IXGBE_ERR_SWFW_SYNC;
3072         }
3073
3074         return status;
3075 }
3076
3077 /**
3078  *  ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
3079  *  @hw: pointer to hardware structure
3080  *  @offset: offset of  word in the EEPROM to write
3081  *  @words: number of words
3082  *  @data: word(s) write to the EEPROM
3083  *
3084  *  Write a 16 bit word(s) to the EEPROM using the hostif.
3085  **/
3086 s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
3087                                       u16 offset, u16 words, u16 *data)
3088 {
3089         s32 status = IXGBE_SUCCESS;
3090         u32 i = 0;
3091
3092         DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550");
3093
3094         /* Take semaphore for the entire operation. */
3095         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3096         if (status != IXGBE_SUCCESS) {
3097                 DEBUGOUT("EEPROM write buffer - semaphore failed\n");
3098                 goto out;
3099         }
3100
3101         for (i = 0; i < words; i++) {
3102                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
3103                                                          data[i]);
3104
3105                 if (status != IXGBE_SUCCESS) {
3106                         DEBUGOUT("Eeprom buffered write failed\n");
3107                         break;
3108                 }
3109         }
3110
3111         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
3112 out:
3113
3114         return status;
3115 }
3116
3117 /**
3118  * ixgbe_checksum_ptr_x550 - Checksum one pointer region
3119  * @hw: pointer to hardware structure
3120  * @ptr: pointer offset in eeprom
3121  * @size: size of section pointed by ptr, if 0 first word will be used as size
3122  * @csum: address of checksum to update
3123  *
3124  * Returns error status for any failure
3125  */
3126 STATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
3127                                    u16 size, u16 *csum, u16 *buffer,
3128                                    u32 buffer_size)
3129 {
3130         u16 buf[256];
3131         s32 status;
3132         u16 length, bufsz, i, start;
3133         u16 *local_buffer;
3134
3135         bufsz = sizeof(buf) / sizeof(buf[0]);
3136
3137         /* Read a chunk at the pointer location */
3138         if (!buffer) {
3139                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
3140                 if (status) {
3141                         DEBUGOUT("Failed to read EEPROM image\n");
3142                         return status;
3143                 }
3144                 local_buffer = buf;
3145         } else {
3146                 if (buffer_size < ptr)
3147                         return  IXGBE_ERR_PARAM;
3148                 local_buffer = &buffer[ptr];
3149         }
3150
3151         if (size) {
3152                 start = 0;
3153                 length = size;
3154         } else {
3155                 start = 1;
3156                 length = local_buffer[0];
3157
3158                 /* Skip pointer section if length is invalid. */
3159                 if (length == 0xFFFF || length == 0 ||
3160                     (ptr + length) >= hw->eeprom.word_size)
3161                         return IXGBE_SUCCESS;
3162         }
3163
3164         if (buffer && ((u32)start + (u32)length > buffer_size))
3165                 return IXGBE_ERR_PARAM;
3166
3167         for (i = start; length; i++, length--) {
3168                 if (i == bufsz && !buffer) {
3169                         ptr += bufsz;
3170                         i = 0;
3171                         if (length < bufsz)
3172                                 bufsz = length;
3173
3174                         /* Read a chunk at the pointer location */
3175                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
3176                                                                   bufsz, buf);
3177                         if (status) {
3178                                 DEBUGOUT("Failed to read EEPROM image\n");
3179                                 return status;
3180                         }
3181                 }
3182                 *csum += local_buffer[i];
3183         }
3184         return IXGBE_SUCCESS;
3185 }
3186
3187 /**
3188  *  ixgbe_calc_checksum_X550 - Calculates and returns the checksum
3189  *  @hw: pointer to hardware structure
3190  *  @buffer: pointer to buffer containing calculated checksum
3191  *  @buffer_size: size of buffer
3192  *
3193  *  Returns a negative error code on error, or the 16-bit checksum
3194  **/
3195 s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)
3196 {
3197         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
3198         u16 *local_buffer;
3199         s32 status;
3200         u16 checksum = 0;
3201         u16 pointer, i, size;
3202
3203         DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550");
3204
3205         hw->eeprom.ops.init_params(hw);
3206
3207         if (!buffer) {
3208                 /* Read pointer area */
3209                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
3210                                                      IXGBE_EEPROM_LAST_WORD + 1,
3211                                                      eeprom_ptrs);
3212                 if (status) {
3213                         DEBUGOUT("Failed to read EEPROM image\n");
3214                         return status;
3215                 }
3216                 local_buffer = eeprom_ptrs;
3217         } else {
3218                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
3219                         return IXGBE_ERR_PARAM;
3220                 local_buffer = buffer;
3221         }
3222
3223         /*
3224          * For X550 hardware include 0x0-0x41 in the checksum, skip the
3225          * checksum word itself
3226          */
3227         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
3228                 if (i != IXGBE_EEPROM_CHECKSUM)
3229                         checksum += local_buffer[i];
3230
3231         /*
3232          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
3233          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
3234          */
3235         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
3236                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
3237                         continue;
3238
3239                 pointer = local_buffer[i];
3240
3241                 /* Skip pointer section if the pointer is invalid. */
3242                 if (pointer == 0xFFFF || pointer == 0 ||
3243                     pointer >= hw->eeprom.word_size)
3244                         continue;
3245
3246                 switch (i) {
3247                 case IXGBE_PCIE_GENERAL_PTR:
3248                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
3249                         break;
3250                 case IXGBE_PCIE_CONFIG0_PTR:
3251                 case IXGBE_PCIE_CONFIG1_PTR:
3252                         size = IXGBE_PCIE_CONFIG_SIZE;
3253                         break;
3254                 default:
3255                         size = 0;
3256                         break;
3257                 }
3258
3259                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
3260                                                 buffer, buffer_size);
3261                 if (status)
3262                         return status;
3263         }
3264
3265         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
3266
3267         return (s32)checksum;
3268 }
3269
3270 /**
3271  *  ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
3272  *  @hw: pointer to hardware structure
3273  *
3274  *  Returns a negative error code on error, or the 16-bit checksum
3275  **/
3276 s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
3277 {
3278         return ixgbe_calc_checksum_X550(hw, NULL, 0);
3279 }
3280
3281 /**
3282  *  ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
3283  *  @hw: pointer to hardware structure
3284  *  @checksum_val: calculated checksum
3285  *
3286  *  Performs checksum calculation and validates the EEPROM checksum.  If the
3287  *  caller does not need checksum_val, the value can be NULL.
3288  **/
3289 s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)
3290 {
3291         s32 status;
3292         u16 checksum;
3293         u16 read_checksum = 0;
3294
3295         DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550");
3296
3297         /* Read the first word from the EEPROM. If this times out or fails, do
3298          * not continue or we could be in for a very long wait while every
3299          * EEPROM read fails
3300          */
3301         status = hw->eeprom.ops.read(hw, 0, &checksum);
3302         if (status) {
3303                 DEBUGOUT("EEPROM read failed\n");
3304                 return status;
3305         }
3306
3307         status = hw->eeprom.ops.calc_checksum(hw);
3308         if (status < 0)
3309                 return status;
3310
3311         checksum = (u16)(status & 0xffff);
3312
3313         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3314                                            &read_checksum);
3315         if (status)
3316                 return status;
3317
3318         /* Verify read checksum from EEPROM is the same as
3319          * calculated checksum
3320          */
3321         if (read_checksum != checksum) {
3322                 status = IXGBE_ERR_EEPROM_CHECKSUM;
3323                 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
3324                              "Invalid EEPROM checksum");
3325         }
3326
3327         /* If the user cares, return the calculated checksum */
3328         if (checksum_val)
3329                 *checksum_val = checksum;
3330
3331         return status;
3332 }
3333
3334 /**
3335  * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
3336  * @hw: pointer to hardware structure
3337  *
3338  * After writing EEPROM to shadow RAM using EEWR register, software calculates
3339  * checksum and updates the EEPROM and instructs the hardware to update
3340  * the flash.
3341  **/
3342 s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
3343 {
3344         s32 status;
3345         u16 checksum = 0;
3346
3347         DEBUGFUNC("ixgbe_update_eeprom_checksum_X550");
3348
3349         /* Read the first word from the EEPROM. If this times out or fails, do
3350          * not continue or we could be in for a very long wait while every
3351          * EEPROM read fails
3352          */
3353         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
3354         if (status) {
3355                 DEBUGOUT("EEPROM read failed\n");
3356                 return status;
3357         }
3358
3359         status = ixgbe_calc_eeprom_checksum_X550(hw);
3360         if (status < 0)
3361                 return status;
3362
3363         checksum = (u16)(status & 0xffff);
3364
3365         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
3366                                             checksum);
3367         if (status)
3368                 return status;
3369
3370         status = ixgbe_update_flash_X550(hw);
3371
3372         return status;
3373 }
3374
3375 /**
3376  *  ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
3377  *  @hw: pointer to hardware structure
3378  *
3379  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
3380  **/
3381 s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
3382 {
3383         s32 status = IXGBE_SUCCESS;
3384         union ixgbe_hic_hdr2 buffer;
3385
3386         DEBUGFUNC("ixgbe_update_flash_X550");
3387
3388         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
3389         buffer.req.buf_lenh = 0;
3390         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
3391         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
3392
3393         status = ixgbe_host_interface_command(hw, (u32 *)&buffer,
3394                                               sizeof(buffer),
3395                                               IXGBE_HI_COMMAND_TIMEOUT, false);
3396
3397         return status;
3398 }
3399
3400 /**
3401  *  ixgbe_get_supported_physical_layer_X550em - Returns physical layer type
3402  *  @hw: pointer to hardware structure
3403  *
3404  *  Determines physical layer capabilities of the current configuration.
3405  **/
3406 u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
3407 {
3408         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
3409         u16 ext_ability = 0;
3410
3411         DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
3412
3413         hw->phy.ops.identify(hw);
3414
3415         switch (hw->phy.type) {
3416         case ixgbe_phy_x550em_kr:
3417                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
3418                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3419                 break;
3420         case ixgbe_phy_x550em_kx4:
3421                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
3422                                  IXGBE_PHYSICAL_LAYER_1000BASE_KX;
3423                 break;
3424         case ixgbe_phy_x550em_ext_t:
3425                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
3426                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
3427                                      &ext_ability);
3428                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
3429                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
3430                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
3431                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
3432                 break;
3433         default:
3434                 break;
3435         }
3436
3437         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)
3438                 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
3439
3440         return physical_layer;
3441 }
3442
3443 /**
3444  * ixgbe_get_bus_info_x550em - Set PCI bus info
3445  * @hw: pointer to hardware structure
3446  *
3447  * Sets bus link width and speed to unknown because X550em is
3448  * not a PCI device.
3449  **/
3450 s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
3451 {
3452
3453         DEBUGFUNC("ixgbe_get_bus_info_x550em");
3454
3455         hw->bus.width = ixgbe_bus_width_unknown;
3456         hw->bus.speed = ixgbe_bus_speed_unknown;
3457
3458         hw->mac.ops.set_lan_id(hw);
3459
3460         return IXGBE_SUCCESS;
3461 }
3462
3463 /**
3464  * ixgbe_disable_rx_x550 - Disable RX unit
3465  *
3466  * Enables the Rx DMA unit for x550
3467  **/
3468 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
3469 {
3470         u32 rxctrl, pfdtxgswc;
3471         s32 status;
3472         struct ixgbe_hic_disable_rxen fw_cmd;
3473
3474         DEBUGFUNC("ixgbe_enable_rx_dma_x550");
3475
3476         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3477         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3478                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3479                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3480                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3481                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3482                         hw->mac.set_lben = true;
3483                 } else {
3484                         hw->mac.set_lben = false;
3485                 }
3486
3487                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
3488                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
3489                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
3490                 fw_cmd.port_number = (u8)hw->bus.lan_id;
3491
3492                 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3493                                         sizeof(struct ixgbe_hic_disable_rxen),
3494                                         IXGBE_HI_COMMAND_TIMEOUT, true);
3495
3496                 /* If we fail - disable RX using register write */
3497                 if (status) {
3498                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3499                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
3500                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3501                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3502                         }
3503                 }
3504         }
3505 }
3506
3507 /**
3508  * ixgbe_enter_lplu_x550em - Transition to low power states
3509  *  @hw: pointer to hardware structure
3510  *
3511  * Configures Low Power Link Up on transition to low power states
3512  * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the
3513  * X557 PHY immediately prior to entering LPLU.
3514  **/
3515 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3516 {
3517         u16 an_10g_cntl_reg, autoneg_reg, speed;
3518         s32 status;
3519         ixgbe_link_speed lcd_speed;
3520         u32 save_autoneg;
3521         bool link_up;
3522
3523         /* SW LPLU not required on later HW revisions. */
3524         if ((hw->mac.type == ixgbe_mac_X550EM_x) &&
3525             (IXGBE_FUSES0_REV_MASK &
3526              IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0))))
3527                 return IXGBE_SUCCESS;
3528
3529         /* If blocked by MNG FW, then don't restart AN */
3530         if (ixgbe_check_reset_blocked(hw))
3531                 return IXGBE_SUCCESS;
3532
3533         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3534         if (status != IXGBE_SUCCESS)
3535                 return status;
3536
3537         status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);
3538
3539         if (status != IXGBE_SUCCESS)
3540                 return status;
3541
3542         /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability
3543          * disabled, then force link down by entering low power mode.
3544          */
3545         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3546             !(hw->wol_enabled || ixgbe_mng_present(hw)))
3547                 return ixgbe_set_copper_phy_power(hw, FALSE);
3548
3549         /* Determine LCD */
3550         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3551
3552         if (status != IXGBE_SUCCESS)
3553                 return status;
3554
3555         /* If no valid LCD link speed, then force link down and exit. */
3556         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3557                 return ixgbe_set_copper_phy_power(hw, FALSE);
3558
3559         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3560                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3561                                       &speed);
3562
3563         if (status != IXGBE_SUCCESS)
3564                 return status;
3565
3566         /* If no link now, speed is invalid so take link down */
3567         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3568         if (status != IXGBE_SUCCESS)
3569                 return ixgbe_set_copper_phy_power(hw, false);
3570
3571         /* clear everything but the speed bits */
3572         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3573
3574         /* If current speed is already LCD, then exit. */
3575         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3576              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3577             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3578              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3579                 return status;
3580
3581         /* Clear AN completed indication */
3582         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3583                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3584                                       &autoneg_reg);
3585
3586         if (status != IXGBE_SUCCESS)
3587                 return status;
3588
3589         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
3590                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3591                              &an_10g_cntl_reg);
3592
3593         if (status != IXGBE_SUCCESS)
3594                 return status;
3595
3596         status = hw->phy.ops.read_reg(hw,
3597                              IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3598                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3599                              &autoneg_reg);
3600
3601         if (status != IXGBE_SUCCESS)
3602                 return status;
3603
3604         save_autoneg = hw->phy.autoneg_advertised;
3605
3606         /* Setup link at least common link speed */
3607         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3608
3609         /* restore autoneg from before setting lplu speed */
3610         hw->phy.autoneg_advertised = save_autoneg;
3611
3612         return status;
3613 }
3614
3615 /**
3616  * ixgbe_get_lcd_x550em - Determine lowest common denominator
3617  *  @hw: pointer to hardware structure
3618  *  @lcd_speed: pointer to lowest common link speed
3619  *
3620  * Determine lowest common link speed with link partner.
3621  **/
3622 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)
3623 {
3624         u16 an_lp_status;
3625         s32 status;
3626         u16 word = hw->eeprom.ctrl_word_3;
3627
3628         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
3629
3630         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
3631                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3632                                       &an_lp_status);
3633
3634         if (status != IXGBE_SUCCESS)
3635                 return status;
3636
3637         /* If link partner advertised 1G, return 1G */
3638         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
3639                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
3640                 return status;
3641         }
3642
3643         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
3644         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
3645             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
3646                 return status;
3647
3648         /* Link partner not capable of lower speeds, return 10G */
3649         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
3650         return status;
3651 }
3652
3653 /**
3654  *  ixgbe_setup_fc_X550em - Set up flow control
3655  *  @hw: pointer to hardware structure
3656  *
3657  *  Called at init time to set up flow control.
3658  **/
3659 s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)
3660 {
3661         s32 ret_val = IXGBE_SUCCESS;
3662         u32 pause, asm_dir, reg_val;
3663
3664         DEBUGFUNC("ixgbe_setup_fc_X550em");
3665
3666         /* Validate the requested mode */
3667         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3668                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3669                         "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3670                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3671                 goto out;
3672         }
3673
3674         /* 10gig parts do not have a word in the EEPROM to determine the
3675          * default flow control setting, so we explicitly set it to full.
3676          */
3677         if (hw->fc.requested_mode == ixgbe_fc_default)
3678                 hw->fc.requested_mode = ixgbe_fc_full;
3679
3680         /* Determine PAUSE and ASM_DIR bits. */
3681         switch (hw->fc.requested_mode) {
3682         case ixgbe_fc_none:
3683                 pause = 0;
3684                 asm_dir = 0;
3685                 break;
3686         case ixgbe_fc_tx_pause:
3687                 pause = 0;
3688                 asm_dir = 1;
3689                 break;
3690         case ixgbe_fc_rx_pause:
3691                 /* Rx Flow control is enabled and Tx Flow control is
3692                  * disabled by software override. Since there really
3693                  * isn't a way to advertise that we are capable of RX
3694                  * Pause ONLY, we will advertise that we support both
3695                  * symmetric and asymmetric Rx PAUSE, as such we fall
3696                  * through to the fc_full statement.  Later, we will
3697                  * disable the adapter's ability to send PAUSE frames.
3698                  */
3699         case ixgbe_fc_full:
3700                 pause = 1;
3701                 asm_dir = 1;
3702                 break;
3703         default:
3704                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3705                         "Flow control param set incorrectly\n");
3706                 ret_val = IXGBE_ERR_CONFIG;
3707                 goto out;
3708         }
3709
3710         switch (hw->device_id) {
3711         case IXGBE_DEV_ID_X550EM_X_KR:
3712         case IXGBE_DEV_ID_X550EM_A_KR:
3713         case IXGBE_DEV_ID_X550EM_A_KR_L:
3714                 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
3715                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3716                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
3717                 if (ret_val != IXGBE_SUCCESS)
3718                         goto out;
3719                 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3720                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3721                 if (pause)
3722                         reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3723                 if (asm_dir)
3724                         reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3725                 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
3726                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3727                                        IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3728
3729                 /* This device does not fully support AN. */
3730                 hw->fc.disable_fc_autoneg = true;
3731                 break;
3732         default:
3733                 break;
3734         }
3735
3736 out:
3737         return ret_val;
3738 }
3739
3740 /**
3741  *  ixgbe_fc_autoneg_x550a - Enable flow control IEEE clause 37
3742  *  @hw: pointer to hardware structure
3743  *
3744  *  Enable flow control according to IEEE clause 37.
3745  **/
3746 void ixgbe_fc_autoneg_x550a(struct ixgbe_hw *hw)
3747 {
3748         u32 link_s1, lp_an_page_low, an_cntl_1;
3749         s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
3750         ixgbe_link_speed speed;
3751         bool link_up;
3752
3753         /* AN should have completed when the cable was plugged in.
3754          * Look for reasons to bail out.  Bail out if:
3755          * - FC autoneg is disabled, or if
3756          * - link is not up.
3757          */
3758         if (hw->fc.disable_fc_autoneg) {
3759                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3760                               "Flow control autoneg is disabled");
3761                 goto out;
3762         }
3763
3764         hw->mac.ops.check_link(hw, &speed, &link_up, false);
3765         if (!link_up) {
3766                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3767                 goto out;
3768         }
3769
3770         /* Check at auto-negotiation has completed */
3771         status = hw->mac.ops.read_iosf_sb_reg(hw,
3772                                       IXGBE_KRM_LINK_S1(hw->bus.lan_id),
3773                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
3774
3775         if (status != IXGBE_SUCCESS ||
3776             (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
3777                 DEBUGOUT("Auto-Negotiation did not complete\n");
3778                 goto out;
3779         }
3780
3781         /* Read the 10g AN autoc and LP ability registers and resolve
3782          * local flow control settings accordingly
3783          */
3784         status = hw->mac.ops.read_iosf_sb_reg(hw,
3785                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3786                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
3787
3788         if (status != IXGBE_SUCCESS) {
3789                 DEBUGOUT("Auto-Negotiation did not complete\n");
3790                 goto out;
3791         }
3792
3793         status = hw->mac.ops.read_iosf_sb_reg(hw,
3794                               IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
3795                               IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
3796
3797         if (status != IXGBE_SUCCESS) {
3798                 DEBUGOUT("Auto-Negotiation did not complete\n");
3799                 goto out;
3800         }
3801
3802         status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
3803                                     IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
3804                                     IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
3805                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3806                                     IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3807
3808 out:
3809         if (status == IXGBE_SUCCESS) {
3810                 hw->fc.fc_was_autonegged = true;
3811         } else {
3812                 hw->fc.fc_was_autonegged = false;
3813                 hw->fc.current_mode = hw->fc.requested_mode;
3814         }
3815 }
3816
3817 /**
3818  *  ixgbe_setup_fc_x550em - Set up flow control
3819  *  @hw: pointer to hardware structure
3820  *
3821  *  Called at init time to set up flow control.
3822  **/
3823 s32 ixgbe_setup_fc_x550a(struct ixgbe_hw *hw)
3824 {
3825         s32 status = IXGBE_SUCCESS;
3826         u32 an_cntl, link_ctrl = 0;
3827
3828         DEBUGFUNC("ixgbe_setup_fc_x550em");
3829
3830         /* Validate the requested mode */
3831         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3832                 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3833                       "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3834                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3835         }
3836
3837         if (hw->fc.requested_mode == ixgbe_fc_default)
3838                 hw->fc.requested_mode = ixgbe_fc_full;
3839
3840         /* Set up the 1G and 10G flow control advertisement registers so the
3841          * HW will be able to do FC autoneg once the cable is plugged in.  If
3842          * we link at 10G, the 1G advertisement is harmless and vice versa.
3843          */
3844         status = hw->mac.ops.read_iosf_sb_reg(hw,
3845                                       IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3846                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3847
3848         if (status != IXGBE_SUCCESS) {
3849                 DEBUGOUT("Auto-Negotiation did not complete\n");
3850                 return status;
3851         }
3852
3853         /* The possible values of fc.requested_mode are:
3854          * 0: Flow control is completely disabled
3855          * 1: Rx flow control is enabled (we can receive pause frames,
3856          *    but not send pause frames).
3857          * 2: Tx flow control is enabled (we can send pause frames but
3858          *    we do not support receiving pause frames).
3859          * 3: Both Rx and Tx flow control (symmetric) are enabled.
3860          * other: Invalid.
3861          */
3862         switch (hw->fc.requested_mode) {
3863         case ixgbe_fc_none:
3864                 /* Flow control completely disabled by software override. */
3865                 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3866                              IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3867                 break;
3868         case ixgbe_fc_tx_pause:
3869                 /* Tx Flow control is enabled, and Rx Flow control is
3870                  * disabled by software override.
3871                  */
3872                 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3873                 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3874                 break;
3875         case ixgbe_fc_rx_pause:
3876                 /* Rx Flow control is enabled and Tx Flow control is
3877                  * disabled by software override. Since there really
3878                  * isn't a way to advertise that we are capable of RX
3879                  * Pause ONLY, we will advertise that we support both
3880                  * symmetric and asymmetric Rx PAUSE, as such we fall
3881                  * through to the fc_full statement.  Later, we will
3882                  * disable the adapter's ability to send PAUSE frames.
3883                  */
3884         case ixgbe_fc_full:
3885                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3886                 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3887                         IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3888                 break;
3889         default:
3890                 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
3891                               "Flow control param set incorrectly\n");
3892                 return IXGBE_ERR_CONFIG;
3893         }
3894
3895         status = hw->mac.ops.write_iosf_sb_reg(hw,
3896                                        IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3897                                        IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3898
3899         /* Restart auto-negotiation. */
3900         status = hw->mac.ops.read_iosf_sb_reg(hw,
3901                                       IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3902                                       IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
3903
3904         if (status != IXGBE_SUCCESS) {
3905                 DEBUGOUT("Auto-Negotiation did not complete\n");
3906                 return status;
3907         }
3908
3909         link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
3910         status = hw->mac.ops.write_iosf_sb_reg(hw,
3911                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
3912                                        IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
3913
3914         return status;
3915 }
3916
3917 /**
3918  * ixgbe_set_mux - Set mux for port 1 access with CS4227
3919  * @hw: pointer to hardware structure
3920  * @state: set mux if 1, clear if 0
3921  */
3922 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3923 {
3924         u32 esdp;
3925
3926         if (!hw->bus.lan_id)
3927                 return;
3928         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3929         if (state)
3930                 esdp |= IXGBE_ESDP_SDP1;
3931         else
3932                 esdp &= ~IXGBE_ESDP_SDP1;
3933         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3934         IXGBE_WRITE_FLUSH(hw);
3935 }
3936
3937 /**
3938  *  ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3939  *  @hw: pointer to hardware structure
3940  *  @mask: Mask to specify which semaphore to acquire
3941  *
3942  *  Acquires the SWFW semaphore and sets the I2C MUX
3943  **/
3944 s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3945 {
3946         s32 status;
3947
3948         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em");
3949
3950         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3951         if (status)
3952                 return status;
3953
3954         if (mask & IXGBE_GSSR_I2C_MASK)
3955                 ixgbe_set_mux(hw, 1);
3956
3957         return IXGBE_SUCCESS;
3958 }
3959
3960 /**
3961  *  ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3962  *  @hw: pointer to hardware structure
3963  *  @mask: Mask to specify which semaphore to release
3964  *
3965  *  Releases the SWFW semaphore and sets the I2C MUX
3966  **/
3967 void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3968 {
3969         DEBUGFUNC("ixgbe_release_swfw_sync_X550em");
3970
3971         if (mask & IXGBE_GSSR_I2C_MASK)
3972                 ixgbe_set_mux(hw, 0);
3973
3974         ixgbe_release_swfw_sync_X540(hw, mask);
3975 }
3976
3977 /**
3978  *  ixgbe_acquire_swfw_sync_X550a - Acquire SWFW semaphore
3979  *  @hw: pointer to hardware structure
3980  *  @mask: Mask to specify which semaphore to acquire
3981  *
3982  *  Acquires the SWFW semaphore and get the shared phy token as needed
3983  */
3984 STATIC s32 ixgbe_acquire_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
3985 {
3986         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3987         int retries = FW_PHY_TOKEN_RETRIES;
3988         s32 status = IXGBE_SUCCESS;
3989
3990         DEBUGFUNC("ixgbe_acquire_swfw_sync_X550a");
3991
3992         while (--retries) {
3993                 status = IXGBE_SUCCESS;
3994                 if (hmask)
3995                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3996                 if (status)
3997                         return status;
3998                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3999                         return IXGBE_SUCCESS;
4000
4001                 status = ixgbe_get_phy_token(hw);
4002                 if (status == IXGBE_SUCCESS)
4003                         return IXGBE_SUCCESS;
4004
4005                 if (hmask)
4006                         ixgbe_release_swfw_sync_X540(hw, hmask);
4007                 if (status != IXGBE_ERR_TOKEN_RETRY)
4008                         return status;
4009                 msec_delay(FW_PHY_TOKEN_DELAY);
4010         }
4011
4012         return status;
4013 }
4014
4015 /**
4016  *  ixgbe_release_swfw_sync_X550a - Release SWFW semaphore
4017  *  @hw: pointer to hardware structure
4018  *  @mask: Mask to specify which semaphore to release
4019  *
4020  *  Releases the SWFW semaphore and puts the shared phy token as needed
4021  */
4022 STATIC void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask)
4023 {
4024         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
4025
4026         DEBUGFUNC("ixgbe_release_swfw_sync_X550a");
4027
4028         if (mask & IXGBE_GSSR_TOKEN_SM)
4029                 ixgbe_put_phy_token(hw);
4030
4031         if (hmask)
4032                 ixgbe_release_swfw_sync_X540(hw, hmask);
4033 }
4034
4035 /**
4036  *  ixgbe_read_phy_reg_x550a  - Reads specified PHY register
4037  *  @hw: pointer to hardware structure
4038  *  @reg_addr: 32 bit address of PHY register to read
4039  *  @phy_data: Pointer to read data from PHY register
4040  *
4041  *  Reads a value from a specified PHY register using the SWFW lock and PHY
4042  *  Token. The PHY Token is needed since the MDIO is shared between to MAC
4043  *  instances.
4044  **/
4045 s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4046                              u32 device_type, u16 *phy_data)
4047 {
4048         s32 status;
4049         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4050
4051         DEBUGFUNC("ixgbe_read_phy_reg_x550a");
4052
4053         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
4054                 return IXGBE_ERR_SWFW_SYNC;
4055
4056         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
4057
4058         hw->mac.ops.release_swfw_sync(hw, mask);
4059
4060         return status;
4061 }
4062
4063 /**
4064  *  ixgbe_write_phy_reg_x550a - Writes specified PHY register
4065  *  @hw: pointer to hardware structure
4066  *  @reg_addr: 32 bit PHY register to write
4067  *  @device_type: 5 bit device type
4068  *  @phy_data: Data to write to the PHY register
4069  *
4070  *  Writes a value to specified PHY register using the SWFW lock and PHY Token.
4071  *  The PHY Token is needed since the MDIO is shared between to MAC instances.
4072  **/
4073 s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
4074                               u32 device_type, u16 phy_data)
4075 {
4076         s32 status;
4077         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
4078
4079         DEBUGFUNC("ixgbe_write_phy_reg_x550a");
4080
4081         if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) {
4082                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
4083                                                  phy_data);
4084                 hw->mac.ops.release_swfw_sync(hw, mask);
4085         } else {
4086                 status = IXGBE_ERR_SWFW_SYNC;
4087         }
4088
4089         return status;
4090 }
4091
4092 /**
4093  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
4094  * @hw: pointer to hardware structure
4095  *
4096  * Handle external Base T PHY interrupt. If high temperature
4097  * failure alarm then return error, else if link status change
4098  * then setup internal/external PHY link
4099  *
4100  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
4101  * failure alarm, else return PHY access status.
4102  */
4103 s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
4104 {
4105         bool lsc;
4106         u32 status;
4107
4108         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
4109
4110         if (status != IXGBE_SUCCESS)
4111                 return status;
4112
4113         if (lsc)
4114                 return ixgbe_setup_internal_phy(hw);
4115
4116         return IXGBE_SUCCESS;
4117 }
4118
4119 /**
4120  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
4121  * @hw: pointer to hardware structure
4122  * @speed: new link speed
4123  * @autoneg_wait_to_complete: true when waiting for completion is needed
4124  *
4125  * Setup internal/external PHY link speed based on link speed, then set
4126  * external PHY auto advertised link speed.
4127  *
4128  * Returns error status for any failure
4129  **/
4130 s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
4131                                   ixgbe_link_speed speed,
4132                                   bool autoneg_wait_to_complete)
4133 {
4134         s32 status;
4135         ixgbe_link_speed force_speed;
4136
4137         DEBUGFUNC("ixgbe_setup_mac_link_t_X550em");
4138
4139         /* Setup internal/external PHY link speed to iXFI (10G), unless
4140          * only 1G is auto advertised then setup KX link.
4141          */
4142         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4143                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
4144         else
4145                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
4146
4147         /* If internal link mode is XFI, then setup XFI internal link. */
4148         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
4149                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
4150
4151                 if (status != IXGBE_SUCCESS)
4152                         return status;
4153         }
4154
4155         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
4156 }
4157
4158 /**
4159  * ixgbe_check_link_t_X550em - Determine link and speed status
4160  * @hw: pointer to hardware structure
4161  * @speed: pointer to link speed
4162  * @link_up: true when link is up
4163  * @link_up_wait_to_complete: bool used to wait for link up or not
4164  *
4165  * Check that both the MAC and X557 external PHY have link.
4166  **/
4167 s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4168                               bool *link_up, bool link_up_wait_to_complete)
4169 {
4170         u32 status;
4171         u16 autoneg_status;
4172
4173         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
4174                 return IXGBE_ERR_CONFIG;
4175
4176         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
4177                                               link_up_wait_to_complete);
4178
4179         /* If check link fails or MAC link is not up, then return */
4180         if (status != IXGBE_SUCCESS || !(*link_up))
4181                 return status;
4182
4183         /* MAC link is up, so check external PHY link.
4184          * Read this twice back to back to indicate current status.
4185          */
4186         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4187                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4188                                       &autoneg_status);
4189
4190         if (status != IXGBE_SUCCESS)
4191                 return status;
4192
4193         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
4194                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
4195                                       &autoneg_status);
4196
4197         if (status != IXGBE_SUCCESS)
4198                 return status;
4199
4200         /* If external PHY link is not up, then indicate link not up */
4201         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
4202                 *link_up = false;
4203
4204         return IXGBE_SUCCESS;
4205 }
4206
4207 /**
4208  *  ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
4209  *  @hw: pointer to hardware structure
4210  **/
4211 s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
4212 {
4213         s32 status;
4214
4215         status = ixgbe_reset_phy_generic(hw);
4216
4217         if (status != IXGBE_SUCCESS)
4218                 return status;
4219
4220         /* Configure Link Status Alarm and Temperature Threshold interrupts */
4221         return ixgbe_enable_lasi_ext_t_x550em(hw);
4222 }
4223
4224 /**
4225  *  ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.
4226  *  @hw: pointer to hardware structure
4227  *  @led_idx: led number to turn on
4228  **/
4229 s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4230 {
4231         u16 phy_data;
4232
4233         DEBUGFUNC("ixgbe_led_on_t_X550em");
4234
4235         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4236                 return IXGBE_ERR_PARAM;
4237
4238         /* To turn on the LED, set mode to ON. */
4239         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4240                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4241         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
4242         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4243                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4244
4245         return IXGBE_SUCCESS;
4246 }
4247
4248 /**
4249  *  ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.
4250  *  @hw: pointer to hardware structure
4251  *  @led_idx: led number to turn off
4252  **/
4253 s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)
4254 {
4255         u16 phy_data;
4256
4257         DEBUGFUNC("ixgbe_led_off_t_X550em");
4258
4259         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
4260                 return IXGBE_ERR_PARAM;
4261
4262         /* To turn on the LED, set mode to ON. */
4263         ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4264                            IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
4265         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
4266         ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
4267                             IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
4268
4269         return IXGBE_SUCCESS;
4270 }
4271