drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153 #define IXGBE_VTEICR_MASK                      0x07
 154
 155 enum ixgbevf_xcast_modes {
 156         IXGBEVF_XCAST_MODE_NONE = 0,
 157         IXGBEVF_XCAST_MODE_MULTI,
 158         IXGBEVF_XCAST_MODE_ALLMULTI,
 159 };
 160
 161 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 162 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 163
 164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 191                                              uint16_t queue_id,
 192                                              uint8_t stat_idx,
 193                                              uint8_t is_rx);
 194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 195                                struct rte_eth_dev_info *dev_info);
 196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 198                                  struct rte_eth_dev_info *dev_info);
 199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200
 201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 202                 uint16_t vlan_id, int on);
 203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 204                                enum rte_vlan_type vlan_type,
 205                                uint16_t tpid_id);
 206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, bool on);
 208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 209                 int on);
 210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 215
 216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 219                                struct rte_eth_fc_conf *fc_conf);
 220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 223                 struct rte_eth_pfc_conf *pfc_conf);
 224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 225                         struct rte_eth_rss_reta_entry64 *reta_conf,
 226                         uint16_t reta_size);
 227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 236                 void *param);
 237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 239                 uint32_t index, uint32_t pool);
 240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 242                                            struct ether_addr *mac_addr);
 243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 255                 struct rte_eth_stats *stats);
 256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 258                 uint16_t vlan_id, int on);
 259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 260                 uint16_t queue, int on);
 261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 264                                             uint16_t queue_id);
 265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 266                                              uint16_t queue_id);
 267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 268                                  uint8_t queue, uint8_t msix_vector);
 269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 272
 273 /* For Eth VMDQ APIs support */
 274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 275                 ether_addr * mac_addr, uint8_t on);
 276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 277 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 278                 uint16_t rx_mask, uint8_t on);
 279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 282                 uint64_t pool_mask, uint8_t vlan_on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 299                 uint16_t tx_rate, uint64_t q_msk);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter,
 309                         bool add);
 310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter);
 312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 313                         enum rte_filter_op filter_op,
 314                         void *arg);
 315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter,
 321                         bool add);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ethertype_filter *filter,
 329                         bool add);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 373                                           void *param);
 374
 375 static int ixgbe_dev_l2_tunnel_eth_type_conf
 376         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 377 static int ixgbe_dev_l2_tunnel_offload_set
 378         (struct rte_eth_dev *dev,
 379          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 380          uint32_t mask,
 381          uint8_t en);
 382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 383                                              enum rte_filter_op filter_op,
 384                                              void *arg);
 385
 386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432
 433 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 434 #include "rte_pci_dev_ids.h"
 435
 436 { .vendor_id = 0, /* sentinel */ },
 437 };
 438
 439
 440 /*
 441  * The set of PCI devices this driver supports (for 82599 VF)
 442  */
 443 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 444
 445 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 446 #include "rte_pci_dev_ids.h"
 447 { .vendor_id = 0, /* sentinel */ },
 448
 449 };
 450
 451 static const struct rte_eth_desc_lim rx_desc_lim = {
 452         .nb_max = IXGBE_MAX_RING_DESC,
 453         .nb_min = IXGBE_MIN_RING_DESC,
 454         .nb_align = IXGBE_RXD_ALIGN,
 455 };
 456
 457 static const struct rte_eth_desc_lim tx_desc_lim = {
 458         .nb_max = IXGBE_MAX_RING_DESC,
 459         .nb_min = IXGBE_MIN_RING_DESC,
 460         .nb_align = IXGBE_TXD_ALIGN,
 461 };
 462
 463 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 464         .dev_configure        = ixgbe_dev_configure,
 465         .dev_start            = ixgbe_dev_start,
 466         .dev_stop             = ixgbe_dev_stop,
 467         .dev_set_link_up    = ixgbe_dev_set_link_up,
 468         .dev_set_link_down  = ixgbe_dev_set_link_down,
 469         .dev_close            = ixgbe_dev_close,
 470         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 471         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 472         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 473         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 474         .link_update          = ixgbe_dev_link_update,
 475         .stats_get            = ixgbe_dev_stats_get,
 476         .xstats_get           = ixgbe_dev_xstats_get,
 477         .stats_reset          = ixgbe_dev_stats_reset,
 478         .xstats_reset         = ixgbe_dev_xstats_reset,
 479         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 480         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 481         .dev_infos_get        = ixgbe_dev_info_get,
 482         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 483         .mtu_set              = ixgbe_dev_mtu_set,
 484         .vlan_filter_set      = ixgbe_vlan_filter_set,
 485         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 486         .vlan_offload_set     = ixgbe_vlan_offload_set,
 487         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 488         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 489         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 490         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 491         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 492         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 493         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 494         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 495         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 496         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 497         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 498         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 499         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 500         .dev_led_on           = ixgbe_dev_led_on,
 501         .dev_led_off          = ixgbe_dev_led_off,
 502         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 503         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 504         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 505         .mac_addr_add         = ixgbe_add_rar,
 506         .mac_addr_remove      = ixgbe_remove_rar,
 507         .mac_addr_set         = ixgbe_set_default_mac_addr,
 508         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 509         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 510         .mirror_rule_set      = ixgbe_mirror_rule_set,
 511         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 512         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 513         .set_vf_rx            = ixgbe_set_pool_rx,
 514         .set_vf_tx            = ixgbe_set_pool_tx,
 515         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 516         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 517         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 518         .reta_update          = ixgbe_dev_rss_reta_update,
 519         .reta_query           = ixgbe_dev_rss_reta_query,
 520 #ifdef RTE_NIC_BYPASS
 521         .bypass_init          = ixgbe_bypass_init,
 522         .bypass_state_set     = ixgbe_bypass_state_store,
 523         .bypass_state_show    = ixgbe_bypass_state_show,
 524         .bypass_event_set     = ixgbe_bypass_event_store,
 525         .bypass_event_show    = ixgbe_bypass_event_show,
 526         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 527         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 528         .bypass_ver_show      = ixgbe_bypass_ver_show,
 529         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 530 #endif /* RTE_NIC_BYPASS */
 531         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 532         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 533         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 534         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 535         .rxq_info_get         = ixgbe_rxq_info_get,
 536         .txq_info_get         = ixgbe_txq_info_get,
 537         .timesync_enable      = ixgbe_timesync_enable,
 538         .timesync_disable     = ixgbe_timesync_disable,
 539         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 540         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 541         .get_reg_length       = ixgbe_get_reg_length,
 542         .get_reg              = ixgbe_get_regs,
 543         .get_eeprom_length    = ixgbe_get_eeprom_length,
 544         .get_eeprom           = ixgbe_get_eeprom,
 545         .set_eeprom           = ixgbe_set_eeprom,
 546         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 547         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 548         .timesync_read_time   = ixgbe_timesync_read_time,
 549         .timesync_write_time  = ixgbe_timesync_write_time,
 550         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 551         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 552         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 553         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 554 };
 555
 556 /*
 557  * dev_ops for virtual function, bare necessities for basic vf
 558  * operation have been implemented
 559  */
 560 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 561         .dev_configure        = ixgbevf_dev_configure,
 562         .dev_start            = ixgbevf_dev_start,
 563         .dev_stop             = ixgbevf_dev_stop,
 564         .link_update          = ixgbe_dev_link_update,
 565         .stats_get            = ixgbevf_dev_stats_get,
 566         .xstats_get           = ixgbevf_dev_xstats_get,
 567         .stats_reset          = ixgbevf_dev_stats_reset,
 568         .xstats_reset         = ixgbevf_dev_stats_reset,
 569         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 570         .dev_close            = ixgbevf_dev_close,
 571         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 572         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 573         .dev_infos_get        = ixgbevf_dev_info_get,
 574         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 575         .mtu_set              = ixgbevf_dev_set_mtu,
 576         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 577         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 578         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 579         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 580         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 581         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 582         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 583         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 584         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 585         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 586         .mac_addr_add         = ixgbevf_add_mac_addr,
 587         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 588         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 589         .rxq_info_get         = ixgbe_rxq_info_get,
 590         .txq_info_get         = ixgbe_txq_info_get,
 591         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 592         .get_reg_length       = ixgbevf_get_reg_length,
 593         .get_reg              = ixgbevf_get_regs,
 594         .reta_update          = ixgbe_dev_rss_reta_update,
 595         .reta_query           = ixgbe_dev_rss_reta_query,
 596         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 597         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 598 };
 599
 600 /* store statistics names and its offset in stats structure */
 601 struct rte_ixgbe_xstats_name_off {
 602         char name[RTE_ETH_XSTATS_NAME_SIZE];
 603         unsigned offset;
 604 };
 605
 606 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 607         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 608         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 609         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 610         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 611         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 612         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 613         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 614         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 615         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 616         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 617         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 618         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 619         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 620         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 621         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 622                 prc1023)},
 623         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 624                 prc1522)},
 625         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 626         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 627         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 628         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 629         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 630         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 631         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 632         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 633         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 634         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 635         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 636         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 637         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 638         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 639         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 640         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 641         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 642                 ptc1023)},
 643         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 644                 ptc1522)},
 645         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 646         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 647         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 648         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 649
 650         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 651                 fdirustat_add)},
 652         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 653                 fdirustat_remove)},
 654         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 655                 fdirfstat_fadd)},
 656         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 657                 fdirfstat_fremove)},
 658         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 659                 fdirmatch)},
 660         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 661                 fdirmiss)},
 662
 663         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 664         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 665         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 666                 fclast)},
 667         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 668         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 669         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 670         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 671         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 672                 fcoe_noddp)},
 673         {"rx_fcoe_no_direct_data_placement_ext_buff",
 674                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 675
 676         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 677                 lxontxc)},
 678         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 679                 lxonrxc)},
 680         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 681                 lxofftxc)},
 682         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 683                 lxoffrxc)},
 684         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 685 };
 686
 687 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 688                            sizeof(rte_ixgbe_stats_strings[0]))
 689
 690 /* Per-queue statistics */
 691 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 692         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 693         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 694         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 695         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 696 };
 697
 698 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 699                            sizeof(rte_ixgbe_rxq_strings[0]))
 700 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 701
 702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 703         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 704         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 705         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 pxon2offc)},
 707 };
 708
 709 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 710                            sizeof(rte_ixgbe_txq_strings[0]))
 711 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 712
 713 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 714         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 715 };
 716
 717 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 718                 sizeof(rte_ixgbevf_stats_strings[0]))
 719
 720 /**
 721  * Atomically reads the link status information from global
 722  * structure rte_eth_dev.
 723  *
 724  * @param dev
 725  *   - Pointer to the structure rte_eth_dev to read from.
 726  *   - Pointer to the buffer to be saved with the link status.
 727  *
 728  * @return
 729  *   - On success, zero.
 730  *   - On failure, negative value.
 731  */
 732 static inline int
 733 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 734                                 struct rte_eth_link *link)
 735 {
 736         struct rte_eth_link *dst = link;
 737         struct rte_eth_link *src = &(dev->data->dev_link);
 738
 739         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 740                                         *(uint64_t *)src) == 0)
 741                 return -1;
 742
 743         return 0;
 744 }
 745
 746 /**
 747  * Atomically writes the link status information into global
 748  * structure rte_eth_dev.
 749  *
 750  * @param dev
 751  *   - Pointer to the structure rte_eth_dev to read from.
 752  *   - Pointer to the buffer to be saved with the link status.
 753  *
 754  * @return
 755  *   - On success, zero.
 756  *   - On failure, negative value.
 757  */
 758 static inline int
 759 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 760                                 struct rte_eth_link *link)
 761 {
 762         struct rte_eth_link *dst = &(dev->data->dev_link);
 763         struct rte_eth_link *src = link;
 764
 765         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 766                                         *(uint64_t *)src) == 0)
 767                 return -1;
 768
 769         return 0;
 770 }
 771
 772 /*
 773  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 774  */
 775 static inline int
 776 ixgbe_is_sfp(struct ixgbe_hw *hw)
 777 {
 778         switch (hw->phy.type) {
 779         case ixgbe_phy_sfp_avago:
 780         case ixgbe_phy_sfp_ftl:
 781         case ixgbe_phy_sfp_intel:
 782         case ixgbe_phy_sfp_unknown:
 783         case ixgbe_phy_sfp_passive_tyco:
 784         case ixgbe_phy_sfp_passive_unknown:
 785                 return 1;
 786         default:
 787                 return 0;
 788         }
 789 }
 790
 791 static inline int32_t
 792 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 793 {
 794         uint32_t ctrl_ext;
 795         int32_t status;
 796
 797         status = ixgbe_reset_hw(hw);
 798
 799         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 800         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 801         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 802         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 803         IXGBE_WRITE_FLUSH(hw);
 804
 805         return status;
 806 }
 807
 808 static inline void
 809 ixgbe_enable_intr(struct rte_eth_dev *dev)
 810 {
 811         struct ixgbe_interrupt *intr =
 812                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 813         struct ixgbe_hw *hw =
 814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815
 816         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 817         IXGBE_WRITE_FLUSH(hw);
 818 }
 819
 820 /*
 821  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 822  */
 823 static void
 824 ixgbe_disable_intr(struct ixgbe_hw *hw)
 825 {
 826         PMD_INIT_FUNC_TRACE();
 827
 828         if (hw->mac.type == ixgbe_mac_82598EB) {
 829                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 830         } else {
 831                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 832                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 833                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 834         }
 835         IXGBE_WRITE_FLUSH(hw);
 836 }
 837
 838 /*
 839  * This function resets queue statistics mapping registers.
 840  * From Niantic datasheet, Initialization of Statistics section:
 841  * "...if software requires the queue counters, the RQSMR and TQSM registers
 842  * must be re-programmed following a device reset.
 843  */
 844 static void
 845 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 846 {
 847         uint32_t i;
 848
 849         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 850                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 851                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 852         }
 853 }
 854
 855
 856 static int
 857 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 858                                   uint16_t queue_id,
 859                                   uint8_t stat_idx,
 860                                   uint8_t is_rx)
 861 {
 862 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 863 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 864 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 865
 866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 867         struct ixgbe_stat_mapping_registers *stat_mappings =
 868                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 869         uint32_t qsmr_mask = 0;
 870         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 871         uint32_t q_map;
 872         uint8_t n, offset;
 873
 874         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 875                 (hw->mac.type != ixgbe_mac_X540) &&
 876                 (hw->mac.type != ixgbe_mac_X550) &&
 877                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 878                 (hw->mac.type != ixgbe_mac_X550EM_a))
 879                 return -ENOSYS;
 880
 881         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 882                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 883                      queue_id, stat_idx);
 884
 885         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 886         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 887                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 888                 return -EIO;
 889         }
 890         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 891
 892         /* Now clear any previous stat_idx set */
 893         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 894         if (!is_rx)
 895                 stat_mappings->tqsm[n] &= ~clearing_mask;
 896         else
 897                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 898
 899         q_map = (uint32_t)stat_idx;
 900         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 901         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 902         if (!is_rx)
 903                 stat_mappings->tqsm[n] |= qsmr_mask;
 904         else
 905                 stat_mappings->rqsmr[n] |= qsmr_mask;
 906
 907         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 908                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 909                      queue_id, stat_idx);
 910         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 911                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 912
 913         /* Now write the mapping in the appropriate register */
 914         if (is_rx) {
 915                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 916                              stat_mappings->rqsmr[n], n);
 917                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 918         } else {
 919                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 920                              stat_mappings->tqsm[n], n);
 921                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 922         }
 923         return 0;
 924 }
 925
 926 static void
 927 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 928 {
 929         struct ixgbe_stat_mapping_registers *stat_mappings =
 930                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932         int i;
 933
 934         /* write whatever was in stat mapping table to the NIC */
 935         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 936                 /* rx */
 937                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 938
 939                 /* tx */
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 941         }
 942 }
 943
 944 static void
 945 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 946 {
 947         uint8_t i;
 948         struct ixgbe_dcb_tc_config *tc;
 949         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 950
 951         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 952         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 953         for (i = 0; i < dcb_max_tc; i++) {
 954                 tc = &dcb_config->tc_config[i];
 955                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 956                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 957                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 958                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 959                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 960                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 961                 tc->pfc = ixgbe_dcb_pfc_disabled;
 962         }
 963
 964         /* Initialize default user to priority mapping, UPx->TC0 */
 965         tc = &dcb_config->tc_config[0];
 966         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 967         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 968         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 969                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 970                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 971         }
 972         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 973         dcb_config->pfc_mode_enable = false;
 974         dcb_config->vt_mode = true;
 975         dcb_config->round_robin_enable = false;
 976         /* support all DCB capabilities in 82599 */
 977         dcb_config->support.capabilities = 0xFF;
 978
 979         /*we only support 4 Tcs for X540, X550 */
 980         if (hw->mac.type == ixgbe_mac_X540 ||
 981                 hw->mac.type == ixgbe_mac_X550 ||
 982                 hw->mac.type == ixgbe_mac_X550EM_x ||
 983                 hw->mac.type == ixgbe_mac_X550EM_a) {
 984                 dcb_config->num_tcs.pg_tcs = 4;
 985                 dcb_config->num_tcs.pfc_tcs = 4;
 986         }
 987 }
 988
 989 /*
 990  * Ensure that all locks are released before first NVM or PHY access
 991  */
 992 static void
 993 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 994 {
 995         uint16_t mask;
 996
 997         /*
 998          * Phy lock should not fail in this early stage. If this is the case,
 999          * it is due to an improper exit of the application.
1000          * So force the release of the faulty lock. Release of common lock
1001          * is done automatically by swfw_sync function.
1002          */
1003         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1004         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1005                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1006         }
1007         ixgbe_release_swfw_semaphore(hw, mask);
1008
1009         /*
1010          * These ones are more tricky since they are common to all ports; but
1011          * swfw_sync retries last long enough (1s) to be almost sure that if
1012          * lock can not be taken it is due to an improper lock of the
1013          * semaphore.
1014          */
1015         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1016         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1017                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1018         }
1019         ixgbe_release_swfw_semaphore(hw, mask);
1020 }
1021
1022 /*
1023  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1024  * It returns 0 on success.
1025  */
1026 static int
1027 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1028 {
1029         struct rte_pci_device *pci_dev;
1030         struct ixgbe_hw *hw =
1031                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1032         struct ixgbe_vfta *shadow_vfta =
1033                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1034         struct ixgbe_hwstrip *hwstrip =
1035                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1036         struct ixgbe_dcb_config *dcb_config =
1037                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1038         struct ixgbe_filter_info *filter_info =
1039                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1040         uint32_t ctrl_ext;
1041         uint16_t csum;
1042         int diag, i;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1047         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1048         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1049
1050         /*
1051          * For secondary processes, we don't initialise any further as primary
1052          * has already done this work. Only check we don't need a different
1053          * RX and TX function.
1054          */
1055         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1056                 struct ixgbe_tx_queue *txq;
1057                 /* TX queue function in primary, set by last queue initialized
1058                  * Tx queue may not initialized by primary process
1059                  */
1060                 if (eth_dev->data->tx_queues) {
1061                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1062                         ixgbe_set_tx_function(eth_dev, txq);
1063                 } else {
1064                         /* Use default TX function if we get here */
1065                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1066                                      "Using default TX function.");
1067                 }
1068
1069                 ixgbe_set_rx_function(eth_dev);
1070
1071                 return 0;
1072         }
1073         pci_dev = eth_dev->pci_dev;
1074
1075         rte_eth_copy_pci_info(eth_dev, pci_dev);
1076
1077         /* Vendor and Device ID need to be set before init of shared code */
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->vendor_id = pci_dev->id.vendor_id;
1080         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1081         hw->allow_unsupported_sfp = 1;
1082
1083         /* Initialize the shared code (base driver) */
1084 #ifdef RTE_NIC_BYPASS
1085         diag = ixgbe_bypass_init_shared_code(hw);
1086 #else
1087         diag = ixgbe_init_shared_code(hw);
1088 #endif /* RTE_NIC_BYPASS */
1089
1090         if (diag != IXGBE_SUCCESS) {
1091                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1092                 return -EIO;
1093         }
1094
1095         /* pick up the PCI bus settings for reporting later */
1096         ixgbe_get_bus_info(hw);
1097
1098         /* Unlock any pending hardware semaphore */
1099         ixgbe_swfw_lock_reset(hw);
1100
1101         /* Initialize DCB configuration*/
1102         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1103         ixgbe_dcb_init(hw, dcb_config);
1104         /* Get Hardware Flow Control setting */
1105         hw->fc.requested_mode = ixgbe_fc_full;
1106         hw->fc.current_mode = ixgbe_fc_full;
1107         hw->fc.pause_time = IXGBE_FC_PAUSE;
1108         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1109                 hw->fc.low_water[i] = IXGBE_FC_LO;
1110                 hw->fc.high_water[i] = IXGBE_FC_HI;
1111         }
1112         hw->fc.send_xon = 1;
1113
1114         /* Make sure we have a good EEPROM before we read from it */
1115         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1118                 return -EIO;
1119         }
1120
1121 #ifdef RTE_NIC_BYPASS
1122         diag = ixgbe_bypass_init_hw(hw);
1123 #else
1124         diag = ixgbe_init_hw(hw);
1125 #endif /* RTE_NIC_BYPASS */
1126
1127         /*
1128          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1129          * is called too soon after the kernel driver unbinding/binding occurs.
1130          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1131          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1132          * also called. See ixgbe_identify_phy_82599(). The reason for the
1133          * failure is not known, and only occuts when virtualisation features
1134          * are disabled in the bios. A delay of 100ms  was found to be enough by
1135          * trial-and-error, and is doubled to be safe.
1136          */
1137         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1138                 rte_delay_ms(200);
1139                 diag = ixgbe_init_hw(hw);
1140         }
1141
1142         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1143                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1144                              "LOM.  Please be aware there may be issues associated "
1145                              "with your hardware.");
1146                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1147                              "please contact your Intel or hardware representative "
1148                              "who provided you with this hardware.");
1149         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1150                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1151         if (diag) {
1152                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1153                 return -EIO;
1154         }
1155
1156         /* Reset the hw statistics */
1157         ixgbe_dev_stats_reset(eth_dev);
1158
1159         /* disable interrupt */
1160         ixgbe_disable_intr(hw);
1161
1162         /* reset mappings for queue statistics hw counters*/
1163         ixgbe_reset_qstat_mappings(hw);
1164
1165         /* Allocate memory for storing MAC addresses */
1166         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                                                hw->mac.num_rar_entries, 0);
1168         if (eth_dev->data->mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to allocate %u bytes needed to store "
1171                              "MAC addresses",
1172                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1173                 return -ENOMEM;
1174         }
1175         /* Copy the permanent MAC address */
1176         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1177                         &eth_dev->data->mac_addrs[0]);
1178
1179         /* Allocate memory for storing hash filter MAC addresses */
1180         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1181                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1182         if (eth_dev->data->hash_mac_addrs == NULL) {
1183                 PMD_INIT_LOG(ERR,
1184                              "Failed to allocate %d bytes needed to store MAC addresses",
1185                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1186                 return -ENOMEM;
1187         }
1188
1189         /* initialize the vfta */
1190         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1191
1192         /* initialize the hw strip bitmap*/
1193         memset(hwstrip, 0, sizeof(*hwstrip));
1194
1195         /* initialize PF if max_vfs not zero */
1196         ixgbe_pf_host_init(eth_dev);
1197
1198         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1199         /* let hardware know driver is loaded */
1200         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1201         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1202         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1203         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1204         IXGBE_WRITE_FLUSH(hw);
1205
1206         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1207                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1208                              (int) hw->mac.type, (int) hw->phy.type,
1209                              (int) hw->phy.sfp_type);
1210         else
1211                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1212                              (int) hw->mac.type, (int) hw->phy.type);
1213
1214         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1215                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1216                      pci_dev->id.device_id);
1217
1218         rte_intr_callback_register(&pci_dev->intr_handle,
1219                                    ixgbe_dev_interrupt_handler,
1220                                    (void *)eth_dev);
1221
1222         /* enable uio/vfio intr/eventfd mapping */
1223         rte_intr_enable(&pci_dev->intr_handle);
1224
1225         /* enable support intr */
1226         ixgbe_enable_intr(eth_dev);
1227
1228         /* initialize 5tuple filter list */
1229         TAILQ_INIT(&filter_info->fivetuple_list);
1230         memset(filter_info->fivetuple_mask, 0,
1231                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1232
1233         return 0;
1234 }
1235
1236 static int
1237 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1238 {
1239         struct rte_pci_device *pci_dev;
1240         struct ixgbe_hw *hw;
1241
1242         PMD_INIT_FUNC_TRACE();
1243
1244         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1245                 return -EPERM;
1246
1247         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1248         pci_dev = eth_dev->pci_dev;
1249
1250         if (hw->adapter_stopped == 0)
1251                 ixgbe_dev_close(eth_dev);
1252
1253         eth_dev->dev_ops = NULL;
1254         eth_dev->rx_pkt_burst = NULL;
1255         eth_dev->tx_pkt_burst = NULL;
1256
1257         /* Unlock any pending hardware semaphore */
1258         ixgbe_swfw_lock_reset(hw);
1259
1260         /* disable uio intr before callback unregister */
1261         rte_intr_disable(&(pci_dev->intr_handle));
1262         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1263                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1264
1265         /* uninitialize PF if max_vfs not zero */
1266         ixgbe_pf_host_uninit(eth_dev);
1267
1268         rte_free(eth_dev->data->mac_addrs);
1269         eth_dev->data->mac_addrs = NULL;
1270
1271         rte_free(eth_dev->data->hash_mac_addrs);
1272         eth_dev->data->hash_mac_addrs = NULL;
1273
1274         return 0;
1275 }
1276
1277 /*
1278  * Negotiate mailbox API version with the PF.
1279  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1280  * Then we try to negotiate starting with the most recent one.
1281  * If all negotiation attempts fail, then we will proceed with
1282  * the default one (ixgbe_mbox_api_10).
1283  */
1284 static void
1285 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1286 {
1287         int32_t i;
1288
1289         /* start with highest supported, proceed down */
1290         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1291                 ixgbe_mbox_api_12,
1292                 ixgbe_mbox_api_11,
1293                 ixgbe_mbox_api_10,
1294         };
1295
1296         for (i = 0;
1297                         i != RTE_DIM(sup_ver) &&
1298                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1299                         i++)
1300                 ;
1301 }
1302
1303 static void
1304 generate_random_mac_addr(struct ether_addr *mac_addr)
1305 {
1306         uint64_t random;
1307
1308         /* Set Organizationally Unique Identifier (OUI) prefix. */
1309         mac_addr->addr_bytes[0] = 0x00;
1310         mac_addr->addr_bytes[1] = 0x09;
1311         mac_addr->addr_bytes[2] = 0xC0;
1312         /* Force indication of locally assigned MAC address. */
1313         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1314         /* Generate the last 3 bytes of the MAC address with a random number. */
1315         random = rte_rand();
1316         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1317 }
1318
1319 /*
1320  * Virtual Function device init
1321  */
1322 static int
1323 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1324 {
1325         int diag;
1326         uint32_t tc, tcs;
1327         struct rte_pci_device *pci_dev;
1328         struct ixgbe_hw *hw =
1329                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1330         struct ixgbe_vfta *shadow_vfta =
1331                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1332         struct ixgbe_hwstrip *hwstrip =
1333                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1334         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1335
1336         PMD_INIT_FUNC_TRACE();
1337
1338         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1339         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1340         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1341
1342         /* for secondary processes, we don't initialise any further as primary
1343          * has already done this work. Only check we don't need a different
1344          * RX function
1345          */
1346         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1347                 struct ixgbe_tx_queue *txq;
1348                 /* TX queue function in primary, set by last queue initialized
1349                  * Tx queue may not initialized by primary process
1350                  */
1351                 if (eth_dev->data->tx_queues) {
1352                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1353                         ixgbe_set_tx_function(eth_dev, txq);
1354                 } else {
1355                         /* Use default TX function if we get here */
1356                         PMD_INIT_LOG(NOTICE,
1357                                      "No TX queues configured yet. Using default TX function.");
1358                 }
1359
1360                 ixgbe_set_rx_function(eth_dev);
1361
1362                 return 0;
1363         }
1364
1365         pci_dev = eth_dev->pci_dev;
1366
1367         rte_eth_copy_pci_info(eth_dev, pci_dev);
1368
1369         hw->device_id = pci_dev->id.device_id;
1370         hw->vendor_id = pci_dev->id.vendor_id;
1371         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1372
1373         /* initialize the vfta */
1374         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1375
1376         /* initialize the hw strip bitmap*/
1377         memset(hwstrip, 0, sizeof(*hwstrip));
1378
1379         /* Initialize the shared code (base driver) */
1380         diag = ixgbe_init_shared_code(hw);
1381         if (diag != IXGBE_SUCCESS) {
1382                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1383                 return -EIO;
1384         }
1385
1386         /* init_mailbox_params */
1387         hw->mbx.ops.init_params(hw);
1388
1389         /* Reset the hw statistics */
1390         ixgbevf_dev_stats_reset(eth_dev);
1391
1392         /* Disable the interrupts for VF */
1393         ixgbevf_intr_disable(hw);
1394
1395         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1396         diag = hw->mac.ops.reset_hw(hw);
1397
1398         /*
1399          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1400          * the underlying PF driver has not assigned a MAC address to the VF.
1401          * In this case, assign a random MAC address.
1402          */
1403         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1404                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1405                 return diag;
1406         }
1407
1408         /* negotiate mailbox API version to use with the PF. */
1409         ixgbevf_negotiate_api(hw);
1410
1411         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1412         ixgbevf_get_queues(hw, &tcs, &tc);
1413
1414         /* Allocate memory for storing MAC addresses */
1415         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1416                                                hw->mac.num_rar_entries, 0);
1417         if (eth_dev->data->mac_addrs == NULL) {
1418                 PMD_INIT_LOG(ERR,
1419                              "Failed to allocate %u bytes needed to store "
1420                              "MAC addresses",
1421                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1422                 return -ENOMEM;
1423         }
1424
1425         /* Generate a random MAC address, if none was assigned by PF. */
1426         if (is_zero_ether_addr(perm_addr)) {
1427                 generate_random_mac_addr(perm_addr);
1428                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1429                 if (diag) {
1430                         rte_free(eth_dev->data->mac_addrs);
1431                         eth_dev->data->mac_addrs = NULL;
1432                         return diag;
1433                 }
1434                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1435                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1436                              "%02x:%02x:%02x:%02x:%02x:%02x",
1437                              perm_addr->addr_bytes[0],
1438                              perm_addr->addr_bytes[1],
1439                              perm_addr->addr_bytes[2],
1440                              perm_addr->addr_bytes[3],
1441                              perm_addr->addr_bytes[4],
1442                              perm_addr->addr_bytes[5]);
1443         }
1444
1445         /* Copy the permanent MAC address */
1446         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1447
1448         /* reset the hardware with the new settings */
1449         diag = hw->mac.ops.start_hw(hw);
1450         switch (diag) {
1451         case  0:
1452                 break;
1453
1454         default:
1455                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1456                 return -EIO;
1457         }
1458
1459         rte_intr_callback_register(&pci_dev->intr_handle,
1460                                    ixgbevf_dev_interrupt_handler,
1461                                    (void *)eth_dev);
1462         rte_intr_enable(&pci_dev->intr_handle);
1463         ixgbevf_intr_enable(hw);
1464
1465         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1466                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1467                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1468
1469         return 0;
1470 }
1471
1472 /* Virtual Function device uninit */
1473
1474 static int
1475 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1476 {
1477         struct ixgbe_hw *hw;
1478         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1479
1480         PMD_INIT_FUNC_TRACE();
1481
1482         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1483                 return -EPERM;
1484
1485         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1486
1487         if (hw->adapter_stopped == 0)
1488                 ixgbevf_dev_close(eth_dev);
1489
1490         eth_dev->dev_ops = NULL;
1491         eth_dev->rx_pkt_burst = NULL;
1492         eth_dev->tx_pkt_burst = NULL;
1493
1494         /* Disable the interrupts for VF */
1495         ixgbevf_intr_disable(hw);
1496
1497         rte_free(eth_dev->data->mac_addrs);
1498         eth_dev->data->mac_addrs = NULL;
1499
1500         rte_intr_disable(&pci_dev->intr_handle);
1501         rte_intr_callback_unregister(&pci_dev->intr_handle,
1502                                      ixgbevf_dev_interrupt_handler,
1503                                      (void *)eth_dev);
1504
1505         return 0;
1506 }
1507
1508 static struct eth_driver rte_ixgbe_pmd = {
1509         .pci_drv = {
1510                 .name = "rte_ixgbe_pmd",
1511                 .id_table = pci_id_ixgbe_map,
1512                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1513                         RTE_PCI_DRV_DETACHABLE,
1514         },
1515         .eth_dev_init = eth_ixgbe_dev_init,
1516         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1517         .dev_private_size = sizeof(struct ixgbe_adapter),
1518 };
1519
1520 /*
1521  * virtual function driver struct
1522  */
1523 static struct eth_driver rte_ixgbevf_pmd = {
1524         .pci_drv = {
1525                 .name = "rte_ixgbevf_pmd",
1526                 .id_table = pci_id_ixgbevf_map,
1527                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1528         },
1529         .eth_dev_init = eth_ixgbevf_dev_init,
1530         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1531         .dev_private_size = sizeof(struct ixgbe_adapter),
1532 };
1533
1534 /*
1535  * Driver initialization routine.
1536  * Invoked once at EAL init time.
1537  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1538  */
1539 static int
1540 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1541 {
1542         PMD_INIT_FUNC_TRACE();
1543
1544         rte_eth_driver_register(&rte_ixgbe_pmd);
1545         return 0;
1546 }
1547
1548 /*
1549  * VF Driver initialization routine.
1550  * Invoked one at EAL init time.
1551  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1552  */
1553 static int
1554 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1555 {
1556         PMD_INIT_FUNC_TRACE();
1557
1558         rte_eth_driver_register(&rte_ixgbevf_pmd);
1559         return 0;
1560 }
1561
1562 static int
1563 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1564 {
1565         struct ixgbe_hw *hw =
1566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         struct ixgbe_vfta *shadow_vfta =
1568                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1569         uint32_t vfta;
1570         uint32_t vid_idx;
1571         uint32_t vid_bit;
1572
1573         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1574         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1575         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1576         if (on)
1577                 vfta |= vid_bit;
1578         else
1579                 vfta &= ~vid_bit;
1580         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1581
1582         /* update local VFTA copy */
1583         shadow_vfta->vfta[vid_idx] = vfta;
1584
1585         return 0;
1586 }
1587
1588 static void
1589 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1590 {
1591         if (on)
1592                 ixgbe_vlan_hw_strip_enable(dev, queue);
1593         else
1594                 ixgbe_vlan_hw_strip_disable(dev, queue);
1595 }
1596
1597 static int
1598 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1599                     enum rte_vlan_type vlan_type,
1600                     uint16_t tpid)
1601 {
1602         struct ixgbe_hw *hw =
1603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         int ret = 0;
1605         uint32_t reg;
1606         uint32_t qinq;
1607
1608         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1609         qinq &= IXGBE_DMATXCTL_GDV;
1610
1611         switch (vlan_type) {
1612         case ETH_VLAN_TYPE_INNER:
1613                 if (qinq) {
1614                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1615                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1616                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1617                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1618                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1619                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1620                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1621                 } else {
1622                         ret = -ENOTSUP;
1623                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1624                                     " by single VLAN");
1625                 }
1626                 break;
1627         case ETH_VLAN_TYPE_OUTER:
1628                 if (qinq) {
1629                         /* Only the high 16-bits is valid */
1630                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1631                                         IXGBE_EXVET_VET_EXT_SHIFT);
1632                 } else {
1633                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1634                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1635                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1636                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1637                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1638                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1639                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1640                 }
1641
1642                 break;
1643         default:
1644                 ret = -EINVAL;
1645                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1646                 break;
1647         }
1648
1649         return ret;
1650 }
1651
1652 void
1653 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1654 {
1655         struct ixgbe_hw *hw =
1656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t vlnctrl;
1658
1659         PMD_INIT_FUNC_TRACE();
1660
1661         /* Filter Table Disable */
1662         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1664
1665         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1666 }
1667
1668 void
1669 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         struct ixgbe_vfta *shadow_vfta =
1674                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1675         uint32_t vlnctrl;
1676         uint16_t i;
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         /* Filter Table Enable */
1681         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1682         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1683         vlnctrl |= IXGBE_VLNCTRL_VFE;
1684
1685         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1686
1687         /* write whatever is in local vfta copy */
1688         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1689                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1690 }
1691
1692 static void
1693 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1694 {
1695         struct ixgbe_hwstrip *hwstrip =
1696                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1697         struct ixgbe_rx_queue *rxq;
1698
1699         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1700                 return;
1701
1702         if (on)
1703                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1704         else
1705                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1706
1707         if (queue >= dev->data->nb_rx_queues)
1708                 return;
1709
1710         rxq = dev->data->rx_queues[queue];
1711
1712         if (on)
1713                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1714         else
1715                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1716 }
1717
1718 static void
1719 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1720 {
1721         struct ixgbe_hw *hw =
1722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         uint32_t ctrl;
1724
1725         PMD_INIT_FUNC_TRACE();
1726
1727         if (hw->mac.type == ixgbe_mac_82598EB) {
1728                 /* No queue level support */
1729                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1730                 return;
1731         }
1732
1733         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1734         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1735         ctrl &= ~IXGBE_RXDCTL_VME;
1736         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1737
1738         /* record those setting for HW strip per queue */
1739         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1740 }
1741
1742 static void
1743 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1744 {
1745         struct ixgbe_hw *hw =
1746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747         uint32_t ctrl;
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         if (hw->mac.type == ixgbe_mac_82598EB) {
1752                 /* No queue level supported */
1753                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1754                 return;
1755         }
1756
1757         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1758         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1759         ctrl |= IXGBE_RXDCTL_VME;
1760         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1761
1762         /* record those setting for HW strip per queue */
1763         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1764 }
1765
1766 void
1767 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1768 {
1769         struct ixgbe_hw *hw =
1770                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         uint32_t ctrl;
1772         uint16_t i;
1773
1774         PMD_INIT_FUNC_TRACE();
1775
1776         if (hw->mac.type == ixgbe_mac_82598EB) {
1777                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1778                 ctrl &= ~IXGBE_VLNCTRL_VME;
1779                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1780         } else {
1781                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1782                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1783                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1784                         ctrl &= ~IXGBE_RXDCTL_VME;
1785                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1786
1787                         /* record those setting for HW strip per queue */
1788                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1789                 }
1790         }
1791 }
1792
1793 void
1794 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1795 {
1796         struct ixgbe_hw *hw =
1797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798         uint32_t ctrl;
1799         uint16_t i;
1800
1801         PMD_INIT_FUNC_TRACE();
1802
1803         if (hw->mac.type == ixgbe_mac_82598EB) {
1804                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1805                 ctrl |= IXGBE_VLNCTRL_VME;
1806                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1807         } else {
1808                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1809                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1810                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1811                         ctrl |= IXGBE_RXDCTL_VME;
1812                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1813
1814                         /* record those setting for HW strip per queue */
1815                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1816                 }
1817         }
1818 }
1819
1820 static void
1821 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1822 {
1823         struct ixgbe_hw *hw =
1824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         uint32_t ctrl;
1826
1827         PMD_INIT_FUNC_TRACE();
1828
1829         /* DMATXCTRL: Geric Double VLAN Disable */
1830         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1831         ctrl &= ~IXGBE_DMATXCTL_GDV;
1832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1833
1834         /* CTRL_EXT: Global Double VLAN Disable */
1835         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1836         ctrl &= ~IXGBE_EXTENDED_VLAN;
1837         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1838
1839 }
1840
1841 static void
1842 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1843 {
1844         struct ixgbe_hw *hw =
1845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         uint32_t ctrl;
1847
1848         PMD_INIT_FUNC_TRACE();
1849
1850         /* DMATXCTRL: Geric Double VLAN Enable */
1851         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1852         ctrl |= IXGBE_DMATXCTL_GDV;
1853         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1854
1855         /* CTRL_EXT: Global Double VLAN Enable */
1856         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1857         ctrl |= IXGBE_EXTENDED_VLAN;
1858         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1859
1860         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1861         if (hw->mac.type == ixgbe_mac_X550 ||
1862             hw->mac.type == ixgbe_mac_X550EM_x ||
1863             hw->mac.type == ixgbe_mac_X550EM_a) {
1864                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1865                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1866                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1867         }
1868
1869         /*
1870          * VET EXT field in the EXVET register = 0x8100 by default
1871          * So no need to change. Same to VT field of DMATXCTL register
1872          */
1873 }
1874
1875 static void
1876 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1877 {
1878         if (mask & ETH_VLAN_STRIP_MASK) {
1879                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1880                         ixgbe_vlan_hw_strip_enable_all(dev);
1881                 else
1882                         ixgbe_vlan_hw_strip_disable_all(dev);
1883         }
1884
1885         if (mask & ETH_VLAN_FILTER_MASK) {
1886                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1887                         ixgbe_vlan_hw_filter_enable(dev);
1888                 else
1889                         ixgbe_vlan_hw_filter_disable(dev);
1890         }
1891
1892         if (mask & ETH_VLAN_EXTEND_MASK) {
1893                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1894                         ixgbe_vlan_hw_extend_enable(dev);
1895                 else
1896                         ixgbe_vlan_hw_extend_disable(dev);
1897         }
1898 }
1899
1900 static void
1901 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1902 {
1903         struct ixgbe_hw *hw =
1904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1906         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907
1908         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1909         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1910 }
1911
1912 static int
1913 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1914 {
1915         switch (nb_rx_q) {
1916         case 1:
1917         case 2:
1918                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1919                 break;
1920         case 4:
1921                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1922                 break;
1923         default:
1924                 return -EINVAL;
1925         }
1926
1927         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1928         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1929
1930         return 0;
1931 }
1932
1933 static int
1934 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1935 {
1936         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1939         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1940
1941         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1942                 /* check multi-queue mode */
1943                 switch (dev_conf->rxmode.mq_mode) {
1944                 case ETH_MQ_RX_VMDQ_DCB:
1945                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1946                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1947                         PMD_INIT_LOG(ERR, "SRIOV active,"
1948                                         " unsupported mq_mode rx %d.",
1949                                         dev_conf->rxmode.mq_mode);
1950                         return -EINVAL;
1951                 case ETH_MQ_RX_RSS:
1952                 case ETH_MQ_RX_VMDQ_RSS:
1953                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1954                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1955                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1956                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1957                                                 " invalid queue number"
1958                                                 " for VMDQ RSS, allowed"
1959                                                 " value are 1, 2 or 4.");
1960                                         return -EINVAL;
1961                                 }
1962                         break;
1963                 case ETH_MQ_RX_VMDQ_ONLY:
1964                 case ETH_MQ_RX_NONE:
1965                         /* if nothing mq mode configure, use default scheme */
1966                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1967                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1968                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1969                         break;
1970                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1971                         /* SRIOV only works in VMDq enable mode */
1972                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1973                                         " wrong mq_mode rx %d.",
1974                                         dev_conf->rxmode.mq_mode);
1975                         return -EINVAL;
1976                 }
1977
1978                 switch (dev_conf->txmode.mq_mode) {
1979                 case ETH_MQ_TX_VMDQ_DCB:
1980                         /* DCB VMDQ in SRIOV mode, not implement yet */
1981                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1982                                         " unsupported VMDQ mq_mode tx %d.",
1983                                         dev_conf->txmode.mq_mode);
1984                         return -EINVAL;
1985                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1986                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1987                         break;
1988                 }
1989
1990                 /* check valid queue number */
1991                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1992                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1993                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1995                                         " must be less than or equal to %d.",
1996                                         nb_rx_q, nb_tx_q,
1997                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1998                         return -EINVAL;
1999                 }
2000         } else {
2001                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2002                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2003                                           " not supported.");
2004                         return -EINVAL;
2005                 }
2006                 /* check configuration for vmdb+dcb mode */
2007                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2008                         const struct rte_eth_vmdq_dcb_conf *conf;
2009
2010                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2011                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2012                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2013                                 return -EINVAL;
2014                         }
2015                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2016                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2017                                conf->nb_queue_pools == ETH_32_POOLS)) {
2018                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2019                                                 " nb_queue_pools must be %d or %d.",
2020                                                 ETH_16_POOLS, ETH_32_POOLS);
2021                                 return -EINVAL;
2022                         }
2023                 }
2024                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2025                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2026
2027                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2028                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2029                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2030                                 return -EINVAL;
2031                         }
2032                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2033                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2034                                conf->nb_queue_pools == ETH_32_POOLS)) {
2035                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2036                                                 " nb_queue_pools != %d and"
2037                                                 " nb_queue_pools != %d.",
2038                                                 ETH_16_POOLS, ETH_32_POOLS);
2039                                 return -EINVAL;
2040                         }
2041                 }
2042
2043                 /* For DCB mode check our configuration before we go further */
2044                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2045                         const struct rte_eth_dcb_rx_conf *conf;
2046
2047                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2048                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2049                                                  IXGBE_DCB_NB_QUEUES);
2050                                 return -EINVAL;
2051                         }
2052                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2053                         if (!(conf->nb_tcs == ETH_4_TCS ||
2054                                conf->nb_tcs == ETH_8_TCS)) {
2055                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2056                                                 " and nb_tcs != %d.",
2057                                                 ETH_4_TCS, ETH_8_TCS);
2058                                 return -EINVAL;
2059                         }
2060                 }
2061
2062                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2063                         const struct rte_eth_dcb_tx_conf *conf;
2064
2065                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2066                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2067                                                  IXGBE_DCB_NB_QUEUES);
2068                                 return -EINVAL;
2069                         }
2070                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2071                         if (!(conf->nb_tcs == ETH_4_TCS ||
2072                                conf->nb_tcs == ETH_8_TCS)) {
2073                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2074                                                 " and nb_tcs != %d.",
2075                                                 ETH_4_TCS, ETH_8_TCS);
2076                                 return -EINVAL;
2077                         }
2078                 }
2079
2080                 /*
2081                  * When DCB/VT is off, maximum number of queues changes,
2082                  * except for 82598EB, which remains constant.
2083                  */
2084                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2085                                 hw->mac.type != ixgbe_mac_82598EB) {
2086                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2087                                 PMD_INIT_LOG(ERR,
2088                                              "Neither VT nor DCB are enabled, "
2089                                              "nb_tx_q > %d.",
2090                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2091                                 return -EINVAL;
2092                         }
2093                 }
2094         }
2095         return 0;
2096 }
2097
2098 static int
2099 ixgbe_dev_configure(struct rte_eth_dev *dev)
2100 {
2101         struct ixgbe_interrupt *intr =
2102                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2103         struct ixgbe_adapter *adapter =
2104                 (struct ixgbe_adapter *)dev->data->dev_private;
2105         int ret;
2106
2107         PMD_INIT_FUNC_TRACE();
2108         /* multipe queue mode checking */
2109         ret  = ixgbe_check_mq_mode(dev);
2110         if (ret != 0) {
2111                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2112                             ret);
2113                 return ret;
2114         }
2115
2116         /* set flag to update link status after init */
2117         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2118
2119         /*
2120          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2121          * allocation or vector Rx preconditions we will reset it.
2122          */
2123         adapter->rx_bulk_alloc_allowed = true;
2124         adapter->rx_vec_allowed = true;
2125
2126         return 0;
2127 }
2128
2129 static void
2130 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2131 {
2132         struct ixgbe_hw *hw =
2133                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct ixgbe_interrupt *intr =
2135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2136         uint32_t gpie;
2137
2138         /* only set up it on X550EM_X */
2139         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2140                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2141                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2142                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2143                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2144                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2145         }
2146 }
2147
2148 /*
2149  * Configure device link speed and setup link.
2150  * It returns 0 on success.
2151  */
2152 static int
2153 ixgbe_dev_start(struct rte_eth_dev *dev)
2154 {
2155         struct ixgbe_hw *hw =
2156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         struct ixgbe_vf_info *vfinfo =
2158                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2159         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2160         uint32_t intr_vector = 0;
2161         int err, link_up = 0, negotiate = 0;
2162         uint32_t speed = 0;
2163         int mask = 0;
2164         int status;
2165         uint16_t vf, idx;
2166         uint32_t *link_speeds;
2167
2168         PMD_INIT_FUNC_TRACE();
2169
2170         /* IXGBE devices don't support:
2171         *    - half duplex (checked afterwards for valid speeds)
2172         *    - fixed speed: TODO implement
2173         */
2174         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2175                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2176                              dev->data->port_id);
2177                 return -EINVAL;
2178         }
2179
2180         /* disable uio/vfio intr/eventfd mapping */
2181         rte_intr_disable(intr_handle);
2182
2183         /* stop adapter */
2184         hw->adapter_stopped = 0;
2185         ixgbe_stop_adapter(hw);
2186
2187         /* reinitialize adapter
2188          * this calls reset and start
2189          */
2190         status = ixgbe_pf_reset_hw(hw);
2191         if (status != 0)
2192                 return -1;
2193         hw->mac.ops.start_hw(hw);
2194         hw->mac.get_link_status = true;
2195
2196         /* configure PF module if SRIOV enabled */
2197         ixgbe_pf_host_configure(dev);
2198
2199         ixgbe_dev_phy_intr_setup(dev);
2200
2201         /* check and configure queue intr-vector mapping */
2202         if ((rte_intr_cap_multiple(intr_handle) ||
2203              !RTE_ETH_DEV_SRIOV(dev).active) &&
2204             dev->data->dev_conf.intr_conf.rxq != 0) {
2205                 intr_vector = dev->data->nb_rx_queues;
2206                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2207                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2208                                         IXGBE_MAX_INTR_QUEUE_NUM);
2209                         return -ENOTSUP;
2210                 }
2211                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2212                         return -1;
2213         }
2214
2215         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2216                 intr_handle->intr_vec =
2217                         rte_zmalloc("intr_vec",
2218                                     dev->data->nb_rx_queues * sizeof(int), 0);
2219                 if (intr_handle->intr_vec == NULL) {
2220                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2221                                      " intr_vec\n", dev->data->nb_rx_queues);
2222                         return -ENOMEM;
2223                 }
2224         }
2225
2226         /* confiugre msix for sleep until rx interrupt */
2227         ixgbe_configure_msix(dev);
2228
2229         /* initialize transmission unit */
2230         ixgbe_dev_tx_init(dev);
2231
2232         /* This can fail when allocating mbufs for descriptor rings */
2233         err = ixgbe_dev_rx_init(dev);
2234         if (err) {
2235                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2236                 goto error;
2237         }
2238
2239         err = ixgbe_dev_rxtx_start(dev);
2240         if (err < 0) {
2241                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2242                 goto error;
2243         }
2244
2245         /* Skip link setup if loopback mode is enabled for 82599. */
2246         if (hw->mac.type == ixgbe_mac_82599EB &&
2247                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2248                 goto skip_link_setup;
2249
2250         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2251                 err = hw->mac.ops.setup_sfp(hw);
2252                 if (err)
2253                         goto error;
2254         }
2255
2256         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2257                 /* Turn on the copper */
2258                 ixgbe_set_phy_power(hw, true);
2259         } else {
2260                 /* Turn on the laser */
2261                 ixgbe_enable_tx_laser(hw);
2262         }
2263
2264         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2265         if (err)
2266                 goto error;
2267         dev->data->dev_link.link_status = link_up;
2268
2269         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2270         if (err)
2271                 goto error;
2272
2273         link_speeds = &dev->data->dev_conf.link_speeds;
2274         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2275                         ETH_LINK_SPEED_10G)) {
2276                 PMD_INIT_LOG(ERR, "Invalid link setting");
2277                 goto error;
2278         }
2279
2280         speed = 0x0;
2281         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2282                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2283                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2284                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2285         } else {
2286                 if (*link_speeds & ETH_LINK_SPEED_10G)
2287                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2288                 if (*link_speeds & ETH_LINK_SPEED_1G)
2289                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2290                 if (*link_speeds & ETH_LINK_SPEED_100M)
2291                         speed |= IXGBE_LINK_SPEED_100_FULL;
2292         }
2293
2294         err = ixgbe_setup_link(hw, speed, link_up);
2295         if (err)
2296                 goto error;
2297
2298 skip_link_setup:
2299
2300         if (rte_intr_allow_others(intr_handle)) {
2301                 /* check if lsc interrupt is enabled */
2302                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2303                         ixgbe_dev_lsc_interrupt_setup(dev);
2304         } else {
2305                 rte_intr_callback_unregister(intr_handle,
2306                                              ixgbe_dev_interrupt_handler,
2307                                              (void *)dev);
2308                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2309                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2310                                      " no intr multiplex\n");
2311         }
2312
2313         /* check if rxq interrupt is enabled */
2314         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2315             rte_intr_dp_is_en(intr_handle))
2316                 ixgbe_dev_rxq_interrupt_setup(dev);
2317
2318         /* enable uio/vfio intr/eventfd mapping */
2319         rte_intr_enable(intr_handle);
2320
2321         /* resume enabled intr since hw reset */
2322         ixgbe_enable_intr(dev);
2323
2324         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2325                 ETH_VLAN_EXTEND_MASK;
2326         ixgbe_vlan_offload_set(dev, mask);
2327
2328         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2329                 /* Enable vlan filtering for VMDq */
2330                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2331         }
2332
2333         /* Configure DCB hw */
2334         ixgbe_configure_dcb(dev);
2335
2336         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2337                 err = ixgbe_fdir_configure(dev);
2338                 if (err)
2339                         goto error;
2340         }
2341
2342         /* Restore vf rate limit */
2343         if (vfinfo != NULL) {
2344                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2345                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2346                                 if (vfinfo[vf].tx_rate[idx] != 0)
2347                                         ixgbe_set_vf_rate_limit(dev, vf,
2348                                                 vfinfo[vf].tx_rate[idx],
2349                                                 1 << idx);
2350         }
2351
2352         ixgbe_restore_statistics_mapping(dev);
2353
2354         return 0;
2355
2356 error:
2357         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2358         ixgbe_dev_clear_queues(dev);
2359         return -EIO;
2360 }
2361
2362 /*
2363  * Stop device: disable rx and tx functions to allow for reconfiguring.
2364  */
2365 static void
2366 ixgbe_dev_stop(struct rte_eth_dev *dev)
2367 {
2368         struct rte_eth_link link;
2369         struct ixgbe_hw *hw =
2370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         struct ixgbe_vf_info *vfinfo =
2372                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2373         struct ixgbe_filter_info *filter_info =
2374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2375         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2376         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2377         int vf;
2378
2379         PMD_INIT_FUNC_TRACE();
2380
2381         /* disable interrupts */
2382         ixgbe_disable_intr(hw);
2383
2384         /* reset the NIC */
2385         ixgbe_pf_reset_hw(hw);
2386         hw->adapter_stopped = 0;
2387
2388         /* stop adapter */
2389         ixgbe_stop_adapter(hw);
2390
2391         for (vf = 0; vfinfo != NULL &&
2392                      vf < dev->pci_dev->max_vfs; vf++)
2393                 vfinfo[vf].clear_to_send = false;
2394
2395         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2396                 /* Turn off the copper */
2397                 ixgbe_set_phy_power(hw, false);
2398         } else {
2399                 /* Turn off the laser */
2400                 ixgbe_disable_tx_laser(hw);
2401         }
2402
2403         ixgbe_dev_clear_queues(dev);
2404
2405         /* Clear stored conf */
2406         dev->data->scattered_rx = 0;
2407         dev->data->lro = 0;
2408
2409         /* Clear recorded link status */
2410         memset(&link, 0, sizeof(link));
2411         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2412
2413         /* Remove all ntuple filters of the device */
2414         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2415              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2416                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2417                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2418                              p_5tuple, entries);
2419                 rte_free(p_5tuple);
2420         }
2421         memset(filter_info->fivetuple_mask, 0,
2422                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2423
2424         if (!rte_intr_allow_others(intr_handle))
2425                 /* resume to the default handler */
2426                 rte_intr_callback_register(intr_handle,
2427                                            ixgbe_dev_interrupt_handler,
2428                                            (void *)dev);
2429
2430         /* Clean datapath event and queue/vec mapping */
2431         rte_intr_efd_disable(intr_handle);
2432         if (intr_handle->intr_vec != NULL) {
2433                 rte_free(intr_handle->intr_vec);
2434                 intr_handle->intr_vec = NULL;
2435         }
2436 }
2437
2438 /*
2439  * Set device link up: enable tx.
2440  */
2441 static int
2442 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2443 {
2444         struct ixgbe_hw *hw =
2445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         if (hw->mac.type == ixgbe_mac_82599EB) {
2447 #ifdef RTE_NIC_BYPASS
2448                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2449                         /* Not suported in bypass mode */
2450                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2451                                      "by device id 0x%x", hw->device_id);
2452                         return -ENOTSUP;
2453                 }
2454 #endif
2455         }
2456
2457         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2458                 /* Turn on the copper */
2459                 ixgbe_set_phy_power(hw, true);
2460         } else {
2461                 /* Turn on the laser */
2462                 ixgbe_enable_tx_laser(hw);
2463         }
2464
2465         return 0;
2466 }
2467
2468 /*
2469  * Set device link down: disable tx.
2470  */
2471 static int
2472 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2473 {
2474         struct ixgbe_hw *hw =
2475                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         if (hw->mac.type == ixgbe_mac_82599EB) {
2477 #ifdef RTE_NIC_BYPASS
2478                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2479                         /* Not suported in bypass mode */
2480                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2481                                      "by device id 0x%x", hw->device_id);
2482                         return -ENOTSUP;
2483                 }
2484 #endif
2485         }
2486
2487         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2488                 /* Turn off the copper */
2489                 ixgbe_set_phy_power(hw, false);
2490         } else {
2491                 /* Turn off the laser */
2492                 ixgbe_disable_tx_laser(hw);
2493         }
2494
2495         return 0;
2496 }
2497
2498 /*
2499  * Reest and stop device.
2500  */
2501 static void
2502 ixgbe_dev_close(struct rte_eth_dev *dev)
2503 {
2504         struct ixgbe_hw *hw =
2505                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506
2507         PMD_INIT_FUNC_TRACE();
2508
2509         ixgbe_pf_reset_hw(hw);
2510
2511         ixgbe_dev_stop(dev);
2512         hw->adapter_stopped = 1;
2513
2514         ixgbe_dev_free_queues(dev);
2515
2516         ixgbe_disable_pcie_master(hw);
2517
2518         /* reprogram the RAR[0] in case user changed it. */
2519         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2520 }
2521
2522 static void
2523 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2524                            struct ixgbe_hw_stats *hw_stats,
2525                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2526                            uint64_t *total_qprc, uint64_t *total_qprdc)
2527 {
2528         uint32_t bprc, lxon, lxoff, total;
2529         uint32_t delta_gprc = 0;
2530         unsigned i;
2531         /* Workaround for RX byte count not including CRC bytes when CRC
2532 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2533          * is disabled.
2534 +        */
2535         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2536                         IXGBE_HLREG0_RXCRCSTRP);
2537
2538         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2539         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2540         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2541         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2542
2543         for (i = 0; i < 8; i++) {
2544                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2545
2546                 /* global total per queue */
2547                 hw_stats->mpc[i] += mp;
2548                 /* Running comprehensive total for stats display */
2549                 *total_missed_rx += hw_stats->mpc[i];
2550                 if (hw->mac.type == ixgbe_mac_82598EB) {
2551                         hw_stats->rnbc[i] +=
2552                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2553                         hw_stats->pxonrxc[i] +=
2554                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2555                         hw_stats->pxoffrxc[i] +=
2556                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2557                 } else {
2558                         hw_stats->pxonrxc[i] +=
2559                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2560                         hw_stats->pxoffrxc[i] +=
2561                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2562                         hw_stats->pxon2offc[i] +=
2563                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2564                 }
2565                 hw_stats->pxontxc[i] +=
2566                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2567                 hw_stats->pxofftxc[i] +=
2568                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2569         }
2570         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2571                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2572                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2573                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2574
2575                 delta_gprc += delta_qprc;
2576
2577                 hw_stats->qprc[i] += delta_qprc;
2578                 hw_stats->qptc[i] += delta_qptc;
2579
2580                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2581                 hw_stats->qbrc[i] +=
2582                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2583                 if (crc_strip == 0)
2584                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2585
2586                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2587                 hw_stats->qbtc[i] +=
2588                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2589
2590                 hw_stats->qprdc[i] += delta_qprdc;
2591                 *total_qprdc += hw_stats->qprdc[i];
2592
2593                 *total_qprc += hw_stats->qprc[i];
2594                 *total_qbrc += hw_stats->qbrc[i];
2595         }
2596         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2597         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2598         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2599
2600         /*
2601          * An errata states that gprc actually counts good + missed packets:
2602          * Workaround to set gprc to summated queue packet receives
2603          */
2604         hw_stats->gprc = *total_qprc;
2605
2606         if (hw->mac.type != ixgbe_mac_82598EB) {
2607                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2608                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2609                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2610                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2611                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2612                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2613                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2614                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2615         } else {
2616                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2617                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2618                 /* 82598 only has a counter in the high register */
2619                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2620                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2621                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2622         }
2623         uint64_t old_tpr = hw_stats->tpr;
2624
2625         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2626         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2627
2628         if (crc_strip == 0)
2629                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2630
2631         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2632         hw_stats->gptc += delta_gptc;
2633         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2634         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2635
2636         /*
2637          * Workaround: mprc hardware is incorrectly counting
2638          * broadcasts, so for now we subtract those.
2639          */
2640         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2641         hw_stats->bprc += bprc;
2642         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2643         if (hw->mac.type == ixgbe_mac_82598EB)
2644                 hw_stats->mprc -= bprc;
2645
2646         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2647         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2648         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2649         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2650         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2651         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2652
2653         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2654         hw_stats->lxontxc += lxon;
2655         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2656         hw_stats->lxofftxc += lxoff;
2657         total = lxon + lxoff;
2658
2659         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2660         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2661         hw_stats->gptc -= total;
2662         hw_stats->mptc -= total;
2663         hw_stats->ptc64 -= total;
2664         hw_stats->gotc -= total * ETHER_MIN_LEN;
2665
2666         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2667         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2668         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2669         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2670         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2671         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2672         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2673         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2674         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2675         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2676         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2677         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2678         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2679         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2680         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2681         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2682         /* Only read FCOE on 82599 */
2683         if (hw->mac.type != ixgbe_mac_82598EB) {
2684                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2685                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2686                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2687                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2688                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2689         }
2690
2691         /* Flow Director Stats registers */
2692         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2693         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2694 }
2695
2696 /*
2697  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2698  */
2699 static void
2700 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2701 {
2702         struct ixgbe_hw *hw =
2703                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_hw_stats *hw_stats =
2705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2707         unsigned i;
2708
2709         total_missed_rx = 0;
2710         total_qbrc = 0;
2711         total_qprc = 0;
2712         total_qprdc = 0;
2713
2714         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2715                         &total_qprc, &total_qprdc);
2716
2717         if (stats == NULL)
2718                 return;
2719
2720         /* Fill out the rte_eth_stats statistics structure */
2721         stats->ipackets = total_qprc;
2722         stats->ibytes = total_qbrc;
2723         stats->opackets = hw_stats->gptc;
2724         stats->obytes = hw_stats->gotc;
2725
2726         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2727                 stats->q_ipackets[i] = hw_stats->qprc[i];
2728                 stats->q_opackets[i] = hw_stats->qptc[i];
2729                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2730                 stats->q_obytes[i] = hw_stats->qbtc[i];
2731                 stats->q_errors[i] = hw_stats->qprdc[i];
2732         }
2733
2734         /* Rx Errors */
2735         stats->imissed  = total_missed_rx;
2736         stats->ierrors  = hw_stats->crcerrs +
2737                           hw_stats->mspdc +
2738                           hw_stats->rlec +
2739                           hw_stats->ruc +
2740                           hw_stats->roc +
2741                           hw_stats->illerrc +
2742                           hw_stats->errbc +
2743                           hw_stats->rfc +
2744                           hw_stats->fccrc +
2745                           hw_stats->fclast;
2746
2747         /* Tx Errors */
2748         stats->oerrors  = 0;
2749 }
2750
2751 static void
2752 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2753 {
2754         struct ixgbe_hw_stats *stats =
2755                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2756
2757         /* HW registers are cleared on read */
2758         ixgbe_dev_stats_get(dev, NULL);
2759
2760         /* Reset software totals */
2761         memset(stats, 0, sizeof(*stats));
2762 }
2763
2764 /* This function calculates the number of xstats based on the current config */
2765 static unsigned
2766 ixgbe_xstats_calc_num(void) {
2767         return IXGBE_NB_HW_STATS +
2768                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2769                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2770 }
2771
2772 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2773         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2774 {
2775         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2776         unsigned stat, i, count;
2777
2778         if (xstats_names != NULL) {
2779                 count = 0;
2780
2781                 /* Note: limit >= cnt_stats checked upstream
2782                  * in rte_eth_xstats_names()
2783                  */
2784
2785                 /* Extended stats from ixgbe_hw_stats */
2786                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2787                         snprintf(xstats_names[count].name,
2788                                 sizeof(xstats_names[count].name),
2789                                 "%s",
2790                                 rte_ixgbe_stats_strings[i].name);
2791                         count++;
2792                 }
2793
2794                 /* RX Priority Stats */
2795                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2796                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2797                                 snprintf(xstats_names[count].name,
2798                                         sizeof(xstats_names[count].name),
2799                                         "rx_priority%u_%s", i,
2800                                         rte_ixgbe_rxq_strings[stat].name);
2801                                 count++;
2802                         }
2803                 }
2804
2805                 /* TX Priority Stats */
2806                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2807                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2808                                 snprintf(xstats_names[count].name,
2809                                         sizeof(xstats_names[count].name),
2810                                         "tx_priority%u_%s", i,
2811                                         rte_ixgbe_txq_strings[stat].name);
2812                                 count++;
2813                         }
2814                 }
2815         }
2816         return cnt_stats;
2817 }
2818
2819 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2820         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2821 {
2822         unsigned i;
2823
2824         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2825                 return -ENOMEM;
2826
2827         if (xstats_names != NULL)
2828                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2829                         snprintf(xstats_names[i].name,
2830                                 sizeof(xstats_names[i].name),
2831                                 "%s", rte_ixgbevf_stats_strings[i].name);
2832         return IXGBEVF_NB_XSTATS;
2833 }
2834
2835 static int
2836 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2837                                          unsigned n)
2838 {
2839         struct ixgbe_hw *hw =
2840                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         struct ixgbe_hw_stats *hw_stats =
2842                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2843         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2844         unsigned i, stat, count = 0;
2845
2846         count = ixgbe_xstats_calc_num();
2847
2848         if (n < count)
2849                 return count;
2850
2851         total_missed_rx = 0;
2852         total_qbrc = 0;
2853         total_qprc = 0;
2854         total_qprdc = 0;
2855
2856         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2857                                    &total_qprc, &total_qprdc);
2858
2859         /* If this is a reset xstats is NULL, and we have cleared the
2860          * registers by reading them.
2861          */
2862         if (!xstats)
2863                 return 0;
2864
2865         /* Extended stats from ixgbe_hw_stats */
2866         count = 0;
2867         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2868                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2869                                 rte_ixgbe_stats_strings[i].offset);
2870                 count++;
2871         }
2872
2873         /* RX Priority Stats */
2874         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2875                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2876                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2877                                         rte_ixgbe_rxq_strings[stat].offset +
2878                                         (sizeof(uint64_t) * i));
2879                         count++;
2880                 }
2881         }
2882
2883         /* TX Priority Stats */
2884         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2885                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2886                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2887                                         rte_ixgbe_txq_strings[stat].offset +
2888                                         (sizeof(uint64_t) * i));
2889                         count++;
2890                 }
2891         }
2892         return count;
2893 }
2894
2895 static void
2896 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2897 {
2898         struct ixgbe_hw_stats *stats =
2899                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2900
2901         unsigned count = ixgbe_xstats_calc_num();
2902
2903         /* HW registers are cleared on read */
2904         ixgbe_dev_xstats_get(dev, NULL, count);
2905
2906         /* Reset software totals */
2907         memset(stats, 0, sizeof(*stats));
2908 }
2909
2910 static void
2911 ixgbevf_update_stats(struct rte_eth_dev *dev)
2912 {
2913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2915                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2916
2917         /* Good Rx packet, include VF loopback */
2918         UPDATE_VF_STAT(IXGBE_VFGPRC,
2919             hw_stats->last_vfgprc, hw_stats->vfgprc);
2920
2921         /* Good Rx octets, include VF loopback */
2922         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2923             hw_stats->last_vfgorc, hw_stats->vfgorc);
2924
2925         /* Good Tx packet, include VF loopback */
2926         UPDATE_VF_STAT(IXGBE_VFGPTC,
2927             hw_stats->last_vfgptc, hw_stats->vfgptc);
2928
2929         /* Good Tx octets, include VF loopback */
2930         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2931             hw_stats->last_vfgotc, hw_stats->vfgotc);
2932
2933         /* Rx Multicst Packet */
2934         UPDATE_VF_STAT(IXGBE_VFMPRC,
2935             hw_stats->last_vfmprc, hw_stats->vfmprc);
2936 }
2937
2938 static int
2939 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2940                        unsigned n)
2941 {
2942         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2943                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2944         unsigned i;
2945
2946         if (n < IXGBEVF_NB_XSTATS)
2947                 return IXGBEVF_NB_XSTATS;
2948
2949         ixgbevf_update_stats(dev);
2950
2951         if (!xstats)
2952                 return 0;
2953
2954         /* Extended stats */
2955         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2956                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2957                         rte_ixgbevf_stats_strings[i].offset);
2958         }
2959
2960         return IXGBEVF_NB_XSTATS;
2961 }
2962
2963 static void
2964 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2965 {
2966         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2967                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2968
2969         ixgbevf_update_stats(dev);
2970
2971         if (stats == NULL)
2972                 return;
2973
2974         stats->ipackets = hw_stats->vfgprc;
2975         stats->ibytes = hw_stats->vfgorc;
2976         stats->opackets = hw_stats->vfgptc;
2977         stats->obytes = hw_stats->vfgotc;
2978 }
2979
2980 static void
2981 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2982 {
2983         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2984                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2985
2986         /* Sync HW register to the last stats */
2987         ixgbevf_dev_stats_get(dev, NULL);
2988
2989         /* reset HW current stats*/
2990         hw_stats->vfgprc = 0;
2991         hw_stats->vfgorc = 0;
2992         hw_stats->vfgptc = 0;
2993         hw_stats->vfgotc = 0;
2994 }
2995
2996 static void
2997 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2998 {
2999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3001
3002         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3003         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3004         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3005                 /*
3006                  * When DCB/VT is off, maximum number of queues changes,
3007                  * except for 82598EB, which remains constant.
3008                  */
3009                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3010                                 hw->mac.type != ixgbe_mac_82598EB)
3011                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3012         }
3013         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3014         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3015         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3016         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3017         dev_info->max_vfs = dev->pci_dev->max_vfs;
3018         if (hw->mac.type == ixgbe_mac_82598EB)
3019                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3020         else
3021                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3022         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3023         dev_info->rx_offload_capa =
3024                 DEV_RX_OFFLOAD_VLAN_STRIP |
3025                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3026                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3027                 DEV_RX_OFFLOAD_TCP_CKSUM;
3028
3029         /*
3030          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3031          * mode.
3032          */
3033         if ((hw->mac.type == ixgbe_mac_82599EB ||
3034              hw->mac.type == ixgbe_mac_X540) &&
3035             !RTE_ETH_DEV_SRIOV(dev).active)
3036                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3037
3038         if (hw->mac.type == ixgbe_mac_X550 ||
3039             hw->mac.type == ixgbe_mac_X550EM_x ||
3040             hw->mac.type == ixgbe_mac_X550EM_a)
3041                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3042
3043         dev_info->tx_offload_capa =
3044                 DEV_TX_OFFLOAD_VLAN_INSERT |
3045                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3046                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3047                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3048                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3049                 DEV_TX_OFFLOAD_TCP_TSO;
3050
3051         if (hw->mac.type == ixgbe_mac_X550 ||
3052             hw->mac.type == ixgbe_mac_X550EM_x ||
3053             hw->mac.type == ixgbe_mac_X550EM_a)
3054                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3055
3056         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3057                 .rx_thresh = {
3058                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3059                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3060                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3061                 },
3062                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3063                 .rx_drop_en = 0,
3064         };
3065
3066         dev_info->default_txconf = (struct rte_eth_txconf) {
3067                 .tx_thresh = {
3068                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3069                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3070                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3071                 },
3072                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3073                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3074                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3075                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3076         };
3077
3078         dev_info->rx_desc_lim = rx_desc_lim;
3079         dev_info->tx_desc_lim = tx_desc_lim;
3080
3081         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3082         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3083         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3084
3085         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3086         if (hw->mac.type == ixgbe_mac_X540 ||
3087             hw->mac.type == ixgbe_mac_X540_vf ||
3088             hw->mac.type == ixgbe_mac_X550 ||
3089             hw->mac.type == ixgbe_mac_X550_vf) {
3090                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3091         }
3092 }
3093
3094 static const uint32_t *
3095 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3096 {
3097         static const uint32_t ptypes[] = {
3098                 /* For non-vec functions,
3099                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3100                  * for vec functions,
3101                  * refers to _recv_raw_pkts_vec().
3102                  */
3103                 RTE_PTYPE_L2_ETHER,
3104                 RTE_PTYPE_L3_IPV4,
3105                 RTE_PTYPE_L3_IPV4_EXT,
3106                 RTE_PTYPE_L3_IPV6,
3107                 RTE_PTYPE_L3_IPV6_EXT,
3108                 RTE_PTYPE_L4_SCTP,
3109                 RTE_PTYPE_L4_TCP,
3110                 RTE_PTYPE_L4_UDP,
3111                 RTE_PTYPE_TUNNEL_IP,
3112                 RTE_PTYPE_INNER_L3_IPV6,
3113                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3114                 RTE_PTYPE_INNER_L4_TCP,
3115                 RTE_PTYPE_INNER_L4_UDP,
3116                 RTE_PTYPE_UNKNOWN
3117         };
3118
3119         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3120             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3121             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3122             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3123                 return ptypes;
3124         return NULL;
3125 }
3126
3127 static void
3128 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3129                      struct rte_eth_dev_info *dev_info)
3130 {
3131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132
3133         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3134         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3135         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3136         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3137         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3138         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3139         dev_info->max_vfs = dev->pci_dev->max_vfs;
3140         if (hw->mac.type == ixgbe_mac_82598EB)
3141                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3142         else
3143                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3144         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3145                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3146                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3147                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3148         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3149                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3150                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3151                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3152                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3153                                 DEV_TX_OFFLOAD_TCP_TSO;
3154
3155         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3156                 .rx_thresh = {
3157                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3158                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3159                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3160                 },
3161                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3162                 .rx_drop_en = 0,
3163         };
3164
3165         dev_info->default_txconf = (struct rte_eth_txconf) {
3166                 .tx_thresh = {
3167                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3168                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3169                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3170                 },
3171                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3172                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3173                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3174                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3175         };
3176
3177         dev_info->rx_desc_lim = rx_desc_lim;
3178         dev_info->tx_desc_lim = tx_desc_lim;
3179 }
3180
3181 /* return 0 means link status changed, -1 means not changed */
3182 static int
3183 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3184 {
3185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186         struct rte_eth_link link, old;
3187         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3188         int link_up;
3189         int diag;
3190
3191         link.link_status = ETH_LINK_DOWN;
3192         link.link_speed = 0;
3193         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3194         memset(&old, 0, sizeof(old));
3195         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3196
3197         hw->mac.get_link_status = true;
3198
3199         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3200         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3201                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3202         else
3203                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3204
3205         if (diag != 0) {
3206                 link.link_speed = ETH_SPEED_NUM_100M;
3207                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3208                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3209                 if (link.link_status == old.link_status)
3210                         return -1;
3211                 return 0;
3212         }
3213
3214         if (link_up == 0) {
3215                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3216                 if (link.link_status == old.link_status)
3217                         return -1;
3218                 return 0;
3219         }
3220         link.link_status = ETH_LINK_UP;
3221         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3222
3223         switch (link_speed) {
3224         default:
3225         case IXGBE_LINK_SPEED_UNKNOWN:
3226                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3227                 link.link_speed = ETH_SPEED_NUM_100M;
3228                 break;
3229
3230         case IXGBE_LINK_SPEED_100_FULL:
3231                 link.link_speed = ETH_SPEED_NUM_100M;
3232                 break;
3233
3234         case IXGBE_LINK_SPEED_1GB_FULL:
3235                 link.link_speed = ETH_SPEED_NUM_1G;
3236                 break;
3237
3238         case IXGBE_LINK_SPEED_10GB_FULL:
3239                 link.link_speed = ETH_SPEED_NUM_10G;
3240                 break;
3241         }
3242         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3243
3244         if (link.link_status == old.link_status)
3245                 return -1;
3246
3247         return 0;
3248 }
3249
3250 static void
3251 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3252 {
3253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3254         uint32_t fctrl;
3255
3256         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3257         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3258         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3259 }
3260
3261 static void
3262 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3263 {
3264         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3265         uint32_t fctrl;
3266
3267         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3268         fctrl &= (~IXGBE_FCTRL_UPE);
3269         if (dev->data->all_multicast == 1)
3270                 fctrl |= IXGBE_FCTRL_MPE;
3271         else
3272                 fctrl &= (~IXGBE_FCTRL_MPE);
3273         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3274 }
3275
3276 static void
3277 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3278 {
3279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280         uint32_t fctrl;
3281
3282         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3283         fctrl |= IXGBE_FCTRL_MPE;
3284         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3285 }
3286
3287 static void
3288 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3289 {
3290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3291         uint32_t fctrl;
3292
3293         if (dev->data->promiscuous == 1)
3294                 return; /* must remain in all_multicast mode */
3295
3296         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3297         fctrl &= (~IXGBE_FCTRL_MPE);
3298         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3299 }
3300
3301 /**
3302  * It clears the interrupt causes and enables the interrupt.
3303  * It will be called once only during nic initialized.
3304  *
3305  * @param dev
3306  *  Pointer to struct rte_eth_dev.
3307  *
3308  * @return
3309  *  - On success, zero.
3310  *  - On failure, a negative value.
3311  */
3312 static int
3313 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3314 {
3315         struct ixgbe_interrupt *intr =
3316                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3317
3318         ixgbe_dev_link_status_print(dev);
3319         intr->mask |= IXGBE_EICR_LSC;
3320
3321         return 0;
3322 }
3323
3324 /**
3325  * It clears the interrupt causes and enables the interrupt.
3326  * It will be called once only during nic initialized.
3327  *
3328  * @param dev
3329  *  Pointer to struct rte_eth_dev.
3330  *
3331  * @return
3332  *  - On success, zero.
3333  *  - On failure, a negative value.
3334  */
3335 static int
3336 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3337 {
3338         struct ixgbe_interrupt *intr =
3339                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3340
3341         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3342
3343         return 0;
3344 }
3345
3346 /*
3347  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3348  *
3349  * @param dev
3350  *  Pointer to struct rte_eth_dev.
3351  *
3352  * @return
3353  *  - On success, zero.
3354  *  - On failure, a negative value.
3355  */
3356 static int
3357 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3358 {
3359         uint32_t eicr;
3360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         struct ixgbe_interrupt *intr =
3362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3363
3364         /* clear all cause mask */
3365         ixgbe_disable_intr(hw);
3366
3367         /* read-on-clear nic registers here */
3368         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3369         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3370
3371         intr->flags = 0;
3372
3373         /* set flag for async link update */
3374         if (eicr & IXGBE_EICR_LSC)
3375                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3376
3377         if (eicr & IXGBE_EICR_MAILBOX)
3378                 intr->flags |= IXGBE_FLAG_MAILBOX;
3379
3380         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3381             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3382             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3383                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3384
3385         return 0;
3386 }
3387
3388 /**
3389  * It gets and then prints the link status.
3390  *
3391  * @param dev
3392  *  Pointer to struct rte_eth_dev.
3393  *
3394  * @return
3395  *  - On success, zero.
3396  *  - On failure, a negative value.
3397  */
3398 static void
3399 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3400 {
3401         struct rte_eth_link link;
3402
3403         memset(&link, 0, sizeof(link));
3404         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3405         if (link.link_status) {
3406                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3407                                         (int)(dev->data->port_id),
3408                                         (unsigned)link.link_speed,
3409                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3410                                         "full-duplex" : "half-duplex");
3411         } else {
3412                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3413                                 (int)(dev->data->port_id));
3414         }
3415         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3416                                 dev->pci_dev->addr.domain,
3417                                 dev->pci_dev->addr.bus,
3418                                 dev->pci_dev->addr.devid,
3419                                 dev->pci_dev->addr.function);
3420 }
3421
3422 /*
3423  * It executes link_update after knowing an interrupt occurred.
3424  *
3425  * @param dev
3426  *  Pointer to struct rte_eth_dev.
3427  *
3428  * @return
3429  *  - On success, zero.
3430  *  - On failure, a negative value.
3431  */
3432 static int
3433 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3434 {
3435         struct ixgbe_interrupt *intr =
3436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3437         int64_t timeout;
3438         struct rte_eth_link link;
3439         int intr_enable_delay = false;
3440         struct ixgbe_hw *hw =
3441                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442
3443         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3444
3445         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3446                 ixgbe_pf_mbx_process(dev);
3447                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3448         }
3449
3450         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3451                 ixgbe_handle_lasi(hw);
3452                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3453         }
3454
3455         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3456                 /* get the link status before link update, for predicting later */
3457                 memset(&link, 0, sizeof(link));
3458                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3459
3460                 ixgbe_dev_link_update(dev, 0);
3461
3462                 /* likely to up */
3463                 if (!link.link_status)
3464                         /* handle it 1 sec later, wait it being stable */
3465                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3466                 /* likely to down */
3467                 else
3468                         /* handle it 4 sec later, wait it being stable */
3469                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3470
3471                 ixgbe_dev_link_status_print(dev);
3472
3473                 intr_enable_delay = true;
3474         }
3475
3476         if (intr_enable_delay) {
3477                 if (rte_eal_alarm_set(timeout * 1000,
3478                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3479                         PMD_DRV_LOG(ERR, "Error setting alarm");
3480         } else {
3481                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3482                 ixgbe_enable_intr(dev);
3483                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3484         }
3485
3486
3487         return 0;
3488 }
3489
3490 /**
3491  * Interrupt handler which shall be registered for alarm callback for delayed
3492  * handling specific interrupt to wait for the stable nic state. As the
3493  * NIC interrupt state is not stable for ixgbe after link is just down,
3494  * it needs to wait 4 seconds to get the stable status.
3495  *
3496  * @param handle
3497  *  Pointer to interrupt handle.
3498  * @param param
3499  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3500  *
3501  * @return
3502  *  void
3503  */
3504 static void
3505 ixgbe_dev_interrupt_delayed_handler(void *param)
3506 {
3507         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3508         struct ixgbe_interrupt *intr =
3509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3510         struct ixgbe_hw *hw =
3511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512         uint32_t eicr;
3513
3514         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3515         if (eicr & IXGBE_EICR_MAILBOX)
3516                 ixgbe_pf_mbx_process(dev);
3517
3518         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3519                 ixgbe_handle_lasi(hw);
3520                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3521         }
3522
3523         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3524                 ixgbe_dev_link_update(dev, 0);
3525                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3526                 ixgbe_dev_link_status_print(dev);
3527                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3528         }
3529
3530         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3531         ixgbe_enable_intr(dev);
3532         rte_intr_enable(&(dev->pci_dev->intr_handle));
3533 }
3534
3535 /**
3536  * Interrupt handler triggered by NIC  for handling
3537  * specific interrupt.
3538  *
3539  * @param handle
3540  *  Pointer to interrupt handle.
3541  * @param param
3542  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3543  *
3544  * @return
3545  *  void
3546  */
3547 static void
3548 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3549                             void *param)
3550 {
3551         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3552
3553         ixgbe_dev_interrupt_get_status(dev);
3554         ixgbe_dev_interrupt_action(dev);
3555 }
3556
3557 static int
3558 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3559 {
3560         struct ixgbe_hw *hw;
3561
3562         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3564 }
3565
3566 static int
3567 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3568 {
3569         struct ixgbe_hw *hw;
3570
3571         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3573 }
3574
3575 static int
3576 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3577 {
3578         struct ixgbe_hw *hw;
3579         uint32_t mflcn_reg;
3580         uint32_t fccfg_reg;
3581         int rx_pause;
3582         int tx_pause;
3583
3584         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585
3586         fc_conf->pause_time = hw->fc.pause_time;
3587         fc_conf->high_water = hw->fc.high_water[0];
3588         fc_conf->low_water = hw->fc.low_water[0];
3589         fc_conf->send_xon = hw->fc.send_xon;
3590         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3591
3592         /*
3593          * Return rx_pause status according to actual setting of
3594          * MFLCN register.
3595          */
3596         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3597         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3598                 rx_pause = 1;
3599         else
3600                 rx_pause = 0;
3601
3602         /*
3603          * Return tx_pause status according to actual setting of
3604          * FCCFG register.
3605          */
3606         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3607         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3608                 tx_pause = 1;
3609         else
3610                 tx_pause = 0;
3611
3612         if (rx_pause && tx_pause)
3613                 fc_conf->mode = RTE_FC_FULL;
3614         else if (rx_pause)
3615                 fc_conf->mode = RTE_FC_RX_PAUSE;
3616         else if (tx_pause)
3617                 fc_conf->mode = RTE_FC_TX_PAUSE;
3618         else
3619                 fc_conf->mode = RTE_FC_NONE;
3620
3621         return 0;
3622 }
3623
3624 static int
3625 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3626 {
3627         struct ixgbe_hw *hw;
3628         int err;
3629         uint32_t rx_buf_size;
3630         uint32_t max_high_water;
3631         uint32_t mflcn;
3632         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3633                 ixgbe_fc_none,
3634                 ixgbe_fc_rx_pause,
3635                 ixgbe_fc_tx_pause,
3636                 ixgbe_fc_full
3637         };
3638
3639         PMD_INIT_FUNC_TRACE();
3640
3641         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3643         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3644
3645         /*
3646          * At least reserve one Ethernet frame for watermark
3647          * high_water/low_water in kilo bytes for ixgbe
3648          */
3649         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3650         if ((fc_conf->high_water > max_high_water) ||
3651                 (fc_conf->high_water < fc_conf->low_water)) {
3652                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3653                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3654                 return -EINVAL;
3655         }
3656
3657         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3658         hw->fc.pause_time     = fc_conf->pause_time;
3659         hw->fc.high_water[0]  = fc_conf->high_water;
3660         hw->fc.low_water[0]   = fc_conf->low_water;
3661         hw->fc.send_xon       = fc_conf->send_xon;
3662         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3663
3664         err = ixgbe_fc_enable(hw);
3665
3666         /* Not negotiated is not an error case */
3667         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3668
3669                 /* check if we want to forward MAC frames - driver doesn't have native
3670                  * capability to do that, so we'll write the registers ourselves */
3671
3672                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3673
3674                 /* set or clear MFLCN.PMCF bit depending on configuration */
3675                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3676                         mflcn |= IXGBE_MFLCN_PMCF;
3677                 else
3678                         mflcn &= ~IXGBE_MFLCN_PMCF;
3679
3680                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3681                 IXGBE_WRITE_FLUSH(hw);
3682
3683                 return 0;
3684         }
3685
3686         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3687         return -EIO;
3688 }
3689
3690 /**
3691  *  ixgbe_pfc_enable_generic - Enable flow control
3692  *  @hw: pointer to hardware structure
3693  *  @tc_num: traffic class number
3694  *  Enable flow control according to the current settings.
3695  */
3696 static int
3697 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3698 {
3699         int ret_val = 0;
3700         uint32_t mflcn_reg, fccfg_reg;
3701         uint32_t reg;
3702         uint32_t fcrtl, fcrth;
3703         uint8_t i;
3704         uint8_t nb_rx_en;
3705
3706         /* Validate the water mark configuration */
3707         if (!hw->fc.pause_time) {
3708                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3709                 goto out;
3710         }
3711
3712         /* Low water mark of zero causes XOFF floods */
3713         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3714                  /* High/Low water can not be 0 */
3715                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3716                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3717                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3718                         goto out;
3719                 }
3720
3721                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3722                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3723                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3724                         goto out;
3725                 }
3726         }
3727         /* Negotiate the fc mode to use */
3728         ixgbe_fc_autoneg(hw);
3729
3730         /* Disable any previous flow control settings */
3731         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3732         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3733
3734         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3735         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3736
3737         switch (hw->fc.current_mode) {
3738         case ixgbe_fc_none:
3739                 /*
3740                  * If the count of enabled RX Priority Flow control >1,
3741                  * and the TX pause can not be disabled
3742                  */
3743                 nb_rx_en = 0;
3744                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3745                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3746                         if (reg & IXGBE_FCRTH_FCEN)
3747                                 nb_rx_en++;
3748                 }
3749                 if (nb_rx_en > 1)
3750                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3751                 break;
3752         case ixgbe_fc_rx_pause:
3753                 /*
3754                  * Rx Flow control is enabled and Tx Flow control is
3755                  * disabled by software override. Since there really
3756                  * isn't a way to advertise that we are capable of RX
3757                  * Pause ONLY, we will advertise that we support both
3758                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3759                  * disable the adapter's ability to send PAUSE frames.
3760                  */
3761                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3762                 /*
3763                  * If the count of enabled RX Priority Flow control >1,
3764                  * and the TX pause can not be disabled
3765                  */
3766                 nb_rx_en = 0;
3767                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3768                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3769                         if (reg & IXGBE_FCRTH_FCEN)
3770                                 nb_rx_en++;
3771                 }
3772                 if (nb_rx_en > 1)
3773                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3774                 break;
3775         case ixgbe_fc_tx_pause:
3776                 /*
3777                  * Tx Flow control is enabled, and Rx Flow control is
3778                  * disabled by software override.
3779                  */
3780                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3781                 break;
3782         case ixgbe_fc_full:
3783                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3784                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3785                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3786                 break;
3787         default:
3788                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3789                 ret_val = IXGBE_ERR_CONFIG;
3790                 goto out;
3791         }
3792
3793         /* Set 802.3x based flow control settings. */
3794         mflcn_reg |= IXGBE_MFLCN_DPF;
3795         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3796         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3797
3798         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3799         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3800                 hw->fc.high_water[tc_num]) {
3801                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3802                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3803                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3804         } else {
3805                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3806                 /*
3807                  * In order to prevent Tx hangs when the internal Tx
3808                  * switch is enabled we must set the high water mark
3809                  * to the maximum FCRTH value.  This allows the Tx
3810                  * switch to function even under heavy Rx workloads.
3811                  */
3812                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3813         }
3814         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3815
3816         /* Configure pause time (2 TCs per register) */
3817         reg = hw->fc.pause_time * 0x00010001;
3818         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3819                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3820
3821         /* Configure flow control refresh threshold value */
3822         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3823
3824 out:
3825         return ret_val;
3826 }
3827
3828 static int
3829 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3830 {
3831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3833
3834         if (hw->mac.type != ixgbe_mac_82598EB) {
3835                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3836         }
3837         return ret_val;
3838 }
3839
3840 static int
3841 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3842 {
3843         int err;
3844         uint32_t rx_buf_size;
3845         uint32_t max_high_water;
3846         uint8_t tc_num;
3847         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3848         struct ixgbe_hw *hw =
3849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850         struct ixgbe_dcb_config *dcb_config =
3851                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3852
3853         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3854                 ixgbe_fc_none,
3855                 ixgbe_fc_rx_pause,
3856                 ixgbe_fc_tx_pause,
3857                 ixgbe_fc_full
3858         };
3859
3860         PMD_INIT_FUNC_TRACE();
3861
3862         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3863         tc_num = map[pfc_conf->priority];
3864         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3865         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3866         /*
3867          * At least reserve one Ethernet frame for watermark
3868          * high_water/low_water in kilo bytes for ixgbe
3869          */
3870         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3871         if ((pfc_conf->fc.high_water > max_high_water) ||
3872             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3873                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3874                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3875                 return -EINVAL;
3876         }
3877
3878         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3879         hw->fc.pause_time = pfc_conf->fc.pause_time;
3880         hw->fc.send_xon = pfc_conf->fc.send_xon;
3881         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3882         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3883
3884         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3885
3886         /* Not negotiated is not an error case */
3887         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3888                 return 0;
3889
3890         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3891         return -EIO;
3892 }
3893
3894 static int
3895 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3896                           struct rte_eth_rss_reta_entry64 *reta_conf,
3897                           uint16_t reta_size)
3898 {
3899         uint16_t i, sp_reta_size;
3900         uint8_t j, mask;
3901         uint32_t reta, r;
3902         uint16_t idx, shift;
3903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         uint32_t reta_reg;
3905
3906         PMD_INIT_FUNC_TRACE();
3907
3908         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3909                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3910                         "NIC.");
3911                 return -ENOTSUP;
3912         }
3913
3914         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3915         if (reta_size != sp_reta_size) {
3916                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3917                         "(%d) doesn't match the number hardware can supported "
3918                         "(%d)\n", reta_size, sp_reta_size);
3919                 return -EINVAL;
3920         }
3921
3922         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3923                 idx = i / RTE_RETA_GROUP_SIZE;
3924                 shift = i % RTE_RETA_GROUP_SIZE;
3925                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3926                                                 IXGBE_4_BIT_MASK);
3927                 if (!mask)
3928                         continue;
3929                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3930                 if (mask == IXGBE_4_BIT_MASK)
3931                         r = 0;
3932                 else
3933                         r = IXGBE_READ_REG(hw, reta_reg);
3934                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3935                         if (mask & (0x1 << j))
3936                                 reta |= reta_conf[idx].reta[shift + j] <<
3937                                                         (CHAR_BIT * j);
3938                         else
3939                                 reta |= r & (IXGBE_8_BIT_MASK <<
3940                                                 (CHAR_BIT * j));
3941                 }
3942                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3943         }
3944
3945         return 0;
3946 }
3947
3948 static int
3949 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3950                          struct rte_eth_rss_reta_entry64 *reta_conf,
3951                          uint16_t reta_size)
3952 {
3953         uint16_t i, sp_reta_size;
3954         uint8_t j, mask;
3955         uint32_t reta;
3956         uint16_t idx, shift;
3957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958         uint32_t reta_reg;
3959
3960         PMD_INIT_FUNC_TRACE();
3961         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3962         if (reta_size != sp_reta_size) {
3963                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3964                         "(%d) doesn't match the number hardware can supported "
3965                         "(%d)\n", reta_size, sp_reta_size);
3966                 return -EINVAL;
3967         }
3968
3969         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3970                 idx = i / RTE_RETA_GROUP_SIZE;
3971                 shift = i % RTE_RETA_GROUP_SIZE;
3972                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3973                                                 IXGBE_4_BIT_MASK);
3974                 if (!mask)
3975                         continue;
3976
3977                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3978                 reta = IXGBE_READ_REG(hw, reta_reg);
3979                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3980                         if (mask & (0x1 << j))
3981                                 reta_conf[idx].reta[shift + j] =
3982                                         ((reta >> (CHAR_BIT * j)) &
3983                                                 IXGBE_8_BIT_MASK);
3984                 }
3985         }
3986
3987         return 0;
3988 }
3989
3990 static void
3991 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3992                                 uint32_t index, uint32_t pool)
3993 {
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         uint32_t enable_addr = 1;
3996
3997         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3998 }
3999
4000 static void
4001 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4002 {
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004
4005         ixgbe_clear_rar(hw, index);
4006 }
4007
4008 static void
4009 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4010 {
4011         ixgbe_remove_rar(dev, 0);
4012
4013         ixgbe_add_rar(dev, addr, 0, 0);
4014 }
4015
4016 static int
4017 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4018 {
4019         uint32_t hlreg0;
4020         uint32_t maxfrs;
4021         struct ixgbe_hw *hw;
4022         struct rte_eth_dev_info dev_info;
4023         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4024
4025         ixgbe_dev_info_get(dev, &dev_info);
4026
4027         /* check that mtu is within the allowed range */
4028         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4029                 return -EINVAL;
4030
4031         /* refuse mtu that requires the support of scattered packets when this
4032          * feature has not been enabled before.
4033          */
4034         if (!dev->data->scattered_rx &&
4035             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4036              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4037                 return -EINVAL;
4038
4039         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4041
4042         /* switch to jumbo mode if needed */
4043         if (frame_size > ETHER_MAX_LEN) {
4044                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4045                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4046         } else {
4047                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4048                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4049         }
4050         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4051
4052         /* update max frame size */
4053         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4054
4055         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4056         maxfrs &= 0x0000FFFF;
4057         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4058         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4059
4060         return 0;
4061 }
4062
4063 /*
4064  * Virtual Function operations
4065  */
4066 static void
4067 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4068 {
4069         PMD_INIT_FUNC_TRACE();
4070
4071         /* Clear interrupt mask to stop from interrupts being generated */
4072         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4073
4074         IXGBE_WRITE_FLUSH(hw);
4075 }
4076
4077 static void
4078 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4079 {
4080         PMD_INIT_FUNC_TRACE();
4081
4082         /* VF enable interrupt autoclean */
4083         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4084         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4085         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4086
4087         IXGBE_WRITE_FLUSH(hw);
4088 }
4089
4090 static int
4091 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4092 {
4093         struct rte_eth_conf *conf = &dev->data->dev_conf;
4094         struct ixgbe_adapter *adapter =
4095                         (struct ixgbe_adapter *)dev->data->dev_private;
4096
4097         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4098                      dev->data->port_id);
4099
4100         /*
4101          * VF has no ability to enable/disable HW CRC
4102          * Keep the persistent behavior the same as Host PF
4103          */
4104 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4105         if (!conf->rxmode.hw_strip_crc) {
4106                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4107                 conf->rxmode.hw_strip_crc = 1;
4108         }
4109 #else
4110         if (conf->rxmode.hw_strip_crc) {
4111                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4112                 conf->rxmode.hw_strip_crc = 0;
4113         }
4114 #endif
4115
4116         /*
4117          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4118          * allocation or vector Rx preconditions we will reset it.
4119          */
4120         adapter->rx_bulk_alloc_allowed = true;
4121         adapter->rx_vec_allowed = true;
4122
4123         return 0;
4124 }
4125
4126 static int
4127 ixgbevf_dev_start(struct rte_eth_dev *dev)
4128 {
4129         struct ixgbe_hw *hw =
4130                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4131         uint32_t intr_vector = 0;
4132         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4133
4134         int err, mask = 0;
4135
4136         PMD_INIT_FUNC_TRACE();
4137
4138         hw->mac.ops.reset_hw(hw);
4139         hw->mac.get_link_status = true;
4140
4141         /* negotiate mailbox API version to use with the PF. */
4142         ixgbevf_negotiate_api(hw);
4143
4144         ixgbevf_dev_tx_init(dev);
4145
4146         /* This can fail when allocating mbufs for descriptor rings */
4147         err = ixgbevf_dev_rx_init(dev);
4148         if (err) {
4149                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4150                 ixgbe_dev_clear_queues(dev);
4151                 return err;
4152         }
4153
4154         /* Set vfta */
4155         ixgbevf_set_vfta_all(dev, 1);
4156
4157         /* Set HW strip */
4158         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4159                 ETH_VLAN_EXTEND_MASK;
4160         ixgbevf_vlan_offload_set(dev, mask);
4161
4162         ixgbevf_dev_rxtx_start(dev);
4163
4164         /* check and configure queue intr-vector mapping */
4165         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4166                 intr_vector = dev->data->nb_rx_queues;
4167                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4168                         return -1;
4169         }
4170
4171         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4172                 intr_handle->intr_vec =
4173                         rte_zmalloc("intr_vec",
4174                                     dev->data->nb_rx_queues * sizeof(int), 0);
4175                 if (intr_handle->intr_vec == NULL) {
4176                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4177                                      " intr_vec\n", dev->data->nb_rx_queues);
4178                         return -ENOMEM;
4179                 }
4180         }
4181         ixgbevf_configure_msix(dev);
4182
4183         rte_intr_enable(intr_handle);
4184
4185         /* Re-enable interrupt for VF */
4186         ixgbevf_intr_enable(hw);
4187
4188         return 0;
4189 }
4190
4191 static void
4192 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4193 {
4194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4195         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4196
4197         PMD_INIT_FUNC_TRACE();
4198
4199         ixgbevf_intr_disable(hw);
4200
4201         hw->adapter_stopped = 1;
4202         ixgbe_stop_adapter(hw);
4203
4204         /*
4205           * Clear what we set, but we still keep shadow_vfta to
4206           * restore after device starts
4207           */
4208         ixgbevf_set_vfta_all(dev, 0);
4209
4210         /* Clear stored conf */
4211         dev->data->scattered_rx = 0;
4212
4213         ixgbe_dev_clear_queues(dev);
4214
4215         /* Clean datapath event and queue/vec mapping */
4216         rte_intr_efd_disable(intr_handle);
4217         if (intr_handle->intr_vec != NULL) {
4218                 rte_free(intr_handle->intr_vec);
4219                 intr_handle->intr_vec = NULL;
4220         }
4221 }
4222
4223 static void
4224 ixgbevf_dev_close(struct rte_eth_dev *dev)
4225 {
4226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227
4228         PMD_INIT_FUNC_TRACE();
4229
4230         ixgbe_reset_hw(hw);
4231
4232         ixgbevf_dev_stop(dev);
4233
4234         ixgbe_dev_free_queues(dev);
4235
4236         /**
4237          * Remove the VF MAC address ro ensure
4238          * that the VF traffic goes to the PF
4239          * after stop, close and detach of the VF
4240          **/
4241         ixgbevf_remove_mac_addr(dev, 0);
4242 }
4243
4244 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4245 {
4246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4247         struct ixgbe_vfta *shadow_vfta =
4248                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4249         int i = 0, j = 0, vfta = 0, mask = 1;
4250
4251         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4252                 vfta = shadow_vfta->vfta[i];
4253                 if (vfta) {
4254                         mask = 1;
4255                         for (j = 0; j < 32; j++) {
4256                                 if (vfta & mask)
4257                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4258                                                        on, false);
4259                                 mask <<= 1;
4260                         }
4261                 }
4262         }
4263
4264 }
4265
4266 static int
4267 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4268 {
4269         struct ixgbe_hw *hw =
4270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         struct ixgbe_vfta *shadow_vfta =
4272                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4273         uint32_t vid_idx = 0;
4274         uint32_t vid_bit = 0;
4275         int ret = 0;
4276
4277         PMD_INIT_FUNC_TRACE();
4278
4279         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4280         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4281         if (ret) {
4282                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4283                 return ret;
4284         }
4285         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4286         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4287
4288         /* Save what we set and retore it after device reset */
4289         if (on)
4290                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4291         else
4292                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4293
4294         return 0;
4295 }
4296
4297 static void
4298 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4299 {
4300         struct ixgbe_hw *hw =
4301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302         uint32_t ctrl;
4303
4304         PMD_INIT_FUNC_TRACE();
4305
4306         if (queue >= hw->mac.max_rx_queues)
4307                 return;
4308
4309         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4310         if (on)
4311                 ctrl |= IXGBE_RXDCTL_VME;
4312         else
4313                 ctrl &= ~IXGBE_RXDCTL_VME;
4314         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4315
4316         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4317 }
4318
4319 static void
4320 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4321 {
4322         struct ixgbe_hw *hw =
4323                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         uint16_t i;
4325         int on = 0;
4326
4327         /* VF function only support hw strip feature, others are not support */
4328         if (mask & ETH_VLAN_STRIP_MASK) {
4329                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4330
4331                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4332                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4333         }
4334 }
4335
4336 static int
4337 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4338 {
4339         uint32_t reg_val;
4340
4341         /* we only need to do this if VMDq is enabled */
4342         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4343         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4344                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4345                 return -1;
4346         }
4347
4348         return 0;
4349 }
4350
4351 static uint32_t
4352 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4353 {
4354         uint32_t vector = 0;
4355
4356         switch (hw->mac.mc_filter_type) {
4357         case 0:   /* use bits [47:36] of the address */
4358                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4359                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4360                 break;
4361         case 1:   /* use bits [46:35] of the address */
4362                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4363                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4364                 break;
4365         case 2:   /* use bits [45:34] of the address */
4366                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4367                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4368                 break;
4369         case 3:   /* use bits [43:32] of the address */
4370                 vector = ((uc_addr->addr_bytes[4]) |
4371                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4372                 break;
4373         default:  /* Invalid mc_filter_type */
4374                 break;
4375         }
4376
4377         /* vector can only be 12-bits or boundary will be exceeded */
4378         vector &= 0xFFF;
4379         return vector;
4380 }
4381
4382 static int
4383 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4384                         uint8_t on)
4385 {
4386         uint32_t vector;
4387         uint32_t uta_idx;
4388         uint32_t reg_val;
4389         uint32_t uta_shift;
4390         uint32_t rc;
4391         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4392         const uint32_t ixgbe_uta_bit_shift = 5;
4393         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4394         const uint32_t bit1 = 0x1;
4395
4396         struct ixgbe_hw *hw =
4397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398         struct ixgbe_uta_info *uta_info =
4399                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4400
4401         /* The UTA table only exists on 82599 hardware and newer */
4402         if (hw->mac.type < ixgbe_mac_82599EB)
4403                 return -ENOTSUP;
4404
4405         vector = ixgbe_uta_vector(hw, mac_addr);
4406         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4407         uta_shift = vector & ixgbe_uta_bit_mask;
4408
4409         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4410         if (rc == on)
4411                 return 0;
4412
4413         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4414         if (on) {
4415                 uta_info->uta_in_use++;
4416                 reg_val |= (bit1 << uta_shift);
4417                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4418         } else {
4419                 uta_info->uta_in_use--;
4420                 reg_val &= ~(bit1 << uta_shift);
4421                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4422         }
4423
4424         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4425
4426         if (uta_info->uta_in_use > 0)
4427                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4428                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4429         else
4430                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4431
4432         return 0;
4433 }
4434
4435 static int
4436 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4437 {
4438         int i;
4439         struct ixgbe_hw *hw =
4440                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4441         struct ixgbe_uta_info *uta_info =
4442                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4443
4444         /* The UTA table only exists on 82599 hardware and newer */
4445         if (hw->mac.type < ixgbe_mac_82599EB)
4446                 return -ENOTSUP;
4447
4448         if (on) {
4449                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4450                         uta_info->uta_shadow[i] = ~0;
4451                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4452                 }
4453         } else {
4454                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4455                         uta_info->uta_shadow[i] = 0;
4456                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4457                 }
4458         }
4459         return 0;
4460
4461 }
4462
4463 uint32_t
4464 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4465 {
4466         uint32_t new_val = orig_val;
4467
4468         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4469                 new_val |= IXGBE_VMOLR_AUPE;
4470         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4471                 new_val |= IXGBE_VMOLR_ROMPE;
4472         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4473                 new_val |= IXGBE_VMOLR_ROPE;
4474         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4475                 new_val |= IXGBE_VMOLR_BAM;
4476         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4477                 new_val |= IXGBE_VMOLR_MPE;
4478
4479         return new_val;
4480 }
4481
4482 static int
4483 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4484                                uint16_t rx_mask, uint8_t on)
4485 {
4486         int val = 0;
4487
4488         struct ixgbe_hw *hw =
4489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4491
4492         if (hw->mac.type == ixgbe_mac_82598EB) {
4493                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4494                              " on 82599 hardware and newer");
4495                 return -ENOTSUP;
4496         }
4497         if (ixgbe_vmdq_mode_check(hw) < 0)
4498                 return -ENOTSUP;
4499
4500         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4501
4502         if (on)
4503                 vmolr |= val;
4504         else
4505                 vmolr &= ~val;
4506
4507         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4508
4509         return 0;
4510 }
4511
4512 static int
4513 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4514 {
4515         uint32_t reg, addr;
4516         uint32_t val;
4517         const uint8_t bit1 = 0x1;
4518
4519         struct ixgbe_hw *hw =
4520                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521
4522         if (ixgbe_vmdq_mode_check(hw) < 0)
4523                 return -ENOTSUP;
4524
4525         if (pool >= ETH_64_POOLS)
4526                 return -EINVAL;
4527
4528         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4529         if (pool >= 32) {
4530                 addr = IXGBE_VFRE(1);
4531                 val = bit1 << (pool - 32);
4532         } else {
4533                 addr = IXGBE_VFRE(0);
4534                 val = bit1 << pool;
4535         }
4536
4537         reg = IXGBE_READ_REG(hw, addr);
4538
4539         if (on)
4540                 reg |= val;
4541         else
4542                 reg &= ~val;
4543
4544         IXGBE_WRITE_REG(hw, addr, reg);
4545
4546         return 0;
4547 }
4548
4549 static int
4550 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4551 {
4552         uint32_t reg, addr;
4553         uint32_t val;
4554         const uint8_t bit1 = 0x1;
4555
4556         struct ixgbe_hw *hw =
4557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4558
4559         if (ixgbe_vmdq_mode_check(hw) < 0)
4560                 return -ENOTSUP;
4561
4562         if (pool >= ETH_64_POOLS)
4563                 return -EINVAL;
4564
4565         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4566         if (pool >= 32) {
4567                 addr = IXGBE_VFTE(1);
4568                 val = bit1 << (pool - 32);
4569         } else {
4570                 addr = IXGBE_VFTE(0);
4571                 val = bit1 << pool;
4572         }
4573
4574         reg = IXGBE_READ_REG(hw, addr);
4575
4576         if (on)
4577                 reg |= val;
4578         else
4579                 reg &= ~val;
4580
4581         IXGBE_WRITE_REG(hw, addr, reg);
4582
4583         return 0;
4584 }
4585
4586 static int
4587 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4588                         uint64_t pool_mask, uint8_t vlan_on)
4589 {
4590         int ret = 0;
4591         uint16_t pool_idx;
4592         struct ixgbe_hw *hw =
4593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594
4595         if (ixgbe_vmdq_mode_check(hw) < 0)
4596                 return -ENOTSUP;
4597         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4598                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4599                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4600                                                    vlan_on, false);
4601                         if (ret < 0)
4602                                 return ret;
4603                 }
4604         }
4605
4606         return ret;
4607 }
4608
4609 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4610 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4611 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4612 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4613 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4614         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4615         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4616
4617 static int
4618 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4619                         struct rte_eth_mirror_conf *mirror_conf,
4620                         uint8_t rule_id, uint8_t on)
4621 {
4622         uint32_t mr_ctl, vlvf;
4623         uint32_t mp_lsb = 0;
4624         uint32_t mv_msb = 0;
4625         uint32_t mv_lsb = 0;
4626         uint32_t mp_msb = 0;
4627         uint8_t i = 0;
4628         int reg_index = 0;
4629         uint64_t vlan_mask = 0;
4630
4631         const uint8_t pool_mask_offset = 32;
4632         const uint8_t vlan_mask_offset = 32;
4633         const uint8_t dst_pool_offset = 8;
4634         const uint8_t rule_mr_offset  = 4;
4635         const uint8_t mirror_rule_mask = 0x0F;
4636
4637         struct ixgbe_mirror_info *mr_info =
4638                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4639         struct ixgbe_hw *hw =
4640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         uint8_t mirror_type = 0;
4642
4643         if (ixgbe_vmdq_mode_check(hw) < 0)
4644                 return -ENOTSUP;
4645
4646         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4647                 return -EINVAL;
4648
4649         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4650                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4651                         mirror_conf->rule_type);
4652                 return -EINVAL;
4653         }
4654
4655         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4656                 mirror_type |= IXGBE_MRCTL_VLME;
4657                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4658                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4659                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4660                                 /* search vlan id related pool vlan filter index */
4661                                 reg_index = ixgbe_find_vlvf_slot(hw,
4662                                                  mirror_conf->vlan.vlan_id[i],
4663                                                  false);
4664                                 if (reg_index < 0)
4665                                         return -EINVAL;
4666                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4667                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4668                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4669                                       mirror_conf->vlan.vlan_id[i]))
4670                                         vlan_mask |= (1ULL << reg_index);
4671                                 else
4672                                         return -EINVAL;
4673                         }
4674                 }
4675
4676                 if (on) {
4677                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4678                         mv_msb = vlan_mask >> vlan_mask_offset;
4679
4680                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4681                                                 mirror_conf->vlan.vlan_mask;
4682                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4683                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4684                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4685                                                 mirror_conf->vlan.vlan_id[i];
4686                         }
4687                 } else {
4688                         mv_lsb = 0;
4689                         mv_msb = 0;
4690                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4691                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4692                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4693                 }
4694         }
4695
4696         /*
4697          * if enable pool mirror, write related pool mask register,if disable
4698          * pool mirror, clear PFMRVM register
4699          */
4700         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4701                 mirror_type |= IXGBE_MRCTL_VPME;
4702                 if (on) {
4703                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4704                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4705                         mr_info->mr_conf[rule_id].pool_mask =
4706                                         mirror_conf->pool_mask;
4707
4708                 } else {
4709                         mp_lsb = 0;
4710                         mp_msb = 0;
4711                         mr_info->mr_conf[rule_id].pool_mask = 0;
4712                 }
4713         }
4714         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4715                 mirror_type |= IXGBE_MRCTL_UPME;
4716         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4717                 mirror_type |= IXGBE_MRCTL_DPME;
4718
4719         /* read  mirror control register and recalculate it */
4720         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4721
4722         if (on) {
4723                 mr_ctl |= mirror_type;
4724                 mr_ctl &= mirror_rule_mask;
4725                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4726         } else
4727                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4728
4729         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4730         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4731
4732         /* write mirrror control  register */
4733         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4734
4735         /* write pool mirrror control  register */
4736         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4737                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4738                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4739                                 mp_msb);
4740         }
4741         /* write VLAN mirrror control  register */
4742         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4743                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4744                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4745                                 mv_msb);
4746         }
4747
4748         return 0;
4749 }
4750
4751 static int
4752 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4753 {
4754         int mr_ctl = 0;
4755         uint32_t lsb_val = 0;
4756         uint32_t msb_val = 0;
4757         const uint8_t rule_mr_offset = 4;
4758
4759         struct ixgbe_hw *hw =
4760                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761         struct ixgbe_mirror_info *mr_info =
4762                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4763
4764         if (ixgbe_vmdq_mode_check(hw) < 0)
4765                 return -ENOTSUP;
4766
4767         memset(&mr_info->mr_conf[rule_id], 0,
4768                 sizeof(struct rte_eth_mirror_conf));
4769
4770         /* clear PFVMCTL register */
4771         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4772
4773         /* clear pool mask register */
4774         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4775         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4776
4777         /* clear vlan mask register */
4778         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4779         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4780
4781         return 0;
4782 }
4783
4784 static int
4785 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4786 {
4787         uint32_t mask;
4788         struct ixgbe_hw *hw =
4789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790
4791         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4792         mask |= (1 << IXGBE_MISC_VEC_ID);
4793         RTE_SET_USED(queue_id);
4794         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4795
4796         rte_intr_enable(&dev->pci_dev->intr_handle);
4797
4798         return 0;
4799 }
4800
4801 static int
4802 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4803 {
4804         uint32_t mask;
4805         struct ixgbe_hw *hw =
4806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807
4808         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4809         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4810         RTE_SET_USED(queue_id);
4811         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4812
4813         return 0;
4814 }
4815
4816 static int
4817 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4818 {
4819         uint32_t mask;
4820         struct ixgbe_hw *hw =
4821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4822         struct ixgbe_interrupt *intr =
4823                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4824
4825         if (queue_id < 16) {
4826                 ixgbe_disable_intr(hw);
4827                 intr->mask |= (1 << queue_id);
4828                 ixgbe_enable_intr(dev);
4829         } else if (queue_id < 32) {
4830                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4831                 mask &= (1 << queue_id);
4832                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4833         } else if (queue_id < 64) {
4834                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4835                 mask &= (1 << (queue_id - 32));
4836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4837         }
4838         rte_intr_enable(&dev->pci_dev->intr_handle);
4839
4840         return 0;
4841 }
4842
4843 static int
4844 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4845 {
4846         uint32_t mask;
4847         struct ixgbe_hw *hw =
4848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849         struct ixgbe_interrupt *intr =
4850                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4851
4852         if (queue_id < 16) {
4853                 ixgbe_disable_intr(hw);
4854                 intr->mask &= ~(1 << queue_id);
4855                 ixgbe_enable_intr(dev);
4856         } else if (queue_id < 32) {
4857                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4858                 mask &= ~(1 << queue_id);
4859                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4860         } else if (queue_id < 64) {
4861                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4862                 mask &= ~(1 << (queue_id - 32));
4863                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4864         }
4865
4866         return 0;
4867 }
4868
4869 static void
4870 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4871                      uint8_t queue, uint8_t msix_vector)
4872 {
4873         uint32_t tmp, idx;
4874
4875         if (direction == -1) {
4876                 /* other causes */
4877                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4878                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4879                 tmp &= ~0xFF;
4880                 tmp |= msix_vector;
4881                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4882         } else {
4883                 /* rx or tx cause */
4884                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4885                 idx = ((16 * (queue & 1)) + (8 * direction));
4886                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4887                 tmp &= ~(0xFF << idx);
4888                 tmp |= (msix_vector << idx);
4889                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4890         }
4891 }
4892
4893 /**
4894  * set the IVAR registers, mapping interrupt causes to vectors
4895  * @param hw
4896  *  pointer to ixgbe_hw struct
4897  * @direction
4898  *  0 for Rx, 1 for Tx, -1 for other causes
4899  * @queue
4900  *  queue to map the corresponding interrupt to
4901  * @msix_vector
4902  *  the vector to map to the corresponding queue
4903  */
4904 static void
4905 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4906                    uint8_t queue, uint8_t msix_vector)
4907 {
4908         uint32_t tmp, idx;
4909
4910         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4911         if (hw->mac.type == ixgbe_mac_82598EB) {
4912                 if (direction == -1)
4913                         direction = 0;
4914                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4915                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4916                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4917                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4918                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4919         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4920                         (hw->mac.type == ixgbe_mac_X540)) {
4921                 if (direction == -1) {
4922                         /* other causes */
4923                         idx = ((queue & 1) * 8);
4924                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4925                         tmp &= ~(0xFF << idx);
4926                         tmp |= (msix_vector << idx);
4927                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4928                 } else {
4929                         /* rx or tx causes */
4930                         idx = ((16 * (queue & 1)) + (8 * direction));
4931                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4932                         tmp &= ~(0xFF << idx);
4933                         tmp |= (msix_vector << idx);
4934                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4935                 }
4936         }
4937 }
4938
4939 static void
4940 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4941 {
4942         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4943         struct ixgbe_hw *hw =
4944                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4945         uint32_t q_idx;
4946         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4947
4948         /* Configure VF other cause ivar */
4949         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4950
4951         /* won't configure msix register if no mapping is done
4952          * between intr vector and event fd.
4953          */
4954         if (!rte_intr_dp_is_en(intr_handle))
4955                 return;
4956
4957         /* Configure all RX queues of VF */
4958         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4959                 /* Force all queue use vector 0,
4960                  * as IXGBE_VF_MAXMSIVECOTR = 1
4961                  */
4962                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4963                 intr_handle->intr_vec[q_idx] = vector_idx;
4964         }
4965 }
4966
4967 /**
4968  * Sets up the hardware to properly generate MSI-X interrupts
4969  * @hw
4970  *  board private structure
4971  */
4972 static void
4973 ixgbe_configure_msix(struct rte_eth_dev *dev)
4974 {
4975         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4976         struct ixgbe_hw *hw =
4977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4979         uint32_t vec = IXGBE_MISC_VEC_ID;
4980         uint32_t mask;
4981         uint32_t gpie;
4982
4983         /* won't configure msix register if no mapping is done
4984          * between intr vector and event fd
4985          */
4986         if (!rte_intr_dp_is_en(intr_handle))
4987                 return;
4988
4989         if (rte_intr_allow_others(intr_handle))
4990                 vec = base = IXGBE_RX_VEC_START;
4991
4992         /* setup GPIE for MSI-x mode */
4993         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4994         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4995                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4996         /* auto clearing and auto setting corresponding bits in EIMS
4997          * when MSI-X interrupt is triggered
4998          */
4999         if (hw->mac.type == ixgbe_mac_82598EB) {
5000                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5001         } else {
5002                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5003                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5004         }
5005         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5006
5007         /* Populate the IVAR table and set the ITR values to the
5008          * corresponding register.
5009          */
5010         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5011              queue_id++) {
5012                 /* by default, 1:1 mapping */
5013                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5014                 intr_handle->intr_vec[queue_id] = vec;
5015                 if (vec < base + intr_handle->nb_efd - 1)
5016                         vec++;
5017         }
5018
5019         switch (hw->mac.type) {
5020         case ixgbe_mac_82598EB:
5021                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5022                                    IXGBE_MISC_VEC_ID);
5023                 break;
5024         case ixgbe_mac_82599EB:
5025         case ixgbe_mac_X540:
5026                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5027                 break;
5028         default:
5029                 break;
5030         }
5031         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5032                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5033
5034         /* set up to autoclear timer, and the vectors */
5035         mask = IXGBE_EIMS_ENABLE_MASK;
5036         mask &= ~(IXGBE_EIMS_OTHER |
5037                   IXGBE_EIMS_MAILBOX |
5038                   IXGBE_EIMS_LSC);
5039
5040         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5041 }
5042
5043 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5044         uint16_t queue_idx, uint16_t tx_rate)
5045 {
5046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047         uint32_t rf_dec, rf_int;
5048         uint32_t bcnrc_val;
5049         uint16_t link_speed = dev->data->dev_link.link_speed;
5050
5051         if (queue_idx >= hw->mac.max_tx_queues)
5052                 return -EINVAL;
5053
5054         if (tx_rate != 0) {
5055                 /* Calculate the rate factor values to set */
5056                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5057                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5058                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5059
5060                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5061                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5062                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5063                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5064         } else {
5065                 bcnrc_val = 0;
5066         }
5067
5068         /*
5069          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5070          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5071          * set as 0x4.
5072          */
5073         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5074                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5075                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5076                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5077                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5078         else
5079                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5080                         IXGBE_MMW_SIZE_DEFAULT);
5081
5082         /* Set RTTBCNRC of queue X */
5083         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5084         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5085         IXGBE_WRITE_FLUSH(hw);
5086
5087         return 0;
5088 }
5089
5090 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5091         uint16_t tx_rate, uint64_t q_msk)
5092 {
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         struct ixgbe_vf_info *vfinfo =
5095                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5096         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5097         uint32_t queue_stride =
5098                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5099         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5100         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5101         uint16_t total_rate = 0;
5102
5103         if (queue_end >= hw->mac.max_tx_queues)
5104                 return -EINVAL;
5105
5106         if (vfinfo != NULL) {
5107                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5108                         if (vf_idx == vf)
5109                                 continue;
5110                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5111                                 idx++)
5112                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5113                 }
5114         } else
5115                 return -EINVAL;
5116
5117         /* Store tx_rate for this vf. */
5118         for (idx = 0; idx < nb_q_per_pool; idx++) {
5119                 if (((uint64_t)0x1 << idx) & q_msk) {
5120                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5121                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5122                         total_rate += tx_rate;
5123                 }
5124         }
5125
5126         if (total_rate > dev->data->dev_link.link_speed) {
5127                 /*
5128                  * Reset stored TX rate of the VF if it causes exceed
5129                  * link speed.
5130                  */
5131                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5132                 return -EINVAL;
5133         }
5134
5135         /* Set RTTBCNRC of each queue/pool for vf X  */
5136         for (; queue_idx <= queue_end; queue_idx++) {
5137                 if (0x1 & q_msk)
5138                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5139                 q_msk = q_msk >> 1;
5140         }
5141
5142         return 0;
5143 }
5144
5145 static void
5146 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5147                      __attribute__((unused)) uint32_t index,
5148                      __attribute__((unused)) uint32_t pool)
5149 {
5150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5151         int diag;
5152
5153         /*
5154          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5155          * operation. Trap this case to avoid exhausting the [very limited]
5156          * set of PF resources used to store VF MAC addresses.
5157          */
5158         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5159                 return;
5160         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5161         if (diag == 0)
5162                 return;
5163         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5164 }
5165
5166 static void
5167 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5168 {
5169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5171         struct ether_addr *mac_addr;
5172         uint32_t i;
5173         int diag;
5174
5175         /*
5176          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5177          * not support the deletion of a given MAC address.
5178          * Instead, it imposes to delete all MAC addresses, then to add again
5179          * all MAC addresses with the exception of the one to be deleted.
5180          */
5181         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5182
5183         /*
5184          * Add again all MAC addresses, with the exception of the deleted one
5185          * and of the permanent MAC address.
5186          */
5187         for (i = 0, mac_addr = dev->data->mac_addrs;
5188              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5189                 /* Skip the deleted MAC address */
5190                 if (i == index)
5191                         continue;
5192                 /* Skip NULL MAC addresses */
5193                 if (is_zero_ether_addr(mac_addr))
5194                         continue;
5195                 /* Skip the permanent MAC address */
5196                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5197                         continue;
5198                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5199                 if (diag != 0)
5200                         PMD_DRV_LOG(ERR,
5201                                     "Adding again MAC address "
5202                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5203                                     "diag=%d",
5204                                     mac_addr->addr_bytes[0],
5205                                     mac_addr->addr_bytes[1],
5206                                     mac_addr->addr_bytes[2],
5207                                     mac_addr->addr_bytes[3],
5208                                     mac_addr->addr_bytes[4],
5209                                     mac_addr->addr_bytes[5],
5210                                     diag);
5211         }
5212 }
5213
5214 static void
5215 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5216 {
5217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5218
5219         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5220 }
5221
5222 #define MAC_TYPE_FILTER_SUP(type)    do {\
5223         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5224                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5225                 (type) != ixgbe_mac_X550EM_a)\
5226                 return -ENOTSUP;\
5227 } while (0)
5228
5229 static int
5230 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5231                         struct rte_eth_syn_filter *filter,
5232                         bool add)
5233 {
5234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         uint32_t synqf;
5236
5237         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5238                 return -EINVAL;
5239
5240         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5241
5242         if (add) {
5243                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5244                         return -EINVAL;
5245                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5246                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5247
5248                 if (filter->hig_pri)
5249                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5250                 else
5251                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5252         } else {
5253                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5254                         return -ENOENT;
5255                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5256         }
5257         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5258         IXGBE_WRITE_FLUSH(hw);
5259         return 0;
5260 }
5261
5262 static int
5263 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5264                         struct rte_eth_syn_filter *filter)
5265 {
5266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5267         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5268
5269         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5270                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5271                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5272                 return 0;
5273         }
5274         return -ENOENT;
5275 }
5276
5277 static int
5278 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5279                         enum rte_filter_op filter_op,
5280                         void *arg)
5281 {
5282         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5283         int ret;
5284
5285         MAC_TYPE_FILTER_SUP(hw->mac.type);
5286
5287         if (filter_op == RTE_ETH_FILTER_NOP)
5288                 return 0;
5289
5290         if (arg == NULL) {
5291                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5292                             filter_op);
5293                 return -EINVAL;
5294         }
5295
5296         switch (filter_op) {
5297         case RTE_ETH_FILTER_ADD:
5298                 ret = ixgbe_syn_filter_set(dev,
5299                                 (struct rte_eth_syn_filter *)arg,
5300                                 TRUE);
5301                 break;
5302         case RTE_ETH_FILTER_DELETE:
5303                 ret = ixgbe_syn_filter_set(dev,
5304                                 (struct rte_eth_syn_filter *)arg,
5305                                 FALSE);
5306                 break;
5307         case RTE_ETH_FILTER_GET:
5308                 ret = ixgbe_syn_filter_get(dev,
5309                                 (struct rte_eth_syn_filter *)arg);
5310                 break;
5311         default:
5312                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5313                 ret = -EINVAL;
5314                 break;
5315         }
5316
5317         return ret;
5318 }
5319
5320
5321 static inline enum ixgbe_5tuple_protocol
5322 convert_protocol_type(uint8_t protocol_value)
5323 {
5324         if (protocol_value == IPPROTO_TCP)
5325                 return IXGBE_FILTER_PROTOCOL_TCP;
5326         else if (protocol_value == IPPROTO_UDP)
5327                 return IXGBE_FILTER_PROTOCOL_UDP;
5328         else if (protocol_value == IPPROTO_SCTP)
5329                 return IXGBE_FILTER_PROTOCOL_SCTP;
5330         else
5331                 return IXGBE_FILTER_PROTOCOL_NONE;
5332 }
5333
5334 /*
5335  * add a 5tuple filter
5336  *
5337  * @param
5338  * dev: Pointer to struct rte_eth_dev.
5339  * index: the index the filter allocates.
5340  * filter: ponter to the filter that will be added.
5341  * rx_queue: the queue id the filter assigned to.
5342  *
5343  * @return
5344  *    - On success, zero.
5345  *    - On failure, a negative value.
5346  */
5347 static int
5348 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5349                         struct ixgbe_5tuple_filter *filter)
5350 {
5351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5352         struct ixgbe_filter_info *filter_info =
5353                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5354         int i, idx, shift;
5355         uint32_t ftqf, sdpqf;
5356         uint32_t l34timir = 0;
5357         uint8_t mask = 0xff;
5358
5359         /*
5360          * look for an unused 5tuple filter index,
5361          * and insert the filter to list.
5362          */
5363         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5364                 idx = i / (sizeof(uint32_t) * NBBY);
5365                 shift = i % (sizeof(uint32_t) * NBBY);
5366                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5367                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5368                         filter->index = i;
5369                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5370                                           filter,
5371                                           entries);
5372                         break;
5373                 }
5374         }
5375         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5376                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5377                 return -ENOSYS;
5378         }
5379
5380         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5381                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5382         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5383
5384         ftqf = (uint32_t)(filter->filter_info.proto &
5385                 IXGBE_FTQF_PROTOCOL_MASK);
5386         ftqf |= (uint32_t)((filter->filter_info.priority &
5387                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5388         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5389                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5390         if (filter->filter_info.dst_ip_mask == 0)
5391                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5392         if (filter->filter_info.src_port_mask == 0)
5393                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5394         if (filter->filter_info.dst_port_mask == 0)
5395                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5396         if (filter->filter_info.proto_mask == 0)
5397                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5398         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5399         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5400         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5401
5402         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5403         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5404         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5405         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5406
5407         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5408         l34timir |= (uint32_t)(filter->queue <<
5409                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5410         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5411         return 0;
5412 }
5413
5414 /*
5415  * remove a 5tuple filter
5416  *
5417  * @param
5418  * dev: Pointer to struct rte_eth_dev.
5419  * filter: the pointer of the filter will be removed.
5420  */
5421 static void
5422 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5423                         struct ixgbe_5tuple_filter *filter)
5424 {
5425         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426         struct ixgbe_filter_info *filter_info =
5427                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5428         uint16_t index = filter->index;
5429
5430         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5431                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5432         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5433         rte_free(filter);
5434
5435         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5436         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5437         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5438         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5439         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5440 }
5441
5442 static int
5443 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5444 {
5445         struct ixgbe_hw *hw;
5446         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5447
5448         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5449
5450         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5451                 return -EINVAL;
5452
5453         /* refuse mtu that requires the support of scattered packets when this
5454          * feature has not been enabled before.
5455          */
5456         if (!dev->data->scattered_rx &&
5457             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5458              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5459                 return -EINVAL;
5460
5461         /*
5462          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5463          * request of the version 2.0 of the mailbox API.
5464          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5465          * of the mailbox API.
5466          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5467          * prior to 3.11.33 which contains the following change:
5468          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5469          */
5470         ixgbevf_rlpml_set_vf(hw, max_frame);
5471
5472         /* update max frame size */
5473         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5474         return 0;
5475 }
5476
5477 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5478         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5479                 return -ENOTSUP;\
5480 } while (0)
5481
5482 static inline struct ixgbe_5tuple_filter *
5483 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5484                         struct ixgbe_5tuple_filter_info *key)
5485 {
5486         struct ixgbe_5tuple_filter *it;
5487
5488         TAILQ_FOREACH(it, filter_list, entries) {
5489                 if (memcmp(key, &it->filter_info,
5490                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5491                         return it;
5492                 }
5493         }
5494         return NULL;
5495 }
5496
5497 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5498 static inline int
5499 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5500                         struct ixgbe_5tuple_filter_info *filter_info)
5501 {
5502         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5503                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5504                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5505                 return -EINVAL;
5506
5507         switch (filter->dst_ip_mask) {
5508         case UINT32_MAX:
5509                 filter_info->dst_ip_mask = 0;
5510                 filter_info->dst_ip = filter->dst_ip;
5511                 break;
5512         case 0:
5513                 filter_info->dst_ip_mask = 1;
5514                 break;
5515         default:
5516                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5517                 return -EINVAL;
5518         }
5519
5520         switch (filter->src_ip_mask) {
5521         case UINT32_MAX:
5522                 filter_info->src_ip_mask = 0;
5523                 filter_info->src_ip = filter->src_ip;
5524                 break;
5525         case 0:
5526                 filter_info->src_ip_mask = 1;
5527                 break;
5528         default:
5529                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5530                 return -EINVAL;
5531         }
5532
5533         switch (filter->dst_port_mask) {
5534         case UINT16_MAX:
5535                 filter_info->dst_port_mask = 0;
5536                 filter_info->dst_port = filter->dst_port;
5537                 break;
5538         case 0:
5539                 filter_info->dst_port_mask = 1;
5540                 break;
5541         default:
5542                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5543                 return -EINVAL;
5544         }
5545
5546         switch (filter->src_port_mask) {
5547         case UINT16_MAX:
5548                 filter_info->src_port_mask = 0;
5549                 filter_info->src_port = filter->src_port;
5550                 break;
5551         case 0:
5552                 filter_info->src_port_mask = 1;
5553                 break;
5554         default:
5555                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5556                 return -EINVAL;
5557         }
5558
5559         switch (filter->proto_mask) {
5560         case UINT8_MAX:
5561                 filter_info->proto_mask = 0;
5562                 filter_info->proto =
5563                         convert_protocol_type(filter->proto);
5564                 break;
5565         case 0:
5566                 filter_info->proto_mask = 1;
5567                 break;
5568         default:
5569                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5570                 return -EINVAL;
5571         }
5572
5573         filter_info->priority = (uint8_t)filter->priority;
5574         return 0;
5575 }
5576
5577 /*
5578  * add or delete a ntuple filter
5579  *
5580  * @param
5581  * dev: Pointer to struct rte_eth_dev.
5582  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5583  * add: if true, add filter, if false, remove filter
5584  *
5585  * @return
5586  *    - On success, zero.
5587  *    - On failure, a negative value.
5588  */
5589 static int
5590 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5591                         struct rte_eth_ntuple_filter *ntuple_filter,
5592                         bool add)
5593 {
5594         struct ixgbe_filter_info *filter_info =
5595                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5596         struct ixgbe_5tuple_filter_info filter_5tuple;
5597         struct ixgbe_5tuple_filter *filter;
5598         int ret;
5599
5600         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5601                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5602                 return -EINVAL;
5603         }
5604
5605         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5606         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5607         if (ret < 0)
5608                 return ret;
5609
5610         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5611                                          &filter_5tuple);
5612         if (filter != NULL && add) {
5613                 PMD_DRV_LOG(ERR, "filter exists.");
5614                 return -EEXIST;
5615         }
5616         if (filter == NULL && !add) {
5617                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5618                 return -ENOENT;
5619         }
5620
5621         if (add) {
5622                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5623                                 sizeof(struct ixgbe_5tuple_filter), 0);
5624                 if (filter == NULL)
5625                         return -ENOMEM;
5626                 (void)rte_memcpy(&filter->filter_info,
5627                                  &filter_5tuple,
5628                                  sizeof(struct ixgbe_5tuple_filter_info));
5629                 filter->queue = ntuple_filter->queue;
5630                 ret = ixgbe_add_5tuple_filter(dev, filter);
5631                 if (ret < 0) {
5632                         rte_free(filter);
5633                         return ret;
5634                 }
5635         } else
5636                 ixgbe_remove_5tuple_filter(dev, filter);
5637
5638         return 0;
5639 }
5640
5641 /*
5642  * get a ntuple filter
5643  *
5644  * @param
5645  * dev: Pointer to struct rte_eth_dev.
5646  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5647  *
5648  * @return
5649  *    - On success, zero.
5650  *    - On failure, a negative value.
5651  */
5652 static int
5653 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5654                         struct rte_eth_ntuple_filter *ntuple_filter)
5655 {
5656         struct ixgbe_filter_info *filter_info =
5657                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5658         struct ixgbe_5tuple_filter_info filter_5tuple;
5659         struct ixgbe_5tuple_filter *filter;
5660         int ret;
5661
5662         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5663                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5664                 return -EINVAL;
5665         }
5666
5667         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5668         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5669         if (ret < 0)
5670                 return ret;
5671
5672         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5673                                          &filter_5tuple);
5674         if (filter == NULL) {
5675                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5676                 return -ENOENT;
5677         }
5678         ntuple_filter->queue = filter->queue;
5679         return 0;
5680 }
5681
5682 /*
5683  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5684  * @dev: pointer to rte_eth_dev structure
5685  * @filter_op:operation will be taken.
5686  * @arg: a pointer to specific structure corresponding to the filter_op
5687  *
5688  * @return
5689  *    - On success, zero.
5690  *    - On failure, a negative value.
5691  */
5692 static int
5693 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5694                                 enum rte_filter_op filter_op,
5695                                 void *arg)
5696 {
5697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698         int ret;
5699
5700         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5701
5702         if (filter_op == RTE_ETH_FILTER_NOP)
5703                 return 0;
5704
5705         if (arg == NULL) {
5706                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5707                             filter_op);
5708                 return -EINVAL;
5709         }
5710
5711         switch (filter_op) {
5712         case RTE_ETH_FILTER_ADD:
5713                 ret = ixgbe_add_del_ntuple_filter(dev,
5714                         (struct rte_eth_ntuple_filter *)arg,
5715                         TRUE);
5716                 break;
5717         case RTE_ETH_FILTER_DELETE:
5718                 ret = ixgbe_add_del_ntuple_filter(dev,
5719                         (struct rte_eth_ntuple_filter *)arg,
5720                         FALSE);
5721                 break;
5722         case RTE_ETH_FILTER_GET:
5723                 ret = ixgbe_get_ntuple_filter(dev,
5724                         (struct rte_eth_ntuple_filter *)arg);
5725                 break;
5726         default:
5727                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5728                 ret = -EINVAL;
5729                 break;
5730         }
5731         return ret;
5732 }
5733
5734 static inline int
5735 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5736                         uint16_t ethertype)
5737 {
5738         int i;
5739
5740         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5741                 if (filter_info->ethertype_filters[i] == ethertype &&
5742                     (filter_info->ethertype_mask & (1 << i)))
5743                         return i;
5744         }
5745         return -1;
5746 }
5747
5748 static inline int
5749 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5750                         uint16_t ethertype)
5751 {
5752         int i;
5753
5754         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5755                 if (!(filter_info->ethertype_mask & (1 << i))) {
5756                         filter_info->ethertype_mask |= 1 << i;
5757                         filter_info->ethertype_filters[i] = ethertype;
5758                         return i;
5759                 }
5760         }
5761         return -1;
5762 }
5763
5764 static inline int
5765 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5766                         uint8_t idx)
5767 {
5768         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5769                 return -1;
5770         filter_info->ethertype_mask &= ~(1 << idx);
5771         filter_info->ethertype_filters[idx] = 0;
5772         return idx;
5773 }
5774
5775 static int
5776 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5777                         struct rte_eth_ethertype_filter *filter,
5778                         bool add)
5779 {
5780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781         struct ixgbe_filter_info *filter_info =
5782                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5783         uint32_t etqf = 0;
5784         uint32_t etqs = 0;
5785         int ret;
5786
5787         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5788                 return -EINVAL;
5789
5790         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5791                 filter->ether_type == ETHER_TYPE_IPv6) {
5792                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5793                         " ethertype filter.", filter->ether_type);
5794                 return -EINVAL;
5795         }
5796
5797         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5798                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5799                 return -EINVAL;
5800         }
5801         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5802                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5803                 return -EINVAL;
5804         }
5805
5806         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5807         if (ret >= 0 && add) {
5808                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5809                             filter->ether_type);
5810                 return -EEXIST;
5811         }
5812         if (ret < 0 && !add) {
5813                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5814                             filter->ether_type);
5815                 return -ENOENT;
5816         }
5817
5818         if (add) {
5819                 ret = ixgbe_ethertype_filter_insert(filter_info,
5820                         filter->ether_type);
5821                 if (ret < 0) {
5822                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5823                         return -ENOSYS;
5824                 }
5825                 etqf = IXGBE_ETQF_FILTER_EN;
5826                 etqf |= (uint32_t)filter->ether_type;
5827                 etqs |= (uint32_t)((filter->queue <<
5828                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5829                                     IXGBE_ETQS_RX_QUEUE);
5830                 etqs |= IXGBE_ETQS_QUEUE_EN;
5831         } else {
5832                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5833                 if (ret < 0)
5834                         return -ENOSYS;
5835         }
5836         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5837         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5838         IXGBE_WRITE_FLUSH(hw);
5839
5840         return 0;
5841 }
5842
5843 static int
5844 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5845                         struct rte_eth_ethertype_filter *filter)
5846 {
5847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5848         struct ixgbe_filter_info *filter_info =
5849                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5850         uint32_t etqf, etqs;
5851         int ret;
5852
5853         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5854         if (ret < 0) {
5855                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5856                             filter->ether_type);
5857                 return -ENOENT;
5858         }
5859
5860         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5861         if (etqf & IXGBE_ETQF_FILTER_EN) {
5862                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5863                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5864                 filter->flags = 0;
5865                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5866                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5867                 return 0;
5868         }
5869         return -ENOENT;
5870 }
5871
5872 /*
5873  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5874  * @dev: pointer to rte_eth_dev structure
5875  * @filter_op:operation will be taken.
5876  * @arg: a pointer to specific structure corresponding to the filter_op
5877  */
5878 static int
5879 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5880                                 enum rte_filter_op filter_op,
5881                                 void *arg)
5882 {
5883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5884         int ret;
5885
5886         MAC_TYPE_FILTER_SUP(hw->mac.type);
5887
5888         if (filter_op == RTE_ETH_FILTER_NOP)
5889                 return 0;
5890
5891         if (arg == NULL) {
5892                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5893                             filter_op);
5894                 return -EINVAL;
5895         }
5896
5897         switch (filter_op) {
5898         case RTE_ETH_FILTER_ADD:
5899                 ret = ixgbe_add_del_ethertype_filter(dev,
5900                         (struct rte_eth_ethertype_filter *)arg,
5901                         TRUE);
5902                 break;
5903         case RTE_ETH_FILTER_DELETE:
5904                 ret = ixgbe_add_del_ethertype_filter(dev,
5905                         (struct rte_eth_ethertype_filter *)arg,
5906                         FALSE);
5907                 break;
5908         case RTE_ETH_FILTER_GET:
5909                 ret = ixgbe_get_ethertype_filter(dev,
5910                         (struct rte_eth_ethertype_filter *)arg);
5911                 break;
5912         default:
5913                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5914                 ret = -EINVAL;
5915                 break;
5916         }
5917         return ret;
5918 }
5919
5920 static int
5921 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5922                      enum rte_filter_type filter_type,
5923                      enum rte_filter_op filter_op,
5924                      void *arg)
5925 {
5926         int ret = -EINVAL;
5927
5928         switch (filter_type) {
5929         case RTE_ETH_FILTER_NTUPLE:
5930                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5931                 break;
5932         case RTE_ETH_FILTER_ETHERTYPE:
5933                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5934                 break;
5935         case RTE_ETH_FILTER_SYN:
5936                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5937                 break;
5938         case RTE_ETH_FILTER_FDIR:
5939                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5940                 break;
5941         case RTE_ETH_FILTER_L2_TUNNEL:
5942                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5943                 break;
5944         default:
5945                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5946                                                         filter_type);
5947                 break;
5948         }
5949
5950         return ret;
5951 }
5952
5953 static u8 *
5954 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5955                         u8 **mc_addr_ptr, u32 *vmdq)
5956 {
5957         u8 *mc_addr;
5958
5959         *vmdq = 0;
5960         mc_addr = *mc_addr_ptr;
5961         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5962         return mc_addr;
5963 }
5964
5965 static int
5966 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5967                           struct ether_addr *mc_addr_set,
5968                           uint32_t nb_mc_addr)
5969 {
5970         struct ixgbe_hw *hw;
5971         u8 *mc_addr_list;
5972
5973         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974         mc_addr_list = (u8 *)mc_addr_set;
5975         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5976                                          ixgbe_dev_addr_list_itr, TRUE);
5977 }
5978
5979 static uint64_t
5980 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5981 {
5982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983         uint64_t systime_cycles;
5984
5985         switch (hw->mac.type) {
5986         case ixgbe_mac_X550:
5987         case ixgbe_mac_X550EM_x:
5988         case ixgbe_mac_X550EM_a:
5989                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5990                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5991                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5992                                 * NSEC_PER_SEC;
5993                 break;
5994         default:
5995                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5996                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5997                                 << 32;
5998         }
5999
6000         return systime_cycles;
6001 }
6002
6003 static uint64_t
6004 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6005 {
6006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007         uint64_t rx_tstamp_cycles;
6008
6009         switch (hw->mac.type) {
6010         case ixgbe_mac_X550:
6011         case ixgbe_mac_X550EM_x:
6012         case ixgbe_mac_X550EM_a:
6013                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6014                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6015                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6016                                 * NSEC_PER_SEC;
6017                 break;
6018         default:
6019                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6020                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6021                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6022                                 << 32;
6023         }
6024
6025         return rx_tstamp_cycles;
6026 }
6027
6028 static uint64_t
6029 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6030 {
6031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032         uint64_t tx_tstamp_cycles;
6033
6034         switch (hw->mac.type) {
6035         case ixgbe_mac_X550:
6036         case ixgbe_mac_X550EM_x:
6037         case ixgbe_mac_X550EM_a:
6038                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6039                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6040                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6041                                 * NSEC_PER_SEC;
6042                 break;
6043         default:
6044                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6045                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6046                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6047                                 << 32;
6048         }
6049
6050         return tx_tstamp_cycles;
6051 }
6052
6053 static void
6054 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6055 {
6056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6057         struct ixgbe_adapter *adapter =
6058                 (struct ixgbe_adapter *)dev->data->dev_private;
6059         struct rte_eth_link link;
6060         uint32_t incval = 0;
6061         uint32_t shift = 0;
6062
6063         /* Get current link speed. */
6064         memset(&link, 0, sizeof(link));
6065         ixgbe_dev_link_update(dev, 1);
6066         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6067
6068         switch (link.link_speed) {
6069         case ETH_SPEED_NUM_100M:
6070                 incval = IXGBE_INCVAL_100;
6071                 shift = IXGBE_INCVAL_SHIFT_100;
6072                 break;
6073         case ETH_SPEED_NUM_1G:
6074                 incval = IXGBE_INCVAL_1GB;
6075                 shift = IXGBE_INCVAL_SHIFT_1GB;
6076                 break;
6077         case ETH_SPEED_NUM_10G:
6078         default:
6079                 incval = IXGBE_INCVAL_10GB;
6080                 shift = IXGBE_INCVAL_SHIFT_10GB;
6081                 break;
6082         }
6083
6084         switch (hw->mac.type) {
6085         case ixgbe_mac_X550:
6086         case ixgbe_mac_X550EM_x:
6087         case ixgbe_mac_X550EM_a:
6088                 /* Independent of link speed. */
6089                 incval = 1;
6090                 /* Cycles read will be interpreted as ns. */
6091                 shift = 0;
6092                 /* Fall-through */
6093         case ixgbe_mac_X540:
6094                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6095                 break;
6096         case ixgbe_mac_82599EB:
6097                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6098                 shift -= IXGBE_INCVAL_SHIFT_82599;
6099                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6100                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6101                 break;
6102         default:
6103                 /* Not supported. */
6104                 return;
6105         }
6106
6107         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6108         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6109         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6110
6111         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6112         adapter->systime_tc.cc_shift = shift;
6113         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6114
6115         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6116         adapter->rx_tstamp_tc.cc_shift = shift;
6117         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6118
6119         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6120         adapter->tx_tstamp_tc.cc_shift = shift;
6121         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6122 }
6123
6124 static int
6125 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6126 {
6127         struct ixgbe_adapter *adapter =
6128                         (struct ixgbe_adapter *)dev->data->dev_private;
6129
6130         adapter->systime_tc.nsec += delta;
6131         adapter->rx_tstamp_tc.nsec += delta;
6132         adapter->tx_tstamp_tc.nsec += delta;
6133
6134         return 0;
6135 }
6136
6137 static int
6138 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6139 {
6140         uint64_t ns;
6141         struct ixgbe_adapter *adapter =
6142                         (struct ixgbe_adapter *)dev->data->dev_private;
6143
6144         ns = rte_timespec_to_ns(ts);
6145         /* Set the timecounters to a new value. */
6146         adapter->systime_tc.nsec = ns;
6147         adapter->rx_tstamp_tc.nsec = ns;
6148         adapter->tx_tstamp_tc.nsec = ns;
6149
6150         return 0;
6151 }
6152
6153 static int
6154 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6155 {
6156         uint64_t ns, systime_cycles;
6157         struct ixgbe_adapter *adapter =
6158                         (struct ixgbe_adapter *)dev->data->dev_private;
6159
6160         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6161         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6162         *ts = rte_ns_to_timespec(ns);
6163
6164         return 0;
6165 }
6166
6167 static int
6168 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6169 {
6170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171         uint32_t tsync_ctl;
6172         uint32_t tsauxc;
6173
6174         /* Stop the timesync system time. */
6175         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6176         /* Reset the timesync system time value. */
6177         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6178         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6179
6180         /* Enable system time for platforms where it isn't on by default. */
6181         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6182         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6183         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6184
6185         ixgbe_start_timecounters(dev);
6186
6187         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6188         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6189                         (ETHER_TYPE_1588 |
6190                          IXGBE_ETQF_FILTER_EN |
6191                          IXGBE_ETQF_1588));
6192
6193         /* Enable timestamping of received PTP packets. */
6194         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6195         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6196         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6197
6198         /* Enable timestamping of transmitted PTP packets. */
6199         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6200         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6201         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6202
6203         IXGBE_WRITE_FLUSH(hw);
6204
6205         return 0;
6206 }
6207
6208 static int
6209 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6210 {
6211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         uint32_t tsync_ctl;
6213
6214         /* Disable timestamping of transmitted PTP packets. */
6215         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6216         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6217         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6218
6219         /* Disable timestamping of received PTP packets. */
6220         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6221         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6222         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6223
6224         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6225         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6226
6227         /* Stop incrementating the System Time registers. */
6228         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6229
6230         return 0;
6231 }
6232
6233 static int
6234 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6235                                  struct timespec *timestamp,
6236                                  uint32_t flags __rte_unused)
6237 {
6238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6239         struct ixgbe_adapter *adapter =
6240                 (struct ixgbe_adapter *)dev->data->dev_private;
6241         uint32_t tsync_rxctl;
6242         uint64_t rx_tstamp_cycles;
6243         uint64_t ns;
6244
6245         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6246         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6247                 return -EINVAL;
6248
6249         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6250         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6251         *timestamp = rte_ns_to_timespec(ns);
6252
6253         return  0;
6254 }
6255
6256 static int
6257 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6258                                  struct timespec *timestamp)
6259 {
6260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6261         struct ixgbe_adapter *adapter =
6262                 (struct ixgbe_adapter *)dev->data->dev_private;
6263         uint32_t tsync_txctl;
6264         uint64_t tx_tstamp_cycles;
6265         uint64_t ns;
6266
6267         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6268         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6269                 return -EINVAL;
6270
6271         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6272         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6273         *timestamp = rte_ns_to_timespec(ns);
6274
6275         return 0;
6276 }
6277
6278 static int
6279 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6280 {
6281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6282         int count = 0;
6283         int g_ind = 0;
6284         const struct reg_info *reg_group;
6285         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6286                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6287
6288         while ((reg_group = reg_set[g_ind++]))
6289                 count += ixgbe_regs_group_count(reg_group);
6290
6291         return count;
6292 }
6293
6294 static int
6295 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6296 {
6297         int count = 0;
6298         int g_ind = 0;
6299         const struct reg_info *reg_group;
6300
6301         while ((reg_group = ixgbevf_regs[g_ind++]))
6302                 count += ixgbe_regs_group_count(reg_group);
6303
6304         return count;
6305 }
6306
6307 static int
6308 ixgbe_get_regs(struct rte_eth_dev *dev,
6309               struct rte_dev_reg_info *regs)
6310 {
6311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6312         uint32_t *data = regs->data;
6313         int g_ind = 0;
6314         int count = 0;
6315         const struct reg_info *reg_group;
6316         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6317                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6318
6319         /* Support only full register dump */
6320         if ((regs->length == 0) ||
6321             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6322                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6323                         hw->device_id;
6324                 while ((reg_group = reg_set[g_ind++]))
6325                         count += ixgbe_read_regs_group(dev, &data[count],
6326                                 reg_group);
6327                 return 0;
6328         }
6329
6330         return -ENOTSUP;
6331 }
6332
6333 static int
6334 ixgbevf_get_regs(struct rte_eth_dev *dev,
6335                 struct rte_dev_reg_info *regs)
6336 {
6337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6338         uint32_t *data = regs->data;
6339         int g_ind = 0;
6340         int count = 0;
6341         const struct reg_info *reg_group;
6342
6343         /* Support only full register dump */
6344         if ((regs->length == 0) ||
6345             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6346                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6347                         hw->device_id;
6348                 while ((reg_group = ixgbevf_regs[g_ind++]))
6349                         count += ixgbe_read_regs_group(dev, &data[count],
6350                                                       reg_group);
6351                 return 0;
6352         }
6353
6354         return -ENOTSUP;
6355 }
6356
6357 static int
6358 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6359 {
6360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6361
6362         /* Return unit is byte count */
6363         return hw->eeprom.word_size * 2;
6364 }
6365
6366 static int
6367 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6368                 struct rte_dev_eeprom_info *in_eeprom)
6369 {
6370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6371         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6372         uint16_t *data = in_eeprom->data;
6373         int first, length;
6374
6375         first = in_eeprom->offset >> 1;
6376         length = in_eeprom->length >> 1;
6377         if ((first > hw->eeprom.word_size) ||
6378             ((first + length) > hw->eeprom.word_size))
6379                 return -EINVAL;
6380
6381         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6382
6383         return eeprom->ops.read_buffer(hw, first, length, data);
6384 }
6385
6386 static int
6387 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6388                 struct rte_dev_eeprom_info *in_eeprom)
6389 {
6390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6391         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6392         uint16_t *data = in_eeprom->data;
6393         int first, length;
6394
6395         first = in_eeprom->offset >> 1;
6396         length = in_eeprom->length >> 1;
6397         if ((first > hw->eeprom.word_size) ||
6398             ((first + length) > hw->eeprom.word_size))
6399                 return -EINVAL;
6400
6401         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6402
6403         return eeprom->ops.write_buffer(hw,  first, length, data);
6404 }
6405
6406 uint16_t
6407 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6408         switch (mac_type) {
6409         case ixgbe_mac_X550:
6410         case ixgbe_mac_X550EM_x:
6411         case ixgbe_mac_X550EM_a:
6412                 return ETH_RSS_RETA_SIZE_512;
6413         case ixgbe_mac_X550_vf:
6414         case ixgbe_mac_X550EM_x_vf:
6415         case ixgbe_mac_X550EM_a_vf:
6416                 return ETH_RSS_RETA_SIZE_64;
6417         default:
6418                 return ETH_RSS_RETA_SIZE_128;
6419         }
6420 }
6421
6422 uint32_t
6423 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6424         switch (mac_type) {
6425         case ixgbe_mac_X550:
6426         case ixgbe_mac_X550EM_x:
6427         case ixgbe_mac_X550EM_a:
6428                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6429                         return IXGBE_RETA(reta_idx >> 2);
6430                 else
6431                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6432         case ixgbe_mac_X550_vf:
6433         case ixgbe_mac_X550EM_x_vf:
6434         case ixgbe_mac_X550EM_a_vf:
6435                 return IXGBE_VFRETA(reta_idx >> 2);
6436         default:
6437                 return IXGBE_RETA(reta_idx >> 2);
6438         }
6439 }
6440
6441 uint32_t
6442 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6443         switch (mac_type) {
6444         case ixgbe_mac_X550_vf:
6445         case ixgbe_mac_X550EM_x_vf:
6446         case ixgbe_mac_X550EM_a_vf:
6447                 return IXGBE_VFMRQC;
6448         default:
6449                 return IXGBE_MRQC;
6450         }
6451 }
6452
6453 uint32_t
6454 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6455         switch (mac_type) {
6456         case ixgbe_mac_X550_vf:
6457         case ixgbe_mac_X550EM_x_vf:
6458         case ixgbe_mac_X550EM_a_vf:
6459                 return IXGBE_VFRSSRK(i);
6460         default:
6461                 return IXGBE_RSSRK(i);
6462         }
6463 }
6464
6465 bool
6466 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6467         switch (mac_type) {
6468         case ixgbe_mac_82599_vf:
6469         case ixgbe_mac_X540_vf:
6470                 return 0;
6471         default:
6472                 return 1;
6473         }
6474 }
6475
6476 static int
6477 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6478                         struct rte_eth_dcb_info *dcb_info)
6479 {
6480         struct ixgbe_dcb_config *dcb_config =
6481                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6482         struct ixgbe_dcb_tc_config *tc;
6483         uint8_t i, j;
6484
6485         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6486                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6487         else
6488                 dcb_info->nb_tcs = 1;
6489
6490         if (dcb_config->vt_mode) { /* vt is enabled*/
6491                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6492                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6493                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6494                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6495                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6496                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6497                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6498                                                 i * dcb_info->nb_tcs + j;
6499                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6500                                 dcb_info->tc_queue.tc_txq[i][j].base =
6501                                                 i * dcb_info->nb_tcs + j;
6502                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6503                         }
6504                 }
6505         } else { /* vt is disabled*/
6506                 struct rte_eth_dcb_rx_conf *rx_conf =
6507                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6508                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6509                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6510                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6511                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6512                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6513                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6514                         }
6515                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6516                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6517                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6518                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6519                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6520                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6521                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6522                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6523                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6524                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6525                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6526                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6527                         }
6528                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6529                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6530                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6531                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6532                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6533                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6534                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6535                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6536                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6537                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6538                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6539                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6540                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6541                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6542                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6543                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6544                 }
6545         }
6546         for (i = 0; i < dcb_info->nb_tcs; i++) {
6547                 tc = &dcb_config->tc_config[i];
6548                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6549         }
6550         return 0;
6551 }
6552
6553 /* Update e-tag ether type */
6554 static int
6555 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6556                             uint16_t ether_type)
6557 {
6558         uint32_t etag_etype;
6559
6560         if (hw->mac.type != ixgbe_mac_X550 &&
6561             hw->mac.type != ixgbe_mac_X550EM_x &&
6562             hw->mac.type != ixgbe_mac_X550EM_a) {
6563                 return -ENOTSUP;
6564         }
6565
6566         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6567         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6568         etag_etype |= ether_type;
6569         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6570         IXGBE_WRITE_FLUSH(hw);
6571
6572         return 0;
6573 }
6574
6575 /* Config l2 tunnel ether type */
6576 static int
6577 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6578                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6579 {
6580         int ret = 0;
6581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6582
6583         if (l2_tunnel == NULL)
6584                 return -EINVAL;
6585
6586         switch (l2_tunnel->l2_tunnel_type) {
6587         case RTE_L2_TUNNEL_TYPE_E_TAG:
6588                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6589                 break;
6590         default:
6591                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6592                 ret = -EINVAL;
6593                 break;
6594         }
6595
6596         return ret;
6597 }
6598
6599 /* Enable e-tag tunnel */
6600 static int
6601 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6602 {
6603         uint32_t etag_etype;
6604
6605         if (hw->mac.type != ixgbe_mac_X550 &&
6606             hw->mac.type != ixgbe_mac_X550EM_x &&
6607             hw->mac.type != ixgbe_mac_X550EM_a) {
6608                 return -ENOTSUP;
6609         }
6610
6611         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6612         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6613         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6614         IXGBE_WRITE_FLUSH(hw);
6615
6616         return 0;
6617 }
6618
6619 /* Enable l2 tunnel */
6620 static int
6621 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6622                            enum rte_eth_tunnel_type l2_tunnel_type)
6623 {
6624         int ret = 0;
6625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626
6627         switch (l2_tunnel_type) {
6628         case RTE_L2_TUNNEL_TYPE_E_TAG:
6629                 ret = ixgbe_e_tag_enable(hw);
6630                 break;
6631         default:
6632                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6633                 ret = -EINVAL;
6634                 break;
6635         }
6636
6637         return ret;
6638 }
6639
6640 /* Disable e-tag tunnel */
6641 static int
6642 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6643 {
6644         uint32_t etag_etype;
6645
6646         if (hw->mac.type != ixgbe_mac_X550 &&
6647             hw->mac.type != ixgbe_mac_X550EM_x &&
6648             hw->mac.type != ixgbe_mac_X550EM_a) {
6649                 return -ENOTSUP;
6650         }
6651
6652         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6653         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6654         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6655         IXGBE_WRITE_FLUSH(hw);
6656
6657         return 0;
6658 }
6659
6660 /* Disable l2 tunnel */
6661 static int
6662 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6663                             enum rte_eth_tunnel_type l2_tunnel_type)
6664 {
6665         int ret = 0;
6666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667
6668         switch (l2_tunnel_type) {
6669         case RTE_L2_TUNNEL_TYPE_E_TAG:
6670                 ret = ixgbe_e_tag_disable(hw);
6671                 break;
6672         default:
6673                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6674                 ret = -EINVAL;
6675                 break;
6676         }
6677
6678         return ret;
6679 }
6680
6681 static int
6682 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6683                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6684 {
6685         int ret = 0;
6686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687         uint32_t i, rar_entries;
6688         uint32_t rar_low, rar_high;
6689
6690         if (hw->mac.type != ixgbe_mac_X550 &&
6691             hw->mac.type != ixgbe_mac_X550EM_x &&
6692             hw->mac.type != ixgbe_mac_X550EM_a) {
6693                 return -ENOTSUP;
6694         }
6695
6696         rar_entries = ixgbe_get_num_rx_addrs(hw);
6697
6698         for (i = 1; i < rar_entries; i++) {
6699                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6700                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6701                 if ((rar_high & IXGBE_RAH_AV) &&
6702                     (rar_high & IXGBE_RAH_ADTYPE) &&
6703                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6704                      l2_tunnel->tunnel_id)) {
6705                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6706                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6707
6708                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6709
6710                         return ret;
6711                 }
6712         }
6713
6714         return ret;
6715 }
6716
6717 static int
6718 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6719                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6720 {
6721         int ret = 0;
6722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6723         uint32_t i, rar_entries;
6724         uint32_t rar_low, rar_high;
6725
6726         if (hw->mac.type != ixgbe_mac_X550 &&
6727             hw->mac.type != ixgbe_mac_X550EM_x &&
6728             hw->mac.type != ixgbe_mac_X550EM_a) {
6729                 return -ENOTSUP;
6730         }
6731
6732         /* One entry for one tunnel. Try to remove potential existing entry. */
6733         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6734
6735         rar_entries = ixgbe_get_num_rx_addrs(hw);
6736
6737         for (i = 1; i < rar_entries; i++) {
6738                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6739                 if (rar_high & IXGBE_RAH_AV) {
6740                         continue;
6741                 } else {
6742                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6743                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6744                         rar_low = l2_tunnel->tunnel_id;
6745
6746                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6747                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6748
6749                         return ret;
6750                 }
6751         }
6752
6753         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6754                      " Please remove a rule before adding a new one.");
6755         return -EINVAL;
6756 }
6757
6758 /* Add l2 tunnel filter */
6759 static int
6760 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6761                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6762 {
6763         int ret = 0;
6764
6765         switch (l2_tunnel->l2_tunnel_type) {
6766         case RTE_L2_TUNNEL_TYPE_E_TAG:
6767                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6768                 break;
6769         default:
6770                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6771                 ret = -EINVAL;
6772                 break;
6773         }
6774
6775         return ret;
6776 }
6777
6778 /* Delete l2 tunnel filter */
6779 static int
6780 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6781                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6782 {
6783         int ret = 0;
6784
6785         switch (l2_tunnel->l2_tunnel_type) {
6786         case RTE_L2_TUNNEL_TYPE_E_TAG:
6787                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6788                 break;
6789         default:
6790                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6791                 ret = -EINVAL;
6792                 break;
6793         }
6794
6795         return ret;
6796 }
6797
6798 /**
6799  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6800  * @dev: pointer to rte_eth_dev structure
6801  * @filter_op:operation will be taken.
6802  * @arg: a pointer to specific structure corresponding to the filter_op
6803  */
6804 static int
6805 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6806                                   enum rte_filter_op filter_op,
6807                                   void *arg)
6808 {
6809         int ret = 0;
6810
6811         if (filter_op == RTE_ETH_FILTER_NOP)
6812                 return 0;
6813
6814         if (arg == NULL) {
6815                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6816                             filter_op);
6817                 return -EINVAL;
6818         }
6819
6820         switch (filter_op) {
6821         case RTE_ETH_FILTER_ADD:
6822                 ret = ixgbe_dev_l2_tunnel_filter_add
6823                         (dev,
6824                          (struct rte_eth_l2_tunnel_conf *)arg);
6825                 break;
6826         case RTE_ETH_FILTER_DELETE:
6827                 ret = ixgbe_dev_l2_tunnel_filter_del
6828                         (dev,
6829                          (struct rte_eth_l2_tunnel_conf *)arg);
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6833                 ret = -EINVAL;
6834                 break;
6835         }
6836         return ret;
6837 }
6838
6839 static int
6840 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6841 {
6842         int ret = 0;
6843         uint32_t ctrl;
6844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845
6846         if (hw->mac.type != ixgbe_mac_X550 &&
6847             hw->mac.type != ixgbe_mac_X550EM_x &&
6848             hw->mac.type != ixgbe_mac_X550EM_a) {
6849                 return -ENOTSUP;
6850         }
6851
6852         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6853         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6854         if (en)
6855                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6856         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6857
6858         return ret;
6859 }
6860
6861 /* Enable l2 tunnel forwarding */
6862 static int
6863 ixgbe_dev_l2_tunnel_forwarding_enable
6864         (struct rte_eth_dev *dev,
6865          enum rte_eth_tunnel_type l2_tunnel_type)
6866 {
6867         int ret = 0;
6868
6869         switch (l2_tunnel_type) {
6870         case RTE_L2_TUNNEL_TYPE_E_TAG:
6871                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6872                 break;
6873         default:
6874                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6875                 ret = -EINVAL;
6876                 break;
6877         }
6878
6879         return ret;
6880 }
6881
6882 /* Disable l2 tunnel forwarding */
6883 static int
6884 ixgbe_dev_l2_tunnel_forwarding_disable
6885         (struct rte_eth_dev *dev,
6886          enum rte_eth_tunnel_type l2_tunnel_type)
6887 {
6888         int ret = 0;
6889
6890         switch (l2_tunnel_type) {
6891         case RTE_L2_TUNNEL_TYPE_E_TAG:
6892                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6893                 break;
6894         default:
6895                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6896                 ret = -EINVAL;
6897                 break;
6898         }
6899
6900         return ret;
6901 }
6902
6903 static int
6904 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6905                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6906                              bool en)
6907 {
6908         int ret = 0;
6909         uint32_t vmtir, vmvir;
6910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911
6912         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6913                 PMD_DRV_LOG(ERR,
6914                             "VF id %u should be less than %u",
6915                             l2_tunnel->vf_id,
6916                             dev->pci_dev->max_vfs);
6917                 return -EINVAL;
6918         }
6919
6920         if (hw->mac.type != ixgbe_mac_X550 &&
6921             hw->mac.type != ixgbe_mac_X550EM_x &&
6922             hw->mac.type != ixgbe_mac_X550EM_a) {
6923                 return -ENOTSUP;
6924         }
6925
6926         if (en)
6927                 vmtir = l2_tunnel->tunnel_id;
6928         else
6929                 vmtir = 0;
6930
6931         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6932
6933         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6934         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6935         if (en)
6936                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6937         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6938
6939         return ret;
6940 }
6941
6942 /* Enable l2 tunnel tag insertion */
6943 static int
6944 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6945                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6946 {
6947         int ret = 0;
6948
6949         switch (l2_tunnel->l2_tunnel_type) {
6950         case RTE_L2_TUNNEL_TYPE_E_TAG:
6951                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6952                 break;
6953         default:
6954                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6955                 ret = -EINVAL;
6956                 break;
6957         }
6958
6959         return ret;
6960 }
6961
6962 /* Disable l2 tunnel tag insertion */
6963 static int
6964 ixgbe_dev_l2_tunnel_insertion_disable
6965         (struct rte_eth_dev *dev,
6966          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6967 {
6968         int ret = 0;
6969
6970         switch (l2_tunnel->l2_tunnel_type) {
6971         case RTE_L2_TUNNEL_TYPE_E_TAG:
6972                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6973                 break;
6974         default:
6975                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6976                 ret = -EINVAL;
6977                 break;
6978         }
6979
6980         return ret;
6981 }
6982
6983 static int
6984 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6985                              bool en)
6986 {
6987         int ret = 0;
6988         uint32_t qde;
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990
6991         if (hw->mac.type != ixgbe_mac_X550 &&
6992             hw->mac.type != ixgbe_mac_X550EM_x &&
6993             hw->mac.type != ixgbe_mac_X550EM_a) {
6994                 return -ENOTSUP;
6995         }
6996
6997         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6998         if (en)
6999                 qde |= IXGBE_QDE_STRIP_TAG;
7000         else
7001                 qde &= ~IXGBE_QDE_STRIP_TAG;
7002         qde &= ~IXGBE_QDE_READ;
7003         qde |= IXGBE_QDE_WRITE;
7004         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7005
7006         return ret;
7007 }
7008
7009 /* Enable l2 tunnel tag stripping */
7010 static int
7011 ixgbe_dev_l2_tunnel_stripping_enable
7012         (struct rte_eth_dev *dev,
7013          enum rte_eth_tunnel_type l2_tunnel_type)
7014 {
7015         int ret = 0;
7016
7017         switch (l2_tunnel_type) {
7018         case RTE_L2_TUNNEL_TYPE_E_TAG:
7019                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7020                 break;
7021         default:
7022                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7023                 ret = -EINVAL;
7024                 break;
7025         }
7026
7027         return ret;
7028 }
7029
7030 /* Disable l2 tunnel tag stripping */
7031 static int
7032 ixgbe_dev_l2_tunnel_stripping_disable
7033         (struct rte_eth_dev *dev,
7034          enum rte_eth_tunnel_type l2_tunnel_type)
7035 {
7036         int ret = 0;
7037
7038         switch (l2_tunnel_type) {
7039         case RTE_L2_TUNNEL_TYPE_E_TAG:
7040                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7041                 break;
7042         default:
7043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7044                 ret = -EINVAL;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 /* Enable/disable l2 tunnel offload functions */
7052 static int
7053 ixgbe_dev_l2_tunnel_offload_set
7054         (struct rte_eth_dev *dev,
7055          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7056          uint32_t mask,
7057          uint8_t en)
7058 {
7059         int ret = 0;
7060
7061         if (l2_tunnel == NULL)
7062                 return -EINVAL;
7063
7064         ret = -EINVAL;
7065         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7066                 if (en)
7067                         ret = ixgbe_dev_l2_tunnel_enable(
7068                                 dev,
7069                                 l2_tunnel->l2_tunnel_type);
7070                 else
7071                         ret = ixgbe_dev_l2_tunnel_disable(
7072                                 dev,
7073                                 l2_tunnel->l2_tunnel_type);
7074         }
7075
7076         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7077                 if (en)
7078                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7079                                 dev,
7080                                 l2_tunnel);
7081                 else
7082                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7083                                 dev,
7084                                 l2_tunnel);
7085         }
7086
7087         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7088                 if (en)
7089                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7090                                 dev,
7091                                 l2_tunnel->l2_tunnel_type);
7092                 else
7093                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7094                                 dev,
7095                                 l2_tunnel->l2_tunnel_type);
7096         }
7097
7098         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7099                 if (en)
7100                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7101                                 dev,
7102                                 l2_tunnel->l2_tunnel_type);
7103                 else
7104                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7105                                 dev,
7106                                 l2_tunnel->l2_tunnel_type);
7107         }
7108
7109         return ret;
7110 }
7111
7112 static int
7113 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7114                         uint16_t port)
7115 {
7116         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7117         IXGBE_WRITE_FLUSH(hw);
7118
7119         return 0;
7120 }
7121
7122 /* There's only one register for VxLAN UDP port.
7123  * So, we cannot add several ports. Will update it.
7124  */
7125 static int
7126 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7127                      uint16_t port)
7128 {
7129         if (port == 0) {
7130                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7131                 return -EINVAL;
7132         }
7133
7134         return ixgbe_update_vxlan_port(hw, port);
7135 }
7136
7137 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7138  * UDP port, it must have a value.
7139  * So, will reset it to the original value 0.
7140  */
7141 static int
7142 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7143                      uint16_t port)
7144 {
7145         uint16_t cur_port;
7146
7147         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7148
7149         if (cur_port != port) {
7150                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7151                 return -EINVAL;
7152         }
7153
7154         return ixgbe_update_vxlan_port(hw, 0);
7155 }
7156
7157 /* Add UDP tunneling port */
7158 static int
7159 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7160                               struct rte_eth_udp_tunnel *udp_tunnel)
7161 {
7162         int ret = 0;
7163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164
7165         if (hw->mac.type != ixgbe_mac_X550 &&
7166             hw->mac.type != ixgbe_mac_X550EM_x &&
7167             hw->mac.type != ixgbe_mac_X550EM_a) {
7168                 return -ENOTSUP;
7169         }
7170
7171         if (udp_tunnel == NULL)
7172                 return -EINVAL;
7173
7174         switch (udp_tunnel->prot_type) {
7175         case RTE_TUNNEL_TYPE_VXLAN:
7176                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7177                 break;
7178
7179         case RTE_TUNNEL_TYPE_GENEVE:
7180         case RTE_TUNNEL_TYPE_TEREDO:
7181                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7182                 ret = -EINVAL;
7183                 break;
7184
7185         default:
7186                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7187                 ret = -EINVAL;
7188                 break;
7189         }
7190
7191         return ret;
7192 }
7193
7194 /* Remove UDP tunneling port */
7195 static int
7196 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7197                               struct rte_eth_udp_tunnel *udp_tunnel)
7198 {
7199         int ret = 0;
7200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201
7202         if (hw->mac.type != ixgbe_mac_X550 &&
7203             hw->mac.type != ixgbe_mac_X550EM_x &&
7204             hw->mac.type != ixgbe_mac_X550EM_a) {
7205                 return -ENOTSUP;
7206         }
7207
7208         if (udp_tunnel == NULL)
7209                 return -EINVAL;
7210
7211         switch (udp_tunnel->prot_type) {
7212         case RTE_TUNNEL_TYPE_VXLAN:
7213                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7214                 break;
7215         case RTE_TUNNEL_TYPE_GENEVE:
7216         case RTE_TUNNEL_TYPE_TEREDO:
7217                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7218                 ret = -EINVAL;
7219                 break;
7220         default:
7221                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7222                 ret = -EINVAL;
7223                 break;
7224         }
7225
7226         return ret;
7227 }
7228
7229 /* ixgbevf_update_xcast_mode - Update Multicast mode
7230  * @hw: pointer to the HW structure
7231  * @netdev: pointer to net device structure
7232  * @xcast_mode: new multicast mode
7233  *
7234  * Updates the Multicast Mode of VF.
7235  */
7236 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7237                                      int xcast_mode)
7238 {
7239         struct ixgbe_mbx_info *mbx = &hw->mbx;
7240         u32 msgbuf[2];
7241         s32 err;
7242
7243         switch (hw->api_version) {
7244         case ixgbe_mbox_api_12:
7245                 break;
7246         default:
7247                 return -EOPNOTSUPP;
7248         }
7249
7250         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7251         msgbuf[1] = xcast_mode;
7252
7253         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7254         if (err)
7255                 return err;
7256
7257         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7258         if (err)
7259                 return err;
7260
7261         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7262         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7263                 return -EPERM;
7264
7265         return 0;
7266 }
7267
7268 static void
7269 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7270 {
7271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7272
7273         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7274 }
7275
7276 static void
7277 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7278 {
7279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7280
7281         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7282 }
7283
7284 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7285 {
7286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287         u32 in_msg = 0;
7288
7289         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7290                 return;
7291
7292         /* PF reset VF event */
7293         if (in_msg == IXGBE_PF_CONTROL_MSG)
7294                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7295 }
7296
7297 static int
7298 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7299 {
7300         uint32_t eicr;
7301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7302         struct ixgbe_interrupt *intr =
7303                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7304         ixgbevf_intr_disable(hw);
7305
7306         /* read-on-clear nic registers here */
7307         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7308         intr->flags = 0;
7309
7310         /* only one misc vector supported - mailbox */
7311         eicr &= IXGBE_VTEICR_MASK;
7312         if (eicr == IXGBE_MISC_VEC_ID)
7313                 intr->flags |= IXGBE_FLAG_MAILBOX;
7314
7315         return 0;
7316 }
7317
7318 static int
7319 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7320 {
7321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7322         struct ixgbe_interrupt *intr =
7323                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7324
7325         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7326                 ixgbevf_mbx_process(dev);
7327                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7328         }
7329
7330         ixgbevf_intr_enable(hw);
7331
7332         return 0;
7333 }
7334
7335 static void
7336 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7337                               void *param)
7338 {
7339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7340
7341         ixgbevf_dev_interrupt_get_status(dev);
7342         ixgbevf_dev_interrupt_action(dev);
7343 }
7344
7345 static struct rte_driver rte_ixgbe_driver = {
7346         .type = PMD_PDEV,
7347         .init = rte_ixgbe_pmd_init,
7348 };
7349
7350 static struct rte_driver rte_ixgbevf_driver = {
7351         .type = PMD_PDEV,
7352         .init = rte_ixgbevf_pmd_init,
7353 };
7354
7355 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7356 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);