drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 /*Default value of Max Rx Queue*/
  97 #define IXGBE_MAX_RX_QUEUE_NUM 128
  98
  99 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
 100 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
 101 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 102
 103 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 104 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 105 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 106
 107 /*
 108  *  Default values for RX/TX configuration
 109  */
 110 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_RX_PTHRESH      8
 112 #define IXGBE_DEFAULT_RX_HTHRESH      8
 113 #define IXGBE_DEFAULT_RX_WTHRESH      0
 114
 115 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 116 #define IXGBE_DEFAULT_TX_PTHRESH      32
 117 #define IXGBE_DEFAULT_TX_HTHRESH      0
 118 #define IXGBE_DEFAULT_TX_WTHRESH      0
 119 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 120
 121 /* Bit shift and mask */
 122 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 123 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 124 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 125 #define IXGBE_8_BIT_MASK   UINT8_MAX
 126
 127 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 128
 129 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 130
 131 #define IXGBE_HKEY_MAX_INDEX 10
 132
 133 /* Additional timesync values. */
 134 #define NSEC_PER_SEC             1000000000L
 135 #define IXGBE_INCVAL_10GB        0x66666666
 136 #define IXGBE_INCVAL_1GB         0x40000000
 137 #define IXGBE_INCVAL_100         0x50000000
 138 #define IXGBE_INCVAL_SHIFT_10GB  28
 139 #define IXGBE_INCVAL_SHIFT_1GB   24
 140 #define IXGBE_INCVAL_SHIFT_100   21
 141 #define IXGBE_INCVAL_SHIFT_82599 7
 142 #define IXGBE_INCPER_SHIFT_82599 24
 143
 144 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 145
 146 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 147 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 148 #define DEFAULT_ETAG_ETYPE                     0x893f
 149 #define IXGBE_ETAG_ETYPE                       0x00005084
 150 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 151 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 152 #define IXGBE_RAH_ADTYPE                       0x40000000
 153 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 154 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 155 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 156 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 157 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 158 #define IXGBE_VTEICR_MASK                      0x07
 159
 160 enum ixgbevf_xcast_modes {
 161         IXGBEVF_XCAST_MODE_NONE = 0,
 162         IXGBEVF_XCAST_MODE_MULTI,
 163         IXGBEVF_XCAST_MODE_ALLMULTI,
 164 };
 165
 166 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 167 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 168
 169 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 170 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 171 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 174 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 182                                 int wait_to_complete);
 183 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *stats);
 185 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 188                                   struct rte_eth_xstat *xstats, unsigned n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 196                                              uint16_t queue_id,
 197                                              uint8_t stat_idx,
 198                                              uint8_t is_rx);
 199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 200                                struct rte_eth_dev_info *dev_info);
 201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 203                                  struct rte_eth_dev_info *dev_info);
 204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205
 206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 207                 uint16_t vlan_id, int on);
 208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 209                                enum rte_vlan_type vlan_type,
 210                                uint16_t tpid_id);
 211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 212                 uint16_t queue, bool on);
 213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 214                 int on);
 215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 220
 221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 224                                struct rte_eth_fc_conf *fc_conf);
 225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 226                                struct rte_eth_fc_conf *fc_conf);
 227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 228                 struct rte_eth_pfc_conf *pfc_conf);
 229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 233                         struct rte_eth_rss_reta_entry64 *reta_conf,
 234                         uint16_t reta_size);
 235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 240 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 241                 void *param);
 242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 244                 uint32_t index, uint32_t pool);
 245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 247                                            struct ether_addr *mac_addr);
 248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 249
 250 /* For Virtual Function support */
 251 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 252 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 253 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 254 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 255 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 256                                    int wait_to_complete);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 285                 uint16_t rx_mask, uint8_t on);
 286 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 287 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 288 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 289                 uint64_t pool_mask, uint8_t vlan_on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 306                 uint16_t tx_rate, uint64_t q_msk);
 307
 308 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                  struct ether_addr *mac_addr,
 310                                  uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter,
 316                         bool add);
 317 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 318                         struct rte_eth_syn_filter *filter);
 319 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 320                         enum rte_filter_op filter_op,
 321                         void *arg);
 322 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 325                         struct ixgbe_5tuple_filter *filter);
 326 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter,
 328                         bool add);
 329 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ntuple_filter *filter);
 334 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 335                         struct rte_eth_ethertype_filter *filter,
 336                         bool add);
 337 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 338                                 enum rte_filter_op filter_op,
 339                                 void *arg);
 340 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 341                         struct rte_eth_ethertype_filter *filter);
 342 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 343                      enum rte_filter_type filter_type,
 344                      enum rte_filter_op filter_op,
 345                      void *arg);
 346 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 347
 348 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 349                                       struct ether_addr *mc_addr_set,
 350                                       uint32_t nb_mc_addr);
 351 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 352                                    struct rte_eth_dcb_info *dcb_info);
 353
 354 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 356                             struct rte_dev_reg_info *regs);
 357 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 358 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 361                                 struct rte_dev_eeprom_info *eeprom);
 362
 363 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 364 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 365                                 struct rte_dev_reg_info *regs);
 366
 367 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 368 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 369 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 370                                             struct timespec *timestamp,
 371                                             uint32_t flags);
 372 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 373                                             struct timespec *timestamp);
 374 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 375 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 376                                    struct timespec *timestamp);
 377 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 378                                    const struct timespec *timestamp);
 379 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                           void *param);
 381
 382 static int ixgbe_dev_l2_tunnel_eth_type_conf
 383         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 384 static int ixgbe_dev_l2_tunnel_offload_set
 385         (struct rte_eth_dev *dev,
 386          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 387          uint32_t mask,
 388          uint8_t en);
 389 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 390                                              enum rte_filter_op filter_op,
 391                                              void *arg);
 392
 393 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 396                                          struct rte_eth_udp_tunnel *udp_tunnel);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 492 #ifdef RTE_NIC_BYPASS
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 494 #endif
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 /*
 499  * The set of PCI devices this driver supports (for 82599 VF)
 500  */
 501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 511         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 512         { .vendor_id = 0, /* sentinel */ },
 513 };
 514
 515 static const struct rte_eth_desc_lim rx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_RXD_ALIGN,
 519 };
 520
 521 static const struct rte_eth_desc_lim tx_desc_lim = {
 522         .nb_max = IXGBE_MAX_RING_DESC,
 523         .nb_min = IXGBE_MIN_RING_DESC,
 524         .nb_align = IXGBE_TXD_ALIGN,
 525 };
 526
 527 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 528         .dev_configure        = ixgbe_dev_configure,
 529         .dev_start            = ixgbe_dev_start,
 530         .dev_stop             = ixgbe_dev_stop,
 531         .dev_set_link_up    = ixgbe_dev_set_link_up,
 532         .dev_set_link_down  = ixgbe_dev_set_link_down,
 533         .dev_close            = ixgbe_dev_close,
 534         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 535         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 536         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 537         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 538         .link_update          = ixgbe_dev_link_update,
 539         .stats_get            = ixgbe_dev_stats_get,
 540         .xstats_get           = ixgbe_dev_xstats_get,
 541         .stats_reset          = ixgbe_dev_stats_reset,
 542         .xstats_reset         = ixgbe_dev_xstats_reset,
 543         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .dev_infos_get        = ixgbe_dev_info_get,
 546         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 547         .mtu_set              = ixgbe_dev_mtu_set,
 548         .vlan_filter_set      = ixgbe_vlan_filter_set,
 549         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 550         .vlan_offload_set     = ixgbe_vlan_offload_set,
 551         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 552         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 553         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 554         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 555         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 556         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 557         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 558         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 559         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 560         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 561         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 577         .set_vf_rx            = ixgbe_set_pool_rx,
 578         .set_vf_tx            = ixgbe_set_pool_tx,
 579         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 580         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 581         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584 #ifdef RTE_NIC_BYPASS
 585         .bypass_init          = ixgbe_bypass_init,
 586         .bypass_state_set     = ixgbe_bypass_state_store,
 587         .bypass_state_show    = ixgbe_bypass_state_show,
 588         .bypass_event_set     = ixgbe_bypass_event_store,
 589         .bypass_event_show    = ixgbe_bypass_event_show,
 590         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 591         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 592         .bypass_ver_show      = ixgbe_bypass_ver_show,
 593         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 594 #endif /* RTE_NIC_BYPASS */
 595         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 596         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 597         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .timesync_enable      = ixgbe_timesync_enable,
 602         .timesync_disable     = ixgbe_timesync_disable,
 603         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 604         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 605         .get_reg              = ixgbe_get_regs,
 606         .get_eeprom_length    = ixgbe_get_eeprom_length,
 607         .get_eeprom           = ixgbe_get_eeprom,
 608         .set_eeprom           = ixgbe_set_eeprom,
 609         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 610         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 611         .timesync_read_time   = ixgbe_timesync_read_time,
 612         .timesync_write_time  = ixgbe_timesync_write_time,
 613         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 614         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 615         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 616         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 617 };
 618
 619 /*
 620  * dev_ops for virtual function, bare necessities for basic vf
 621  * operation have been implemented
 622  */
 623 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 624         .dev_configure        = ixgbevf_dev_configure,
 625         .dev_start            = ixgbevf_dev_start,
 626         .dev_stop             = ixgbevf_dev_stop,
 627         .link_update          = ixgbevf_dev_link_update,
 628         .stats_get            = ixgbevf_dev_stats_get,
 629         .xstats_get           = ixgbevf_dev_xstats_get,
 630         .stats_reset          = ixgbevf_dev_stats_reset,
 631         .xstats_reset         = ixgbevf_dev_stats_reset,
 632         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 633         .dev_close            = ixgbevf_dev_close,
 634         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 635         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 636         .dev_infos_get        = ixgbevf_dev_info_get,
 637         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 638         .mtu_set              = ixgbevf_dev_set_mtu,
 639         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 640         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 641         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 642         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 643         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 644         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 645         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 646         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 647         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 648         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 649         .mac_addr_add         = ixgbevf_add_mac_addr,
 650         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 651         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 652         .rxq_info_get         = ixgbe_rxq_info_get,
 653         .txq_info_get         = ixgbe_txq_info_get,
 654         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 655         .get_reg              = ixgbevf_get_regs,
 656         .reta_update          = ixgbe_dev_rss_reta_update,
 657         .reta_query           = ixgbe_dev_rss_reta_query,
 658         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 659         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 660 };
 661
 662 /* store statistics names and its offset in stats structure */
 663 struct rte_ixgbe_xstats_name_off {
 664         char name[RTE_ETH_XSTATS_NAME_SIZE];
 665         unsigned offset;
 666 };
 667
 668 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 669         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 670         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 671         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 672         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 673         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 674         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 675         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 676         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 677         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 678         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 679         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 680         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 681         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 682         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 683         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1023)},
 685         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 686                 prc1522)},
 687         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 688         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 689         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 690         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 691         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 692         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 693         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 694         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 695         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 696         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 697         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 698         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 699         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 700         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 701         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 702         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 703         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1023)},
 705         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 706                 ptc1522)},
 707         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 708         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 709         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 710         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 711
 712         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_add)},
 714         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirustat_remove)},
 716         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fadd)},
 718         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 719                 fdirfstat_fremove)},
 720         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmatch)},
 722         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 723                 fdirmiss)},
 724
 725         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 726         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 727         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 728                 fclast)},
 729         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 730         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 731         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 732         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 733         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 734                 fcoe_noddp)},
 735         {"rx_fcoe_no_direct_data_placement_ext_buff",
 736                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 737
 738         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxontxc)},
 740         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxonrxc)},
 742         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxofftxc)},
 744         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 745                 lxoffrxc)},
 746         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 747 };
 748
 749 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 750                            sizeof(rte_ixgbe_stats_strings[0]))
 751
 752 /* Per-queue statistics */
 753 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 754         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 755         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 756         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 757         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 758 };
 759
 760 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 761                            sizeof(rte_ixgbe_rxq_strings[0]))
 762 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 763
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 765         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 766         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 767         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 768                 pxon2offc)},
 769 };
 770
 771 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 772                            sizeof(rte_ixgbe_txq_strings[0]))
 773 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 776         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 777 };
 778
 779 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 780                 sizeof(rte_ixgbevf_stats_strings[0]))
 781
 782 /**
 783  * Atomically reads the link status information from global
 784  * structure rte_eth_dev.
 785  *
 786  * @param dev
 787  *   - Pointer to the structure rte_eth_dev to read from.
 788  *   - Pointer to the buffer to be saved with the link status.
 789  *
 790  * @return
 791  *   - On success, zero.
 792  *   - On failure, negative value.
 793  */
 794 static inline int
 795 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 796                                 struct rte_eth_link *link)
 797 {
 798         struct rte_eth_link *dst = link;
 799         struct rte_eth_link *src = &(dev->data->dev_link);
 800
 801         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 802                                         *(uint64_t *)src) == 0)
 803                 return -1;
 804
 805         return 0;
 806 }
 807
 808 /**
 809  * Atomically writes the link status information into global
 810  * structure rte_eth_dev.
 811  *
 812  * @param dev
 813  *   - Pointer to the structure rte_eth_dev to read from.
 814  *   - Pointer to the buffer to be saved with the link status.
 815  *
 816  * @return
 817  *   - On success, zero.
 818  *   - On failure, negative value.
 819  */
 820 static inline int
 821 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 822                                 struct rte_eth_link *link)
 823 {
 824         struct rte_eth_link *dst = &(dev->data->dev_link);
 825         struct rte_eth_link *src = link;
 826
 827         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 828                                         *(uint64_t *)src) == 0)
 829                 return -1;
 830
 831         return 0;
 832 }
 833
 834 /*
 835  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 836  */
 837 static inline int
 838 ixgbe_is_sfp(struct ixgbe_hw *hw)
 839 {
 840         switch (hw->phy.type) {
 841         case ixgbe_phy_sfp_avago:
 842         case ixgbe_phy_sfp_ftl:
 843         case ixgbe_phy_sfp_intel:
 844         case ixgbe_phy_sfp_unknown:
 845         case ixgbe_phy_sfp_passive_tyco:
 846         case ixgbe_phy_sfp_passive_unknown:
 847                 return 1;
 848         default:
 849                 return 0;
 850         }
 851 }
 852
 853 static inline int32_t
 854 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 855 {
 856         uint32_t ctrl_ext;
 857         int32_t status;
 858
 859         status = ixgbe_reset_hw(hw);
 860
 861         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 862         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 863         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 864         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 865         IXGBE_WRITE_FLUSH(hw);
 866
 867         return status;
 868 }
 869
 870 static inline void
 871 ixgbe_enable_intr(struct rte_eth_dev *dev)
 872 {
 873         struct ixgbe_interrupt *intr =
 874                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 875         struct ixgbe_hw *hw =
 876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 879         IXGBE_WRITE_FLUSH(hw);
 880 }
 881
 882 /*
 883  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 884  */
 885 static void
 886 ixgbe_disable_intr(struct ixgbe_hw *hw)
 887 {
 888         PMD_INIT_FUNC_TRACE();
 889
 890         if (hw->mac.type == ixgbe_mac_82598EB) {
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 892         } else {
 893                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 894                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 895                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 896         }
 897         IXGBE_WRITE_FLUSH(hw);
 898 }
 899
 900 /*
 901  * This function resets queue statistics mapping registers.
 902  * From Niantic datasheet, Initialization of Statistics section:
 903  * "...if software requires the queue counters, the RQSMR and TQSM registers
 904  * must be re-programmed following a device reset.
 905  */
 906 static void
 907 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 908 {
 909         uint32_t i;
 910
 911         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 912                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 914         }
 915 }
 916
 917
 918 static int
 919 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 920                                   uint16_t queue_id,
 921                                   uint8_t stat_idx,
 922                                   uint8_t is_rx)
 923 {
 924 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 925 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 926 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 927
 928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         struct ixgbe_stat_mapping_registers *stat_mappings =
 930                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 931         uint32_t qsmr_mask = 0;
 932         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 933         uint32_t q_map;
 934         uint8_t n, offset;
 935
 936         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 937                 (hw->mac.type != ixgbe_mac_X540) &&
 938                 (hw->mac.type != ixgbe_mac_X550) &&
 939                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 940                 (hw->mac.type != ixgbe_mac_X550EM_a))
 941                 return -ENOSYS;
 942
 943         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 944                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 945                      queue_id, stat_idx);
 946
 947         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 948         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 949                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 950                 return -EIO;
 951         }
 952         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 953
 954         /* Now clear any previous stat_idx set */
 955         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 956         if (!is_rx)
 957                 stat_mappings->tqsm[n] &= ~clearing_mask;
 958         else
 959                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 960
 961         q_map = (uint32_t)stat_idx;
 962         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 963         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 964         if (!is_rx)
 965                 stat_mappings->tqsm[n] |= qsmr_mask;
 966         else
 967                 stat_mappings->rqsmr[n] |= qsmr_mask;
 968
 969         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 970                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 971                      queue_id, stat_idx);
 972         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 973                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 974
 975         /* Now write the mapping in the appropriate register */
 976         if (is_rx) {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 978                              stat_mappings->rqsmr[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 980         } else {
 981                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 982                              stat_mappings->tqsm[n], n);
 983                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 984         }
 985         return 0;
 986 }
 987
 988 static void
 989 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 990 {
 991         struct ixgbe_stat_mapping_registers *stat_mappings =
 992                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 994         int i;
 995
 996         /* write whatever was in stat mapping table to the NIC */
 997         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 998                 /* rx */
 999                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1000
1001                 /* tx */
1002                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1003         }
1004 }
1005
1006 static void
1007 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1008 {
1009         uint8_t i;
1010         struct ixgbe_dcb_tc_config *tc;
1011         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1012
1013         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1014         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1015         for (i = 0; i < dcb_max_tc; i++) {
1016                 tc = &dcb_config->tc_config[i];
1017                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1018                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1019                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1020                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1021                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1022                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1023                 tc->pfc = ixgbe_dcb_pfc_disabled;
1024         }
1025
1026         /* Initialize default user to priority mapping, UPx->TC0 */
1027         tc = &dcb_config->tc_config[0];
1028         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1029         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1030         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1031                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1032                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1033         }
1034         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1035         dcb_config->pfc_mode_enable = false;
1036         dcb_config->vt_mode = true;
1037         dcb_config->round_robin_enable = false;
1038         /* support all DCB capabilities in 82599 */
1039         dcb_config->support.capabilities = 0xFF;
1040
1041         /*we only support 4 Tcs for X540, X550 */
1042         if (hw->mac.type == ixgbe_mac_X540 ||
1043                 hw->mac.type == ixgbe_mac_X550 ||
1044                 hw->mac.type == ixgbe_mac_X550EM_x ||
1045                 hw->mac.type == ixgbe_mac_X550EM_a) {
1046                 dcb_config->num_tcs.pg_tcs = 4;
1047                 dcb_config->num_tcs.pfc_tcs = 4;
1048         }
1049 }
1050
1051 /*
1052  * Ensure that all locks are released before first NVM or PHY access
1053  */
1054 static void
1055 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1056 {
1057         uint16_t mask;
1058
1059         /*
1060          * Phy lock should not fail in this early stage. If this is the case,
1061          * it is due to an improper exit of the application.
1062          * So force the release of the faulty lock. Release of common lock
1063          * is done automatically by swfw_sync function.
1064          */
1065         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1066         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1068         }
1069         ixgbe_release_swfw_semaphore(hw, mask);
1070
1071         /*
1072          * These ones are more tricky since they are common to all ports; but
1073          * swfw_sync retries last long enough (1s) to be almost sure that if
1074          * lock can not be taken it is due to an improper lock of the
1075          * semaphore.
1076          */
1077         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1078         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1079                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1080         }
1081         ixgbe_release_swfw_semaphore(hw, mask);
1082 }
1083
1084 /*
1085  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1086  * It returns 0 on success.
1087  */
1088 static int
1089 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1090 {
1091         struct rte_pci_device *pci_dev;
1092         struct ixgbe_hw *hw =
1093                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1094         struct ixgbe_vfta *shadow_vfta =
1095                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1096         struct ixgbe_hwstrip *hwstrip =
1097                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1098         struct ixgbe_dcb_config *dcb_config =
1099                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1100         struct ixgbe_filter_info *filter_info =
1101                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1102         uint32_t ctrl_ext;
1103         uint16_t csum;
1104         int diag, i;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1109         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1110         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1111
1112         /*
1113          * For secondary processes, we don't initialise any further as primary
1114          * has already done this work. Only check we don't need a different
1115          * RX and TX function.
1116          */
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118                 struct ixgbe_tx_queue *txq;
1119                 /* TX queue function in primary, set by last queue initialized
1120                  * Tx queue may not initialized by primary process
1121                  */
1122                 if (eth_dev->data->tx_queues) {
1123                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124                         ixgbe_set_tx_function(eth_dev, txq);
1125                 } else {
1126                         /* Use default TX function if we get here */
1127                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128                                      "Using default TX function.");
1129                 }
1130
1131                 ixgbe_set_rx_function(eth_dev);
1132
1133                 return 0;
1134         }
1135         pci_dev = eth_dev->pci_dev;
1136
1137         rte_eth_copy_pci_info(eth_dev, pci_dev);
1138
1139         /* Vendor and Device ID need to be set before init of shared code */
1140         hw->device_id = pci_dev->id.device_id;
1141         hw->vendor_id = pci_dev->id.vendor_id;
1142         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1143         hw->allow_unsupported_sfp = 1;
1144
1145         /* Initialize the shared code (base driver) */
1146 #ifdef RTE_NIC_BYPASS
1147         diag = ixgbe_bypass_init_shared_code(hw);
1148 #else
1149         diag = ixgbe_init_shared_code(hw);
1150 #endif /* RTE_NIC_BYPASS */
1151
1152         if (diag != IXGBE_SUCCESS) {
1153                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1154                 return -EIO;
1155         }
1156
1157         /* pick up the PCI bus settings for reporting later */
1158         ixgbe_get_bus_info(hw);
1159
1160         /* Unlock any pending hardware semaphore */
1161         ixgbe_swfw_lock_reset(hw);
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_full;
1168         hw->fc.current_mode = ixgbe_fc_full;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1243                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(&pci_dev->intr_handle,
1281                                    ixgbe_dev_interrupt_handler,
1282                                    (void *)eth_dev);
1283
1284         /* enable uio/vfio intr/eventfd mapping */
1285         rte_intr_enable(&pci_dev->intr_handle);
1286
1287         /* enable support intr */
1288         ixgbe_enable_intr(eth_dev);
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292         memset(filter_info->fivetuple_mask, 0,
1293                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1294
1295         return 0;
1296 }
1297
1298 static int
1299 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1300 {
1301         struct rte_pci_device *pci_dev;
1302         struct ixgbe_hw *hw;
1303         int retries = 0;
1304         int ret;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1309                 return -EPERM;
1310
1311         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1312         pci_dev = eth_dev->pci_dev;
1313
1314         if (hw->adapter_stopped == 0)
1315                 ixgbe_dev_close(eth_dev);
1316
1317         eth_dev->dev_ops = NULL;
1318         eth_dev->rx_pkt_burst = NULL;
1319         eth_dev->tx_pkt_burst = NULL;
1320
1321         /* Unlock any pending hardware semaphore */
1322         ixgbe_swfw_lock_reset(hw);
1323
1324         /* disable uio intr before callback unregister */
1325         rte_intr_disable(&(pci_dev->intr_handle));
1326
1327         do {
1328                 ret = rte_intr_callback_unregister(&(pci_dev->intr_handle),
1329                                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1330                 if (ret >= 0) {
1331                         break;
1332                 } else if (ret != -EAGAIN) {
1333                         PMD_INIT_LOG(ERR,
1334                                 "intr callback unregister failed: %d",
1335                                 ret);
1336                         return ret;
1337                 }
1338                 rte_delay_ms(100);
1339         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1340
1341         /* uninitialize PF if max_vfs not zero */
1342         ixgbe_pf_host_uninit(eth_dev);
1343
1344         rte_free(eth_dev->data->mac_addrs);
1345         eth_dev->data->mac_addrs = NULL;
1346
1347         rte_free(eth_dev->data->hash_mac_addrs);
1348         eth_dev->data->hash_mac_addrs = NULL;
1349
1350         return 0;
1351 }
1352
1353 /*
1354  * Negotiate mailbox API version with the PF.
1355  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1356  * Then we try to negotiate starting with the most recent one.
1357  * If all negotiation attempts fail, then we will proceed with
1358  * the default one (ixgbe_mbox_api_10).
1359  */
1360 static void
1361 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1362 {
1363         int32_t i;
1364
1365         /* start with highest supported, proceed down */
1366         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1367                 ixgbe_mbox_api_12,
1368                 ixgbe_mbox_api_11,
1369                 ixgbe_mbox_api_10,
1370         };
1371
1372         for (i = 0;
1373                         i != RTE_DIM(sup_ver) &&
1374                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1375                         i++)
1376                 ;
1377 }
1378
1379 static void
1380 generate_random_mac_addr(struct ether_addr *mac_addr)
1381 {
1382         uint64_t random;
1383
1384         /* Set Organizationally Unique Identifier (OUI) prefix. */
1385         mac_addr->addr_bytes[0] = 0x00;
1386         mac_addr->addr_bytes[1] = 0x09;
1387         mac_addr->addr_bytes[2] = 0xC0;
1388         /* Force indication of locally assigned MAC address. */
1389         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1390         /* Generate the last 3 bytes of the MAC address with a random number. */
1391         random = rte_rand();
1392         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1393 }
1394
1395 /*
1396  * Virtual Function device init
1397  */
1398 static int
1399 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1400 {
1401         int diag;
1402         uint32_t tc, tcs;
1403         struct rte_pci_device *pci_dev;
1404         struct ixgbe_hw *hw =
1405                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1406         struct ixgbe_vfta *shadow_vfta =
1407                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1408         struct ixgbe_hwstrip *hwstrip =
1409                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1410         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1415         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1416         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1417
1418         /* for secondary processes, we don't initialise any further as primary
1419          * has already done this work. Only check we don't need a different
1420          * RX function
1421          */
1422         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1423                 struct ixgbe_tx_queue *txq;
1424                 /* TX queue function in primary, set by last queue initialized
1425                  * Tx queue may not initialized by primary process
1426                  */
1427                 if (eth_dev->data->tx_queues) {
1428                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1429                         ixgbe_set_tx_function(eth_dev, txq);
1430                 } else {
1431                         /* Use default TX function if we get here */
1432                         PMD_INIT_LOG(NOTICE,
1433                                      "No TX queues configured yet. Using default TX function.");
1434                 }
1435
1436                 ixgbe_set_rx_function(eth_dev);
1437
1438                 return 0;
1439         }
1440
1441         pci_dev = eth_dev->pci_dev;
1442
1443         rte_eth_copy_pci_info(eth_dev, pci_dev);
1444
1445         hw->device_id = pci_dev->id.device_id;
1446         hw->vendor_id = pci_dev->id.vendor_id;
1447         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1448
1449         /* initialize the vfta */
1450         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1451
1452         /* initialize the hw strip bitmap*/
1453         memset(hwstrip, 0, sizeof(*hwstrip));
1454
1455         /* Initialize the shared code (base driver) */
1456         diag = ixgbe_init_shared_code(hw);
1457         if (diag != IXGBE_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1459                 return -EIO;
1460         }
1461
1462         /* init_mailbox_params */
1463         hw->mbx.ops.init_params(hw);
1464
1465         /* Reset the hw statistics */
1466         ixgbevf_dev_stats_reset(eth_dev);
1467
1468         /* Disable the interrupts for VF */
1469         ixgbevf_intr_disable(hw);
1470
1471         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1472         diag = hw->mac.ops.reset_hw(hw);
1473
1474         /*
1475          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1476          * the underlying PF driver has not assigned a MAC address to the VF.
1477          * In this case, assign a random MAC address.
1478          */
1479         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1480                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1481                 return diag;
1482         }
1483
1484         /* negotiate mailbox API version to use with the PF. */
1485         ixgbevf_negotiate_api(hw);
1486
1487         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1488         ixgbevf_get_queues(hw, &tcs, &tc);
1489
1490         /* Allocate memory for storing MAC addresses */
1491         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1492                                                hw->mac.num_rar_entries, 0);
1493         if (eth_dev->data->mac_addrs == NULL) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate %u bytes needed to store "
1496                              "MAC addresses",
1497                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1498                 return -ENOMEM;
1499         }
1500
1501         /* Generate a random MAC address, if none was assigned by PF. */
1502         if (is_zero_ether_addr(perm_addr)) {
1503                 generate_random_mac_addr(perm_addr);
1504                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1505                 if (diag) {
1506                         rte_free(eth_dev->data->mac_addrs);
1507                         eth_dev->data->mac_addrs = NULL;
1508                         return diag;
1509                 }
1510                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1511                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1512                              "%02x:%02x:%02x:%02x:%02x:%02x",
1513                              perm_addr->addr_bytes[0],
1514                              perm_addr->addr_bytes[1],
1515                              perm_addr->addr_bytes[2],
1516                              perm_addr->addr_bytes[3],
1517                              perm_addr->addr_bytes[4],
1518                              perm_addr->addr_bytes[5]);
1519         }
1520
1521         /* Copy the permanent MAC address */
1522         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1523
1524         /* reset the hardware with the new settings */
1525         diag = hw->mac.ops.start_hw(hw);
1526         switch (diag) {
1527         case  0:
1528                 break;
1529
1530         default:
1531                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1532                 return -EIO;
1533         }
1534
1535         rte_intr_callback_register(&pci_dev->intr_handle,
1536                                    ixgbevf_dev_interrupt_handler,
1537                                    (void *)eth_dev);
1538         rte_intr_enable(&pci_dev->intr_handle);
1539         ixgbevf_intr_enable(hw);
1540
1541         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1542                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1543                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1544
1545         return 0;
1546 }
1547
1548 /* Virtual Function device uninit */
1549
1550 static int
1551 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1552 {
1553         struct ixgbe_hw *hw;
1554         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1555
1556         PMD_INIT_FUNC_TRACE();
1557
1558         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1559                 return -EPERM;
1560
1561         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1562
1563         if (hw->adapter_stopped == 0)
1564                 ixgbevf_dev_close(eth_dev);
1565
1566         eth_dev->dev_ops = NULL;
1567         eth_dev->rx_pkt_burst = NULL;
1568         eth_dev->tx_pkt_burst = NULL;
1569
1570         /* Disable the interrupts for VF */
1571         ixgbevf_intr_disable(hw);
1572
1573         rte_free(eth_dev->data->mac_addrs);
1574         eth_dev->data->mac_addrs = NULL;
1575
1576         rte_intr_disable(&pci_dev->intr_handle);
1577         rte_intr_callback_unregister(&pci_dev->intr_handle,
1578                                      ixgbevf_dev_interrupt_handler,
1579                                      (void *)eth_dev);
1580
1581         return 0;
1582 }
1583
1584 static struct eth_driver rte_ixgbe_pmd = {
1585         .pci_drv = {
1586                 .id_table = pci_id_ixgbe_map,
1587                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1588                         RTE_PCI_DRV_DETACHABLE,
1589                 .probe = rte_eth_dev_pci_probe,
1590                 .remove = rte_eth_dev_pci_remove,
1591         },
1592         .eth_dev_init = eth_ixgbe_dev_init,
1593         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1594         .dev_private_size = sizeof(struct ixgbe_adapter),
1595 };
1596
1597 /*
1598  * virtual function driver struct
1599  */
1600 static struct eth_driver rte_ixgbevf_pmd = {
1601         .pci_drv = {
1602                 .id_table = pci_id_ixgbevf_map,
1603                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1604                 .probe = rte_eth_dev_pci_probe,
1605                 .remove = rte_eth_dev_pci_remove,
1606         },
1607         .eth_dev_init = eth_ixgbevf_dev_init,
1608         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1609         .dev_private_size = sizeof(struct ixgbe_adapter),
1610 };
1611
1612 static int
1613 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1614 {
1615         struct ixgbe_hw *hw =
1616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         struct ixgbe_vfta *shadow_vfta =
1618                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619         uint32_t vfta;
1620         uint32_t vid_idx;
1621         uint32_t vid_bit;
1622
1623         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1624         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1625         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1626         if (on)
1627                 vfta |= vid_bit;
1628         else
1629                 vfta &= ~vid_bit;
1630         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1631
1632         /* update local VFTA copy */
1633         shadow_vfta->vfta[vid_idx] = vfta;
1634
1635         return 0;
1636 }
1637
1638 static void
1639 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1640 {
1641         if (on)
1642                 ixgbe_vlan_hw_strip_enable(dev, queue);
1643         else
1644                 ixgbe_vlan_hw_strip_disable(dev, queue);
1645 }
1646
1647 static int
1648 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1649                     enum rte_vlan_type vlan_type,
1650                     uint16_t tpid)
1651 {
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         int ret = 0;
1655         uint32_t reg;
1656         uint32_t qinq;
1657
1658         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1659         qinq &= IXGBE_DMATXCTL_GDV;
1660
1661         switch (vlan_type) {
1662         case ETH_VLAN_TYPE_INNER:
1663                 if (qinq) {
1664                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1671                 } else {
1672                         ret = -ENOTSUP;
1673                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1674                                     " by single VLAN");
1675                 }
1676                 break;
1677         case ETH_VLAN_TYPE_OUTER:
1678                 if (qinq) {
1679                         /* Only the high 16-bits is valid */
1680                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1681                                         IXGBE_EXVET_VET_EXT_SHIFT);
1682                 } else {
1683                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1684                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1685                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1686                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1687                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1688                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1689                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1690                 }
1691
1692                 break;
1693         default:
1694                 ret = -EINVAL;
1695                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1696                 break;
1697         }
1698
1699         return ret;
1700 }
1701
1702 void
1703 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1704 {
1705         struct ixgbe_hw *hw =
1706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707         uint32_t vlnctrl;
1708
1709         PMD_INIT_FUNC_TRACE();
1710
1711         /* Filter Table Disable */
1712         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1714
1715         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1716 }
1717
1718 void
1719 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1720 {
1721         struct ixgbe_hw *hw =
1722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         struct ixgbe_vfta *shadow_vfta =
1724                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1725         uint32_t vlnctrl;
1726         uint16_t i;
1727
1728         PMD_INIT_FUNC_TRACE();
1729
1730         /* Filter Table Enable */
1731         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1732         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1733         vlnctrl |= IXGBE_VLNCTRL_VFE;
1734
1735         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1736
1737         /* write whatever is in local vfta copy */
1738         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1739                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1740 }
1741
1742 static void
1743 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1744 {
1745         struct ixgbe_hwstrip *hwstrip =
1746                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1747         struct ixgbe_rx_queue *rxq;
1748
1749         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1750                 return;
1751
1752         if (on)
1753                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1754         else
1755                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1756
1757         if (queue >= dev->data->nb_rx_queues)
1758                 return;
1759
1760         rxq = dev->data->rx_queues[queue];
1761
1762         if (on)
1763                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1764         else
1765                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1766 }
1767
1768 static void
1769 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1770 {
1771         struct ixgbe_hw *hw =
1772                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         uint32_t ctrl;
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         if (hw->mac.type == ixgbe_mac_82598EB) {
1778                 /* No queue level support */
1779                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1780                 return;
1781         }
1782
1783         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1784         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1785         ctrl &= ~IXGBE_RXDCTL_VME;
1786         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1787
1788         /* record those setting for HW strip per queue */
1789         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1790 }
1791
1792 static void
1793 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1794 {
1795         struct ixgbe_hw *hw =
1796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         uint32_t ctrl;
1798
1799         PMD_INIT_FUNC_TRACE();
1800
1801         if (hw->mac.type == ixgbe_mac_82598EB) {
1802                 /* No queue level supported */
1803                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1804                 return;
1805         }
1806
1807         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1808         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1809         ctrl |= IXGBE_RXDCTL_VME;
1810         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1811
1812         /* record those setting for HW strip per queue */
1813         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1814 }
1815
1816 void
1817 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1818 {
1819         struct ixgbe_hw *hw =
1820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         uint32_t ctrl;
1822         uint16_t i;
1823         struct ixgbe_rx_queue *rxq;
1824
1825         PMD_INIT_FUNC_TRACE();
1826
1827         if (hw->mac.type == ixgbe_mac_82598EB) {
1828                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1829                 ctrl &= ~IXGBE_VLNCTRL_VME;
1830                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1831         } else {
1832                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1833                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1834                         rxq = dev->data->rx_queues[i];
1835                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1836                         ctrl &= ~IXGBE_RXDCTL_VME;
1837                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1838
1839                         /* record those setting for HW strip per queue */
1840                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1841                 }
1842         }
1843 }
1844
1845 void
1846 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1847 {
1848         struct ixgbe_hw *hw =
1849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         uint32_t ctrl;
1851         uint16_t i;
1852         struct ixgbe_rx_queue *rxq;
1853
1854         PMD_INIT_FUNC_TRACE();
1855
1856         if (hw->mac.type == ixgbe_mac_82598EB) {
1857                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1858                 ctrl |= IXGBE_VLNCTRL_VME;
1859                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1860         } else {
1861                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1862                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1863                         rxq = dev->data->rx_queues[i];
1864                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1865                         ctrl |= IXGBE_RXDCTL_VME;
1866                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1867
1868                         /* record those setting for HW strip per queue */
1869                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1870                 }
1871         }
1872 }
1873
1874 static void
1875 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* DMATXCTRL: Geric Double VLAN Disable */
1884         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         ctrl &= ~IXGBE_DMATXCTL_GDV;
1886         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1887
1888         /* CTRL_EXT: Global Double VLAN Disable */
1889         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1890         ctrl &= ~IXGBE_EXTENDED_VLAN;
1891         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1892
1893 }
1894
1895 static void
1896 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1897 {
1898         struct ixgbe_hw *hw =
1899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         uint32_t ctrl;
1901
1902         PMD_INIT_FUNC_TRACE();
1903
1904         /* DMATXCTRL: Geric Double VLAN Enable */
1905         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906         ctrl |= IXGBE_DMATXCTL_GDV;
1907         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1908
1909         /* CTRL_EXT: Global Double VLAN Enable */
1910         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1911         ctrl |= IXGBE_EXTENDED_VLAN;
1912         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1913
1914         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1915         if (hw->mac.type == ixgbe_mac_X550 ||
1916             hw->mac.type == ixgbe_mac_X550EM_x ||
1917             hw->mac.type == ixgbe_mac_X550EM_a) {
1918                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1919                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1920                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1921         }
1922
1923         /*
1924          * VET EXT field in the EXVET register = 0x8100 by default
1925          * So no need to change. Same to VT field of DMATXCTL register
1926          */
1927 }
1928
1929 static void
1930 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1931 {
1932         if (mask & ETH_VLAN_STRIP_MASK) {
1933                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1934                         ixgbe_vlan_hw_strip_enable_all(dev);
1935                 else
1936                         ixgbe_vlan_hw_strip_disable_all(dev);
1937         }
1938
1939         if (mask & ETH_VLAN_FILTER_MASK) {
1940                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1941                         ixgbe_vlan_hw_filter_enable(dev);
1942                 else
1943                         ixgbe_vlan_hw_filter_disable(dev);
1944         }
1945
1946         if (mask & ETH_VLAN_EXTEND_MASK) {
1947                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1948                         ixgbe_vlan_hw_extend_enable(dev);
1949                 else
1950                         ixgbe_vlan_hw_extend_disable(dev);
1951         }
1952 }
1953
1954 static void
1955 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1960         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1961
1962         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1964 }
1965
1966 static int
1967 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1968 {
1969         switch (nb_rx_q) {
1970         case 1:
1971         case 2:
1972                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1973                 break;
1974         case 4:
1975                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1976                 break;
1977         default:
1978                 return -EINVAL;
1979         }
1980
1981         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1982                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1983         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1984                 dev->pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1985         return 0;
1986 }
1987
1988 static int
1989 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1990 {
1991         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1994         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1995
1996         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1997                 /* check multi-queue mode */
1998                 switch (dev_conf->rxmode.mq_mode) {
1999                 case ETH_MQ_RX_VMDQ_DCB:
2000                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2001                         break;
2002                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2003                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2004                         PMD_INIT_LOG(ERR, "SRIOV active,"
2005                                         " unsupported mq_mode rx %d.",
2006                                         dev_conf->rxmode.mq_mode);
2007                         return -EINVAL;
2008                 case ETH_MQ_RX_RSS:
2009                 case ETH_MQ_RX_VMDQ_RSS:
2010                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2011                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2012                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2013                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2014                                                 " invalid queue number"
2015                                                 " for VMDQ RSS, allowed"
2016                                                 " value are 1, 2 or 4.");
2017                                         return -EINVAL;
2018                                 }
2019                         break;
2020                 case ETH_MQ_RX_VMDQ_ONLY:
2021                 case ETH_MQ_RX_NONE:
2022                         /* if nothing mq mode configure, use default scheme */
2023                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2024                         break;
2025                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2026                         /* SRIOV only works in VMDq enable mode */
2027                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2028                                         " wrong mq_mode rx %d.",
2029                                         dev_conf->rxmode.mq_mode);
2030                         return -EINVAL;
2031                 }
2032
2033                 switch (dev_conf->txmode.mq_mode) {
2034                 case ETH_MQ_TX_VMDQ_DCB:
2035                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2036                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2037                         break;
2038                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2039                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2040                         break;
2041                 }
2042
2043                 /* check valid queue number */
2044                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2045                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2046                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2047                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2048                                         " must be less than or equal to %d.",
2049                                         nb_rx_q, nb_tx_q,
2050                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2051                         return -EINVAL;
2052                 }
2053         } else {
2054                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2055                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2056                                           " not supported.");
2057                         return -EINVAL;
2058                 }
2059                 /* check configuration for vmdb+dcb mode */
2060                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2061                         const struct rte_eth_vmdq_dcb_conf *conf;
2062
2063                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2064                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2065                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2066                                 return -EINVAL;
2067                         }
2068                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2069                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2070                                conf->nb_queue_pools == ETH_32_POOLS)) {
2071                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2072                                                 " nb_queue_pools must be %d or %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2078                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2079
2080                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2081                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2082                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2083                                 return -EINVAL;
2084                         }
2085                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2086                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2087                                conf->nb_queue_pools == ETH_32_POOLS)) {
2088                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2089                                                 " nb_queue_pools != %d and"
2090                                                 " nb_queue_pools != %d.",
2091                                                 ETH_16_POOLS, ETH_32_POOLS);
2092                                 return -EINVAL;
2093                         }
2094                 }
2095
2096                 /* For DCB mode check our configuration before we go further */
2097                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2098                         const struct rte_eth_dcb_rx_conf *conf;
2099
2100                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2101                         if (!(conf->nb_tcs == ETH_4_TCS ||
2102                                conf->nb_tcs == ETH_8_TCS)) {
2103                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2104                                                 " and nb_tcs != %d.",
2105                                                 ETH_4_TCS, ETH_8_TCS);
2106                                 return -EINVAL;
2107                         }
2108                 }
2109
2110                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2111                         const struct rte_eth_dcb_tx_conf *conf;
2112
2113                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2114                         if (!(conf->nb_tcs == ETH_4_TCS ||
2115                                conf->nb_tcs == ETH_8_TCS)) {
2116                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2117                                                 " and nb_tcs != %d.",
2118                                                 ETH_4_TCS, ETH_8_TCS);
2119                                 return -EINVAL;
2120                         }
2121                 }
2122
2123                 /*
2124                  * When DCB/VT is off, maximum number of queues changes,
2125                  * except for 82598EB, which remains constant.
2126                  */
2127                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2128                                 hw->mac.type != ixgbe_mac_82598EB) {
2129                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2130                                 PMD_INIT_LOG(ERR,
2131                                              "Neither VT nor DCB are enabled, "
2132                                              "nb_tx_q > %d.",
2133                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2134                                 return -EINVAL;
2135                         }
2136                 }
2137         }
2138         return 0;
2139 }
2140
2141 static int
2142 ixgbe_dev_configure(struct rte_eth_dev *dev)
2143 {
2144         struct ixgbe_interrupt *intr =
2145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2146         struct ixgbe_adapter *adapter =
2147                 (struct ixgbe_adapter *)dev->data->dev_private;
2148         int ret;
2149
2150         PMD_INIT_FUNC_TRACE();
2151         /* multipe queue mode checking */
2152         ret  = ixgbe_check_mq_mode(dev);
2153         if (ret != 0) {
2154                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2155                             ret);
2156                 return ret;
2157         }
2158
2159         /* set flag to update link status after init */
2160         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2161
2162         /*
2163          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2164          * allocation or vector Rx preconditions we will reset it.
2165          */
2166         adapter->rx_bulk_alloc_allowed = true;
2167         adapter->rx_vec_allowed = true;
2168
2169         return 0;
2170 }
2171
2172 static void
2173 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2174 {
2175         struct ixgbe_hw *hw =
2176                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         struct ixgbe_interrupt *intr =
2178                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2179         uint32_t gpie;
2180
2181         /* only set up it on X550EM_X */
2182         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2183                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2184                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2185                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2186                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2187                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2188         }
2189 }
2190
2191 /*
2192  * Configure device link speed and setup link.
2193  * It returns 0 on success.
2194  */
2195 static int
2196 ixgbe_dev_start(struct rte_eth_dev *dev)
2197 {
2198         struct ixgbe_hw *hw =
2199                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct ixgbe_vf_info *vfinfo =
2201                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2202         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2203         uint32_t intr_vector = 0;
2204         int err, link_up = 0, negotiate = 0;
2205         uint32_t speed = 0;
2206         int mask = 0;
2207         int status;
2208         uint16_t vf, idx;
2209         uint32_t *link_speeds;
2210
2211         PMD_INIT_FUNC_TRACE();
2212
2213         /* IXGBE devices don't support:
2214         *    - half duplex (checked afterwards for valid speeds)
2215         *    - fixed speed: TODO implement
2216         */
2217         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2218                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2219                              dev->data->port_id);
2220                 return -EINVAL;
2221         }
2222
2223         /* disable uio/vfio intr/eventfd mapping */
2224         rte_intr_disable(intr_handle);
2225
2226         /* stop adapter */
2227         hw->adapter_stopped = 0;
2228         ixgbe_stop_adapter(hw);
2229
2230         /* reinitialize adapter
2231          * this calls reset and start
2232          */
2233         status = ixgbe_pf_reset_hw(hw);
2234         if (status != 0)
2235                 return -1;
2236         hw->mac.ops.start_hw(hw);
2237         hw->mac.get_link_status = true;
2238
2239         /* configure PF module if SRIOV enabled */
2240         ixgbe_pf_host_configure(dev);
2241
2242         ixgbe_dev_phy_intr_setup(dev);
2243
2244         /* check and configure queue intr-vector mapping */
2245         if ((rte_intr_cap_multiple(intr_handle) ||
2246              !RTE_ETH_DEV_SRIOV(dev).active) &&
2247             dev->data->dev_conf.intr_conf.rxq != 0) {
2248                 intr_vector = dev->data->nb_rx_queues;
2249                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2250                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2251                                         IXGBE_MAX_INTR_QUEUE_NUM);
2252                         return -ENOTSUP;
2253                 }
2254                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2255                         return -1;
2256         }
2257
2258         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2259                 intr_handle->intr_vec =
2260                         rte_zmalloc("intr_vec",
2261                                     dev->data->nb_rx_queues * sizeof(int), 0);
2262                 if (intr_handle->intr_vec == NULL) {
2263                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2264                                      " intr_vec\n", dev->data->nb_rx_queues);
2265                         return -ENOMEM;
2266                 }
2267         }
2268
2269         /* confiugre msix for sleep until rx interrupt */
2270         ixgbe_configure_msix(dev);
2271
2272         /* initialize transmission unit */
2273         ixgbe_dev_tx_init(dev);
2274
2275         /* This can fail when allocating mbufs for descriptor rings */
2276         err = ixgbe_dev_rx_init(dev);
2277         if (err) {
2278                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2279                 goto error;
2280         }
2281
2282     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2283                 ETH_VLAN_EXTEND_MASK;
2284         ixgbe_vlan_offload_set(dev, mask);
2285
2286         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2287                 /* Enable vlan filtering for VMDq */
2288                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2289         }
2290
2291         /* Configure DCB hw */
2292         ixgbe_configure_dcb(dev);
2293
2294         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2295                 err = ixgbe_fdir_configure(dev);
2296                 if (err)
2297                         goto error;
2298         }
2299
2300         /* Restore vf rate limit */
2301         if (vfinfo != NULL) {
2302                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2303                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2304                                 if (vfinfo[vf].tx_rate[idx] != 0)
2305                                         ixgbe_set_vf_rate_limit(dev, vf,
2306                                                 vfinfo[vf].tx_rate[idx],
2307                                                 1 << idx);
2308         }
2309
2310         ixgbe_restore_statistics_mapping(dev);
2311
2312         err = ixgbe_dev_rxtx_start(dev);
2313         if (err < 0) {
2314                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2315                 goto error;
2316         }
2317
2318         /* Skip link setup if loopback mode is enabled for 82599. */
2319         if (hw->mac.type == ixgbe_mac_82599EB &&
2320                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2321                 goto skip_link_setup;
2322
2323         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2324                 err = hw->mac.ops.setup_sfp(hw);
2325                 if (err)
2326                         goto error;
2327         }
2328
2329         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2330                 /* Turn on the copper */
2331                 ixgbe_set_phy_power(hw, true);
2332         } else {
2333                 /* Turn on the laser */
2334                 ixgbe_enable_tx_laser(hw);
2335         }
2336
2337         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2338         if (err)
2339                 goto error;
2340         dev->data->dev_link.link_status = link_up;
2341
2342         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2343         if (err)
2344                 goto error;
2345
2346         link_speeds = &dev->data->dev_conf.link_speeds;
2347         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2348                         ETH_LINK_SPEED_10G)) {
2349                 PMD_INIT_LOG(ERR, "Invalid link setting");
2350                 goto error;
2351         }
2352
2353         speed = 0x0;
2354         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2355                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2356                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2357                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2358         } else {
2359                 if (*link_speeds & ETH_LINK_SPEED_10G)
2360                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2361                 if (*link_speeds & ETH_LINK_SPEED_1G)
2362                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2363                 if (*link_speeds & ETH_LINK_SPEED_100M)
2364                         speed |= IXGBE_LINK_SPEED_100_FULL;
2365         }
2366
2367         err = ixgbe_setup_link(hw, speed, link_up);
2368         if (err)
2369                 goto error;
2370
2371 skip_link_setup:
2372
2373         if (rte_intr_allow_others(intr_handle)) {
2374                 /* check if lsc interrupt is enabled */
2375                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2376                         ixgbe_dev_lsc_interrupt_setup(dev);
2377         } else {
2378                 rte_intr_callback_unregister(intr_handle,
2379                                              ixgbe_dev_interrupt_handler,
2380                                              (void *)dev);
2381                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2382                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2383                                      " no intr multiplex\n");
2384         }
2385
2386         /* check if rxq interrupt is enabled */
2387         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2388             rte_intr_dp_is_en(intr_handle))
2389                 ixgbe_dev_rxq_interrupt_setup(dev);
2390
2391         /* enable uio/vfio intr/eventfd mapping */
2392         rte_intr_enable(intr_handle);
2393
2394         /* resume enabled intr since hw reset */
2395         ixgbe_enable_intr(dev);
2396
2397         return 0;
2398
2399 error:
2400         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2401         ixgbe_dev_clear_queues(dev);
2402         return -EIO;
2403 }
2404
2405 /*
2406  * Stop device: disable rx and tx functions to allow for reconfiguring.
2407  */
2408 static void
2409 ixgbe_dev_stop(struct rte_eth_dev *dev)
2410 {
2411         struct rte_eth_link link;
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct ixgbe_vf_info *vfinfo =
2415                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2416         struct ixgbe_filter_info *filter_info =
2417                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2418         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2419         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2420         int vf;
2421
2422         PMD_INIT_FUNC_TRACE();
2423
2424         /* disable interrupts */
2425         ixgbe_disable_intr(hw);
2426
2427         /* reset the NIC */
2428         ixgbe_pf_reset_hw(hw);
2429         hw->adapter_stopped = 0;
2430
2431         /* stop adapter */
2432         ixgbe_stop_adapter(hw);
2433
2434         for (vf = 0; vfinfo != NULL &&
2435                      vf < dev->pci_dev->max_vfs; vf++)
2436                 vfinfo[vf].clear_to_send = false;
2437
2438         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2439                 /* Turn off the copper */
2440                 ixgbe_set_phy_power(hw, false);
2441         } else {
2442                 /* Turn off the laser */
2443                 ixgbe_disable_tx_laser(hw);
2444         }
2445
2446         ixgbe_dev_clear_queues(dev);
2447
2448         /* Clear stored conf */
2449         dev->data->scattered_rx = 0;
2450         dev->data->lro = 0;
2451
2452         /* Clear recorded link status */
2453         memset(&link, 0, sizeof(link));
2454         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2455
2456         /* Remove all ntuple filters of the device */
2457         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2458              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2459                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2460                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2461                              p_5tuple, entries);
2462                 rte_free(p_5tuple);
2463         }
2464         memset(filter_info->fivetuple_mask, 0,
2465                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2466
2467         if (!rte_intr_allow_others(intr_handle))
2468                 /* resume to the default handler */
2469                 rte_intr_callback_register(intr_handle,
2470                                            ixgbe_dev_interrupt_handler,
2471                                            (void *)dev);
2472
2473         /* Clean datapath event and queue/vec mapping */
2474         rte_intr_efd_disable(intr_handle);
2475         if (intr_handle->intr_vec != NULL) {
2476                 rte_free(intr_handle->intr_vec);
2477                 intr_handle->intr_vec = NULL;
2478         }
2479 }
2480
2481 /*
2482  * Set device link up: enable tx.
2483  */
2484 static int
2485 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2486 {
2487         struct ixgbe_hw *hw =
2488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         if (hw->mac.type == ixgbe_mac_82599EB) {
2490 #ifdef RTE_NIC_BYPASS
2491                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2492                         /* Not suported in bypass mode */
2493                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2494                                      "by device id 0x%x", hw->device_id);
2495                         return -ENOTSUP;
2496                 }
2497 #endif
2498         }
2499
2500         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2501                 /* Turn on the copper */
2502                 ixgbe_set_phy_power(hw, true);
2503         } else {
2504                 /* Turn on the laser */
2505                 ixgbe_enable_tx_laser(hw);
2506         }
2507
2508         return 0;
2509 }
2510
2511 /*
2512  * Set device link down: disable tx.
2513  */
2514 static int
2515 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2516 {
2517         struct ixgbe_hw *hw =
2518                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         if (hw->mac.type == ixgbe_mac_82599EB) {
2520 #ifdef RTE_NIC_BYPASS
2521                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2522                         /* Not suported in bypass mode */
2523                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2524                                      "by device id 0x%x", hw->device_id);
2525                         return -ENOTSUP;
2526                 }
2527 #endif
2528         }
2529
2530         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2531                 /* Turn off the copper */
2532                 ixgbe_set_phy_power(hw, false);
2533         } else {
2534                 /* Turn off the laser */
2535                 ixgbe_disable_tx_laser(hw);
2536         }
2537
2538         return 0;
2539 }
2540
2541 /*
2542  * Reest and stop device.
2543  */
2544 static void
2545 ixgbe_dev_close(struct rte_eth_dev *dev)
2546 {
2547         struct ixgbe_hw *hw =
2548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549
2550         PMD_INIT_FUNC_TRACE();
2551
2552         ixgbe_pf_reset_hw(hw);
2553
2554         ixgbe_dev_stop(dev);
2555         hw->adapter_stopped = 1;
2556
2557         ixgbe_dev_free_queues(dev);
2558
2559         ixgbe_disable_pcie_master(hw);
2560
2561         /* reprogram the RAR[0] in case user changed it. */
2562         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2563 }
2564
2565 static void
2566 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2567                            struct ixgbe_hw_stats *hw_stats,
2568                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2569                            uint64_t *total_qprc, uint64_t *total_qprdc)
2570 {
2571         uint32_t bprc, lxon, lxoff, total;
2572         uint32_t delta_gprc = 0;
2573         unsigned i;
2574         /* Workaround for RX byte count not including CRC bytes when CRC
2575 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2576          * is disabled.
2577 +        */
2578         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2579                         IXGBE_HLREG0_RXCRCSTRP);
2580
2581         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2582         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2583         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2584         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2585
2586         for (i = 0; i < 8; i++) {
2587                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2588
2589                 /* global total per queue */
2590                 hw_stats->mpc[i] += mp;
2591                 /* Running comprehensive total for stats display */
2592                 *total_missed_rx += hw_stats->mpc[i];
2593                 if (hw->mac.type == ixgbe_mac_82598EB) {
2594                         hw_stats->rnbc[i] +=
2595                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2596                         hw_stats->pxonrxc[i] +=
2597                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2598                         hw_stats->pxoffrxc[i] +=
2599                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2600                 } else {
2601                         hw_stats->pxonrxc[i] +=
2602                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2603                         hw_stats->pxoffrxc[i] +=
2604                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2605                         hw_stats->pxon2offc[i] +=
2606                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2607                 }
2608                 hw_stats->pxontxc[i] +=
2609                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2610                 hw_stats->pxofftxc[i] +=
2611                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2612         }
2613         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2614                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2615                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2616                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2617
2618                 delta_gprc += delta_qprc;
2619
2620                 hw_stats->qprc[i] += delta_qprc;
2621                 hw_stats->qptc[i] += delta_qptc;
2622
2623                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2624                 hw_stats->qbrc[i] +=
2625                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2626                 if (crc_strip == 0)
2627                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2628
2629                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2630                 hw_stats->qbtc[i] +=
2631                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2632
2633                 hw_stats->qprdc[i] += delta_qprdc;
2634                 *total_qprdc += hw_stats->qprdc[i];
2635
2636                 *total_qprc += hw_stats->qprc[i];
2637                 *total_qbrc += hw_stats->qbrc[i];
2638         }
2639         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2640         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2641         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2642
2643         /*
2644          * An errata states that gprc actually counts good + missed packets:
2645          * Workaround to set gprc to summated queue packet receives
2646          */
2647         hw_stats->gprc = *total_qprc;
2648
2649         if (hw->mac.type != ixgbe_mac_82598EB) {
2650                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2651                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2652                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2653                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2654                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2655                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2656                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2657                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2658         } else {
2659                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2660                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2661                 /* 82598 only has a counter in the high register */
2662                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2663                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2664                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2665         }
2666         uint64_t old_tpr = hw_stats->tpr;
2667
2668         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2669         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2670
2671         if (crc_strip == 0)
2672                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2673
2674         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2675         hw_stats->gptc += delta_gptc;
2676         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2677         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2678
2679         /*
2680          * Workaround: mprc hardware is incorrectly counting
2681          * broadcasts, so for now we subtract those.
2682          */
2683         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2684         hw_stats->bprc += bprc;
2685         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2686         if (hw->mac.type == ixgbe_mac_82598EB)
2687                 hw_stats->mprc -= bprc;
2688
2689         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2690         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2691         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2692         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2693         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2694         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2695
2696         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2697         hw_stats->lxontxc += lxon;
2698         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2699         hw_stats->lxofftxc += lxoff;
2700         total = lxon + lxoff;
2701
2702         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2703         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2704         hw_stats->gptc -= total;
2705         hw_stats->mptc -= total;
2706         hw_stats->ptc64 -= total;
2707         hw_stats->gotc -= total * ETHER_MIN_LEN;
2708
2709         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2710         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2711         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2712         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2713         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2714         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2715         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2716         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2717         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2718         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2719         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2720         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2721         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2722         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2723         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2724         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2725         /* Only read FCOE on 82599 */
2726         if (hw->mac.type != ixgbe_mac_82598EB) {
2727                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2728                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2729                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2730                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2731                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2732         }
2733
2734         /* Flow Director Stats registers */
2735         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2736         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2737 }
2738
2739 /*
2740  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2741  */
2742 static void
2743 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2744 {
2745         struct ixgbe_hw *hw =
2746                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747         struct ixgbe_hw_stats *hw_stats =
2748                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2749         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2750         unsigned i;
2751
2752         total_missed_rx = 0;
2753         total_qbrc = 0;
2754         total_qprc = 0;
2755         total_qprdc = 0;
2756
2757         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2758                         &total_qprc, &total_qprdc);
2759
2760         if (stats == NULL)
2761                 return;
2762
2763         /* Fill out the rte_eth_stats statistics structure */
2764         stats->ipackets = total_qprc;
2765         stats->ibytes = total_qbrc;
2766         stats->opackets = hw_stats->gptc;
2767         stats->obytes = hw_stats->gotc;
2768
2769         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2770                 stats->q_ipackets[i] = hw_stats->qprc[i];
2771                 stats->q_opackets[i] = hw_stats->qptc[i];
2772                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2773                 stats->q_obytes[i] = hw_stats->qbtc[i];
2774                 stats->q_errors[i] = hw_stats->qprdc[i];
2775         }
2776
2777         /* Rx Errors */
2778         stats->imissed  = total_missed_rx;
2779         stats->ierrors  = hw_stats->crcerrs +
2780                           hw_stats->mspdc +
2781                           hw_stats->rlec +
2782                           hw_stats->ruc +
2783                           hw_stats->roc +
2784                           hw_stats->illerrc +
2785                           hw_stats->errbc +
2786                           hw_stats->rfc +
2787                           hw_stats->fccrc +
2788                           hw_stats->fclast;
2789
2790         /* Tx Errors */
2791         stats->oerrors  = 0;
2792 }
2793
2794 static void
2795 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2796 {
2797         struct ixgbe_hw_stats *stats =
2798                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2799
2800         /* HW registers are cleared on read */
2801         ixgbe_dev_stats_get(dev, NULL);
2802
2803         /* Reset software totals */
2804         memset(stats, 0, sizeof(*stats));
2805 }
2806
2807 /* This function calculates the number of xstats based on the current config */
2808 static unsigned
2809 ixgbe_xstats_calc_num(void) {
2810         return IXGBE_NB_HW_STATS +
2811                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2812                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2813 }
2814
2815 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2816         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2817 {
2818         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2819         unsigned stat, i, count;
2820
2821         if (xstats_names != NULL) {
2822                 count = 0;
2823
2824                 /* Note: limit >= cnt_stats checked upstream
2825                  * in rte_eth_xstats_names()
2826                  */
2827
2828                 /* Extended stats from ixgbe_hw_stats */
2829                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2830                         snprintf(xstats_names[count].name,
2831                                 sizeof(xstats_names[count].name),
2832                                 "%s",
2833                                 rte_ixgbe_stats_strings[i].name);
2834                         count++;
2835                 }
2836
2837                 /* RX Priority Stats */
2838                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2839                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2840                                 snprintf(xstats_names[count].name,
2841                                         sizeof(xstats_names[count].name),
2842                                         "rx_priority%u_%s", i,
2843                                         rte_ixgbe_rxq_strings[stat].name);
2844                                 count++;
2845                         }
2846                 }
2847
2848                 /* TX Priority Stats */
2849                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2850                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2851                                 snprintf(xstats_names[count].name,
2852                                         sizeof(xstats_names[count].name),
2853                                         "tx_priority%u_%s", i,
2854                                         rte_ixgbe_txq_strings[stat].name);
2855                                 count++;
2856                         }
2857                 }
2858         }
2859         return cnt_stats;
2860 }
2861
2862 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2863         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2864 {
2865         unsigned i;
2866
2867         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2868                 return -ENOMEM;
2869
2870         if (xstats_names != NULL)
2871                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2872                         snprintf(xstats_names[i].name,
2873                                 sizeof(xstats_names[i].name),
2874                                 "%s", rte_ixgbevf_stats_strings[i].name);
2875         return IXGBEVF_NB_XSTATS;
2876 }
2877
2878 static int
2879 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2880                                          unsigned n)
2881 {
2882         struct ixgbe_hw *hw =
2883                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct ixgbe_hw_stats *hw_stats =
2885                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2886         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2887         unsigned i, stat, count = 0;
2888
2889         count = ixgbe_xstats_calc_num();
2890
2891         if (n < count)
2892                 return count;
2893
2894         total_missed_rx = 0;
2895         total_qbrc = 0;
2896         total_qprc = 0;
2897         total_qprdc = 0;
2898
2899         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2900                                    &total_qprc, &total_qprdc);
2901
2902         /* If this is a reset xstats is NULL, and we have cleared the
2903          * registers by reading them.
2904          */
2905         if (!xstats)
2906                 return 0;
2907
2908         /* Extended stats from ixgbe_hw_stats */
2909         count = 0;
2910         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2911                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2912                                 rte_ixgbe_stats_strings[i].offset);
2913                 xstats[count].id = count;
2914                 count++;
2915         }
2916
2917         /* RX Priority Stats */
2918         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2919                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2920                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2921                                         rte_ixgbe_rxq_strings[stat].offset +
2922                                         (sizeof(uint64_t) * i));
2923                         xstats[count].id = count;
2924                         count++;
2925                 }
2926         }
2927
2928         /* TX Priority Stats */
2929         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2930                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2931                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2932                                         rte_ixgbe_txq_strings[stat].offset +
2933                                         (sizeof(uint64_t) * i));
2934                         xstats[count].id = count;
2935                         count++;
2936                 }
2937         }
2938         return count;
2939 }
2940
2941 static void
2942 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2943 {
2944         struct ixgbe_hw_stats *stats =
2945                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2946
2947         unsigned count = ixgbe_xstats_calc_num();
2948
2949         /* HW registers are cleared on read */
2950         ixgbe_dev_xstats_get(dev, NULL, count);
2951
2952         /* Reset software totals */
2953         memset(stats, 0, sizeof(*stats));
2954 }
2955
2956 static void
2957 ixgbevf_update_stats(struct rte_eth_dev *dev)
2958 {
2959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2961                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2962
2963         /* Good Rx packet, include VF loopback */
2964         UPDATE_VF_STAT(IXGBE_VFGPRC,
2965             hw_stats->last_vfgprc, hw_stats->vfgprc);
2966
2967         /* Good Rx octets, include VF loopback */
2968         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2969             hw_stats->last_vfgorc, hw_stats->vfgorc);
2970
2971         /* Good Tx packet, include VF loopback */
2972         UPDATE_VF_STAT(IXGBE_VFGPTC,
2973             hw_stats->last_vfgptc, hw_stats->vfgptc);
2974
2975         /* Good Tx octets, include VF loopback */
2976         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2977             hw_stats->last_vfgotc, hw_stats->vfgotc);
2978
2979         /* Rx Multicst Packet */
2980         UPDATE_VF_STAT(IXGBE_VFMPRC,
2981             hw_stats->last_vfmprc, hw_stats->vfmprc);
2982 }
2983
2984 static int
2985 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2986                        unsigned n)
2987 {
2988         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2989                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2990         unsigned i;
2991
2992         if (n < IXGBEVF_NB_XSTATS)
2993                 return IXGBEVF_NB_XSTATS;
2994
2995         ixgbevf_update_stats(dev);
2996
2997         if (!xstats)
2998                 return 0;
2999
3000         /* Extended stats */
3001         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3002                 xstats[i].id = i;
3003                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3004                         rte_ixgbevf_stats_strings[i].offset);
3005         }
3006
3007         return IXGBEVF_NB_XSTATS;
3008 }
3009
3010 static void
3011 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3012 {
3013         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3014                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3015
3016         ixgbevf_update_stats(dev);
3017
3018         if (stats == NULL)
3019                 return;
3020
3021         stats->ipackets = hw_stats->vfgprc;
3022         stats->ibytes = hw_stats->vfgorc;
3023         stats->opackets = hw_stats->vfgptc;
3024         stats->obytes = hw_stats->vfgotc;
3025 }
3026
3027 static void
3028 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3029 {
3030         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3031                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3032
3033         /* Sync HW register to the last stats */
3034         ixgbevf_dev_stats_get(dev, NULL);
3035
3036         /* reset HW current stats*/
3037         hw_stats->vfgprc = 0;
3038         hw_stats->vfgorc = 0;
3039         hw_stats->vfgptc = 0;
3040         hw_stats->vfgotc = 0;
3041 }
3042
3043 static void
3044 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3045 {
3046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3048
3049         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3050         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3051         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3052                 /*
3053                  * When DCB/VT is off, maximum number of queues changes,
3054                  * except for 82598EB, which remains constant.
3055                  */
3056                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3057                                 hw->mac.type != ixgbe_mac_82598EB)
3058                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3059         }
3060         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3061         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3062         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3063         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3064         dev_info->max_vfs = dev->pci_dev->max_vfs;
3065         if (hw->mac.type == ixgbe_mac_82598EB)
3066                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3067         else
3068                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3069         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3070         dev_info->rx_offload_capa =
3071                 DEV_RX_OFFLOAD_VLAN_STRIP |
3072                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3073                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3074                 DEV_RX_OFFLOAD_TCP_CKSUM;
3075
3076         /*
3077          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3078          * mode.
3079          */
3080         if ((hw->mac.type == ixgbe_mac_82599EB ||
3081              hw->mac.type == ixgbe_mac_X540) &&
3082             !RTE_ETH_DEV_SRIOV(dev).active)
3083                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3084
3085         if (hw->mac.type == ixgbe_mac_X550 ||
3086             hw->mac.type == ixgbe_mac_X550EM_x ||
3087             hw->mac.type == ixgbe_mac_X550EM_a)
3088                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3089
3090         dev_info->tx_offload_capa =
3091                 DEV_TX_OFFLOAD_VLAN_INSERT |
3092                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3093                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3094                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3095                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3096                 DEV_TX_OFFLOAD_TCP_TSO;
3097
3098         if (hw->mac.type == ixgbe_mac_X550 ||
3099             hw->mac.type == ixgbe_mac_X550EM_x ||
3100             hw->mac.type == ixgbe_mac_X550EM_a)
3101                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3102
3103         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3104                 .rx_thresh = {
3105                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3106                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3107                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3108                 },
3109                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3110                 .rx_drop_en = 0,
3111         };
3112
3113         dev_info->default_txconf = (struct rte_eth_txconf) {
3114                 .tx_thresh = {
3115                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3116                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3117                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3118                 },
3119                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3120                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3121                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3122                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3123         };
3124
3125         dev_info->rx_desc_lim = rx_desc_lim;
3126         dev_info->tx_desc_lim = tx_desc_lim;
3127
3128         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3129         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3130         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3131
3132         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3133         if (hw->mac.type == ixgbe_mac_X540 ||
3134             hw->mac.type == ixgbe_mac_X540_vf ||
3135             hw->mac.type == ixgbe_mac_X550 ||
3136             hw->mac.type == ixgbe_mac_X550_vf) {
3137                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3138         }
3139 }
3140
3141 static const uint32_t *
3142 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3143 {
3144         static const uint32_t ptypes[] = {
3145                 /* For non-vec functions,
3146                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3147                  * for vec functions,
3148                  * refers to _recv_raw_pkts_vec().
3149                  */
3150                 RTE_PTYPE_L2_ETHER,
3151                 RTE_PTYPE_L3_IPV4,
3152                 RTE_PTYPE_L3_IPV4_EXT,
3153                 RTE_PTYPE_L3_IPV6,
3154                 RTE_PTYPE_L3_IPV6_EXT,
3155                 RTE_PTYPE_L4_SCTP,
3156                 RTE_PTYPE_L4_TCP,
3157                 RTE_PTYPE_L4_UDP,
3158                 RTE_PTYPE_TUNNEL_IP,
3159                 RTE_PTYPE_INNER_L3_IPV6,
3160                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3161                 RTE_PTYPE_INNER_L4_TCP,
3162                 RTE_PTYPE_INNER_L4_UDP,
3163                 RTE_PTYPE_UNKNOWN
3164         };
3165
3166         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3167             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3168             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3169             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3170                 return ptypes;
3171         return NULL;
3172 }
3173
3174 static void
3175 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3176                      struct rte_eth_dev_info *dev_info)
3177 {
3178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179
3180         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3181         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3182         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3183         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3184         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3185         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3186         dev_info->max_vfs = dev->pci_dev->max_vfs;
3187         if (hw->mac.type == ixgbe_mac_82598EB)
3188                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3189         else
3190                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3191         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3192                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3193                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3194                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3195         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3196                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3197                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3198                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3199                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3200                                 DEV_TX_OFFLOAD_TCP_TSO;
3201
3202         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3203                 .rx_thresh = {
3204                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3205                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3206                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3207                 },
3208                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3209                 .rx_drop_en = 0,
3210         };
3211
3212         dev_info->default_txconf = (struct rte_eth_txconf) {
3213                 .tx_thresh = {
3214                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3215                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3216                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3217                 },
3218                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3219                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3220                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3221                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3222         };
3223
3224         dev_info->rx_desc_lim = rx_desc_lim;
3225         dev_info->tx_desc_lim = tx_desc_lim;
3226 }
3227
3228 static int
3229 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3230                    int *link_up, int wait_to_complete)
3231 {
3232         /**
3233          * for a quick link status checking, wait_to_compelet == 0,
3234          * skip PF link status checking
3235          */
3236         bool no_pflink_check = wait_to_complete == 0;
3237         struct ixgbe_mbx_info *mbx = &hw->mbx;
3238         struct ixgbe_mac_info *mac = &hw->mac;
3239         uint32_t links_reg, in_msg;
3240         int ret_val = 0;
3241
3242         /* If we were hit with a reset drop the link */
3243         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3244                 mac->get_link_status = true;
3245
3246         if (!mac->get_link_status)
3247                 goto out;
3248
3249         /* if link status is down no point in checking to see if pf is up */
3250         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3251         if (!(links_reg & IXGBE_LINKS_UP))
3252                 goto out;
3253
3254         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3255          * before the link status is correct
3256          */
3257         if (mac->type == ixgbe_mac_82599_vf) {
3258                 int i;
3259
3260                 for (i = 0; i < 5; i++) {
3261                         rte_delay_us(100);
3262                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3263
3264                         if (!(links_reg & IXGBE_LINKS_UP))
3265                                 goto out;
3266                 }
3267         }
3268
3269         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3270         case IXGBE_LINKS_SPEED_10G_82599:
3271                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3272                 if (hw->mac.type >= ixgbe_mac_X550) {
3273                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3274                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3275                 }
3276                 break;
3277         case IXGBE_LINKS_SPEED_1G_82599:
3278                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3279                 break;
3280         case IXGBE_LINKS_SPEED_100_82599:
3281                 *speed = IXGBE_LINK_SPEED_100_FULL;
3282                 if (hw->mac.type == ixgbe_mac_X550) {
3283                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3284                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3285                 }
3286                 break;
3287         case IXGBE_LINKS_SPEED_10_X550EM_A:
3288                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3289                 /* Since Reserved in older MAC's */
3290                 if (hw->mac.type >= ixgbe_mac_X550)
3291                         *speed = IXGBE_LINK_SPEED_10_FULL;
3292                 break;
3293         default:
3294                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3295         }
3296
3297         if (no_pflink_check) {
3298                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3299                         mac->get_link_status = true;
3300                 else
3301                         mac->get_link_status = false;
3302
3303                 goto out;
3304         }
3305         /* if the read failed it could just be a mailbox collision, best wait
3306          * until we are called again and don't report an error
3307          */
3308         if (mbx->ops.read(hw, &in_msg, 1, 0))
3309                 goto out;
3310
3311         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3312                 /* msg is not CTS and is NACK we must have lost CTS status */
3313                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3314                         ret_val = -1;
3315                 goto out;
3316         }
3317
3318         /* the pf is talking, if we timed out in the past we reinit */
3319         if (!mbx->timeout) {
3320                 ret_val = -1;
3321                 goto out;
3322         }
3323
3324         /* if we passed all the tests above then the link is up and we no
3325          * longer need to check for link
3326          */
3327         mac->get_link_status = false;
3328
3329 out:
3330         *link_up = !mac->get_link_status;
3331         return ret_val;
3332 }
3333
3334 /* return 0 means link status changed, -1 means not changed */
3335 static int
3336 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3337                             int wait_to_complete, int vf)
3338 {
3339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         struct rte_eth_link link, old;
3341         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3342         int link_up;
3343         int diag;
3344         int wait = 1;
3345
3346         link.link_status = ETH_LINK_DOWN;
3347         link.link_speed = 0;
3348         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3349         link.link_autoneg = ETH_LINK_AUTONEG;
3350         memset(&old, 0, sizeof(old));
3351         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3352
3353         hw->mac.get_link_status = true;
3354
3355         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3356         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3357                 wait = 0;
3358
3359         if (vf)
3360                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3361         else
3362                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3363
3364         if (diag != 0) {
3365                 link.link_speed = ETH_SPEED_NUM_100M;
3366                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3367                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3368                 if (link.link_status == old.link_status)
3369                         return -1;
3370                 return 0;
3371         }
3372
3373         if (link_up == 0) {
3374                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3375                 if (link.link_status == old.link_status)
3376                         return -1;
3377                 return 0;
3378         }
3379         link.link_status = ETH_LINK_UP;
3380         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3381
3382         switch (link_speed) {
3383         default:
3384         case IXGBE_LINK_SPEED_UNKNOWN:
3385                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3386                 link.link_speed = ETH_SPEED_NUM_100M;
3387                 break;
3388
3389         case IXGBE_LINK_SPEED_100_FULL:
3390                 link.link_speed = ETH_SPEED_NUM_100M;
3391                 break;
3392
3393         case IXGBE_LINK_SPEED_1GB_FULL:
3394                 link.link_speed = ETH_SPEED_NUM_1G;
3395                 break;
3396
3397         case IXGBE_LINK_SPEED_10GB_FULL:
3398                 link.link_speed = ETH_SPEED_NUM_10G;
3399                 break;
3400         }
3401         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3402
3403         if (link.link_status == old.link_status)
3404                 return -1;
3405
3406         return 0;
3407 }
3408
3409 static int
3410 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3411 {
3412         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3413 }
3414
3415 static int
3416 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3417 {
3418         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3419 }
3420
3421 static void
3422 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3423 {
3424         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425         uint32_t fctrl;
3426
3427         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3428         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3429         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3430 }
3431
3432 static void
3433 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3434 {
3435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436         uint32_t fctrl;
3437
3438         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3439         fctrl &= (~IXGBE_FCTRL_UPE);
3440         if (dev->data->all_multicast == 1)
3441                 fctrl |= IXGBE_FCTRL_MPE;
3442         else
3443                 fctrl &= (~IXGBE_FCTRL_MPE);
3444         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3445 }
3446
3447 static void
3448 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3449 {
3450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451         uint32_t fctrl;
3452
3453         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3454         fctrl |= IXGBE_FCTRL_MPE;
3455         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3456 }
3457
3458 static void
3459 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3460 {
3461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462         uint32_t fctrl;
3463
3464         if (dev->data->promiscuous == 1)
3465                 return; /* must remain in all_multicast mode */
3466
3467         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3468         fctrl &= (~IXGBE_FCTRL_MPE);
3469         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3470 }
3471
3472 /**
3473  * It clears the interrupt causes and enables the interrupt.
3474  * It will be called once only during nic initialized.
3475  *
3476  * @param dev
3477  *  Pointer to struct rte_eth_dev.
3478  *
3479  * @return
3480  *  - On success, zero.
3481  *  - On failure, a negative value.
3482  */
3483 static int
3484 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3485 {
3486         struct ixgbe_interrupt *intr =
3487                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3488
3489         ixgbe_dev_link_status_print(dev);
3490         intr->mask |= IXGBE_EICR_LSC;
3491
3492         return 0;
3493 }
3494
3495 /**
3496  * It clears the interrupt causes and enables the interrupt.
3497  * It will be called once only during nic initialized.
3498  *
3499  * @param dev
3500  *  Pointer to struct rte_eth_dev.
3501  *
3502  * @return
3503  *  - On success, zero.
3504  *  - On failure, a negative value.
3505  */
3506 static int
3507 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3508 {
3509         struct ixgbe_interrupt *intr =
3510                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3511
3512         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3513
3514         return 0;
3515 }
3516
3517 /*
3518  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3519  *
3520  * @param dev
3521  *  Pointer to struct rte_eth_dev.
3522  *
3523  * @return
3524  *  - On success, zero.
3525  *  - On failure, a negative value.
3526  */
3527 static int
3528 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3529 {
3530         uint32_t eicr;
3531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532         struct ixgbe_interrupt *intr =
3533                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3534
3535         /* clear all cause mask */
3536         ixgbe_disable_intr(hw);
3537
3538         /* read-on-clear nic registers here */
3539         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3540         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3541
3542         intr->flags = 0;
3543
3544         /* set flag for async link update */
3545         if (eicr & IXGBE_EICR_LSC)
3546                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3547
3548         if (eicr & IXGBE_EICR_MAILBOX)
3549                 intr->flags |= IXGBE_FLAG_MAILBOX;
3550
3551         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3552             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3553             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3554                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3555
3556         return 0;
3557 }
3558
3559 /**
3560  * It gets and then prints the link status.
3561  *
3562  * @param dev
3563  *  Pointer to struct rte_eth_dev.
3564  *
3565  * @return
3566  *  - On success, zero.
3567  *  - On failure, a negative value.
3568  */
3569 static void
3570 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3571 {
3572         struct rte_eth_link link;
3573
3574         memset(&link, 0, sizeof(link));
3575         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3576         if (link.link_status) {
3577                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3578                                         (int)(dev->data->port_id),
3579                                         (unsigned)link.link_speed,
3580                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3581                                         "full-duplex" : "half-duplex");
3582         } else {
3583                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3584                                 (int)(dev->data->port_id));
3585         }
3586         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3587                                 dev->pci_dev->addr.domain,
3588                                 dev->pci_dev->addr.bus,
3589                                 dev->pci_dev->addr.devid,
3590                                 dev->pci_dev->addr.function);
3591 }
3592
3593 /*
3594  * It executes link_update after knowing an interrupt occurred.
3595  *
3596  * @param dev
3597  *  Pointer to struct rte_eth_dev.
3598  *
3599  * @return
3600  *  - On success, zero.
3601  *  - On failure, a negative value.
3602  */
3603 static int
3604 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3605 {
3606         struct ixgbe_interrupt *intr =
3607                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3608         int64_t timeout;
3609         struct rte_eth_link link;
3610         struct ixgbe_hw *hw =
3611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612
3613         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3614
3615         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3616                 ixgbe_pf_mbx_process(dev);
3617                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3618         }
3619
3620         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3621                 ixgbe_handle_lasi(hw);
3622                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3623         }
3624
3625         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3626                 /* get the link status before link update, for predicting later */
3627                 memset(&link, 0, sizeof(link));
3628                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3629
3630                 ixgbe_dev_link_update(dev, 0);
3631
3632                 /* likely to up */
3633                 if (!link.link_status)
3634                         /* handle it 1 sec later, wait it being stable */
3635                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3636                 /* likely to down */
3637                 else
3638                         /* handle it 4 sec later, wait it being stable */
3639                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3640
3641                 ixgbe_dev_link_status_print(dev);
3642                 intr->mask_original = intr->mask;
3643                 /* only disable lsc interrupt */
3644                 intr->mask &= ~IXGBE_EIMS_LSC;
3645                 if (rte_eal_alarm_set(timeout * 1000,
3646                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3647                         PMD_DRV_LOG(ERR, "Error setting alarm");
3648                 else
3649                         intr->mask = intr->mask_original;
3650         }
3651
3652         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3653         ixgbe_enable_intr(dev);
3654         rte_intr_enable(&dev->pci_dev->intr_handle);
3655
3656         return 0;
3657 }
3658
3659 /**
3660  * Interrupt handler which shall be registered for alarm callback for delayed
3661  * handling specific interrupt to wait for the stable nic state. As the
3662  * NIC interrupt state is not stable for ixgbe after link is just down,
3663  * it needs to wait 4 seconds to get the stable status.
3664  *
3665  * @param handle
3666  *  Pointer to interrupt handle.
3667  * @param param
3668  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3669  *
3670  * @return
3671  *  void
3672  */
3673 static void
3674 ixgbe_dev_interrupt_delayed_handler(void *param)
3675 {
3676         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3677         struct ixgbe_interrupt *intr =
3678                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3679         struct ixgbe_hw *hw =
3680                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681         uint32_t eicr;
3682
3683         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3684         if (eicr & IXGBE_EICR_MAILBOX)
3685                 ixgbe_pf_mbx_process(dev);
3686
3687         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3688                 ixgbe_handle_lasi(hw);
3689                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3690         }
3691
3692         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3693                 ixgbe_dev_link_update(dev, 0);
3694                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3695                 ixgbe_dev_link_status_print(dev);
3696                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3697         }
3698
3699         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3700         ixgbe_enable_intr(dev);
3701         rte_intr_enable(&(dev->pci_dev->intr_handle));
3702 }
3703
3704 /**
3705  * Interrupt handler triggered by NIC  for handling
3706  * specific interrupt.
3707  *
3708  * @param handle
3709  *  Pointer to interrupt handle.
3710  * @param param
3711  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3712  *
3713  * @return
3714  *  void
3715  */
3716 static void
3717 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3718                             void *param)
3719 {
3720         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3721
3722         ixgbe_dev_interrupt_get_status(dev);
3723         ixgbe_dev_interrupt_action(dev);
3724 }
3725
3726 static int
3727 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3728 {
3729         struct ixgbe_hw *hw;
3730
3731         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3733 }
3734
3735 static int
3736 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3737 {
3738         struct ixgbe_hw *hw;
3739
3740         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3742 }
3743
3744 static int
3745 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3746 {
3747         struct ixgbe_hw *hw;
3748         uint32_t mflcn_reg;
3749         uint32_t fccfg_reg;
3750         int rx_pause;
3751         int tx_pause;
3752
3753         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754
3755         fc_conf->pause_time = hw->fc.pause_time;
3756         fc_conf->high_water = hw->fc.high_water[0];
3757         fc_conf->low_water = hw->fc.low_water[0];
3758         fc_conf->send_xon = hw->fc.send_xon;
3759         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3760
3761         /*
3762          * Return rx_pause status according to actual setting of
3763          * MFLCN register.
3764          */
3765         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3766         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3767                 rx_pause = 1;
3768         else
3769                 rx_pause = 0;
3770
3771         /*
3772          * Return tx_pause status according to actual setting of
3773          * FCCFG register.
3774          */
3775         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3776         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3777                 tx_pause = 1;
3778         else
3779                 tx_pause = 0;
3780
3781         if (rx_pause && tx_pause)
3782                 fc_conf->mode = RTE_FC_FULL;
3783         else if (rx_pause)
3784                 fc_conf->mode = RTE_FC_RX_PAUSE;
3785         else if (tx_pause)
3786                 fc_conf->mode = RTE_FC_TX_PAUSE;
3787         else
3788                 fc_conf->mode = RTE_FC_NONE;
3789
3790         return 0;
3791 }
3792
3793 static int
3794 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3795 {
3796         struct ixgbe_hw *hw;
3797         int err;
3798         uint32_t rx_buf_size;
3799         uint32_t max_high_water;
3800         uint32_t mflcn;
3801         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3802                 ixgbe_fc_none,
3803                 ixgbe_fc_rx_pause,
3804                 ixgbe_fc_tx_pause,
3805                 ixgbe_fc_full
3806         };
3807
3808         PMD_INIT_FUNC_TRACE();
3809
3810         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3812         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3813
3814         /*
3815          * At least reserve one Ethernet frame for watermark
3816          * high_water/low_water in kilo bytes for ixgbe
3817          */
3818         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3819         if ((fc_conf->high_water > max_high_water) ||
3820                 (fc_conf->high_water < fc_conf->low_water)) {
3821                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3822                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3823                 return -EINVAL;
3824         }
3825
3826         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3827         hw->fc.pause_time     = fc_conf->pause_time;
3828         hw->fc.high_water[0]  = fc_conf->high_water;
3829         hw->fc.low_water[0]   = fc_conf->low_water;
3830         hw->fc.send_xon       = fc_conf->send_xon;
3831         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3832
3833         err = ixgbe_fc_enable(hw);
3834
3835         /* Not negotiated is not an error case */
3836         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3837
3838                 /* check if we want to forward MAC frames - driver doesn't have native
3839                  * capability to do that, so we'll write the registers ourselves */
3840
3841                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3842
3843                 /* set or clear MFLCN.PMCF bit depending on configuration */
3844                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3845                         mflcn |= IXGBE_MFLCN_PMCF;
3846                 else
3847                         mflcn &= ~IXGBE_MFLCN_PMCF;
3848
3849                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3850                 IXGBE_WRITE_FLUSH(hw);
3851
3852                 return 0;
3853         }
3854
3855         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3856         return -EIO;
3857 }
3858
3859 /**
3860  *  ixgbe_pfc_enable_generic - Enable flow control
3861  *  @hw: pointer to hardware structure
3862  *  @tc_num: traffic class number
3863  *  Enable flow control according to the current settings.
3864  */
3865 static int
3866 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3867 {
3868         int ret_val = 0;
3869         uint32_t mflcn_reg, fccfg_reg;
3870         uint32_t reg;
3871         uint32_t fcrtl, fcrth;
3872         uint8_t i;
3873         uint8_t nb_rx_en;
3874
3875         /* Validate the water mark configuration */
3876         if (!hw->fc.pause_time) {
3877                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3878                 goto out;
3879         }
3880
3881         /* Low water mark of zero causes XOFF floods */
3882         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3883                  /* High/Low water can not be 0 */
3884                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3885                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3886                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3887                         goto out;
3888                 }
3889
3890                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3891                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3892                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3893                         goto out;
3894                 }
3895         }
3896         /* Negotiate the fc mode to use */
3897         ixgbe_fc_autoneg(hw);
3898
3899         /* Disable any previous flow control settings */
3900         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3901         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3902
3903         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3904         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3905
3906         switch (hw->fc.current_mode) {
3907         case ixgbe_fc_none:
3908                 /*
3909                  * If the count of enabled RX Priority Flow control >1,
3910                  * and the TX pause can not be disabled
3911                  */
3912                 nb_rx_en = 0;
3913                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3914                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3915                         if (reg & IXGBE_FCRTH_FCEN)
3916                                 nb_rx_en++;
3917                 }
3918                 if (nb_rx_en > 1)
3919                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3920                 break;
3921         case ixgbe_fc_rx_pause:
3922                 /*
3923                  * Rx Flow control is enabled and Tx Flow control is
3924                  * disabled by software override. Since there really
3925                  * isn't a way to advertise that we are capable of RX
3926                  * Pause ONLY, we will advertise that we support both
3927                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3928                  * disable the adapter's ability to send PAUSE frames.
3929                  */
3930                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3931                 /*
3932                  * If the count of enabled RX Priority Flow control >1,
3933                  * and the TX pause can not be disabled
3934                  */
3935                 nb_rx_en = 0;
3936                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3937                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3938                         if (reg & IXGBE_FCRTH_FCEN)
3939                                 nb_rx_en++;
3940                 }
3941                 if (nb_rx_en > 1)
3942                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3943                 break;
3944         case ixgbe_fc_tx_pause:
3945                 /*
3946                  * Tx Flow control is enabled, and Rx Flow control is
3947                  * disabled by software override.
3948                  */
3949                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3950                 break;
3951         case ixgbe_fc_full:
3952                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3953                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3954                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3955                 break;
3956         default:
3957                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3958                 ret_val = IXGBE_ERR_CONFIG;
3959                 goto out;
3960         }
3961
3962         /* Set 802.3x based flow control settings. */
3963         mflcn_reg |= IXGBE_MFLCN_DPF;
3964         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3965         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3966
3967         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3968         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3969                 hw->fc.high_water[tc_num]) {
3970                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3971                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3972                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3973         } else {
3974                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3975                 /*
3976                  * In order to prevent Tx hangs when the internal Tx
3977                  * switch is enabled we must set the high water mark
3978                  * to the maximum FCRTH value.  This allows the Tx
3979                  * switch to function even under heavy Rx workloads.
3980                  */
3981                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3982         }
3983         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3984
3985         /* Configure pause time (2 TCs per register) */
3986         reg = hw->fc.pause_time * 0x00010001;
3987         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3988                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3989
3990         /* Configure flow control refresh threshold value */
3991         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3992
3993 out:
3994         return ret_val;
3995 }
3996
3997 static int
3998 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3999 {
4000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4002
4003         if (hw->mac.type != ixgbe_mac_82598EB) {
4004                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4005         }
4006         return ret_val;
4007 }
4008
4009 static int
4010 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4011 {
4012         int err;
4013         uint32_t rx_buf_size;
4014         uint32_t max_high_water;
4015         uint8_t tc_num;
4016         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4017         struct ixgbe_hw *hw =
4018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         struct ixgbe_dcb_config *dcb_config =
4020                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4021
4022         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4023                 ixgbe_fc_none,
4024                 ixgbe_fc_rx_pause,
4025                 ixgbe_fc_tx_pause,
4026                 ixgbe_fc_full
4027         };
4028
4029         PMD_INIT_FUNC_TRACE();
4030
4031         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4032         tc_num = map[pfc_conf->priority];
4033         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4034         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4035         /*
4036          * At least reserve one Ethernet frame for watermark
4037          * high_water/low_water in kilo bytes for ixgbe
4038          */
4039         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4040         if ((pfc_conf->fc.high_water > max_high_water) ||
4041             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4042                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4043                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4044                 return -EINVAL;
4045         }
4046
4047         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4048         hw->fc.pause_time = pfc_conf->fc.pause_time;
4049         hw->fc.send_xon = pfc_conf->fc.send_xon;
4050         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4051         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4052
4053         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4054
4055         /* Not negotiated is not an error case */
4056         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4057                 return 0;
4058
4059         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4060         return -EIO;
4061 }
4062
4063 static int
4064 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4065                           struct rte_eth_rss_reta_entry64 *reta_conf,
4066                           uint16_t reta_size)
4067 {
4068         uint16_t i, sp_reta_size;
4069         uint8_t j, mask;
4070         uint32_t reta, r;
4071         uint16_t idx, shift;
4072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073         uint32_t reta_reg;
4074
4075         PMD_INIT_FUNC_TRACE();
4076
4077         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4078                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4079                         "NIC.");
4080                 return -ENOTSUP;
4081         }
4082
4083         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4084         if (reta_size != sp_reta_size) {
4085                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4086                         "(%d) doesn't match the number hardware can supported "
4087                         "(%d)\n", reta_size, sp_reta_size);
4088                 return -EINVAL;
4089         }
4090
4091         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4092                 idx = i / RTE_RETA_GROUP_SIZE;
4093                 shift = i % RTE_RETA_GROUP_SIZE;
4094                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4095                                                 IXGBE_4_BIT_MASK);
4096                 if (!mask)
4097                         continue;
4098                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4099                 if (mask == IXGBE_4_BIT_MASK)
4100                         r = 0;
4101                 else
4102                         r = IXGBE_READ_REG(hw, reta_reg);
4103                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4104                         if (mask & (0x1 << j))
4105                                 reta |= reta_conf[idx].reta[shift + j] <<
4106                                                         (CHAR_BIT * j);
4107                         else
4108                                 reta |= r & (IXGBE_8_BIT_MASK <<
4109                                                 (CHAR_BIT * j));
4110                 }
4111                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4112         }
4113
4114         return 0;
4115 }
4116
4117 static int
4118 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4119                          struct rte_eth_rss_reta_entry64 *reta_conf,
4120                          uint16_t reta_size)
4121 {
4122         uint16_t i, sp_reta_size;
4123         uint8_t j, mask;
4124         uint32_t reta;
4125         uint16_t idx, shift;
4126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         uint32_t reta_reg;
4128
4129         PMD_INIT_FUNC_TRACE();
4130         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4131         if (reta_size != sp_reta_size) {
4132                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4133                         "(%d) doesn't match the number hardware can supported "
4134                         "(%d)\n", reta_size, sp_reta_size);
4135                 return -EINVAL;
4136         }
4137
4138         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4139                 idx = i / RTE_RETA_GROUP_SIZE;
4140                 shift = i % RTE_RETA_GROUP_SIZE;
4141                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4142                                                 IXGBE_4_BIT_MASK);
4143                 if (!mask)
4144                         continue;
4145
4146                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4147                 reta = IXGBE_READ_REG(hw, reta_reg);
4148                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4149                         if (mask & (0x1 << j))
4150                                 reta_conf[idx].reta[shift + j] =
4151                                         ((reta >> (CHAR_BIT * j)) &
4152                                                 IXGBE_8_BIT_MASK);
4153                 }
4154         }
4155
4156         return 0;
4157 }
4158
4159 static void
4160 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4161                                 uint32_t index, uint32_t pool)
4162 {
4163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4164         uint32_t enable_addr = 1;
4165
4166         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4167 }
4168
4169 static void
4170 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4171 {
4172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4173
4174         ixgbe_clear_rar(hw, index);
4175 }
4176
4177 static void
4178 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4179 {
4180         ixgbe_remove_rar(dev, 0);
4181
4182         ixgbe_add_rar(dev, addr, 0, 0);
4183 }
4184
4185 int
4186 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4187                 struct ether_addr *mac_addr)
4188 {
4189         struct ixgbe_hw *hw;
4190         struct ixgbe_vf_info *vfinfo;
4191         int rar_entry;
4192         uint8_t *new_mac = (uint8_t *)(mac_addr);
4193         struct rte_eth_dev *dev;
4194         struct rte_eth_dev_info dev_info;
4195
4196         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4197
4198         dev = &rte_eth_devices[port];
4199         rte_eth_dev_info_get(port, &dev_info);
4200
4201         if (vf >= dev_info.max_vfs)
4202                 return -EINVAL;
4203
4204         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4206         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4207
4208         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4209                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4210                                 ETHER_ADDR_LEN);
4211                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4212                                 IXGBE_RAH_AV);
4213         }
4214         return -EINVAL;
4215 }
4216
4217 static int
4218 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4219 {
4220         uint32_t hlreg0;
4221         uint32_t maxfrs;
4222         struct ixgbe_hw *hw;
4223         struct rte_eth_dev_info dev_info;
4224         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4225         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4226
4227         ixgbe_dev_info_get(dev, &dev_info);
4228
4229         /* check that mtu is within the allowed range */
4230         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4231                 return -EINVAL;
4232
4233         /* refuse mtu that requires the support of scattered packets when this
4234          * feature has not been enabled before.
4235          */
4236         if (!rx_conf->enable_scatter &&
4237             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4238              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4239                 return -EINVAL;
4240
4241         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4242         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4243
4244         /* switch to jumbo mode if needed */
4245         if (frame_size > ETHER_MAX_LEN) {
4246                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4247                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4248         } else {
4249                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4250                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4251         }
4252         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4253
4254         /* update max frame size */
4255         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4256
4257         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4258         maxfrs &= 0x0000FFFF;
4259         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4260         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4261
4262         return 0;
4263 }
4264
4265 /*
4266  * Virtual Function operations
4267  */
4268 static void
4269 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4270 {
4271         PMD_INIT_FUNC_TRACE();
4272
4273         /* Clear interrupt mask to stop from interrupts being generated */
4274         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4275
4276         IXGBE_WRITE_FLUSH(hw);
4277 }
4278
4279 static void
4280 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4281 {
4282         PMD_INIT_FUNC_TRACE();
4283
4284         /* VF enable interrupt autoclean */
4285         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4286         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4287         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4288
4289         IXGBE_WRITE_FLUSH(hw);
4290 }
4291
4292 static int
4293 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4294 {
4295         struct rte_eth_conf *conf = &dev->data->dev_conf;
4296         struct ixgbe_adapter *adapter =
4297                         (struct ixgbe_adapter *)dev->data->dev_private;
4298
4299         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4300                      dev->data->port_id);
4301
4302         /*
4303          * VF has no ability to enable/disable HW CRC
4304          * Keep the persistent behavior the same as Host PF
4305          */
4306 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4307         if (!conf->rxmode.hw_strip_crc) {
4308                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4309                 conf->rxmode.hw_strip_crc = 1;
4310         }
4311 #else
4312         if (conf->rxmode.hw_strip_crc) {
4313                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4314                 conf->rxmode.hw_strip_crc = 0;
4315         }
4316 #endif
4317
4318         /*
4319          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4320          * allocation or vector Rx preconditions we will reset it.
4321          */
4322         adapter->rx_bulk_alloc_allowed = true;
4323         adapter->rx_vec_allowed = true;
4324
4325         return 0;
4326 }
4327
4328 static int
4329 ixgbevf_dev_start(struct rte_eth_dev *dev)
4330 {
4331         struct ixgbe_hw *hw =
4332                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4333         uint32_t intr_vector = 0;
4334         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4335
4336         int err, mask = 0;
4337
4338         PMD_INIT_FUNC_TRACE();
4339
4340         err = hw->mac.ops.reset_hw(hw);
4341         if (err) {
4342                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4343                 return err;
4344         }
4345         hw->mac.get_link_status = true;
4346
4347         /* negotiate mailbox API version to use with the PF. */
4348         ixgbevf_negotiate_api(hw);
4349
4350         ixgbevf_dev_tx_init(dev);
4351
4352         /* This can fail when allocating mbufs for descriptor rings */
4353         err = ixgbevf_dev_rx_init(dev);
4354         if (err) {
4355                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4356                 ixgbe_dev_clear_queues(dev);
4357                 return err;
4358         }
4359
4360         /* Set vfta */
4361         ixgbevf_set_vfta_all(dev, 1);
4362
4363         /* Set HW strip */
4364         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4365                 ETH_VLAN_EXTEND_MASK;
4366         ixgbevf_vlan_offload_set(dev, mask);
4367
4368         ixgbevf_dev_rxtx_start(dev);
4369
4370         /* check and configure queue intr-vector mapping */
4371         if (rte_intr_cap_multiple(intr_handle) &&
4372             dev->data->dev_conf.intr_conf.rxq != 0) {
4373                 intr_vector = dev->data->nb_rx_queues;
4374                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4375                         return -1;
4376         }
4377
4378         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4379                 intr_handle->intr_vec =
4380                         rte_zmalloc("intr_vec",
4381                                     dev->data->nb_rx_queues * sizeof(int), 0);
4382                 if (intr_handle->intr_vec == NULL) {
4383                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4384                                      " intr_vec\n", dev->data->nb_rx_queues);
4385                         return -ENOMEM;
4386                 }
4387         }
4388         ixgbevf_configure_msix(dev);
4389
4390         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
4391          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
4392          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
4393          * is not cleared, it will fail when following rte_intr_enable( ) tries
4394          * to map Rx queue interrupt to other VFIO vectors.
4395          * So clear uio/vfio intr/evevnfd first to avoid failure.
4396          */
4397         rte_intr_disable(intr_handle);
4398
4399         rte_intr_enable(intr_handle);
4400
4401         /* Re-enable interrupt for VF */
4402         ixgbevf_intr_enable(hw);
4403
4404         return 0;
4405 }
4406
4407 static void
4408 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4409 {
4410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4412
4413         PMD_INIT_FUNC_TRACE();
4414
4415         ixgbevf_intr_disable(hw);
4416
4417         hw->adapter_stopped = 1;
4418         ixgbe_stop_adapter(hw);
4419
4420         /*
4421           * Clear what we set, but we still keep shadow_vfta to
4422           * restore after device starts
4423           */
4424         ixgbevf_set_vfta_all(dev, 0);
4425
4426         /* Clear stored conf */
4427         dev->data->scattered_rx = 0;
4428
4429         ixgbe_dev_clear_queues(dev);
4430
4431         /* Clean datapath event and queue/vec mapping */
4432         rte_intr_efd_disable(intr_handle);
4433         if (intr_handle->intr_vec != NULL) {
4434                 rte_free(intr_handle->intr_vec);
4435                 intr_handle->intr_vec = NULL;
4436         }
4437 }
4438
4439 static void
4440 ixgbevf_dev_close(struct rte_eth_dev *dev)
4441 {
4442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443
4444         PMD_INIT_FUNC_TRACE();
4445
4446         ixgbe_reset_hw(hw);
4447
4448         ixgbevf_dev_stop(dev);
4449
4450         ixgbe_dev_free_queues(dev);
4451
4452         /**
4453          * Remove the VF MAC address ro ensure
4454          * that the VF traffic goes to the PF
4455          * after stop, close and detach of the VF
4456          **/
4457         ixgbevf_remove_mac_addr(dev, 0);
4458 }
4459
4460 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4461 {
4462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4463         struct ixgbe_vfta *shadow_vfta =
4464                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4465         int i = 0, j = 0, vfta = 0, mask = 1;
4466
4467         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4468                 vfta = shadow_vfta->vfta[i];
4469                 if (vfta) {
4470                         mask = 1;
4471                         for (j = 0; j < 32; j++) {
4472                                 if (vfta & mask)
4473                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4474                                                        on, false);
4475                                 mask <<= 1;
4476                         }
4477                 }
4478         }
4479
4480 }
4481
4482 static int
4483 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4484 {
4485         struct ixgbe_hw *hw =
4486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         struct ixgbe_vfta *shadow_vfta =
4488                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4489         uint32_t vid_idx = 0;
4490         uint32_t vid_bit = 0;
4491         int ret = 0;
4492
4493         PMD_INIT_FUNC_TRACE();
4494
4495         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4496         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4497         if (ret) {
4498                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4499                 return ret;
4500         }
4501         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4502         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4503
4504         /* Save what we set and retore it after device reset */
4505         if (on)
4506                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4507         else
4508                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4509
4510         return 0;
4511 }
4512
4513 static void
4514 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4515 {
4516         struct ixgbe_hw *hw =
4517                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4518         uint32_t ctrl;
4519
4520         PMD_INIT_FUNC_TRACE();
4521
4522         if (queue >= hw->mac.max_rx_queues)
4523                 return;
4524
4525         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4526         if (on)
4527                 ctrl |= IXGBE_RXDCTL_VME;
4528         else
4529                 ctrl &= ~IXGBE_RXDCTL_VME;
4530         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4531
4532         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4533 }
4534
4535 static void
4536 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4537 {
4538         struct ixgbe_hw *hw =
4539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540         uint16_t i;
4541         int on = 0;
4542
4543         /* VF function only support hw strip feature, others are not support */
4544         if (mask & ETH_VLAN_STRIP_MASK) {
4545                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4546
4547                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4548                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4549         }
4550 }
4551
4552 static int
4553 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4554 {
4555         uint32_t reg_val;
4556
4557         /* we only need to do this if VMDq is enabled */
4558         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4559         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4560                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4561                 return -1;
4562         }
4563
4564         return 0;
4565 }
4566
4567 static uint32_t
4568 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4569 {
4570         uint32_t vector = 0;
4571
4572         switch (hw->mac.mc_filter_type) {
4573         case 0:   /* use bits [47:36] of the address */
4574                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4575                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4576                 break;
4577         case 1:   /* use bits [46:35] of the address */
4578                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4579                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4580                 break;
4581         case 2:   /* use bits [45:34] of the address */
4582                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4583                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4584                 break;
4585         case 3:   /* use bits [43:32] of the address */
4586                 vector = ((uc_addr->addr_bytes[4]) |
4587                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4588                 break;
4589         default:  /* Invalid mc_filter_type */
4590                 break;
4591         }
4592
4593         /* vector can only be 12-bits or boundary will be exceeded */
4594         vector &= 0xFFF;
4595         return vector;
4596 }
4597
4598 static int
4599 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4600                         uint8_t on)
4601 {
4602         uint32_t vector;
4603         uint32_t uta_idx;
4604         uint32_t reg_val;
4605         uint32_t uta_shift;
4606         uint32_t rc;
4607         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4608         const uint32_t ixgbe_uta_bit_shift = 5;
4609         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4610         const uint32_t bit1 = 0x1;
4611
4612         struct ixgbe_hw *hw =
4613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4614         struct ixgbe_uta_info *uta_info =
4615                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4616
4617         /* The UTA table only exists on 82599 hardware and newer */
4618         if (hw->mac.type < ixgbe_mac_82599EB)
4619                 return -ENOTSUP;
4620
4621         vector = ixgbe_uta_vector(hw, mac_addr);
4622         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4623         uta_shift = vector & ixgbe_uta_bit_mask;
4624
4625         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4626         if (rc == on)
4627                 return 0;
4628
4629         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4630         if (on) {
4631                 uta_info->uta_in_use++;
4632                 reg_val |= (bit1 << uta_shift);
4633                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4634         } else {
4635                 uta_info->uta_in_use--;
4636                 reg_val &= ~(bit1 << uta_shift);
4637                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4638         }
4639
4640         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4641
4642         if (uta_info->uta_in_use > 0)
4643                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4644                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4645         else
4646                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4647
4648         return 0;
4649 }
4650
4651 static int
4652 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4653 {
4654         int i;
4655         struct ixgbe_hw *hw =
4656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4657         struct ixgbe_uta_info *uta_info =
4658                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4659
4660         /* The UTA table only exists on 82599 hardware and newer */
4661         if (hw->mac.type < ixgbe_mac_82599EB)
4662                 return -ENOTSUP;
4663
4664         if (on) {
4665                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4666                         uta_info->uta_shadow[i] = ~0;
4667                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4668                 }
4669         } else {
4670                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4671                         uta_info->uta_shadow[i] = 0;
4672                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4673                 }
4674         }
4675         return 0;
4676
4677 }
4678
4679 uint32_t
4680 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4681 {
4682         uint32_t new_val = orig_val;
4683
4684         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4685                 new_val |= IXGBE_VMOLR_AUPE;
4686         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4687                 new_val |= IXGBE_VMOLR_ROMPE;
4688         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4689                 new_val |= IXGBE_VMOLR_ROPE;
4690         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4691                 new_val |= IXGBE_VMOLR_BAM;
4692         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4693                 new_val |= IXGBE_VMOLR_MPE;
4694
4695         return new_val;
4696 }
4697
4698 static int
4699 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4700                                uint16_t rx_mask, uint8_t on)
4701 {
4702         int val = 0;
4703
4704         struct ixgbe_hw *hw =
4705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4707
4708         if (hw->mac.type == ixgbe_mac_82598EB) {
4709                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4710                              " on 82599 hardware and newer");
4711                 return -ENOTSUP;
4712         }
4713         if (ixgbe_vmdq_mode_check(hw) < 0)
4714                 return -ENOTSUP;
4715
4716         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4717
4718         if (on)
4719                 vmolr |= val;
4720         else
4721                 vmolr &= ~val;
4722
4723         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4724
4725         return 0;
4726 }
4727
4728 static int
4729 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4730 {
4731         uint32_t reg, addr;
4732         uint32_t val;
4733         const uint8_t bit1 = 0x1;
4734
4735         struct ixgbe_hw *hw =
4736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737
4738         if (ixgbe_vmdq_mode_check(hw) < 0)
4739                 return -ENOTSUP;
4740
4741         if (pool >= ETH_64_POOLS)
4742                 return -EINVAL;
4743
4744         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4745         if (pool >= 32) {
4746                 addr = IXGBE_VFRE(1);
4747                 val = bit1 << (pool - 32);
4748         } else {
4749                 addr = IXGBE_VFRE(0);
4750                 val = bit1 << pool;
4751         }
4752
4753         reg = IXGBE_READ_REG(hw, addr);
4754
4755         if (on)
4756                 reg |= val;
4757         else
4758                 reg &= ~val;
4759
4760         IXGBE_WRITE_REG(hw, addr, reg);
4761
4762         return 0;
4763 }
4764
4765 static int
4766 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4767 {
4768         uint32_t reg, addr;
4769         uint32_t val;
4770         const uint8_t bit1 = 0x1;
4771
4772         struct ixgbe_hw *hw =
4773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774
4775         if (ixgbe_vmdq_mode_check(hw) < 0)
4776                 return -ENOTSUP;
4777
4778         if (pool >= ETH_64_POOLS)
4779                 return -EINVAL;
4780
4781         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4782         if (pool >= 32) {
4783                 addr = IXGBE_VFTE(1);
4784                 val = bit1 << (pool - 32);
4785         } else {
4786                 addr = IXGBE_VFTE(0);
4787                 val = bit1 << pool;
4788         }
4789
4790         reg = IXGBE_READ_REG(hw, addr);
4791
4792         if (on)
4793                 reg |= val;
4794         else
4795                 reg &= ~val;
4796
4797         IXGBE_WRITE_REG(hw, addr, reg);
4798
4799         return 0;
4800 }
4801
4802 static int
4803 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4804                         uint64_t pool_mask, uint8_t vlan_on)
4805 {
4806         int ret = 0;
4807         uint16_t pool_idx;
4808         struct ixgbe_hw *hw =
4809                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810
4811         if (ixgbe_vmdq_mode_check(hw) < 0)
4812                 return -ENOTSUP;
4813         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4814                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4815                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4816                                                    vlan_on, false);
4817                         if (ret < 0)
4818                                 return ret;
4819                 }
4820         }
4821
4822         return ret;
4823 }
4824
4825 int
4826 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4827 {
4828         struct ixgbe_hw *hw;
4829         struct ixgbe_mac_info *mac;
4830         struct rte_eth_dev *dev;
4831         struct rte_eth_dev_info dev_info;
4832
4833         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4834
4835         dev = &rte_eth_devices[port];
4836         rte_eth_dev_info_get(port, &dev_info);
4837
4838         if (vf >= dev_info.max_vfs)
4839                 return -EINVAL;
4840
4841         if (on > 1)
4842                 return -EINVAL;
4843
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         mac = &hw->mac;
4846
4847         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4848
4849         return 0;
4850 }
4851
4852 int
4853 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4854 {
4855         struct ixgbe_hw *hw;
4856         struct ixgbe_mac_info *mac;
4857         struct rte_eth_dev *dev;
4858         struct rte_eth_dev_info dev_info;
4859
4860         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4861
4862         dev = &rte_eth_devices[port];
4863         rte_eth_dev_info_get(port, &dev_info);
4864
4865         if (vf >= dev_info.max_vfs)
4866                 return -EINVAL;
4867
4868         if (on > 1)
4869                 return -EINVAL;
4870
4871         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4872         mac = &hw->mac;
4873         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4874
4875         return 0;
4876 }
4877
4878 int
4879 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4880 {
4881         struct ixgbe_hw *hw;
4882         uint32_t ctrl;
4883         struct rte_eth_dev *dev;
4884         struct rte_eth_dev_info dev_info;
4885
4886         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4887
4888         dev = &rte_eth_devices[port];
4889         rte_eth_dev_info_get(port, &dev_info);
4890
4891         if (vf >= dev_info.max_vfs)
4892                 return -EINVAL;
4893
4894         if (vlan_id > 4095)
4895                 return -EINVAL;
4896
4897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4899         if (vlan_id) {
4900                 ctrl = vlan_id;
4901                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4902         } else {
4903                 ctrl = 0;
4904         }
4905
4906         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4907
4908         return 0;
4909 }
4910
4911 int
4912 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4913 {
4914         struct ixgbe_hw *hw;
4915         uint32_t ctrl;
4916         struct rte_eth_dev *dev;
4917
4918         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4919
4920         dev = &rte_eth_devices[port];
4921
4922         if (on > 1)
4923                 return -EINVAL;
4924
4925         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4927         /* enable or disable VMDQ loopback */
4928         if (on)
4929                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4930         else
4931                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4932
4933         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4934
4935         return 0;
4936 }
4937
4938 int
4939 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4940 {
4941         struct ixgbe_hw *hw;
4942         uint32_t reg_value;
4943         int i;
4944         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4945         struct rte_eth_dev *dev;
4946
4947         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4948
4949         dev = &rte_eth_devices[port];
4950
4951         if (on > 1)
4952                 return -EINVAL;
4953
4954         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         for (i = 0; i <= num_queues; i++) {
4956                 reg_value = IXGBE_QDE_WRITE |
4957                                 (i << IXGBE_QDE_IDX_SHIFT) |
4958                                 (on & IXGBE_QDE_ENABLE);
4959                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4960         }
4961
4962         return 0;
4963 }
4964
4965 int
4966 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4967 {
4968         struct ixgbe_hw *hw;
4969         uint32_t reg_value;
4970         struct rte_eth_dev *dev;
4971         struct rte_eth_dev_info dev_info;
4972
4973         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4974
4975         dev = &rte_eth_devices[port];
4976         rte_eth_dev_info_get(port, &dev_info);
4977
4978         /* only support VF's 0 to 63 */
4979         if ((vf >= dev_info.max_vfs) || (vf > 63))
4980                 return -EINVAL;
4981
4982         if (on > 1)
4983                 return -EINVAL;
4984
4985         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4987         if (on)
4988                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4989         else
4990                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4991
4992         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4993
4994         return 0;
4995 }
4996
4997 int
4998 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4999 {
5000         struct rte_eth_dev *dev;
5001         struct rte_eth_dev_info dev_info;
5002         uint16_t queues_per_pool;
5003         uint32_t q;
5004
5005         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5006
5007         dev = &rte_eth_devices[port];
5008         rte_eth_dev_info_get(port, &dev_info);
5009
5010         if (vf >= dev_info.max_vfs)
5011                 return -EINVAL;
5012
5013         if (on > 1)
5014                 return -EINVAL;
5015
5016         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5017
5018         /* The PF has 128 queue pairs and in SRIOV configuration
5019          * those queues will be assigned to VF's, so RXDCTL
5020          * registers will be dealing with queues which will be
5021          * assigned to VF's.
5022          * Let's say we have SRIOV configured with 31 VF's then the
5023          * first 124 queues 0-123 will be allocated to VF's and only
5024          * the last 4 queues 123-127 will be assigned to the PF.
5025          */
5026
5027         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5028
5029         for (q = 0; q < queues_per_pool; q++)
5030                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5031                                 q + vf * queues_per_pool, on);
5032         return 0;
5033 }
5034
5035 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5036 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5037 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5038 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5039 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5040         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5041         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5042
5043 static int
5044 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5045                         struct rte_eth_mirror_conf *mirror_conf,
5046                         uint8_t rule_id, uint8_t on)
5047 {
5048         uint32_t mr_ctl, vlvf;
5049         uint32_t mp_lsb = 0;
5050         uint32_t mv_msb = 0;
5051         uint32_t mv_lsb = 0;
5052         uint32_t mp_msb = 0;
5053         uint8_t i = 0;
5054         int reg_index = 0;
5055         uint64_t vlan_mask = 0;
5056
5057         const uint8_t pool_mask_offset = 32;
5058         const uint8_t vlan_mask_offset = 32;
5059         const uint8_t dst_pool_offset = 8;
5060         const uint8_t rule_mr_offset  = 4;
5061         const uint8_t mirror_rule_mask = 0x0F;
5062
5063         struct ixgbe_mirror_info *mr_info =
5064                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5065         struct ixgbe_hw *hw =
5066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067         uint8_t mirror_type = 0;
5068
5069         if (ixgbe_vmdq_mode_check(hw) < 0)
5070                 return -ENOTSUP;
5071
5072         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5073                 return -EINVAL;
5074
5075         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5076                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5077                         mirror_conf->rule_type);
5078                 return -EINVAL;
5079         }
5080
5081         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5082                 mirror_type |= IXGBE_MRCTL_VLME;
5083                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5084                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5085                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5086                                 /* search vlan id related pool vlan filter index */
5087                                 reg_index = ixgbe_find_vlvf_slot(hw,
5088                                                  mirror_conf->vlan.vlan_id[i],
5089                                                  false);
5090                                 if (reg_index < 0)
5091                                         return -EINVAL;
5092                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5093                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5094                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5095                                       mirror_conf->vlan.vlan_id[i]))
5096                                         vlan_mask |= (1ULL << reg_index);
5097                                 else
5098                                         return -EINVAL;
5099                         }
5100                 }
5101
5102                 if (on) {
5103                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5104                         mv_msb = vlan_mask >> vlan_mask_offset;
5105
5106                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5107                                                 mirror_conf->vlan.vlan_mask;
5108                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5109                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5110                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5111                                                 mirror_conf->vlan.vlan_id[i];
5112                         }
5113                 } else {
5114                         mv_lsb = 0;
5115                         mv_msb = 0;
5116                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5117                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5118                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5119                 }
5120         }
5121
5122         /*
5123          * if enable pool mirror, write related pool mask register,if disable
5124          * pool mirror, clear PFMRVM register
5125          */
5126         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5127                 mirror_type |= IXGBE_MRCTL_VPME;
5128                 if (on) {
5129                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5130                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5131                         mr_info->mr_conf[rule_id].pool_mask =
5132                                         mirror_conf->pool_mask;
5133
5134                 } else {
5135                         mp_lsb = 0;
5136                         mp_msb = 0;
5137                         mr_info->mr_conf[rule_id].pool_mask = 0;
5138                 }
5139         }
5140         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5141                 mirror_type |= IXGBE_MRCTL_UPME;
5142         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5143                 mirror_type |= IXGBE_MRCTL_DPME;
5144
5145         /* read  mirror control register and recalculate it */
5146         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5147
5148         if (on) {
5149                 mr_ctl |= mirror_type;
5150                 mr_ctl &= mirror_rule_mask;
5151                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5152         } else
5153                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5154
5155         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5156         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5157
5158         /* write mirrror control  register */
5159         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5160
5161         /* write pool mirrror control  register */
5162         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5163                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5164                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5165                                 mp_msb);
5166         }
5167         /* write VLAN mirrror control  register */
5168         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5169                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5170                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5171                                 mv_msb);
5172         }
5173
5174         return 0;
5175 }
5176
5177 static int
5178 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5179 {
5180         int mr_ctl = 0;
5181         uint32_t lsb_val = 0;
5182         uint32_t msb_val = 0;
5183         const uint8_t rule_mr_offset = 4;
5184
5185         struct ixgbe_hw *hw =
5186                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5187         struct ixgbe_mirror_info *mr_info =
5188                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5189
5190         if (ixgbe_vmdq_mode_check(hw) < 0)
5191                 return -ENOTSUP;
5192
5193         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5194                 return -EINVAL;
5195
5196         memset(&mr_info->mr_conf[rule_id], 0,
5197                 sizeof(struct rte_eth_mirror_conf));
5198
5199         /* clear PFVMCTL register */
5200         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5201
5202         /* clear pool mask register */
5203         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5204         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5205
5206         /* clear vlan mask register */
5207         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5208         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5209
5210         return 0;
5211 }
5212
5213 static int
5214 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5215 {
5216         uint32_t mask;
5217         struct ixgbe_hw *hw =
5218                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219
5220         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5221         mask |= (1 << IXGBE_MISC_VEC_ID);
5222         RTE_SET_USED(queue_id);
5223         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5224
5225         rte_intr_enable(&dev->pci_dev->intr_handle);
5226
5227         return 0;
5228 }
5229
5230 static int
5231 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5232 {
5233         uint32_t mask;
5234         struct ixgbe_hw *hw =
5235                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236
5237         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5238         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5239         RTE_SET_USED(queue_id);
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5241
5242         return 0;
5243 }
5244
5245 static int
5246 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5247 {
5248         uint32_t mask;
5249         struct ixgbe_hw *hw =
5250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct ixgbe_interrupt *intr =
5252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5253
5254         if (queue_id < 16) {
5255                 ixgbe_disable_intr(hw);
5256                 intr->mask |= (1 << queue_id);
5257                 ixgbe_enable_intr(dev);
5258         } else if (queue_id < 32) {
5259                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5260                 mask &= (1 << queue_id);
5261                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5262         } else if (queue_id < 64) {
5263                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5264                 mask &= (1 << (queue_id - 32));
5265                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5266         }
5267         rte_intr_enable(&dev->pci_dev->intr_handle);
5268
5269         return 0;
5270 }
5271
5272 static int
5273 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5274 {
5275         uint32_t mask;
5276         struct ixgbe_hw *hw =
5277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278         struct ixgbe_interrupt *intr =
5279                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5280
5281         if (queue_id < 16) {
5282                 ixgbe_disable_intr(hw);
5283                 intr->mask &= ~(1 << queue_id);
5284                 ixgbe_enable_intr(dev);
5285         } else if (queue_id < 32) {
5286                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5287                 mask &= ~(1 << queue_id);
5288                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5289         } else if (queue_id < 64) {
5290                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5291                 mask &= ~(1 << (queue_id - 32));
5292                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5293         }
5294
5295         return 0;
5296 }
5297
5298 static void
5299 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5300                      uint8_t queue, uint8_t msix_vector)
5301 {
5302         uint32_t tmp, idx;
5303
5304         if (direction == -1) {
5305                 /* other causes */
5306                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5307                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5308                 tmp &= ~0xFF;
5309                 tmp |= msix_vector;
5310                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5311         } else {
5312                 /* rx or tx cause */
5313                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5314                 idx = ((16 * (queue & 1)) + (8 * direction));
5315                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5316                 tmp &= ~(0xFF << idx);
5317                 tmp |= (msix_vector << idx);
5318                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5319         }
5320 }
5321
5322 /**
5323  * set the IVAR registers, mapping interrupt causes to vectors
5324  * @param hw
5325  *  pointer to ixgbe_hw struct
5326  * @direction
5327  *  0 for Rx, 1 for Tx, -1 for other causes
5328  * @queue
5329  *  queue to map the corresponding interrupt to
5330  * @msix_vector
5331  *  the vector to map to the corresponding queue
5332  */
5333 static void
5334 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5335                    uint8_t queue, uint8_t msix_vector)
5336 {
5337         uint32_t tmp, idx;
5338
5339         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5340         if (hw->mac.type == ixgbe_mac_82598EB) {
5341                 if (direction == -1)
5342                         direction = 0;
5343                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5344                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5345                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5346                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5347                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5348         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5349                         (hw->mac.type == ixgbe_mac_X540) ||
5350                         (hw->mac.type == ixgbe_mac_X550)) {
5351                 if (direction == -1) {
5352                         /* other causes */
5353                         idx = ((queue & 1) * 8);
5354                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5355                         tmp &= ~(0xFF << idx);
5356                         tmp |= (msix_vector << idx);
5357                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5358                 } else {
5359                         /* rx or tx causes */
5360                         idx = ((16 * (queue & 1)) + (8 * direction));
5361                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5362                         tmp &= ~(0xFF << idx);
5363                         tmp |= (msix_vector << idx);
5364                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5365                 }
5366         }
5367 }
5368
5369 static void
5370 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5371 {
5372         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5373         struct ixgbe_hw *hw =
5374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5375         uint32_t q_idx;
5376         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5377
5378         /* Configure VF other cause ivar */
5379         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5380
5381         /* won't configure msix register if no mapping is done
5382          * between intr vector and event fd.
5383          */
5384         if (!rte_intr_dp_is_en(intr_handle))
5385                 return;
5386
5387         /* Configure all RX queues of VF */
5388         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5389                 /* Force all queue use vector 0,
5390                  * as IXGBE_VF_MAXMSIVECOTR = 1
5391                  */
5392                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5393                 intr_handle->intr_vec[q_idx] = vector_idx;
5394         }
5395 }
5396
5397 /**
5398  * Sets up the hardware to properly generate MSI-X interrupts
5399  * @hw
5400  *  board private structure
5401  */
5402 static void
5403 ixgbe_configure_msix(struct rte_eth_dev *dev)
5404 {
5405         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5406         struct ixgbe_hw *hw =
5407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5409         uint32_t vec = IXGBE_MISC_VEC_ID;
5410         uint32_t mask;
5411         uint32_t gpie;
5412
5413         /* won't configure msix register if no mapping is done
5414          * between intr vector and event fd
5415          * but if misx has been enabled already, need to configure
5416          * auto clean, auto mask and throttling.
5417          */
5418         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5419         if (!rte_intr_dp_is_en(intr_handle) &&
5420             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5421                 return;
5422
5423         if (rte_intr_allow_others(intr_handle))
5424                 vec = base = IXGBE_RX_VEC_START;
5425
5426         /* setup GPIE for MSI-x mode */
5427         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5428         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5429                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5430         /* auto clearing and auto setting corresponding bits in EIMS
5431          * when MSI-X interrupt is triggered
5432          */
5433         if (hw->mac.type == ixgbe_mac_82598EB) {
5434                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5435         } else {
5436                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5437                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5438         }
5439         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5440
5441         /* Populate the IVAR table and set the ITR values to the
5442          * corresponding register.
5443          */
5444         if (rte_intr_dp_is_en(intr_handle)) {
5445                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5446                         queue_id++) {
5447                         /* by default, 1:1 mapping */
5448                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5449                         intr_handle->intr_vec[queue_id] = vec;
5450                         if (vec < base + intr_handle->nb_efd - 1)
5451                                 vec++;
5452                 }
5453
5454                 switch (hw->mac.type) {
5455                 case ixgbe_mac_82598EB:
5456                         ixgbe_set_ivar_map(hw, -1,
5457                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5458                                            IXGBE_MISC_VEC_ID);
5459                         break;
5460                 case ixgbe_mac_82599EB:
5461                 case ixgbe_mac_X540:
5462                 case ixgbe_mac_X550:
5463                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5464                         break;
5465                 default:
5466                         break;
5467                 }
5468         }
5469         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5470                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5471
5472         /* set up to autoclear timer, and the vectors */
5473         mask = IXGBE_EIMS_ENABLE_MASK;
5474         mask &= ~(IXGBE_EIMS_OTHER |
5475                   IXGBE_EIMS_MAILBOX |
5476                   IXGBE_EIMS_LSC);
5477
5478         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5479 }
5480
5481 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5482         uint16_t queue_idx, uint16_t tx_rate)
5483 {
5484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5485         uint32_t rf_dec, rf_int;
5486         uint32_t bcnrc_val;
5487         uint16_t link_speed = dev->data->dev_link.link_speed;
5488
5489         if (queue_idx >= hw->mac.max_tx_queues)
5490                 return -EINVAL;
5491
5492         if (tx_rate != 0) {
5493                 /* Calculate the rate factor values to set */
5494                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5495                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5496                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5497
5498                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5499                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5500                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5501                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5502         } else {
5503                 bcnrc_val = 0;
5504         }
5505
5506         /*
5507          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5508          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5509          * set as 0x4.
5510          */
5511         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5512                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5513                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5514                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5515                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5516         else
5517                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5518                         IXGBE_MMW_SIZE_DEFAULT);
5519
5520         /* Set RTTBCNRC of queue X */
5521         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5522         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5523         IXGBE_WRITE_FLUSH(hw);
5524
5525         return 0;
5526 }
5527
5528 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5529         uint16_t tx_rate, uint64_t q_msk)
5530 {
5531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532         struct ixgbe_vf_info *vfinfo =
5533                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5534         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5535         uint32_t queue_stride =
5536                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5537         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5538         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5539         uint16_t total_rate = 0;
5540
5541         if (queue_end >= hw->mac.max_tx_queues)
5542                 return -EINVAL;
5543
5544         if (vfinfo != NULL) {
5545                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5546                         if (vf_idx == vf)
5547                                 continue;
5548                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5549                                 idx++)
5550                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5551                 }
5552         } else
5553                 return -EINVAL;
5554
5555         /* Store tx_rate for this vf. */
5556         for (idx = 0; idx < nb_q_per_pool; idx++) {
5557                 if (((uint64_t)0x1 << idx) & q_msk) {
5558                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5559                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5560                         total_rate += tx_rate;
5561                 }
5562         }
5563
5564         if (total_rate > dev->data->dev_link.link_speed) {
5565                 /*
5566                  * Reset stored TX rate of the VF if it causes exceed
5567                  * link speed.
5568                  */
5569                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5570                 return -EINVAL;
5571         }
5572
5573         /* Set RTTBCNRC of each queue/pool for vf X  */
5574         for (; queue_idx <= queue_end; queue_idx++) {
5575                 if (0x1 & q_msk)
5576                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5577                 q_msk = q_msk >> 1;
5578         }
5579
5580         return 0;
5581 }
5582
5583 static void
5584 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5585                      __attribute__((unused)) uint32_t index,
5586                      __attribute__((unused)) uint32_t pool)
5587 {
5588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5589         int diag;
5590
5591         /*
5592          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5593          * operation. Trap this case to avoid exhausting the [very limited]
5594          * set of PF resources used to store VF MAC addresses.
5595          */
5596         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5597                 return;
5598         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5599         if (diag == 0)
5600                 return;
5601         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5602 }
5603
5604 static void
5605 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5606 {
5607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5608         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5609         struct ether_addr *mac_addr;
5610         uint32_t i;
5611         int diag;
5612
5613         /*
5614          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5615          * not support the deletion of a given MAC address.
5616          * Instead, it imposes to delete all MAC addresses, then to add again
5617          * all MAC addresses with the exception of the one to be deleted.
5618          */
5619         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5620
5621         /*
5622          * Add again all MAC addresses, with the exception of the deleted one
5623          * and of the permanent MAC address.
5624          */
5625         for (i = 0, mac_addr = dev->data->mac_addrs;
5626              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5627                 /* Skip the deleted MAC address */
5628                 if (i == index)
5629                         continue;
5630                 /* Skip NULL MAC addresses */
5631                 if (is_zero_ether_addr(mac_addr))
5632                         continue;
5633                 /* Skip the permanent MAC address */
5634                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5635                         continue;
5636                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5637                 if (diag != 0)
5638                         PMD_DRV_LOG(ERR,
5639                                     "Adding again MAC address "
5640                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5641                                     "diag=%d",
5642                                     mac_addr->addr_bytes[0],
5643                                     mac_addr->addr_bytes[1],
5644                                     mac_addr->addr_bytes[2],
5645                                     mac_addr->addr_bytes[3],
5646                                     mac_addr->addr_bytes[4],
5647                                     mac_addr->addr_bytes[5],
5648                                     diag);
5649         }
5650 }
5651
5652 static void
5653 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5654 {
5655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5656
5657         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5658 }
5659
5660 #define MAC_TYPE_FILTER_SUP(type)    do {\
5661         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5662                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5663                 (type) != ixgbe_mac_X550EM_a)\
5664                 return -ENOTSUP;\
5665 } while (0)
5666
5667 static int
5668 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5669                         struct rte_eth_syn_filter *filter,
5670                         bool add)
5671 {
5672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5673         uint32_t synqf;
5674
5675         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5676                 return -EINVAL;
5677
5678         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5679
5680         if (add) {
5681                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5682                         return -EINVAL;
5683                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5684                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5685
5686                 if (filter->hig_pri)
5687                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5688                 else
5689                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5690         } else {
5691                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5692                         return -ENOENT;
5693                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5694         }
5695         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5696         IXGBE_WRITE_FLUSH(hw);
5697         return 0;
5698 }
5699
5700 static int
5701 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5702                         struct rte_eth_syn_filter *filter)
5703 {
5704         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5706
5707         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5708                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5709                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5710                 return 0;
5711         }
5712         return -ENOENT;
5713 }
5714
5715 static int
5716 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5717                         enum rte_filter_op filter_op,
5718                         void *arg)
5719 {
5720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721         int ret;
5722
5723         MAC_TYPE_FILTER_SUP(hw->mac.type);
5724
5725         if (filter_op == RTE_ETH_FILTER_NOP)
5726                 return 0;
5727
5728         if (arg == NULL) {
5729                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5730                             filter_op);
5731                 return -EINVAL;
5732         }
5733
5734         switch (filter_op) {
5735         case RTE_ETH_FILTER_ADD:
5736                 ret = ixgbe_syn_filter_set(dev,
5737                                 (struct rte_eth_syn_filter *)arg,
5738                                 TRUE);
5739                 break;
5740         case RTE_ETH_FILTER_DELETE:
5741                 ret = ixgbe_syn_filter_set(dev,
5742                                 (struct rte_eth_syn_filter *)arg,
5743                                 FALSE);
5744                 break;
5745         case RTE_ETH_FILTER_GET:
5746                 ret = ixgbe_syn_filter_get(dev,
5747                                 (struct rte_eth_syn_filter *)arg);
5748                 break;
5749         default:
5750                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5751                 ret = -EINVAL;
5752                 break;
5753         }
5754
5755         return ret;
5756 }
5757
5758
5759 static inline enum ixgbe_5tuple_protocol
5760 convert_protocol_type(uint8_t protocol_value)
5761 {
5762         if (protocol_value == IPPROTO_TCP)
5763                 return IXGBE_FILTER_PROTOCOL_TCP;
5764         else if (protocol_value == IPPROTO_UDP)
5765                 return IXGBE_FILTER_PROTOCOL_UDP;
5766         else if (protocol_value == IPPROTO_SCTP)
5767                 return IXGBE_FILTER_PROTOCOL_SCTP;
5768         else
5769                 return IXGBE_FILTER_PROTOCOL_NONE;
5770 }
5771
5772 /*
5773  * add a 5tuple filter
5774  *
5775  * @param
5776  * dev: Pointer to struct rte_eth_dev.
5777  * index: the index the filter allocates.
5778  * filter: ponter to the filter that will be added.
5779  * rx_queue: the queue id the filter assigned to.
5780  *
5781  * @return
5782  *    - On success, zero.
5783  *    - On failure, a negative value.
5784  */
5785 static int
5786 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5787                         struct ixgbe_5tuple_filter *filter)
5788 {
5789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5790         struct ixgbe_filter_info *filter_info =
5791                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5792         int i, idx, shift;
5793         uint32_t ftqf, sdpqf;
5794         uint32_t l34timir = 0;
5795         uint8_t mask = 0xff;
5796
5797         /*
5798          * look for an unused 5tuple filter index,
5799          * and insert the filter to list.
5800          */
5801         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5802                 idx = i / (sizeof(uint32_t) * NBBY);
5803                 shift = i % (sizeof(uint32_t) * NBBY);
5804                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5805                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5806                         filter->index = i;
5807                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5808                                           filter,
5809                                           entries);
5810                         break;
5811                 }
5812         }
5813         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5814                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5815                 return -ENOSYS;
5816         }
5817
5818         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5819                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5820         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5821
5822         ftqf = (uint32_t)(filter->filter_info.proto &
5823                 IXGBE_FTQF_PROTOCOL_MASK);
5824         ftqf |= (uint32_t)((filter->filter_info.priority &
5825                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5826         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5827                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5828         if (filter->filter_info.dst_ip_mask == 0)
5829                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5830         if (filter->filter_info.src_port_mask == 0)
5831                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5832         if (filter->filter_info.dst_port_mask == 0)
5833                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5834         if (filter->filter_info.proto_mask == 0)
5835                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5836         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5837         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5838         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5839
5840         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5841         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5842         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5843         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5844
5845         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5846         l34timir |= (uint32_t)(filter->queue <<
5847                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5848         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5849         return 0;
5850 }
5851
5852 /*
5853  * remove a 5tuple filter
5854  *
5855  * @param
5856  * dev: Pointer to struct rte_eth_dev.
5857  * filter: the pointer of the filter will be removed.
5858  */
5859 static void
5860 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5861                         struct ixgbe_5tuple_filter *filter)
5862 {
5863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864         struct ixgbe_filter_info *filter_info =
5865                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5866         uint16_t index = filter->index;
5867
5868         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5869                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5870         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5871         rte_free(filter);
5872
5873         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5874         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5875         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5876         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5877         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5878 }
5879
5880 static int
5881 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5882 {
5883         struct ixgbe_hw *hw;
5884         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5885         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5886
5887         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5888
5889         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5890                 return -EINVAL;
5891
5892         /* refuse mtu that requires the support of scattered packets when this
5893          * feature has not been enabled before.
5894          */
5895         if (!rx_conf->enable_scatter &&
5896             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5897              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5898                 return -EINVAL;
5899
5900         /*
5901          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5902          * request of the version 2.0 of the mailbox API.
5903          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5904          * of the mailbox API.
5905          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5906          * prior to 3.11.33 which contains the following change:
5907          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5908          */
5909         ixgbevf_rlpml_set_vf(hw, max_frame);
5910
5911         /* update max frame size */
5912         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5913         return 0;
5914 }
5915
5916 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5917         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5918                 return -ENOTSUP;\
5919 } while (0)
5920
5921 static inline struct ixgbe_5tuple_filter *
5922 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5923                         struct ixgbe_5tuple_filter_info *key)
5924 {
5925         struct ixgbe_5tuple_filter *it;
5926
5927         TAILQ_FOREACH(it, filter_list, entries) {
5928                 if (memcmp(key, &it->filter_info,
5929                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5930                         return it;
5931                 }
5932         }
5933         return NULL;
5934 }
5935
5936 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5937 static inline int
5938 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5939                         struct ixgbe_5tuple_filter_info *filter_info)
5940 {
5941         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5942                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5943                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5944                 return -EINVAL;
5945
5946         switch (filter->dst_ip_mask) {
5947         case UINT32_MAX:
5948                 filter_info->dst_ip_mask = 0;
5949                 filter_info->dst_ip = filter->dst_ip;
5950                 break;
5951         case 0:
5952                 filter_info->dst_ip_mask = 1;
5953                 break;
5954         default:
5955                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5956                 return -EINVAL;
5957         }
5958
5959         switch (filter->src_ip_mask) {
5960         case UINT32_MAX:
5961                 filter_info->src_ip_mask = 0;
5962                 filter_info->src_ip = filter->src_ip;
5963                 break;
5964         case 0:
5965                 filter_info->src_ip_mask = 1;
5966                 break;
5967         default:
5968                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5969                 return -EINVAL;
5970         }
5971
5972         switch (filter->dst_port_mask) {
5973         case UINT16_MAX:
5974                 filter_info->dst_port_mask = 0;
5975                 filter_info->dst_port = filter->dst_port;
5976                 break;
5977         case 0:
5978                 filter_info->dst_port_mask = 1;
5979                 break;
5980         default:
5981                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5982                 return -EINVAL;
5983         }
5984
5985         switch (filter->src_port_mask) {
5986         case UINT16_MAX:
5987                 filter_info->src_port_mask = 0;
5988                 filter_info->src_port = filter->src_port;
5989                 break;
5990         case 0:
5991                 filter_info->src_port_mask = 1;
5992                 break;
5993         default:
5994                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5995                 return -EINVAL;
5996         }
5997
5998         switch (filter->proto_mask) {
5999         case UINT8_MAX:
6000                 filter_info->proto_mask = 0;
6001                 filter_info->proto =
6002                         convert_protocol_type(filter->proto);
6003                 break;
6004         case 0:
6005                 filter_info->proto_mask = 1;
6006                 break;
6007         default:
6008                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6009                 return -EINVAL;
6010         }
6011
6012         filter_info->priority = (uint8_t)filter->priority;
6013         return 0;
6014 }
6015
6016 /*
6017  * add or delete a ntuple filter
6018  *
6019  * @param
6020  * dev: Pointer to struct rte_eth_dev.
6021  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6022  * add: if true, add filter, if false, remove filter
6023  *
6024  * @return
6025  *    - On success, zero.
6026  *    - On failure, a negative value.
6027  */
6028 static int
6029 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6030                         struct rte_eth_ntuple_filter *ntuple_filter,
6031                         bool add)
6032 {
6033         struct ixgbe_filter_info *filter_info =
6034                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6035         struct ixgbe_5tuple_filter_info filter_5tuple;
6036         struct ixgbe_5tuple_filter *filter;
6037         int ret;
6038
6039         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6040                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6041                 return -EINVAL;
6042         }
6043
6044         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6045         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6046         if (ret < 0)
6047                 return ret;
6048
6049         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6050                                          &filter_5tuple);
6051         if (filter != NULL && add) {
6052                 PMD_DRV_LOG(ERR, "filter exists.");
6053                 return -EEXIST;
6054         }
6055         if (filter == NULL && !add) {
6056                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6057                 return -ENOENT;
6058         }
6059
6060         if (add) {
6061                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6062                                 sizeof(struct ixgbe_5tuple_filter), 0);
6063                 if (filter == NULL)
6064                         return -ENOMEM;
6065                 (void)rte_memcpy(&filter->filter_info,
6066                                  &filter_5tuple,
6067                                  sizeof(struct ixgbe_5tuple_filter_info));
6068                 filter->queue = ntuple_filter->queue;
6069                 ret = ixgbe_add_5tuple_filter(dev, filter);
6070                 if (ret < 0) {
6071                         rte_free(filter);
6072                         return ret;
6073                 }
6074         } else
6075                 ixgbe_remove_5tuple_filter(dev, filter);
6076
6077         return 0;
6078 }
6079
6080 /*
6081  * get a ntuple filter
6082  *
6083  * @param
6084  * dev: Pointer to struct rte_eth_dev.
6085  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6086  *
6087  * @return
6088  *    - On success, zero.
6089  *    - On failure, a negative value.
6090  */
6091 static int
6092 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6093                         struct rte_eth_ntuple_filter *ntuple_filter)
6094 {
6095         struct ixgbe_filter_info *filter_info =
6096                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6097         struct ixgbe_5tuple_filter_info filter_5tuple;
6098         struct ixgbe_5tuple_filter *filter;
6099         int ret;
6100
6101         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6102                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6103                 return -EINVAL;
6104         }
6105
6106         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6107         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6108         if (ret < 0)
6109                 return ret;
6110
6111         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6112                                          &filter_5tuple);
6113         if (filter == NULL) {
6114                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6115                 return -ENOENT;
6116         }
6117         ntuple_filter->queue = filter->queue;
6118         return 0;
6119 }
6120
6121 /*
6122  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6123  * @dev: pointer to rte_eth_dev structure
6124  * @filter_op:operation will be taken.
6125  * @arg: a pointer to specific structure corresponding to the filter_op
6126  *
6127  * @return
6128  *    - On success, zero.
6129  *    - On failure, a negative value.
6130  */
6131 static int
6132 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6133                                 enum rte_filter_op filter_op,
6134                                 void *arg)
6135 {
6136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6137         int ret;
6138
6139         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6140
6141         if (filter_op == RTE_ETH_FILTER_NOP)
6142                 return 0;
6143
6144         if (arg == NULL) {
6145                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6146                             filter_op);
6147                 return -EINVAL;
6148         }
6149
6150         switch (filter_op) {
6151         case RTE_ETH_FILTER_ADD:
6152                 ret = ixgbe_add_del_ntuple_filter(dev,
6153                         (struct rte_eth_ntuple_filter *)arg,
6154                         TRUE);
6155                 break;
6156         case RTE_ETH_FILTER_DELETE:
6157                 ret = ixgbe_add_del_ntuple_filter(dev,
6158                         (struct rte_eth_ntuple_filter *)arg,
6159                         FALSE);
6160                 break;
6161         case RTE_ETH_FILTER_GET:
6162                 ret = ixgbe_get_ntuple_filter(dev,
6163                         (struct rte_eth_ntuple_filter *)arg);
6164                 break;
6165         default:
6166                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6167                 ret = -EINVAL;
6168                 break;
6169         }
6170         return ret;
6171 }
6172
6173 static inline int
6174 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6175                         uint16_t ethertype)
6176 {
6177         int i;
6178
6179         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6180                 if (filter_info->ethertype_filters[i] == ethertype &&
6181                     (filter_info->ethertype_mask & (1 << i)))
6182                         return i;
6183         }
6184         return -1;
6185 }
6186
6187 static inline int
6188 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6189                         uint16_t ethertype)
6190 {
6191         int i;
6192
6193         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6194                 if (!(filter_info->ethertype_mask & (1 << i))) {
6195                         filter_info->ethertype_mask |= 1 << i;
6196                         filter_info->ethertype_filters[i] = ethertype;
6197                         return i;
6198                 }
6199         }
6200         return -1;
6201 }
6202
6203 static inline int
6204 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6205                         uint8_t idx)
6206 {
6207         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6208                 return -1;
6209         filter_info->ethertype_mask &= ~(1 << idx);
6210         filter_info->ethertype_filters[idx] = 0;
6211         return idx;
6212 }
6213
6214 static int
6215 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6216                         struct rte_eth_ethertype_filter *filter,
6217                         bool add)
6218 {
6219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6220         struct ixgbe_filter_info *filter_info =
6221                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6222         uint32_t etqf = 0;
6223         uint32_t etqs = 0;
6224         int ret;
6225
6226         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6227                 return -EINVAL;
6228
6229         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6230                 filter->ether_type == ETHER_TYPE_IPv6) {
6231                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6232                         " ethertype filter.", filter->ether_type);
6233                 return -EINVAL;
6234         }
6235
6236         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6237                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6238                 return -EINVAL;
6239         }
6240         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6241                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6242                 return -EINVAL;
6243         }
6244
6245         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6246         if (ret >= 0 && add) {
6247                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6248                             filter->ether_type);
6249                 return -EEXIST;
6250         }
6251         if (ret < 0 && !add) {
6252                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6253                             filter->ether_type);
6254                 return -ENOENT;
6255         }
6256
6257         if (add) {
6258                 ret = ixgbe_ethertype_filter_insert(filter_info,
6259                         filter->ether_type);
6260                 if (ret < 0) {
6261                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6262                         return -ENOSYS;
6263                 }
6264                 etqf = IXGBE_ETQF_FILTER_EN;
6265                 etqf |= (uint32_t)filter->ether_type;
6266                 etqs |= (uint32_t)((filter->queue <<
6267                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6268                                     IXGBE_ETQS_RX_QUEUE);
6269                 etqs |= IXGBE_ETQS_QUEUE_EN;
6270         } else {
6271                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6272                 if (ret < 0)
6273                         return -ENOSYS;
6274         }
6275         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6276         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6277         IXGBE_WRITE_FLUSH(hw);
6278
6279         return 0;
6280 }
6281
6282 static int
6283 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6284                         struct rte_eth_ethertype_filter *filter)
6285 {
6286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6287         struct ixgbe_filter_info *filter_info =
6288                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6289         uint32_t etqf, etqs;
6290         int ret;
6291
6292         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6293         if (ret < 0) {
6294                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6295                             filter->ether_type);
6296                 return -ENOENT;
6297         }
6298
6299         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6300         if (etqf & IXGBE_ETQF_FILTER_EN) {
6301                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6302                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6303                 filter->flags = 0;
6304                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6305                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6306                 return 0;
6307         }
6308         return -ENOENT;
6309 }
6310
6311 /*
6312  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6313  * @dev: pointer to rte_eth_dev structure
6314  * @filter_op:operation will be taken.
6315  * @arg: a pointer to specific structure corresponding to the filter_op
6316  */
6317 static int
6318 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6319                                 enum rte_filter_op filter_op,
6320                                 void *arg)
6321 {
6322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6323         int ret;
6324
6325         MAC_TYPE_FILTER_SUP(hw->mac.type);
6326
6327         if (filter_op == RTE_ETH_FILTER_NOP)
6328                 return 0;
6329
6330         if (arg == NULL) {
6331                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6332                             filter_op);
6333                 return -EINVAL;
6334         }
6335
6336         switch (filter_op) {
6337         case RTE_ETH_FILTER_ADD:
6338                 ret = ixgbe_add_del_ethertype_filter(dev,
6339                         (struct rte_eth_ethertype_filter *)arg,
6340                         TRUE);
6341                 break;
6342         case RTE_ETH_FILTER_DELETE:
6343                 ret = ixgbe_add_del_ethertype_filter(dev,
6344                         (struct rte_eth_ethertype_filter *)arg,
6345                         FALSE);
6346                 break;
6347         case RTE_ETH_FILTER_GET:
6348                 ret = ixgbe_get_ethertype_filter(dev,
6349                         (struct rte_eth_ethertype_filter *)arg);
6350                 break;
6351         default:
6352                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6353                 ret = -EINVAL;
6354                 break;
6355         }
6356         return ret;
6357 }
6358
6359 static int
6360 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6361                      enum rte_filter_type filter_type,
6362                      enum rte_filter_op filter_op,
6363                      void *arg)
6364 {
6365         int ret = -EINVAL;
6366
6367         switch (filter_type) {
6368         case RTE_ETH_FILTER_NTUPLE:
6369                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6370                 break;
6371         case RTE_ETH_FILTER_ETHERTYPE:
6372                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6373                 break;
6374         case RTE_ETH_FILTER_SYN:
6375                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6376                 break;
6377         case RTE_ETH_FILTER_FDIR:
6378                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6379                 break;
6380         case RTE_ETH_FILTER_L2_TUNNEL:
6381                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6382                 break;
6383         default:
6384                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6385                                                         filter_type);
6386                 break;
6387         }
6388
6389         return ret;
6390 }
6391
6392 static u8 *
6393 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6394                         u8 **mc_addr_ptr, u32 *vmdq)
6395 {
6396         u8 *mc_addr;
6397
6398         *vmdq = 0;
6399         mc_addr = *mc_addr_ptr;
6400         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6401         return mc_addr;
6402 }
6403
6404 static int
6405 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6406                           struct ether_addr *mc_addr_set,
6407                           uint32_t nb_mc_addr)
6408 {
6409         struct ixgbe_hw *hw;
6410         u8 *mc_addr_list;
6411
6412         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6413         mc_addr_list = (u8 *)mc_addr_set;
6414         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6415                                          ixgbe_dev_addr_list_itr, TRUE);
6416 }
6417
6418 static uint64_t
6419 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6420 {
6421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6422         uint64_t systime_cycles;
6423
6424         switch (hw->mac.type) {
6425         case ixgbe_mac_X550:
6426         case ixgbe_mac_X550EM_x:
6427         case ixgbe_mac_X550EM_a:
6428                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6429                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6430                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6431                                 * NSEC_PER_SEC;
6432                 break;
6433         default:
6434                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6435                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6436                                 << 32;
6437         }
6438
6439         return systime_cycles;
6440 }
6441
6442 static uint64_t
6443 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6444 {
6445         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6446         uint64_t rx_tstamp_cycles;
6447
6448         switch (hw->mac.type) {
6449         case ixgbe_mac_X550:
6450         case ixgbe_mac_X550EM_x:
6451         case ixgbe_mac_X550EM_a:
6452                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6453                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6454                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6455                                 * NSEC_PER_SEC;
6456                 break;
6457         default:
6458                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6459                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6460                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6461                                 << 32;
6462         }
6463
6464         return rx_tstamp_cycles;
6465 }
6466
6467 static uint64_t
6468 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6469 {
6470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6471         uint64_t tx_tstamp_cycles;
6472
6473         switch (hw->mac.type) {
6474         case ixgbe_mac_X550:
6475         case ixgbe_mac_X550EM_x:
6476         case ixgbe_mac_X550EM_a:
6477                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6478                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6479                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6480                                 * NSEC_PER_SEC;
6481                 break;
6482         default:
6483                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6484                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6485                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6486                                 << 32;
6487         }
6488
6489         return tx_tstamp_cycles;
6490 }
6491
6492 static void
6493 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6494 {
6495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6496         struct ixgbe_adapter *adapter =
6497                 (struct ixgbe_adapter *)dev->data->dev_private;
6498         struct rte_eth_link link;
6499         uint32_t incval = 0;
6500         uint32_t shift = 0;
6501
6502         /* Get current link speed. */
6503         memset(&link, 0, sizeof(link));
6504         ixgbe_dev_link_update(dev, 1);
6505         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6506
6507         switch (link.link_speed) {
6508         case ETH_SPEED_NUM_100M:
6509                 incval = IXGBE_INCVAL_100;
6510                 shift = IXGBE_INCVAL_SHIFT_100;
6511                 break;
6512         case ETH_SPEED_NUM_1G:
6513                 incval = IXGBE_INCVAL_1GB;
6514                 shift = IXGBE_INCVAL_SHIFT_1GB;
6515                 break;
6516         case ETH_SPEED_NUM_10G:
6517         default:
6518                 incval = IXGBE_INCVAL_10GB;
6519                 shift = IXGBE_INCVAL_SHIFT_10GB;
6520                 break;
6521         }
6522
6523         switch (hw->mac.type) {
6524         case ixgbe_mac_X550:
6525         case ixgbe_mac_X550EM_x:
6526         case ixgbe_mac_X550EM_a:
6527                 /* Independent of link speed. */
6528                 incval = 1;
6529                 /* Cycles read will be interpreted as ns. */
6530                 shift = 0;
6531                 /* Fall-through */
6532         case ixgbe_mac_X540:
6533                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6534                 break;
6535         case ixgbe_mac_82599EB:
6536                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6537                 shift -= IXGBE_INCVAL_SHIFT_82599;
6538                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6539                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6540                 break;
6541         default:
6542                 /* Not supported. */
6543                 return;
6544         }
6545
6546         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6547         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6548         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6549
6550         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6551         adapter->systime_tc.cc_shift = shift;
6552         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6553
6554         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6555         adapter->rx_tstamp_tc.cc_shift = shift;
6556         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6557
6558         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6559         adapter->tx_tstamp_tc.cc_shift = shift;
6560         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6561 }
6562
6563 static int
6564 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6565 {
6566         struct ixgbe_adapter *adapter =
6567                         (struct ixgbe_adapter *)dev->data->dev_private;
6568
6569         adapter->systime_tc.nsec += delta;
6570         adapter->rx_tstamp_tc.nsec += delta;
6571         adapter->tx_tstamp_tc.nsec += delta;
6572
6573         return 0;
6574 }
6575
6576 static int
6577 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6578 {
6579         uint64_t ns;
6580         struct ixgbe_adapter *adapter =
6581                         (struct ixgbe_adapter *)dev->data->dev_private;
6582
6583         ns = rte_timespec_to_ns(ts);
6584         /* Set the timecounters to a new value. */
6585         adapter->systime_tc.nsec = ns;
6586         adapter->rx_tstamp_tc.nsec = ns;
6587         adapter->tx_tstamp_tc.nsec = ns;
6588
6589         return 0;
6590 }
6591
6592 static int
6593 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6594 {
6595         uint64_t ns, systime_cycles;
6596         struct ixgbe_adapter *adapter =
6597                         (struct ixgbe_adapter *)dev->data->dev_private;
6598
6599         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6600         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6601         *ts = rte_ns_to_timespec(ns);
6602
6603         return 0;
6604 }
6605
6606 static int
6607 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6608 {
6609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6610         uint32_t tsync_ctl;
6611         uint32_t tsauxc;
6612
6613         /* Stop the timesync system time. */
6614         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6615         /* Reset the timesync system time value. */
6616         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6617         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6618
6619         /* Enable system time for platforms where it isn't on by default. */
6620         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6621         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6622         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6623
6624         ixgbe_start_timecounters(dev);
6625
6626         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6627         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6628                         (ETHER_TYPE_1588 |
6629                          IXGBE_ETQF_FILTER_EN |
6630                          IXGBE_ETQF_1588));
6631
6632         /* Enable timestamping of received PTP packets. */
6633         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6634         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6635         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6636
6637         /* Enable timestamping of transmitted PTP packets. */
6638         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6639         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6640         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6641
6642         IXGBE_WRITE_FLUSH(hw);
6643
6644         return 0;
6645 }
6646
6647 static int
6648 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6649 {
6650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6651         uint32_t tsync_ctl;
6652
6653         /* Disable timestamping of transmitted PTP packets. */
6654         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6655         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6656         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6657
6658         /* Disable timestamping of received PTP packets. */
6659         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6660         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6661         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6662
6663         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6664         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6665
6666         /* Stop incrementating the System Time registers. */
6667         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6668
6669         return 0;
6670 }
6671
6672 static int
6673 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6674                                  struct timespec *timestamp,
6675                                  uint32_t flags __rte_unused)
6676 {
6677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6678         struct ixgbe_adapter *adapter =
6679                 (struct ixgbe_adapter *)dev->data->dev_private;
6680         uint32_t tsync_rxctl;
6681         uint64_t rx_tstamp_cycles;
6682         uint64_t ns;
6683
6684         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6685         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6686                 return -EINVAL;
6687
6688         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6689         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6690         *timestamp = rte_ns_to_timespec(ns);
6691
6692         return  0;
6693 }
6694
6695 static int
6696 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6697                                  struct timespec *timestamp)
6698 {
6699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         struct ixgbe_adapter *adapter =
6701                 (struct ixgbe_adapter *)dev->data->dev_private;
6702         uint32_t tsync_txctl;
6703         uint64_t tx_tstamp_cycles;
6704         uint64_t ns;
6705
6706         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6707         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6708                 return -EINVAL;
6709
6710         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6711         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6712         *timestamp = rte_ns_to_timespec(ns);
6713
6714         return 0;
6715 }
6716
6717 static int
6718 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6719 {
6720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6721         int count = 0;
6722         int g_ind = 0;
6723         const struct reg_info *reg_group;
6724         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6725                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6726
6727         while ((reg_group = reg_set[g_ind++]))
6728                 count += ixgbe_regs_group_count(reg_group);
6729
6730         return count;
6731 }
6732
6733 static int
6734 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6735 {
6736         int count = 0;
6737         int g_ind = 0;
6738         const struct reg_info *reg_group;
6739
6740         while ((reg_group = ixgbevf_regs[g_ind++]))
6741                 count += ixgbe_regs_group_count(reg_group);
6742
6743         return count;
6744 }
6745
6746 static int
6747 ixgbe_get_regs(struct rte_eth_dev *dev,
6748               struct rte_dev_reg_info *regs)
6749 {
6750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751         uint32_t *data = regs->data;
6752         int g_ind = 0;
6753         int count = 0;
6754         const struct reg_info *reg_group;
6755         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6756                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6757
6758         if (data == NULL) {
6759                 regs->length = ixgbe_get_reg_length(dev);
6760                 regs->width = sizeof(uint32_t);
6761                 return 0;
6762         }
6763
6764         /* Support only full register dump */
6765         if ((regs->length == 0) ||
6766             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6767                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6768                         hw->device_id;
6769                 while ((reg_group = reg_set[g_ind++]))
6770                         count += ixgbe_read_regs_group(dev, &data[count],
6771                                 reg_group);
6772                 return 0;
6773         }
6774
6775         return -ENOTSUP;
6776 }
6777
6778 static int
6779 ixgbevf_get_regs(struct rte_eth_dev *dev,
6780                 struct rte_dev_reg_info *regs)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         uint32_t *data = regs->data;
6784         int g_ind = 0;
6785         int count = 0;
6786         const struct reg_info *reg_group;
6787
6788         if (data == NULL) {
6789                 regs->length = ixgbevf_get_reg_length(dev);
6790                 regs->width = sizeof(uint32_t);
6791                 return 0;
6792         }
6793
6794         /* Support only full register dump */
6795         if ((regs->length == 0) ||
6796             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6797                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6798                         hw->device_id;
6799                 while ((reg_group = ixgbevf_regs[g_ind++]))
6800                         count += ixgbe_read_regs_group(dev, &data[count],
6801                                                       reg_group);
6802                 return 0;
6803         }
6804
6805         return -ENOTSUP;
6806 }
6807
6808 static int
6809 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6810 {
6811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6812
6813         /* Return unit is byte count */
6814         return hw->eeprom.word_size * 2;
6815 }
6816
6817 static int
6818 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6819                 struct rte_dev_eeprom_info *in_eeprom)
6820 {
6821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6822         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6823         uint16_t *data = in_eeprom->data;
6824         int first, length;
6825
6826         first = in_eeprom->offset >> 1;
6827         length = in_eeprom->length >> 1;
6828         if ((first > hw->eeprom.word_size) ||
6829             ((first + length) > hw->eeprom.word_size))
6830                 return -EINVAL;
6831
6832         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6833
6834         return eeprom->ops.read_buffer(hw, first, length, data);
6835 }
6836
6837 static int
6838 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6839                 struct rte_dev_eeprom_info *in_eeprom)
6840 {
6841         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6842         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6843         uint16_t *data = in_eeprom->data;
6844         int first, length;
6845
6846         first = in_eeprom->offset >> 1;
6847         length = in_eeprom->length >> 1;
6848         if ((first > hw->eeprom.word_size) ||
6849             ((first + length) > hw->eeprom.word_size))
6850                 return -EINVAL;
6851
6852         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6853
6854         return eeprom->ops.write_buffer(hw,  first, length, data);
6855 }
6856
6857 uint16_t
6858 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6859         switch (mac_type) {
6860         case ixgbe_mac_X550:
6861         case ixgbe_mac_X550EM_x:
6862         case ixgbe_mac_X550EM_a:
6863                 return ETH_RSS_RETA_SIZE_512;
6864         case ixgbe_mac_X550_vf:
6865         case ixgbe_mac_X550EM_x_vf:
6866         case ixgbe_mac_X550EM_a_vf:
6867                 return ETH_RSS_RETA_SIZE_64;
6868         default:
6869                 return ETH_RSS_RETA_SIZE_128;
6870         }
6871 }
6872
6873 uint32_t
6874 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6875         switch (mac_type) {
6876         case ixgbe_mac_X550:
6877         case ixgbe_mac_X550EM_x:
6878         case ixgbe_mac_X550EM_a:
6879                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6880                         return IXGBE_RETA(reta_idx >> 2);
6881                 else
6882                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6883         case ixgbe_mac_X550_vf:
6884         case ixgbe_mac_X550EM_x_vf:
6885         case ixgbe_mac_X550EM_a_vf:
6886                 return IXGBE_VFRETA(reta_idx >> 2);
6887         default:
6888                 return IXGBE_RETA(reta_idx >> 2);
6889         }
6890 }
6891
6892 uint32_t
6893 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6894         switch (mac_type) {
6895         case ixgbe_mac_X550_vf:
6896         case ixgbe_mac_X550EM_x_vf:
6897         case ixgbe_mac_X550EM_a_vf:
6898                 return IXGBE_VFMRQC;
6899         default:
6900                 return IXGBE_MRQC;
6901         }
6902 }
6903
6904 uint32_t
6905 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6906         switch (mac_type) {
6907         case ixgbe_mac_X550_vf:
6908         case ixgbe_mac_X550EM_x_vf:
6909         case ixgbe_mac_X550EM_a_vf:
6910                 return IXGBE_VFRSSRK(i);
6911         default:
6912                 return IXGBE_RSSRK(i);
6913         }
6914 }
6915
6916 bool
6917 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6918         switch (mac_type) {
6919         case ixgbe_mac_82599_vf:
6920         case ixgbe_mac_X540_vf:
6921                 return 0;
6922         default:
6923                 return 1;
6924         }
6925 }
6926
6927 static int
6928 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6929                         struct rte_eth_dcb_info *dcb_info)
6930 {
6931         struct ixgbe_dcb_config *dcb_config =
6932                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6933         struct ixgbe_dcb_tc_config *tc;
6934         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
6935         uint8_t nb_tcs;
6936         uint8_t i, j;
6937
6938         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6939                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6940         else
6941                 dcb_info->nb_tcs = 1;
6942
6943         tc_queue = &dcb_info->tc_queue;
6944         nb_tcs = dcb_info->nb_tcs;
6945
6946         if (dcb_config->vt_mode) { /* vt is enabled*/
6947                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6948                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6949                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6950                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6951                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
6952                         for (j = 0; j < nb_tcs; j++) {
6953                                 tc_queue->tc_rxq[0][j].base = j;
6954                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
6955                                 tc_queue->tc_txq[0][j].base = j;
6956                                 tc_queue->tc_txq[0][j].nb_queue = 1;
6957                         }
6958                 } else {
6959                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6960                                 for (j = 0; j < nb_tcs; j++) {
6961                                         tc_queue->tc_rxq[i][j].base =
6962                                                 i * nb_tcs + j;
6963                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
6964                                         tc_queue->tc_txq[i][j].base =
6965                                                 i * nb_tcs + j;
6966                                         tc_queue->tc_txq[i][j].nb_queue = 1;
6967                                 }
6968                         }
6969                 }
6970         } else { /* vt is disabled*/
6971                 struct rte_eth_dcb_rx_conf *rx_conf =
6972                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6973                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6974                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6975                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6976                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6977                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6978                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6979                         }
6980                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6981                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6982                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6983                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6984                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6985                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6986                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6987                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6988                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6989                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6990                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6991                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6992                         }
6993                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6994                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6995                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6996                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6997                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6998                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6999                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7000                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7001                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7002                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7003                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7004                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7005                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7006                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7007                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7008                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7009                 }
7010         }
7011         for (i = 0; i < dcb_info->nb_tcs; i++) {
7012                 tc = &dcb_config->tc_config[i];
7013                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7014         }
7015         return 0;
7016 }
7017
7018 /* Update e-tag ether type */
7019 static int
7020 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7021                             uint16_t ether_type)
7022 {
7023         uint32_t etag_etype;
7024
7025         if (hw->mac.type != ixgbe_mac_X550 &&
7026             hw->mac.type != ixgbe_mac_X550EM_x &&
7027             hw->mac.type != ixgbe_mac_X550EM_a) {
7028                 return -ENOTSUP;
7029         }
7030
7031         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7032         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7033         etag_etype |= ether_type;
7034         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7035         IXGBE_WRITE_FLUSH(hw);
7036
7037         return 0;
7038 }
7039
7040 /* Config l2 tunnel ether type */
7041 static int
7042 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7043                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7044 {
7045         int ret = 0;
7046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7047
7048         if (l2_tunnel == NULL)
7049                 return -EINVAL;
7050
7051         switch (l2_tunnel->l2_tunnel_type) {
7052         case RTE_L2_TUNNEL_TYPE_E_TAG:
7053                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7054                 break;
7055         default:
7056                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7057                 ret = -EINVAL;
7058                 break;
7059         }
7060
7061         return ret;
7062 }
7063
7064 /* Enable e-tag tunnel */
7065 static int
7066 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7067 {
7068         uint32_t etag_etype;
7069
7070         if (hw->mac.type != ixgbe_mac_X550 &&
7071             hw->mac.type != ixgbe_mac_X550EM_x &&
7072             hw->mac.type != ixgbe_mac_X550EM_a) {
7073                 return -ENOTSUP;
7074         }
7075
7076         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7077         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7078         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7079         IXGBE_WRITE_FLUSH(hw);
7080
7081         return 0;
7082 }
7083
7084 /* Enable l2 tunnel */
7085 static int
7086 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7087                            enum rte_eth_tunnel_type l2_tunnel_type)
7088 {
7089         int ret = 0;
7090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7091
7092         switch (l2_tunnel_type) {
7093         case RTE_L2_TUNNEL_TYPE_E_TAG:
7094                 ret = ixgbe_e_tag_enable(hw);
7095                 break;
7096         default:
7097                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7098                 ret = -EINVAL;
7099                 break;
7100         }
7101
7102         return ret;
7103 }
7104
7105 /* Disable e-tag tunnel */
7106 static int
7107 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7108 {
7109         uint32_t etag_etype;
7110
7111         if (hw->mac.type != ixgbe_mac_X550 &&
7112             hw->mac.type != ixgbe_mac_X550EM_x &&
7113             hw->mac.type != ixgbe_mac_X550EM_a) {
7114                 return -ENOTSUP;
7115         }
7116
7117         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7118         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7119         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7120         IXGBE_WRITE_FLUSH(hw);
7121
7122         return 0;
7123 }
7124
7125 /* Disable l2 tunnel */
7126 static int
7127 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7128                             enum rte_eth_tunnel_type l2_tunnel_type)
7129 {
7130         int ret = 0;
7131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7132
7133         switch (l2_tunnel_type) {
7134         case RTE_L2_TUNNEL_TYPE_E_TAG:
7135                 ret = ixgbe_e_tag_disable(hw);
7136                 break;
7137         default:
7138                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7139                 ret = -EINVAL;
7140                 break;
7141         }
7142
7143         return ret;
7144 }
7145
7146 static int
7147 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7148                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7149 {
7150         int ret = 0;
7151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7152         uint32_t i, rar_entries;
7153         uint32_t rar_low, rar_high;
7154
7155         if (hw->mac.type != ixgbe_mac_X550 &&
7156             hw->mac.type != ixgbe_mac_X550EM_x &&
7157             hw->mac.type != ixgbe_mac_X550EM_a) {
7158                 return -ENOTSUP;
7159         }
7160
7161         rar_entries = ixgbe_get_num_rx_addrs(hw);
7162
7163         for (i = 1; i < rar_entries; i++) {
7164                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7165                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7166                 if ((rar_high & IXGBE_RAH_AV) &&
7167                     (rar_high & IXGBE_RAH_ADTYPE) &&
7168                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7169                      l2_tunnel->tunnel_id)) {
7170                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7171                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7172
7173                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7174
7175                         return ret;
7176                 }
7177         }
7178
7179         return ret;
7180 }
7181
7182 static int
7183 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7184                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7185 {
7186         int ret = 0;
7187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7188         uint32_t i, rar_entries;
7189         uint32_t rar_low, rar_high;
7190
7191         if (hw->mac.type != ixgbe_mac_X550 &&
7192             hw->mac.type != ixgbe_mac_X550EM_x &&
7193             hw->mac.type != ixgbe_mac_X550EM_a) {
7194                 return -ENOTSUP;
7195         }
7196
7197         /* One entry for one tunnel. Try to remove potential existing entry. */
7198         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7199
7200         rar_entries = ixgbe_get_num_rx_addrs(hw);
7201
7202         for (i = 1; i < rar_entries; i++) {
7203                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7204                 if (rar_high & IXGBE_RAH_AV) {
7205                         continue;
7206                 } else {
7207                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7208                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7209                         rar_low = l2_tunnel->tunnel_id;
7210
7211                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7212                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7213
7214                         return ret;
7215                 }
7216         }
7217
7218         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7219                      " Please remove a rule before adding a new one.");
7220         return -EINVAL;
7221 }
7222
7223 /* Add l2 tunnel filter */
7224 static int
7225 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7226                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7227 {
7228         int ret = 0;
7229
7230         switch (l2_tunnel->l2_tunnel_type) {
7231         case RTE_L2_TUNNEL_TYPE_E_TAG:
7232                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7233                 break;
7234         default:
7235                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7236                 ret = -EINVAL;
7237                 break;
7238         }
7239
7240         return ret;
7241 }
7242
7243 /* Delete l2 tunnel filter */
7244 static int
7245 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7246                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7247 {
7248         int ret = 0;
7249
7250         switch (l2_tunnel->l2_tunnel_type) {
7251         case RTE_L2_TUNNEL_TYPE_E_TAG:
7252                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7253                 break;
7254         default:
7255                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7256                 ret = -EINVAL;
7257                 break;
7258         }
7259
7260         return ret;
7261 }
7262
7263 /**
7264  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7265  * @dev: pointer to rte_eth_dev structure
7266  * @filter_op:operation will be taken.
7267  * @arg: a pointer to specific structure corresponding to the filter_op
7268  */
7269 static int
7270 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7271                                   enum rte_filter_op filter_op,
7272                                   void *arg)
7273 {
7274         int ret = 0;
7275
7276         if (filter_op == RTE_ETH_FILTER_NOP)
7277                 return 0;
7278
7279         if (arg == NULL) {
7280                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7281                             filter_op);
7282                 return -EINVAL;
7283         }
7284
7285         switch (filter_op) {
7286         case RTE_ETH_FILTER_ADD:
7287                 ret = ixgbe_dev_l2_tunnel_filter_add
7288                         (dev,
7289                          (struct rte_eth_l2_tunnel_conf *)arg);
7290                 break;
7291         case RTE_ETH_FILTER_DELETE:
7292                 ret = ixgbe_dev_l2_tunnel_filter_del
7293                         (dev,
7294                          (struct rte_eth_l2_tunnel_conf *)arg);
7295                 break;
7296         default:
7297                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7298                 ret = -EINVAL;
7299                 break;
7300         }
7301         return ret;
7302 }
7303
7304 static int
7305 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7306 {
7307         int ret = 0;
7308         uint32_t ctrl;
7309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7310
7311         if (hw->mac.type != ixgbe_mac_X550 &&
7312             hw->mac.type != ixgbe_mac_X550EM_x &&
7313             hw->mac.type != ixgbe_mac_X550EM_a) {
7314                 return -ENOTSUP;
7315         }
7316
7317         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7318         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7319         if (en)
7320                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7321         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7322
7323         return ret;
7324 }
7325
7326 /* Enable l2 tunnel forwarding */
7327 static int
7328 ixgbe_dev_l2_tunnel_forwarding_enable
7329         (struct rte_eth_dev *dev,
7330          enum rte_eth_tunnel_type l2_tunnel_type)
7331 {
7332         int ret = 0;
7333
7334         switch (l2_tunnel_type) {
7335         case RTE_L2_TUNNEL_TYPE_E_TAG:
7336                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7337                 break;
7338         default:
7339                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7340                 ret = -EINVAL;
7341                 break;
7342         }
7343
7344         return ret;
7345 }
7346
7347 /* Disable l2 tunnel forwarding */
7348 static int
7349 ixgbe_dev_l2_tunnel_forwarding_disable
7350         (struct rte_eth_dev *dev,
7351          enum rte_eth_tunnel_type l2_tunnel_type)
7352 {
7353         int ret = 0;
7354
7355         switch (l2_tunnel_type) {
7356         case RTE_L2_TUNNEL_TYPE_E_TAG:
7357                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7358                 break;
7359         default:
7360                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7361                 ret = -EINVAL;
7362                 break;
7363         }
7364
7365         return ret;
7366 }
7367
7368 static int
7369 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7370                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7371                              bool en)
7372 {
7373         int ret = 0;
7374         uint32_t vmtir, vmvir;
7375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7376
7377         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7378                 PMD_DRV_LOG(ERR,
7379                             "VF id %u should be less than %u",
7380                             l2_tunnel->vf_id,
7381                             dev->pci_dev->max_vfs);
7382                 return -EINVAL;
7383         }
7384
7385         if (hw->mac.type != ixgbe_mac_X550 &&
7386             hw->mac.type != ixgbe_mac_X550EM_x &&
7387             hw->mac.type != ixgbe_mac_X550EM_a) {
7388                 return -ENOTSUP;
7389         }
7390
7391         if (en)
7392                 vmtir = l2_tunnel->tunnel_id;
7393         else
7394                 vmtir = 0;
7395
7396         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7397
7398         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7399         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7400         if (en)
7401                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7402         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7403
7404         return ret;
7405 }
7406
7407 /* Enable l2 tunnel tag insertion */
7408 static int
7409 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7410                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7411 {
7412         int ret = 0;
7413
7414         switch (l2_tunnel->l2_tunnel_type) {
7415         case RTE_L2_TUNNEL_TYPE_E_TAG:
7416                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7417                 break;
7418         default:
7419                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7420                 ret = -EINVAL;
7421                 break;
7422         }
7423
7424         return ret;
7425 }
7426
7427 /* Disable l2 tunnel tag insertion */
7428 static int
7429 ixgbe_dev_l2_tunnel_insertion_disable
7430         (struct rte_eth_dev *dev,
7431          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7432 {
7433         int ret = 0;
7434
7435         switch (l2_tunnel->l2_tunnel_type) {
7436         case RTE_L2_TUNNEL_TYPE_E_TAG:
7437                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7438                 break;
7439         default:
7440                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7441                 ret = -EINVAL;
7442                 break;
7443         }
7444
7445         return ret;
7446 }
7447
7448 static int
7449 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7450                              bool en)
7451 {
7452         int ret = 0;
7453         uint32_t qde;
7454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7455
7456         if (hw->mac.type != ixgbe_mac_X550 &&
7457             hw->mac.type != ixgbe_mac_X550EM_x &&
7458             hw->mac.type != ixgbe_mac_X550EM_a) {
7459                 return -ENOTSUP;
7460         }
7461
7462         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7463         if (en)
7464                 qde |= IXGBE_QDE_STRIP_TAG;
7465         else
7466                 qde &= ~IXGBE_QDE_STRIP_TAG;
7467         qde &= ~IXGBE_QDE_READ;
7468         qde |= IXGBE_QDE_WRITE;
7469         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7470
7471         return ret;
7472 }
7473
7474 /* Enable l2 tunnel tag stripping */
7475 static int
7476 ixgbe_dev_l2_tunnel_stripping_enable
7477         (struct rte_eth_dev *dev,
7478          enum rte_eth_tunnel_type l2_tunnel_type)
7479 {
7480         int ret = 0;
7481
7482         switch (l2_tunnel_type) {
7483         case RTE_L2_TUNNEL_TYPE_E_TAG:
7484                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7485                 break;
7486         default:
7487                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7488                 ret = -EINVAL;
7489                 break;
7490         }
7491
7492         return ret;
7493 }
7494
7495 /* Disable l2 tunnel tag stripping */
7496 static int
7497 ixgbe_dev_l2_tunnel_stripping_disable
7498         (struct rte_eth_dev *dev,
7499          enum rte_eth_tunnel_type l2_tunnel_type)
7500 {
7501         int ret = 0;
7502
7503         switch (l2_tunnel_type) {
7504         case RTE_L2_TUNNEL_TYPE_E_TAG:
7505                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7506                 break;
7507         default:
7508                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7509                 ret = -EINVAL;
7510                 break;
7511         }
7512
7513         return ret;
7514 }
7515
7516 /* Enable/disable l2 tunnel offload functions */
7517 static int
7518 ixgbe_dev_l2_tunnel_offload_set
7519         (struct rte_eth_dev *dev,
7520          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7521          uint32_t mask,
7522          uint8_t en)
7523 {
7524         int ret = 0;
7525
7526         if (l2_tunnel == NULL)
7527                 return -EINVAL;
7528
7529         ret = -EINVAL;
7530         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7531                 if (en)
7532                         ret = ixgbe_dev_l2_tunnel_enable(
7533                                 dev,
7534                                 l2_tunnel->l2_tunnel_type);
7535                 else
7536                         ret = ixgbe_dev_l2_tunnel_disable(
7537                                 dev,
7538                                 l2_tunnel->l2_tunnel_type);
7539         }
7540
7541         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7542                 if (en)
7543                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7544                                 dev,
7545                                 l2_tunnel);
7546                 else
7547                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7548                                 dev,
7549                                 l2_tunnel);
7550         }
7551
7552         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7553                 if (en)
7554                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7555                                 dev,
7556                                 l2_tunnel->l2_tunnel_type);
7557                 else
7558                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7559                                 dev,
7560                                 l2_tunnel->l2_tunnel_type);
7561         }
7562
7563         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7564                 if (en)
7565                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7566                                 dev,
7567                                 l2_tunnel->l2_tunnel_type);
7568                 else
7569                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7570                                 dev,
7571                                 l2_tunnel->l2_tunnel_type);
7572         }
7573
7574         return ret;
7575 }
7576
7577 static int
7578 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7579                         uint16_t port)
7580 {
7581         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7582         IXGBE_WRITE_FLUSH(hw);
7583
7584         return 0;
7585 }
7586
7587 /* There's only one register for VxLAN UDP port.
7588  * So, we cannot add several ports. Will update it.
7589  */
7590 static int
7591 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7592                      uint16_t port)
7593 {
7594         if (port == 0) {
7595                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7596                 return -EINVAL;
7597         }
7598
7599         return ixgbe_update_vxlan_port(hw, port);
7600 }
7601
7602 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7603  * UDP port, it must have a value.
7604  * So, will reset it to the original value 0.
7605  */
7606 static int
7607 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7608                      uint16_t port)
7609 {
7610         uint16_t cur_port;
7611
7612         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7613
7614         if (cur_port != port) {
7615                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7616                 return -EINVAL;
7617         }
7618
7619         return ixgbe_update_vxlan_port(hw, 0);
7620 }
7621
7622 /* Add UDP tunneling port */
7623 static int
7624 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7625                               struct rte_eth_udp_tunnel *udp_tunnel)
7626 {
7627         int ret = 0;
7628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7629
7630         if (hw->mac.type != ixgbe_mac_X550 &&
7631             hw->mac.type != ixgbe_mac_X550EM_x &&
7632             hw->mac.type != ixgbe_mac_X550EM_a) {
7633                 return -ENOTSUP;
7634         }
7635
7636         if (udp_tunnel == NULL)
7637                 return -EINVAL;
7638
7639         switch (udp_tunnel->prot_type) {
7640         case RTE_TUNNEL_TYPE_VXLAN:
7641                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7642                 break;
7643
7644         case RTE_TUNNEL_TYPE_GENEVE:
7645         case RTE_TUNNEL_TYPE_TEREDO:
7646                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7647                 ret = -EINVAL;
7648                 break;
7649
7650         default:
7651                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7652                 ret = -EINVAL;
7653                 break;
7654         }
7655
7656         return ret;
7657 }
7658
7659 /* Remove UDP tunneling port */
7660 static int
7661 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7662                               struct rte_eth_udp_tunnel *udp_tunnel)
7663 {
7664         int ret = 0;
7665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7666
7667         if (hw->mac.type != ixgbe_mac_X550 &&
7668             hw->mac.type != ixgbe_mac_X550EM_x &&
7669             hw->mac.type != ixgbe_mac_X550EM_a) {
7670                 return -ENOTSUP;
7671         }
7672
7673         if (udp_tunnel == NULL)
7674                 return -EINVAL;
7675
7676         switch (udp_tunnel->prot_type) {
7677         case RTE_TUNNEL_TYPE_VXLAN:
7678                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7679                 break;
7680         case RTE_TUNNEL_TYPE_GENEVE:
7681         case RTE_TUNNEL_TYPE_TEREDO:
7682                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7683                 ret = -EINVAL;
7684                 break;
7685         default:
7686                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7687                 ret = -EINVAL;
7688                 break;
7689         }
7690
7691         return ret;
7692 }
7693
7694 static void
7695 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7696 {
7697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7698
7699         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7700 }
7701
7702 static void
7703 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7704 {
7705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7706
7707         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7708 }
7709
7710 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7711 {
7712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7713         u32 in_msg = 0;
7714
7715         /* peek the message first */
7716         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7717
7718         /* PF reset VF event */
7719         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7720                 /* dummy mbx read to ack pf */
7721                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7722                         return;
7723                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7724                                               NULL);
7725         }
7726 }
7727
7728 static int
7729 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7730 {
7731         uint32_t eicr;
7732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7733         struct ixgbe_interrupt *intr =
7734                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7735         ixgbevf_intr_disable(hw);
7736
7737         /* read-on-clear nic registers here */
7738         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7739         intr->flags = 0;
7740
7741         /* only one misc vector supported - mailbox */
7742         eicr &= IXGBE_VTEICR_MASK;
7743         if (eicr == IXGBE_MISC_VEC_ID)
7744                 intr->flags |= IXGBE_FLAG_MAILBOX;
7745
7746         return 0;
7747 }
7748
7749 static int
7750 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7751 {
7752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7753         struct ixgbe_interrupt *intr =
7754                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7755
7756         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7757                 ixgbevf_mbx_process(dev);
7758                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7759         }
7760
7761         ixgbevf_intr_enable(hw);
7762
7763         return 0;
7764 }
7765
7766 static void
7767 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7768                               void *param)
7769 {
7770         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7771
7772         ixgbevf_dev_interrupt_get_status(dev);
7773         ixgbevf_dev_interrupt_action(dev);
7774 }
7775
7776 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7777 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7778 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7779 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);