drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 /*
  77  * High threshold controlling when to start sending XOFF frames. Must be at
  78  * least 8 bytes less than receive packet buffer size. This value is in units
  79  * of 1024 bytes.
  80  */
  81 #define IXGBE_FC_HI    0x80
  82
  83 /*
  84  * Low threshold controlling when to start sending XON frames. This value is
  85  * in units of 1024 bytes.
  86  */
  87 #define IXGBE_FC_LO    0x40
  88
  89 /* Default minimum inter-interrupt interval for EITR configuration */
  90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  91
  92 /* Timer value included in XOFF frames. */
  93 #define IXGBE_FC_PAUSE 0x680
  94
  95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  96 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  97 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  98
  99 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 100 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 101 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 102
 103 /*
 104  *  Default values for RX/TX configuration
 105  */
 106 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 107 #define IXGBE_DEFAULT_RX_PTHRESH      8
 108 #define IXGBE_DEFAULT_RX_HTHRESH      8
 109 #define IXGBE_DEFAULT_RX_WTHRESH      0
 110
 111 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 112 #define IXGBE_DEFAULT_TX_PTHRESH      32
 113 #define IXGBE_DEFAULT_TX_HTHRESH      0
 114 #define IXGBE_DEFAULT_TX_WTHRESH      0
 115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 116
 117 /* Bit shift and mask */
 118 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 119 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 120 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 121 #define IXGBE_8_BIT_MASK   UINT8_MAX
 122
 123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 124
 125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 126
 127 #define IXGBE_HKEY_MAX_INDEX 10
 128
 129 /* Additional timesync values. */
 130 #define NSEC_PER_SEC             1000000000L
 131 #define IXGBE_INCVAL_10GB        0x66666666
 132 #define IXGBE_INCVAL_1GB         0x40000000
 133 #define IXGBE_INCVAL_100         0x50000000
 134 #define IXGBE_INCVAL_SHIFT_10GB  28
 135 #define IXGBE_INCVAL_SHIFT_1GB   24
 136 #define IXGBE_INCVAL_SHIFT_100   21
 137 #define IXGBE_INCVAL_SHIFT_82599 7
 138 #define IXGBE_INCPER_SHIFT_82599 24
 139
 140 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 144 #define DEFAULT_ETAG_ETYPE                     0x893f
 145 #define IXGBE_ETAG_ETYPE                       0x00005084
 146 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 147 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 148 #define IXGBE_RAH_ADTYPE                       0x40000000
 149 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 150 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 153 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 154 #define IXGBE_VTEICR_MASK                      0x07
 155
 156 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 157 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 158
 159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static int
 185 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 186                 uint64_t *values, unsigned int n);
 187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 189 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 190         struct rte_eth_xstat_name *xstats_names,
 191         unsigned int size);
 192 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 193         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 194 static int ixgbe_dev_xstats_get_names_by_id(
 195         struct rte_eth_dev *dev,
 196         struct rte_eth_xstat_name *xstats_names,
 197         const uint64_t *ids,
 198         unsigned int limit);
 199 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 200                                              uint16_t queue_id,
 201                                              uint8_t stat_idx,
 202                                              uint8_t is_rx);
 203 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 204                                  size_t fw_size);
 205 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 206                                struct rte_eth_dev_info *dev_info);
 207 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 208 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 209                                  struct rte_eth_dev_info *dev_info);
 210 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 211
 212 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 213                 uint16_t vlan_id, int on);
 214 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 215                                enum rte_vlan_type vlan_type,
 216                                uint16_t tpid_id);
 217 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 218                 uint16_t queue, bool on);
 219 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 220                 int on);
 221 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 222 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 225 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 226
 227 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 229 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_fc_conf *fc_conf);
 231 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 232                                struct rte_eth_fc_conf *fc_conf);
 233 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 234                 struct rte_eth_pfc_conf *pfc_conf);
 235 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 236                         struct rte_eth_rss_reta_entry64 *reta_conf,
 237                         uint16_t reta_size);
 238 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 239                         struct rte_eth_rss_reta_entry64 *reta_conf,
 240                         uint16_t reta_size);
 241 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 243 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 247                                       struct rte_intr_handle *handle);
 248 static void ixgbe_dev_interrupt_handler(void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                          uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static bool is_device_supported(struct rte_eth_dev *dev,
 257                                 struct rte_pci_driver *drv);
 258
 259 /* For Virtual Function support */
 260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 262 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 263 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 264 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 265                                    int wait_to_complete);
 266 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 267 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 268 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 269 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 270 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 271                 struct rte_eth_stats *stats);
 272 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 273 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 274                 uint16_t vlan_id, int on);
 275 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                 uint16_t queue, int on);
 277 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 278 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 279 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                             uint16_t queue_id);
 281 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                              uint16_t queue_id);
 283 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                  uint8_t queue, uint8_t msix_vector);
 285 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 287 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 288
 289 /* For Eth VMDQ APIs support */
 290 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 291                 ether_addr * mac_addr, uint8_t on);
 292 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 293 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 294                 struct rte_eth_mirror_conf *mirror_conf,
 295                 uint8_t rule_id, uint8_t on);
 296 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 297                 uint8_t rule_id);
 298 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 299                                           uint16_t queue_id);
 300 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 301                                            uint16_t queue_id);
 302 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 303                                uint8_t queue, uint8_t msix_vector);
 304 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 305
 306 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                 struct ether_addr *mac_addr,
 308                                 uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368 static void ixgbevf_dev_interrupt_handler(void *param);
 369
 370 static int ixgbe_dev_l2_tunnel_eth_type_conf
 371         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 372 static int ixgbe_dev_l2_tunnel_offload_set
 373         (struct rte_eth_dev *dev,
 374          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 375          uint32_t mask,
 376          uint8_t en);
 377 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 378                                              enum rte_filter_op filter_op,
 379                                              void *arg);
 380
 381 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 382                                          struct rte_eth_udp_tunnel *udp_tunnel);
 383 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 386 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 387
 388 /*
 389  * Define VF Stats MACRO for Non "cleared on read" register
 390  */
 391 #define UPDATE_VF_STAT(reg, last, cur)                          \
 392 {                                                               \
 393         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 394         cur += (latest - last) & UINT_MAX;                      \
 395         last = latest;                                          \
 396 }
 397
 398 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 399 {                                                                \
 400         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 401         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 402         u64 latest = ((new_msb << 32) | new_lsb);                \
 403         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 404         last = latest;                                           \
 405 }
 406
 407 #define IXGBE_SET_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] |= 1 << bit;\
 411         } while (0)
 412
 413 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] &= ~(1 << bit);\
 417         } while (0)
 418
 419 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (r) = (h)->bitmap[idx] >> bit & 1;\
 423         } while (0)
 424
 425 /*
 426  * The set of PCI devices this driver supports
 427  */
 428 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 477 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 479 #endif
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 /*
 484  * The set of PCI devices this driver supports (for 82599 VF)
 485  */
 486 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 497         { .vendor_id = 0, /* sentinel */ },
 498 };
 499
 500 static const struct rte_eth_desc_lim rx_desc_lim = {
 501         .nb_max = IXGBE_MAX_RING_DESC,
 502         .nb_min = IXGBE_MIN_RING_DESC,
 503         .nb_align = IXGBE_RXD_ALIGN,
 504 };
 505
 506 static const struct rte_eth_desc_lim tx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_TXD_ALIGN,
 510         .nb_seg_max = IXGBE_TX_MAX_SEG,
 511         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 512 };
 513
 514 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 515         .dev_configure        = ixgbe_dev_configure,
 516         .dev_start            = ixgbe_dev_start,
 517         .dev_stop             = ixgbe_dev_stop,
 518         .dev_set_link_up    = ixgbe_dev_set_link_up,
 519         .dev_set_link_down  = ixgbe_dev_set_link_down,
 520         .dev_close            = ixgbe_dev_close,
 521         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 522         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 523         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 524         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 525         .link_update          = ixgbe_dev_link_update,
 526         .stats_get            = ixgbe_dev_stats_get,
 527         .xstats_get           = ixgbe_dev_xstats_get,
 528         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 529         .stats_reset          = ixgbe_dev_stats_reset,
 530         .xstats_reset         = ixgbe_dev_xstats_reset,
 531         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 532         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 533         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 534         .fw_version_get       = ixgbe_fw_version_get,
 535         .dev_infos_get        = ixgbe_dev_info_get,
 536         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 537         .mtu_set              = ixgbe_dev_mtu_set,
 538         .vlan_filter_set      = ixgbe_vlan_filter_set,
 539         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 540         .vlan_offload_set     = ixgbe_vlan_offload_set,
 541         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 542         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 543         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 544         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 545         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 546         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 547         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 548         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 549         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 550         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 551         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 552         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 553         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 554         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 555         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 556         .dev_led_on           = ixgbe_dev_led_on,
 557         .dev_led_off          = ixgbe_dev_led_off,
 558         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 559         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 560         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 561         .mac_addr_add         = ixgbe_add_rar,
 562         .mac_addr_remove      = ixgbe_remove_rar,
 563         .mac_addr_set         = ixgbe_set_default_mac_addr,
 564         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 565         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 566         .mirror_rule_set      = ixgbe_mirror_rule_set,
 567         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 568         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 569         .reta_update          = ixgbe_dev_rss_reta_update,
 570         .reta_query           = ixgbe_dev_rss_reta_query,
 571         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 572         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 573         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 574         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 575         .rxq_info_get         = ixgbe_rxq_info_get,
 576         .txq_info_get         = ixgbe_txq_info_get,
 577         .timesync_enable      = ixgbe_timesync_enable,
 578         .timesync_disable     = ixgbe_timesync_disable,
 579         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 580         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 581         .get_reg              = ixgbe_get_regs,
 582         .get_eeprom_length    = ixgbe_get_eeprom_length,
 583         .get_eeprom           = ixgbe_get_eeprom,
 584         .set_eeprom           = ixgbe_set_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594 };
 595
 596 /*
 597  * dev_ops for virtual function, bare necessities for basic vf
 598  * operation have been implemented
 599  */
 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 601         .dev_configure        = ixgbevf_dev_configure,
 602         .dev_start            = ixgbevf_dev_start,
 603         .dev_stop             = ixgbevf_dev_stop,
 604         .link_update          = ixgbevf_dev_link_update,
 605         .stats_get            = ixgbevf_dev_stats_get,
 606         .xstats_get           = ixgbevf_dev_xstats_get,
 607         .stats_reset          = ixgbevf_dev_stats_reset,
 608         .xstats_reset         = ixgbevf_dev_stats_reset,
 609         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 610         .dev_close            = ixgbevf_dev_close,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 622         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 623         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 624         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 625         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 626         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 627         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 628         .mac_addr_add         = ixgbevf_add_mac_addr,
 629         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 630         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 631         .rxq_info_get         = ixgbe_rxq_info_get,
 632         .txq_info_get         = ixgbe_txq_info_get,
 633         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 634         .get_reg              = ixgbevf_get_regs,
 635         .reta_update          = ixgbe_dev_rss_reta_update,
 636         .reta_query           = ixgbe_dev_rss_reta_query,
 637         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 638         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 639 };
 640
 641 /* store statistics names and its offset in stats structure */
 642 struct rte_ixgbe_xstats_name_off {
 643         char name[RTE_ETH_XSTATS_NAME_SIZE];
 644         unsigned offset;
 645 };
 646
 647 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 648         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 649         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 650         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 651         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 652         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 653         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 654         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 655         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 656         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 657         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 658         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 659         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 660         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 661         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 662         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1023)},
 664         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 665                 prc1522)},
 666         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 667         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 668         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 669         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 670         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 671         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 672         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 673         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 674         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 675         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 676         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 677         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 678         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 679         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 680         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 681         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 682         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1023)},
 684         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 685                 ptc1522)},
 686         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 687         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 688         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 689         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 690
 691         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_add)},
 693         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 694                 fdirustat_remove)},
 695         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fadd)},
 697         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 698                 fdirfstat_fremove)},
 699         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmatch)},
 701         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 702                 fdirmiss)},
 703
 704         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 705         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 706         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 707                 fclast)},
 708         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 709         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 710         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 711         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 712         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 713                 fcoe_noddp)},
 714         {"rx_fcoe_no_direct_data_placement_ext_buff",
 715                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 716
 717         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxontxc)},
 719         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxonrxc)},
 721         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxofftxc)},
 723         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxoffrxc)},
 725         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 726 };
 727
 728 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 729                            sizeof(rte_ixgbe_stats_strings[0]))
 730
 731 /* MACsec statistics */
 732 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 733         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_untagged)},
 735         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_encrypted)},
 737         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 738                 out_pkts_protected)},
 739         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_encrypted)},
 741         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 742                 out_octets_protected)},
 743         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_untagged)},
 745         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_badtag)},
 747         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_nosci)},
 749         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_unknownsci)},
 751         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_decrypted)},
 753         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 754                 in_octets_validated)},
 755         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unchecked)},
 757         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_delayed)},
 759         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_late)},
 761         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_ok)},
 763         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_invalid)},
 765         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_notvalid)},
 767         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_unusedsa)},
 769         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_notusingsa)},
 771 };
 772
 773 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 774                            sizeof(rte_ixgbe_macsec_strings[0]))
 775
 776 /* Per-queue statistics */
 777 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 778         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 779         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 780         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 781         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 782 };
 783
 784 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 785                            sizeof(rte_ixgbe_rxq_strings[0]))
 786 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 787
 788 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 789         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 790         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 791         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 792                 pxon2offc)},
 793 };
 794
 795 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 796                            sizeof(rte_ixgbe_txq_strings[0]))
 797 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 798
 799 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 800         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 801 };
 802
 803 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 804                 sizeof(rte_ixgbevf_stats_strings[0]))
 805
 806 /**
 807  * Atomically reads the link status information from global
 808  * structure rte_eth_dev.
 809  *
 810  * @param dev
 811  *   - Pointer to the structure rte_eth_dev to read from.
 812  *   - Pointer to the buffer to be saved with the link status.
 813  *
 814  * @return
 815  *   - On success, zero.
 816  *   - On failure, negative value.
 817  */
 818 static inline int
 819 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 820                                 struct rte_eth_link *link)
 821 {
 822         struct rte_eth_link *dst = link;
 823         struct rte_eth_link *src = &(dev->data->dev_link);
 824
 825         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 826                                         *(uint64_t *)src) == 0)
 827                 return -1;
 828
 829         return 0;
 830 }
 831
 832 /**
 833  * Atomically writes the link status information into global
 834  * structure rte_eth_dev.
 835  *
 836  * @param dev
 837  *   - Pointer to the structure rte_eth_dev to read from.
 838  *   - Pointer to the buffer to be saved with the link status.
 839  *
 840  * @return
 841  *   - On success, zero.
 842  *   - On failure, negative value.
 843  */
 844 static inline int
 845 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 846                                 struct rte_eth_link *link)
 847 {
 848         struct rte_eth_link *dst = &(dev->data->dev_link);
 849         struct rte_eth_link *src = link;
 850
 851         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 852                                         *(uint64_t *)src) == 0)
 853                 return -1;
 854
 855         return 0;
 856 }
 857
 858 /*
 859  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 860  */
 861 static inline int
 862 ixgbe_is_sfp(struct ixgbe_hw *hw)
 863 {
 864         switch (hw->phy.type) {
 865         case ixgbe_phy_sfp_avago:
 866         case ixgbe_phy_sfp_ftl:
 867         case ixgbe_phy_sfp_intel:
 868         case ixgbe_phy_sfp_unknown:
 869         case ixgbe_phy_sfp_passive_tyco:
 870         case ixgbe_phy_sfp_passive_unknown:
 871                 return 1;
 872         default:
 873                 return 0;
 874         }
 875 }
 876
 877 static inline int32_t
 878 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 879 {
 880         uint32_t ctrl_ext;
 881         int32_t status;
 882
 883         status = ixgbe_reset_hw(hw);
 884
 885         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 886         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 887         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 888         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 889         IXGBE_WRITE_FLUSH(hw);
 890
 891         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 892                 status = IXGBE_SUCCESS;
 893         return status;
 894 }
 895
 896 static inline void
 897 ixgbe_enable_intr(struct rte_eth_dev *dev)
 898 {
 899         struct ixgbe_interrupt *intr =
 900                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 901         struct ixgbe_hw *hw =
 902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 903
 904         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 905         IXGBE_WRITE_FLUSH(hw);
 906 }
 907
 908 /*
 909  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 910  */
 911 static void
 912 ixgbe_disable_intr(struct ixgbe_hw *hw)
 913 {
 914         PMD_INIT_FUNC_TRACE();
 915
 916         if (hw->mac.type == ixgbe_mac_82598EB) {
 917                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 918         } else {
 919                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 920                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 921                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 922         }
 923         IXGBE_WRITE_FLUSH(hw);
 924 }
 925
 926 /*
 927  * This function resets queue statistics mapping registers.
 928  * From Niantic datasheet, Initialization of Statistics section:
 929  * "...if software requires the queue counters, the RQSMR and TQSM registers
 930  * must be re-programmed following a device reset.
 931  */
 932 static void
 933 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 934 {
 935         uint32_t i;
 936
 937         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 938                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 939                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 940         }
 941 }
 942
 943
 944 static int
 945 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 946                                   uint16_t queue_id,
 947                                   uint8_t stat_idx,
 948                                   uint8_t is_rx)
 949 {
 950 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 951 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 952 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 953
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 955         struct ixgbe_stat_mapping_registers *stat_mappings =
 956                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 957         uint32_t qsmr_mask = 0;
 958         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 959         uint32_t q_map;
 960         uint8_t n, offset;
 961
 962         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 963                 (hw->mac.type != ixgbe_mac_X540) &&
 964                 (hw->mac.type != ixgbe_mac_X550) &&
 965                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 966                 (hw->mac.type != ixgbe_mac_X550EM_a))
 967                 return -ENOSYS;
 968
 969         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 970                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 971                      queue_id, stat_idx);
 972
 973         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 974         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 975                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 976                 return -EIO;
 977         }
 978         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 979
 980         /* Now clear any previous stat_idx set */
 981         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 982         if (!is_rx)
 983                 stat_mappings->tqsm[n] &= ~clearing_mask;
 984         else
 985                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 986
 987         q_map = (uint32_t)stat_idx;
 988         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 989         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 990         if (!is_rx)
 991                 stat_mappings->tqsm[n] |= qsmr_mask;
 992         else
 993                 stat_mappings->rqsmr[n] |= qsmr_mask;
 994
 995         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 996                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 997                      queue_id, stat_idx);
 998         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 999                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1000
1001         /* Now write the mapping in the appropriate register */
1002         if (is_rx) {
1003                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1004                              stat_mappings->rqsmr[n], n);
1005                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1006         } else {
1007                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1008                              stat_mappings->tqsm[n], n);
1009                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1010         }
1011         return 0;
1012 }
1013
1014 static void
1015 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1016 {
1017         struct ixgbe_stat_mapping_registers *stat_mappings =
1018                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         int i;
1021
1022         /* write whatever was in stat mapping table to the NIC */
1023         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1024                 /* rx */
1025                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1026
1027                 /* tx */
1028                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1029         }
1030 }
1031
1032 static void
1033 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1034 {
1035         uint8_t i;
1036         struct ixgbe_dcb_tc_config *tc;
1037         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1038
1039         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1040         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1041         for (i = 0; i < dcb_max_tc; i++) {
1042                 tc = &dcb_config->tc_config[i];
1043                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1044                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1045                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1046                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1047                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1048                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1049                 tc->pfc = ixgbe_dcb_pfc_disabled;
1050         }
1051
1052         /* Initialize default user to priority mapping, UPx->TC0 */
1053         tc = &dcb_config->tc_config[0];
1054         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1055         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1056         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1057                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1058                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1059         }
1060         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1061         dcb_config->pfc_mode_enable = false;
1062         dcb_config->vt_mode = true;
1063         dcb_config->round_robin_enable = false;
1064         /* support all DCB capabilities in 82599 */
1065         dcb_config->support.capabilities = 0xFF;
1066
1067         /*we only support 4 Tcs for X540, X550 */
1068         if (hw->mac.type == ixgbe_mac_X540 ||
1069                 hw->mac.type == ixgbe_mac_X550 ||
1070                 hw->mac.type == ixgbe_mac_X550EM_x ||
1071                 hw->mac.type == ixgbe_mac_X550EM_a) {
1072                 dcb_config->num_tcs.pg_tcs = 4;
1073                 dcb_config->num_tcs.pfc_tcs = 4;
1074         }
1075 }
1076
1077 /*
1078  * Ensure that all locks are released before first NVM or PHY access
1079  */
1080 static void
1081 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1082 {
1083         uint16_t mask;
1084
1085         /*
1086          * Phy lock should not fail in this early stage. If this is the case,
1087          * it is due to an improper exit of the application.
1088          * So force the release of the faulty lock. Release of common lock
1089          * is done automatically by swfw_sync function.
1090          */
1091         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1092         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1093                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1094         }
1095         ixgbe_release_swfw_semaphore(hw, mask);
1096
1097         /*
1098          * These ones are more tricky since they are common to all ports; but
1099          * swfw_sync retries last long enough (1s) to be almost sure that if
1100          * lock can not be taken it is due to an improper lock of the
1101          * semaphore.
1102          */
1103         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1104         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1105                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1106         }
1107         ixgbe_release_swfw_semaphore(hw, mask);
1108 }
1109
1110 /*
1111  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1112  * It returns 0 on success.
1113  */
1114 static int
1115 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1116 {
1117         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1118         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1119         struct ixgbe_hw *hw =
1120                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1121         struct ixgbe_vfta *shadow_vfta =
1122                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1123         struct ixgbe_hwstrip *hwstrip =
1124                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1125         struct ixgbe_dcb_config *dcb_config =
1126                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1127         struct ixgbe_filter_info *filter_info =
1128                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1129         struct ixgbe_bw_conf *bw_conf =
1130                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1131         uint32_t ctrl_ext;
1132         uint16_t csum;
1133         int diag, i;
1134
1135         PMD_INIT_FUNC_TRACE();
1136
1137         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1138         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1139         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1140         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1141
1142         /*
1143          * For secondary processes, we don't initialise any further as primary
1144          * has already done this work. Only check we don't need a different
1145          * RX and TX function.
1146          */
1147         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1148                 struct ixgbe_tx_queue *txq;
1149                 /* TX queue function in primary, set by last queue initialized
1150                  * Tx queue may not initialized by primary process
1151                  */
1152                 if (eth_dev->data->tx_queues) {
1153                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1154                         ixgbe_set_tx_function(eth_dev, txq);
1155                 } else {
1156                         /* Use default TX function if we get here */
1157                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1158                                      "Using default TX function.");
1159                 }
1160
1161                 ixgbe_set_rx_function(eth_dev);
1162
1163                 return 0;
1164         }
1165
1166         rte_eth_copy_pci_info(eth_dev, pci_dev);
1167         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1168
1169         /* Vendor and Device ID need to be set before init of shared code */
1170         hw->device_id = pci_dev->id.device_id;
1171         hw->vendor_id = pci_dev->id.vendor_id;
1172         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1173         hw->allow_unsupported_sfp = 1;
1174
1175         /* Initialize the shared code (base driver) */
1176 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1177         diag = ixgbe_bypass_init_shared_code(hw);
1178 #else
1179         diag = ixgbe_init_shared_code(hw);
1180 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1181
1182         if (diag != IXGBE_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1184                 return -EIO;
1185         }
1186
1187         /* pick up the PCI bus settings for reporting later */
1188         ixgbe_get_bus_info(hw);
1189
1190         /* Unlock any pending hardware semaphore */
1191         ixgbe_swfw_lock_reset(hw);
1192
1193         /* Initialize DCB configuration*/
1194         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1195         ixgbe_dcb_init(hw, dcb_config);
1196         /* Get Hardware Flow Control setting */
1197         hw->fc.requested_mode = ixgbe_fc_full;
1198         hw->fc.current_mode = ixgbe_fc_full;
1199         hw->fc.pause_time = IXGBE_FC_PAUSE;
1200         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1201                 hw->fc.low_water[i] = IXGBE_FC_LO;
1202                 hw->fc.high_water[i] = IXGBE_FC_HI;
1203         }
1204         hw->fc.send_xon = 1;
1205
1206         /* Make sure we have a good EEPROM before we read from it */
1207         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1208         if (diag != IXGBE_SUCCESS) {
1209                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1210                 return -EIO;
1211         }
1212
1213 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1214         diag = ixgbe_bypass_init_hw(hw);
1215 #else
1216         diag = ixgbe_init_hw(hw);
1217 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1218
1219         /*
1220          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1221          * is called too soon after the kernel driver unbinding/binding occurs.
1222          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1223          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1224          * also called. See ixgbe_identify_phy_82599(). The reason for the
1225          * failure is not known, and only occuts when virtualisation features
1226          * are disabled in the bios. A delay of 100ms  was found to be enough by
1227          * trial-and-error, and is doubled to be safe.
1228          */
1229         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1230                 rte_delay_ms(200);
1231                 diag = ixgbe_init_hw(hw);
1232         }
1233
1234         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1235                 diag = IXGBE_SUCCESS;
1236
1237         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1238                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1239                              "LOM.  Please be aware there may be issues associated "
1240                              "with your hardware.");
1241                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1242                              "please contact your Intel or hardware representative "
1243                              "who provided you with this hardware.");
1244         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1245                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1246         if (diag) {
1247                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1248                 return -EIO;
1249         }
1250
1251         /* Reset the hw statistics */
1252         ixgbe_dev_stats_reset(eth_dev);
1253
1254         /* disable interrupt */
1255         ixgbe_disable_intr(hw);
1256
1257         /* reset mappings for queue statistics hw counters*/
1258         ixgbe_reset_qstat_mappings(hw);
1259
1260         /* Allocate memory for storing MAC addresses */
1261         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1262                                                hw->mac.num_rar_entries, 0);
1263         if (eth_dev->data->mac_addrs == NULL) {
1264                 PMD_INIT_LOG(ERR,
1265                              "Failed to allocate %u bytes needed to store "
1266                              "MAC addresses",
1267                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1268                 return -ENOMEM;
1269         }
1270         /* Copy the permanent MAC address */
1271         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1272                         &eth_dev->data->mac_addrs[0]);
1273
1274         /* Allocate memory for storing hash filter MAC addresses */
1275         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1276                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1277         if (eth_dev->data->hash_mac_addrs == NULL) {
1278                 PMD_INIT_LOG(ERR,
1279                              "Failed to allocate %d bytes needed to store MAC addresses",
1280                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1281                 return -ENOMEM;
1282         }
1283
1284         /* initialize the vfta */
1285         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1286
1287         /* initialize the hw strip bitmap*/
1288         memset(hwstrip, 0, sizeof(*hwstrip));
1289
1290         /* initialize PF if max_vfs not zero */
1291         ixgbe_pf_host_init(eth_dev);
1292
1293         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1294         /* let hardware know driver is loaded */
1295         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1296         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1297         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1298         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1299         IXGBE_WRITE_FLUSH(hw);
1300
1301         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1302                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1303                              (int) hw->mac.type, (int) hw->phy.type,
1304                              (int) hw->phy.sfp_type);
1305         else
1306                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1307                              (int) hw->mac.type, (int) hw->phy.type);
1308
1309         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1310                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1311                      pci_dev->id.device_id);
1312
1313         rte_intr_callback_register(intr_handle,
1314                                    ixgbe_dev_interrupt_handler, eth_dev);
1315
1316         /* enable uio/vfio intr/eventfd mapping */
1317         rte_intr_enable(intr_handle);
1318
1319         /* enable support intr */
1320         ixgbe_enable_intr(eth_dev);
1321
1322         /* initialize filter info */
1323         memset(filter_info, 0,
1324                sizeof(struct ixgbe_filter_info));
1325
1326         /* initialize 5tuple filter list */
1327         TAILQ_INIT(&filter_info->fivetuple_list);
1328
1329         /* initialize flow director filter list & hash */
1330         ixgbe_fdir_filter_init(eth_dev);
1331
1332         /* initialize l2 tunnel filter list & hash */
1333         ixgbe_l2_tn_filter_init(eth_dev);
1334
1335         TAILQ_INIT(&filter_ntuple_list);
1336         TAILQ_INIT(&filter_ethertype_list);
1337         TAILQ_INIT(&filter_syn_list);
1338         TAILQ_INIT(&filter_fdir_list);
1339         TAILQ_INIT(&filter_l2_tunnel_list);
1340         TAILQ_INIT(&ixgbe_flow_list);
1341
1342         /* initialize bandwidth configuration info */
1343         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1344
1345         /* initialize Traffic Manager configuration */
1346         ixgbe_tm_conf_init(eth_dev);
1347
1348         return 0;
1349 }
1350
1351 static int
1352 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1353 {
1354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1356         struct ixgbe_hw *hw;
1357
1358         PMD_INIT_FUNC_TRACE();
1359
1360         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1361                 return -EPERM;
1362
1363         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1364
1365         if (hw->adapter_stopped == 0)
1366                 ixgbe_dev_close(eth_dev);
1367
1368         eth_dev->dev_ops = NULL;
1369         eth_dev->rx_pkt_burst = NULL;
1370         eth_dev->tx_pkt_burst = NULL;
1371
1372         /* Unlock any pending hardware semaphore */
1373         ixgbe_swfw_lock_reset(hw);
1374
1375         /* disable uio intr before callback unregister */
1376         rte_intr_disable(intr_handle);
1377         rte_intr_callback_unregister(intr_handle,
1378                                      ixgbe_dev_interrupt_handler, eth_dev);
1379
1380         /* uninitialize PF if max_vfs not zero */
1381         ixgbe_pf_host_uninit(eth_dev);
1382
1383         rte_free(eth_dev->data->mac_addrs);
1384         eth_dev->data->mac_addrs = NULL;
1385
1386         rte_free(eth_dev->data->hash_mac_addrs);
1387         eth_dev->data->hash_mac_addrs = NULL;
1388
1389         /* remove all the fdir filters & hash */
1390         ixgbe_fdir_filter_uninit(eth_dev);
1391
1392         /* remove all the L2 tunnel filters & hash */
1393         ixgbe_l2_tn_filter_uninit(eth_dev);
1394
1395         /* Remove all ntuple filters of the device */
1396         ixgbe_ntuple_filter_uninit(eth_dev);
1397
1398         /* clear all the filters list */
1399         ixgbe_filterlist_flush();
1400
1401         /* Remove all Traffic Manager configuration */
1402         ixgbe_tm_conf_uninit(eth_dev);
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->device->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->device->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785         .probe = eth_ixgbe_pci_probe,
1786         .remove = eth_ixgbe_pci_remove,
1787 };
1788
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790         struct rte_pci_device *pci_dev)
1791 {
1792         return rte_eth_dev_pci_generic_probe(pci_dev,
1793                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1794 }
1795
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1799 }
1800
1801 /*
1802  * virtual function driver struct
1803  */
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805         .id_table = pci_id_ixgbevf_map,
1806         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807         .probe = eth_ixgbevf_pci_probe,
1808         .remove = eth_ixgbevf_pci_remove,
1809 };
1810
1811 static int
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct ixgbe_vfta *shadow_vfta =
1817                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1818         uint32_t vfta;
1819         uint32_t vid_idx;
1820         uint32_t vid_bit;
1821
1822         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1825         if (on)
1826                 vfta |= vid_bit;
1827         else
1828                 vfta &= ~vid_bit;
1829         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1830
1831         /* update local VFTA copy */
1832         shadow_vfta->vfta[vid_idx] = vfta;
1833
1834         return 0;
1835 }
1836
1837 static void
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1839 {
1840         if (on)
1841                 ixgbe_vlan_hw_strip_enable(dev, queue);
1842         else
1843                 ixgbe_vlan_hw_strip_disable(dev, queue);
1844 }
1845
1846 static int
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848                     enum rte_vlan_type vlan_type,
1849                     uint16_t tpid)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         int ret = 0;
1854         uint32_t reg;
1855         uint32_t qinq;
1856
1857         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858         qinq &= IXGBE_DMATXCTL_GDV;
1859
1860         switch (vlan_type) {
1861         case ETH_VLAN_TYPE_INNER:
1862                 if (qinq) {
1863                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870                 } else {
1871                         ret = -ENOTSUP;
1872                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1873                                     " by single VLAN");
1874                 }
1875                 break;
1876         case ETH_VLAN_TYPE_OUTER:
1877                 if (qinq) {
1878                         /* Only the high 16-bits is valid */
1879                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880                                         IXGBE_EXVET_VET_EXT_SHIFT);
1881                 } else {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 }
1890
1891                 break;
1892         default:
1893                 ret = -EINVAL;
1894                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1895                 break;
1896         }
1897
1898         return ret;
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         uint32_t vlnctrl;
1907
1908         PMD_INIT_FUNC_TRACE();
1909
1910         /* Filter Table Disable */
1911         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ixgbe_vfta *shadow_vfta =
1923                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925         uint16_t i;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Enable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932         vlnctrl |= IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935
1936         /* write whatever is in local vfta copy */
1937         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1943 {
1944         struct ixgbe_hwstrip *hwstrip =
1945                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946         struct ixgbe_rx_queue *rxq;
1947
1948         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1949                 return;
1950
1951         if (on)
1952                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1953         else
1954                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1955
1956         if (queue >= dev->data->nb_rx_queues)
1957                 return;
1958
1959         rxq = dev->data->rx_queues[queue];
1960
1961         if (on)
1962                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1963         else
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level support */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl &= ~IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level supported */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl |= IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2013 }
2014
2015 void
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021         uint16_t i;
2022         struct ixgbe_rx_queue *rxq;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028                 ctrl &= ~IXGBE_VLNCTRL_VME;
2029                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2030         } else {
2031                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033                         rxq = dev->data->rx_queues[i];
2034                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035                         ctrl &= ~IXGBE_RXDCTL_VME;
2036                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2037
2038                         /* record those setting for HW strip per queue */
2039                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2040                 }
2041         }
2042 }
2043
2044 void
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050         uint16_t i;
2051         struct ixgbe_rx_queue *rxq;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (hw->mac.type == ixgbe_mac_82598EB) {
2056                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057                 ctrl |= IXGBE_VLNCTRL_VME;
2058                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2059         } else {
2060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062                         rxq = dev->data->rx_queues[i];
2063                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064                         ctrl |= IXGBE_RXDCTL_VME;
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2069                 }
2070         }
2071 }
2072
2073 static void
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2075 {
2076         struct ixgbe_hw *hw =
2077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint32_t ctrl;
2079
2080         PMD_INIT_FUNC_TRACE();
2081
2082         /* DMATXCTRL: Geric Double VLAN Disable */
2083         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084         ctrl &= ~IXGBE_DMATXCTL_GDV;
2085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2086
2087         /* CTRL_EXT: Global Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089         ctrl &= ~IXGBE_EXTENDED_VLAN;
2090         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2091
2092 }
2093
2094 static void
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t ctrl;
2100
2101         PMD_INIT_FUNC_TRACE();
2102
2103         /* DMATXCTRL: Geric Double VLAN Enable */
2104         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105         ctrl |= IXGBE_DMATXCTL_GDV;
2106         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2107
2108         /* CTRL_EXT: Global Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110         ctrl |= IXGBE_EXTENDED_VLAN;
2111         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2112
2113         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114         if (hw->mac.type == ixgbe_mac_X550 ||
2115             hw->mac.type == ixgbe_mac_X550EM_x ||
2116             hw->mac.type == ixgbe_mac_X550EM_a) {
2117                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2120         }
2121
2122         /*
2123          * VET EXT field in the EXVET register = 0x8100 by default
2124          * So no need to change. Same to VT field of DMATXCTL register
2125          */
2126 }
2127
2128 static void
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2130 {
2131         if (mask & ETH_VLAN_STRIP_MASK) {
2132                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133                         ixgbe_vlan_hw_strip_enable_all(dev);
2134                 else
2135                         ixgbe_vlan_hw_strip_disable_all(dev);
2136         }
2137
2138         if (mask & ETH_VLAN_FILTER_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140                         ixgbe_vlan_hw_filter_enable(dev);
2141                 else
2142                         ixgbe_vlan_hw_filter_disable(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_EXTEND_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147                         ixgbe_vlan_hw_extend_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_extend_disable(dev);
2150         }
2151 }
2152
2153 static void
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw =
2157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160
2161         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 }
2164
2165 static int
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2167 {
2168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169
2170         switch (nb_rx_q) {
2171         case 1:
2172         case 2:
2173                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2174                 break;
2175         case 4:
2176                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2190 {
2191         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2195
2196         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197                 /* check multi-queue mode */
2198                 switch (dev_conf->rxmode.mq_mode) {
2199                 case ETH_MQ_RX_VMDQ_DCB:
2200                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2201                         break;
2202                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204                         PMD_INIT_LOG(ERR, "SRIOV active,"
2205                                         " unsupported mq_mode rx %d.",
2206                                         dev_conf->rxmode.mq_mode);
2207                         return -EINVAL;
2208                 case ETH_MQ_RX_RSS:
2209                 case ETH_MQ_RX_VMDQ_RSS:
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                                 " invalid queue number"
2215                                                 " for VMDQ RSS, allowed"
2216                                                 " value are 1, 2 or 4.");
2217                                         return -EINVAL;
2218                                 }
2219                         break;
2220                 case ETH_MQ_RX_VMDQ_ONLY:
2221                 case ETH_MQ_RX_NONE:
2222                         /* if nothing mq mode configure, use default scheme */
2223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2226                         break;
2227                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228                         /* SRIOV only works in VMDq enable mode */
2229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2230                                         " wrong mq_mode rx %d.",
2231                                         dev_conf->rxmode.mq_mode);
2232                         return -EINVAL;
2233                 }
2234
2235                 switch (dev_conf->txmode.mq_mode) {
2236                 case ETH_MQ_TX_VMDQ_DCB:
2237                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2239                         break;
2240                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2242                         break;
2243                 }
2244
2245                 /* check valid queue number */
2246                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2250                                         " must be less than or equal to %d.",
2251                                         nb_rx_q, nb_tx_q,
2252                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2253                         return -EINVAL;
2254                 }
2255         } else {
2256                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2258                                           " not supported.");
2259                         return -EINVAL;
2260                 }
2261                 /* check configuration for vmdb+dcb mode */
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263                         const struct rte_eth_vmdq_dcb_conf *conf;
2264
2265                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2268                                 return -EINVAL;
2269                         }
2270                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272                                conf->nb_queue_pools == ETH_32_POOLS)) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274                                                 " nb_queue_pools must be %d or %d.",
2275                                                 ETH_16_POOLS, ETH_32_POOLS);
2276                                 return -EINVAL;
2277                         }
2278                 }
2279                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2281
2282                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289                                conf->nb_queue_pools == ETH_32_POOLS)) {
2290                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291                                                 " nb_queue_pools != %d and"
2292                                                 " nb_queue_pools != %d.",
2293                                                 ETH_16_POOLS, ETH_32_POOLS);
2294                                 return -EINVAL;
2295                         }
2296                 }
2297
2298                 /* For DCB mode check our configuration before we go further */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300                         const struct rte_eth_dcb_rx_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304                                                  IXGBE_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322                                                  IXGBE_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326                         if (!(conf->nb_tcs == ETH_4_TCS ||
2327                                conf->nb_tcs == ETH_8_TCS)) {
2328                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329                                                 " and nb_tcs != %d.",
2330                                                 ETH_4_TCS, ETH_8_TCS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /*
2336                  * When DCB/VT is off, maximum number of queues changes,
2337                  * except for 82598EB, which remains constant.
2338                  */
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340                                 hw->mac.type != ixgbe_mac_82598EB) {
2341                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2342                                 PMD_INIT_LOG(ERR,
2343                                              "Neither VT nor DCB are enabled, "
2344                                              "nb_tx_q > %d.",
2345                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349         }
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2355 {
2356         struct ixgbe_interrupt *intr =
2357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358         struct ixgbe_adapter *adapter =
2359                 (struct ixgbe_adapter *)dev->data->dev_private;
2360         int ret;
2361
2362         PMD_INIT_FUNC_TRACE();
2363         /* multipe queue mode checking */
2364         ret  = ixgbe_check_mq_mode(dev);
2365         if (ret != 0) {
2366                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2367                             ret);
2368                 return ret;
2369         }
2370
2371         /* set flag to update link status after init */
2372         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2373
2374         /*
2375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376          * allocation or vector Rx preconditions we will reset it.
2377          */
2378         adapter->rx_bulk_alloc_allowed = true;
2379         adapter->rx_vec_allowed = true;
2380
2381         return 0;
2382 }
2383
2384 static void
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ixgbe_hw *hw =
2388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         uint32_t gpie;
2392
2393         /* only set up it on X550EM_X */
2394         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2400         }
2401 }
2402
2403 int
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405                         uint16_t tx_rate, uint64_t q_msk)
2406 {
2407         struct ixgbe_hw *hw;
2408         struct ixgbe_vf_info *vfinfo;
2409         struct rte_eth_link link;
2410         uint8_t  nb_q_per_pool;
2411         uint32_t queue_stride;
2412         uint32_t queue_idx, idx = 0, vf_idx;
2413         uint32_t queue_end;
2414         uint16_t total_rate = 0;
2415         struct rte_pci_device *pci_dev;
2416
2417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418         rte_eth_link_get_nowait(dev->data->port_id, &link);
2419
2420         if (vf >= pci_dev->max_vfs)
2421                 return -EINVAL;
2422
2423         if (tx_rate > link.link_speed)
2424                 return -EINVAL;
2425
2426         if (q_msk == 0)
2427                 return 0;
2428
2429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433         queue_idx = vf * queue_stride;
2434         queue_end = queue_idx + nb_q_per_pool - 1;
2435         if (queue_end >= hw->mac.max_tx_queues)
2436                 return -EINVAL;
2437
2438         if (vfinfo) {
2439                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2440                         if (vf_idx == vf)
2441                                 continue;
2442                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2443                                 idx++)
2444                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2445                 }
2446         } else {
2447                 return -EINVAL;
2448         }
2449
2450         /* Store tx_rate for this vf. */
2451         for (idx = 0; idx < nb_q_per_pool; idx++) {
2452                 if (((uint64_t)0x1 << idx) & q_msk) {
2453                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2455                         total_rate += tx_rate;
2456                 }
2457         }
2458
2459         if (total_rate > dev->data->dev_link.link_speed) {
2460                 /* Reset stored TX rate of the VF if it causes exceed
2461                  * link speed.
2462                  */
2463                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2464                 return -EINVAL;
2465         }
2466
2467         /* Set RTTBCNRC of each queue/pool for vf X  */
2468         for (; queue_idx <= queue_end; queue_idx++) {
2469                 if (0x1 & q_msk)
2470                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2471                 q_msk = q_msk >> 1;
2472         }
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Configure device link speed and setup link.
2479  * It returns 0 on success.
2480  */
2481 static int
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2483 {
2484         struct ixgbe_hw *hw =
2485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct ixgbe_vf_info *vfinfo =
2487                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490         uint32_t intr_vector = 0;
2491         int err, link_up = 0, negotiate = 0;
2492         uint32_t speed = 0;
2493         int mask = 0;
2494         int status;
2495         uint16_t vf, idx;
2496         uint32_t *link_speeds;
2497         struct ixgbe_tm_conf *tm_conf =
2498                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2499
2500         PMD_INIT_FUNC_TRACE();
2501
2502         /* IXGBE devices don't support:
2503         *    - half duplex (checked afterwards for valid speeds)
2504         *    - fixed speed: TODO implement
2505         */
2506         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2507                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2508                              dev->data->port_id);
2509                 return -EINVAL;
2510         }
2511
2512         /* disable uio/vfio intr/eventfd mapping */
2513         rte_intr_disable(intr_handle);
2514
2515         /* stop adapter */
2516         hw->adapter_stopped = 0;
2517         ixgbe_stop_adapter(hw);
2518
2519         /* reinitialize adapter
2520          * this calls reset and start
2521          */
2522         status = ixgbe_pf_reset_hw(hw);
2523         if (status != 0)
2524                 return -1;
2525         hw->mac.ops.start_hw(hw);
2526         hw->mac.get_link_status = true;
2527
2528         /* configure PF module if SRIOV enabled */
2529         ixgbe_pf_host_configure(dev);
2530
2531         ixgbe_dev_phy_intr_setup(dev);
2532
2533         /* check and configure queue intr-vector mapping */
2534         if ((rte_intr_cap_multiple(intr_handle) ||
2535              !RTE_ETH_DEV_SRIOV(dev).active) &&
2536             dev->data->dev_conf.intr_conf.rxq != 0) {
2537                 intr_vector = dev->data->nb_rx_queues;
2538                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2539                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2540                                         IXGBE_MAX_INTR_QUEUE_NUM);
2541                         return -ENOTSUP;
2542                 }
2543                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2544                         return -1;
2545         }
2546
2547         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2548                 intr_handle->intr_vec =
2549                         rte_zmalloc("intr_vec",
2550                                     dev->data->nb_rx_queues * sizeof(int), 0);
2551                 if (intr_handle->intr_vec == NULL) {
2552                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2553                                      " intr_vec", dev->data->nb_rx_queues);
2554                         return -ENOMEM;
2555                 }
2556         }
2557
2558         /* confiugre msix for sleep until rx interrupt */
2559         ixgbe_configure_msix(dev);
2560
2561         /* initialize transmission unit */
2562         ixgbe_dev_tx_init(dev);
2563
2564         /* This can fail when allocating mbufs for descriptor rings */
2565         err = ixgbe_dev_rx_init(dev);
2566         if (err) {
2567                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2568                 goto error;
2569         }
2570
2571     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2572                 ETH_VLAN_EXTEND_MASK;
2573         ixgbe_vlan_offload_set(dev, mask);
2574
2575         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2576                 /* Enable vlan filtering for VMDq */
2577                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2578         }
2579
2580         /* Configure DCB hw */
2581         ixgbe_configure_dcb(dev);
2582
2583         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2584                 err = ixgbe_fdir_configure(dev);
2585                 if (err)
2586                         goto error;
2587         }
2588
2589         /* Restore vf rate limit */
2590         if (vfinfo != NULL) {
2591                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2592                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2593                                 if (vfinfo[vf].tx_rate[idx] != 0)
2594                                         ixgbe_set_vf_rate_limit(
2595                                                 dev, vf,
2596                                                 vfinfo[vf].tx_rate[idx],
2597                                                 1 << idx);
2598         }
2599
2600         ixgbe_restore_statistics_mapping(dev);
2601
2602         err = ixgbe_dev_rxtx_start(dev);
2603         if (err < 0) {
2604                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2605                 goto error;
2606         }
2607
2608         /* Skip link setup if loopback mode is enabled for 82599. */
2609         if (hw->mac.type == ixgbe_mac_82599EB &&
2610                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2611                 goto skip_link_setup;
2612
2613         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2614                 err = hw->mac.ops.setup_sfp(hw);
2615                 if (err)
2616                         goto error;
2617         }
2618
2619         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2620                 /* Turn on the copper */
2621                 ixgbe_set_phy_power(hw, true);
2622         } else {
2623                 /* Turn on the laser */
2624                 ixgbe_enable_tx_laser(hw);
2625         }
2626
2627         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2628         if (err)
2629                 goto error;
2630         dev->data->dev_link.link_status = link_up;
2631
2632         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2633         if (err)
2634                 goto error;
2635
2636         link_speeds = &dev->data->dev_conf.link_speeds;
2637         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2638                         ETH_LINK_SPEED_10G)) {
2639                 PMD_INIT_LOG(ERR, "Invalid link setting");
2640                 goto error;
2641         }
2642
2643         speed = 0x0;
2644         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2645                 switch (hw->mac.type) {
2646                 case ixgbe_mac_82598EB:
2647                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2648                         break;
2649                 case ixgbe_mac_82599EB:
2650                 case ixgbe_mac_X540:
2651                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2652                         break;
2653                 case ixgbe_mac_X550:
2654                 case ixgbe_mac_X550EM_x:
2655                 case ixgbe_mac_X550EM_a:
2656                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2657                         break;
2658                 default:
2659                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2660                 }
2661         } else {
2662                 if (*link_speeds & ETH_LINK_SPEED_10G)
2663                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2664                 if (*link_speeds & ETH_LINK_SPEED_1G)
2665                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2666                 if (*link_speeds & ETH_LINK_SPEED_100M)
2667                         speed |= IXGBE_LINK_SPEED_100_FULL;
2668         }
2669
2670         err = ixgbe_setup_link(hw, speed, link_up);
2671         if (err)
2672                 goto error;
2673
2674 skip_link_setup:
2675
2676         if (rte_intr_allow_others(intr_handle)) {
2677                 /* check if lsc interrupt is enabled */
2678                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2679                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2680                 else
2681                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2682                 ixgbe_dev_macsec_interrupt_setup(dev);
2683         } else {
2684                 rte_intr_callback_unregister(intr_handle,
2685                                              ixgbe_dev_interrupt_handler, dev);
2686                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2687                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2688                                      " no intr multiplex");
2689         }
2690
2691         /* check if rxq interrupt is enabled */
2692         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2693             rte_intr_dp_is_en(intr_handle))
2694                 ixgbe_dev_rxq_interrupt_setup(dev);
2695
2696         /* enable uio/vfio intr/eventfd mapping */
2697         rte_intr_enable(intr_handle);
2698
2699         /* resume enabled intr since hw reset */
2700         ixgbe_enable_intr(dev);
2701         ixgbe_l2_tunnel_conf(dev);
2702         ixgbe_filter_restore(dev);
2703
2704         if (tm_conf->root && !tm_conf->committed)
2705                 PMD_DRV_LOG(WARNING,
2706                             "please call hierarchy_commit() "
2707                             "before starting the port");
2708
2709         return 0;
2710
2711 error:
2712         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2713         ixgbe_dev_clear_queues(dev);
2714         return -EIO;
2715 }
2716
2717 /*
2718  * Stop device: disable rx and tx functions to allow for reconfiguring.
2719  */
2720 static void
2721 ixgbe_dev_stop(struct rte_eth_dev *dev)
2722 {
2723         struct rte_eth_link link;
2724         struct ixgbe_hw *hw =
2725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2726         struct ixgbe_vf_info *vfinfo =
2727                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2728         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2729         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2730         int vf;
2731         struct ixgbe_tm_conf *tm_conf =
2732                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2733
2734         PMD_INIT_FUNC_TRACE();
2735
2736         /* disable interrupts */
2737         ixgbe_disable_intr(hw);
2738
2739         /* reset the NIC */
2740         ixgbe_pf_reset_hw(hw);
2741         hw->adapter_stopped = 0;
2742
2743         /* stop adapter */
2744         ixgbe_stop_adapter(hw);
2745
2746         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2747                 vfinfo[vf].clear_to_send = false;
2748
2749         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2750                 /* Turn off the copper */
2751                 ixgbe_set_phy_power(hw, false);
2752         } else {
2753                 /* Turn off the laser */
2754                 ixgbe_disable_tx_laser(hw);
2755         }
2756
2757         ixgbe_dev_clear_queues(dev);
2758
2759         /* Clear stored conf */
2760         dev->data->scattered_rx = 0;
2761         dev->data->lro = 0;
2762
2763         /* Clear recorded link status */
2764         memset(&link, 0, sizeof(link));
2765         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2766
2767         if (!rte_intr_allow_others(intr_handle))
2768                 /* resume to the default handler */
2769                 rte_intr_callback_register(intr_handle,
2770                                            ixgbe_dev_interrupt_handler,
2771                                            (void *)dev);
2772
2773         /* Clean datapath event and queue/vec mapping */
2774         rte_intr_efd_disable(intr_handle);
2775         if (intr_handle->intr_vec != NULL) {
2776                 rte_free(intr_handle->intr_vec);
2777                 intr_handle->intr_vec = NULL;
2778         }
2779
2780         /* reset hierarchy commit */
2781         tm_conf->committed = false;
2782 }
2783
2784 /*
2785  * Set device link up: enable tx.
2786  */
2787 static int
2788 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2789 {
2790         struct ixgbe_hw *hw =
2791                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         if (hw->mac.type == ixgbe_mac_82599EB) {
2793 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2794                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2795                         /* Not suported in bypass mode */
2796                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2797                                      "by device id 0x%x", hw->device_id);
2798                         return -ENOTSUP;
2799                 }
2800 #endif
2801         }
2802
2803         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2804                 /* Turn on the copper */
2805                 ixgbe_set_phy_power(hw, true);
2806         } else {
2807                 /* Turn on the laser */
2808                 ixgbe_enable_tx_laser(hw);
2809         }
2810
2811         return 0;
2812 }
2813
2814 /*
2815  * Set device link down: disable tx.
2816  */
2817 static int
2818 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2819 {
2820         struct ixgbe_hw *hw =
2821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         if (hw->mac.type == ixgbe_mac_82599EB) {
2823 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2824                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2825                         /* Not suported in bypass mode */
2826                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2827                                      "by device id 0x%x", hw->device_id);
2828                         return -ENOTSUP;
2829                 }
2830 #endif
2831         }
2832
2833         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2834                 /* Turn off the copper */
2835                 ixgbe_set_phy_power(hw, false);
2836         } else {
2837                 /* Turn off the laser */
2838                 ixgbe_disable_tx_laser(hw);
2839         }
2840
2841         return 0;
2842 }
2843
2844 /*
2845  * Reest and stop device.
2846  */
2847 static void
2848 ixgbe_dev_close(struct rte_eth_dev *dev)
2849 {
2850         struct ixgbe_hw *hw =
2851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852
2853         PMD_INIT_FUNC_TRACE();
2854
2855         ixgbe_pf_reset_hw(hw);
2856
2857         ixgbe_dev_stop(dev);
2858         hw->adapter_stopped = 1;
2859
2860         ixgbe_dev_free_queues(dev);
2861
2862         ixgbe_disable_pcie_master(hw);
2863
2864         /* reprogram the RAR[0] in case user changed it. */
2865         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2866 }
2867
2868 static void
2869 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2870                            struct ixgbe_hw_stats *hw_stats,
2871                            struct ixgbe_macsec_stats *macsec_stats,
2872                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2873                            uint64_t *total_qprc, uint64_t *total_qprdc)
2874 {
2875         uint32_t bprc, lxon, lxoff, total;
2876         uint32_t delta_gprc = 0;
2877         unsigned i;
2878         /* Workaround for RX byte count not including CRC bytes when CRC
2879          * strip is enabled. CRC bytes are removed from counters when crc_strip
2880          * is disabled.
2881          */
2882         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2883                         IXGBE_HLREG0_RXCRCSTRP);
2884
2885         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2886         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2887         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2888         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2889
2890         for (i = 0; i < 8; i++) {
2891                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2892
2893                 /* global total per queue */
2894                 hw_stats->mpc[i] += mp;
2895                 /* Running comprehensive total for stats display */
2896                 *total_missed_rx += hw_stats->mpc[i];
2897                 if (hw->mac.type == ixgbe_mac_82598EB) {
2898                         hw_stats->rnbc[i] +=
2899                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2900                         hw_stats->pxonrxc[i] +=
2901                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2902                         hw_stats->pxoffrxc[i] +=
2903                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2904                 } else {
2905                         hw_stats->pxonrxc[i] +=
2906                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2907                         hw_stats->pxoffrxc[i] +=
2908                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2909                         hw_stats->pxon2offc[i] +=
2910                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2911                 }
2912                 hw_stats->pxontxc[i] +=
2913                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2914                 hw_stats->pxofftxc[i] +=
2915                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2916         }
2917         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2918                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2919                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2920                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2921
2922                 delta_gprc += delta_qprc;
2923
2924                 hw_stats->qprc[i] += delta_qprc;
2925                 hw_stats->qptc[i] += delta_qptc;
2926
2927                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2928                 hw_stats->qbrc[i] +=
2929                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2930                 if (crc_strip == 0)
2931                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2932
2933                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2934                 hw_stats->qbtc[i] +=
2935                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2936
2937                 hw_stats->qprdc[i] += delta_qprdc;
2938                 *total_qprdc += hw_stats->qprdc[i];
2939
2940                 *total_qprc += hw_stats->qprc[i];
2941                 *total_qbrc += hw_stats->qbrc[i];
2942         }
2943         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2944         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2945         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2946
2947         /*
2948          * An errata states that gprc actually counts good + missed packets:
2949          * Workaround to set gprc to summated queue packet receives
2950          */
2951         hw_stats->gprc = *total_qprc;
2952
2953         if (hw->mac.type != ixgbe_mac_82598EB) {
2954                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2955                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2956                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2957                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2958                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2959                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2960                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2961                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2962         } else {
2963                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2964                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2965                 /* 82598 only has a counter in the high register */
2966                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2967                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2968                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2969         }
2970         uint64_t old_tpr = hw_stats->tpr;
2971
2972         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2973         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2974
2975         if (crc_strip == 0)
2976                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2977
2978         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2979         hw_stats->gptc += delta_gptc;
2980         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2981         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2982
2983         /*
2984          * Workaround: mprc hardware is incorrectly counting
2985          * broadcasts, so for now we subtract those.
2986          */
2987         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2988         hw_stats->bprc += bprc;
2989         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2990         if (hw->mac.type == ixgbe_mac_82598EB)
2991                 hw_stats->mprc -= bprc;
2992
2993         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2994         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2995         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2996         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2997         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2998         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2999
3000         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3001         hw_stats->lxontxc += lxon;
3002         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3003         hw_stats->lxofftxc += lxoff;
3004         total = lxon + lxoff;
3005
3006         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3007         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3008         hw_stats->gptc -= total;
3009         hw_stats->mptc -= total;
3010         hw_stats->ptc64 -= total;
3011         hw_stats->gotc -= total * ETHER_MIN_LEN;
3012
3013         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3014         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3015         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3016         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3017         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3018         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3019         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3020         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3021         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3022         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3023         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3024         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3025         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3026         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3027         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3028         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3029         /* Only read FCOE on 82599 */
3030         if (hw->mac.type != ixgbe_mac_82598EB) {
3031                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3032                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3033                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3034                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3035                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3036         }
3037
3038         /* Flow Director Stats registers */
3039         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3040         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3041
3042         /* MACsec Stats registers */
3043         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3044         macsec_stats->out_pkts_encrypted +=
3045                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3046         macsec_stats->out_pkts_protected +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3048         macsec_stats->out_octets_encrypted +=
3049                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3050         macsec_stats->out_octets_protected +=
3051                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3052         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3053         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3054         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3055         macsec_stats->in_pkts_unknownsci +=
3056                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3057         macsec_stats->in_octets_decrypted +=
3058                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3059         macsec_stats->in_octets_validated +=
3060                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3061         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3062         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3063         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3064         for (i = 0; i < 2; i++) {
3065                 macsec_stats->in_pkts_ok +=
3066                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3067                 macsec_stats->in_pkts_invalid +=
3068                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3069                 macsec_stats->in_pkts_notvalid +=
3070                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3071         }
3072         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3073         macsec_stats->in_pkts_notusingsa +=
3074                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3075 }
3076
3077 /*
3078  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3079  */
3080 static void
3081 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3082 {
3083         struct ixgbe_hw *hw =
3084                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085         struct ixgbe_hw_stats *hw_stats =
3086                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3087         struct ixgbe_macsec_stats *macsec_stats =
3088                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3089                                 dev->data->dev_private);
3090         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3091         unsigned i;
3092
3093         total_missed_rx = 0;
3094         total_qbrc = 0;
3095         total_qprc = 0;
3096         total_qprdc = 0;
3097
3098         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3099                         &total_qbrc, &total_qprc, &total_qprdc);
3100
3101         if (stats == NULL)
3102                 return;
3103
3104         /* Fill out the rte_eth_stats statistics structure */
3105         stats->ipackets = total_qprc;
3106         stats->ibytes = total_qbrc;
3107         stats->opackets = hw_stats->gptc;
3108         stats->obytes = hw_stats->gotc;
3109
3110         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3111                 stats->q_ipackets[i] = hw_stats->qprc[i];
3112                 stats->q_opackets[i] = hw_stats->qptc[i];
3113                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3114                 stats->q_obytes[i] = hw_stats->qbtc[i];
3115                 stats->q_errors[i] = hw_stats->qprdc[i];
3116         }
3117
3118         /* Rx Errors */
3119         stats->imissed  = total_missed_rx;
3120         stats->ierrors  = hw_stats->crcerrs +
3121                           hw_stats->mspdc +
3122                           hw_stats->rlec +
3123                           hw_stats->ruc +
3124                           hw_stats->roc +
3125                           hw_stats->illerrc +
3126                           hw_stats->errbc +
3127                           hw_stats->rfc +
3128                           hw_stats->fccrc +
3129                           hw_stats->fclast;
3130
3131         /* Tx Errors */
3132         stats->oerrors  = 0;
3133 }
3134
3135 static void
3136 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3137 {
3138         struct ixgbe_hw_stats *stats =
3139                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3140
3141         /* HW registers are cleared on read */
3142         ixgbe_dev_stats_get(dev, NULL);
3143
3144         /* Reset software totals */
3145         memset(stats, 0, sizeof(*stats));
3146 }
3147
3148 /* This function calculates the number of xstats based on the current config */
3149 static unsigned
3150 ixgbe_xstats_calc_num(void) {
3151         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3152                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3153                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3154 }
3155
3156 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3157         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3158 {
3159         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3160         unsigned stat, i, count;
3161
3162         if (xstats_names != NULL) {
3163                 count = 0;
3164
3165                 /* Note: limit >= cnt_stats checked upstream
3166                  * in rte_eth_xstats_names()
3167                  */
3168
3169                 /* Extended stats from ixgbe_hw_stats */
3170                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3171                         snprintf(xstats_names[count].name,
3172                                 sizeof(xstats_names[count].name),
3173                                 "%s",
3174                                 rte_ixgbe_stats_strings[i].name);
3175                         count++;
3176                 }
3177
3178                 /* MACsec Stats */
3179                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3180                         snprintf(xstats_names[count].name,
3181                                 sizeof(xstats_names[count].name),
3182                                 "%s",
3183                                 rte_ixgbe_macsec_strings[i].name);
3184                         count++;
3185                 }
3186
3187                 /* RX Priority Stats */
3188                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3189                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3190                                 snprintf(xstats_names[count].name,
3191                                         sizeof(xstats_names[count].name),
3192                                         "rx_priority%u_%s", i,
3193                                         rte_ixgbe_rxq_strings[stat].name);
3194                                 count++;
3195                         }
3196                 }
3197
3198                 /* TX Priority Stats */
3199                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3200                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3201                                 snprintf(xstats_names[count].name,
3202                                         sizeof(xstats_names[count].name),
3203                                         "tx_priority%u_%s", i,
3204                                         rte_ixgbe_txq_strings[stat].name);
3205                                 count++;
3206                         }
3207                 }
3208         }
3209         return cnt_stats;
3210 }
3211
3212 static int ixgbe_dev_xstats_get_names_by_id(
3213         struct rte_eth_dev *dev,
3214         struct rte_eth_xstat_name *xstats_names,
3215         const uint64_t *ids,
3216         unsigned int limit)
3217 {
3218         if (!ids) {
3219                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3220                 unsigned int stat, i, count;
3221
3222                 if (xstats_names != NULL) {
3223                         count = 0;
3224
3225                         /* Note: limit >= cnt_stats checked upstream
3226                          * in rte_eth_xstats_names()
3227                          */
3228
3229                         /* Extended stats from ixgbe_hw_stats */
3230                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3231                                 snprintf(xstats_names[count].name,
3232                                         sizeof(xstats_names[count].name),
3233                                         "%s",
3234                                         rte_ixgbe_stats_strings[i].name);
3235                                 count++;
3236                         }
3237
3238                         /* MACsec Stats */
3239                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3240                                 snprintf(xstats_names[count].name,
3241                                         sizeof(xstats_names[count].name),
3242                                         "%s",
3243                                         rte_ixgbe_macsec_strings[i].name);
3244                                 count++;
3245                         }
3246
3247                         /* RX Priority Stats */
3248                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3249                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3250                                         snprintf(xstats_names[count].name,
3251                                             sizeof(xstats_names[count].name),
3252                                             "rx_priority%u_%s", i,
3253                                             rte_ixgbe_rxq_strings[stat].name);
3254                                         count++;
3255                                 }
3256                         }
3257
3258                         /* TX Priority Stats */
3259                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3260                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3261                                         snprintf(xstats_names[count].name,
3262                                             sizeof(xstats_names[count].name),
3263                                             "tx_priority%u_%s", i,
3264                                             rte_ixgbe_txq_strings[stat].name);
3265                                         count++;
3266                                 }
3267                         }
3268                 }
3269                 return cnt_stats;
3270         }
3271
3272         uint16_t i;
3273         uint16_t size = ixgbe_xstats_calc_num();
3274         struct rte_eth_xstat_name xstats_names_copy[size];
3275
3276         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3277                         size);
3278
3279         for (i = 0; i < limit; i++) {
3280                 if (ids[i] >= size) {
3281                         PMD_INIT_LOG(ERR, "id value isn't valid");
3282                         return -1;
3283                 }
3284                 strcpy(xstats_names[i].name,
3285                                 xstats_names_copy[ids[i]].name);
3286         }
3287         return limit;
3288 }
3289
3290 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3291         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3292 {
3293         unsigned i;
3294
3295         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3296                 return -ENOMEM;
3297
3298         if (xstats_names != NULL)
3299                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3300                         snprintf(xstats_names[i].name,
3301                                 sizeof(xstats_names[i].name),
3302                                 "%s", rte_ixgbevf_stats_strings[i].name);
3303         return IXGBEVF_NB_XSTATS;
3304 }
3305
3306 static int
3307 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3308                                          unsigned n)
3309 {
3310         struct ixgbe_hw *hw =
3311                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312         struct ixgbe_hw_stats *hw_stats =
3313                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3314         struct ixgbe_macsec_stats *macsec_stats =
3315                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3316                                 dev->data->dev_private);
3317         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3318         unsigned i, stat, count = 0;
3319
3320         count = ixgbe_xstats_calc_num();
3321
3322         if (n < count)
3323                 return count;
3324
3325         total_missed_rx = 0;
3326         total_qbrc = 0;
3327         total_qprc = 0;
3328         total_qprdc = 0;
3329
3330         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3331                         &total_qbrc, &total_qprc, &total_qprdc);
3332
3333         /* If this is a reset xstats is NULL, and we have cleared the
3334          * registers by reading them.
3335          */
3336         if (!xstats)
3337                 return 0;
3338
3339         /* Extended stats from ixgbe_hw_stats */
3340         count = 0;
3341         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3342                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3343                                 rte_ixgbe_stats_strings[i].offset);
3344                 xstats[count].id = count;
3345                 count++;
3346         }
3347
3348         /* MACsec Stats */
3349         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3350                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3351                                 rte_ixgbe_macsec_strings[i].offset);
3352                 xstats[count].id = count;
3353                 count++;
3354         }
3355
3356         /* RX Priority Stats */
3357         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3358                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3359                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3360                                         rte_ixgbe_rxq_strings[stat].offset +
3361                                         (sizeof(uint64_t) * i));
3362                         xstats[count].id = count;
3363                         count++;
3364                 }
3365         }
3366
3367         /* TX Priority Stats */
3368         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3369                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3370                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3371                                         rte_ixgbe_txq_strings[stat].offset +
3372                                         (sizeof(uint64_t) * i));
3373                         xstats[count].id = count;
3374                         count++;
3375                 }
3376         }
3377         return count;
3378 }
3379
3380 static int
3381 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3382                 uint64_t *values, unsigned int n)
3383 {
3384         if (!ids) {
3385                 struct ixgbe_hw *hw =
3386                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387                 struct ixgbe_hw_stats *hw_stats =
3388                                 IXGBE_DEV_PRIVATE_TO_STATS(
3389                                                 dev->data->dev_private);
3390                 struct ixgbe_macsec_stats *macsec_stats =
3391                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3392                                         dev->data->dev_private);
3393                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3394                 unsigned int i, stat, count = 0;
3395
3396                 count = ixgbe_xstats_calc_num();
3397
3398                 if (!ids && n < count)
3399                         return count;
3400
3401                 total_missed_rx = 0;
3402                 total_qbrc = 0;
3403                 total_qprc = 0;
3404                 total_qprdc = 0;
3405
3406                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3407                                 &total_missed_rx, &total_qbrc, &total_qprc,
3408                                 &total_qprdc);
3409
3410                 /* If this is a reset xstats is NULL, and we have cleared the
3411                  * registers by reading them.
3412                  */
3413                 if (!ids && !values)
3414                         return 0;
3415
3416                 /* Extended stats from ixgbe_hw_stats */
3417                 count = 0;
3418                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3419                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3420                                         rte_ixgbe_stats_strings[i].offset);
3421                         count++;
3422                 }
3423
3424                 /* MACsec Stats */
3425                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3426                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3427                                         rte_ixgbe_macsec_strings[i].offset);
3428                         count++;
3429                 }
3430
3431                 /* RX Priority Stats */
3432                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3433                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3434                                 values[count] =
3435                                         *(uint64_t *)(((char *)hw_stats) +
3436                                         rte_ixgbe_rxq_strings[stat].offset +
3437                                         (sizeof(uint64_t) * i));
3438                                 count++;
3439                         }
3440                 }
3441
3442                 /* TX Priority Stats */
3443                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3444                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3445                                 values[count] =
3446                                         *(uint64_t *)(((char *)hw_stats) +
3447                                         rte_ixgbe_txq_strings[stat].offset +
3448                                         (sizeof(uint64_t) * i));
3449                                 count++;
3450                         }
3451                 }
3452                 return count;
3453         }
3454
3455         uint16_t i;
3456         uint16_t size = ixgbe_xstats_calc_num();
3457         uint64_t values_copy[size];
3458
3459         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3460
3461         for (i = 0; i < n; i++) {
3462                 if (ids[i] >= size) {
3463                         PMD_INIT_LOG(ERR, "id value isn't valid");
3464                         return -1;
3465                 }
3466                 values[i] = values_copy[ids[i]];
3467         }
3468         return n;
3469 }
3470
3471 static void
3472 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3473 {
3474         struct ixgbe_hw_stats *stats =
3475                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3476         struct ixgbe_macsec_stats *macsec_stats =
3477                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3478                                 dev->data->dev_private);
3479
3480         unsigned count = ixgbe_xstats_calc_num();
3481
3482         /* HW registers are cleared on read */
3483         ixgbe_dev_xstats_get(dev, NULL, count);
3484
3485         /* Reset software totals */
3486         memset(stats, 0, sizeof(*stats));
3487         memset(macsec_stats, 0, sizeof(*macsec_stats));
3488 }
3489
3490 static void
3491 ixgbevf_update_stats(struct rte_eth_dev *dev)
3492 {
3493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3495                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3496
3497         /* Good Rx packet, include VF loopback */
3498         UPDATE_VF_STAT(IXGBE_VFGPRC,
3499             hw_stats->last_vfgprc, hw_stats->vfgprc);
3500
3501         /* Good Rx octets, include VF loopback */
3502         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3503             hw_stats->last_vfgorc, hw_stats->vfgorc);
3504
3505         /* Good Tx packet, include VF loopback */
3506         UPDATE_VF_STAT(IXGBE_VFGPTC,
3507             hw_stats->last_vfgptc, hw_stats->vfgptc);
3508
3509         /* Good Tx octets, include VF loopback */
3510         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3511             hw_stats->last_vfgotc, hw_stats->vfgotc);
3512
3513         /* Rx Multicst Packet */
3514         UPDATE_VF_STAT(IXGBE_VFMPRC,
3515             hw_stats->last_vfmprc, hw_stats->vfmprc);
3516 }
3517
3518 static int
3519 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3520                        unsigned n)
3521 {
3522         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3523                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3524         unsigned i;
3525
3526         if (n < IXGBEVF_NB_XSTATS)
3527                 return IXGBEVF_NB_XSTATS;
3528
3529         ixgbevf_update_stats(dev);
3530
3531         if (!xstats)
3532                 return 0;
3533
3534         /* Extended stats */
3535         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3536                 xstats[i].id = i;
3537                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3538                         rte_ixgbevf_stats_strings[i].offset);
3539         }
3540
3541         return IXGBEVF_NB_XSTATS;
3542 }
3543
3544 static void
3545 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3546 {
3547         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3548                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3549
3550         ixgbevf_update_stats(dev);
3551
3552         if (stats == NULL)
3553                 return;
3554
3555         stats->ipackets = hw_stats->vfgprc;
3556         stats->ibytes = hw_stats->vfgorc;
3557         stats->opackets = hw_stats->vfgptc;
3558         stats->obytes = hw_stats->vfgotc;
3559 }
3560
3561 static void
3562 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3563 {
3564         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3565                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3566
3567         /* Sync HW register to the last stats */
3568         ixgbevf_dev_stats_get(dev, NULL);
3569
3570         /* reset HW current stats*/
3571         hw_stats->vfgprc = 0;
3572         hw_stats->vfgorc = 0;
3573         hw_stats->vfgptc = 0;
3574         hw_stats->vfgotc = 0;
3575 }
3576
3577 static int
3578 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3579 {
3580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581         u16 eeprom_verh, eeprom_verl;
3582         u32 etrack_id;
3583         int ret;
3584
3585         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3586         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3587
3588         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3589         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3590
3591         ret += 1; /* add the size of '\0' */
3592         if (fw_size < (u32)ret)
3593                 return ret;
3594         else
3595                 return 0;
3596 }
3597
3598 static void
3599 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3600 {
3601         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3604
3605         dev_info->pci_dev = pci_dev;
3606         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3607         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3608         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3609                 /*
3610                  * When DCB/VT is off, maximum number of queues changes,
3611                  * except for 82598EB, which remains constant.
3612                  */
3613                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3614                                 hw->mac.type != ixgbe_mac_82598EB)
3615                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3616         }
3617         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3618         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3619         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3620         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3621         dev_info->max_vfs = pci_dev->max_vfs;
3622         if (hw->mac.type == ixgbe_mac_82598EB)
3623                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3624         else
3625                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3626         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3627         dev_info->rx_offload_capa =
3628                 DEV_RX_OFFLOAD_VLAN_STRIP |
3629                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3630                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3631                 DEV_RX_OFFLOAD_TCP_CKSUM;
3632
3633         /*
3634          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3635          * mode.
3636          */
3637         if ((hw->mac.type == ixgbe_mac_82599EB ||
3638              hw->mac.type == ixgbe_mac_X540) &&
3639             !RTE_ETH_DEV_SRIOV(dev).active)
3640                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3641
3642         if (hw->mac.type == ixgbe_mac_82599EB ||
3643             hw->mac.type == ixgbe_mac_X540)
3644                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3645
3646         if (hw->mac.type == ixgbe_mac_X550 ||
3647             hw->mac.type == ixgbe_mac_X550EM_x ||
3648             hw->mac.type == ixgbe_mac_X550EM_a)
3649                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3650
3651         dev_info->tx_offload_capa =
3652                 DEV_TX_OFFLOAD_VLAN_INSERT |
3653                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3654                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3655                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3656                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3657                 DEV_TX_OFFLOAD_TCP_TSO;
3658
3659         if (hw->mac.type == ixgbe_mac_82599EB ||
3660             hw->mac.type == ixgbe_mac_X540)
3661                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3662
3663         if (hw->mac.type == ixgbe_mac_X550 ||
3664             hw->mac.type == ixgbe_mac_X550EM_x ||
3665             hw->mac.type == ixgbe_mac_X550EM_a)
3666                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3667
3668         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3669                 .rx_thresh = {
3670                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3671                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3672                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3673                 },
3674                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3675                 .rx_drop_en = 0,
3676         };
3677
3678         dev_info->default_txconf = (struct rte_eth_txconf) {
3679                 .tx_thresh = {
3680                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3681                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3682                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3683                 },
3684                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3685                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3686                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3687                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3688         };
3689
3690         dev_info->rx_desc_lim = rx_desc_lim;
3691         dev_info->tx_desc_lim = tx_desc_lim;
3692
3693         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3694         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3695         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3696
3697         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3698         if (hw->mac.type == ixgbe_mac_X540 ||
3699             hw->mac.type == ixgbe_mac_X540_vf ||
3700             hw->mac.type == ixgbe_mac_X550 ||
3701             hw->mac.type == ixgbe_mac_X550_vf) {
3702                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3703         }
3704         if (hw->mac.type == ixgbe_mac_X550) {
3705                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3706                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3707         }
3708 }
3709
3710 static const uint32_t *
3711 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3712 {
3713         static const uint32_t ptypes[] = {
3714                 /* For non-vec functions,
3715                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3716                  * for vec functions,
3717                  * refers to _recv_raw_pkts_vec().
3718                  */
3719                 RTE_PTYPE_L2_ETHER,
3720                 RTE_PTYPE_L3_IPV4,
3721                 RTE_PTYPE_L3_IPV4_EXT,
3722                 RTE_PTYPE_L3_IPV6,
3723                 RTE_PTYPE_L3_IPV6_EXT,
3724                 RTE_PTYPE_L4_SCTP,
3725                 RTE_PTYPE_L4_TCP,
3726                 RTE_PTYPE_L4_UDP,
3727                 RTE_PTYPE_TUNNEL_IP,
3728                 RTE_PTYPE_INNER_L3_IPV6,
3729                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3730                 RTE_PTYPE_INNER_L4_TCP,
3731                 RTE_PTYPE_INNER_L4_UDP,
3732                 RTE_PTYPE_UNKNOWN
3733         };
3734
3735         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3736             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3737             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3738             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3739                 return ptypes;
3740
3741 #if defined(RTE_ARCH_X86)
3742         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3743             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3744                 return ptypes;
3745 #endif
3746         return NULL;
3747 }
3748
3749 static void
3750 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3751                      struct rte_eth_dev_info *dev_info)
3752 {
3753         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3755
3756         dev_info->pci_dev = pci_dev;
3757         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3758         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3759         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3760         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3761         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3762         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3763         dev_info->max_vfs = pci_dev->max_vfs;
3764         if (hw->mac.type == ixgbe_mac_82598EB)
3765                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3766         else
3767                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3768         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3769                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3770                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3771                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3772         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3773                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3774                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3775                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3776                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3777                                 DEV_TX_OFFLOAD_TCP_TSO;
3778
3779         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3780                 .rx_thresh = {
3781                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3782                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3783                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3784                 },
3785                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3786                 .rx_drop_en = 0,
3787         };
3788
3789         dev_info->default_txconf = (struct rte_eth_txconf) {
3790                 .tx_thresh = {
3791                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3792                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3793                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3794                 },
3795                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3796                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3797                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3798                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3799         };
3800
3801         dev_info->rx_desc_lim = rx_desc_lim;
3802         dev_info->tx_desc_lim = tx_desc_lim;
3803 }
3804
3805 static int
3806 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3807                    int *link_up, int wait_to_complete)
3808 {
3809         /**
3810          * for a quick link status checking, wait_to_compelet == 0,
3811          * skip PF link status checking
3812          */
3813         bool no_pflink_check = wait_to_complete == 0;
3814         struct ixgbe_mbx_info *mbx = &hw->mbx;
3815         struct ixgbe_mac_info *mac = &hw->mac;
3816         uint32_t links_reg, in_msg;
3817         int ret_val = 0;
3818
3819         /* If we were hit with a reset drop the link */
3820         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3821                 mac->get_link_status = true;
3822
3823         if (!mac->get_link_status)
3824                 goto out;
3825
3826         /* if link status is down no point in checking to see if pf is up */
3827         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3828         if (!(links_reg & IXGBE_LINKS_UP))
3829                 goto out;
3830
3831         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3832          * before the link status is correct
3833          */
3834         if (mac->type == ixgbe_mac_82599_vf) {
3835                 int i;
3836
3837                 for (i = 0; i < 5; i++) {
3838                         rte_delay_us(100);
3839                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3840
3841                         if (!(links_reg & IXGBE_LINKS_UP))
3842                                 goto out;
3843                 }
3844         }
3845
3846         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3847         case IXGBE_LINKS_SPEED_10G_82599:
3848                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3849                 if (hw->mac.type >= ixgbe_mac_X550) {
3850                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3851                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3852                 }
3853                 break;
3854         case IXGBE_LINKS_SPEED_1G_82599:
3855                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3856                 break;
3857         case IXGBE_LINKS_SPEED_100_82599:
3858                 *speed = IXGBE_LINK_SPEED_100_FULL;
3859                 if (hw->mac.type == ixgbe_mac_X550) {
3860                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3861                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3862                 }
3863                 break;
3864         case IXGBE_LINKS_SPEED_10_X550EM_A:
3865                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3866                 /* Since Reserved in older MAC's */
3867                 if (hw->mac.type >= ixgbe_mac_X550)
3868                         *speed = IXGBE_LINK_SPEED_10_FULL;
3869                 break;
3870         default:
3871                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3872         }
3873
3874         if (no_pflink_check) {
3875                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3876                         mac->get_link_status = true;
3877                 else
3878                         mac->get_link_status = false;
3879
3880                 goto out;
3881         }
3882         /* if the read failed it could just be a mailbox collision, best wait
3883          * until we are called again and don't report an error
3884          */
3885         if (mbx->ops.read(hw, &in_msg, 1, 0))
3886                 goto out;
3887
3888         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3889                 /* msg is not CTS and is NACK we must have lost CTS status */
3890                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3891                         ret_val = -1;
3892                 goto out;
3893         }
3894
3895         /* the pf is talking, if we timed out in the past we reinit */
3896         if (!mbx->timeout) {
3897                 ret_val = -1;
3898                 goto out;
3899         }
3900
3901         /* if we passed all the tests above then the link is up and we no
3902          * longer need to check for link
3903          */
3904         mac->get_link_status = false;
3905
3906 out:
3907         *link_up = !mac->get_link_status;
3908         return ret_val;
3909 }
3910
3911 /* return 0 means link status changed, -1 means not changed */
3912 static int
3913 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3914                             int wait_to_complete, int vf)
3915 {
3916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         struct rte_eth_link link, old;
3918         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3919         struct ixgbe_interrupt *intr =
3920                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3921         int link_up;
3922         int diag;
3923         u32 speed = 0;
3924         int wait = 1;
3925         bool autoneg = false;
3926
3927         link.link_status = ETH_LINK_DOWN;
3928         link.link_speed = 0;
3929         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3930         memset(&old, 0, sizeof(old));
3931         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3932
3933         hw->mac.get_link_status = true;
3934
3935         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3936                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3937                 speed = hw->phy.autoneg_advertised;
3938                 if (!speed)
3939                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3940                 ixgbe_setup_link(hw, speed, true);
3941         }
3942
3943         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3944         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3945                 wait = 0;
3946
3947         if (vf)
3948                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3949         else
3950                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3951
3952         if (diag != 0) {
3953                 link.link_speed = ETH_SPEED_NUM_100M;
3954                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3955                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3956                 if (link.link_status == old.link_status)
3957                         return -1;
3958                 return 0;
3959         }
3960
3961         if (link_up == 0) {
3962                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3963                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3964                 if (link.link_status == old.link_status)
3965                         return -1;
3966                 return 0;
3967         }
3968         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3969         link.link_status = ETH_LINK_UP;
3970         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3971
3972         switch (link_speed) {
3973         default:
3974         case IXGBE_LINK_SPEED_UNKNOWN:
3975                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3976                 link.link_speed = ETH_SPEED_NUM_100M;
3977                 break;
3978
3979         case IXGBE_LINK_SPEED_100_FULL:
3980                 link.link_speed = ETH_SPEED_NUM_100M;
3981                 break;
3982
3983         case IXGBE_LINK_SPEED_1GB_FULL:
3984                 link.link_speed = ETH_SPEED_NUM_1G;
3985                 break;
3986
3987         case IXGBE_LINK_SPEED_2_5GB_FULL:
3988                 link.link_speed = ETH_SPEED_NUM_2_5G;
3989                 break;
3990
3991         case IXGBE_LINK_SPEED_5GB_FULL:
3992                 link.link_speed = ETH_SPEED_NUM_5G;
3993                 break;
3994
3995         case IXGBE_LINK_SPEED_10GB_FULL:
3996                 link.link_speed = ETH_SPEED_NUM_10G;
3997                 break;
3998         }
3999         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4000
4001         if (link.link_status == old.link_status)
4002                 return -1;
4003
4004         return 0;
4005 }
4006
4007 static int
4008 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4009 {
4010         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4011 }
4012
4013 static int
4014 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4015 {
4016         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4017 }
4018
4019 static void
4020 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4021 {
4022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4023         uint32_t fctrl;
4024
4025         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4026         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4027         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4028 }
4029
4030 static void
4031 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4032 {
4033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034         uint32_t fctrl;
4035
4036         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4037         fctrl &= (~IXGBE_FCTRL_UPE);
4038         if (dev->data->all_multicast == 1)
4039                 fctrl |= IXGBE_FCTRL_MPE;
4040         else
4041                 fctrl &= (~IXGBE_FCTRL_MPE);
4042         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4043 }
4044
4045 static void
4046 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4047 {
4048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4049         uint32_t fctrl;
4050
4051         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4052         fctrl |= IXGBE_FCTRL_MPE;
4053         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4054 }
4055
4056 static void
4057 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4058 {
4059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060         uint32_t fctrl;
4061
4062         if (dev->data->promiscuous == 1)
4063                 return; /* must remain in all_multicast mode */
4064
4065         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4066         fctrl &= (~IXGBE_FCTRL_MPE);
4067         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4068 }
4069
4070 /**
4071  * It clears the interrupt causes and enables the interrupt.
4072  * It will be called once only during nic initialized.
4073  *
4074  * @param dev
4075  *  Pointer to struct rte_eth_dev.
4076  * @param on
4077  *  Enable or Disable.
4078  *
4079  * @return
4080  *  - On success, zero.
4081  *  - On failure, a negative value.
4082  */
4083 static int
4084 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4085 {
4086         struct ixgbe_interrupt *intr =
4087                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4088
4089         ixgbe_dev_link_status_print(dev);
4090         if (on)
4091                 intr->mask |= IXGBE_EICR_LSC;
4092         else
4093                 intr->mask &= ~IXGBE_EICR_LSC;
4094
4095         return 0;
4096 }
4097
4098 /**
4099  * It clears the interrupt causes and enables the interrupt.
4100  * It will be called once only during nic initialized.
4101  *
4102  * @param dev
4103  *  Pointer to struct rte_eth_dev.
4104  *
4105  * @return
4106  *  - On success, zero.
4107  *  - On failure, a negative value.
4108  */
4109 static int
4110 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4111 {
4112         struct ixgbe_interrupt *intr =
4113                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4114
4115         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4116
4117         return 0;
4118 }
4119
4120 /**
4121  * It clears the interrupt causes and enables the interrupt.
4122  * It will be called once only during nic initialized.
4123  *
4124  * @param dev
4125  *  Pointer to struct rte_eth_dev.
4126  *
4127  * @return
4128  *  - On success, zero.
4129  *  - On failure, a negative value.
4130  */
4131 static int
4132 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4133 {
4134         struct ixgbe_interrupt *intr =
4135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4136
4137         intr->mask |= IXGBE_EICR_LINKSEC;
4138
4139         return 0;
4140 }
4141
4142 /*
4143  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4144  *
4145  * @param dev
4146  *  Pointer to struct rte_eth_dev.
4147  *
4148  * @return
4149  *  - On success, zero.
4150  *  - On failure, a negative value.
4151  */
4152 static int
4153 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4154 {
4155         uint32_t eicr;
4156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157         struct ixgbe_interrupt *intr =
4158                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4159
4160         /* clear all cause mask */
4161         ixgbe_disable_intr(hw);
4162
4163         /* read-on-clear nic registers here */
4164         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4165         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4166
4167         intr->flags = 0;
4168
4169         /* set flag for async link update */
4170         if (eicr & IXGBE_EICR_LSC)
4171                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4172
4173         if (eicr & IXGBE_EICR_MAILBOX)
4174                 intr->flags |= IXGBE_FLAG_MAILBOX;
4175
4176         if (eicr & IXGBE_EICR_LINKSEC)
4177                 intr->flags |= IXGBE_FLAG_MACSEC;
4178
4179         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4180             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4181             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4182                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4183
4184         return 0;
4185 }
4186
4187 /**
4188  * It gets and then prints the link status.
4189  *
4190  * @param dev
4191  *  Pointer to struct rte_eth_dev.
4192  *
4193  * @return
4194  *  - On success, zero.
4195  *  - On failure, a negative value.
4196  */
4197 static void
4198 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4199 {
4200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4201         struct rte_eth_link link;
4202
4203         memset(&link, 0, sizeof(link));
4204         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4205         if (link.link_status) {
4206                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4207                                         (int)(dev->data->port_id),
4208                                         (unsigned)link.link_speed,
4209                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4210                                         "full-duplex" : "half-duplex");
4211         } else {
4212                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4213                                 (int)(dev->data->port_id));
4214         }
4215         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4216                                 pci_dev->addr.domain,
4217                                 pci_dev->addr.bus,
4218                                 pci_dev->addr.devid,
4219                                 pci_dev->addr.function);
4220 }
4221
4222 /*
4223  * It executes link_update after knowing an interrupt occurred.
4224  *
4225  * @param dev
4226  *  Pointer to struct rte_eth_dev.
4227  *
4228  * @return
4229  *  - On success, zero.
4230  *  - On failure, a negative value.
4231  */
4232 static int
4233 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4234                            struct rte_intr_handle *intr_handle)
4235 {
4236         struct ixgbe_interrupt *intr =
4237                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4238         int64_t timeout;
4239         struct rte_eth_link link;
4240         struct ixgbe_hw *hw =
4241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4242
4243         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4244
4245         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4246                 ixgbe_pf_mbx_process(dev);
4247                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4248         }
4249
4250         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4251                 ixgbe_handle_lasi(hw);
4252                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4253         }
4254
4255         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4256                 /* get the link status before link update, for predicting later */
4257                 memset(&link, 0, sizeof(link));
4258                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4259
4260                 ixgbe_dev_link_update(dev, 0);
4261
4262                 /* likely to up */
4263                 if (!link.link_status)
4264                         /* handle it 1 sec later, wait it being stable */
4265                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4266                 /* likely to down */
4267                 else
4268                         /* handle it 4 sec later, wait it being stable */
4269                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4270
4271                 ixgbe_dev_link_status_print(dev);
4272                 if (rte_eal_alarm_set(timeout * 1000,
4273                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4274                         PMD_DRV_LOG(ERR, "Error setting alarm");
4275                 else {
4276                         /* remember original mask */
4277                         intr->mask_original = intr->mask;
4278                         /* only disable lsc interrupt */
4279                         intr->mask &= ~IXGBE_EIMS_LSC;
4280                 }
4281         }
4282
4283         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4284         ixgbe_enable_intr(dev);
4285         rte_intr_enable(intr_handle);
4286
4287         return 0;
4288 }
4289
4290 /**
4291  * Interrupt handler which shall be registered for alarm callback for delayed
4292  * handling specific interrupt to wait for the stable nic state. As the
4293  * NIC interrupt state is not stable for ixgbe after link is just down,
4294  * it needs to wait 4 seconds to get the stable status.
4295  *
4296  * @param handle
4297  *  Pointer to interrupt handle.
4298  * @param param
4299  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4300  *
4301  * @return
4302  *  void
4303  */
4304 static void
4305 ixgbe_dev_interrupt_delayed_handler(void *param)
4306 {
4307         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4309         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4310         struct ixgbe_interrupt *intr =
4311                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4312         struct ixgbe_hw *hw =
4313                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314         uint32_t eicr;
4315
4316         ixgbe_disable_intr(hw);
4317
4318         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4319         if (eicr & IXGBE_EICR_MAILBOX)
4320                 ixgbe_pf_mbx_process(dev);
4321
4322         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4323                 ixgbe_handle_lasi(hw);
4324                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4325         }
4326
4327         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4328                 ixgbe_dev_link_update(dev, 0);
4329                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4330                 ixgbe_dev_link_status_print(dev);
4331                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4332                                               NULL, NULL);
4333         }
4334
4335         if (intr->flags & IXGBE_FLAG_MACSEC) {
4336                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4337                                               NULL, NULL);
4338                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4339         }
4340
4341         /* restore original mask */
4342         intr->mask = intr->mask_original;
4343         intr->mask_original = 0;
4344
4345         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4346         ixgbe_enable_intr(dev);
4347         rte_intr_enable(intr_handle);
4348 }
4349
4350 /**
4351  * Interrupt handler triggered by NIC  for handling
4352  * specific interrupt.
4353  *
4354  * @param handle
4355  *  Pointer to interrupt handle.
4356  * @param param
4357  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4358  *
4359  * @return
4360  *  void
4361  */
4362 static void
4363 ixgbe_dev_interrupt_handler(void *param)
4364 {
4365         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4366
4367         ixgbe_dev_interrupt_get_status(dev);
4368         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4369 }
4370
4371 static int
4372 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4373 {
4374         struct ixgbe_hw *hw;
4375
4376         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4378 }
4379
4380 static int
4381 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4382 {
4383         struct ixgbe_hw *hw;
4384
4385         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4386         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4387 }
4388
4389 static int
4390 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4391 {
4392         struct ixgbe_hw *hw;
4393         uint32_t mflcn_reg;
4394         uint32_t fccfg_reg;
4395         int rx_pause;
4396         int tx_pause;
4397
4398         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4399
4400         fc_conf->pause_time = hw->fc.pause_time;
4401         fc_conf->high_water = hw->fc.high_water[0];
4402         fc_conf->low_water = hw->fc.low_water[0];
4403         fc_conf->send_xon = hw->fc.send_xon;
4404         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4405
4406         /*
4407          * Return rx_pause status according to actual setting of
4408          * MFLCN register.
4409          */
4410         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4411         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4412                 rx_pause = 1;
4413         else
4414                 rx_pause = 0;
4415
4416         /*
4417          * Return tx_pause status according to actual setting of
4418          * FCCFG register.
4419          */
4420         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4421         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4422                 tx_pause = 1;
4423         else
4424                 tx_pause = 0;
4425
4426         if (rx_pause && tx_pause)
4427                 fc_conf->mode = RTE_FC_FULL;
4428         else if (rx_pause)
4429                 fc_conf->mode = RTE_FC_RX_PAUSE;
4430         else if (tx_pause)
4431                 fc_conf->mode = RTE_FC_TX_PAUSE;
4432         else
4433                 fc_conf->mode = RTE_FC_NONE;
4434
4435         return 0;
4436 }
4437
4438 static int
4439 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4440 {
4441         struct ixgbe_hw *hw;
4442         int err;
4443         uint32_t rx_buf_size;
4444         uint32_t max_high_water;
4445         uint32_t mflcn;
4446         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4447                 ixgbe_fc_none,
4448                 ixgbe_fc_rx_pause,
4449                 ixgbe_fc_tx_pause,
4450                 ixgbe_fc_full
4451         };
4452
4453         PMD_INIT_FUNC_TRACE();
4454
4455         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4456         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4457         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4458
4459         /*
4460          * At least reserve one Ethernet frame for watermark
4461          * high_water/low_water in kilo bytes for ixgbe
4462          */
4463         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4464         if ((fc_conf->high_water > max_high_water) ||
4465                 (fc_conf->high_water < fc_conf->low_water)) {
4466                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4467                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4468                 return -EINVAL;
4469         }
4470
4471         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4472         hw->fc.pause_time     = fc_conf->pause_time;
4473         hw->fc.high_water[0]  = fc_conf->high_water;
4474         hw->fc.low_water[0]   = fc_conf->low_water;
4475         hw->fc.send_xon       = fc_conf->send_xon;
4476         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4477
4478         err = ixgbe_fc_enable(hw);
4479
4480         /* Not negotiated is not an error case */
4481         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4482
4483                 /* check if we want to forward MAC frames - driver doesn't have native
4484                  * capability to do that, so we'll write the registers ourselves */
4485
4486                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4487
4488                 /* set or clear MFLCN.PMCF bit depending on configuration */
4489                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4490                         mflcn |= IXGBE_MFLCN_PMCF;
4491                 else
4492                         mflcn &= ~IXGBE_MFLCN_PMCF;
4493
4494                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4495                 IXGBE_WRITE_FLUSH(hw);
4496
4497                 return 0;
4498         }
4499
4500         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4501         return -EIO;
4502 }
4503
4504 /**
4505  *  ixgbe_pfc_enable_generic - Enable flow control
4506  *  @hw: pointer to hardware structure
4507  *  @tc_num: traffic class number
4508  *  Enable flow control according to the current settings.
4509  */
4510 static int
4511 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4512 {
4513         int ret_val = 0;
4514         uint32_t mflcn_reg, fccfg_reg;
4515         uint32_t reg;
4516         uint32_t fcrtl, fcrth;
4517         uint8_t i;
4518         uint8_t nb_rx_en;
4519
4520         /* Validate the water mark configuration */
4521         if (!hw->fc.pause_time) {
4522                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4523                 goto out;
4524         }
4525
4526         /* Low water mark of zero causes XOFF floods */
4527         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4528                  /* High/Low water can not be 0 */
4529                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4530                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4531                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4532                         goto out;
4533                 }
4534
4535                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4536                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4537                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4538                         goto out;
4539                 }
4540         }
4541         /* Negotiate the fc mode to use */
4542         ixgbe_fc_autoneg(hw);
4543
4544         /* Disable any previous flow control settings */
4545         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4546         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4547
4548         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4549         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4550
4551         switch (hw->fc.current_mode) {
4552         case ixgbe_fc_none:
4553                 /*
4554                  * If the count of enabled RX Priority Flow control >1,
4555                  * and the TX pause can not be disabled
4556                  */
4557                 nb_rx_en = 0;
4558                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4559                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4560                         if (reg & IXGBE_FCRTH_FCEN)
4561                                 nb_rx_en++;
4562                 }
4563                 if (nb_rx_en > 1)
4564                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4565                 break;
4566         case ixgbe_fc_rx_pause:
4567                 /*
4568                  * Rx Flow control is enabled and Tx Flow control is
4569                  * disabled by software override. Since there really
4570                  * isn't a way to advertise that we are capable of RX
4571                  * Pause ONLY, we will advertise that we support both
4572                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4573                  * disable the adapter's ability to send PAUSE frames.
4574                  */
4575                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4576                 /*
4577                  * If the count of enabled RX Priority Flow control >1,
4578                  * and the TX pause can not be disabled
4579                  */
4580                 nb_rx_en = 0;
4581                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4582                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4583                         if (reg & IXGBE_FCRTH_FCEN)
4584                                 nb_rx_en++;
4585                 }
4586                 if (nb_rx_en > 1)
4587                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4588                 break;
4589         case ixgbe_fc_tx_pause:
4590                 /*
4591                  * Tx Flow control is enabled, and Rx Flow control is
4592                  * disabled by software override.
4593                  */
4594                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4595                 break;
4596         case ixgbe_fc_full:
4597                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4598                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4599                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4600                 break;
4601         default:
4602                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4603                 ret_val = IXGBE_ERR_CONFIG;
4604                 goto out;
4605         }
4606
4607         /* Set 802.3x based flow control settings. */
4608         mflcn_reg |= IXGBE_MFLCN_DPF;
4609         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4610         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4611
4612         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4613         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4614                 hw->fc.high_water[tc_num]) {
4615                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4616                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4617                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4618         } else {
4619                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4620                 /*
4621                  * In order to prevent Tx hangs when the internal Tx
4622                  * switch is enabled we must set the high water mark
4623                  * to the maximum FCRTH value.  This allows the Tx
4624                  * switch to function even under heavy Rx workloads.
4625                  */
4626                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4627         }
4628         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4629
4630         /* Configure pause time (2 TCs per register) */
4631         reg = hw->fc.pause_time * 0x00010001;
4632         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4633                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4634
4635         /* Configure flow control refresh threshold value */
4636         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4637
4638 out:
4639         return ret_val;
4640 }
4641
4642 static int
4643 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4644 {
4645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4647
4648         if (hw->mac.type != ixgbe_mac_82598EB) {
4649                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4650         }
4651         return ret_val;
4652 }
4653
4654 static int
4655 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4656 {
4657         int err;
4658         uint32_t rx_buf_size;
4659         uint32_t max_high_water;
4660         uint8_t tc_num;
4661         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4662         struct ixgbe_hw *hw =
4663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4664         struct ixgbe_dcb_config *dcb_config =
4665                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4666
4667         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4668                 ixgbe_fc_none,
4669                 ixgbe_fc_rx_pause,
4670                 ixgbe_fc_tx_pause,
4671                 ixgbe_fc_full
4672         };
4673
4674         PMD_INIT_FUNC_TRACE();
4675
4676         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4677         tc_num = map[pfc_conf->priority];
4678         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4679         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4680         /*
4681          * At least reserve one Ethernet frame for watermark
4682          * high_water/low_water in kilo bytes for ixgbe
4683          */
4684         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4685         if ((pfc_conf->fc.high_water > max_high_water) ||
4686             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4687                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4688                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4689                 return -EINVAL;
4690         }
4691
4692         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4693         hw->fc.pause_time = pfc_conf->fc.pause_time;
4694         hw->fc.send_xon = pfc_conf->fc.send_xon;
4695         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4696         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4697
4698         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4699
4700         /* Not negotiated is not an error case */
4701         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4702                 return 0;
4703
4704         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4705         return -EIO;
4706 }
4707
4708 static int
4709 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4710                           struct rte_eth_rss_reta_entry64 *reta_conf,
4711                           uint16_t reta_size)
4712 {
4713         uint16_t i, sp_reta_size;
4714         uint8_t j, mask;
4715         uint32_t reta, r;
4716         uint16_t idx, shift;
4717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718         uint32_t reta_reg;
4719
4720         PMD_INIT_FUNC_TRACE();
4721
4722         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4723                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4724                         "NIC.");
4725                 return -ENOTSUP;
4726         }
4727
4728         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4729         if (reta_size != sp_reta_size) {
4730                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4731                         "(%d) doesn't match the number hardware can supported "
4732                         "(%d)", reta_size, sp_reta_size);
4733                 return -EINVAL;
4734         }
4735
4736         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4737                 idx = i / RTE_RETA_GROUP_SIZE;
4738                 shift = i % RTE_RETA_GROUP_SIZE;
4739                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4740                                                 IXGBE_4_BIT_MASK);
4741                 if (!mask)
4742                         continue;
4743                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4744                 if (mask == IXGBE_4_BIT_MASK)
4745                         r = 0;
4746                 else
4747                         r = IXGBE_READ_REG(hw, reta_reg);
4748                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4749                         if (mask & (0x1 << j))
4750                                 reta |= reta_conf[idx].reta[shift + j] <<
4751                                                         (CHAR_BIT * j);
4752                         else
4753                                 reta |= r & (IXGBE_8_BIT_MASK <<
4754                                                 (CHAR_BIT * j));
4755                 }
4756                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4757         }
4758
4759         return 0;
4760 }
4761
4762 static int
4763 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4764                          struct rte_eth_rss_reta_entry64 *reta_conf,
4765                          uint16_t reta_size)
4766 {
4767         uint16_t i, sp_reta_size;
4768         uint8_t j, mask;
4769         uint32_t reta;
4770         uint16_t idx, shift;
4771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4772         uint32_t reta_reg;
4773
4774         PMD_INIT_FUNC_TRACE();
4775         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4776         if (reta_size != sp_reta_size) {
4777                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4778                         "(%d) doesn't match the number hardware can supported "
4779                         "(%d)", reta_size, sp_reta_size);
4780                 return -EINVAL;
4781         }
4782
4783         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4784                 idx = i / RTE_RETA_GROUP_SIZE;
4785                 shift = i % RTE_RETA_GROUP_SIZE;
4786                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4787                                                 IXGBE_4_BIT_MASK);
4788                 if (!mask)
4789                         continue;
4790
4791                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4792                 reta = IXGBE_READ_REG(hw, reta_reg);
4793                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4794                         if (mask & (0x1 << j))
4795                                 reta_conf[idx].reta[shift + j] =
4796                                         ((reta >> (CHAR_BIT * j)) &
4797                                                 IXGBE_8_BIT_MASK);
4798                 }
4799         }
4800
4801         return 0;
4802 }
4803
4804 static int
4805 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4806                                 uint32_t index, uint32_t pool)
4807 {
4808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809         uint32_t enable_addr = 1;
4810
4811         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4812                              pool, enable_addr);
4813 }
4814
4815 static void
4816 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4817 {
4818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4819
4820         ixgbe_clear_rar(hw, index);
4821 }
4822
4823 static void
4824 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4825 {
4826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4827
4828         ixgbe_remove_rar(dev, 0);
4829
4830         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4831 }
4832
4833 static bool
4834 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4835 {
4836         if (strcmp(dev->device->driver->name, drv->driver.name))
4837                 return false;
4838
4839         return true;
4840 }
4841
4842 bool
4843 is_ixgbe_supported(struct rte_eth_dev *dev)
4844 {
4845         return is_device_supported(dev, &rte_ixgbe_pmd);
4846 }
4847
4848 static int
4849 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4850 {
4851         uint32_t hlreg0;
4852         uint32_t maxfrs;
4853         struct ixgbe_hw *hw;
4854         struct rte_eth_dev_info dev_info;
4855         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4856         struct rte_eth_dev_data *dev_data = dev->data;
4857
4858         ixgbe_dev_info_get(dev, &dev_info);
4859
4860         /* check that mtu is within the allowed range */
4861         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4862                 return -EINVAL;
4863
4864         /* If device is started, refuse mtu that requires the support of
4865          * scattered packets when this feature has not been enabled before.
4866          */
4867         if (dev_data->dev_started && !dev_data->scattered_rx &&
4868             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4869              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4870                 PMD_INIT_LOG(ERR, "Stop port first.");
4871                 return -EINVAL;
4872         }
4873
4874         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4876
4877         /* switch to jumbo mode if needed */
4878         if (frame_size > ETHER_MAX_LEN) {
4879                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4880                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4881         } else {
4882                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4883                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4884         }
4885         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4886
4887         /* update max frame size */
4888         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4889
4890         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4891         maxfrs &= 0x0000FFFF;
4892         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4893         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4894
4895         return 0;
4896 }
4897
4898 /*
4899  * Virtual Function operations
4900  */
4901 static void
4902 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4903 {
4904         PMD_INIT_FUNC_TRACE();
4905
4906         /* Clear interrupt mask to stop from interrupts being generated */
4907         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4908
4909         IXGBE_WRITE_FLUSH(hw);
4910 }
4911
4912 static void
4913 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4914 {
4915         PMD_INIT_FUNC_TRACE();
4916
4917         /* VF enable interrupt autoclean */
4918         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4919         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4920         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4921
4922         IXGBE_WRITE_FLUSH(hw);
4923 }
4924
4925 static int
4926 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4927 {
4928         struct rte_eth_conf *conf = &dev->data->dev_conf;
4929         struct ixgbe_adapter *adapter =
4930                         (struct ixgbe_adapter *)dev->data->dev_private;
4931
4932         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4933                      dev->data->port_id);
4934
4935         /*
4936          * VF has no ability to enable/disable HW CRC
4937          * Keep the persistent behavior the same as Host PF
4938          */
4939 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4940         if (!conf->rxmode.hw_strip_crc) {
4941                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4942                 conf->rxmode.hw_strip_crc = 1;
4943         }
4944 #else
4945         if (conf->rxmode.hw_strip_crc) {
4946                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4947                 conf->rxmode.hw_strip_crc = 0;
4948         }
4949 #endif
4950
4951         /*
4952          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4953          * allocation or vector Rx preconditions we will reset it.
4954          */
4955         adapter->rx_bulk_alloc_allowed = true;
4956         adapter->rx_vec_allowed = true;
4957
4958         return 0;
4959 }
4960
4961 static int
4962 ixgbevf_dev_start(struct rte_eth_dev *dev)
4963 {
4964         struct ixgbe_hw *hw =
4965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966         uint32_t intr_vector = 0;
4967         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4968         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4969
4970         int err, mask = 0;
4971
4972         PMD_INIT_FUNC_TRACE();
4973
4974         hw->mac.ops.reset_hw(hw);
4975         hw->mac.get_link_status = true;
4976
4977         /* negotiate mailbox API version to use with the PF. */
4978         ixgbevf_negotiate_api(hw);
4979
4980         ixgbevf_dev_tx_init(dev);
4981
4982         /* This can fail when allocating mbufs for descriptor rings */
4983         err = ixgbevf_dev_rx_init(dev);
4984         if (err) {
4985                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4986                 ixgbe_dev_clear_queues(dev);
4987                 return err;
4988         }
4989
4990         /* Set vfta */
4991         ixgbevf_set_vfta_all(dev, 1);
4992
4993         /* Set HW strip */
4994         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4995                 ETH_VLAN_EXTEND_MASK;
4996         ixgbevf_vlan_offload_set(dev, mask);
4997
4998         ixgbevf_dev_rxtx_start(dev);
4999
5000         /* check and configure queue intr-vector mapping */
5001         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5002                 intr_vector = dev->data->nb_rx_queues;
5003                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5004                         return -1;
5005         }
5006
5007         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5008                 intr_handle->intr_vec =
5009                         rte_zmalloc("intr_vec",
5010                                     dev->data->nb_rx_queues * sizeof(int), 0);
5011                 if (intr_handle->intr_vec == NULL) {
5012                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5013                                      " intr_vec", dev->data->nb_rx_queues);
5014                         return -ENOMEM;
5015                 }
5016         }
5017         ixgbevf_configure_msix(dev);
5018
5019         rte_intr_enable(intr_handle);
5020
5021         /* Re-enable interrupt for VF */
5022         ixgbevf_intr_enable(hw);
5023
5024         return 0;
5025 }
5026
5027 static void
5028 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5029 {
5030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5031         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5032         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5033
5034         PMD_INIT_FUNC_TRACE();
5035
5036         ixgbevf_intr_disable(hw);
5037
5038         hw->adapter_stopped = 1;
5039         ixgbe_stop_adapter(hw);
5040
5041         /*
5042           * Clear what we set, but we still keep shadow_vfta to
5043           * restore after device starts
5044           */
5045         ixgbevf_set_vfta_all(dev, 0);
5046
5047         /* Clear stored conf */
5048         dev->data->scattered_rx = 0;
5049
5050         ixgbe_dev_clear_queues(dev);
5051
5052         /* Clean datapath event and queue/vec mapping */
5053         rte_intr_efd_disable(intr_handle);
5054         if (intr_handle->intr_vec != NULL) {
5055                 rte_free(intr_handle->intr_vec);
5056                 intr_handle->intr_vec = NULL;
5057         }
5058 }
5059
5060 static void
5061 ixgbevf_dev_close(struct rte_eth_dev *dev)
5062 {
5063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064
5065         PMD_INIT_FUNC_TRACE();
5066
5067         ixgbe_reset_hw(hw);
5068
5069         ixgbevf_dev_stop(dev);
5070
5071         ixgbe_dev_free_queues(dev);
5072
5073         /**
5074          * Remove the VF MAC address ro ensure
5075          * that the VF traffic goes to the PF
5076          * after stop, close and detach of the VF
5077          **/
5078         ixgbevf_remove_mac_addr(dev, 0);
5079 }
5080
5081 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5082 {
5083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         struct ixgbe_vfta *shadow_vfta =
5085                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5086         int i = 0, j = 0, vfta = 0, mask = 1;
5087
5088         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5089                 vfta = shadow_vfta->vfta[i];
5090                 if (vfta) {
5091                         mask = 1;
5092                         for (j = 0; j < 32; j++) {
5093                                 if (vfta & mask)
5094                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5095                                                        on, false);
5096                                 mask <<= 1;
5097                         }
5098                 }
5099         }
5100
5101 }
5102
5103 static int
5104 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5105 {
5106         struct ixgbe_hw *hw =
5107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108         struct ixgbe_vfta *shadow_vfta =
5109                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5110         uint32_t vid_idx = 0;
5111         uint32_t vid_bit = 0;
5112         int ret = 0;
5113
5114         PMD_INIT_FUNC_TRACE();
5115
5116         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5117         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5118         if (ret) {
5119                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5120                 return ret;
5121         }
5122         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5123         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5124
5125         /* Save what we set and retore it after device reset */
5126         if (on)
5127                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5128         else
5129                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5130
5131         return 0;
5132 }
5133
5134 static void
5135 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5136 {
5137         struct ixgbe_hw *hw =
5138                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5139         uint32_t ctrl;
5140
5141         PMD_INIT_FUNC_TRACE();
5142
5143         if (queue >= hw->mac.max_rx_queues)
5144                 return;
5145
5146         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5147         if (on)
5148                 ctrl |= IXGBE_RXDCTL_VME;
5149         else
5150                 ctrl &= ~IXGBE_RXDCTL_VME;
5151         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5152
5153         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5154 }
5155
5156 static void
5157 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5158 {
5159         struct ixgbe_hw *hw =
5160                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161         uint16_t i;
5162         int on = 0;
5163
5164         /* VF function only support hw strip feature, others are not support */
5165         if (mask & ETH_VLAN_STRIP_MASK) {
5166                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5167
5168                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5169                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5170         }
5171 }
5172
5173 int
5174 ixgbe_vt_check(struct ixgbe_hw *hw)
5175 {
5176         uint32_t reg_val;
5177
5178         /* if Virtualization Technology is enabled */
5179         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5180         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5181                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5182                 return -1;
5183         }
5184
5185         return 0;
5186 }
5187
5188 static uint32_t
5189 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5190 {
5191         uint32_t vector = 0;
5192
5193         switch (hw->mac.mc_filter_type) {
5194         case 0:   /* use bits [47:36] of the address */
5195                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5196                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5197                 break;
5198         case 1:   /* use bits [46:35] of the address */
5199                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5200                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5201                 break;
5202         case 2:   /* use bits [45:34] of the address */
5203                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5204                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5205                 break;
5206         case 3:   /* use bits [43:32] of the address */
5207                 vector = ((uc_addr->addr_bytes[4]) |
5208                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5209                 break;
5210         default:  /* Invalid mc_filter_type */
5211                 break;
5212         }
5213
5214         /* vector can only be 12-bits or boundary will be exceeded */
5215         vector &= 0xFFF;
5216         return vector;
5217 }
5218
5219 static int
5220 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5221                         uint8_t on)
5222 {
5223         uint32_t vector;
5224         uint32_t uta_idx;
5225         uint32_t reg_val;
5226         uint32_t uta_shift;
5227         uint32_t rc;
5228         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5229         const uint32_t ixgbe_uta_bit_shift = 5;
5230         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5231         const uint32_t bit1 = 0x1;
5232
5233         struct ixgbe_hw *hw =
5234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         struct ixgbe_uta_info *uta_info =
5236                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5237
5238         /* The UTA table only exists on 82599 hardware and newer */
5239         if (hw->mac.type < ixgbe_mac_82599EB)
5240                 return -ENOTSUP;
5241
5242         vector = ixgbe_uta_vector(hw, mac_addr);
5243         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5244         uta_shift = vector & ixgbe_uta_bit_mask;
5245
5246         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5247         if (rc == on)
5248                 return 0;
5249
5250         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5251         if (on) {
5252                 uta_info->uta_in_use++;
5253                 reg_val |= (bit1 << uta_shift);
5254                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5255         } else {
5256                 uta_info->uta_in_use--;
5257                 reg_val &= ~(bit1 << uta_shift);
5258                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5259         }
5260
5261         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5262
5263         if (uta_info->uta_in_use > 0)
5264                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5265                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5266         else
5267                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5268
5269         return 0;
5270 }
5271
5272 static int
5273 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5274 {
5275         int i;
5276         struct ixgbe_hw *hw =
5277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278         struct ixgbe_uta_info *uta_info =
5279                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5280
5281         /* The UTA table only exists on 82599 hardware and newer */
5282         if (hw->mac.type < ixgbe_mac_82599EB)
5283                 return -ENOTSUP;
5284
5285         if (on) {
5286                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5287                         uta_info->uta_shadow[i] = ~0;
5288                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5289                 }
5290         } else {
5291                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5292                         uta_info->uta_shadow[i] = 0;
5293                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5294                 }
5295         }
5296         return 0;
5297
5298 }
5299
5300 uint32_t
5301 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5302 {
5303         uint32_t new_val = orig_val;
5304
5305         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5306                 new_val |= IXGBE_VMOLR_AUPE;
5307         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5308                 new_val |= IXGBE_VMOLR_ROMPE;
5309         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5310                 new_val |= IXGBE_VMOLR_ROPE;
5311         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5312                 new_val |= IXGBE_VMOLR_BAM;
5313         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5314                 new_val |= IXGBE_VMOLR_MPE;
5315
5316         return new_val;
5317 }
5318
5319 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5320 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5321 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5322 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5323 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5324         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5325         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5326
5327 static int
5328 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5329                       struct rte_eth_mirror_conf *mirror_conf,
5330                       uint8_t rule_id, uint8_t on)
5331 {
5332         uint32_t mr_ctl, vlvf;
5333         uint32_t mp_lsb = 0;
5334         uint32_t mv_msb = 0;
5335         uint32_t mv_lsb = 0;
5336         uint32_t mp_msb = 0;
5337         uint8_t i = 0;
5338         int reg_index = 0;
5339         uint64_t vlan_mask = 0;
5340
5341         const uint8_t pool_mask_offset = 32;
5342         const uint8_t vlan_mask_offset = 32;
5343         const uint8_t dst_pool_offset = 8;
5344         const uint8_t rule_mr_offset  = 4;
5345         const uint8_t mirror_rule_mask = 0x0F;
5346
5347         struct ixgbe_mirror_info *mr_info =
5348                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5349         struct ixgbe_hw *hw =
5350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351         uint8_t mirror_type = 0;
5352
5353         if (ixgbe_vt_check(hw) < 0)
5354                 return -ENOTSUP;
5355
5356         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5357                 return -EINVAL;
5358
5359         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5360                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5361                             mirror_conf->rule_type);
5362                 return -EINVAL;
5363         }
5364
5365         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5366                 mirror_type |= IXGBE_MRCTL_VLME;
5367                 /* Check if vlan id is valid and find conresponding VLAN ID
5368                  * index in VLVF
5369                  */
5370                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5371                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5372                                 /* search vlan id related pool vlan filter
5373                                  * index
5374                                  */
5375                                 reg_index = ixgbe_find_vlvf_slot(
5376                                                 hw,
5377                                                 mirror_conf->vlan.vlan_id[i],
5378                                                 false);
5379                                 if (reg_index < 0)
5380                                         return -EINVAL;
5381                                 vlvf = IXGBE_READ_REG(hw,
5382                                                       IXGBE_VLVF(reg_index));
5383                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5384                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5385                                       mirror_conf->vlan.vlan_id[i]))
5386                                         vlan_mask |= (1ULL << reg_index);
5387                                 else
5388                                         return -EINVAL;
5389                         }
5390                 }
5391
5392                 if (on) {
5393                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5394                         mv_msb = vlan_mask >> vlan_mask_offset;
5395
5396                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5397                                                 mirror_conf->vlan.vlan_mask;
5398                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5399                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5400                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5401                                                 mirror_conf->vlan.vlan_id[i];
5402                         }
5403                 } else {
5404                         mv_lsb = 0;
5405                         mv_msb = 0;
5406                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5407                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5408                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5409                 }
5410         }
5411
5412         /**
5413          * if enable pool mirror, write related pool mask register,if disable
5414          * pool mirror, clear PFMRVM register
5415          */
5416         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5417                 mirror_type |= IXGBE_MRCTL_VPME;
5418                 if (on) {
5419                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5420                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5421                         mr_info->mr_conf[rule_id].pool_mask =
5422                                         mirror_conf->pool_mask;
5423
5424                 } else {
5425                         mp_lsb = 0;
5426                         mp_msb = 0;
5427                         mr_info->mr_conf[rule_id].pool_mask = 0;
5428                 }
5429         }
5430         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5431                 mirror_type |= IXGBE_MRCTL_UPME;
5432         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5433                 mirror_type |= IXGBE_MRCTL_DPME;
5434
5435         /* read  mirror control register and recalculate it */
5436         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5437
5438         if (on) {
5439                 mr_ctl |= mirror_type;
5440                 mr_ctl &= mirror_rule_mask;
5441                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5442         } else {
5443                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5444         }
5445
5446         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5447         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5448
5449         /* write mirrror control  register */
5450         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5451
5452         /* write pool mirrror control  register */
5453         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5454                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5455                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5456                                 mp_msb);
5457         }
5458         /* write VLAN mirrror control  register */
5459         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5460                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5461                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5462                                 mv_msb);
5463         }
5464
5465         return 0;
5466 }
5467
5468 static int
5469 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5470 {
5471         int mr_ctl = 0;
5472         uint32_t lsb_val = 0;
5473         uint32_t msb_val = 0;
5474         const uint8_t rule_mr_offset = 4;
5475
5476         struct ixgbe_hw *hw =
5477                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5478         struct ixgbe_mirror_info *mr_info =
5479                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5480
5481         if (ixgbe_vt_check(hw) < 0)
5482                 return -ENOTSUP;
5483
5484         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5485                 return -EINVAL;
5486
5487         memset(&mr_info->mr_conf[rule_id], 0,
5488                sizeof(struct rte_eth_mirror_conf));
5489
5490         /* clear PFVMCTL register */
5491         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5492
5493         /* clear pool mask register */
5494         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5495         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5496
5497         /* clear vlan mask register */
5498         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5499         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5500
5501         return 0;
5502 }
5503
5504 static int
5505 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5506 {
5507         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5509         uint32_t mask;
5510         struct ixgbe_hw *hw =
5511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512
5513         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5514         mask |= (1 << IXGBE_MISC_VEC_ID);
5515         RTE_SET_USED(queue_id);
5516         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5517
5518         rte_intr_enable(intr_handle);
5519
5520         return 0;
5521 }
5522
5523 static int
5524 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5525 {
5526         uint32_t mask;
5527         struct ixgbe_hw *hw =
5528                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529
5530         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5531         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5532         RTE_SET_USED(queue_id);
5533         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5534
5535         return 0;
5536 }
5537
5538 static int
5539 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5540 {
5541         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5543         uint32_t mask;
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct ixgbe_interrupt *intr =
5547                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5548
5549         if (queue_id < 16) {
5550                 ixgbe_disable_intr(hw);
5551                 intr->mask |= (1 << queue_id);
5552                 ixgbe_enable_intr(dev);
5553         } else if (queue_id < 32) {
5554                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5555                 mask &= (1 << queue_id);
5556                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5557         } else if (queue_id < 64) {
5558                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5559                 mask &= (1 << (queue_id - 32));
5560                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5561         }
5562         rte_intr_enable(intr_handle);
5563
5564         return 0;
5565 }
5566
5567 static int
5568 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5569 {
5570         uint32_t mask;
5571         struct ixgbe_hw *hw =
5572                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5573         struct ixgbe_interrupt *intr =
5574                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5575
5576         if (queue_id < 16) {
5577                 ixgbe_disable_intr(hw);
5578                 intr->mask &= ~(1 << queue_id);
5579                 ixgbe_enable_intr(dev);
5580         } else if (queue_id < 32) {
5581                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5582                 mask &= ~(1 << queue_id);
5583                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5584         } else if (queue_id < 64) {
5585                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5586                 mask &= ~(1 << (queue_id - 32));
5587                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5588         }
5589
5590         return 0;
5591 }
5592
5593 static void
5594 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5595                      uint8_t queue, uint8_t msix_vector)
5596 {
5597         uint32_t tmp, idx;
5598
5599         if (direction == -1) {
5600                 /* other causes */
5601                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5602                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5603                 tmp &= ~0xFF;
5604                 tmp |= msix_vector;
5605                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5606         } else {
5607                 /* rx or tx cause */
5608                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5609                 idx = ((16 * (queue & 1)) + (8 * direction));
5610                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5611                 tmp &= ~(0xFF << idx);
5612                 tmp |= (msix_vector << idx);
5613                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5614         }
5615 }
5616
5617 /**
5618  * set the IVAR registers, mapping interrupt causes to vectors
5619  * @param hw
5620  *  pointer to ixgbe_hw struct
5621  * @direction
5622  *  0 for Rx, 1 for Tx, -1 for other causes
5623  * @queue
5624  *  queue to map the corresponding interrupt to
5625  * @msix_vector
5626  *  the vector to map to the corresponding queue
5627  */
5628 static void
5629 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5630                    uint8_t queue, uint8_t msix_vector)
5631 {
5632         uint32_t tmp, idx;
5633
5634         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5635         if (hw->mac.type == ixgbe_mac_82598EB) {
5636                 if (direction == -1)
5637                         direction = 0;
5638                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5639                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5640                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5641                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5642                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5643         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5644                         (hw->mac.type == ixgbe_mac_X540) ||
5645                         (hw->mac.type == ixgbe_mac_X550)) {
5646                 if (direction == -1) {
5647                         /* other causes */
5648                         idx = ((queue & 1) * 8);
5649                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5650                         tmp &= ~(0xFF << idx);
5651                         tmp |= (msix_vector << idx);
5652                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5653                 } else {
5654                         /* rx or tx causes */
5655                         idx = ((16 * (queue & 1)) + (8 * direction));
5656                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5657                         tmp &= ~(0xFF << idx);
5658                         tmp |= (msix_vector << idx);
5659                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5660                 }
5661         }
5662 }
5663
5664 static void
5665 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5666 {
5667         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5668         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5669         struct ixgbe_hw *hw =
5670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671         uint32_t q_idx;
5672         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5673
5674         /* Configure VF other cause ivar */
5675         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5676
5677         /* won't configure msix register if no mapping is done
5678          * between intr vector and event fd.
5679          */
5680         if (!rte_intr_dp_is_en(intr_handle))
5681                 return;
5682
5683         /* Configure all RX queues of VF */
5684         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5685                 /* Force all queue use vector 0,
5686                  * as IXGBE_VF_MAXMSIVECOTR = 1
5687                  */
5688                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5689                 intr_handle->intr_vec[q_idx] = vector_idx;
5690         }
5691 }
5692
5693 /**
5694  * Sets up the hardware to properly generate MSI-X interrupts
5695  * @hw
5696  *  board private structure
5697  */
5698 static void
5699 ixgbe_configure_msix(struct rte_eth_dev *dev)
5700 {
5701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5703         struct ixgbe_hw *hw =
5704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5706         uint32_t vec = IXGBE_MISC_VEC_ID;
5707         uint32_t mask;
5708         uint32_t gpie;
5709
5710         /* won't configure msix register if no mapping is done
5711          * between intr vector and event fd
5712          */
5713         if (!rte_intr_dp_is_en(intr_handle))
5714                 return;
5715
5716         if (rte_intr_allow_others(intr_handle))
5717                 vec = base = IXGBE_RX_VEC_START;
5718
5719         /* setup GPIE for MSI-x mode */
5720         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5721         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5722                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5723         /* auto clearing and auto setting corresponding bits in EIMS
5724          * when MSI-X interrupt is triggered
5725          */
5726         if (hw->mac.type == ixgbe_mac_82598EB) {
5727                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5728         } else {
5729                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5730                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5731         }
5732         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5733
5734         /* Populate the IVAR table and set the ITR values to the
5735          * corresponding register.
5736          */
5737         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5738              queue_id++) {
5739                 /* by default, 1:1 mapping */
5740                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5741                 intr_handle->intr_vec[queue_id] = vec;
5742                 if (vec < base + intr_handle->nb_efd - 1)
5743                         vec++;
5744         }
5745
5746         switch (hw->mac.type) {
5747         case ixgbe_mac_82598EB:
5748                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5749                                    IXGBE_MISC_VEC_ID);
5750                 break;
5751         case ixgbe_mac_82599EB:
5752         case ixgbe_mac_X540:
5753         case ixgbe_mac_X550:
5754                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5755                 break;
5756         default:
5757                 break;
5758         }
5759         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5760                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5761
5762         /* set up to autoclear timer, and the vectors */
5763         mask = IXGBE_EIMS_ENABLE_MASK;
5764         mask &= ~(IXGBE_EIMS_OTHER |
5765                   IXGBE_EIMS_MAILBOX |
5766                   IXGBE_EIMS_LSC);
5767
5768         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5769 }
5770
5771 int
5772 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5773                            uint16_t queue_idx, uint16_t tx_rate)
5774 {
5775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t rf_dec, rf_int;
5777         uint32_t bcnrc_val;
5778         uint16_t link_speed = dev->data->dev_link.link_speed;
5779
5780         if (queue_idx >= hw->mac.max_tx_queues)
5781                 return -EINVAL;
5782
5783         if (tx_rate != 0) {
5784                 /* Calculate the rate factor values to set */
5785                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5786                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5787                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5788
5789                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5790                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5791                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5792                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5793         } else {
5794                 bcnrc_val = 0;
5795         }
5796
5797         /*
5798          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5799          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5800          * set as 0x4.
5801          */
5802         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5803                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5804                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5805                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5806                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5807         else
5808                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5809                         IXGBE_MMW_SIZE_DEFAULT);
5810
5811         /* Set RTTBCNRC of queue X */
5812         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5813         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5814         IXGBE_WRITE_FLUSH(hw);
5815
5816         return 0;
5817 }
5818
5819 static int
5820 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5821                      __attribute__((unused)) uint32_t index,
5822                      __attribute__((unused)) uint32_t pool)
5823 {
5824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825         int diag;
5826
5827         /*
5828          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5829          * operation. Trap this case to avoid exhausting the [very limited]
5830          * set of PF resources used to store VF MAC addresses.
5831          */
5832         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5833                 return -1;
5834         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5835         if (diag != 0)
5836                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5837                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5838                             mac_addr->addr_bytes[0],
5839                             mac_addr->addr_bytes[1],
5840                             mac_addr->addr_bytes[2],
5841                             mac_addr->addr_bytes[3],
5842                             mac_addr->addr_bytes[4],
5843                             mac_addr->addr_bytes[5],
5844                             diag);
5845         return diag;
5846 }
5847
5848 static void
5849 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5853         struct ether_addr *mac_addr;
5854         uint32_t i;
5855         int diag;
5856
5857         /*
5858          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5859          * not support the deletion of a given MAC address.
5860          * Instead, it imposes to delete all MAC addresses, then to add again
5861          * all MAC addresses with the exception of the one to be deleted.
5862          */
5863         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5864
5865         /*
5866          * Add again all MAC addresses, with the exception of the deleted one
5867          * and of the permanent MAC address.
5868          */
5869         for (i = 0, mac_addr = dev->data->mac_addrs;
5870              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5871                 /* Skip the deleted MAC address */
5872                 if (i == index)
5873                         continue;
5874                 /* Skip NULL MAC addresses */
5875                 if (is_zero_ether_addr(mac_addr))
5876                         continue;
5877                 /* Skip the permanent MAC address */
5878                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5879                         continue;
5880                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5881                 if (diag != 0)
5882                         PMD_DRV_LOG(ERR,
5883                                     "Adding again MAC address "
5884                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5885                                     "diag=%d",
5886                                     mac_addr->addr_bytes[0],
5887                                     mac_addr->addr_bytes[1],
5888                                     mac_addr->addr_bytes[2],
5889                                     mac_addr->addr_bytes[3],
5890                                     mac_addr->addr_bytes[4],
5891                                     mac_addr->addr_bytes[5],
5892                                     diag);
5893         }
5894 }
5895
5896 static void
5897 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5898 {
5899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900
5901         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5902 }
5903
5904 int
5905 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5906                         struct rte_eth_syn_filter *filter,
5907                         bool add)
5908 {
5909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5910         struct ixgbe_filter_info *filter_info =
5911                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5912         uint32_t syn_info;
5913         uint32_t synqf;
5914
5915         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5916                 return -EINVAL;
5917
5918         syn_info = filter_info->syn_info;
5919
5920         if (add) {
5921                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5922                         return -EINVAL;
5923                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5924                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5925
5926                 if (filter->hig_pri)
5927                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5928                 else
5929                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5930         } else {
5931                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5932                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5933                         return -ENOENT;
5934                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5935         }
5936
5937         filter_info->syn_info = synqf;
5938         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5939         IXGBE_WRITE_FLUSH(hw);
5940         return 0;
5941 }
5942
5943 static int
5944 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5945                         struct rte_eth_syn_filter *filter)
5946 {
5947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5949
5950         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5951                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5952                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5953                 return 0;
5954         }
5955         return -ENOENT;
5956 }
5957
5958 static int
5959 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5960                         enum rte_filter_op filter_op,
5961                         void *arg)
5962 {
5963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964         int ret;
5965
5966         MAC_TYPE_FILTER_SUP(hw->mac.type);
5967
5968         if (filter_op == RTE_ETH_FILTER_NOP)
5969                 return 0;
5970
5971         if (arg == NULL) {
5972                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5973                             filter_op);
5974                 return -EINVAL;
5975         }
5976
5977         switch (filter_op) {
5978         case RTE_ETH_FILTER_ADD:
5979                 ret = ixgbe_syn_filter_set(dev,
5980                                 (struct rte_eth_syn_filter *)arg,
5981                                 TRUE);
5982                 break;
5983         case RTE_ETH_FILTER_DELETE:
5984                 ret = ixgbe_syn_filter_set(dev,
5985                                 (struct rte_eth_syn_filter *)arg,
5986                                 FALSE);
5987                 break;
5988         case RTE_ETH_FILTER_GET:
5989                 ret = ixgbe_syn_filter_get(dev,
5990                                 (struct rte_eth_syn_filter *)arg);
5991                 break;
5992         default:
5993                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5994                 ret = -EINVAL;
5995                 break;
5996         }
5997
5998         return ret;
5999 }
6000
6001
6002 static inline enum ixgbe_5tuple_protocol
6003 convert_protocol_type(uint8_t protocol_value)
6004 {
6005         if (protocol_value == IPPROTO_TCP)
6006                 return IXGBE_FILTER_PROTOCOL_TCP;
6007         else if (protocol_value == IPPROTO_UDP)
6008                 return IXGBE_FILTER_PROTOCOL_UDP;
6009         else if (protocol_value == IPPROTO_SCTP)
6010                 return IXGBE_FILTER_PROTOCOL_SCTP;
6011         else
6012                 return IXGBE_FILTER_PROTOCOL_NONE;
6013 }
6014
6015 /* inject a 5-tuple filter to HW */
6016 static inline void
6017 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6018                            struct ixgbe_5tuple_filter *filter)
6019 {
6020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6021         int i;
6022         uint32_t ftqf, sdpqf;
6023         uint32_t l34timir = 0;
6024         uint8_t mask = 0xff;
6025
6026         i = filter->index;
6027
6028         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6029                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6030         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6031
6032         ftqf = (uint32_t)(filter->filter_info.proto &
6033                 IXGBE_FTQF_PROTOCOL_MASK);
6034         ftqf |= (uint32_t)((filter->filter_info.priority &
6035                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6036         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6037                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6038         if (filter->filter_info.dst_ip_mask == 0)
6039                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6040         if (filter->filter_info.src_port_mask == 0)
6041                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6042         if (filter->filter_info.dst_port_mask == 0)
6043                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6044         if (filter->filter_info.proto_mask == 0)
6045                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6046         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6047         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6048         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6049
6050         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6051         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6052         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6053         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6054
6055         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6056         l34timir |= (uint32_t)(filter->queue <<
6057                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6058         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6059 }
6060
6061 /*
6062  * add a 5tuple filter
6063  *
6064  * @param
6065  * dev: Pointer to struct rte_eth_dev.
6066  * index: the index the filter allocates.
6067  * filter: ponter to the filter that will be added.
6068  * rx_queue: the queue id the filter assigned to.
6069  *
6070  * @return
6071  *    - On success, zero.
6072  *    - On failure, a negative value.
6073  */
6074 static int
6075 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6076                         struct ixgbe_5tuple_filter *filter)
6077 {
6078         struct ixgbe_filter_info *filter_info =
6079                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6080         int i, idx, shift;
6081
6082         /*
6083          * look for an unused 5tuple filter index,
6084          * and insert the filter to list.
6085          */
6086         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6087                 idx = i / (sizeof(uint32_t) * NBBY);
6088                 shift = i % (sizeof(uint32_t) * NBBY);
6089                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6090                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6091                         filter->index = i;
6092                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6093                                           filter,
6094                                           entries);
6095                         break;
6096                 }
6097         }
6098         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6099                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6100                 return -ENOSYS;
6101         }
6102
6103         ixgbe_inject_5tuple_filter(dev, filter);
6104
6105         return 0;
6106 }
6107
6108 /*
6109  * remove a 5tuple filter
6110  *
6111  * @param
6112  * dev: Pointer to struct rte_eth_dev.
6113  * filter: the pointer of the filter will be removed.
6114  */
6115 static void
6116 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6117                         struct ixgbe_5tuple_filter *filter)
6118 {
6119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6120         struct ixgbe_filter_info *filter_info =
6121                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6122         uint16_t index = filter->index;
6123
6124         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6125                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6126         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6127         rte_free(filter);
6128
6129         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6130         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6131         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6132         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6133         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6134 }
6135
6136 static int
6137 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6138 {
6139         struct ixgbe_hw *hw;
6140         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6141         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6142
6143         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6144
6145         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6146                 return -EINVAL;
6147
6148         /* refuse mtu that requires the support of scattered packets when this
6149          * feature has not been enabled before.
6150          */
6151         if (!rx_conf->enable_scatter &&
6152             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6153              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6154                 return -EINVAL;
6155
6156         /*
6157          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6158          * request of the version 2.0 of the mailbox API.
6159          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6160          * of the mailbox API.
6161          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6162          * prior to 3.11.33 which contains the following change:
6163          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6164          */
6165         ixgbevf_rlpml_set_vf(hw, max_frame);
6166
6167         /* update max frame size */
6168         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6169         return 0;
6170 }
6171
6172 static inline struct ixgbe_5tuple_filter *
6173 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6174                         struct ixgbe_5tuple_filter_info *key)
6175 {
6176         struct ixgbe_5tuple_filter *it;
6177
6178         TAILQ_FOREACH(it, filter_list, entries) {
6179                 if (memcmp(key, &it->filter_info,
6180                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6181                         return it;
6182                 }
6183         }
6184         return NULL;
6185 }
6186
6187 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6188 static inline int
6189 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6190                         struct ixgbe_5tuple_filter_info *filter_info)
6191 {
6192         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6193                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6194                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6195                 return -EINVAL;
6196
6197         switch (filter->dst_ip_mask) {
6198         case UINT32_MAX:
6199                 filter_info->dst_ip_mask = 0;
6200                 filter_info->dst_ip = filter->dst_ip;
6201                 break;
6202         case 0:
6203                 filter_info->dst_ip_mask = 1;
6204                 break;
6205         default:
6206                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6207                 return -EINVAL;
6208         }
6209
6210         switch (filter->src_ip_mask) {
6211         case UINT32_MAX:
6212                 filter_info->src_ip_mask = 0;
6213                 filter_info->src_ip = filter->src_ip;
6214                 break;
6215         case 0:
6216                 filter_info->src_ip_mask = 1;
6217                 break;
6218         default:
6219                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6220                 return -EINVAL;
6221         }
6222
6223         switch (filter->dst_port_mask) {
6224         case UINT16_MAX:
6225                 filter_info->dst_port_mask = 0;
6226                 filter_info->dst_port = filter->dst_port;
6227                 break;
6228         case 0:
6229                 filter_info->dst_port_mask = 1;
6230                 break;
6231         default:
6232                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6233                 return -EINVAL;
6234         }
6235
6236         switch (filter->src_port_mask) {
6237         case UINT16_MAX:
6238                 filter_info->src_port_mask = 0;
6239                 filter_info->src_port = filter->src_port;
6240                 break;
6241         case 0:
6242                 filter_info->src_port_mask = 1;
6243                 break;
6244         default:
6245                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6246                 return -EINVAL;
6247         }
6248
6249         switch (filter->proto_mask) {
6250         case UINT8_MAX:
6251                 filter_info->proto_mask = 0;
6252                 filter_info->proto =
6253                         convert_protocol_type(filter->proto);
6254                 break;
6255         case 0:
6256                 filter_info->proto_mask = 1;
6257                 break;
6258         default:
6259                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6260                 return -EINVAL;
6261         }
6262
6263         filter_info->priority = (uint8_t)filter->priority;
6264         return 0;
6265 }
6266
6267 /*
6268  * add or delete a ntuple filter
6269  *
6270  * @param
6271  * dev: Pointer to struct rte_eth_dev.
6272  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6273  * add: if true, add filter, if false, remove filter
6274  *
6275  * @return
6276  *    - On success, zero.
6277  *    - On failure, a negative value.
6278  */
6279 int
6280 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6281                         struct rte_eth_ntuple_filter *ntuple_filter,
6282                         bool add)
6283 {
6284         struct ixgbe_filter_info *filter_info =
6285                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6286         struct ixgbe_5tuple_filter_info filter_5tuple;
6287         struct ixgbe_5tuple_filter *filter;
6288         int ret;
6289
6290         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6291                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6292                 return -EINVAL;
6293         }
6294
6295         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6296         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6297         if (ret < 0)
6298                 return ret;
6299
6300         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6301                                          &filter_5tuple);
6302         if (filter != NULL && add) {
6303                 PMD_DRV_LOG(ERR, "filter exists.");
6304                 return -EEXIST;
6305         }
6306         if (filter == NULL && !add) {
6307                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6308                 return -ENOENT;
6309         }
6310
6311         if (add) {
6312                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6313                                 sizeof(struct ixgbe_5tuple_filter), 0);
6314                 if (filter == NULL)
6315                         return -ENOMEM;
6316                 (void)rte_memcpy(&filter->filter_info,
6317                                  &filter_5tuple,
6318                                  sizeof(struct ixgbe_5tuple_filter_info));
6319                 filter->queue = ntuple_filter->queue;
6320                 ret = ixgbe_add_5tuple_filter(dev, filter);
6321                 if (ret < 0) {
6322                         rte_free(filter);
6323                         return ret;
6324                 }
6325         } else
6326                 ixgbe_remove_5tuple_filter(dev, filter);
6327
6328         return 0;
6329 }
6330
6331 /*
6332  * get a ntuple filter
6333  *
6334  * @param
6335  * dev: Pointer to struct rte_eth_dev.
6336  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6337  *
6338  * @return
6339  *    - On success, zero.
6340  *    - On failure, a negative value.
6341  */
6342 static int
6343 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6344                         struct rte_eth_ntuple_filter *ntuple_filter)
6345 {
6346         struct ixgbe_filter_info *filter_info =
6347                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6348         struct ixgbe_5tuple_filter_info filter_5tuple;
6349         struct ixgbe_5tuple_filter *filter;
6350         int ret;
6351
6352         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6353                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6354                 return -EINVAL;
6355         }
6356
6357         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6358         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6359         if (ret < 0)
6360                 return ret;
6361
6362         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6363                                          &filter_5tuple);
6364         if (filter == NULL) {
6365                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6366                 return -ENOENT;
6367         }
6368         ntuple_filter->queue = filter->queue;
6369         return 0;
6370 }
6371
6372 /*
6373  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6374  * @dev: pointer to rte_eth_dev structure
6375  * @filter_op:operation will be taken.
6376  * @arg: a pointer to specific structure corresponding to the filter_op
6377  *
6378  * @return
6379  *    - On success, zero.
6380  *    - On failure, a negative value.
6381  */
6382 static int
6383 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6384                                 enum rte_filter_op filter_op,
6385                                 void *arg)
6386 {
6387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6388         int ret;
6389
6390         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6391
6392         if (filter_op == RTE_ETH_FILTER_NOP)
6393                 return 0;
6394
6395         if (arg == NULL) {
6396                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6397                             filter_op);
6398                 return -EINVAL;
6399         }
6400
6401         switch (filter_op) {
6402         case RTE_ETH_FILTER_ADD:
6403                 ret = ixgbe_add_del_ntuple_filter(dev,
6404                         (struct rte_eth_ntuple_filter *)arg,
6405                         TRUE);
6406                 break;
6407         case RTE_ETH_FILTER_DELETE:
6408                 ret = ixgbe_add_del_ntuple_filter(dev,
6409                         (struct rte_eth_ntuple_filter *)arg,
6410                         FALSE);
6411                 break;
6412         case RTE_ETH_FILTER_GET:
6413                 ret = ixgbe_get_ntuple_filter(dev,
6414                         (struct rte_eth_ntuple_filter *)arg);
6415                 break;
6416         default:
6417                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6418                 ret = -EINVAL;
6419                 break;
6420         }
6421         return ret;
6422 }
6423
6424 int
6425 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6426                         struct rte_eth_ethertype_filter *filter,
6427                         bool add)
6428 {
6429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430         struct ixgbe_filter_info *filter_info =
6431                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6432         uint32_t etqf = 0;
6433         uint32_t etqs = 0;
6434         int ret;
6435         struct ixgbe_ethertype_filter ethertype_filter;
6436
6437         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6438                 return -EINVAL;
6439
6440         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6441                 filter->ether_type == ETHER_TYPE_IPv6) {
6442                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6443                         " ethertype filter.", filter->ether_type);
6444                 return -EINVAL;
6445         }
6446
6447         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6448                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6449                 return -EINVAL;
6450         }
6451         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6452                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6453                 return -EINVAL;
6454         }
6455
6456         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6457         if (ret >= 0 && add) {
6458                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6459                             filter->ether_type);
6460                 return -EEXIST;
6461         }
6462         if (ret < 0 && !add) {
6463                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6464                             filter->ether_type);
6465                 return -ENOENT;
6466         }
6467
6468         if (add) {
6469                 etqf = IXGBE_ETQF_FILTER_EN;
6470                 etqf |= (uint32_t)filter->ether_type;
6471                 etqs |= (uint32_t)((filter->queue <<
6472                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6473                                     IXGBE_ETQS_RX_QUEUE);
6474                 etqs |= IXGBE_ETQS_QUEUE_EN;
6475
6476                 ethertype_filter.ethertype = filter->ether_type;
6477                 ethertype_filter.etqf = etqf;
6478                 ethertype_filter.etqs = etqs;
6479                 ethertype_filter.conf = FALSE;
6480                 ret = ixgbe_ethertype_filter_insert(filter_info,
6481                                                     &ethertype_filter);
6482                 if (ret < 0) {
6483                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6484                         return -ENOSPC;
6485                 }
6486         } else {
6487                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6488                 if (ret < 0)
6489                         return -ENOSYS;
6490         }
6491         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6492         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6493         IXGBE_WRITE_FLUSH(hw);
6494
6495         return 0;
6496 }
6497
6498 static int
6499 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6500                         struct rte_eth_ethertype_filter *filter)
6501 {
6502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6503         struct ixgbe_filter_info *filter_info =
6504                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6505         uint32_t etqf, etqs;
6506         int ret;
6507
6508         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6509         if (ret < 0) {
6510                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6511                             filter->ether_type);
6512                 return -ENOENT;
6513         }
6514
6515         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6516         if (etqf & IXGBE_ETQF_FILTER_EN) {
6517                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6518                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6519                 filter->flags = 0;
6520                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6521                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6522                 return 0;
6523         }
6524         return -ENOENT;
6525 }
6526
6527 /*
6528  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6529  * @dev: pointer to rte_eth_dev structure
6530  * @filter_op:operation will be taken.
6531  * @arg: a pointer to specific structure corresponding to the filter_op
6532  */
6533 static int
6534 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6535                                 enum rte_filter_op filter_op,
6536                                 void *arg)
6537 {
6538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6539         int ret;
6540
6541         MAC_TYPE_FILTER_SUP(hw->mac.type);
6542
6543         if (filter_op == RTE_ETH_FILTER_NOP)
6544                 return 0;
6545
6546         if (arg == NULL) {
6547                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6548                             filter_op);
6549                 return -EINVAL;
6550         }
6551
6552         switch (filter_op) {
6553         case RTE_ETH_FILTER_ADD:
6554                 ret = ixgbe_add_del_ethertype_filter(dev,
6555                         (struct rte_eth_ethertype_filter *)arg,
6556                         TRUE);
6557                 break;
6558         case RTE_ETH_FILTER_DELETE:
6559                 ret = ixgbe_add_del_ethertype_filter(dev,
6560                         (struct rte_eth_ethertype_filter *)arg,
6561                         FALSE);
6562                 break;
6563         case RTE_ETH_FILTER_GET:
6564                 ret = ixgbe_get_ethertype_filter(dev,
6565                         (struct rte_eth_ethertype_filter *)arg);
6566                 break;
6567         default:
6568                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6569                 ret = -EINVAL;
6570                 break;
6571         }
6572         return ret;
6573 }
6574
6575 static int
6576 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6577                      enum rte_filter_type filter_type,
6578                      enum rte_filter_op filter_op,
6579                      void *arg)
6580 {
6581         int ret = 0;
6582
6583         switch (filter_type) {
6584         case RTE_ETH_FILTER_NTUPLE:
6585                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6586                 break;
6587         case RTE_ETH_FILTER_ETHERTYPE:
6588                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6589                 break;
6590         case RTE_ETH_FILTER_SYN:
6591                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6592                 break;
6593         case RTE_ETH_FILTER_FDIR:
6594                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6595                 break;
6596         case RTE_ETH_FILTER_L2_TUNNEL:
6597                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6598                 break;
6599         case RTE_ETH_FILTER_GENERIC:
6600                 if (filter_op != RTE_ETH_FILTER_GET)
6601                         return -EINVAL;
6602                 *(const void **)arg = &ixgbe_flow_ops;
6603                 break;
6604         default:
6605                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6606                                                         filter_type);
6607                 ret = -EINVAL;
6608                 break;
6609         }
6610
6611         return ret;
6612 }
6613
6614 static u8 *
6615 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6616                         u8 **mc_addr_ptr, u32 *vmdq)
6617 {
6618         u8 *mc_addr;
6619
6620         *vmdq = 0;
6621         mc_addr = *mc_addr_ptr;
6622         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6623         return mc_addr;
6624 }
6625
6626 static int
6627 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6628                           struct ether_addr *mc_addr_set,
6629                           uint32_t nb_mc_addr)
6630 {
6631         struct ixgbe_hw *hw;
6632         u8 *mc_addr_list;
6633
6634         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6635         mc_addr_list = (u8 *)mc_addr_set;
6636         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6637                                          ixgbe_dev_addr_list_itr, TRUE);
6638 }
6639
6640 static uint64_t
6641 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6642 {
6643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6644         uint64_t systime_cycles;
6645
6646         switch (hw->mac.type) {
6647         case ixgbe_mac_X550:
6648         case ixgbe_mac_X550EM_x:
6649         case ixgbe_mac_X550EM_a:
6650                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6651                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6652                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6653                                 * NSEC_PER_SEC;
6654                 break;
6655         default:
6656                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6657                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6658                                 << 32;
6659         }
6660
6661         return systime_cycles;
6662 }
6663
6664 static uint64_t
6665 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6666 {
6667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668         uint64_t rx_tstamp_cycles;
6669
6670         switch (hw->mac.type) {
6671         case ixgbe_mac_X550:
6672         case ixgbe_mac_X550EM_x:
6673         case ixgbe_mac_X550EM_a:
6674                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6675                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6676                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6677                                 * NSEC_PER_SEC;
6678                 break;
6679         default:
6680                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6681                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6682                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6683                                 << 32;
6684         }
6685
6686         return rx_tstamp_cycles;
6687 }
6688
6689 static uint64_t
6690 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6691 {
6692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693         uint64_t tx_tstamp_cycles;
6694
6695         switch (hw->mac.type) {
6696         case ixgbe_mac_X550:
6697         case ixgbe_mac_X550EM_x:
6698         case ixgbe_mac_X550EM_a:
6699                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6700                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6701                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6702                                 * NSEC_PER_SEC;
6703                 break;
6704         default:
6705                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6706                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6707                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6708                                 << 32;
6709         }
6710
6711         return tx_tstamp_cycles;
6712 }
6713
6714 static void
6715 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6716 {
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         struct ixgbe_adapter *adapter =
6719                 (struct ixgbe_adapter *)dev->data->dev_private;
6720         struct rte_eth_link link;
6721         uint32_t incval = 0;
6722         uint32_t shift = 0;
6723
6724         /* Get current link speed. */
6725         memset(&link, 0, sizeof(link));
6726         ixgbe_dev_link_update(dev, 1);
6727         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6728
6729         switch (link.link_speed) {
6730         case ETH_SPEED_NUM_100M:
6731                 incval = IXGBE_INCVAL_100;
6732                 shift = IXGBE_INCVAL_SHIFT_100;
6733                 break;
6734         case ETH_SPEED_NUM_1G:
6735                 incval = IXGBE_INCVAL_1GB;
6736                 shift = IXGBE_INCVAL_SHIFT_1GB;
6737                 break;
6738         case ETH_SPEED_NUM_10G:
6739         default:
6740                 incval = IXGBE_INCVAL_10GB;
6741                 shift = IXGBE_INCVAL_SHIFT_10GB;
6742                 break;
6743         }
6744
6745         switch (hw->mac.type) {
6746         case ixgbe_mac_X550:
6747         case ixgbe_mac_X550EM_x:
6748         case ixgbe_mac_X550EM_a:
6749                 /* Independent of link speed. */
6750                 incval = 1;
6751                 /* Cycles read will be interpreted as ns. */
6752                 shift = 0;
6753                 /* Fall-through */
6754         case ixgbe_mac_X540:
6755                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6756                 break;
6757         case ixgbe_mac_82599EB:
6758                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6759                 shift -= IXGBE_INCVAL_SHIFT_82599;
6760                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6761                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6762                 break;
6763         default:
6764                 /* Not supported. */
6765                 return;
6766         }
6767
6768         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6769         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6770         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6771
6772         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6773         adapter->systime_tc.cc_shift = shift;
6774         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6775
6776         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6777         adapter->rx_tstamp_tc.cc_shift = shift;
6778         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6779
6780         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6781         adapter->tx_tstamp_tc.cc_shift = shift;
6782         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6783 }
6784
6785 static int
6786 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6787 {
6788         struct ixgbe_adapter *adapter =
6789                         (struct ixgbe_adapter *)dev->data->dev_private;
6790
6791         adapter->systime_tc.nsec += delta;
6792         adapter->rx_tstamp_tc.nsec += delta;
6793         adapter->tx_tstamp_tc.nsec += delta;
6794
6795         return 0;
6796 }
6797
6798 static int
6799 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6800 {
6801         uint64_t ns;
6802         struct ixgbe_adapter *adapter =
6803                         (struct ixgbe_adapter *)dev->data->dev_private;
6804
6805         ns = rte_timespec_to_ns(ts);
6806         /* Set the timecounters to a new value. */
6807         adapter->systime_tc.nsec = ns;
6808         adapter->rx_tstamp_tc.nsec = ns;
6809         adapter->tx_tstamp_tc.nsec = ns;
6810
6811         return 0;
6812 }
6813
6814 static int
6815 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6816 {
6817         uint64_t ns, systime_cycles;
6818         struct ixgbe_adapter *adapter =
6819                         (struct ixgbe_adapter *)dev->data->dev_private;
6820
6821         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6822         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6823         *ts = rte_ns_to_timespec(ns);
6824
6825         return 0;
6826 }
6827
6828 static int
6829 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6830 {
6831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6832         uint32_t tsync_ctl;
6833         uint32_t tsauxc;
6834
6835         /* Stop the timesync system time. */
6836         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6837         /* Reset the timesync system time value. */
6838         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6839         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6840
6841         /* Enable system time for platforms where it isn't on by default. */
6842         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6843         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6844         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6845
6846         ixgbe_start_timecounters(dev);
6847
6848         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6849         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6850                         (ETHER_TYPE_1588 |
6851                          IXGBE_ETQF_FILTER_EN |
6852                          IXGBE_ETQF_1588));
6853
6854         /* Enable timestamping of received PTP packets. */
6855         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6856         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6857         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6858
6859         /* Enable timestamping of transmitted PTP packets. */
6860         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6861         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6862         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6863
6864         IXGBE_WRITE_FLUSH(hw);
6865
6866         return 0;
6867 }
6868
6869 static int
6870 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6871 {
6872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6873         uint32_t tsync_ctl;
6874
6875         /* Disable timestamping of transmitted PTP packets. */
6876         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6877         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6878         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6879
6880         /* Disable timestamping of received PTP packets. */
6881         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6882         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6883         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6884
6885         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6886         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6887
6888         /* Stop incrementating the System Time registers. */
6889         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6890
6891         return 0;
6892 }
6893
6894 static int
6895 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6896                                  struct timespec *timestamp,
6897                                  uint32_t flags __rte_unused)
6898 {
6899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900         struct ixgbe_adapter *adapter =
6901                 (struct ixgbe_adapter *)dev->data->dev_private;
6902         uint32_t tsync_rxctl;
6903         uint64_t rx_tstamp_cycles;
6904         uint64_t ns;
6905
6906         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6907         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6908                 return -EINVAL;
6909
6910         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6911         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6912         *timestamp = rte_ns_to_timespec(ns);
6913
6914         return  0;
6915 }
6916
6917 static int
6918 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6919                                  struct timespec *timestamp)
6920 {
6921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922         struct ixgbe_adapter *adapter =
6923                 (struct ixgbe_adapter *)dev->data->dev_private;
6924         uint32_t tsync_txctl;
6925         uint64_t tx_tstamp_cycles;
6926         uint64_t ns;
6927
6928         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6929         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6930                 return -EINVAL;
6931
6932         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6933         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6934         *timestamp = rte_ns_to_timespec(ns);
6935
6936         return 0;
6937 }
6938
6939 static int
6940 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6941 {
6942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6943         int count = 0;
6944         int g_ind = 0;
6945         const struct reg_info *reg_group;
6946         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6947                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6948
6949         while ((reg_group = reg_set[g_ind++]))
6950                 count += ixgbe_regs_group_count(reg_group);
6951
6952         return count;
6953 }
6954
6955 static int
6956 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6957 {
6958         int count = 0;
6959         int g_ind = 0;
6960         const struct reg_info *reg_group;
6961
6962         while ((reg_group = ixgbevf_regs[g_ind++]))
6963                 count += ixgbe_regs_group_count(reg_group);
6964
6965         return count;
6966 }
6967
6968 static int
6969 ixgbe_get_regs(struct rte_eth_dev *dev,
6970               struct rte_dev_reg_info *regs)
6971 {
6972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973         uint32_t *data = regs->data;
6974         int g_ind = 0;
6975         int count = 0;
6976         const struct reg_info *reg_group;
6977         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6978                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6979
6980         if (data == NULL) {
6981                 regs->length = ixgbe_get_reg_length(dev);
6982                 regs->width = sizeof(uint32_t);
6983                 return 0;
6984         }
6985
6986         /* Support only full register dump */
6987         if ((regs->length == 0) ||
6988             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6989                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6990                         hw->device_id;
6991                 while ((reg_group = reg_set[g_ind++]))
6992                         count += ixgbe_read_regs_group(dev, &data[count],
6993                                 reg_group);
6994                 return 0;
6995         }
6996
6997         return -ENOTSUP;
6998 }
6999
7000 static int
7001 ixgbevf_get_regs(struct rte_eth_dev *dev,
7002                 struct rte_dev_reg_info *regs)
7003 {
7004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7005         uint32_t *data = regs->data;
7006         int g_ind = 0;
7007         int count = 0;
7008         const struct reg_info *reg_group;
7009
7010         if (data == NULL) {
7011                 regs->length = ixgbevf_get_reg_length(dev);
7012                 regs->width = sizeof(uint32_t);
7013                 return 0;
7014         }
7015
7016         /* Support only full register dump */
7017         if ((regs->length == 0) ||
7018             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7019                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7020                         hw->device_id;
7021                 while ((reg_group = ixgbevf_regs[g_ind++]))
7022                         count += ixgbe_read_regs_group(dev, &data[count],
7023                                                       reg_group);
7024                 return 0;
7025         }
7026
7027         return -ENOTSUP;
7028 }
7029
7030 static int
7031 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7032 {
7033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034
7035         /* Return unit is byte count */
7036         return hw->eeprom.word_size * 2;
7037 }
7038
7039 static int
7040 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7041                 struct rte_dev_eeprom_info *in_eeprom)
7042 {
7043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7044         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7045         uint16_t *data = in_eeprom->data;
7046         int first, length;
7047
7048         first = in_eeprom->offset >> 1;
7049         length = in_eeprom->length >> 1;
7050         if ((first > hw->eeprom.word_size) ||
7051             ((first + length) > hw->eeprom.word_size))
7052                 return -EINVAL;
7053
7054         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7055
7056         return eeprom->ops.read_buffer(hw, first, length, data);
7057 }
7058
7059 static int
7060 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7061                 struct rte_dev_eeprom_info *in_eeprom)
7062 {
7063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7065         uint16_t *data = in_eeprom->data;
7066         int first, length;
7067
7068         first = in_eeprom->offset >> 1;
7069         length = in_eeprom->length >> 1;
7070         if ((first > hw->eeprom.word_size) ||
7071             ((first + length) > hw->eeprom.word_size))
7072                 return -EINVAL;
7073
7074         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7075
7076         return eeprom->ops.write_buffer(hw,  first, length, data);
7077 }
7078
7079 uint16_t
7080 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7081         switch (mac_type) {
7082         case ixgbe_mac_X550:
7083         case ixgbe_mac_X550EM_x:
7084         case ixgbe_mac_X550EM_a:
7085                 return ETH_RSS_RETA_SIZE_512;
7086         case ixgbe_mac_X550_vf:
7087         case ixgbe_mac_X550EM_x_vf:
7088         case ixgbe_mac_X550EM_a_vf:
7089                 return ETH_RSS_RETA_SIZE_64;
7090         default:
7091                 return ETH_RSS_RETA_SIZE_128;
7092         }
7093 }
7094
7095 uint32_t
7096 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7097         switch (mac_type) {
7098         case ixgbe_mac_X550:
7099         case ixgbe_mac_X550EM_x:
7100         case ixgbe_mac_X550EM_a:
7101                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7102                         return IXGBE_RETA(reta_idx >> 2);
7103                 else
7104                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7105         case ixgbe_mac_X550_vf:
7106         case ixgbe_mac_X550EM_x_vf:
7107         case ixgbe_mac_X550EM_a_vf:
7108                 return IXGBE_VFRETA(reta_idx >> 2);
7109         default:
7110                 return IXGBE_RETA(reta_idx >> 2);
7111         }
7112 }
7113
7114 uint32_t
7115 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7116         switch (mac_type) {
7117         case ixgbe_mac_X550_vf:
7118         case ixgbe_mac_X550EM_x_vf:
7119         case ixgbe_mac_X550EM_a_vf:
7120                 return IXGBE_VFMRQC;
7121         default:
7122                 return IXGBE_MRQC;
7123         }
7124 }
7125
7126 uint32_t
7127 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7128         switch (mac_type) {
7129         case ixgbe_mac_X550_vf:
7130         case ixgbe_mac_X550EM_x_vf:
7131         case ixgbe_mac_X550EM_a_vf:
7132                 return IXGBE_VFRSSRK(i);
7133         default:
7134                 return IXGBE_RSSRK(i);
7135         }
7136 }
7137
7138 bool
7139 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7140         switch (mac_type) {
7141         case ixgbe_mac_82599_vf:
7142         case ixgbe_mac_X540_vf:
7143                 return 0;
7144         default:
7145                 return 1;
7146         }
7147 }
7148
7149 static int
7150 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7151                         struct rte_eth_dcb_info *dcb_info)
7152 {
7153         struct ixgbe_dcb_config *dcb_config =
7154                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7155         struct ixgbe_dcb_tc_config *tc;
7156         uint8_t i, j;
7157
7158         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7159                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7160         else
7161                 dcb_info->nb_tcs = 1;
7162
7163         if (dcb_config->vt_mode) { /* vt is enabled*/
7164                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7165                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7166                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7167                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7168                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7169                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7170                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7171                                                 i * dcb_info->nb_tcs + j;
7172                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7173                                 dcb_info->tc_queue.tc_txq[i][j].base =
7174                                                 i * dcb_info->nb_tcs + j;
7175                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7176                         }
7177                 }
7178         } else { /* vt is disabled*/
7179                 struct rte_eth_dcb_rx_conf *rx_conf =
7180                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7181                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7182                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7183                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7184                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7185                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7186                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7187                         }
7188                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7189                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7190                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7191                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7192                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7193                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7194                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7195                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7196                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7197                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7198                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7199                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7200                         }
7201                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7202                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7203                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7204                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7205                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7206                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7207                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7208                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7209                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7210                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7211                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7212                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7213                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7214                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7215                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7216                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7217                 }
7218         }
7219         for (i = 0; i < dcb_info->nb_tcs; i++) {
7220                 tc = &dcb_config->tc_config[i];
7221                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7222         }
7223         return 0;
7224 }
7225
7226 /* Update e-tag ether type */
7227 static int
7228 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7229                             uint16_t ether_type)
7230 {
7231         uint32_t etag_etype;
7232
7233         if (hw->mac.type != ixgbe_mac_X550 &&
7234             hw->mac.type != ixgbe_mac_X550EM_x &&
7235             hw->mac.type != ixgbe_mac_X550EM_a) {
7236                 return -ENOTSUP;
7237         }
7238
7239         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7240         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7241         etag_etype |= ether_type;
7242         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7243         IXGBE_WRITE_FLUSH(hw);
7244
7245         return 0;
7246 }
7247
7248 /* Config l2 tunnel ether type */
7249 static int
7250 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7251                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7252 {
7253         int ret = 0;
7254         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7255         struct ixgbe_l2_tn_info *l2_tn_info =
7256                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7257
7258         if (l2_tunnel == NULL)
7259                 return -EINVAL;
7260
7261         switch (l2_tunnel->l2_tunnel_type) {
7262         case RTE_L2_TUNNEL_TYPE_E_TAG:
7263                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7264                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7265                 break;
7266         default:
7267                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7268                 ret = -EINVAL;
7269                 break;
7270         }
7271
7272         return ret;
7273 }
7274
7275 /* Enable e-tag tunnel */
7276 static int
7277 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7278 {
7279         uint32_t etag_etype;
7280
7281         if (hw->mac.type != ixgbe_mac_X550 &&
7282             hw->mac.type != ixgbe_mac_X550EM_x &&
7283             hw->mac.type != ixgbe_mac_X550EM_a) {
7284                 return -ENOTSUP;
7285         }
7286
7287         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7288         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7289         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7290         IXGBE_WRITE_FLUSH(hw);
7291
7292         return 0;
7293 }
7294
7295 /* Enable l2 tunnel */
7296 static int
7297 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7298                            enum rte_eth_tunnel_type l2_tunnel_type)
7299 {
7300         int ret = 0;
7301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7302         struct ixgbe_l2_tn_info *l2_tn_info =
7303                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7304
7305         switch (l2_tunnel_type) {
7306         case RTE_L2_TUNNEL_TYPE_E_TAG:
7307                 l2_tn_info->e_tag_en = TRUE;
7308                 ret = ixgbe_e_tag_enable(hw);
7309                 break;
7310         default:
7311                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7312                 ret = -EINVAL;
7313                 break;
7314         }
7315
7316         return ret;
7317 }
7318
7319 /* Disable e-tag tunnel */
7320 static int
7321 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7322 {
7323         uint32_t etag_etype;
7324
7325         if (hw->mac.type != ixgbe_mac_X550 &&
7326             hw->mac.type != ixgbe_mac_X550EM_x &&
7327             hw->mac.type != ixgbe_mac_X550EM_a) {
7328                 return -ENOTSUP;
7329         }
7330
7331         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7332         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7333         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7334         IXGBE_WRITE_FLUSH(hw);
7335
7336         return 0;
7337 }
7338
7339 /* Disable l2 tunnel */
7340 static int
7341 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7342                             enum rte_eth_tunnel_type l2_tunnel_type)
7343 {
7344         int ret = 0;
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         struct ixgbe_l2_tn_info *l2_tn_info =
7347                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7348
7349         switch (l2_tunnel_type) {
7350         case RTE_L2_TUNNEL_TYPE_E_TAG:
7351                 l2_tn_info->e_tag_en = FALSE;
7352                 ret = ixgbe_e_tag_disable(hw);
7353                 break;
7354         default:
7355                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7356                 ret = -EINVAL;
7357                 break;
7358         }
7359
7360         return ret;
7361 }
7362
7363 static int
7364 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7365                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7366 {
7367         int ret = 0;
7368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7369         uint32_t i, rar_entries;
7370         uint32_t rar_low, rar_high;
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         rar_entries = ixgbe_get_num_rx_addrs(hw);
7379
7380         for (i = 1; i < rar_entries; i++) {
7381                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7382                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7383                 if ((rar_high & IXGBE_RAH_AV) &&
7384                     (rar_high & IXGBE_RAH_ADTYPE) &&
7385                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7386                      l2_tunnel->tunnel_id)) {
7387                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7388                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7389
7390                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7391
7392                         return ret;
7393                 }
7394         }
7395
7396         return ret;
7397 }
7398
7399 static int
7400 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7401                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7402 {
7403         int ret = 0;
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         uint32_t i, rar_entries;
7406         uint32_t rar_low, rar_high;
7407
7408         if (hw->mac.type != ixgbe_mac_X550 &&
7409             hw->mac.type != ixgbe_mac_X550EM_x &&
7410             hw->mac.type != ixgbe_mac_X550EM_a) {
7411                 return -ENOTSUP;
7412         }
7413
7414         /* One entry for one tunnel. Try to remove potential existing entry. */
7415         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7416
7417         rar_entries = ixgbe_get_num_rx_addrs(hw);
7418
7419         for (i = 1; i < rar_entries; i++) {
7420                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7421                 if (rar_high & IXGBE_RAH_AV) {
7422                         continue;
7423                 } else {
7424                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7425                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7426                         rar_low = l2_tunnel->tunnel_id;
7427
7428                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7429                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7430
7431                         return ret;
7432                 }
7433         }
7434
7435         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7436                      " Please remove a rule before adding a new one.");
7437         return -EINVAL;
7438 }
7439
7440 static inline struct ixgbe_l2_tn_filter *
7441 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7442                           struct ixgbe_l2_tn_key *key)
7443 {
7444         int ret;
7445
7446         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7447         if (ret < 0)
7448                 return NULL;
7449
7450         return l2_tn_info->hash_map[ret];
7451 }
7452
7453 static inline int
7454 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7455                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7456 {
7457         int ret;
7458
7459         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7460                                &l2_tn_filter->key);
7461
7462         if (ret < 0) {
7463                 PMD_DRV_LOG(ERR,
7464                             "Failed to insert L2 tunnel filter"
7465                             " to hash table %d!",
7466                             ret);
7467                 return ret;
7468         }
7469
7470         l2_tn_info->hash_map[ret] = l2_tn_filter;
7471
7472         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7473
7474         return 0;
7475 }
7476
7477 static inline int
7478 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7479                           struct ixgbe_l2_tn_key *key)
7480 {
7481         int ret;
7482         struct ixgbe_l2_tn_filter *l2_tn_filter;
7483
7484         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7485
7486         if (ret < 0) {
7487                 PMD_DRV_LOG(ERR,
7488                             "No such L2 tunnel filter to delete %d!",
7489                             ret);
7490                 return ret;
7491         }
7492
7493         l2_tn_filter = l2_tn_info->hash_map[ret];
7494         l2_tn_info->hash_map[ret] = NULL;
7495
7496         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7497         rte_free(l2_tn_filter);
7498
7499         return 0;
7500 }
7501
7502 /* Add l2 tunnel filter */
7503 int
7504 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7505                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7506                                bool restore)
7507 {
7508         int ret;
7509         struct ixgbe_l2_tn_info *l2_tn_info =
7510                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7511         struct ixgbe_l2_tn_key key;
7512         struct ixgbe_l2_tn_filter *node;
7513
7514         if (!restore) {
7515                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7516                 key.tn_id = l2_tunnel->tunnel_id;
7517
7518                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7519
7520                 if (node) {
7521                         PMD_DRV_LOG(ERR,
7522                                     "The L2 tunnel filter already exists!");
7523                         return -EINVAL;
7524                 }
7525
7526                 node = rte_zmalloc("ixgbe_l2_tn",
7527                                    sizeof(struct ixgbe_l2_tn_filter),
7528                                    0);
7529                 if (!node)
7530                         return -ENOMEM;
7531
7532                 (void)rte_memcpy(&node->key,
7533                                  &key,
7534                                  sizeof(struct ixgbe_l2_tn_key));
7535                 node->pool = l2_tunnel->pool;
7536                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7537                 if (ret < 0) {
7538                         rte_free(node);
7539                         return ret;
7540                 }
7541         }
7542
7543         switch (l2_tunnel->l2_tunnel_type) {
7544         case RTE_L2_TUNNEL_TYPE_E_TAG:
7545                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7546                 break;
7547         default:
7548                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7549                 ret = -EINVAL;
7550                 break;
7551         }
7552
7553         if ((!restore) && (ret < 0))
7554                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7555
7556         return ret;
7557 }
7558
7559 /* Delete l2 tunnel filter */
7560 int
7561 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7562                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7563 {
7564         int ret;
7565         struct ixgbe_l2_tn_info *l2_tn_info =
7566                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7567         struct ixgbe_l2_tn_key key;
7568
7569         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7570         key.tn_id = l2_tunnel->tunnel_id;
7571         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7572         if (ret < 0)
7573                 return ret;
7574
7575         switch (l2_tunnel->l2_tunnel_type) {
7576         case RTE_L2_TUNNEL_TYPE_E_TAG:
7577                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7578                 break;
7579         default:
7580                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7581                 ret = -EINVAL;
7582                 break;
7583         }
7584
7585         return ret;
7586 }
7587
7588 /**
7589  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7590  * @dev: pointer to rte_eth_dev structure
7591  * @filter_op:operation will be taken.
7592  * @arg: a pointer to specific structure corresponding to the filter_op
7593  */
7594 static int
7595 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7596                                   enum rte_filter_op filter_op,
7597                                   void *arg)
7598 {
7599         int ret;
7600
7601         if (filter_op == RTE_ETH_FILTER_NOP)
7602                 return 0;
7603
7604         if (arg == NULL) {
7605                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7606                             filter_op);
7607                 return -EINVAL;
7608         }
7609
7610         switch (filter_op) {
7611         case RTE_ETH_FILTER_ADD:
7612                 ret = ixgbe_dev_l2_tunnel_filter_add
7613                         (dev,
7614                          (struct rte_eth_l2_tunnel_conf *)arg,
7615                          FALSE);
7616                 break;
7617         case RTE_ETH_FILTER_DELETE:
7618                 ret = ixgbe_dev_l2_tunnel_filter_del
7619                         (dev,
7620                          (struct rte_eth_l2_tunnel_conf *)arg);
7621                 break;
7622         default:
7623                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7624                 ret = -EINVAL;
7625                 break;
7626         }
7627         return ret;
7628 }
7629
7630 static int
7631 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7632 {
7633         int ret = 0;
7634         uint32_t ctrl;
7635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7636
7637         if (hw->mac.type != ixgbe_mac_X550 &&
7638             hw->mac.type != ixgbe_mac_X550EM_x &&
7639             hw->mac.type != ixgbe_mac_X550EM_a) {
7640                 return -ENOTSUP;
7641         }
7642
7643         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7644         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7645         if (en)
7646                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7647         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7648
7649         return ret;
7650 }
7651
7652 /* Enable l2 tunnel forwarding */
7653 static int
7654 ixgbe_dev_l2_tunnel_forwarding_enable
7655         (struct rte_eth_dev *dev,
7656          enum rte_eth_tunnel_type l2_tunnel_type)
7657 {
7658         struct ixgbe_l2_tn_info *l2_tn_info =
7659                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7660         int ret = 0;
7661
7662         switch (l2_tunnel_type) {
7663         case RTE_L2_TUNNEL_TYPE_E_TAG:
7664                 l2_tn_info->e_tag_fwd_en = TRUE;
7665                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7666                 break;
7667         default:
7668                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7669                 ret = -EINVAL;
7670                 break;
7671         }
7672
7673         return ret;
7674 }
7675
7676 /* Disable l2 tunnel forwarding */
7677 static int
7678 ixgbe_dev_l2_tunnel_forwarding_disable
7679         (struct rte_eth_dev *dev,
7680          enum rte_eth_tunnel_type l2_tunnel_type)
7681 {
7682         struct ixgbe_l2_tn_info *l2_tn_info =
7683                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7684         int ret = 0;
7685
7686         switch (l2_tunnel_type) {
7687         case RTE_L2_TUNNEL_TYPE_E_TAG:
7688                 l2_tn_info->e_tag_fwd_en = FALSE;
7689                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7690                 break;
7691         default:
7692                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7693                 ret = -EINVAL;
7694                 break;
7695         }
7696
7697         return ret;
7698 }
7699
7700 static int
7701 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7702                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7703                              bool en)
7704 {
7705         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7706         int ret = 0;
7707         uint32_t vmtir, vmvir;
7708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7709
7710         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7711                 PMD_DRV_LOG(ERR,
7712                             "VF id %u should be less than %u",
7713                             l2_tunnel->vf_id,
7714                             pci_dev->max_vfs);
7715                 return -EINVAL;
7716         }
7717
7718         if (hw->mac.type != ixgbe_mac_X550 &&
7719             hw->mac.type != ixgbe_mac_X550EM_x &&
7720             hw->mac.type != ixgbe_mac_X550EM_a) {
7721                 return -ENOTSUP;
7722         }
7723
7724         if (en)
7725                 vmtir = l2_tunnel->tunnel_id;
7726         else
7727                 vmtir = 0;
7728
7729         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7730
7731         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7732         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7733         if (en)
7734                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7735         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7736
7737         return ret;
7738 }
7739
7740 /* Enable l2 tunnel tag insertion */
7741 static int
7742 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7743                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7744 {
7745         int ret = 0;
7746
7747         switch (l2_tunnel->l2_tunnel_type) {
7748         case RTE_L2_TUNNEL_TYPE_E_TAG:
7749                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7750                 break;
7751         default:
7752                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7753                 ret = -EINVAL;
7754                 break;
7755         }
7756
7757         return ret;
7758 }
7759
7760 /* Disable l2 tunnel tag insertion */
7761 static int
7762 ixgbe_dev_l2_tunnel_insertion_disable
7763         (struct rte_eth_dev *dev,
7764          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7765 {
7766         int ret = 0;
7767
7768         switch (l2_tunnel->l2_tunnel_type) {
7769         case RTE_L2_TUNNEL_TYPE_E_TAG:
7770                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7771                 break;
7772         default:
7773                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7774                 ret = -EINVAL;
7775                 break;
7776         }
7777
7778         return ret;
7779 }
7780
7781 static int
7782 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7783                              bool en)
7784 {
7785         int ret = 0;
7786         uint32_t qde;
7787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7788
7789         if (hw->mac.type != ixgbe_mac_X550 &&
7790             hw->mac.type != ixgbe_mac_X550EM_x &&
7791             hw->mac.type != ixgbe_mac_X550EM_a) {
7792                 return -ENOTSUP;
7793         }
7794
7795         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7796         if (en)
7797                 qde |= IXGBE_QDE_STRIP_TAG;
7798         else
7799                 qde &= ~IXGBE_QDE_STRIP_TAG;
7800         qde &= ~IXGBE_QDE_READ;
7801         qde |= IXGBE_QDE_WRITE;
7802         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7803
7804         return ret;
7805 }
7806
7807 /* Enable l2 tunnel tag stripping */
7808 static int
7809 ixgbe_dev_l2_tunnel_stripping_enable
7810         (struct rte_eth_dev *dev,
7811          enum rte_eth_tunnel_type l2_tunnel_type)
7812 {
7813         int ret = 0;
7814
7815         switch (l2_tunnel_type) {
7816         case RTE_L2_TUNNEL_TYPE_E_TAG:
7817                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7818                 break;
7819         default:
7820                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821                 ret = -EINVAL;
7822                 break;
7823         }
7824
7825         return ret;
7826 }
7827
7828 /* Disable l2 tunnel tag stripping */
7829 static int
7830 ixgbe_dev_l2_tunnel_stripping_disable
7831         (struct rte_eth_dev *dev,
7832          enum rte_eth_tunnel_type l2_tunnel_type)
7833 {
7834         int ret = 0;
7835
7836         switch (l2_tunnel_type) {
7837         case RTE_L2_TUNNEL_TYPE_E_TAG:
7838                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7839                 break;
7840         default:
7841                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7842                 ret = -EINVAL;
7843                 break;
7844         }
7845
7846         return ret;
7847 }
7848
7849 /* Enable/disable l2 tunnel offload functions */
7850 static int
7851 ixgbe_dev_l2_tunnel_offload_set
7852         (struct rte_eth_dev *dev,
7853          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7854          uint32_t mask,
7855          uint8_t en)
7856 {
7857         int ret = 0;
7858
7859         if (l2_tunnel == NULL)
7860                 return -EINVAL;
7861
7862         ret = -EINVAL;
7863         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7864                 if (en)
7865                         ret = ixgbe_dev_l2_tunnel_enable(
7866                                 dev,
7867                                 l2_tunnel->l2_tunnel_type);
7868                 else
7869                         ret = ixgbe_dev_l2_tunnel_disable(
7870                                 dev,
7871                                 l2_tunnel->l2_tunnel_type);
7872         }
7873
7874         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7875                 if (en)
7876                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7877                                 dev,
7878                                 l2_tunnel);
7879                 else
7880                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7881                                 dev,
7882                                 l2_tunnel);
7883         }
7884
7885         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7886                 if (en)
7887                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7888                                 dev,
7889                                 l2_tunnel->l2_tunnel_type);
7890                 else
7891                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7892                                 dev,
7893                                 l2_tunnel->l2_tunnel_type);
7894         }
7895
7896         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7897                 if (en)
7898                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7899                                 dev,
7900                                 l2_tunnel->l2_tunnel_type);
7901                 else
7902                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7903                                 dev,
7904                                 l2_tunnel->l2_tunnel_type);
7905         }
7906
7907         return ret;
7908 }
7909
7910 static int
7911 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7912                         uint16_t port)
7913 {
7914         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7915         IXGBE_WRITE_FLUSH(hw);
7916
7917         return 0;
7918 }
7919
7920 /* There's only one register for VxLAN UDP port.
7921  * So, we cannot add several ports. Will update it.
7922  */
7923 static int
7924 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7925                      uint16_t port)
7926 {
7927         if (port == 0) {
7928                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7929                 return -EINVAL;
7930         }
7931
7932         return ixgbe_update_vxlan_port(hw, port);
7933 }
7934
7935 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7936  * UDP port, it must have a value.
7937  * So, will reset it to the original value 0.
7938  */
7939 static int
7940 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7941                      uint16_t port)
7942 {
7943         uint16_t cur_port;
7944
7945         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7946
7947         if (cur_port != port) {
7948                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7949                 return -EINVAL;
7950         }
7951
7952         return ixgbe_update_vxlan_port(hw, 0);
7953 }
7954
7955 /* Add UDP tunneling port */
7956 static int
7957 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7958                               struct rte_eth_udp_tunnel *udp_tunnel)
7959 {
7960         int ret = 0;
7961         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7962
7963         if (hw->mac.type != ixgbe_mac_X550 &&
7964             hw->mac.type != ixgbe_mac_X550EM_x &&
7965             hw->mac.type != ixgbe_mac_X550EM_a) {
7966                 return -ENOTSUP;
7967         }
7968
7969         if (udp_tunnel == NULL)
7970                 return -EINVAL;
7971
7972         switch (udp_tunnel->prot_type) {
7973         case RTE_TUNNEL_TYPE_VXLAN:
7974                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7975                 break;
7976
7977         case RTE_TUNNEL_TYPE_GENEVE:
7978         case RTE_TUNNEL_TYPE_TEREDO:
7979                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7980                 ret = -EINVAL;
7981                 break;
7982
7983         default:
7984                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7985                 ret = -EINVAL;
7986                 break;
7987         }
7988
7989         return ret;
7990 }
7991
7992 /* Remove UDP tunneling port */
7993 static int
7994 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7995                               struct rte_eth_udp_tunnel *udp_tunnel)
7996 {
7997         int ret = 0;
7998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7999
8000         if (hw->mac.type != ixgbe_mac_X550 &&
8001             hw->mac.type != ixgbe_mac_X550EM_x &&
8002             hw->mac.type != ixgbe_mac_X550EM_a) {
8003                 return -ENOTSUP;
8004         }
8005
8006         if (udp_tunnel == NULL)
8007                 return -EINVAL;
8008
8009         switch (udp_tunnel->prot_type) {
8010         case RTE_TUNNEL_TYPE_VXLAN:
8011                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8012                 break;
8013         case RTE_TUNNEL_TYPE_GENEVE:
8014         case RTE_TUNNEL_TYPE_TEREDO:
8015                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8016                 ret = -EINVAL;
8017                 break;
8018         default:
8019                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8020                 ret = -EINVAL;
8021                 break;
8022         }
8023
8024         return ret;
8025 }
8026
8027 static void
8028 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8029 {
8030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8031
8032         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8033 }
8034
8035 static void
8036 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8037 {
8038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8039
8040         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8041 }
8042
8043 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8044 {
8045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046         u32 in_msg = 0;
8047
8048         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8049                 return;
8050
8051         /* PF reset VF event */
8052         if (in_msg == IXGBE_PF_CONTROL_MSG)
8053                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8054                                               NULL, NULL);
8055 }
8056
8057 static int
8058 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8059 {
8060         uint32_t eicr;
8061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8062         struct ixgbe_interrupt *intr =
8063                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8064         ixgbevf_intr_disable(hw);
8065
8066         /* read-on-clear nic registers here */
8067         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8068         intr->flags = 0;
8069
8070         /* only one misc vector supported - mailbox */
8071         eicr &= IXGBE_VTEICR_MASK;
8072         if (eicr == IXGBE_MISC_VEC_ID)
8073                 intr->flags |= IXGBE_FLAG_MAILBOX;
8074
8075         return 0;
8076 }
8077
8078 static int
8079 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8080 {
8081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8082         struct ixgbe_interrupt *intr =
8083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8084
8085         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8086                 ixgbevf_mbx_process(dev);
8087                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8088         }
8089
8090         ixgbevf_intr_enable(hw);
8091
8092         return 0;
8093 }
8094
8095 static void
8096 ixgbevf_dev_interrupt_handler(void *param)
8097 {
8098         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8099
8100         ixgbevf_dev_interrupt_get_status(dev);
8101         ixgbevf_dev_interrupt_action(dev);
8102 }
8103
8104 /**
8105  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8106  *  @hw: pointer to hardware structure
8107  *
8108  *  Stops the transmit data path and waits for the HW to internally empty
8109  *  the Tx security block
8110  **/
8111 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8112 {
8113 #define IXGBE_MAX_SECTX_POLL 40
8114
8115         int i;
8116         int sectxreg;
8117
8118         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8119         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8120         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8121         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8122                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8123                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8124                         break;
8125                 /* Use interrupt-safe sleep just in case */
8126                 usec_delay(1000);
8127         }
8128
8129         /* For informational purposes only */
8130         if (i >= IXGBE_MAX_SECTX_POLL)
8131                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8132                          "path fully disabled.  Continuing with init.");
8133
8134         return IXGBE_SUCCESS;
8135 }
8136
8137 /**
8138  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8139  *  @hw: pointer to hardware structure
8140  *
8141  *  Enables the transmit data path.
8142  **/
8143 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8144 {
8145         uint32_t sectxreg;
8146
8147         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8148         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8149         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8150         IXGBE_WRITE_FLUSH(hw);
8151
8152         return IXGBE_SUCCESS;
8153 }
8154
8155 /* restore n-tuple filter */
8156 static inline void
8157 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8158 {
8159         struct ixgbe_filter_info *filter_info =
8160                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8161         struct ixgbe_5tuple_filter *node;
8162
8163         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8164                 ixgbe_inject_5tuple_filter(dev, node);
8165         }
8166 }
8167
8168 /* restore ethernet type filter */
8169 static inline void
8170 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8171 {
8172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8173         struct ixgbe_filter_info *filter_info =
8174                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8175         int i;
8176
8177         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8178                 if (filter_info->ethertype_mask & (1 << i)) {
8179                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8180                                         filter_info->ethertype_filters[i].etqf);
8181                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8182                                         filter_info->ethertype_filters[i].etqs);
8183                         IXGBE_WRITE_FLUSH(hw);
8184                 }
8185         }
8186 }
8187
8188 /* restore SYN filter */
8189 static inline void
8190 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8191 {
8192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8193         struct ixgbe_filter_info *filter_info =
8194                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8195         uint32_t synqf;
8196
8197         synqf = filter_info->syn_info;
8198
8199         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8200                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8201                 IXGBE_WRITE_FLUSH(hw);
8202         }
8203 }
8204
8205 /* restore L2 tunnel filter */
8206 static inline void
8207 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8208 {
8209         struct ixgbe_l2_tn_info *l2_tn_info =
8210                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8211         struct ixgbe_l2_tn_filter *node;
8212         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8213
8214         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8215                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8216                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8217                 l2_tn_conf.pool           = node->pool;
8218                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8219         }
8220 }
8221
8222 static int
8223 ixgbe_filter_restore(struct rte_eth_dev *dev)
8224 {
8225         ixgbe_ntuple_filter_restore(dev);
8226         ixgbe_ethertype_filter_restore(dev);
8227         ixgbe_syn_filter_restore(dev);
8228         ixgbe_fdir_filter_restore(dev);
8229         ixgbe_l2_tn_filter_restore(dev);
8230
8231         return 0;
8232 }
8233
8234 static void
8235 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8236 {
8237         struct ixgbe_l2_tn_info *l2_tn_info =
8238                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240
8241         if (l2_tn_info->e_tag_en)
8242                 (void)ixgbe_e_tag_enable(hw);
8243
8244         if (l2_tn_info->e_tag_fwd_en)
8245                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8246
8247         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8248 }
8249
8250 /* remove all the n-tuple filters */
8251 void
8252 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8253 {
8254         struct ixgbe_filter_info *filter_info =
8255                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8256         struct ixgbe_5tuple_filter *p_5tuple;
8257
8258         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8259                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8260 }
8261
8262 /* remove all the ether type filters */
8263 void
8264 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8265 {
8266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         struct ixgbe_filter_info *filter_info =
8268                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8269         int i;
8270
8271         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8272                 if (filter_info->ethertype_mask & (1 << i) &&
8273                     !filter_info->ethertype_filters[i].conf) {
8274                         (void)ixgbe_ethertype_filter_remove(filter_info,
8275                                                             (uint8_t)i);
8276                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8277                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8278                         IXGBE_WRITE_FLUSH(hw);
8279                 }
8280         }
8281 }
8282
8283 /* remove the SYN filter */
8284 void
8285 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8286 {
8287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8288         struct ixgbe_filter_info *filter_info =
8289                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8290
8291         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8292                 filter_info->syn_info = 0;
8293
8294                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8295                 IXGBE_WRITE_FLUSH(hw);
8296         }
8297 }
8298
8299 /* remove all the L2 tunnel filters */
8300 int
8301 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8302 {
8303         struct ixgbe_l2_tn_info *l2_tn_info =
8304                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8305         struct ixgbe_l2_tn_filter *l2_tn_filter;
8306         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8307         int ret = 0;
8308
8309         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8310                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8311                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8312                 l2_tn_conf.pool           = l2_tn_filter->pool;
8313                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8314                 if (ret < 0)
8315                         return ret;
8316         }
8317
8318         return 0;
8319 }
8320
8321 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8322 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8323 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8324 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8325 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8326 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");