drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_eth_type_conf
 352         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 353 static int ixgbe_dev_l2_tunnel_offload_set
 354         (struct rte_eth_dev *dev,
 355          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 356          uint32_t mask,
 357          uint8_t en);
 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 359                                              enum rte_filter_op filter_op,
 360                                              void *arg);
 361
 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 368
 369 /*
 370  * Define VF Stats MACRO for Non "cleared on read" register
 371  */
 372 #define UPDATE_VF_STAT(reg, last, cur)                          \
 373 {                                                               \
 374         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 375         cur += (latest - last) & UINT_MAX;                      \
 376         last = latest;                                          \
 377 }
 378
 379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 380 {                                                                \
 381         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 382         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 383         u64 latest = ((new_msb << 32) | new_lsb);                \
 384         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 385         last = latest;                                           \
 386 }
 387
 388 #define IXGBE_SET_HWSTRIP(h, q) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (h)->bitmap[idx] |= 1 << bit;\
 392         } while (0)
 393
 394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 395                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 396                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 397                 (h)->bitmap[idx] &= ~(1 << bit);\
 398         } while (0)
 399
 400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (r) = (h)->bitmap[idx] >> bit & 1;\
 404         } while (0)
 405
 406 int ixgbe_logtype_init;
 407 int ixgbe_logtype_driver;
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         /* pick up the PCI bus settings for reporting later */
1123         ixgbe_get_bus_info(hw);
1124
1125         /* Unlock any pending hardware semaphore */
1126         ixgbe_swfw_lock_reset(hw);
1127
1128 #ifdef RTE_LIBRTE_SECURITY
1129         /* Initialize security_ctx only for primary process*/
1130         if (ixgbe_ipsec_ctx_create(eth_dev))
1131                 return -ENOMEM;
1132 #endif
1133
1134         /* Initialize DCB configuration*/
1135         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136         ixgbe_dcb_init(hw, dcb_config);
1137         /* Get Hardware Flow Control setting */
1138         hw->fc.requested_mode = ixgbe_fc_full;
1139         hw->fc.current_mode = ixgbe_fc_full;
1140         hw->fc.pause_time = IXGBE_FC_PAUSE;
1141         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142                 hw->fc.low_water[i] = IXGBE_FC_LO;
1143                 hw->fc.high_water[i] = IXGBE_FC_HI;
1144         }
1145         hw->fc.send_xon = 1;
1146
1147         /* Make sure we have a good EEPROM before we read from it */
1148         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149         if (diag != IXGBE_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1151                 return -EIO;
1152         }
1153
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155         diag = ixgbe_bypass_init_hw(hw);
1156 #else
1157         diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159
1160         /*
1161          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162          * is called too soon after the kernel driver unbinding/binding occurs.
1163          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165          * also called. See ixgbe_identify_phy_82599(). The reason for the
1166          * failure is not known, and only occuts when virtualisation features
1167          * are disabled in the bios. A delay of 100ms  was found to be enough by
1168          * trial-and-error, and is doubled to be safe.
1169          */
1170         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171                 rte_delay_ms(200);
1172                 diag = ixgbe_init_hw(hw);
1173         }
1174
1175         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176                 diag = IXGBE_SUCCESS;
1177
1178         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180                              "LOM.  Please be aware there may be issues associated "
1181                              "with your hardware.");
1182                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183                              "please contact your Intel or hardware representative "
1184                              "who provided you with this hardware.");
1185         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187         if (diag) {
1188                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* Reset the hw statistics */
1193         ixgbe_dev_stats_reset(eth_dev);
1194
1195         /* disable interrupt */
1196         ixgbe_disable_intr(hw);
1197
1198         /* reset mappings for queue statistics hw counters*/
1199         ixgbe_reset_qstat_mappings(hw);
1200
1201         /* Allocate memory for storing MAC addresses */
1202         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1203                                                hw->mac.num_rar_entries, 0);
1204         if (eth_dev->data->mac_addrs == NULL) {
1205                 PMD_INIT_LOG(ERR,
1206                              "Failed to allocate %u bytes needed to store "
1207                              "MAC addresses",
1208                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209                 return -ENOMEM;
1210         }
1211         /* Copy the permanent MAC address */
1212         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1213                         &eth_dev->data->mac_addrs[0]);
1214
1215         /* Allocate memory for storing hash filter MAC addresses */
1216         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1218         if (eth_dev->data->hash_mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %d bytes needed to store MAC addresses",
1221                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1222                 return -ENOMEM;
1223         }
1224
1225         /* initialize the vfta */
1226         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227
1228         /* initialize the hw strip bitmap*/
1229         memset(hwstrip, 0, sizeof(*hwstrip));
1230
1231         /* initialize PF if max_vfs not zero */
1232         ixgbe_pf_host_init(eth_dev);
1233
1234         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235         /* let hardware know driver is loaded */
1236         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type,
1245                              (int) hw->phy.sfp_type);
1246         else
1247                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248                              (int) hw->mac.type, (int) hw->phy.type);
1249
1250         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1252                      pci_dev->id.device_id);
1253
1254         rte_intr_callback_register(intr_handle,
1255                                    ixgbe_dev_interrupt_handler, eth_dev);
1256
1257         /* enable uio/vfio intr/eventfd mapping */
1258         rte_intr_enable(intr_handle);
1259
1260         /* enable support intr */
1261         ixgbe_enable_intr(eth_dev);
1262
1263         /* initialize filter info */
1264         memset(filter_info, 0,
1265                sizeof(struct ixgbe_filter_info));
1266
1267         /* initialize 5tuple filter list */
1268         TAILQ_INIT(&filter_info->fivetuple_list);
1269
1270         /* initialize flow director filter list & hash */
1271         ixgbe_fdir_filter_init(eth_dev);
1272
1273         /* initialize l2 tunnel filter list & hash */
1274         ixgbe_l2_tn_filter_init(eth_dev);
1275
1276         /* initialize flow filter lists */
1277         ixgbe_filterlist_init();
1278
1279         /* initialize bandwidth configuration info */
1280         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281
1282         /* initialize Traffic Manager configuration */
1283         ixgbe_tm_conf_init(eth_dev);
1284
1285         return 0;
1286 }
1287
1288 static int
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 {
1291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1293         struct ixgbe_hw *hw;
1294         int retries = 0;
1295         int ret;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303
1304         if (hw->adapter_stopped == 0)
1305                 ixgbe_dev_close(eth_dev);
1306
1307         eth_dev->dev_ops = NULL;
1308         eth_dev->rx_pkt_burst = NULL;
1309         eth_dev->tx_pkt_burst = NULL;
1310
1311         /* Unlock any pending hardware semaphore */
1312         ixgbe_swfw_lock_reset(hw);
1313
1314         /* disable uio intr before callback unregister */
1315         rte_intr_disable(intr_handle);
1316
1317         do {
1318                 ret = rte_intr_callback_unregister(intr_handle,
1319                                 ixgbe_dev_interrupt_handler, eth_dev);
1320                 if (ret >= 0) {
1321                         break;
1322                 } else if (ret != -EAGAIN) {
1323                         PMD_INIT_LOG(ERR,
1324                                 "intr callback unregister failed: %d",
1325                                 ret);
1326                         return ret;
1327                 }
1328                 rte_delay_ms(100);
1329         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1330
1331         /* uninitialize PF if max_vfs not zero */
1332         ixgbe_pf_host_uninit(eth_dev);
1333
1334         rte_free(eth_dev->data->mac_addrs);
1335         eth_dev->data->mac_addrs = NULL;
1336
1337         rte_free(eth_dev->data->hash_mac_addrs);
1338         eth_dev->data->hash_mac_addrs = NULL;
1339
1340         /* remove all the fdir filters & hash */
1341         ixgbe_fdir_filter_uninit(eth_dev);
1342
1343         /* remove all the L2 tunnel filters & hash */
1344         ixgbe_l2_tn_filter_uninit(eth_dev);
1345
1346         /* Remove all ntuple filters of the device */
1347         ixgbe_ntuple_filter_uninit(eth_dev);
1348
1349         /* clear all the filters list */
1350         ixgbe_filterlist_flush();
1351
1352         /* Remove all Traffic Manager configuration */
1353         ixgbe_tm_conf_uninit(eth_dev);
1354
1355 #ifdef RTE_LIBRTE_SECURITY
1356         rte_free(eth_dev->security_ctx);
1357 #endif
1358
1359         return 0;
1360 }
1361
1362 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1363 {
1364         struct ixgbe_filter_info *filter_info =
1365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1366         struct ixgbe_5tuple_filter *p_5tuple;
1367
1368         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1369                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1370                              p_5tuple,
1371                              entries);
1372                 rte_free(p_5tuple);
1373         }
1374         memset(filter_info->fivetuple_mask, 0,
1375                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1376
1377         return 0;
1378 }
1379
1380 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1381 {
1382         struct ixgbe_hw_fdir_info *fdir_info =
1383                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384         struct ixgbe_fdir_filter *fdir_filter;
1385
1386                 if (fdir_info->hash_map)
1387                 rte_free(fdir_info->hash_map);
1388         if (fdir_info->hash_handle)
1389                 rte_hash_free(fdir_info->hash_handle);
1390
1391         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392                 TAILQ_REMOVE(&fdir_info->fdir_list,
1393                              fdir_filter,
1394                              entries);
1395                 rte_free(fdir_filter);
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1402 {
1403         struct ixgbe_l2_tn_info *l2_tn_info =
1404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1405         struct ixgbe_l2_tn_filter *l2_tn_filter;
1406
1407         if (l2_tn_info->hash_map)
1408                 rte_free(l2_tn_info->hash_map);
1409         if (l2_tn_info->hash_handle)
1410                 rte_hash_free(l2_tn_info->hash_handle);
1411
1412         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1413                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1414                              l2_tn_filter,
1415                              entries);
1416                 rte_free(l2_tn_filter);
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1423 {
1424         struct ixgbe_hw_fdir_info *fdir_info =
1425                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1426         char fdir_hash_name[RTE_HASH_NAMESIZE];
1427         struct rte_hash_parameters fdir_hash_params = {
1428                 .name = fdir_hash_name,
1429                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1430                 .key_len = sizeof(union ixgbe_atr_input),
1431                 .hash_func = rte_hash_crc,
1432                 .hash_func_init_val = 0,
1433                 .socket_id = rte_socket_id(),
1434         };
1435
1436         TAILQ_INIT(&fdir_info->fdir_list);
1437         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1438                  "fdir_%s", eth_dev->device->name);
1439         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1440         if (!fdir_info->hash_handle) {
1441                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1442                 return -EINVAL;
1443         }
1444         fdir_info->hash_map = rte_zmalloc("ixgbe",
1445                                           sizeof(struct ixgbe_fdir_filter *) *
1446                                           IXGBE_MAX_FDIR_FILTER_NUM,
1447                                           0);
1448         if (!fdir_info->hash_map) {
1449                 PMD_INIT_LOG(ERR,
1450                              "Failed to allocate memory for fdir hash map!");
1451                 return -ENOMEM;
1452         }
1453         fdir_info->mask_added = FALSE;
1454
1455         return 0;
1456 }
1457
1458 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct ixgbe_l2_tn_info *l2_tn_info =
1461                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1462         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1463         struct rte_hash_parameters l2_tn_hash_params = {
1464                 .name = l2_tn_hash_name,
1465                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1466                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1467                 .hash_func = rte_hash_crc,
1468                 .hash_func_init_val = 0,
1469                 .socket_id = rte_socket_id(),
1470         };
1471
1472         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1473         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1474                  "l2_tn_%s", eth_dev->device->name);
1475         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1476         if (!l2_tn_info->hash_handle) {
1477                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1478                 return -EINVAL;
1479         }
1480         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1481                                    sizeof(struct ixgbe_l2_tn_filter *) *
1482                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1483                                    0);
1484         if (!l2_tn_info->hash_map) {
1485                 PMD_INIT_LOG(ERR,
1486                         "Failed to allocate memory for L2 TN hash map!");
1487                 return -ENOMEM;
1488         }
1489         l2_tn_info->e_tag_en = FALSE;
1490         l2_tn_info->e_tag_fwd_en = FALSE;
1491         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1492
1493         return 0;
1494 }
1495 /*
1496  * Negotiate mailbox API version with the PF.
1497  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1498  * Then we try to negotiate starting with the most recent one.
1499  * If all negotiation attempts fail, then we will proceed with
1500  * the default one (ixgbe_mbox_api_10).
1501  */
1502 static void
1503 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1504 {
1505         int32_t i;
1506
1507         /* start with highest supported, proceed down */
1508         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1509                 ixgbe_mbox_api_12,
1510                 ixgbe_mbox_api_11,
1511                 ixgbe_mbox_api_10,
1512         };
1513
1514         for (i = 0;
1515                         i != RTE_DIM(sup_ver) &&
1516                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517                         i++)
1518                 ;
1519 }
1520
1521 static void
1522 generate_random_mac_addr(struct ether_addr *mac_addr)
1523 {
1524         uint64_t random;
1525
1526         /* Set Organizationally Unique Identifier (OUI) prefix. */
1527         mac_addr->addr_bytes[0] = 0x00;
1528         mac_addr->addr_bytes[1] = 0x09;
1529         mac_addr->addr_bytes[2] = 0xC0;
1530         /* Force indication of locally assigned MAC address. */
1531         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1532         /* Generate the last 3 bytes of the MAC address with a random number. */
1533         random = rte_rand();
1534         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1535 }
1536
1537 /*
1538  * Virtual Function device init
1539  */
1540 static int
1541 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1542 {
1543         int diag;
1544         uint32_t tc, tcs;
1545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1551         struct ixgbe_hwstrip *hwstrip =
1552                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1553         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1559         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1560
1561         /* for secondary processes, we don't initialise any further as primary
1562          * has already done this work. Only check we don't need a different
1563          * RX function
1564          */
1565         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1566                 struct ixgbe_tx_queue *txq;
1567                 /* TX queue function in primary, set by last queue initialized
1568                  * Tx queue may not initialized by primary process
1569                  */
1570                 if (eth_dev->data->tx_queues) {
1571                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1572                         ixgbe_set_tx_function(eth_dev, txq);
1573                 } else {
1574                         /* Use default TX function if we get here */
1575                         PMD_INIT_LOG(NOTICE,
1576                                      "No TX queues configured yet. Using default TX function.");
1577                 }
1578
1579                 ixgbe_set_rx_function(eth_dev);
1580
1581                 return 0;
1582         }
1583
1584         rte_eth_copy_pci_info(eth_dev, pci_dev);
1585
1586         hw->device_id = pci_dev->id.device_id;
1587         hw->vendor_id = pci_dev->id.vendor_id;
1588         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1589
1590         /* initialize the vfta */
1591         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1592
1593         /* initialize the hw strip bitmap*/
1594         memset(hwstrip, 0, sizeof(*hwstrip));
1595
1596         /* Initialize the shared code (base driver) */
1597         diag = ixgbe_init_shared_code(hw);
1598         if (diag != IXGBE_SUCCESS) {
1599                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1600                 return -EIO;
1601         }
1602
1603         /* init_mailbox_params */
1604         hw->mbx.ops.init_params(hw);
1605
1606         /* Reset the hw statistics */
1607         ixgbevf_dev_stats_reset(eth_dev);
1608
1609         /* Disable the interrupts for VF */
1610         ixgbevf_intr_disable(eth_dev);
1611
1612         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1613         diag = hw->mac.ops.reset_hw(hw);
1614
1615         /*
1616          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1617          * the underlying PF driver has not assigned a MAC address to the VF.
1618          * In this case, assign a random MAC address.
1619          */
1620         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1621                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1622                 return diag;
1623         }
1624
1625         /* negotiate mailbox API version to use with the PF. */
1626         ixgbevf_negotiate_api(hw);
1627
1628         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629         ixgbevf_get_queues(hw, &tcs, &tc);
1630
1631         /* Allocate memory for storing MAC addresses */
1632         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1633                                                hw->mac.num_rar_entries, 0);
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 PMD_INIT_LOG(ERR,
1636                              "Failed to allocate %u bytes needed to store "
1637                              "MAC addresses",
1638                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1639                 return -ENOMEM;
1640         }
1641
1642         /* Generate a random MAC address, if none was assigned by PF. */
1643         if (is_zero_ether_addr(perm_addr)) {
1644                 generate_random_mac_addr(perm_addr);
1645                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646                 if (diag) {
1647                         rte_free(eth_dev->data->mac_addrs);
1648                         eth_dev->data->mac_addrs = NULL;
1649                         return diag;
1650                 }
1651                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653                              "%02x:%02x:%02x:%02x:%02x:%02x",
1654                              perm_addr->addr_bytes[0],
1655                              perm_addr->addr_bytes[1],
1656                              perm_addr->addr_bytes[2],
1657                              perm_addr->addr_bytes[3],
1658                              perm_addr->addr_bytes[4],
1659                              perm_addr->addr_bytes[5]);
1660         }
1661
1662         /* Copy the permanent MAC address */
1663         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1664
1665         /* reset the hardware with the new settings */
1666         diag = hw->mac.ops.start_hw(hw);
1667         switch (diag) {
1668         case  0:
1669                 break;
1670
1671         default:
1672                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673                 return -EIO;
1674         }
1675
1676         rte_intr_callback_register(intr_handle,
1677                                    ixgbevf_dev_interrupt_handler, eth_dev);
1678         rte_intr_enable(intr_handle);
1679         ixgbevf_intr_enable(eth_dev);
1680
1681         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1683                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1684
1685         return 0;
1686 }
1687
1688 /* Virtual Function device uninit */
1689
1690 static int
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 {
1693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695         struct ixgbe_hw *hw;
1696
1697         PMD_INIT_FUNC_TRACE();
1698
1699         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1700                 return -EPERM;
1701
1702         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1703
1704         if (hw->adapter_stopped == 0)
1705                 ixgbevf_dev_close(eth_dev);
1706
1707         eth_dev->dev_ops = NULL;
1708         eth_dev->rx_pkt_burst = NULL;
1709         eth_dev->tx_pkt_burst = NULL;
1710
1711         /* Disable the interrupts for VF */
1712         ixgbevf_intr_disable(eth_dev);
1713
1714         rte_free(eth_dev->data->mac_addrs);
1715         eth_dev->data->mac_addrs = NULL;
1716
1717         rte_intr_disable(intr_handle);
1718         rte_intr_callback_unregister(intr_handle,
1719                                      ixgbevf_dev_interrupt_handler, eth_dev);
1720
1721         return 0;
1722 }
1723
1724 static int
1725 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1726                 struct rte_pci_device *pci_dev)
1727 {
1728         char name[RTE_ETH_NAME_MAX_LEN];
1729         struct rte_eth_dev *pf_ethdev;
1730         struct rte_eth_devargs eth_da;
1731         int i, retval;
1732
1733         if (pci_dev->device.devargs) {
1734                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1735                                 &eth_da);
1736                 if (retval)
1737                         return retval;
1738         } else
1739                 memset(&eth_da, 0, sizeof(eth_da));
1740
1741         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1742                 sizeof(struct ixgbe_adapter),
1743                 eth_dev_pci_specific_init, pci_dev,
1744                 eth_ixgbe_dev_init, NULL);
1745
1746         if (retval || eth_da.nb_representor_ports < 1)
1747                 return retval;
1748
1749         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1750         if (pf_ethdev == NULL)
1751                 return -ENODEV;
1752
1753         /* probe VF representor ports */
1754         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1755                 struct ixgbe_vf_info *vfinfo;
1756                 struct ixgbe_vf_representor representor;
1757
1758                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1759                         pf_ethdev->data->dev_private);
1760                 if (vfinfo == NULL) {
1761                         PMD_DRV_LOG(ERR,
1762                                 "no virtual functions supported by PF");
1763                         break;
1764                 }
1765
1766                 representor.vf_id = eth_da.representor_ports[i];
1767                 representor.switch_domain_id = vfinfo->switch_domain_id;
1768                 representor.pf_ethdev = pf_ethdev;
1769
1770                 /* representor port net_bdf_port */
1771                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1772                         pci_dev->device.name,
1773                         eth_da.representor_ports[i]);
1774
1775                 retval = rte_eth_dev_create(&pci_dev->device, name,
1776                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1777                         ixgbe_vf_representor_init, &representor);
1778
1779                 if (retval)
1780                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1781                                 "representor %s.", name);
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1788 {
1789         struct rte_eth_dev *ethdev;
1790
1791         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1792         if (!ethdev)
1793                 return -ENODEV;
1794
1795         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1796                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1797         else
1798                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1804                      RTE_PCI_DRV_IOVA_AS_VA,
1805         .probe = eth_ixgbe_pci_probe,
1806         .remove = eth_ixgbe_pci_remove,
1807 };
1808
1809 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1810         struct rte_pci_device *pci_dev)
1811 {
1812         return rte_eth_dev_pci_generic_probe(pci_dev,
1813                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1814 }
1815
1816 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1817 {
1818         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1819 }
1820
1821 /*
1822  * virtual function driver struct
1823  */
1824 static struct rte_pci_driver rte_ixgbevf_pmd = {
1825         .id_table = pci_id_ixgbevf_map,
1826         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1827         .probe = eth_ixgbevf_pci_probe,
1828         .remove = eth_ixgbevf_pci_remove,
1829 };
1830
1831 static int
1832 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct ixgbe_vfta *shadow_vfta =
1837                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1838         uint32_t vfta;
1839         uint32_t vid_idx;
1840         uint32_t vid_bit;
1841
1842         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1843         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1844         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1845         if (on)
1846                 vfta |= vid_bit;
1847         else
1848                 vfta &= ~vid_bit;
1849         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1850
1851         /* update local VFTA copy */
1852         shadow_vfta->vfta[vid_idx] = vfta;
1853
1854         return 0;
1855 }
1856
1857 static void
1858 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1859 {
1860         if (on)
1861                 ixgbe_vlan_hw_strip_enable(dev, queue);
1862         else
1863                 ixgbe_vlan_hw_strip_disable(dev, queue);
1864 }
1865
1866 static int
1867 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1868                     enum rte_vlan_type vlan_type,
1869                     uint16_t tpid)
1870 {
1871         struct ixgbe_hw *hw =
1872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         int ret = 0;
1874         uint32_t reg;
1875         uint32_t qinq;
1876
1877         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878         qinq &= IXGBE_DMATXCTL_GDV;
1879
1880         switch (vlan_type) {
1881         case ETH_VLAN_TYPE_INNER:
1882                 if (qinq) {
1883                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1884                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1885                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1886                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1888                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1889                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1890                 } else {
1891                         ret = -ENOTSUP;
1892                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1893                                     " by single VLAN");
1894                 }
1895                 break;
1896         case ETH_VLAN_TYPE_OUTER:
1897                 if (qinq) {
1898                         /* Only the high 16-bits is valid */
1899                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1900                                         IXGBE_EXVET_VET_EXT_SHIFT);
1901                 } else {
1902                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1909                 }
1910
1911                 break;
1912         default:
1913                 ret = -EINVAL;
1914                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1915                 break;
1916         }
1917
1918         return ret;
1919 }
1920
1921 void
1922 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         uint32_t vlnctrl;
1927
1928         PMD_INIT_FUNC_TRACE();
1929
1930         /* Filter Table Disable */
1931         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1932         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935 }
1936
1937 void
1938 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1939 {
1940         struct ixgbe_hw *hw =
1941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct ixgbe_vfta *shadow_vfta =
1943                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1944         uint32_t vlnctrl;
1945         uint16_t i;
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         /* Filter Table Enable */
1950         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1952         vlnctrl |= IXGBE_VLNCTRL_VFE;
1953
1954         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1955
1956         /* write whatever is in local vfta copy */
1957         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1958                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1959 }
1960
1961 static void
1962 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1963 {
1964         struct ixgbe_hwstrip *hwstrip =
1965                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1966         struct ixgbe_rx_queue *rxq;
1967
1968         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1969                 return;
1970
1971         if (on)
1972                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1973         else
1974                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1975
1976         if (queue >= dev->data->nb_rx_queues)
1977                 return;
1978
1979         rxq = dev->data->rx_queues[queue];
1980
1981         if (on) {
1982                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1983                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1984         } else {
1985                 rxq->vlan_flags = PKT_RX_VLAN;
1986                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1987         }
1988 }
1989
1990 static void
1991 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1992 {
1993         struct ixgbe_hw *hw =
1994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         uint32_t ctrl;
1996
1997         PMD_INIT_FUNC_TRACE();
1998
1999         if (hw->mac.type == ixgbe_mac_82598EB) {
2000                 /* No queue level support */
2001                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2002                 return;
2003         }
2004
2005         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2006         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2007         ctrl &= ~IXGBE_RXDCTL_VME;
2008         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2009
2010         /* record those setting for HW strip per queue */
2011         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2012 }
2013
2014 static void
2015 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2016 {
2017         struct ixgbe_hw *hw =
2018                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2019         uint32_t ctrl;
2020
2021         PMD_INIT_FUNC_TRACE();
2022
2023         if (hw->mac.type == ixgbe_mac_82598EB) {
2024                 /* No queue level supported */
2025                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2026                 return;
2027         }
2028
2029         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2030         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2031         ctrl |= IXGBE_RXDCTL_VME;
2032         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2033
2034         /* record those setting for HW strip per queue */
2035         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2036 }
2037
2038 static void
2039 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2040 {
2041         struct ixgbe_hw *hw =
2042                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043         uint32_t ctrl;
2044
2045         PMD_INIT_FUNC_TRACE();
2046
2047         /* DMATXCTRL: Geric Double VLAN Disable */
2048         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2049         ctrl &= ~IXGBE_DMATXCTL_GDV;
2050         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2051
2052         /* CTRL_EXT: Global Double VLAN Disable */
2053         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2054         ctrl &= ~IXGBE_EXTENDED_VLAN;
2055         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2056
2057 }
2058
2059 static void
2060 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2061 {
2062         struct ixgbe_hw *hw =
2063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064         uint32_t ctrl;
2065
2066         PMD_INIT_FUNC_TRACE();
2067
2068         /* DMATXCTRL: Geric Double VLAN Enable */
2069         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2070         ctrl |= IXGBE_DMATXCTL_GDV;
2071         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2072
2073         /* CTRL_EXT: Global Double VLAN Enable */
2074         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2075         ctrl |= IXGBE_EXTENDED_VLAN;
2076         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2077
2078         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2079         if (hw->mac.type == ixgbe_mac_X550 ||
2080             hw->mac.type == ixgbe_mac_X550EM_x ||
2081             hw->mac.type == ixgbe_mac_X550EM_a) {
2082                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2083                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2084                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2085         }
2086
2087         /*
2088          * VET EXT field in the EXVET register = 0x8100 by default
2089          * So no need to change. Same to VT field of DMATXCTL register
2090          */
2091 }
2092
2093 void
2094 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2095 {
2096         struct ixgbe_hw *hw =
2097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2099         uint32_t ctrl;
2100         uint16_t i;
2101         struct ixgbe_rx_queue *rxq;
2102         bool on;
2103
2104         PMD_INIT_FUNC_TRACE();
2105
2106         if (hw->mac.type == ixgbe_mac_82598EB) {
2107                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2108                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2109                         ctrl |= IXGBE_VLNCTRL_VME;
2110                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2111                 } else {
2112                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113                         ctrl &= ~IXGBE_VLNCTRL_VME;
2114                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2115                 }
2116         } else {
2117                 /*
2118                  * Other 10G NIC, the VLAN strip can be setup
2119                  * per queue in RXDCTL
2120                  */
2121                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2122                         rxq = dev->data->rx_queues[i];
2123                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2124                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2125                                 ctrl |= IXGBE_RXDCTL_VME;
2126                                 on = TRUE;
2127                         } else {
2128                                 ctrl &= ~IXGBE_RXDCTL_VME;
2129                                 on = FALSE;
2130                         }
2131                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2132
2133                         /* record those setting for HW strip per queue */
2134                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2135                 }
2136         }
2137 }
2138
2139 static void
2140 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2141 {
2142         uint16_t i;
2143         struct rte_eth_rxmode *rxmode;
2144         struct ixgbe_rx_queue *rxq;
2145
2146         if (mask & ETH_VLAN_STRIP_MASK) {
2147                 rxmode = &dev->data->dev_conf.rxmode;
2148                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2149                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2150                                 rxq = dev->data->rx_queues[i];
2151                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2152                         }
2153                 else
2154                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155                                 rxq = dev->data->rx_queues[i];
2156                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2157                         }
2158         }
2159 }
2160
2161 static int
2162 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2163 {
2164         struct rte_eth_rxmode *rxmode;
2165         rxmode = &dev->data->dev_conf.rxmode;
2166
2167         if (mask & ETH_VLAN_STRIP_MASK) {
2168                 ixgbe_vlan_hw_strip_config(dev);
2169         }
2170
2171         if (mask & ETH_VLAN_FILTER_MASK) {
2172                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2173                         ixgbe_vlan_hw_filter_enable(dev);
2174                 else
2175                         ixgbe_vlan_hw_filter_disable(dev);
2176         }
2177
2178         if (mask & ETH_VLAN_EXTEND_MASK) {
2179                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2180                         ixgbe_vlan_hw_extend_enable(dev);
2181                 else
2182                         ixgbe_vlan_hw_extend_disable(dev);
2183         }
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2190 {
2191         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2192
2193         ixgbe_vlan_offload_config(dev, mask);
2194
2195         return 0;
2196 }
2197
2198 static void
2199 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2200 {
2201         struct ixgbe_hw *hw =
2202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2204         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2205
2206         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2207         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2208 }
2209
2210 static int
2211 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2212 {
2213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2214
2215         switch (nb_rx_q) {
2216         case 1:
2217         case 2:
2218                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2219                 break;
2220         case 4:
2221                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2222                 break;
2223         default:
2224                 return -EINVAL;
2225         }
2226
2227         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2228                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2229         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2230                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2231         return 0;
2232 }
2233
2234 static int
2235 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2236 {
2237         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2240         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2241
2242         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2243                 /* check multi-queue mode */
2244                 switch (dev_conf->rxmode.mq_mode) {
2245                 case ETH_MQ_RX_VMDQ_DCB:
2246                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2247                         break;
2248                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2249                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2250                         PMD_INIT_LOG(ERR, "SRIOV active,"
2251                                         " unsupported mq_mode rx %d.",
2252                                         dev_conf->rxmode.mq_mode);
2253                         return -EINVAL;
2254                 case ETH_MQ_RX_RSS:
2255                 case ETH_MQ_RX_VMDQ_RSS:
2256                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2257                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2258                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2259                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                                 " invalid queue number"
2261                                                 " for VMDQ RSS, allowed"
2262                                                 " value are 1, 2 or 4.");
2263                                         return -EINVAL;
2264                                 }
2265                         break;
2266                 case ETH_MQ_RX_VMDQ_ONLY:
2267                 case ETH_MQ_RX_NONE:
2268                         /* if nothing mq mode configure, use default scheme */
2269                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2270                         break;
2271                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2272                         /* SRIOV only works in VMDq enable mode */
2273                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2274                                         " wrong mq_mode rx %d.",
2275                                         dev_conf->rxmode.mq_mode);
2276                         return -EINVAL;
2277                 }
2278
2279                 switch (dev_conf->txmode.mq_mode) {
2280                 case ETH_MQ_TX_VMDQ_DCB:
2281                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2282                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2283                         break;
2284                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2285                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2286                         break;
2287                 }
2288
2289                 /* check valid queue number */
2290                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2291                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2292                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2293                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2294                                         " must be less than or equal to %d.",
2295                                         nb_rx_q, nb_tx_q,
2296                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2297                         return -EINVAL;
2298                 }
2299         } else {
2300                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2301                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2302                                           " not supported.");
2303                         return -EINVAL;
2304                 }
2305                 /* check configuration for vmdb+dcb mode */
2306                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2307                         const struct rte_eth_vmdq_dcb_conf *conf;
2308
2309                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2310                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2311                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2312                                 return -EINVAL;
2313                         }
2314                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2315                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2316                                conf->nb_queue_pools == ETH_32_POOLS)) {
2317                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2318                                                 " nb_queue_pools must be %d or %d.",
2319                                                 ETH_16_POOLS, ETH_32_POOLS);
2320                                 return -EINVAL;
2321                         }
2322                 }
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2324                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2325
2326                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2328                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2332                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2333                                conf->nb_queue_pools == ETH_32_POOLS)) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2335                                                 " nb_queue_pools != %d and"
2336                                                 " nb_queue_pools != %d.",
2337                                                 ETH_16_POOLS, ETH_32_POOLS);
2338                                 return -EINVAL;
2339                         }
2340                 }
2341
2342                 /* For DCB mode check our configuration before we go further */
2343                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2344                         const struct rte_eth_dcb_rx_conf *conf;
2345
2346                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2347                         if (!(conf->nb_tcs == ETH_4_TCS ||
2348                                conf->nb_tcs == ETH_8_TCS)) {
2349                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2350                                                 " and nb_tcs != %d.",
2351                                                 ETH_4_TCS, ETH_8_TCS);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355
2356                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2357                         const struct rte_eth_dcb_tx_conf *conf;
2358
2359                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2360                         if (!(conf->nb_tcs == ETH_4_TCS ||
2361                                conf->nb_tcs == ETH_8_TCS)) {
2362                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2363                                                 " and nb_tcs != %d.",
2364                                                 ETH_4_TCS, ETH_8_TCS);
2365                                 return -EINVAL;
2366                         }
2367                 }
2368
2369                 /*
2370                  * When DCB/VT is off, maximum number of queues changes,
2371                  * except for 82598EB, which remains constant.
2372                  */
2373                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2374                                 hw->mac.type != ixgbe_mac_82598EB) {
2375                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2376                                 PMD_INIT_LOG(ERR,
2377                                              "Neither VT nor DCB are enabled, "
2378                                              "nb_tx_q > %d.",
2379                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2380                                 return -EINVAL;
2381                         }
2382                 }
2383         }
2384         return 0;
2385 }
2386
2387 static int
2388 ixgbe_dev_configure(struct rte_eth_dev *dev)
2389 {
2390         struct ixgbe_interrupt *intr =
2391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2392         struct ixgbe_adapter *adapter =
2393                 (struct ixgbe_adapter *)dev->data->dev_private;
2394         int ret;
2395
2396         PMD_INIT_FUNC_TRACE();
2397         /* multipe queue mode checking */
2398         ret  = ixgbe_check_mq_mode(dev);
2399         if (ret != 0) {
2400                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2401                             ret);
2402                 return ret;
2403         }
2404
2405         /* set flag to update link status after init */
2406         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2407
2408         /*
2409          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2410          * allocation or vector Rx preconditions we will reset it.
2411          */
2412         adapter->rx_bulk_alloc_allowed = true;
2413         adapter->rx_vec_allowed = true;
2414
2415         return 0;
2416 }
2417
2418 static void
2419 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2420 {
2421         struct ixgbe_hw *hw =
2422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct ixgbe_interrupt *intr =
2424                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2425         uint32_t gpie;
2426
2427         /* only set up it on X550EM_X */
2428         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2429                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2430                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2431                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2432                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2433                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2434         }
2435 }
2436
2437 int
2438 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2439                         uint16_t tx_rate, uint64_t q_msk)
2440 {
2441         struct ixgbe_hw *hw;
2442         struct ixgbe_vf_info *vfinfo;
2443         struct rte_eth_link link;
2444         uint8_t  nb_q_per_pool;
2445         uint32_t queue_stride;
2446         uint32_t queue_idx, idx = 0, vf_idx;
2447         uint32_t queue_end;
2448         uint16_t total_rate = 0;
2449         struct rte_pci_device *pci_dev;
2450
2451         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2452         rte_eth_link_get_nowait(dev->data->port_id, &link);
2453
2454         if (vf >= pci_dev->max_vfs)
2455                 return -EINVAL;
2456
2457         if (tx_rate > link.link_speed)
2458                 return -EINVAL;
2459
2460         if (q_msk == 0)
2461                 return 0;
2462
2463         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2464         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2465         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2466         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2467         queue_idx = vf * queue_stride;
2468         queue_end = queue_idx + nb_q_per_pool - 1;
2469         if (queue_end >= hw->mac.max_tx_queues)
2470                 return -EINVAL;
2471
2472         if (vfinfo) {
2473                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2474                         if (vf_idx == vf)
2475                                 continue;
2476                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2477                                 idx++)
2478                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2479                 }
2480         } else {
2481                 return -EINVAL;
2482         }
2483
2484         /* Store tx_rate for this vf. */
2485         for (idx = 0; idx < nb_q_per_pool; idx++) {
2486                 if (((uint64_t)0x1 << idx) & q_msk) {
2487                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2488                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2489                         total_rate += tx_rate;
2490                 }
2491         }
2492
2493         if (total_rate > dev->data->dev_link.link_speed) {
2494                 /* Reset stored TX rate of the VF if it causes exceed
2495                  * link speed.
2496                  */
2497                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2498                 return -EINVAL;
2499         }
2500
2501         /* Set RTTBCNRC of each queue/pool for vf X  */
2502         for (; queue_idx <= queue_end; queue_idx++) {
2503                 if (0x1 & q_msk)
2504                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2505                 q_msk = q_msk >> 1;
2506         }
2507
2508         return 0;
2509 }
2510
2511 /*
2512  * Configure device link speed and setup link.
2513  * It returns 0 on success.
2514  */
2515 static int
2516 ixgbe_dev_start(struct rte_eth_dev *dev)
2517 {
2518         struct ixgbe_hw *hw =
2519                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520         struct ixgbe_vf_info *vfinfo =
2521                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2522         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2523         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2524         uint32_t intr_vector = 0;
2525         int err, link_up = 0, negotiate = 0;
2526         uint32_t speed = 0;
2527         uint32_t allowed_speeds = 0;
2528         int mask = 0;
2529         int status;
2530         uint16_t vf, idx;
2531         uint32_t *link_speeds;
2532         struct ixgbe_tm_conf *tm_conf =
2533                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2534
2535         PMD_INIT_FUNC_TRACE();
2536
2537         /* IXGBE devices don't support:
2538         *    - half duplex (checked afterwards for valid speeds)
2539         *    - fixed speed: TODO implement
2540         */
2541         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2542                 PMD_INIT_LOG(ERR,
2543                 "Invalid link_speeds for port %u, fix speed not supported",
2544                                 dev->data->port_id);
2545                 return -EINVAL;
2546         }
2547
2548         /* disable uio/vfio intr/eventfd mapping */
2549         rte_intr_disable(intr_handle);
2550
2551         /* stop adapter */
2552         hw->adapter_stopped = 0;
2553         ixgbe_stop_adapter(hw);
2554
2555         /* reinitialize adapter
2556          * this calls reset and start
2557          */
2558         status = ixgbe_pf_reset_hw(hw);
2559         if (status != 0)
2560                 return -1;
2561         hw->mac.ops.start_hw(hw);
2562         hw->mac.get_link_status = true;
2563
2564         /* configure PF module if SRIOV enabled */
2565         ixgbe_pf_host_configure(dev);
2566
2567         ixgbe_dev_phy_intr_setup(dev);
2568
2569         /* check and configure queue intr-vector mapping */
2570         if ((rte_intr_cap_multiple(intr_handle) ||
2571              !RTE_ETH_DEV_SRIOV(dev).active) &&
2572             dev->data->dev_conf.intr_conf.rxq != 0) {
2573                 intr_vector = dev->data->nb_rx_queues;
2574                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2575                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2576                                         IXGBE_MAX_INTR_QUEUE_NUM);
2577                         return -ENOTSUP;
2578                 }
2579                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2580                         return -1;
2581         }
2582
2583         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2584                 intr_handle->intr_vec =
2585                         rte_zmalloc("intr_vec",
2586                                     dev->data->nb_rx_queues * sizeof(int), 0);
2587                 if (intr_handle->intr_vec == NULL) {
2588                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2589                                      " intr_vec", dev->data->nb_rx_queues);
2590                         return -ENOMEM;
2591                 }
2592         }
2593
2594         /* confiugre msix for sleep until rx interrupt */
2595         ixgbe_configure_msix(dev);
2596
2597         /* initialize transmission unit */
2598         ixgbe_dev_tx_init(dev);
2599
2600         /* This can fail when allocating mbufs for descriptor rings */
2601         err = ixgbe_dev_rx_init(dev);
2602         if (err) {
2603                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2604                 goto error;
2605         }
2606
2607         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2608                 ETH_VLAN_EXTEND_MASK;
2609         err = ixgbe_vlan_offload_config(dev, mask);
2610         if (err) {
2611                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2612                 goto error;
2613         }
2614
2615         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2616                 /* Enable vlan filtering for VMDq */
2617                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2618         }
2619
2620         /* Configure DCB hw */
2621         ixgbe_configure_dcb(dev);
2622
2623         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2624                 err = ixgbe_fdir_configure(dev);
2625                 if (err)
2626                         goto error;
2627         }
2628
2629         /* Restore vf rate limit */
2630         if (vfinfo != NULL) {
2631                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2632                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2633                                 if (vfinfo[vf].tx_rate[idx] != 0)
2634                                         ixgbe_set_vf_rate_limit(
2635                                                 dev, vf,
2636                                                 vfinfo[vf].tx_rate[idx],
2637                                                 1 << idx);
2638         }
2639
2640         ixgbe_restore_statistics_mapping(dev);
2641
2642         err = ixgbe_dev_rxtx_start(dev);
2643         if (err < 0) {
2644                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2645                 goto error;
2646         }
2647
2648         /* Skip link setup if loopback mode is enabled for 82599. */
2649         if (hw->mac.type == ixgbe_mac_82599EB &&
2650                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2651                 goto skip_link_setup;
2652
2653         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2654                 err = hw->mac.ops.setup_sfp(hw);
2655                 if (err)
2656                         goto error;
2657         }
2658
2659         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2660                 /* Turn on the copper */
2661                 ixgbe_set_phy_power(hw, true);
2662         } else {
2663                 /* Turn on the laser */
2664                 ixgbe_enable_tx_laser(hw);
2665         }
2666
2667         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2668         if (err)
2669                 goto error;
2670         dev->data->dev_link.link_status = link_up;
2671
2672         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2673         if (err)
2674                 goto error;
2675
2676         switch (hw->mac.type) {
2677         case ixgbe_mac_X550:
2678         case ixgbe_mac_X550EM_x:
2679         case ixgbe_mac_X550EM_a:
2680                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2681                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2682                         ETH_LINK_SPEED_10G;
2683                 break;
2684         default:
2685                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2686                         ETH_LINK_SPEED_10G;
2687         }
2688
2689         link_speeds = &dev->data->dev_conf.link_speeds;
2690         if (*link_speeds & ~allowed_speeds) {
2691                 PMD_INIT_LOG(ERR, "Invalid link setting");
2692                 goto error;
2693         }
2694
2695         speed = 0x0;
2696         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2697                 switch (hw->mac.type) {
2698                 case ixgbe_mac_82598EB:
2699                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2700                         break;
2701                 case ixgbe_mac_82599EB:
2702                 case ixgbe_mac_X540:
2703                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2704                         break;
2705                 case ixgbe_mac_X550:
2706                 case ixgbe_mac_X550EM_x:
2707                 case ixgbe_mac_X550EM_a:
2708                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2709                         break;
2710                 default:
2711                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2712                 }
2713         } else {
2714                 if (*link_speeds & ETH_LINK_SPEED_10G)
2715                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2716                 if (*link_speeds & ETH_LINK_SPEED_5G)
2717                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2718                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2719                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2720                 if (*link_speeds & ETH_LINK_SPEED_1G)
2721                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2722                 if (*link_speeds & ETH_LINK_SPEED_100M)
2723                         speed |= IXGBE_LINK_SPEED_100_FULL;
2724         }
2725
2726         err = ixgbe_setup_link(hw, speed, link_up);
2727         if (err)
2728                 goto error;
2729
2730         ixgbe_dev_link_update(dev, 0);
2731
2732 skip_link_setup:
2733
2734         if (rte_intr_allow_others(intr_handle)) {
2735                 /* check if lsc interrupt is enabled */
2736                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2737                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2738                 else
2739                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2740                 ixgbe_dev_macsec_interrupt_setup(dev);
2741         } else {
2742                 rte_intr_callback_unregister(intr_handle,
2743                                              ixgbe_dev_interrupt_handler, dev);
2744                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2745                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2746                                      " no intr multiplex");
2747         }
2748
2749         /* check if rxq interrupt is enabled */
2750         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2751             rte_intr_dp_is_en(intr_handle))
2752                 ixgbe_dev_rxq_interrupt_setup(dev);
2753
2754         /* enable uio/vfio intr/eventfd mapping */
2755         rte_intr_enable(intr_handle);
2756
2757         /* resume enabled intr since hw reset */
2758         ixgbe_enable_intr(dev);
2759         ixgbe_l2_tunnel_conf(dev);
2760         ixgbe_filter_restore(dev);
2761
2762         if (tm_conf->root && !tm_conf->committed)
2763                 PMD_DRV_LOG(WARNING,
2764                             "please call hierarchy_commit() "
2765                             "before starting the port");
2766
2767         return 0;
2768
2769 error:
2770         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2771         ixgbe_dev_clear_queues(dev);
2772         return -EIO;
2773 }
2774
2775 /*
2776  * Stop device: disable rx and tx functions to allow for reconfiguring.
2777  */
2778 static void
2779 ixgbe_dev_stop(struct rte_eth_dev *dev)
2780 {
2781         struct rte_eth_link link;
2782         struct ixgbe_hw *hw =
2783                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct ixgbe_vf_info *vfinfo =
2785                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2788         int vf;
2789         struct ixgbe_tm_conf *tm_conf =
2790                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2791
2792         PMD_INIT_FUNC_TRACE();
2793
2794         /* disable interrupts */
2795         ixgbe_disable_intr(hw);
2796
2797         /* reset the NIC */
2798         ixgbe_pf_reset_hw(hw);
2799         hw->adapter_stopped = 0;
2800
2801         /* stop adapter */
2802         ixgbe_stop_adapter(hw);
2803
2804         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2805                 vfinfo[vf].clear_to_send = false;
2806
2807         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2808                 /* Turn off the copper */
2809                 ixgbe_set_phy_power(hw, false);
2810         } else {
2811                 /* Turn off the laser */
2812                 ixgbe_disable_tx_laser(hw);
2813         }
2814
2815         ixgbe_dev_clear_queues(dev);
2816
2817         /* Clear stored conf */
2818         dev->data->scattered_rx = 0;
2819         dev->data->lro = 0;
2820
2821         /* Clear recorded link status */
2822         memset(&link, 0, sizeof(link));
2823         rte_eth_linkstatus_set(dev, &link);
2824
2825         if (!rte_intr_allow_others(intr_handle))
2826                 /* resume to the default handler */
2827                 rte_intr_callback_register(intr_handle,
2828                                            ixgbe_dev_interrupt_handler,
2829                                            (void *)dev);
2830
2831         /* Clean datapath event and queue/vec mapping */
2832         rte_intr_efd_disable(intr_handle);
2833         if (intr_handle->intr_vec != NULL) {
2834                 rte_free(intr_handle->intr_vec);
2835                 intr_handle->intr_vec = NULL;
2836         }
2837
2838         /* reset hierarchy commit */
2839         tm_conf->committed = false;
2840 }
2841
2842 /*
2843  * Set device link up: enable tx.
2844  */
2845 static int
2846 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2847 {
2848         struct ixgbe_hw *hw =
2849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850         if (hw->mac.type == ixgbe_mac_82599EB) {
2851 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2852                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2853                         /* Not suported in bypass mode */
2854                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2855                                      "by device id 0x%x", hw->device_id);
2856                         return -ENOTSUP;
2857                 }
2858 #endif
2859         }
2860
2861         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2862                 /* Turn on the copper */
2863                 ixgbe_set_phy_power(hw, true);
2864         } else {
2865                 /* Turn on the laser */
2866                 ixgbe_enable_tx_laser(hw);
2867         }
2868
2869         return 0;
2870 }
2871
2872 /*
2873  * Set device link down: disable tx.
2874  */
2875 static int
2876 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2877 {
2878         struct ixgbe_hw *hw =
2879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880         if (hw->mac.type == ixgbe_mac_82599EB) {
2881 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2882                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2883                         /* Not suported in bypass mode */
2884                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2885                                      "by device id 0x%x", hw->device_id);
2886                         return -ENOTSUP;
2887                 }
2888 #endif
2889         }
2890
2891         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2892                 /* Turn off the copper */
2893                 ixgbe_set_phy_power(hw, false);
2894         } else {
2895                 /* Turn off the laser */
2896                 ixgbe_disable_tx_laser(hw);
2897         }
2898
2899         return 0;
2900 }
2901
2902 /*
2903  * Reset and stop device.
2904  */
2905 static void
2906 ixgbe_dev_close(struct rte_eth_dev *dev)
2907 {
2908         struct ixgbe_hw *hw =
2909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910
2911         PMD_INIT_FUNC_TRACE();
2912
2913         ixgbe_pf_reset_hw(hw);
2914
2915         ixgbe_dev_stop(dev);
2916         hw->adapter_stopped = 1;
2917
2918         ixgbe_dev_free_queues(dev);
2919
2920         ixgbe_disable_pcie_master(hw);
2921
2922         /* reprogram the RAR[0] in case user changed it. */
2923         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2924 }
2925
2926 /*
2927  * Reset PF device.
2928  */
2929 static int
2930 ixgbe_dev_reset(struct rte_eth_dev *dev)
2931 {
2932         int ret;
2933
2934         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2935          * its VF to make them align with it. The detailed notification
2936          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2937          * To avoid unexpected behavior in VF, currently reset of PF with
2938          * SR-IOV activation is not supported. It might be supported later.
2939          */
2940         if (dev->data->sriov.active)
2941                 return -ENOTSUP;
2942
2943         ret = eth_ixgbe_dev_uninit(dev);
2944         if (ret)
2945                 return ret;
2946
2947         ret = eth_ixgbe_dev_init(dev, NULL);
2948
2949         return ret;
2950 }
2951
2952 static void
2953 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2954                            struct ixgbe_hw_stats *hw_stats,
2955                            struct ixgbe_macsec_stats *macsec_stats,
2956                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2957                            uint64_t *total_qprc, uint64_t *total_qprdc)
2958 {
2959         uint32_t bprc, lxon, lxoff, total;
2960         uint32_t delta_gprc = 0;
2961         unsigned i;
2962         /* Workaround for RX byte count not including CRC bytes when CRC
2963          * strip is enabled. CRC bytes are removed from counters when crc_strip
2964          * is disabled.
2965          */
2966         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2967                         IXGBE_HLREG0_RXCRCSTRP);
2968
2969         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2970         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2971         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2972         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2973
2974         for (i = 0; i < 8; i++) {
2975                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2976
2977                 /* global total per queue */
2978                 hw_stats->mpc[i] += mp;
2979                 /* Running comprehensive total for stats display */
2980                 *total_missed_rx += hw_stats->mpc[i];
2981                 if (hw->mac.type == ixgbe_mac_82598EB) {
2982                         hw_stats->rnbc[i] +=
2983                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2984                         hw_stats->pxonrxc[i] +=
2985                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2986                         hw_stats->pxoffrxc[i] +=
2987                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2988                 } else {
2989                         hw_stats->pxonrxc[i] +=
2990                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2991                         hw_stats->pxoffrxc[i] +=
2992                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2993                         hw_stats->pxon2offc[i] +=
2994                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2995                 }
2996                 hw_stats->pxontxc[i] +=
2997                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2998                 hw_stats->pxofftxc[i] +=
2999                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3000         }
3001         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3002                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3003                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3004                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3005
3006                 delta_gprc += delta_qprc;
3007
3008                 hw_stats->qprc[i] += delta_qprc;
3009                 hw_stats->qptc[i] += delta_qptc;
3010
3011                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3012                 hw_stats->qbrc[i] +=
3013                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3014                 if (crc_strip == 0)
3015                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3016
3017                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3018                 hw_stats->qbtc[i] +=
3019                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3020
3021                 hw_stats->qprdc[i] += delta_qprdc;
3022                 *total_qprdc += hw_stats->qprdc[i];
3023
3024                 *total_qprc += hw_stats->qprc[i];
3025                 *total_qbrc += hw_stats->qbrc[i];
3026         }
3027         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3028         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3029         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3030
3031         /*
3032          * An errata states that gprc actually counts good + missed packets:
3033          * Workaround to set gprc to summated queue packet receives
3034          */
3035         hw_stats->gprc = *total_qprc;
3036
3037         if (hw->mac.type != ixgbe_mac_82598EB) {
3038                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3039                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3040                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3041                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3042                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3043                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3044                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3045                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3046         } else {
3047                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3048                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3049                 /* 82598 only has a counter in the high register */
3050                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3051                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3052                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3053         }
3054         uint64_t old_tpr = hw_stats->tpr;
3055
3056         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3057         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3058
3059         if (crc_strip == 0)
3060                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3061
3062         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3063         hw_stats->gptc += delta_gptc;
3064         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3065         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3066
3067         /*
3068          * Workaround: mprc hardware is incorrectly counting
3069          * broadcasts, so for now we subtract those.
3070          */
3071         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3072         hw_stats->bprc += bprc;
3073         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3074         if (hw->mac.type == ixgbe_mac_82598EB)
3075                 hw_stats->mprc -= bprc;
3076
3077         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3078         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3079         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3080         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3081         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3082         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3083
3084         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3085         hw_stats->lxontxc += lxon;
3086         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3087         hw_stats->lxofftxc += lxoff;
3088         total = lxon + lxoff;
3089
3090         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3091         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3092         hw_stats->gptc -= total;
3093         hw_stats->mptc -= total;
3094         hw_stats->ptc64 -= total;
3095         hw_stats->gotc -= total * ETHER_MIN_LEN;
3096
3097         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3098         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3099         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3100         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3101         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3102         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3103         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3104         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3105         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3106         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3107         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3108         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3109         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3110         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3111         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3112         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3113         /* Only read FCOE on 82599 */
3114         if (hw->mac.type != ixgbe_mac_82598EB) {
3115                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3116                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3117                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3118                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3119                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3120         }
3121
3122         /* Flow Director Stats registers */
3123         if (hw->mac.type != ixgbe_mac_82598EB) {
3124                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3125                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3126                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3127                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3128                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3129                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3130                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3131                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3132                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3133                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3134         }
3135         /* MACsec Stats registers */
3136         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3137         macsec_stats->out_pkts_encrypted +=
3138                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3139         macsec_stats->out_pkts_protected +=
3140                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3141         macsec_stats->out_octets_encrypted +=
3142                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3143         macsec_stats->out_octets_protected +=
3144                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3145         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3146         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3147         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3148         macsec_stats->in_pkts_unknownsci +=
3149                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3150         macsec_stats->in_octets_decrypted +=
3151                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3152         macsec_stats->in_octets_validated +=
3153                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3154         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3155         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3156         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3157         for (i = 0; i < 2; i++) {
3158                 macsec_stats->in_pkts_ok +=
3159                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3160                 macsec_stats->in_pkts_invalid +=
3161                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3162                 macsec_stats->in_pkts_notvalid +=
3163                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3164         }
3165         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3166         macsec_stats->in_pkts_notusingsa +=
3167                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3168 }
3169
3170 /*
3171  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3172  */
3173 static int
3174 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3175 {
3176         struct ixgbe_hw *hw =
3177                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178         struct ixgbe_hw_stats *hw_stats =
3179                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3180         struct ixgbe_macsec_stats *macsec_stats =
3181                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3182                                 dev->data->dev_private);
3183         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3184         unsigned i;
3185
3186         total_missed_rx = 0;
3187         total_qbrc = 0;
3188         total_qprc = 0;
3189         total_qprdc = 0;
3190
3191         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3192                         &total_qbrc, &total_qprc, &total_qprdc);
3193
3194         if (stats == NULL)
3195                 return -EINVAL;
3196
3197         /* Fill out the rte_eth_stats statistics structure */
3198         stats->ipackets = total_qprc;
3199         stats->ibytes = total_qbrc;
3200         stats->opackets = hw_stats->gptc;
3201         stats->obytes = hw_stats->gotc;
3202
3203         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3204                 stats->q_ipackets[i] = hw_stats->qprc[i];
3205                 stats->q_opackets[i] = hw_stats->qptc[i];
3206                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3207                 stats->q_obytes[i] = hw_stats->qbtc[i];
3208                 stats->q_errors[i] = hw_stats->qprdc[i];
3209         }
3210
3211         /* Rx Errors */
3212         stats->imissed  = total_missed_rx;
3213         stats->ierrors  = hw_stats->crcerrs +
3214                           hw_stats->mspdc +
3215                           hw_stats->rlec +
3216                           hw_stats->ruc +
3217                           hw_stats->roc +
3218                           hw_stats->illerrc +
3219                           hw_stats->errbc +
3220                           hw_stats->rfc +
3221                           hw_stats->fccrc +
3222                           hw_stats->fclast;
3223
3224         /* Tx Errors */
3225         stats->oerrors  = 0;
3226         return 0;
3227 }
3228
3229 static void
3230 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3231 {
3232         struct ixgbe_hw_stats *stats =
3233                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3234
3235         /* HW registers are cleared on read */
3236         ixgbe_dev_stats_get(dev, NULL);
3237
3238         /* Reset software totals */
3239         memset(stats, 0, sizeof(*stats));
3240 }
3241
3242 /* This function calculates the number of xstats based on the current config */
3243 static unsigned
3244 ixgbe_xstats_calc_num(void) {
3245         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3246                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3247                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3248 }
3249
3250 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3251         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3252 {
3253         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3254         unsigned stat, i, count;
3255
3256         if (xstats_names != NULL) {
3257                 count = 0;
3258
3259                 /* Note: limit >= cnt_stats checked upstream
3260                  * in rte_eth_xstats_names()
3261                  */
3262
3263                 /* Extended stats from ixgbe_hw_stats */
3264                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3265                         snprintf(xstats_names[count].name,
3266                                 sizeof(xstats_names[count].name),
3267                                 "%s",
3268                                 rte_ixgbe_stats_strings[i].name);
3269                         count++;
3270                 }
3271
3272                 /* MACsec Stats */
3273                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3274                         snprintf(xstats_names[count].name,
3275                                 sizeof(xstats_names[count].name),
3276                                 "%s",
3277                                 rte_ixgbe_macsec_strings[i].name);
3278                         count++;
3279                 }
3280
3281                 /* RX Priority Stats */
3282                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3283                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3284                                 snprintf(xstats_names[count].name,
3285                                         sizeof(xstats_names[count].name),
3286                                         "rx_priority%u_%s", i,
3287                                         rte_ixgbe_rxq_strings[stat].name);
3288                                 count++;
3289                         }
3290                 }
3291
3292                 /* TX Priority Stats */
3293                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3294                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3295                                 snprintf(xstats_names[count].name,
3296                                         sizeof(xstats_names[count].name),
3297                                         "tx_priority%u_%s", i,
3298                                         rte_ixgbe_txq_strings[stat].name);
3299                                 count++;
3300                         }
3301                 }
3302         }
3303         return cnt_stats;
3304 }
3305
3306 static int ixgbe_dev_xstats_get_names_by_id(
3307         struct rte_eth_dev *dev,
3308         struct rte_eth_xstat_name *xstats_names,
3309         const uint64_t *ids,
3310         unsigned int limit)
3311 {
3312         if (!ids) {
3313                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3314                 unsigned int stat, i, count;
3315
3316                 if (xstats_names != NULL) {
3317                         count = 0;
3318
3319                         /* Note: limit >= cnt_stats checked upstream
3320                          * in rte_eth_xstats_names()
3321                          */
3322
3323                         /* Extended stats from ixgbe_hw_stats */
3324                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3325                                 snprintf(xstats_names[count].name,
3326                                         sizeof(xstats_names[count].name),
3327                                         "%s",
3328                                         rte_ixgbe_stats_strings[i].name);
3329                                 count++;
3330                         }
3331
3332                         /* MACsec Stats */
3333                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3334                                 snprintf(xstats_names[count].name,
3335                                         sizeof(xstats_names[count].name),
3336                                         "%s",
3337                                         rte_ixgbe_macsec_strings[i].name);
3338                                 count++;
3339                         }
3340
3341                         /* RX Priority Stats */
3342                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3343                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3344                                         snprintf(xstats_names[count].name,
3345                                             sizeof(xstats_names[count].name),
3346                                             "rx_priority%u_%s", i,
3347                                             rte_ixgbe_rxq_strings[stat].name);
3348                                         count++;
3349                                 }
3350                         }
3351
3352                         /* TX Priority Stats */
3353                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3354                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3355                                         snprintf(xstats_names[count].name,
3356                                             sizeof(xstats_names[count].name),
3357                                             "tx_priority%u_%s", i,
3358                                             rte_ixgbe_txq_strings[stat].name);
3359                                         count++;
3360                                 }
3361                         }
3362                 }
3363                 return cnt_stats;
3364         }
3365
3366         uint16_t i;
3367         uint16_t size = ixgbe_xstats_calc_num();
3368         struct rte_eth_xstat_name xstats_names_copy[size];
3369
3370         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3371                         size);
3372
3373         for (i = 0; i < limit; i++) {
3374                 if (ids[i] >= size) {
3375                         PMD_INIT_LOG(ERR, "id value isn't valid");
3376                         return -1;
3377                 }
3378                 strcpy(xstats_names[i].name,
3379                                 xstats_names_copy[ids[i]].name);
3380         }
3381         return limit;
3382 }
3383
3384 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3385         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3386 {
3387         unsigned i;
3388
3389         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3390                 return -ENOMEM;
3391
3392         if (xstats_names != NULL)
3393                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3394                         snprintf(xstats_names[i].name,
3395                                 sizeof(xstats_names[i].name),
3396                                 "%s", rte_ixgbevf_stats_strings[i].name);
3397         return IXGBEVF_NB_XSTATS;
3398 }
3399
3400 static int
3401 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3402                                          unsigned n)
3403 {
3404         struct ixgbe_hw *hw =
3405                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406         struct ixgbe_hw_stats *hw_stats =
3407                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3408         struct ixgbe_macsec_stats *macsec_stats =
3409                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3410                                 dev->data->dev_private);
3411         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3412         unsigned i, stat, count = 0;
3413
3414         count = ixgbe_xstats_calc_num();
3415
3416         if (n < count)
3417                 return count;
3418
3419         total_missed_rx = 0;
3420         total_qbrc = 0;
3421         total_qprc = 0;
3422         total_qprdc = 0;
3423
3424         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3425                         &total_qbrc, &total_qprc, &total_qprdc);
3426
3427         /* If this is a reset xstats is NULL, and we have cleared the
3428          * registers by reading them.
3429          */
3430         if (!xstats)
3431                 return 0;
3432
3433         /* Extended stats from ixgbe_hw_stats */
3434         count = 0;
3435         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3436                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3437                                 rte_ixgbe_stats_strings[i].offset);
3438                 xstats[count].id = count;
3439                 count++;
3440         }
3441
3442         /* MACsec Stats */
3443         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3444                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3445                                 rte_ixgbe_macsec_strings[i].offset);
3446                 xstats[count].id = count;
3447                 count++;
3448         }
3449
3450         /* RX Priority Stats */
3451         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3452                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3453                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3454                                         rte_ixgbe_rxq_strings[stat].offset +
3455                                         (sizeof(uint64_t) * i));
3456                         xstats[count].id = count;
3457                         count++;
3458                 }
3459         }
3460
3461         /* TX Priority Stats */
3462         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3463                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3464                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3465                                         rte_ixgbe_txq_strings[stat].offset +
3466                                         (sizeof(uint64_t) * i));
3467                         xstats[count].id = count;
3468                         count++;
3469                 }
3470         }
3471         return count;
3472 }
3473
3474 static int
3475 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3476                 uint64_t *values, unsigned int n)
3477 {
3478         if (!ids) {
3479                 struct ixgbe_hw *hw =
3480                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481                 struct ixgbe_hw_stats *hw_stats =
3482                                 IXGBE_DEV_PRIVATE_TO_STATS(
3483                                                 dev->data->dev_private);
3484                 struct ixgbe_macsec_stats *macsec_stats =
3485                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3486                                         dev->data->dev_private);
3487                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3488                 unsigned int i, stat, count = 0;
3489
3490                 count = ixgbe_xstats_calc_num();
3491
3492                 if (!ids && n < count)
3493                         return count;
3494
3495                 total_missed_rx = 0;
3496                 total_qbrc = 0;
3497                 total_qprc = 0;
3498                 total_qprdc = 0;
3499
3500                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3501                                 &total_missed_rx, &total_qbrc, &total_qprc,
3502                                 &total_qprdc);
3503
3504                 /* If this is a reset xstats is NULL, and we have cleared the
3505                  * registers by reading them.
3506                  */
3507                 if (!ids && !values)
3508                         return 0;
3509
3510                 /* Extended stats from ixgbe_hw_stats */
3511                 count = 0;
3512                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3513                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3514                                         rte_ixgbe_stats_strings[i].offset);
3515                         count++;
3516                 }
3517
3518                 /* MACsec Stats */
3519                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3520                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3521                                         rte_ixgbe_macsec_strings[i].offset);
3522                         count++;
3523                 }
3524
3525                 /* RX Priority Stats */
3526                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3527                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3528                                 values[count] =
3529                                         *(uint64_t *)(((char *)hw_stats) +
3530                                         rte_ixgbe_rxq_strings[stat].offset +
3531                                         (sizeof(uint64_t) * i));
3532                                 count++;
3533                         }
3534                 }
3535
3536                 /* TX Priority Stats */
3537                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3538                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3539                                 values[count] =
3540                                         *(uint64_t *)(((char *)hw_stats) +
3541                                         rte_ixgbe_txq_strings[stat].offset +
3542                                         (sizeof(uint64_t) * i));
3543                                 count++;
3544                         }
3545                 }
3546                 return count;
3547         }
3548
3549         uint16_t i;
3550         uint16_t size = ixgbe_xstats_calc_num();
3551         uint64_t values_copy[size];
3552
3553         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3554
3555         for (i = 0; i < n; i++) {
3556                 if (ids[i] >= size) {
3557                         PMD_INIT_LOG(ERR, "id value isn't valid");
3558                         return -1;
3559                 }
3560                 values[i] = values_copy[ids[i]];
3561         }
3562         return n;
3563 }
3564
3565 static void
3566 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3567 {
3568         struct ixgbe_hw_stats *stats =
3569                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3570         struct ixgbe_macsec_stats *macsec_stats =
3571                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3572                                 dev->data->dev_private);
3573
3574         unsigned count = ixgbe_xstats_calc_num();
3575
3576         /* HW registers are cleared on read */
3577         ixgbe_dev_xstats_get(dev, NULL, count);
3578
3579         /* Reset software totals */
3580         memset(stats, 0, sizeof(*stats));
3581         memset(macsec_stats, 0, sizeof(*macsec_stats));
3582 }
3583
3584 static void
3585 ixgbevf_update_stats(struct rte_eth_dev *dev)
3586 {
3587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590
3591         /* Good Rx packet, include VF loopback */
3592         UPDATE_VF_STAT(IXGBE_VFGPRC,
3593             hw_stats->last_vfgprc, hw_stats->vfgprc);
3594
3595         /* Good Rx octets, include VF loopback */
3596         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3597             hw_stats->last_vfgorc, hw_stats->vfgorc);
3598
3599         /* Good Tx packet, include VF loopback */
3600         UPDATE_VF_STAT(IXGBE_VFGPTC,
3601             hw_stats->last_vfgptc, hw_stats->vfgptc);
3602
3603         /* Good Tx octets, include VF loopback */
3604         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3605             hw_stats->last_vfgotc, hw_stats->vfgotc);
3606
3607         /* Rx Multicst Packet */
3608         UPDATE_VF_STAT(IXGBE_VFMPRC,
3609             hw_stats->last_vfmprc, hw_stats->vfmprc);
3610 }
3611
3612 static int
3613 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3614                        unsigned n)
3615 {
3616         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3617                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3618         unsigned i;
3619
3620         if (n < IXGBEVF_NB_XSTATS)
3621                 return IXGBEVF_NB_XSTATS;
3622
3623         ixgbevf_update_stats(dev);
3624
3625         if (!xstats)
3626                 return 0;
3627
3628         /* Extended stats */
3629         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3630                 xstats[i].id = i;
3631                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3632                         rte_ixgbevf_stats_strings[i].offset);
3633         }
3634
3635         return IXGBEVF_NB_XSTATS;
3636 }
3637
3638 static int
3639 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3640 {
3641         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3642                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3643
3644         ixgbevf_update_stats(dev);
3645
3646         if (stats == NULL)
3647                 return -EINVAL;
3648
3649         stats->ipackets = hw_stats->vfgprc;
3650         stats->ibytes = hw_stats->vfgorc;
3651         stats->opackets = hw_stats->vfgptc;
3652         stats->obytes = hw_stats->vfgotc;
3653         return 0;
3654 }
3655
3656 static void
3657 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3658 {
3659         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3660                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3661
3662         /* Sync HW register to the last stats */
3663         ixgbevf_dev_stats_get(dev, NULL);
3664
3665         /* reset HW current stats*/
3666         hw_stats->vfgprc = 0;
3667         hw_stats->vfgorc = 0;
3668         hw_stats->vfgptc = 0;
3669         hw_stats->vfgotc = 0;
3670 }
3671
3672 static int
3673 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3674 {
3675         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676         u16 eeprom_verh, eeprom_verl;
3677         u32 etrack_id;
3678         int ret;
3679
3680         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3681         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3682
3683         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3684         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3685
3686         ret += 1; /* add the size of '\0' */
3687         if (fw_size < (u32)ret)
3688                 return ret;
3689         else
3690                 return 0;
3691 }
3692
3693 static void
3694 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3695 {
3696         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3699
3700         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3701         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3702         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3703                 /*
3704                  * When DCB/VT is off, maximum number of queues changes,
3705                  * except for 82598EB, which remains constant.
3706                  */
3707                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3708                                 hw->mac.type != ixgbe_mac_82598EB)
3709                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3710         }
3711         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3712         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3713         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3714         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3715         dev_info->max_vfs = pci_dev->max_vfs;
3716         if (hw->mac.type == ixgbe_mac_82598EB)
3717                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3718         else
3719                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3720         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3721         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3722         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3723                                      dev_info->rx_queue_offload_capa);
3724         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3725         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3726
3727         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3728                 .rx_thresh = {
3729                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3730                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3731                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3732                 },
3733                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3734                 .rx_drop_en = 0,
3735                 .offloads = 0,
3736         };
3737
3738         dev_info->default_txconf = (struct rte_eth_txconf) {
3739                 .tx_thresh = {
3740                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3741                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3742                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3743                 },
3744                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3745                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3746                 .offloads = 0,
3747         };
3748
3749         dev_info->rx_desc_lim = rx_desc_lim;
3750         dev_info->tx_desc_lim = tx_desc_lim;
3751
3752         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3753         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3754         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3755
3756         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3757         if (hw->mac.type == ixgbe_mac_X540 ||
3758             hw->mac.type == ixgbe_mac_X540_vf ||
3759             hw->mac.type == ixgbe_mac_X550 ||
3760             hw->mac.type == ixgbe_mac_X550_vf) {
3761                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3762         }
3763         if (hw->mac.type == ixgbe_mac_X550) {
3764                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3765                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3766         }
3767
3768         /* Driver-preferred Rx/Tx parameters */
3769         dev_info->default_rxportconf.burst_size = 32;
3770         dev_info->default_txportconf.burst_size = 32;
3771         dev_info->default_rxportconf.nb_queues = 1;
3772         dev_info->default_txportconf.nb_queues = 1;
3773         dev_info->default_rxportconf.ring_size = 256;
3774         dev_info->default_txportconf.ring_size = 256;
3775 }
3776
3777 static const uint32_t *
3778 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3779 {
3780         static const uint32_t ptypes[] = {
3781                 /* For non-vec functions,
3782                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3783                  * for vec functions,
3784                  * refers to _recv_raw_pkts_vec().
3785                  */
3786                 RTE_PTYPE_L2_ETHER,
3787                 RTE_PTYPE_L3_IPV4,
3788                 RTE_PTYPE_L3_IPV4_EXT,
3789                 RTE_PTYPE_L3_IPV6,
3790                 RTE_PTYPE_L3_IPV6_EXT,
3791                 RTE_PTYPE_L4_SCTP,
3792                 RTE_PTYPE_L4_TCP,
3793                 RTE_PTYPE_L4_UDP,
3794                 RTE_PTYPE_TUNNEL_IP,
3795                 RTE_PTYPE_INNER_L3_IPV6,
3796                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3797                 RTE_PTYPE_INNER_L4_TCP,
3798                 RTE_PTYPE_INNER_L4_UDP,
3799                 RTE_PTYPE_UNKNOWN
3800         };
3801
3802         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3803             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3804             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3805             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3806                 return ptypes;
3807
3808 #if defined(RTE_ARCH_X86)
3809         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3810             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3811                 return ptypes;
3812 #endif
3813         return NULL;
3814 }
3815
3816 static void
3817 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3818                      struct rte_eth_dev_info *dev_info)
3819 {
3820         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822
3823         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3824         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3825         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3826         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3827         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3828         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3829         dev_info->max_vfs = pci_dev->max_vfs;
3830         if (hw->mac.type == ixgbe_mac_82598EB)
3831                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3832         else
3833                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3834         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3835         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3836                                      dev_info->rx_queue_offload_capa);
3837         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3838         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3839
3840         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3841                 .rx_thresh = {
3842                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3843                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3844                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3845                 },
3846                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3847                 .rx_drop_en = 0,
3848                 .offloads = 0,
3849         };
3850
3851         dev_info->default_txconf = (struct rte_eth_txconf) {
3852                 .tx_thresh = {
3853                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3854                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3855                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3856                 },
3857                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3858                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3859                 .offloads = 0,
3860         };
3861
3862         dev_info->rx_desc_lim = rx_desc_lim;
3863         dev_info->tx_desc_lim = tx_desc_lim;
3864 }
3865
3866 static int
3867 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3868                    int *link_up, int wait_to_complete)
3869 {
3870         /**
3871          * for a quick link status checking, wait_to_compelet == 0,
3872          * skip PF link status checking
3873          */
3874         bool no_pflink_check = wait_to_complete == 0;
3875         struct ixgbe_mbx_info *mbx = &hw->mbx;
3876         struct ixgbe_mac_info *mac = &hw->mac;
3877         uint32_t links_reg, in_msg;
3878         int ret_val = 0;
3879
3880         /* If we were hit with a reset drop the link */
3881         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3882                 mac->get_link_status = true;
3883
3884         if (!mac->get_link_status)
3885                 goto out;
3886
3887         /* if link status is down no point in checking to see if pf is up */
3888         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3889         if (!(links_reg & IXGBE_LINKS_UP))
3890                 goto out;
3891
3892         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3893          * before the link status is correct
3894          */
3895         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3896                 int i;
3897
3898                 for (i = 0; i < 5; i++) {
3899                         rte_delay_us(100);
3900                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3901
3902                         if (!(links_reg & IXGBE_LINKS_UP))
3903                                 goto out;
3904                 }
3905         }
3906
3907         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3908         case IXGBE_LINKS_SPEED_10G_82599:
3909                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3910                 if (hw->mac.type >= ixgbe_mac_X550) {
3911                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3912                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3913                 }
3914                 break;
3915         case IXGBE_LINKS_SPEED_1G_82599:
3916                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3917                 break;
3918         case IXGBE_LINKS_SPEED_100_82599:
3919                 *speed = IXGBE_LINK_SPEED_100_FULL;
3920                 if (hw->mac.type == ixgbe_mac_X550) {
3921                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3922                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3923                 }
3924                 break;
3925         case IXGBE_LINKS_SPEED_10_X550EM_A:
3926                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3927                 /* Since Reserved in older MAC's */
3928                 if (hw->mac.type >= ixgbe_mac_X550)
3929                         *speed = IXGBE_LINK_SPEED_10_FULL;
3930                 break;
3931         default:
3932                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3933         }
3934
3935         if (no_pflink_check) {
3936                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3937                         mac->get_link_status = true;
3938                 else
3939                         mac->get_link_status = false;
3940
3941                 goto out;
3942         }
3943         /* if the read failed it could just be a mailbox collision, best wait
3944          * until we are called again and don't report an error
3945          */
3946         if (mbx->ops.read(hw, &in_msg, 1, 0))
3947                 goto out;
3948
3949         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3950                 /* msg is not CTS and is NACK we must have lost CTS status */
3951                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3952                         ret_val = -1;
3953                 goto out;
3954         }
3955
3956         /* the pf is talking, if we timed out in the past we reinit */
3957         if (!mbx->timeout) {
3958                 ret_val = -1;
3959                 goto out;
3960         }
3961
3962         /* if we passed all the tests above then the link is up and we no
3963          * longer need to check for link
3964          */
3965         mac->get_link_status = false;
3966
3967 out:
3968         *link_up = !mac->get_link_status;
3969         return ret_val;
3970 }
3971
3972 /* return 0 means link status changed, -1 means not changed */
3973 int
3974 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3975                             int wait_to_complete, int vf)
3976 {
3977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3978         struct rte_eth_link link;
3979         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3980         struct ixgbe_interrupt *intr =
3981                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3982         int link_up;
3983         int diag;
3984         u32 speed = 0;
3985         int wait = 1;
3986         bool autoneg = false;
3987
3988         memset(&link, 0, sizeof(link));
3989         link.link_status = ETH_LINK_DOWN;
3990         link.link_speed = ETH_SPEED_NUM_NONE;
3991         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3992         link.link_autoneg = ETH_LINK_AUTONEG;
3993
3994         hw->mac.get_link_status = true;
3995
3996         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3997                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3998                 speed = hw->phy.autoneg_advertised;
3999                 if (!speed)
4000                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4001                 ixgbe_setup_link(hw, speed, true);
4002         }
4003
4004         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4005         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4006                 wait = 0;
4007
4008         if (vf)
4009                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4010         else
4011                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4012
4013         if (diag != 0) {
4014                 link.link_speed = ETH_SPEED_NUM_100M;
4015                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4016                 return rte_eth_linkstatus_set(dev, &link);
4017         }
4018
4019         if (link_up == 0) {
4020                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4021                 return rte_eth_linkstatus_set(dev, &link);
4022         }
4023
4024         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4025         link.link_status = ETH_LINK_UP;
4026         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4027
4028         switch (link_speed) {
4029         default:
4030         case IXGBE_LINK_SPEED_UNKNOWN:
4031                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4032                 link.link_speed = ETH_SPEED_NUM_100M;
4033                 break;
4034
4035         case IXGBE_LINK_SPEED_100_FULL:
4036                 link.link_speed = ETH_SPEED_NUM_100M;
4037                 break;
4038
4039         case IXGBE_LINK_SPEED_1GB_FULL:
4040                 link.link_speed = ETH_SPEED_NUM_1G;
4041                 break;
4042
4043         case IXGBE_LINK_SPEED_2_5GB_FULL:
4044                 link.link_speed = ETH_SPEED_NUM_2_5G;
4045                 break;
4046
4047         case IXGBE_LINK_SPEED_5GB_FULL:
4048                 link.link_speed = ETH_SPEED_NUM_5G;
4049                 break;
4050
4051         case IXGBE_LINK_SPEED_10GB_FULL:
4052                 link.link_speed = ETH_SPEED_NUM_10G;
4053                 break;
4054         }
4055
4056         return rte_eth_linkstatus_set(dev, &link);
4057 }
4058
4059 static int
4060 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4061 {
4062         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4063 }
4064
4065 static int
4066 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4067 {
4068         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4069 }
4070
4071 static void
4072 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4073 {
4074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075         uint32_t fctrl;
4076
4077         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4078         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4079         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4080 }
4081
4082 static void
4083 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4084 {
4085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086         uint32_t fctrl;
4087
4088         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4089         fctrl &= (~IXGBE_FCTRL_UPE);
4090         if (dev->data->all_multicast == 1)
4091                 fctrl |= IXGBE_FCTRL_MPE;
4092         else
4093                 fctrl &= (~IXGBE_FCTRL_MPE);
4094         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4095 }
4096
4097 static void
4098 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4099 {
4100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         uint32_t fctrl;
4102
4103         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4104         fctrl |= IXGBE_FCTRL_MPE;
4105         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4106 }
4107
4108 static void
4109 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4110 {
4111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         uint32_t fctrl;
4113
4114         if (dev->data->promiscuous == 1)
4115                 return; /* must remain in all_multicast mode */
4116
4117         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4118         fctrl &= (~IXGBE_FCTRL_MPE);
4119         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4120 }
4121
4122 /**
4123  * It clears the interrupt causes and enables the interrupt.
4124  * It will be called once only during nic initialized.
4125  *
4126  * @param dev
4127  *  Pointer to struct rte_eth_dev.
4128  * @param on
4129  *  Enable or Disable.
4130  *
4131  * @return
4132  *  - On success, zero.
4133  *  - On failure, a negative value.
4134  */
4135 static int
4136 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4137 {
4138         struct ixgbe_interrupt *intr =
4139                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4140
4141         ixgbe_dev_link_status_print(dev);
4142         if (on)
4143                 intr->mask |= IXGBE_EICR_LSC;
4144         else
4145                 intr->mask &= ~IXGBE_EICR_LSC;
4146
4147         return 0;
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  *
4157  * @return
4158  *  - On success, zero.
4159  *  - On failure, a negative value.
4160  */
4161 static int
4162 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4163 {
4164         struct ixgbe_interrupt *intr =
4165                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4166
4167         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4168
4169         return 0;
4170 }
4171
4172 /**
4173  * It clears the interrupt causes and enables the interrupt.
4174  * It will be called once only during nic initialized.
4175  *
4176  * @param dev
4177  *  Pointer to struct rte_eth_dev.
4178  *
4179  * @return
4180  *  - On success, zero.
4181  *  - On failure, a negative value.
4182  */
4183 static int
4184 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4185 {
4186         struct ixgbe_interrupt *intr =
4187                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4188
4189         intr->mask |= IXGBE_EICR_LINKSEC;
4190
4191         return 0;
4192 }
4193
4194 /*
4195  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4196  *
4197  * @param dev
4198  *  Pointer to struct rte_eth_dev.
4199  *
4200  * @return
4201  *  - On success, zero.
4202  *  - On failure, a negative value.
4203  */
4204 static int
4205 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4206 {
4207         uint32_t eicr;
4208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209         struct ixgbe_interrupt *intr =
4210                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4211
4212         /* clear all cause mask */
4213         ixgbe_disable_intr(hw);
4214
4215         /* read-on-clear nic registers here */
4216         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4217         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4218
4219         intr->flags = 0;
4220
4221         /* set flag for async link update */
4222         if (eicr & IXGBE_EICR_LSC)
4223                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4224
4225         if (eicr & IXGBE_EICR_MAILBOX)
4226                 intr->flags |= IXGBE_FLAG_MAILBOX;
4227
4228         if (eicr & IXGBE_EICR_LINKSEC)
4229                 intr->flags |= IXGBE_FLAG_MACSEC;
4230
4231         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4232             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4233             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4234                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4235
4236         return 0;
4237 }
4238
4239 /**
4240  * It gets and then prints the link status.
4241  *
4242  * @param dev
4243  *  Pointer to struct rte_eth_dev.
4244  *
4245  * @return
4246  *  - On success, zero.
4247  *  - On failure, a negative value.
4248  */
4249 static void
4250 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4251 {
4252         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4253         struct rte_eth_link link;
4254
4255         rte_eth_linkstatus_get(dev, &link);
4256
4257         if (link.link_status) {
4258                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4259                                         (int)(dev->data->port_id),
4260                                         (unsigned)link.link_speed,
4261                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4262                                         "full-duplex" : "half-duplex");
4263         } else {
4264                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4265                                 (int)(dev->data->port_id));
4266         }
4267         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4268                                 pci_dev->addr.domain,
4269                                 pci_dev->addr.bus,
4270                                 pci_dev->addr.devid,
4271                                 pci_dev->addr.function);
4272 }
4273
4274 /*
4275  * It executes link_update after knowing an interrupt occurred.
4276  *
4277  * @param dev
4278  *  Pointer to struct rte_eth_dev.
4279  *
4280  * @return
4281  *  - On success, zero.
4282  *  - On failure, a negative value.
4283  */
4284 static int
4285 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4286                            struct rte_intr_handle *intr_handle)
4287 {
4288         struct ixgbe_interrupt *intr =
4289                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4290         int64_t timeout;
4291         struct ixgbe_hw *hw =
4292                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293
4294         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4295
4296         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4297                 ixgbe_pf_mbx_process(dev);
4298                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4299         }
4300
4301         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4302                 ixgbe_handle_lasi(hw);
4303                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4304         }
4305
4306         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4307                 struct rte_eth_link link;
4308
4309                 /* get the link status before link update, for predicting later */
4310                 rte_eth_linkstatus_get(dev, &link);
4311
4312                 ixgbe_dev_link_update(dev, 0);
4313
4314                 /* likely to up */
4315                 if (!link.link_status)
4316                         /* handle it 1 sec later, wait it being stable */
4317                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4318                 /* likely to down */
4319                 else
4320                         /* handle it 4 sec later, wait it being stable */
4321                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4322
4323                 ixgbe_dev_link_status_print(dev);
4324                 if (rte_eal_alarm_set(timeout * 1000,
4325                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4326                         PMD_DRV_LOG(ERR, "Error setting alarm");
4327                 else {
4328                         /* remember original mask */
4329                         intr->mask_original = intr->mask;
4330                         /* only disable lsc interrupt */
4331                         intr->mask &= ~IXGBE_EIMS_LSC;
4332                 }
4333         }
4334
4335         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4336         ixgbe_enable_intr(dev);
4337         rte_intr_enable(intr_handle);
4338
4339         return 0;
4340 }
4341
4342 /**
4343  * Interrupt handler which shall be registered for alarm callback for delayed
4344  * handling specific interrupt to wait for the stable nic state. As the
4345  * NIC interrupt state is not stable for ixgbe after link is just down,
4346  * it needs to wait 4 seconds to get the stable status.
4347  *
4348  * @param handle
4349  *  Pointer to interrupt handle.
4350  * @param param
4351  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4352  *
4353  * @return
4354  *  void
4355  */
4356 static void
4357 ixgbe_dev_interrupt_delayed_handler(void *param)
4358 {
4359         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4360         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4362         struct ixgbe_interrupt *intr =
4363                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4364         struct ixgbe_hw *hw =
4365                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366         uint32_t eicr;
4367
4368         ixgbe_disable_intr(hw);
4369
4370         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4371         if (eicr & IXGBE_EICR_MAILBOX)
4372                 ixgbe_pf_mbx_process(dev);
4373
4374         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4375                 ixgbe_handle_lasi(hw);
4376                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4377         }
4378
4379         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4380                 ixgbe_dev_link_update(dev, 0);
4381                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4382                 ixgbe_dev_link_status_print(dev);
4383                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4384                                               NULL);
4385         }
4386
4387         if (intr->flags & IXGBE_FLAG_MACSEC) {
4388                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4389                                               NULL);
4390                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4391         }
4392
4393         /* restore original mask */
4394         intr->mask = intr->mask_original;
4395         intr->mask_original = 0;
4396
4397         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4398         ixgbe_enable_intr(dev);
4399         rte_intr_enable(intr_handle);
4400 }
4401
4402 /**
4403  * Interrupt handler triggered by NIC  for handling
4404  * specific interrupt.
4405  *
4406  * @param handle
4407  *  Pointer to interrupt handle.
4408  * @param param
4409  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4410  *
4411  * @return
4412  *  void
4413  */
4414 static void
4415 ixgbe_dev_interrupt_handler(void *param)
4416 {
4417         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4418
4419         ixgbe_dev_interrupt_get_status(dev);
4420         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4421 }
4422
4423 static int
4424 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4425 {
4426         struct ixgbe_hw *hw;
4427
4428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4429         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4430 }
4431
4432 static int
4433 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4434 {
4435         struct ixgbe_hw *hw;
4436
4437         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4439 }
4440
4441 static int
4442 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4443 {
4444         struct ixgbe_hw *hw;
4445         uint32_t mflcn_reg;
4446         uint32_t fccfg_reg;
4447         int rx_pause;
4448         int tx_pause;
4449
4450         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451
4452         fc_conf->pause_time = hw->fc.pause_time;
4453         fc_conf->high_water = hw->fc.high_water[0];
4454         fc_conf->low_water = hw->fc.low_water[0];
4455         fc_conf->send_xon = hw->fc.send_xon;
4456         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4457
4458         /*
4459          * Return rx_pause status according to actual setting of
4460          * MFLCN register.
4461          */
4462         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4463         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4464                 rx_pause = 1;
4465         else
4466                 rx_pause = 0;
4467
4468         /*
4469          * Return tx_pause status according to actual setting of
4470          * FCCFG register.
4471          */
4472         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4473         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4474                 tx_pause = 1;
4475         else
4476                 tx_pause = 0;
4477
4478         if (rx_pause && tx_pause)
4479                 fc_conf->mode = RTE_FC_FULL;
4480         else if (rx_pause)
4481                 fc_conf->mode = RTE_FC_RX_PAUSE;
4482         else if (tx_pause)
4483                 fc_conf->mode = RTE_FC_TX_PAUSE;
4484         else
4485                 fc_conf->mode = RTE_FC_NONE;
4486
4487         return 0;
4488 }
4489
4490 static int
4491 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4492 {
4493         struct ixgbe_hw *hw;
4494         int err;
4495         uint32_t rx_buf_size;
4496         uint32_t max_high_water;
4497         uint32_t mflcn;
4498         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4499                 ixgbe_fc_none,
4500                 ixgbe_fc_rx_pause,
4501                 ixgbe_fc_tx_pause,
4502                 ixgbe_fc_full
4503         };
4504
4505         PMD_INIT_FUNC_TRACE();
4506
4507         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4509         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4510
4511         /*
4512          * At least reserve one Ethernet frame for watermark
4513          * high_water/low_water in kilo bytes for ixgbe
4514          */
4515         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4516         if ((fc_conf->high_water > max_high_water) ||
4517                 (fc_conf->high_water < fc_conf->low_water)) {
4518                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4519                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4520                 return -EINVAL;
4521         }
4522
4523         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4524         hw->fc.pause_time     = fc_conf->pause_time;
4525         hw->fc.high_water[0]  = fc_conf->high_water;
4526         hw->fc.low_water[0]   = fc_conf->low_water;
4527         hw->fc.send_xon       = fc_conf->send_xon;
4528         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4529
4530         err = ixgbe_fc_enable(hw);
4531
4532         /* Not negotiated is not an error case */
4533         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4534
4535                 /* check if we want to forward MAC frames - driver doesn't have native
4536                  * capability to do that, so we'll write the registers ourselves */
4537
4538                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4539
4540                 /* set or clear MFLCN.PMCF bit depending on configuration */
4541                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4542                         mflcn |= IXGBE_MFLCN_PMCF;
4543                 else
4544                         mflcn &= ~IXGBE_MFLCN_PMCF;
4545
4546                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4547                 IXGBE_WRITE_FLUSH(hw);
4548
4549                 return 0;
4550         }
4551
4552         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4553         return -EIO;
4554 }
4555
4556 /**
4557  *  ixgbe_pfc_enable_generic - Enable flow control
4558  *  @hw: pointer to hardware structure
4559  *  @tc_num: traffic class number
4560  *  Enable flow control according to the current settings.
4561  */
4562 static int
4563 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4564 {
4565         int ret_val = 0;
4566         uint32_t mflcn_reg, fccfg_reg;
4567         uint32_t reg;
4568         uint32_t fcrtl, fcrth;
4569         uint8_t i;
4570         uint8_t nb_rx_en;
4571
4572         /* Validate the water mark configuration */
4573         if (!hw->fc.pause_time) {
4574                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4575                 goto out;
4576         }
4577
4578         /* Low water mark of zero causes XOFF floods */
4579         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4580                  /* High/Low water can not be 0 */
4581                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4582                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4583                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4584                         goto out;
4585                 }
4586
4587                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4588                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4589                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4590                         goto out;
4591                 }
4592         }
4593         /* Negotiate the fc mode to use */
4594         ixgbe_fc_autoneg(hw);
4595
4596         /* Disable any previous flow control settings */
4597         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4598         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4599
4600         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4601         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4602
4603         switch (hw->fc.current_mode) {
4604         case ixgbe_fc_none:
4605                 /*
4606                  * If the count of enabled RX Priority Flow control >1,
4607                  * and the TX pause can not be disabled
4608                  */
4609                 nb_rx_en = 0;
4610                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4611                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4612                         if (reg & IXGBE_FCRTH_FCEN)
4613                                 nb_rx_en++;
4614                 }
4615                 if (nb_rx_en > 1)
4616                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4617                 break;
4618         case ixgbe_fc_rx_pause:
4619                 /*
4620                  * Rx Flow control is enabled and Tx Flow control is
4621                  * disabled by software override. Since there really
4622                  * isn't a way to advertise that we are capable of RX
4623                  * Pause ONLY, we will advertise that we support both
4624                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4625                  * disable the adapter's ability to send PAUSE frames.
4626                  */
4627                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4628                 /*
4629                  * If the count of enabled RX Priority Flow control >1,
4630                  * and the TX pause can not be disabled
4631                  */
4632                 nb_rx_en = 0;
4633                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4634                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4635                         if (reg & IXGBE_FCRTH_FCEN)
4636                                 nb_rx_en++;
4637                 }
4638                 if (nb_rx_en > 1)
4639                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4640                 break;
4641         case ixgbe_fc_tx_pause:
4642                 /*
4643                  * Tx Flow control is enabled, and Rx Flow control is
4644                  * disabled by software override.
4645                  */
4646                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4647                 break;
4648         case ixgbe_fc_full:
4649                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4650                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4651                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4652                 break;
4653         default:
4654                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4655                 ret_val = IXGBE_ERR_CONFIG;
4656                 goto out;
4657         }
4658
4659         /* Set 802.3x based flow control settings. */
4660         mflcn_reg |= IXGBE_MFLCN_DPF;
4661         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4662         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4663
4664         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4665         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4666                 hw->fc.high_water[tc_num]) {
4667                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4668                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4669                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4670         } else {
4671                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4672                 /*
4673                  * In order to prevent Tx hangs when the internal Tx
4674                  * switch is enabled we must set the high water mark
4675                  * to the maximum FCRTH value.  This allows the Tx
4676                  * switch to function even under heavy Rx workloads.
4677                  */
4678                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4679         }
4680         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4681
4682         /* Configure pause time (2 TCs per register) */
4683         reg = hw->fc.pause_time * 0x00010001;
4684         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4685                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4686
4687         /* Configure flow control refresh threshold value */
4688         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4689
4690 out:
4691         return ret_val;
4692 }
4693
4694 static int
4695 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4696 {
4697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4699
4700         if (hw->mac.type != ixgbe_mac_82598EB) {
4701                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4702         }
4703         return ret_val;
4704 }
4705
4706 static int
4707 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4708 {
4709         int err;
4710         uint32_t rx_buf_size;
4711         uint32_t max_high_water;
4712         uint8_t tc_num;
4713         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4714         struct ixgbe_hw *hw =
4715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4716         struct ixgbe_dcb_config *dcb_config =
4717                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4718
4719         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4720                 ixgbe_fc_none,
4721                 ixgbe_fc_rx_pause,
4722                 ixgbe_fc_tx_pause,
4723                 ixgbe_fc_full
4724         };
4725
4726         PMD_INIT_FUNC_TRACE();
4727
4728         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4729         tc_num = map[pfc_conf->priority];
4730         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4731         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4732         /*
4733          * At least reserve one Ethernet frame for watermark
4734          * high_water/low_water in kilo bytes for ixgbe
4735          */
4736         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4737         if ((pfc_conf->fc.high_water > max_high_water) ||
4738             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4739                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4740                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4741                 return -EINVAL;
4742         }
4743
4744         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4745         hw->fc.pause_time = pfc_conf->fc.pause_time;
4746         hw->fc.send_xon = pfc_conf->fc.send_xon;
4747         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4748         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4749
4750         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4751
4752         /* Not negotiated is not an error case */
4753         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4754                 return 0;
4755
4756         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4757         return -EIO;
4758 }
4759
4760 static int
4761 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4762                           struct rte_eth_rss_reta_entry64 *reta_conf,
4763                           uint16_t reta_size)
4764 {
4765         uint16_t i, sp_reta_size;
4766         uint8_t j, mask;
4767         uint32_t reta, r;
4768         uint16_t idx, shift;
4769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770         uint32_t reta_reg;
4771
4772         PMD_INIT_FUNC_TRACE();
4773
4774         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4775                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4776                         "NIC.");
4777                 return -ENOTSUP;
4778         }
4779
4780         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4781         if (reta_size != sp_reta_size) {
4782                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4783                         "(%d) doesn't match the number hardware can supported "
4784                         "(%d)", reta_size, sp_reta_size);
4785                 return -EINVAL;
4786         }
4787
4788         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4789                 idx = i / RTE_RETA_GROUP_SIZE;
4790                 shift = i % RTE_RETA_GROUP_SIZE;
4791                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4792                                                 IXGBE_4_BIT_MASK);
4793                 if (!mask)
4794                         continue;
4795                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4796                 if (mask == IXGBE_4_BIT_MASK)
4797                         r = 0;
4798                 else
4799                         r = IXGBE_READ_REG(hw, reta_reg);
4800                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4801                         if (mask & (0x1 << j))
4802                                 reta |= reta_conf[idx].reta[shift + j] <<
4803                                                         (CHAR_BIT * j);
4804                         else
4805                                 reta |= r & (IXGBE_8_BIT_MASK <<
4806                                                 (CHAR_BIT * j));
4807                 }
4808                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4809         }
4810
4811         return 0;
4812 }
4813
4814 static int
4815 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4816                          struct rte_eth_rss_reta_entry64 *reta_conf,
4817                          uint16_t reta_size)
4818 {
4819         uint16_t i, sp_reta_size;
4820         uint8_t j, mask;
4821         uint32_t reta;
4822         uint16_t idx, shift;
4823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4824         uint32_t reta_reg;
4825
4826         PMD_INIT_FUNC_TRACE();
4827         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4828         if (reta_size != sp_reta_size) {
4829                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4830                         "(%d) doesn't match the number hardware can supported "
4831                         "(%d)", reta_size, sp_reta_size);
4832                 return -EINVAL;
4833         }
4834
4835         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4836                 idx = i / RTE_RETA_GROUP_SIZE;
4837                 shift = i % RTE_RETA_GROUP_SIZE;
4838                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4839                                                 IXGBE_4_BIT_MASK);
4840                 if (!mask)
4841                         continue;
4842
4843                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4844                 reta = IXGBE_READ_REG(hw, reta_reg);
4845                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4846                         if (mask & (0x1 << j))
4847                                 reta_conf[idx].reta[shift + j] =
4848                                         ((reta >> (CHAR_BIT * j)) &
4849                                                 IXGBE_8_BIT_MASK);
4850                 }
4851         }
4852
4853         return 0;
4854 }
4855
4856 static int
4857 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4858                                 uint32_t index, uint32_t pool)
4859 {
4860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         uint32_t enable_addr = 1;
4862
4863         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4864                              pool, enable_addr);
4865 }
4866
4867 static void
4868 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4869 {
4870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871
4872         ixgbe_clear_rar(hw, index);
4873 }
4874
4875 static int
4876 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4877 {
4878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4879
4880         ixgbe_remove_rar(dev, 0);
4881         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4882
4883         return 0;
4884 }
4885
4886 static bool
4887 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4888 {
4889         if (strcmp(dev->device->driver->name, drv->driver.name))
4890                 return false;
4891
4892         return true;
4893 }
4894
4895 bool
4896 is_ixgbe_supported(struct rte_eth_dev *dev)
4897 {
4898         return is_device_supported(dev, &rte_ixgbe_pmd);
4899 }
4900
4901 static int
4902 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4903 {
4904         uint32_t hlreg0;
4905         uint32_t maxfrs;
4906         struct ixgbe_hw *hw;
4907         struct rte_eth_dev_info dev_info;
4908         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4909         struct rte_eth_dev_data *dev_data = dev->data;
4910
4911         ixgbe_dev_info_get(dev, &dev_info);
4912
4913         /* check that mtu is within the allowed range */
4914         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4915                 return -EINVAL;
4916
4917         /* If device is started, refuse mtu that requires the support of
4918          * scattered packets when this feature has not been enabled before.
4919          */
4920         if (dev_data->dev_started && !dev_data->scattered_rx &&
4921             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4922              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4923                 PMD_INIT_LOG(ERR, "Stop port first.");
4924                 return -EINVAL;
4925         }
4926
4927         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4929
4930         /* switch to jumbo mode if needed */
4931         if (frame_size > ETHER_MAX_LEN) {
4932                 dev->data->dev_conf.rxmode.offloads |=
4933                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4934                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4935         } else {
4936                 dev->data->dev_conf.rxmode.offloads &=
4937                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4938                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4939         }
4940         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4941
4942         /* update max frame size */
4943         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4944
4945         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4946         maxfrs &= 0x0000FFFF;
4947         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4948         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4949
4950         return 0;
4951 }
4952
4953 /*
4954  * Virtual Function operations
4955  */
4956 static void
4957 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4958 {
4959         struct ixgbe_interrupt *intr =
4960                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4961         struct ixgbe_hw *hw =
4962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963
4964         PMD_INIT_FUNC_TRACE();
4965
4966         /* Clear interrupt mask to stop from interrupts being generated */
4967         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4968
4969         IXGBE_WRITE_FLUSH(hw);
4970
4971         /* Clear mask value. */
4972         intr->mask = 0;
4973 }
4974
4975 static void
4976 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4977 {
4978         struct ixgbe_interrupt *intr =
4979                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4980         struct ixgbe_hw *hw =
4981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982
4983         PMD_INIT_FUNC_TRACE();
4984
4985         /* VF enable interrupt autoclean */
4986         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4987         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4988         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4989
4990         IXGBE_WRITE_FLUSH(hw);
4991
4992         /* Save IXGBE_VTEIMS value to mask. */
4993         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4994 }
4995
4996 static int
4997 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4998 {
4999         struct rte_eth_conf *conf = &dev->data->dev_conf;
5000         struct ixgbe_adapter *adapter =
5001                         (struct ixgbe_adapter *)dev->data->dev_private;
5002
5003         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5004                      dev->data->port_id);
5005
5006         /*
5007          * VF has no ability to enable/disable HW CRC
5008          * Keep the persistent behavior the same as Host PF
5009          */
5010 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5011         if (rte_eth_dev_must_keep_crc(conf->rxmode.offloads)) {
5012                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5013                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
5014         }
5015 #else
5016         if (!rte_eth_dev_must_keep_crc(conf->rxmode.offloads)) {
5017                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5018                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5019         }
5020 #endif
5021
5022         /*
5023          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5024          * allocation or vector Rx preconditions we will reset it.
5025          */
5026         adapter->rx_bulk_alloc_allowed = true;
5027         adapter->rx_vec_allowed = true;
5028
5029         return 0;
5030 }
5031
5032 static int
5033 ixgbevf_dev_start(struct rte_eth_dev *dev)
5034 {
5035         struct ixgbe_hw *hw =
5036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037         uint32_t intr_vector = 0;
5038         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5039         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5040
5041         int err, mask = 0;
5042
5043         PMD_INIT_FUNC_TRACE();
5044
5045         err = hw->mac.ops.reset_hw(hw);
5046         if (err) {
5047                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5048                 return err;
5049         }
5050         hw->mac.get_link_status = true;
5051
5052         /* negotiate mailbox API version to use with the PF. */
5053         ixgbevf_negotiate_api(hw);
5054
5055         ixgbevf_dev_tx_init(dev);
5056
5057         /* This can fail when allocating mbufs for descriptor rings */
5058         err = ixgbevf_dev_rx_init(dev);
5059         if (err) {
5060                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5061                 ixgbe_dev_clear_queues(dev);
5062                 return err;
5063         }
5064
5065         /* Set vfta */
5066         ixgbevf_set_vfta_all(dev, 1);
5067
5068         /* Set HW strip */
5069         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5070                 ETH_VLAN_EXTEND_MASK;
5071         err = ixgbevf_vlan_offload_config(dev, mask);
5072         if (err) {
5073                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5074                 ixgbe_dev_clear_queues(dev);
5075                 return err;
5076         }
5077
5078         ixgbevf_dev_rxtx_start(dev);
5079
5080         ixgbevf_dev_link_update(dev, 0);
5081
5082         /* check and configure queue intr-vector mapping */
5083         if (rte_intr_cap_multiple(intr_handle) &&
5084             dev->data->dev_conf.intr_conf.rxq) {
5085                 /* According to datasheet, only vector 0/1/2 can be used,
5086                  * now only one vector is used for Rx queue
5087                  */
5088                 intr_vector = 1;
5089                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5090                         return -1;
5091         }
5092
5093         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5094                 intr_handle->intr_vec =
5095                         rte_zmalloc("intr_vec",
5096                                     dev->data->nb_rx_queues * sizeof(int), 0);
5097                 if (intr_handle->intr_vec == NULL) {
5098                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5099                                      " intr_vec", dev->data->nb_rx_queues);
5100                         return -ENOMEM;
5101                 }
5102         }
5103         ixgbevf_configure_msix(dev);
5104
5105         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5106          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5107          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5108          * is not cleared, it will fail when following rte_intr_enable( ) tries
5109          * to map Rx queue interrupt to other VFIO vectors.
5110          * So clear uio/vfio intr/evevnfd first to avoid failure.
5111          */
5112         rte_intr_disable(intr_handle);
5113
5114         rte_intr_enable(intr_handle);
5115
5116         /* Re-enable interrupt for VF */
5117         ixgbevf_intr_enable(dev);
5118
5119         return 0;
5120 }
5121
5122 static void
5123 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5124 {
5125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5128
5129         PMD_INIT_FUNC_TRACE();
5130
5131         ixgbevf_intr_disable(dev);
5132
5133         hw->adapter_stopped = 1;
5134         ixgbe_stop_adapter(hw);
5135
5136         /*
5137           * Clear what we set, but we still keep shadow_vfta to
5138           * restore after device starts
5139           */
5140         ixgbevf_set_vfta_all(dev, 0);
5141
5142         /* Clear stored conf */
5143         dev->data->scattered_rx = 0;
5144
5145         ixgbe_dev_clear_queues(dev);
5146
5147         /* Clean datapath event and queue/vec mapping */
5148         rte_intr_efd_disable(intr_handle);
5149         if (intr_handle->intr_vec != NULL) {
5150                 rte_free(intr_handle->intr_vec);
5151                 intr_handle->intr_vec = NULL;
5152         }
5153 }
5154
5155 static void
5156 ixgbevf_dev_close(struct rte_eth_dev *dev)
5157 {
5158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5159
5160         PMD_INIT_FUNC_TRACE();
5161
5162         ixgbe_reset_hw(hw);
5163
5164         ixgbevf_dev_stop(dev);
5165
5166         ixgbe_dev_free_queues(dev);
5167
5168         /**
5169          * Remove the VF MAC address ro ensure
5170          * that the VF traffic goes to the PF
5171          * after stop, close and detach of the VF
5172          **/
5173         ixgbevf_remove_mac_addr(dev, 0);
5174 }
5175
5176 /*
5177  * Reset VF device
5178  */
5179 static int
5180 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5181 {
5182         int ret;
5183
5184         ret = eth_ixgbevf_dev_uninit(dev);
5185         if (ret)
5186                 return ret;
5187
5188         ret = eth_ixgbevf_dev_init(dev);
5189
5190         return ret;
5191 }
5192
5193 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5194 {
5195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196         struct ixgbe_vfta *shadow_vfta =
5197                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5198         int i = 0, j = 0, vfta = 0, mask = 1;
5199
5200         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5201                 vfta = shadow_vfta->vfta[i];
5202                 if (vfta) {
5203                         mask = 1;
5204                         for (j = 0; j < 32; j++) {
5205                                 if (vfta & mask)
5206                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5207                                                        on, false);
5208                                 mask <<= 1;
5209                         }
5210                 }
5211         }
5212
5213 }
5214
5215 static int
5216 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5217 {
5218         struct ixgbe_hw *hw =
5219                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5220         struct ixgbe_vfta *shadow_vfta =
5221                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5222         uint32_t vid_idx = 0;
5223         uint32_t vid_bit = 0;
5224         int ret = 0;
5225
5226         PMD_INIT_FUNC_TRACE();
5227
5228         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5229         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5230         if (ret) {
5231                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5232                 return ret;
5233         }
5234         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5235         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5236
5237         /* Save what we set and retore it after device reset */
5238         if (on)
5239                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5240         else
5241                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5242
5243         return 0;
5244 }
5245
5246 static void
5247 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5248 {
5249         struct ixgbe_hw *hw =
5250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         uint32_t ctrl;
5252
5253         PMD_INIT_FUNC_TRACE();
5254
5255         if (queue >= hw->mac.max_rx_queues)
5256                 return;
5257
5258         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5259         if (on)
5260                 ctrl |= IXGBE_RXDCTL_VME;
5261         else
5262                 ctrl &= ~IXGBE_RXDCTL_VME;
5263         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5264
5265         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5266 }
5267
5268 static int
5269 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5270 {
5271         struct ixgbe_rx_queue *rxq;
5272         uint16_t i;
5273         int on = 0;
5274
5275         /* VF function only support hw strip feature, others are not support */
5276         if (mask & ETH_VLAN_STRIP_MASK) {
5277                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5278                         rxq = dev->data->rx_queues[i];
5279                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5280                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5281                 }
5282         }
5283
5284         return 0;
5285 }
5286
5287 static int
5288 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5289 {
5290         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5291
5292         ixgbevf_vlan_offload_config(dev, mask);
5293
5294         return 0;
5295 }
5296
5297 int
5298 ixgbe_vt_check(struct ixgbe_hw *hw)
5299 {
5300         uint32_t reg_val;
5301
5302         /* if Virtualization Technology is enabled */
5303         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5304         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5305                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5306                 return -1;
5307         }
5308
5309         return 0;
5310 }
5311
5312 static uint32_t
5313 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5314 {
5315         uint32_t vector = 0;
5316
5317         switch (hw->mac.mc_filter_type) {
5318         case 0:   /* use bits [47:36] of the address */
5319                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5320                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5321                 break;
5322         case 1:   /* use bits [46:35] of the address */
5323                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5324                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5325                 break;
5326         case 2:   /* use bits [45:34] of the address */
5327                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5328                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5329                 break;
5330         case 3:   /* use bits [43:32] of the address */
5331                 vector = ((uc_addr->addr_bytes[4]) |
5332                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5333                 break;
5334         default:  /* Invalid mc_filter_type */
5335                 break;
5336         }
5337
5338         /* vector can only be 12-bits or boundary will be exceeded */
5339         vector &= 0xFFF;
5340         return vector;
5341 }
5342
5343 static int
5344 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5345                         uint8_t on)
5346 {
5347         uint32_t vector;
5348         uint32_t uta_idx;
5349         uint32_t reg_val;
5350         uint32_t uta_shift;
5351         uint32_t rc;
5352         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5353         const uint32_t ixgbe_uta_bit_shift = 5;
5354         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5355         const uint32_t bit1 = 0x1;
5356
5357         struct ixgbe_hw *hw =
5358                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5359         struct ixgbe_uta_info *uta_info =
5360                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5361
5362         /* The UTA table only exists on 82599 hardware and newer */
5363         if (hw->mac.type < ixgbe_mac_82599EB)
5364                 return -ENOTSUP;
5365
5366         vector = ixgbe_uta_vector(hw, mac_addr);
5367         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5368         uta_shift = vector & ixgbe_uta_bit_mask;
5369
5370         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5371         if (rc == on)
5372                 return 0;
5373
5374         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5375         if (on) {
5376                 uta_info->uta_in_use++;
5377                 reg_val |= (bit1 << uta_shift);
5378                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5379         } else {
5380                 uta_info->uta_in_use--;
5381                 reg_val &= ~(bit1 << uta_shift);
5382                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5383         }
5384
5385         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5386
5387         if (uta_info->uta_in_use > 0)
5388                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5389                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5390         else
5391                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5392
5393         return 0;
5394 }
5395
5396 static int
5397 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5398 {
5399         int i;
5400         struct ixgbe_hw *hw =
5401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5402         struct ixgbe_uta_info *uta_info =
5403                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5404
5405         /* The UTA table only exists on 82599 hardware and newer */
5406         if (hw->mac.type < ixgbe_mac_82599EB)
5407                 return -ENOTSUP;
5408
5409         if (on) {
5410                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5411                         uta_info->uta_shadow[i] = ~0;
5412                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5413                 }
5414         } else {
5415                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5416                         uta_info->uta_shadow[i] = 0;
5417                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5418                 }
5419         }
5420         return 0;
5421
5422 }
5423
5424 uint32_t
5425 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5426 {
5427         uint32_t new_val = orig_val;
5428
5429         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5430                 new_val |= IXGBE_VMOLR_AUPE;
5431         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5432                 new_val |= IXGBE_VMOLR_ROMPE;
5433         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5434                 new_val |= IXGBE_VMOLR_ROPE;
5435         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5436                 new_val |= IXGBE_VMOLR_BAM;
5437         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5438                 new_val |= IXGBE_VMOLR_MPE;
5439
5440         return new_val;
5441 }
5442
5443 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5444 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5445 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5446 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5447 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5448         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5449         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5450
5451 static int
5452 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5453                       struct rte_eth_mirror_conf *mirror_conf,
5454                       uint8_t rule_id, uint8_t on)
5455 {
5456         uint32_t mr_ctl, vlvf;
5457         uint32_t mp_lsb = 0;
5458         uint32_t mv_msb = 0;
5459         uint32_t mv_lsb = 0;
5460         uint32_t mp_msb = 0;
5461         uint8_t i = 0;
5462         int reg_index = 0;
5463         uint64_t vlan_mask = 0;
5464
5465         const uint8_t pool_mask_offset = 32;
5466         const uint8_t vlan_mask_offset = 32;
5467         const uint8_t dst_pool_offset = 8;
5468         const uint8_t rule_mr_offset  = 4;
5469         const uint8_t mirror_rule_mask = 0x0F;
5470
5471         struct ixgbe_mirror_info *mr_info =
5472                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5473         struct ixgbe_hw *hw =
5474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475         uint8_t mirror_type = 0;
5476
5477         if (ixgbe_vt_check(hw) < 0)
5478                 return -ENOTSUP;
5479
5480         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5481                 return -EINVAL;
5482
5483         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5484                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5485                             mirror_conf->rule_type);
5486                 return -EINVAL;
5487         }
5488
5489         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5490                 mirror_type |= IXGBE_MRCTL_VLME;
5491                 /* Check if vlan id is valid and find conresponding VLAN ID
5492                  * index in VLVF
5493                  */
5494                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5495                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5496                                 /* search vlan id related pool vlan filter
5497                                  * index
5498                                  */
5499                                 reg_index = ixgbe_find_vlvf_slot(
5500                                                 hw,
5501                                                 mirror_conf->vlan.vlan_id[i],
5502                                                 false);
5503                                 if (reg_index < 0)
5504                                         return -EINVAL;
5505                                 vlvf = IXGBE_READ_REG(hw,
5506                                                       IXGBE_VLVF(reg_index));
5507                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5508                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5509                                       mirror_conf->vlan.vlan_id[i]))
5510                                         vlan_mask |= (1ULL << reg_index);
5511                                 else
5512                                         return -EINVAL;
5513                         }
5514                 }
5515
5516                 if (on) {
5517                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5518                         mv_msb = vlan_mask >> vlan_mask_offset;
5519
5520                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5521                                                 mirror_conf->vlan.vlan_mask;
5522                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5523                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5524                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5525                                                 mirror_conf->vlan.vlan_id[i];
5526                         }
5527                 } else {
5528                         mv_lsb = 0;
5529                         mv_msb = 0;
5530                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5531                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5532                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5533                 }
5534         }
5535
5536         /**
5537          * if enable pool mirror, write related pool mask register,if disable
5538          * pool mirror, clear PFMRVM register
5539          */
5540         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5541                 mirror_type |= IXGBE_MRCTL_VPME;
5542                 if (on) {
5543                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5544                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5545                         mr_info->mr_conf[rule_id].pool_mask =
5546                                         mirror_conf->pool_mask;
5547
5548                 } else {
5549                         mp_lsb = 0;
5550                         mp_msb = 0;
5551                         mr_info->mr_conf[rule_id].pool_mask = 0;
5552                 }
5553         }
5554         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5555                 mirror_type |= IXGBE_MRCTL_UPME;
5556         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5557                 mirror_type |= IXGBE_MRCTL_DPME;
5558
5559         /* read  mirror control register and recalculate it */
5560         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5561
5562         if (on) {
5563                 mr_ctl |= mirror_type;
5564                 mr_ctl &= mirror_rule_mask;
5565                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5566         } else {
5567                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5568         }
5569
5570         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5571         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5572
5573         /* write mirrror control  register */
5574         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5575
5576         /* write pool mirrror control  register */
5577         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5578                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5579                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5580                                 mp_msb);
5581         }
5582         /* write VLAN mirrror control  register */
5583         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5584                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5585                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5586                                 mv_msb);
5587         }
5588
5589         return 0;
5590 }
5591
5592 static int
5593 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5594 {
5595         int mr_ctl = 0;
5596         uint32_t lsb_val = 0;
5597         uint32_t msb_val = 0;
5598         const uint8_t rule_mr_offset = 4;
5599
5600         struct ixgbe_hw *hw =
5601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5602         struct ixgbe_mirror_info *mr_info =
5603                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5604
5605         if (ixgbe_vt_check(hw) < 0)
5606                 return -ENOTSUP;
5607
5608         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5609                 return -EINVAL;
5610
5611         memset(&mr_info->mr_conf[rule_id], 0,
5612                sizeof(struct rte_eth_mirror_conf));
5613
5614         /* clear PFVMCTL register */
5615         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5616
5617         /* clear pool mask register */
5618         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5619         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5620
5621         /* clear vlan mask register */
5622         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5623         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5624
5625         return 0;
5626 }
5627
5628 static int
5629 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5630 {
5631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5632         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5633         struct ixgbe_interrupt *intr =
5634                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5635         struct ixgbe_hw *hw =
5636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5637         uint32_t vec = IXGBE_MISC_VEC_ID;
5638
5639         if (rte_intr_allow_others(intr_handle))
5640                 vec = IXGBE_RX_VEC_START;
5641         intr->mask |= (1 << vec);
5642         RTE_SET_USED(queue_id);
5643         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5644
5645         rte_intr_enable(intr_handle);
5646
5647         return 0;
5648 }
5649
5650 static int
5651 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5652 {
5653         struct ixgbe_interrupt *intr =
5654                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5655         struct ixgbe_hw *hw =
5656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5658         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5659         uint32_t vec = IXGBE_MISC_VEC_ID;
5660
5661         if (rte_intr_allow_others(intr_handle))
5662                 vec = IXGBE_RX_VEC_START;
5663         intr->mask &= ~(1 << vec);
5664         RTE_SET_USED(queue_id);
5665         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5666
5667         return 0;
5668 }
5669
5670 static int
5671 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5672 {
5673         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5674         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5675         uint32_t mask;
5676         struct ixgbe_hw *hw =
5677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5678         struct ixgbe_interrupt *intr =
5679                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5680
5681         if (queue_id < 16) {
5682                 ixgbe_disable_intr(hw);
5683                 intr->mask |= (1 << queue_id);
5684                 ixgbe_enable_intr(dev);
5685         } else if (queue_id < 32) {
5686                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5687                 mask &= (1 << queue_id);
5688                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5689         } else if (queue_id < 64) {
5690                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5691                 mask &= (1 << (queue_id - 32));
5692                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5693         }
5694         rte_intr_enable(intr_handle);
5695
5696         return 0;
5697 }
5698
5699 static int
5700 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5701 {
5702         uint32_t mask;
5703         struct ixgbe_hw *hw =
5704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         struct ixgbe_interrupt *intr =
5706                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5707
5708         if (queue_id < 16) {
5709                 ixgbe_disable_intr(hw);
5710                 intr->mask &= ~(1 << queue_id);
5711                 ixgbe_enable_intr(dev);
5712         } else if (queue_id < 32) {
5713                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5714                 mask &= ~(1 << queue_id);
5715                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5716         } else if (queue_id < 64) {
5717                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5718                 mask &= ~(1 << (queue_id - 32));
5719                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5720         }
5721
5722         return 0;
5723 }
5724
5725 static void
5726 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5727                      uint8_t queue, uint8_t msix_vector)
5728 {
5729         uint32_t tmp, idx;
5730
5731         if (direction == -1) {
5732                 /* other causes */
5733                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5734                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5735                 tmp &= ~0xFF;
5736                 tmp |= msix_vector;
5737                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5738         } else {
5739                 /* rx or tx cause */
5740                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5741                 idx = ((16 * (queue & 1)) + (8 * direction));
5742                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5743                 tmp &= ~(0xFF << idx);
5744                 tmp |= (msix_vector << idx);
5745                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5746         }
5747 }
5748
5749 /**
5750  * set the IVAR registers, mapping interrupt causes to vectors
5751  * @param hw
5752  *  pointer to ixgbe_hw struct
5753  * @direction
5754  *  0 for Rx, 1 for Tx, -1 for other causes
5755  * @queue
5756  *  queue to map the corresponding interrupt to
5757  * @msix_vector
5758  *  the vector to map to the corresponding queue
5759  */
5760 static void
5761 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5762                    uint8_t queue, uint8_t msix_vector)
5763 {
5764         uint32_t tmp, idx;
5765
5766         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5767         if (hw->mac.type == ixgbe_mac_82598EB) {
5768                 if (direction == -1)
5769                         direction = 0;
5770                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5771                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5772                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5773                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5774                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5775         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5776                         (hw->mac.type == ixgbe_mac_X540) ||
5777                         (hw->mac.type == ixgbe_mac_X550)) {
5778                 if (direction == -1) {
5779                         /* other causes */
5780                         idx = ((queue & 1) * 8);
5781                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5782                         tmp &= ~(0xFF << idx);
5783                         tmp |= (msix_vector << idx);
5784                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5785                 } else {
5786                         /* rx or tx causes */
5787                         idx = ((16 * (queue & 1)) + (8 * direction));
5788                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5789                         tmp &= ~(0xFF << idx);
5790                         tmp |= (msix_vector << idx);
5791                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5792                 }
5793         }
5794 }
5795
5796 static void
5797 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5798 {
5799         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5800         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5801         struct ixgbe_hw *hw =
5802                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5803         uint32_t q_idx;
5804         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5805         uint32_t base = IXGBE_MISC_VEC_ID;
5806
5807         /* Configure VF other cause ivar */
5808         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5809
5810         /* won't configure msix register if no mapping is done
5811          * between intr vector and event fd.
5812          */
5813         if (!rte_intr_dp_is_en(intr_handle))
5814                 return;
5815
5816         if (rte_intr_allow_others(intr_handle)) {
5817                 base = IXGBE_RX_VEC_START;
5818                 vector_idx = IXGBE_RX_VEC_START;
5819         }
5820
5821         /* Configure all RX queues of VF */
5822         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5823                 /* Force all queue use vector 0,
5824                  * as IXGBE_VF_MAXMSIVECOTR = 1
5825                  */
5826                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5827                 intr_handle->intr_vec[q_idx] = vector_idx;
5828                 if (vector_idx < base + intr_handle->nb_efd - 1)
5829                         vector_idx++;
5830         }
5831
5832         /* As RX queue setting above show, all queues use the vector 0.
5833          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5834          */
5835         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5836                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5837                         | IXGBE_EITR_CNT_WDIS);
5838 }
5839
5840 /**
5841  * Sets up the hardware to properly generate MSI-X interrupts
5842  * @hw
5843  *  board private structure
5844  */
5845 static void
5846 ixgbe_configure_msix(struct rte_eth_dev *dev)
5847 {
5848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5849         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5850         struct ixgbe_hw *hw =
5851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5853         uint32_t vec = IXGBE_MISC_VEC_ID;
5854         uint32_t mask;
5855         uint32_t gpie;
5856
5857         /* won't configure msix register if no mapping is done
5858          * between intr vector and event fd
5859          * but if misx has been enabled already, need to configure
5860          * auto clean, auto mask and throttling.
5861          */
5862         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5863         if (!rte_intr_dp_is_en(intr_handle) &&
5864             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5865                 return;
5866
5867         if (rte_intr_allow_others(intr_handle))
5868                 vec = base = IXGBE_RX_VEC_START;
5869
5870         /* setup GPIE for MSI-x mode */
5871         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5872         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5873                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5874         /* auto clearing and auto setting corresponding bits in EIMS
5875          * when MSI-X interrupt is triggered
5876          */
5877         if (hw->mac.type == ixgbe_mac_82598EB) {
5878                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5879         } else {
5880                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5881                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5882         }
5883         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5884
5885         /* Populate the IVAR table and set the ITR values to the
5886          * corresponding register.
5887          */
5888         if (rte_intr_dp_is_en(intr_handle)) {
5889                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5890                         queue_id++) {
5891                         /* by default, 1:1 mapping */
5892                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5893                         intr_handle->intr_vec[queue_id] = vec;
5894                         if (vec < base + intr_handle->nb_efd - 1)
5895                                 vec++;
5896                 }
5897
5898                 switch (hw->mac.type) {
5899                 case ixgbe_mac_82598EB:
5900                         ixgbe_set_ivar_map(hw, -1,
5901                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5902                                            IXGBE_MISC_VEC_ID);
5903                         break;
5904                 case ixgbe_mac_82599EB:
5905                 case ixgbe_mac_X540:
5906                 case ixgbe_mac_X550:
5907                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5908                         break;
5909                 default:
5910                         break;
5911                 }
5912         }
5913         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5914                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5915                         | IXGBE_EITR_CNT_WDIS);
5916
5917         /* set up to autoclear timer, and the vectors */
5918         mask = IXGBE_EIMS_ENABLE_MASK;
5919         mask &= ~(IXGBE_EIMS_OTHER |
5920                   IXGBE_EIMS_MAILBOX |
5921                   IXGBE_EIMS_LSC);
5922
5923         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5924 }
5925
5926 int
5927 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5928                            uint16_t queue_idx, uint16_t tx_rate)
5929 {
5930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5931         struct rte_eth_rxmode *rxmode;
5932         uint32_t rf_dec, rf_int;
5933         uint32_t bcnrc_val;
5934         uint16_t link_speed = dev->data->dev_link.link_speed;
5935
5936         if (queue_idx >= hw->mac.max_tx_queues)
5937                 return -EINVAL;
5938
5939         if (tx_rate != 0) {
5940                 /* Calculate the rate factor values to set */
5941                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5942                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5943                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5944
5945                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5946                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5947                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5948                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5949         } else {
5950                 bcnrc_val = 0;
5951         }
5952
5953         rxmode = &dev->data->dev_conf.rxmode;
5954         /*
5955          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5956          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5957          * set as 0x4.
5958          */
5959         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5960             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5961                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5962                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5963         else
5964                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5965                         IXGBE_MMW_SIZE_DEFAULT);
5966
5967         /* Set RTTBCNRC of queue X */
5968         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5969         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5970         IXGBE_WRITE_FLUSH(hw);
5971
5972         return 0;
5973 }
5974
5975 static int
5976 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5977                      __attribute__((unused)) uint32_t index,
5978                      __attribute__((unused)) uint32_t pool)
5979 {
5980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981         int diag;
5982
5983         /*
5984          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5985          * operation. Trap this case to avoid exhausting the [very limited]
5986          * set of PF resources used to store VF MAC addresses.
5987          */
5988         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5989                 return -1;
5990         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5991         if (diag != 0)
5992                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5993                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5994                             mac_addr->addr_bytes[0],
5995                             mac_addr->addr_bytes[1],
5996                             mac_addr->addr_bytes[2],
5997                             mac_addr->addr_bytes[3],
5998                             mac_addr->addr_bytes[4],
5999                             mac_addr->addr_bytes[5],
6000                             diag);
6001         return diag;
6002 }
6003
6004 static void
6005 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6006 {
6007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6009         struct ether_addr *mac_addr;
6010         uint32_t i;
6011         int diag;
6012
6013         /*
6014          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6015          * not support the deletion of a given MAC address.
6016          * Instead, it imposes to delete all MAC addresses, then to add again
6017          * all MAC addresses with the exception of the one to be deleted.
6018          */
6019         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6020
6021         /*
6022          * Add again all MAC addresses, with the exception of the deleted one
6023          * and of the permanent MAC address.
6024          */
6025         for (i = 0, mac_addr = dev->data->mac_addrs;
6026              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6027                 /* Skip the deleted MAC address */
6028                 if (i == index)
6029                         continue;
6030                 /* Skip NULL MAC addresses */
6031                 if (is_zero_ether_addr(mac_addr))
6032                         continue;
6033                 /* Skip the permanent MAC address */
6034                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6035                         continue;
6036                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6037                 if (diag != 0)
6038                         PMD_DRV_LOG(ERR,
6039                                     "Adding again MAC address "
6040                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6041                                     "diag=%d",
6042                                     mac_addr->addr_bytes[0],
6043                                     mac_addr->addr_bytes[1],
6044                                     mac_addr->addr_bytes[2],
6045                                     mac_addr->addr_bytes[3],
6046                                     mac_addr->addr_bytes[4],
6047                                     mac_addr->addr_bytes[5],
6048                                     diag);
6049         }
6050 }
6051
6052 static int
6053 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6054 {
6055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6056
6057         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6058
6059         return 0;
6060 }
6061
6062 int
6063 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6064                         struct rte_eth_syn_filter *filter,
6065                         bool add)
6066 {
6067         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068         struct ixgbe_filter_info *filter_info =
6069                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6070         uint32_t syn_info;
6071         uint32_t synqf;
6072
6073         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6074                 return -EINVAL;
6075
6076         syn_info = filter_info->syn_info;
6077
6078         if (add) {
6079                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6080                         return -EINVAL;
6081                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6082                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6083
6084                 if (filter->hig_pri)
6085                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6086                 else
6087                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6088         } else {
6089                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6090                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6091                         return -ENOENT;
6092                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6093         }
6094
6095         filter_info->syn_info = synqf;
6096         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6097         IXGBE_WRITE_FLUSH(hw);
6098         return 0;
6099 }
6100
6101 static int
6102 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6103                         struct rte_eth_syn_filter *filter)
6104 {
6105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6107
6108         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6109                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6110                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6111                 return 0;
6112         }
6113         return -ENOENT;
6114 }
6115
6116 static int
6117 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6118                         enum rte_filter_op filter_op,
6119                         void *arg)
6120 {
6121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6122         int ret;
6123
6124         MAC_TYPE_FILTER_SUP(hw->mac.type);
6125
6126         if (filter_op == RTE_ETH_FILTER_NOP)
6127                 return 0;
6128
6129         if (arg == NULL) {
6130                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6131                             filter_op);
6132                 return -EINVAL;
6133         }
6134
6135         switch (filter_op) {
6136         case RTE_ETH_FILTER_ADD:
6137                 ret = ixgbe_syn_filter_set(dev,
6138                                 (struct rte_eth_syn_filter *)arg,
6139                                 TRUE);
6140                 break;
6141         case RTE_ETH_FILTER_DELETE:
6142                 ret = ixgbe_syn_filter_set(dev,
6143                                 (struct rte_eth_syn_filter *)arg,
6144                                 FALSE);
6145                 break;
6146         case RTE_ETH_FILTER_GET:
6147                 ret = ixgbe_syn_filter_get(dev,
6148                                 (struct rte_eth_syn_filter *)arg);
6149                 break;
6150         default:
6151                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6152                 ret = -EINVAL;
6153                 break;
6154         }
6155
6156         return ret;
6157 }
6158
6159
6160 static inline enum ixgbe_5tuple_protocol
6161 convert_protocol_type(uint8_t protocol_value)
6162 {
6163         if (protocol_value == IPPROTO_TCP)
6164                 return IXGBE_FILTER_PROTOCOL_TCP;
6165         else if (protocol_value == IPPROTO_UDP)
6166                 return IXGBE_FILTER_PROTOCOL_UDP;
6167         else if (protocol_value == IPPROTO_SCTP)
6168                 return IXGBE_FILTER_PROTOCOL_SCTP;
6169         else
6170                 return IXGBE_FILTER_PROTOCOL_NONE;
6171 }
6172
6173 /* inject a 5-tuple filter to HW */
6174 static inline void
6175 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6176                            struct ixgbe_5tuple_filter *filter)
6177 {
6178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6179         int i;
6180         uint32_t ftqf, sdpqf;
6181         uint32_t l34timir = 0;
6182         uint8_t mask = 0xff;
6183
6184         i = filter->index;
6185
6186         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6187                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6188         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6189
6190         ftqf = (uint32_t)(filter->filter_info.proto &
6191                 IXGBE_FTQF_PROTOCOL_MASK);
6192         ftqf |= (uint32_t)((filter->filter_info.priority &
6193                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6194         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6195                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6196         if (filter->filter_info.dst_ip_mask == 0)
6197                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6198         if (filter->filter_info.src_port_mask == 0)
6199                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6200         if (filter->filter_info.dst_port_mask == 0)
6201                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6202         if (filter->filter_info.proto_mask == 0)
6203                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6204         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6205         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6206         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6207
6208         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6209         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6210         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6211         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6212
6213         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6214         l34timir |= (uint32_t)(filter->queue <<
6215                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6216         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6217 }
6218
6219 /*
6220  * add a 5tuple filter
6221  *
6222  * @param
6223  * dev: Pointer to struct rte_eth_dev.
6224  * index: the index the filter allocates.
6225  * filter: ponter to the filter that will be added.
6226  * rx_queue: the queue id the filter assigned to.
6227  *
6228  * @return
6229  *    - On success, zero.
6230  *    - On failure, a negative value.
6231  */
6232 static int
6233 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6234                         struct ixgbe_5tuple_filter *filter)
6235 {
6236         struct ixgbe_filter_info *filter_info =
6237                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6238         int i, idx, shift;
6239
6240         /*
6241          * look for an unused 5tuple filter index,
6242          * and insert the filter to list.
6243          */
6244         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6245                 idx = i / (sizeof(uint32_t) * NBBY);
6246                 shift = i % (sizeof(uint32_t) * NBBY);
6247                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6248                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6249                         filter->index = i;
6250                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6251                                           filter,
6252                                           entries);
6253                         break;
6254                 }
6255         }
6256         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6257                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6258                 return -ENOSYS;
6259         }
6260
6261         ixgbe_inject_5tuple_filter(dev, filter);
6262
6263         return 0;
6264 }
6265
6266 /*
6267  * remove a 5tuple filter
6268  *
6269  * @param
6270  * dev: Pointer to struct rte_eth_dev.
6271  * filter: the pointer of the filter will be removed.
6272  */
6273 static void
6274 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6275                         struct ixgbe_5tuple_filter *filter)
6276 {
6277         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6278         struct ixgbe_filter_info *filter_info =
6279                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6280         uint16_t index = filter->index;
6281
6282         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6283                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6284         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6285         rte_free(filter);
6286
6287         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6288         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6289         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6290         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6291         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6292 }
6293
6294 static int
6295 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6296 {
6297         struct ixgbe_hw *hw;
6298         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6299         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6300
6301         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6302
6303         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6304                 return -EINVAL;
6305
6306         /* refuse mtu that requires the support of scattered packets when this
6307          * feature has not been enabled before.
6308          */
6309         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6310             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6311              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6312                 return -EINVAL;
6313
6314         /*
6315          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6316          * request of the version 2.0 of the mailbox API.
6317          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6318          * of the mailbox API.
6319          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6320          * prior to 3.11.33 which contains the following change:
6321          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6322          */
6323         ixgbevf_rlpml_set_vf(hw, max_frame);
6324
6325         /* update max frame size */
6326         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6327         return 0;
6328 }
6329
6330 static inline struct ixgbe_5tuple_filter *
6331 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6332                         struct ixgbe_5tuple_filter_info *key)
6333 {
6334         struct ixgbe_5tuple_filter *it;
6335
6336         TAILQ_FOREACH(it, filter_list, entries) {
6337                 if (memcmp(key, &it->filter_info,
6338                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6339                         return it;
6340                 }
6341         }
6342         return NULL;
6343 }
6344
6345 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6346 static inline int
6347 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6348                         struct ixgbe_5tuple_filter_info *filter_info)
6349 {
6350         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6351                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6352                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6353                 return -EINVAL;
6354
6355         switch (filter->dst_ip_mask) {
6356         case UINT32_MAX:
6357                 filter_info->dst_ip_mask = 0;
6358                 filter_info->dst_ip = filter->dst_ip;
6359                 break;
6360         case 0:
6361                 filter_info->dst_ip_mask = 1;
6362                 break;
6363         default:
6364                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6365                 return -EINVAL;
6366         }
6367
6368         switch (filter->src_ip_mask) {
6369         case UINT32_MAX:
6370                 filter_info->src_ip_mask = 0;
6371                 filter_info->src_ip = filter->src_ip;
6372                 break;
6373         case 0:
6374                 filter_info->src_ip_mask = 1;
6375                 break;
6376         default:
6377                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6378                 return -EINVAL;
6379         }
6380
6381         switch (filter->dst_port_mask) {
6382         case UINT16_MAX:
6383                 filter_info->dst_port_mask = 0;
6384                 filter_info->dst_port = filter->dst_port;
6385                 break;
6386         case 0:
6387                 filter_info->dst_port_mask = 1;
6388                 break;
6389         default:
6390                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6391                 return -EINVAL;
6392         }
6393
6394         switch (filter->src_port_mask) {
6395         case UINT16_MAX:
6396                 filter_info->src_port_mask = 0;
6397                 filter_info->src_port = filter->src_port;
6398                 break;
6399         case 0:
6400                 filter_info->src_port_mask = 1;
6401                 break;
6402         default:
6403                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6404                 return -EINVAL;
6405         }
6406
6407         switch (filter->proto_mask) {
6408         case UINT8_MAX:
6409                 filter_info->proto_mask = 0;
6410                 filter_info->proto =
6411                         convert_protocol_type(filter->proto);
6412                 break;
6413         case 0:
6414                 filter_info->proto_mask = 1;
6415                 break;
6416         default:
6417                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6418                 return -EINVAL;
6419         }
6420
6421         filter_info->priority = (uint8_t)filter->priority;
6422         return 0;
6423 }
6424
6425 /*
6426  * add or delete a ntuple filter
6427  *
6428  * @param
6429  * dev: Pointer to struct rte_eth_dev.
6430  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6431  * add: if true, add filter, if false, remove filter
6432  *
6433  * @return
6434  *    - On success, zero.
6435  *    - On failure, a negative value.
6436  */
6437 int
6438 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6439                         struct rte_eth_ntuple_filter *ntuple_filter,
6440                         bool add)
6441 {
6442         struct ixgbe_filter_info *filter_info =
6443                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6444         struct ixgbe_5tuple_filter_info filter_5tuple;
6445         struct ixgbe_5tuple_filter *filter;
6446         int ret;
6447
6448         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6449                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6450                 return -EINVAL;
6451         }
6452
6453         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6454         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6455         if (ret < 0)
6456                 return ret;
6457
6458         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6459                                          &filter_5tuple);
6460         if (filter != NULL && add) {
6461                 PMD_DRV_LOG(ERR, "filter exists.");
6462                 return -EEXIST;
6463         }
6464         if (filter == NULL && !add) {
6465                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6466                 return -ENOENT;
6467         }
6468
6469         if (add) {
6470                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6471                                 sizeof(struct ixgbe_5tuple_filter), 0);
6472                 if (filter == NULL)
6473                         return -ENOMEM;
6474                 rte_memcpy(&filter->filter_info,
6475                                  &filter_5tuple,
6476                                  sizeof(struct ixgbe_5tuple_filter_info));
6477                 filter->queue = ntuple_filter->queue;
6478                 ret = ixgbe_add_5tuple_filter(dev, filter);
6479                 if (ret < 0) {
6480                         rte_free(filter);
6481                         return ret;
6482                 }
6483         } else
6484                 ixgbe_remove_5tuple_filter(dev, filter);
6485
6486         return 0;
6487 }
6488
6489 /*
6490  * get a ntuple filter
6491  *
6492  * @param
6493  * dev: Pointer to struct rte_eth_dev.
6494  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6495  *
6496  * @return
6497  *    - On success, zero.
6498  *    - On failure, a negative value.
6499  */
6500 static int
6501 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6502                         struct rte_eth_ntuple_filter *ntuple_filter)
6503 {
6504         struct ixgbe_filter_info *filter_info =
6505                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6506         struct ixgbe_5tuple_filter_info filter_5tuple;
6507         struct ixgbe_5tuple_filter *filter;
6508         int ret;
6509
6510         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6511                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6512                 return -EINVAL;
6513         }
6514
6515         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6516         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6517         if (ret < 0)
6518                 return ret;
6519
6520         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6521                                          &filter_5tuple);
6522         if (filter == NULL) {
6523                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6524                 return -ENOENT;
6525         }
6526         ntuple_filter->queue = filter->queue;
6527         return 0;
6528 }
6529
6530 /*
6531  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6532  * @dev: pointer to rte_eth_dev structure
6533  * @filter_op:operation will be taken.
6534  * @arg: a pointer to specific structure corresponding to the filter_op
6535  *
6536  * @return
6537  *    - On success, zero.
6538  *    - On failure, a negative value.
6539  */
6540 static int
6541 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6542                                 enum rte_filter_op filter_op,
6543                                 void *arg)
6544 {
6545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546         int ret;
6547
6548         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6549
6550         if (filter_op == RTE_ETH_FILTER_NOP)
6551                 return 0;
6552
6553         if (arg == NULL) {
6554                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6555                             filter_op);
6556                 return -EINVAL;
6557         }
6558
6559         switch (filter_op) {
6560         case RTE_ETH_FILTER_ADD:
6561                 ret = ixgbe_add_del_ntuple_filter(dev,
6562                         (struct rte_eth_ntuple_filter *)arg,
6563                         TRUE);
6564                 break;
6565         case RTE_ETH_FILTER_DELETE:
6566                 ret = ixgbe_add_del_ntuple_filter(dev,
6567                         (struct rte_eth_ntuple_filter *)arg,
6568                         FALSE);
6569                 break;
6570         case RTE_ETH_FILTER_GET:
6571                 ret = ixgbe_get_ntuple_filter(dev,
6572                         (struct rte_eth_ntuple_filter *)arg);
6573                 break;
6574         default:
6575                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6576                 ret = -EINVAL;
6577                 break;
6578         }
6579         return ret;
6580 }
6581
6582 int
6583 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6584                         struct rte_eth_ethertype_filter *filter,
6585                         bool add)
6586 {
6587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588         struct ixgbe_filter_info *filter_info =
6589                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6590         uint32_t etqf = 0;
6591         uint32_t etqs = 0;
6592         int ret;
6593         struct ixgbe_ethertype_filter ethertype_filter;
6594
6595         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6596                 return -EINVAL;
6597
6598         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6599                 filter->ether_type == ETHER_TYPE_IPv6) {
6600                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6601                         " ethertype filter.", filter->ether_type);
6602                 return -EINVAL;
6603         }
6604
6605         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6606                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6607                 return -EINVAL;
6608         }
6609         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6610                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6611                 return -EINVAL;
6612         }
6613
6614         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6615         if (ret >= 0 && add) {
6616                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6617                             filter->ether_type);
6618                 return -EEXIST;
6619         }
6620         if (ret < 0 && !add) {
6621                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6622                             filter->ether_type);
6623                 return -ENOENT;
6624         }
6625
6626         if (add) {
6627                 etqf = IXGBE_ETQF_FILTER_EN;
6628                 etqf |= (uint32_t)filter->ether_type;
6629                 etqs |= (uint32_t)((filter->queue <<
6630                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6631                                     IXGBE_ETQS_RX_QUEUE);
6632                 etqs |= IXGBE_ETQS_QUEUE_EN;
6633
6634                 ethertype_filter.ethertype = filter->ether_type;
6635                 ethertype_filter.etqf = etqf;
6636                 ethertype_filter.etqs = etqs;
6637                 ethertype_filter.conf = FALSE;
6638                 ret = ixgbe_ethertype_filter_insert(filter_info,
6639                                                     &ethertype_filter);
6640                 if (ret < 0) {
6641                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6642                         return -ENOSPC;
6643                 }
6644         } else {
6645                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6646                 if (ret < 0)
6647                         return -ENOSYS;
6648         }
6649         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6650         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6651         IXGBE_WRITE_FLUSH(hw);
6652
6653         return 0;
6654 }
6655
6656 static int
6657 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6658                         struct rte_eth_ethertype_filter *filter)
6659 {
6660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         struct ixgbe_filter_info *filter_info =
6662                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6663         uint32_t etqf, etqs;
6664         int ret;
6665
6666         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6667         if (ret < 0) {
6668                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6669                             filter->ether_type);
6670                 return -ENOENT;
6671         }
6672
6673         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6674         if (etqf & IXGBE_ETQF_FILTER_EN) {
6675                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6676                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6677                 filter->flags = 0;
6678                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6679                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6680                 return 0;
6681         }
6682         return -ENOENT;
6683 }
6684
6685 /*
6686  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6687  * @dev: pointer to rte_eth_dev structure
6688  * @filter_op:operation will be taken.
6689  * @arg: a pointer to specific structure corresponding to the filter_op
6690  */
6691 static int
6692 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6693                                 enum rte_filter_op filter_op,
6694                                 void *arg)
6695 {
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         int ret;
6698
6699         MAC_TYPE_FILTER_SUP(hw->mac.type);
6700
6701         if (filter_op == RTE_ETH_FILTER_NOP)
6702                 return 0;
6703
6704         if (arg == NULL) {
6705                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6706                             filter_op);
6707                 return -EINVAL;
6708         }
6709
6710         switch (filter_op) {
6711         case RTE_ETH_FILTER_ADD:
6712                 ret = ixgbe_add_del_ethertype_filter(dev,
6713                         (struct rte_eth_ethertype_filter *)arg,
6714                         TRUE);
6715                 break;
6716         case RTE_ETH_FILTER_DELETE:
6717                 ret = ixgbe_add_del_ethertype_filter(dev,
6718                         (struct rte_eth_ethertype_filter *)arg,
6719                         FALSE);
6720                 break;
6721         case RTE_ETH_FILTER_GET:
6722                 ret = ixgbe_get_ethertype_filter(dev,
6723                         (struct rte_eth_ethertype_filter *)arg);
6724                 break;
6725         default:
6726                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6727                 ret = -EINVAL;
6728                 break;
6729         }
6730         return ret;
6731 }
6732
6733 static int
6734 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6735                      enum rte_filter_type filter_type,
6736                      enum rte_filter_op filter_op,
6737                      void *arg)
6738 {
6739         int ret = 0;
6740
6741         switch (filter_type) {
6742         case RTE_ETH_FILTER_NTUPLE:
6743                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6744                 break;
6745         case RTE_ETH_FILTER_ETHERTYPE:
6746                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6747                 break;
6748         case RTE_ETH_FILTER_SYN:
6749                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6750                 break;
6751         case RTE_ETH_FILTER_FDIR:
6752                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6753                 break;
6754         case RTE_ETH_FILTER_L2_TUNNEL:
6755                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6756                 break;
6757         case RTE_ETH_FILTER_GENERIC:
6758                 if (filter_op != RTE_ETH_FILTER_GET)
6759                         return -EINVAL;
6760                 *(const void **)arg = &ixgbe_flow_ops;
6761                 break;
6762         default:
6763                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6764                                                         filter_type);
6765                 ret = -EINVAL;
6766                 break;
6767         }
6768
6769         return ret;
6770 }
6771
6772 static u8 *
6773 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6774                         u8 **mc_addr_ptr, u32 *vmdq)
6775 {
6776         u8 *mc_addr;
6777
6778         *vmdq = 0;
6779         mc_addr = *mc_addr_ptr;
6780         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6781         return mc_addr;
6782 }
6783
6784 static int
6785 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6786                           struct ether_addr *mc_addr_set,
6787                           uint32_t nb_mc_addr)
6788 {
6789         struct ixgbe_hw *hw;
6790         u8 *mc_addr_list;
6791
6792         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6793         mc_addr_list = (u8 *)mc_addr_set;
6794         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6795                                          ixgbe_dev_addr_list_itr, TRUE);
6796 }
6797
6798 static uint64_t
6799 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6800 {
6801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6802         uint64_t systime_cycles;
6803
6804         switch (hw->mac.type) {
6805         case ixgbe_mac_X550:
6806         case ixgbe_mac_X550EM_x:
6807         case ixgbe_mac_X550EM_a:
6808                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6809                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6810                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6811                                 * NSEC_PER_SEC;
6812                 break;
6813         default:
6814                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6815                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6816                                 << 32;
6817         }
6818
6819         return systime_cycles;
6820 }
6821
6822 static uint64_t
6823 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6824 {
6825         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6826         uint64_t rx_tstamp_cycles;
6827
6828         switch (hw->mac.type) {
6829         case ixgbe_mac_X550:
6830         case ixgbe_mac_X550EM_x:
6831         case ixgbe_mac_X550EM_a:
6832                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6833                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6834                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6835                                 * NSEC_PER_SEC;
6836                 break;
6837         default:
6838                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6839                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6840                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6841                                 << 32;
6842         }
6843
6844         return rx_tstamp_cycles;
6845 }
6846
6847 static uint64_t
6848 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6849 {
6850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6851         uint64_t tx_tstamp_cycles;
6852
6853         switch (hw->mac.type) {
6854         case ixgbe_mac_X550:
6855         case ixgbe_mac_X550EM_x:
6856         case ixgbe_mac_X550EM_a:
6857                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6858                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6859                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6860                                 * NSEC_PER_SEC;
6861                 break;
6862         default:
6863                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6864                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6865                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6866                                 << 32;
6867         }
6868
6869         return tx_tstamp_cycles;
6870 }
6871
6872 static void
6873 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6874 {
6875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6876         struct ixgbe_adapter *adapter =
6877                 (struct ixgbe_adapter *)dev->data->dev_private;
6878         struct rte_eth_link link;
6879         uint32_t incval = 0;
6880         uint32_t shift = 0;
6881
6882         /* Get current link speed. */
6883         ixgbe_dev_link_update(dev, 1);
6884         rte_eth_linkstatus_get(dev, &link);
6885
6886         switch (link.link_speed) {
6887         case ETH_SPEED_NUM_100M:
6888                 incval = IXGBE_INCVAL_100;
6889                 shift = IXGBE_INCVAL_SHIFT_100;
6890                 break;
6891         case ETH_SPEED_NUM_1G:
6892                 incval = IXGBE_INCVAL_1GB;
6893                 shift = IXGBE_INCVAL_SHIFT_1GB;
6894                 break;
6895         case ETH_SPEED_NUM_10G:
6896         default:
6897                 incval = IXGBE_INCVAL_10GB;
6898                 shift = IXGBE_INCVAL_SHIFT_10GB;
6899                 break;
6900         }
6901
6902         switch (hw->mac.type) {
6903         case ixgbe_mac_X550:
6904         case ixgbe_mac_X550EM_x:
6905         case ixgbe_mac_X550EM_a:
6906                 /* Independent of link speed. */
6907                 incval = 1;
6908                 /* Cycles read will be interpreted as ns. */
6909                 shift = 0;
6910                 /* Fall-through */
6911         case ixgbe_mac_X540:
6912                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6913                 break;
6914         case ixgbe_mac_82599EB:
6915                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6916                 shift -= IXGBE_INCVAL_SHIFT_82599;
6917                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6918                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6919                 break;
6920         default:
6921                 /* Not supported. */
6922                 return;
6923         }
6924
6925         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6926         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6927         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6928
6929         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6930         adapter->systime_tc.cc_shift = shift;
6931         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6932
6933         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6934         adapter->rx_tstamp_tc.cc_shift = shift;
6935         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6936
6937         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6938         adapter->tx_tstamp_tc.cc_shift = shift;
6939         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6940 }
6941
6942 static int
6943 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6944 {
6945         struct ixgbe_adapter *adapter =
6946                         (struct ixgbe_adapter *)dev->data->dev_private;
6947
6948         adapter->systime_tc.nsec += delta;
6949         adapter->rx_tstamp_tc.nsec += delta;
6950         adapter->tx_tstamp_tc.nsec += delta;
6951
6952         return 0;
6953 }
6954
6955 static int
6956 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6957 {
6958         uint64_t ns;
6959         struct ixgbe_adapter *adapter =
6960                         (struct ixgbe_adapter *)dev->data->dev_private;
6961
6962         ns = rte_timespec_to_ns(ts);
6963         /* Set the timecounters to a new value. */
6964         adapter->systime_tc.nsec = ns;
6965         adapter->rx_tstamp_tc.nsec = ns;
6966         adapter->tx_tstamp_tc.nsec = ns;
6967
6968         return 0;
6969 }
6970
6971 static int
6972 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6973 {
6974         uint64_t ns, systime_cycles;
6975         struct ixgbe_adapter *adapter =
6976                         (struct ixgbe_adapter *)dev->data->dev_private;
6977
6978         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6979         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6980         *ts = rte_ns_to_timespec(ns);
6981
6982         return 0;
6983 }
6984
6985 static int
6986 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6987 {
6988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6989         uint32_t tsync_ctl;
6990         uint32_t tsauxc;
6991
6992         /* Stop the timesync system time. */
6993         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6994         /* Reset the timesync system time value. */
6995         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6996         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6997
6998         /* Enable system time for platforms where it isn't on by default. */
6999         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7000         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7001         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7002
7003         ixgbe_start_timecounters(dev);
7004
7005         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7006         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7007                         (ETHER_TYPE_1588 |
7008                          IXGBE_ETQF_FILTER_EN |
7009                          IXGBE_ETQF_1588));
7010
7011         /* Enable timestamping of received PTP packets. */
7012         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7013         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7014         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7015
7016         /* Enable timestamping of transmitted PTP packets. */
7017         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7018         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7019         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7020
7021         IXGBE_WRITE_FLUSH(hw);
7022
7023         return 0;
7024 }
7025
7026 static int
7027 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7028 {
7029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030         uint32_t tsync_ctl;
7031
7032         /* Disable timestamping of transmitted PTP packets. */
7033         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7034         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7035         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7036
7037         /* Disable timestamping of received PTP packets. */
7038         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7039         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7040         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7041
7042         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7043         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7044
7045         /* Stop incrementating the System Time registers. */
7046         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7047
7048         return 0;
7049 }
7050
7051 static int
7052 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7053                                  struct timespec *timestamp,
7054                                  uint32_t flags __rte_unused)
7055 {
7056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7057         struct ixgbe_adapter *adapter =
7058                 (struct ixgbe_adapter *)dev->data->dev_private;
7059         uint32_t tsync_rxctl;
7060         uint64_t rx_tstamp_cycles;
7061         uint64_t ns;
7062
7063         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7064         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7065                 return -EINVAL;
7066
7067         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7068         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7069         *timestamp = rte_ns_to_timespec(ns);
7070
7071         return  0;
7072 }
7073
7074 static int
7075 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7076                                  struct timespec *timestamp)
7077 {
7078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079         struct ixgbe_adapter *adapter =
7080                 (struct ixgbe_adapter *)dev->data->dev_private;
7081         uint32_t tsync_txctl;
7082         uint64_t tx_tstamp_cycles;
7083         uint64_t ns;
7084
7085         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7086         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7087                 return -EINVAL;
7088
7089         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7090         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7091         *timestamp = rte_ns_to_timespec(ns);
7092
7093         return 0;
7094 }
7095
7096 static int
7097 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7098 {
7099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7100         int count = 0;
7101         int g_ind = 0;
7102         const struct reg_info *reg_group;
7103         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7104                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7105
7106         while ((reg_group = reg_set[g_ind++]))
7107                 count += ixgbe_regs_group_count(reg_group);
7108
7109         return count;
7110 }
7111
7112 static int
7113 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7114 {
7115         int count = 0;
7116         int g_ind = 0;
7117         const struct reg_info *reg_group;
7118
7119         while ((reg_group = ixgbevf_regs[g_ind++]))
7120                 count += ixgbe_regs_group_count(reg_group);
7121
7122         return count;
7123 }
7124
7125 static int
7126 ixgbe_get_regs(struct rte_eth_dev *dev,
7127               struct rte_dev_reg_info *regs)
7128 {
7129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7130         uint32_t *data = regs->data;
7131         int g_ind = 0;
7132         int count = 0;
7133         const struct reg_info *reg_group;
7134         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7135                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7136
7137         if (data == NULL) {
7138                 regs->length = ixgbe_get_reg_length(dev);
7139                 regs->width = sizeof(uint32_t);
7140                 return 0;
7141         }
7142
7143         /* Support only full register dump */
7144         if ((regs->length == 0) ||
7145             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7146                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7147                         hw->device_id;
7148                 while ((reg_group = reg_set[g_ind++]))
7149                         count += ixgbe_read_regs_group(dev, &data[count],
7150                                 reg_group);
7151                 return 0;
7152         }
7153
7154         return -ENOTSUP;
7155 }
7156
7157 static int
7158 ixgbevf_get_regs(struct rte_eth_dev *dev,
7159                 struct rte_dev_reg_info *regs)
7160 {
7161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7162         uint32_t *data = regs->data;
7163         int g_ind = 0;
7164         int count = 0;
7165         const struct reg_info *reg_group;
7166
7167         if (data == NULL) {
7168                 regs->length = ixgbevf_get_reg_length(dev);
7169                 regs->width = sizeof(uint32_t);
7170                 return 0;
7171         }
7172
7173         /* Support only full register dump */
7174         if ((regs->length == 0) ||
7175             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7176                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7177                         hw->device_id;
7178                 while ((reg_group = ixgbevf_regs[g_ind++]))
7179                         count += ixgbe_read_regs_group(dev, &data[count],
7180                                                       reg_group);
7181                 return 0;
7182         }
7183
7184         return -ENOTSUP;
7185 }
7186
7187 static int
7188 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7189 {
7190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7191
7192         /* Return unit is byte count */
7193         return hw->eeprom.word_size * 2;
7194 }
7195
7196 static int
7197 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7198                 struct rte_dev_eeprom_info *in_eeprom)
7199 {
7200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7202         uint16_t *data = in_eeprom->data;
7203         int first, length;
7204
7205         first = in_eeprom->offset >> 1;
7206         length = in_eeprom->length >> 1;
7207         if ((first > hw->eeprom.word_size) ||
7208             ((first + length) > hw->eeprom.word_size))
7209                 return -EINVAL;
7210
7211         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7212
7213         return eeprom->ops.read_buffer(hw, first, length, data);
7214 }
7215
7216 static int
7217 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7218                 struct rte_dev_eeprom_info *in_eeprom)
7219 {
7220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7221         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7222         uint16_t *data = in_eeprom->data;
7223         int first, length;
7224
7225         first = in_eeprom->offset >> 1;
7226         length = in_eeprom->length >> 1;
7227         if ((first > hw->eeprom.word_size) ||
7228             ((first + length) > hw->eeprom.word_size))
7229                 return -EINVAL;
7230
7231         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7232
7233         return eeprom->ops.write_buffer(hw,  first, length, data);
7234 }
7235
7236 static int
7237 ixgbe_get_module_info(struct rte_eth_dev *dev,
7238                       struct rte_eth_dev_module_info *modinfo)
7239 {
7240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7241         uint32_t status;
7242         uint8_t sff8472_rev, addr_mode;
7243         bool page_swap = false;
7244
7245         /* Check whether we support SFF-8472 or not */
7246         status = hw->phy.ops.read_i2c_eeprom(hw,
7247                                              IXGBE_SFF_SFF_8472_COMP,
7248                                              &sff8472_rev);
7249         if (status != 0)
7250                 return -EIO;
7251
7252         /* addressing mode is not supported */
7253         status = hw->phy.ops.read_i2c_eeprom(hw,
7254                                              IXGBE_SFF_SFF_8472_SWAP,
7255                                              &addr_mode);
7256         if (status != 0)
7257                 return -EIO;
7258
7259         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7260                 PMD_DRV_LOG(ERR,
7261                             "Address change required to access page 0xA2, "
7262                             "but not supported. Please report the module "
7263                             "type to the driver maintainers.");
7264                 page_swap = true;
7265         }
7266
7267         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7268                 /* We have a SFP, but it does not support SFF-8472 */
7269                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7270                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7271         } else {
7272                 /* We have a SFP which supports a revision of SFF-8472. */
7273                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7274                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7275         }
7276
7277         return 0;
7278 }
7279
7280 static int
7281 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7282                         struct rte_dev_eeprom_info *info)
7283 {
7284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7285         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7286         uint8_t databyte = 0xFF;
7287         uint8_t *data = info->data;
7288         uint32_t i = 0;
7289
7290         if (info->length == 0)
7291                 return -EINVAL;
7292
7293         for (i = info->offset; i < info->offset + info->length; i++) {
7294                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7295                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7296                 else
7297                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7298
7299                 if (status != 0)
7300                         return -EIO;
7301
7302                 data[i - info->offset] = databyte;
7303         }
7304
7305         return 0;
7306 }
7307
7308 uint16_t
7309 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7310         switch (mac_type) {
7311         case ixgbe_mac_X550:
7312         case ixgbe_mac_X550EM_x:
7313         case ixgbe_mac_X550EM_a:
7314                 return ETH_RSS_RETA_SIZE_512;
7315         case ixgbe_mac_X550_vf:
7316         case ixgbe_mac_X550EM_x_vf:
7317         case ixgbe_mac_X550EM_a_vf:
7318                 return ETH_RSS_RETA_SIZE_64;
7319         default:
7320                 return ETH_RSS_RETA_SIZE_128;
7321         }
7322 }
7323
7324 uint32_t
7325 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7326         switch (mac_type) {
7327         case ixgbe_mac_X550:
7328         case ixgbe_mac_X550EM_x:
7329         case ixgbe_mac_X550EM_a:
7330                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7331                         return IXGBE_RETA(reta_idx >> 2);
7332                 else
7333                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7334         case ixgbe_mac_X550_vf:
7335         case ixgbe_mac_X550EM_x_vf:
7336         case ixgbe_mac_X550EM_a_vf:
7337                 return IXGBE_VFRETA(reta_idx >> 2);
7338         default:
7339                 return IXGBE_RETA(reta_idx >> 2);
7340         }
7341 }
7342
7343 uint32_t
7344 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7345         switch (mac_type) {
7346         case ixgbe_mac_X550_vf:
7347         case ixgbe_mac_X550EM_x_vf:
7348         case ixgbe_mac_X550EM_a_vf:
7349                 return IXGBE_VFMRQC;
7350         default:
7351                 return IXGBE_MRQC;
7352         }
7353 }
7354
7355 uint32_t
7356 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7357         switch (mac_type) {
7358         case ixgbe_mac_X550_vf:
7359         case ixgbe_mac_X550EM_x_vf:
7360         case ixgbe_mac_X550EM_a_vf:
7361                 return IXGBE_VFRSSRK(i);
7362         default:
7363                 return IXGBE_RSSRK(i);
7364         }
7365 }
7366
7367 bool
7368 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7369         switch (mac_type) {
7370         case ixgbe_mac_82599_vf:
7371         case ixgbe_mac_X540_vf:
7372                 return 0;
7373         default:
7374                 return 1;
7375         }
7376 }
7377
7378 static int
7379 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7380                         struct rte_eth_dcb_info *dcb_info)
7381 {
7382         struct ixgbe_dcb_config *dcb_config =
7383                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7384         struct ixgbe_dcb_tc_config *tc;
7385         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7386         uint8_t nb_tcs;
7387         uint8_t i, j;
7388
7389         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7390                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7391         else
7392                 dcb_info->nb_tcs = 1;
7393
7394         tc_queue = &dcb_info->tc_queue;
7395         nb_tcs = dcb_info->nb_tcs;
7396
7397         if (dcb_config->vt_mode) { /* vt is enabled*/
7398                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7399                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7400                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7401                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7402                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7403                         for (j = 0; j < nb_tcs; j++) {
7404                                 tc_queue->tc_rxq[0][j].base = j;
7405                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7406                                 tc_queue->tc_txq[0][j].base = j;
7407                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7408                         }
7409                 } else {
7410                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7411                                 for (j = 0; j < nb_tcs; j++) {
7412                                         tc_queue->tc_rxq[i][j].base =
7413                                                 i * nb_tcs + j;
7414                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7415                                         tc_queue->tc_txq[i][j].base =
7416                                                 i * nb_tcs + j;
7417                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7418                                 }
7419                         }
7420                 }
7421         } else { /* vt is disabled*/
7422                 struct rte_eth_dcb_rx_conf *rx_conf =
7423                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7424                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7425                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7426                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7427                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7428                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7429                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7430                         }
7431                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7432                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7433                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7434                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7435                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7436                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7437                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7438                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7439                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7440                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7441                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7442                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7443                         }
7444                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7445                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7446                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7447                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7448                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7449                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7450                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7451                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7452                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7453                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7454                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7455                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7456                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7457                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7458                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7459                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7460                 }
7461         }
7462         for (i = 0; i < dcb_info->nb_tcs; i++) {
7463                 tc = &dcb_config->tc_config[i];
7464                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7465         }
7466         return 0;
7467 }
7468
7469 /* Update e-tag ether type */
7470 static int
7471 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7472                             uint16_t ether_type)
7473 {
7474         uint32_t etag_etype;
7475
7476         if (hw->mac.type != ixgbe_mac_X550 &&
7477             hw->mac.type != ixgbe_mac_X550EM_x &&
7478             hw->mac.type != ixgbe_mac_X550EM_a) {
7479                 return -ENOTSUP;
7480         }
7481
7482         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7483         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7484         etag_etype |= ether_type;
7485         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7486         IXGBE_WRITE_FLUSH(hw);
7487
7488         return 0;
7489 }
7490
7491 /* Config l2 tunnel ether type */
7492 static int
7493 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7494                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7495 {
7496         int ret = 0;
7497         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7498         struct ixgbe_l2_tn_info *l2_tn_info =
7499                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7500
7501         if (l2_tunnel == NULL)
7502                 return -EINVAL;
7503
7504         switch (l2_tunnel->l2_tunnel_type) {
7505         case RTE_L2_TUNNEL_TYPE_E_TAG:
7506                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7507                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7508                 break;
7509         default:
7510                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7511                 ret = -EINVAL;
7512                 break;
7513         }
7514
7515         return ret;
7516 }
7517
7518 /* Enable e-tag tunnel */
7519 static int
7520 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7521 {
7522         uint32_t etag_etype;
7523
7524         if (hw->mac.type != ixgbe_mac_X550 &&
7525             hw->mac.type != ixgbe_mac_X550EM_x &&
7526             hw->mac.type != ixgbe_mac_X550EM_a) {
7527                 return -ENOTSUP;
7528         }
7529
7530         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7531         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7532         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7533         IXGBE_WRITE_FLUSH(hw);
7534
7535         return 0;
7536 }
7537
7538 /* Enable l2 tunnel */
7539 static int
7540 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7541                            enum rte_eth_tunnel_type l2_tunnel_type)
7542 {
7543         int ret = 0;
7544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7545         struct ixgbe_l2_tn_info *l2_tn_info =
7546                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7547
7548         switch (l2_tunnel_type) {
7549         case RTE_L2_TUNNEL_TYPE_E_TAG:
7550                 l2_tn_info->e_tag_en = TRUE;
7551                 ret = ixgbe_e_tag_enable(hw);
7552                 break;
7553         default:
7554                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7555                 ret = -EINVAL;
7556                 break;
7557         }
7558
7559         return ret;
7560 }
7561
7562 /* Disable e-tag tunnel */
7563 static int
7564 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7565 {
7566         uint32_t etag_etype;
7567
7568         if (hw->mac.type != ixgbe_mac_X550 &&
7569             hw->mac.type != ixgbe_mac_X550EM_x &&
7570             hw->mac.type != ixgbe_mac_X550EM_a) {
7571                 return -ENOTSUP;
7572         }
7573
7574         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7575         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7576         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7577         IXGBE_WRITE_FLUSH(hw);
7578
7579         return 0;
7580 }
7581
7582 /* Disable l2 tunnel */
7583 static int
7584 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7585                             enum rte_eth_tunnel_type l2_tunnel_type)
7586 {
7587         int ret = 0;
7588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7589         struct ixgbe_l2_tn_info *l2_tn_info =
7590                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7591
7592         switch (l2_tunnel_type) {
7593         case RTE_L2_TUNNEL_TYPE_E_TAG:
7594                 l2_tn_info->e_tag_en = FALSE;
7595                 ret = ixgbe_e_tag_disable(hw);
7596                 break;
7597         default:
7598                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7599                 ret = -EINVAL;
7600                 break;
7601         }
7602
7603         return ret;
7604 }
7605
7606 static int
7607 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7608                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7609 {
7610         int ret = 0;
7611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7612         uint32_t i, rar_entries;
7613         uint32_t rar_low, rar_high;
7614
7615         if (hw->mac.type != ixgbe_mac_X550 &&
7616             hw->mac.type != ixgbe_mac_X550EM_x &&
7617             hw->mac.type != ixgbe_mac_X550EM_a) {
7618                 return -ENOTSUP;
7619         }
7620
7621         rar_entries = ixgbe_get_num_rx_addrs(hw);
7622
7623         for (i = 1; i < rar_entries; i++) {
7624                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7625                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7626                 if ((rar_high & IXGBE_RAH_AV) &&
7627                     (rar_high & IXGBE_RAH_ADTYPE) &&
7628                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7629                      l2_tunnel->tunnel_id)) {
7630                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7631                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7632
7633                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7634
7635                         return ret;
7636                 }
7637         }
7638
7639         return ret;
7640 }
7641
7642 static int
7643 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7644                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7645 {
7646         int ret = 0;
7647         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7648         uint32_t i, rar_entries;
7649         uint32_t rar_low, rar_high;
7650
7651         if (hw->mac.type != ixgbe_mac_X550 &&
7652             hw->mac.type != ixgbe_mac_X550EM_x &&
7653             hw->mac.type != ixgbe_mac_X550EM_a) {
7654                 return -ENOTSUP;
7655         }
7656
7657         /* One entry for one tunnel. Try to remove potential existing entry. */
7658         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7659
7660         rar_entries = ixgbe_get_num_rx_addrs(hw);
7661
7662         for (i = 1; i < rar_entries; i++) {
7663                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7664                 if (rar_high & IXGBE_RAH_AV) {
7665                         continue;
7666                 } else {
7667                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7668                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7669                         rar_low = l2_tunnel->tunnel_id;
7670
7671                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7672                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7673
7674                         return ret;
7675                 }
7676         }
7677
7678         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7679                      " Please remove a rule before adding a new one.");
7680         return -EINVAL;
7681 }
7682
7683 static inline struct ixgbe_l2_tn_filter *
7684 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7685                           struct ixgbe_l2_tn_key *key)
7686 {
7687         int ret;
7688
7689         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7690         if (ret < 0)
7691                 return NULL;
7692
7693         return l2_tn_info->hash_map[ret];
7694 }
7695
7696 static inline int
7697 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7698                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7699 {
7700         int ret;
7701
7702         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7703                                &l2_tn_filter->key);
7704
7705         if (ret < 0) {
7706                 PMD_DRV_LOG(ERR,
7707                             "Failed to insert L2 tunnel filter"
7708                             " to hash table %d!",
7709                             ret);
7710                 return ret;
7711         }
7712
7713         l2_tn_info->hash_map[ret] = l2_tn_filter;
7714
7715         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7716
7717         return 0;
7718 }
7719
7720 static inline int
7721 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7722                           struct ixgbe_l2_tn_key *key)
7723 {
7724         int ret;
7725         struct ixgbe_l2_tn_filter *l2_tn_filter;
7726
7727         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7728
7729         if (ret < 0) {
7730                 PMD_DRV_LOG(ERR,
7731                             "No such L2 tunnel filter to delete %d!",
7732                             ret);
7733                 return ret;
7734         }
7735
7736         l2_tn_filter = l2_tn_info->hash_map[ret];
7737         l2_tn_info->hash_map[ret] = NULL;
7738
7739         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7740         rte_free(l2_tn_filter);
7741
7742         return 0;
7743 }
7744
7745 /* Add l2 tunnel filter */
7746 int
7747 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7748                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7749                                bool restore)
7750 {
7751         int ret;
7752         struct ixgbe_l2_tn_info *l2_tn_info =
7753                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7754         struct ixgbe_l2_tn_key key;
7755         struct ixgbe_l2_tn_filter *node;
7756
7757         if (!restore) {
7758                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7759                 key.tn_id = l2_tunnel->tunnel_id;
7760
7761                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7762
7763                 if (node) {
7764                         PMD_DRV_LOG(ERR,
7765                                     "The L2 tunnel filter already exists!");
7766                         return -EINVAL;
7767                 }
7768
7769                 node = rte_zmalloc("ixgbe_l2_tn",
7770                                    sizeof(struct ixgbe_l2_tn_filter),
7771                                    0);
7772                 if (!node)
7773                         return -ENOMEM;
7774
7775                 rte_memcpy(&node->key,
7776                                  &key,
7777                                  sizeof(struct ixgbe_l2_tn_key));
7778                 node->pool = l2_tunnel->pool;
7779                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7780                 if (ret < 0) {
7781                         rte_free(node);
7782                         return ret;
7783                 }
7784         }
7785
7786         switch (l2_tunnel->l2_tunnel_type) {
7787         case RTE_L2_TUNNEL_TYPE_E_TAG:
7788                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7789                 break;
7790         default:
7791                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7792                 ret = -EINVAL;
7793                 break;
7794         }
7795
7796         if ((!restore) && (ret < 0))
7797                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7798
7799         return ret;
7800 }
7801
7802 /* Delete l2 tunnel filter */
7803 int
7804 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7805                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7806 {
7807         int ret;
7808         struct ixgbe_l2_tn_info *l2_tn_info =
7809                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7810         struct ixgbe_l2_tn_key key;
7811
7812         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7813         key.tn_id = l2_tunnel->tunnel_id;
7814         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7815         if (ret < 0)
7816                 return ret;
7817
7818         switch (l2_tunnel->l2_tunnel_type) {
7819         case RTE_L2_TUNNEL_TYPE_E_TAG:
7820                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7821                 break;
7822         default:
7823                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7824                 ret = -EINVAL;
7825                 break;
7826         }
7827
7828         return ret;
7829 }
7830
7831 /**
7832  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7833  * @dev: pointer to rte_eth_dev structure
7834  * @filter_op:operation will be taken.
7835  * @arg: a pointer to specific structure corresponding to the filter_op
7836  */
7837 static int
7838 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7839                                   enum rte_filter_op filter_op,
7840                                   void *arg)
7841 {
7842         int ret;
7843
7844         if (filter_op == RTE_ETH_FILTER_NOP)
7845                 return 0;
7846
7847         if (arg == NULL) {
7848                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7849                             filter_op);
7850                 return -EINVAL;
7851         }
7852
7853         switch (filter_op) {
7854         case RTE_ETH_FILTER_ADD:
7855                 ret = ixgbe_dev_l2_tunnel_filter_add
7856                         (dev,
7857                          (struct rte_eth_l2_tunnel_conf *)arg,
7858                          FALSE);
7859                 break;
7860         case RTE_ETH_FILTER_DELETE:
7861                 ret = ixgbe_dev_l2_tunnel_filter_del
7862                         (dev,
7863                          (struct rte_eth_l2_tunnel_conf *)arg);
7864                 break;
7865         default:
7866                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7867                 ret = -EINVAL;
7868                 break;
7869         }
7870         return ret;
7871 }
7872
7873 static int
7874 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7875 {
7876         int ret = 0;
7877         uint32_t ctrl;
7878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7879
7880         if (hw->mac.type != ixgbe_mac_X550 &&
7881             hw->mac.type != ixgbe_mac_X550EM_x &&
7882             hw->mac.type != ixgbe_mac_X550EM_a) {
7883                 return -ENOTSUP;
7884         }
7885
7886         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7887         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7888         if (en)
7889                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7890         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7891
7892         return ret;
7893 }
7894
7895 /* Enable l2 tunnel forwarding */
7896 static int
7897 ixgbe_dev_l2_tunnel_forwarding_enable
7898         (struct rte_eth_dev *dev,
7899          enum rte_eth_tunnel_type l2_tunnel_type)
7900 {
7901         struct ixgbe_l2_tn_info *l2_tn_info =
7902                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7903         int ret = 0;
7904
7905         switch (l2_tunnel_type) {
7906         case RTE_L2_TUNNEL_TYPE_E_TAG:
7907                 l2_tn_info->e_tag_fwd_en = TRUE;
7908                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7909                 break;
7910         default:
7911                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7912                 ret = -EINVAL;
7913                 break;
7914         }
7915
7916         return ret;
7917 }
7918
7919 /* Disable l2 tunnel forwarding */
7920 static int
7921 ixgbe_dev_l2_tunnel_forwarding_disable
7922         (struct rte_eth_dev *dev,
7923          enum rte_eth_tunnel_type l2_tunnel_type)
7924 {
7925         struct ixgbe_l2_tn_info *l2_tn_info =
7926                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7927         int ret = 0;
7928
7929         switch (l2_tunnel_type) {
7930         case RTE_L2_TUNNEL_TYPE_E_TAG:
7931                 l2_tn_info->e_tag_fwd_en = FALSE;
7932                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7933                 break;
7934         default:
7935                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7936                 ret = -EINVAL;
7937                 break;
7938         }
7939
7940         return ret;
7941 }
7942
7943 static int
7944 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7945                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7946                              bool en)
7947 {
7948         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7949         int ret = 0;
7950         uint32_t vmtir, vmvir;
7951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7952
7953         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7954                 PMD_DRV_LOG(ERR,
7955                             "VF id %u should be less than %u",
7956                             l2_tunnel->vf_id,
7957                             pci_dev->max_vfs);
7958                 return -EINVAL;
7959         }
7960
7961         if (hw->mac.type != ixgbe_mac_X550 &&
7962             hw->mac.type != ixgbe_mac_X550EM_x &&
7963             hw->mac.type != ixgbe_mac_X550EM_a) {
7964                 return -ENOTSUP;
7965         }
7966
7967         if (en)
7968                 vmtir = l2_tunnel->tunnel_id;
7969         else
7970                 vmtir = 0;
7971
7972         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7973
7974         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7975         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7976         if (en)
7977                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7978         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7979
7980         return ret;
7981 }
7982
7983 /* Enable l2 tunnel tag insertion */
7984 static int
7985 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7986                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7987 {
7988         int ret = 0;
7989
7990         switch (l2_tunnel->l2_tunnel_type) {
7991         case RTE_L2_TUNNEL_TYPE_E_TAG:
7992                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7993                 break;
7994         default:
7995                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7996                 ret = -EINVAL;
7997                 break;
7998         }
7999
8000         return ret;
8001 }
8002
8003 /* Disable l2 tunnel tag insertion */
8004 static int
8005 ixgbe_dev_l2_tunnel_insertion_disable
8006         (struct rte_eth_dev *dev,
8007          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8008 {
8009         int ret = 0;
8010
8011         switch (l2_tunnel->l2_tunnel_type) {
8012         case RTE_L2_TUNNEL_TYPE_E_TAG:
8013                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8014                 break;
8015         default:
8016                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8017                 ret = -EINVAL;
8018                 break;
8019         }
8020
8021         return ret;
8022 }
8023
8024 static int
8025 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8026                              bool en)
8027 {
8028         int ret = 0;
8029         uint32_t qde;
8030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8031
8032         if (hw->mac.type != ixgbe_mac_X550 &&
8033             hw->mac.type != ixgbe_mac_X550EM_x &&
8034             hw->mac.type != ixgbe_mac_X550EM_a) {
8035                 return -ENOTSUP;
8036         }
8037
8038         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8039         if (en)
8040                 qde |= IXGBE_QDE_STRIP_TAG;
8041         else
8042                 qde &= ~IXGBE_QDE_STRIP_TAG;
8043         qde &= ~IXGBE_QDE_READ;
8044         qde |= IXGBE_QDE_WRITE;
8045         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8046
8047         return ret;
8048 }
8049
8050 /* Enable l2 tunnel tag stripping */
8051 static int
8052 ixgbe_dev_l2_tunnel_stripping_enable
8053         (struct rte_eth_dev *dev,
8054          enum rte_eth_tunnel_type l2_tunnel_type)
8055 {
8056         int ret = 0;
8057
8058         switch (l2_tunnel_type) {
8059         case RTE_L2_TUNNEL_TYPE_E_TAG:
8060                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8061                 break;
8062         default:
8063                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8064                 ret = -EINVAL;
8065                 break;
8066         }
8067
8068         return ret;
8069 }
8070
8071 /* Disable l2 tunnel tag stripping */
8072 static int
8073 ixgbe_dev_l2_tunnel_stripping_disable
8074         (struct rte_eth_dev *dev,
8075          enum rte_eth_tunnel_type l2_tunnel_type)
8076 {
8077         int ret = 0;
8078
8079         switch (l2_tunnel_type) {
8080         case RTE_L2_TUNNEL_TYPE_E_TAG:
8081                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8082                 break;
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -EINVAL;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 /* Enable/disable l2 tunnel offload functions */
8093 static int
8094 ixgbe_dev_l2_tunnel_offload_set
8095         (struct rte_eth_dev *dev,
8096          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8097          uint32_t mask,
8098          uint8_t en)
8099 {
8100         int ret = 0;
8101
8102         if (l2_tunnel == NULL)
8103                 return -EINVAL;
8104
8105         ret = -EINVAL;
8106         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8107                 if (en)
8108                         ret = ixgbe_dev_l2_tunnel_enable(
8109                                 dev,
8110                                 l2_tunnel->l2_tunnel_type);
8111                 else
8112                         ret = ixgbe_dev_l2_tunnel_disable(
8113                                 dev,
8114                                 l2_tunnel->l2_tunnel_type);
8115         }
8116
8117         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8118                 if (en)
8119                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8120                                 dev,
8121                                 l2_tunnel);
8122                 else
8123                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8124                                 dev,
8125                                 l2_tunnel);
8126         }
8127
8128         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8129                 if (en)
8130                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8131                                 dev,
8132                                 l2_tunnel->l2_tunnel_type);
8133                 else
8134                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8135                                 dev,
8136                                 l2_tunnel->l2_tunnel_type);
8137         }
8138
8139         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8140                 if (en)
8141                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8142                                 dev,
8143                                 l2_tunnel->l2_tunnel_type);
8144                 else
8145                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8146                                 dev,
8147                                 l2_tunnel->l2_tunnel_type);
8148         }
8149
8150         return ret;
8151 }
8152
8153 static int
8154 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8155                         uint16_t port)
8156 {
8157         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8158         IXGBE_WRITE_FLUSH(hw);
8159
8160         return 0;
8161 }
8162
8163 /* There's only one register for VxLAN UDP port.
8164  * So, we cannot add several ports. Will update it.
8165  */
8166 static int
8167 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8168                      uint16_t port)
8169 {
8170         if (port == 0) {
8171                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8172                 return -EINVAL;
8173         }
8174
8175         return ixgbe_update_vxlan_port(hw, port);
8176 }
8177
8178 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8179  * UDP port, it must have a value.
8180  * So, will reset it to the original value 0.
8181  */
8182 static int
8183 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8184                      uint16_t port)
8185 {
8186         uint16_t cur_port;
8187
8188         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8189
8190         if (cur_port != port) {
8191                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8192                 return -EINVAL;
8193         }
8194
8195         return ixgbe_update_vxlan_port(hw, 0);
8196 }
8197
8198 /* Add UDP tunneling port */
8199 static int
8200 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8201                               struct rte_eth_udp_tunnel *udp_tunnel)
8202 {
8203         int ret = 0;
8204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8205
8206         if (hw->mac.type != ixgbe_mac_X550 &&
8207             hw->mac.type != ixgbe_mac_X550EM_x &&
8208             hw->mac.type != ixgbe_mac_X550EM_a) {
8209                 return -ENOTSUP;
8210         }
8211
8212         if (udp_tunnel == NULL)
8213                 return -EINVAL;
8214
8215         switch (udp_tunnel->prot_type) {
8216         case RTE_TUNNEL_TYPE_VXLAN:
8217                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8218                 break;
8219
8220         case RTE_TUNNEL_TYPE_GENEVE:
8221         case RTE_TUNNEL_TYPE_TEREDO:
8222                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8223                 ret = -EINVAL;
8224                 break;
8225
8226         default:
8227                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8228                 ret = -EINVAL;
8229                 break;
8230         }
8231
8232         return ret;
8233 }
8234
8235 /* Remove UDP tunneling port */
8236 static int
8237 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8238                               struct rte_eth_udp_tunnel *udp_tunnel)
8239 {
8240         int ret = 0;
8241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8242
8243         if (hw->mac.type != ixgbe_mac_X550 &&
8244             hw->mac.type != ixgbe_mac_X550EM_x &&
8245             hw->mac.type != ixgbe_mac_X550EM_a) {
8246                 return -ENOTSUP;
8247         }
8248
8249         if (udp_tunnel == NULL)
8250                 return -EINVAL;
8251
8252         switch (udp_tunnel->prot_type) {
8253         case RTE_TUNNEL_TYPE_VXLAN:
8254                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8255                 break;
8256         case RTE_TUNNEL_TYPE_GENEVE:
8257         case RTE_TUNNEL_TYPE_TEREDO:
8258                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8259                 ret = -EINVAL;
8260                 break;
8261         default:
8262                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8263                 ret = -EINVAL;
8264                 break;
8265         }
8266
8267         return ret;
8268 }
8269
8270 static void
8271 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8272 {
8273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274
8275         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8276 }
8277
8278 static void
8279 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8280 {
8281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8282
8283         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8284 }
8285
8286 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8287 {
8288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8289         u32 in_msg = 0;
8290
8291         /* peek the message first */
8292         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8293
8294         /* PF reset VF event */
8295         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8296                 /* dummy mbx read to ack pf */
8297                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8298                         return;
8299                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8300                                               NULL);
8301         }
8302 }
8303
8304 static int
8305 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8306 {
8307         uint32_t eicr;
8308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8309         struct ixgbe_interrupt *intr =
8310                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8311         ixgbevf_intr_disable(dev);
8312
8313         /* read-on-clear nic registers here */
8314         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8315         intr->flags = 0;
8316
8317         /* only one misc vector supported - mailbox */
8318         eicr &= IXGBE_VTEICR_MASK;
8319         if (eicr == IXGBE_MISC_VEC_ID)
8320                 intr->flags |= IXGBE_FLAG_MAILBOX;
8321
8322         return 0;
8323 }
8324
8325 static int
8326 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8327 {
8328         struct ixgbe_interrupt *intr =
8329                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8330
8331         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8332                 ixgbevf_mbx_process(dev);
8333                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8334         }
8335
8336         ixgbevf_intr_enable(dev);
8337
8338         return 0;
8339 }
8340
8341 static void
8342 ixgbevf_dev_interrupt_handler(void *param)
8343 {
8344         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8345
8346         ixgbevf_dev_interrupt_get_status(dev);
8347         ixgbevf_dev_interrupt_action(dev);
8348 }
8349
8350 /**
8351  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8352  *  @hw: pointer to hardware structure
8353  *
8354  *  Stops the transmit data path and waits for the HW to internally empty
8355  *  the Tx security block
8356  **/
8357 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8358 {
8359 #define IXGBE_MAX_SECTX_POLL 40
8360
8361         int i;
8362         int sectxreg;
8363
8364         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8365         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8366         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8367         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8368                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8369                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8370                         break;
8371                 /* Use interrupt-safe sleep just in case */
8372                 usec_delay(1000);
8373         }
8374
8375         /* For informational purposes only */
8376         if (i >= IXGBE_MAX_SECTX_POLL)
8377                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8378                          "path fully disabled.  Continuing with init.");
8379
8380         return IXGBE_SUCCESS;
8381 }
8382
8383 /**
8384  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8385  *  @hw: pointer to hardware structure
8386  *
8387  *  Enables the transmit data path.
8388  **/
8389 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8390 {
8391         uint32_t sectxreg;
8392
8393         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8394         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8395         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8396         IXGBE_WRITE_FLUSH(hw);
8397
8398         return IXGBE_SUCCESS;
8399 }
8400
8401 /* restore n-tuple filter */
8402 static inline void
8403 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8404 {
8405         struct ixgbe_filter_info *filter_info =
8406                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8407         struct ixgbe_5tuple_filter *node;
8408
8409         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8410                 ixgbe_inject_5tuple_filter(dev, node);
8411         }
8412 }
8413
8414 /* restore ethernet type filter */
8415 static inline void
8416 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8417 {
8418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419         struct ixgbe_filter_info *filter_info =
8420                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8421         int i;
8422
8423         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8424                 if (filter_info->ethertype_mask & (1 << i)) {
8425                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8426                                         filter_info->ethertype_filters[i].etqf);
8427                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8428                                         filter_info->ethertype_filters[i].etqs);
8429                         IXGBE_WRITE_FLUSH(hw);
8430                 }
8431         }
8432 }
8433
8434 /* restore SYN filter */
8435 static inline void
8436 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8437 {
8438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8439         struct ixgbe_filter_info *filter_info =
8440                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8441         uint32_t synqf;
8442
8443         synqf = filter_info->syn_info;
8444
8445         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8446                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8447                 IXGBE_WRITE_FLUSH(hw);
8448         }
8449 }
8450
8451 /* restore L2 tunnel filter */
8452 static inline void
8453 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8454 {
8455         struct ixgbe_l2_tn_info *l2_tn_info =
8456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8457         struct ixgbe_l2_tn_filter *node;
8458         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8459
8460         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8461                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8462                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8463                 l2_tn_conf.pool           = node->pool;
8464                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8465         }
8466 }
8467
8468 /* restore rss filter */
8469 static inline void
8470 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8471 {
8472         struct ixgbe_filter_info *filter_info =
8473                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8474
8475         if (filter_info->rss_info.conf.queue_num)
8476                 ixgbe_config_rss_filter(dev,
8477                         &filter_info->rss_info, TRUE);
8478 }
8479
8480 static int
8481 ixgbe_filter_restore(struct rte_eth_dev *dev)
8482 {
8483         ixgbe_ntuple_filter_restore(dev);
8484         ixgbe_ethertype_filter_restore(dev);
8485         ixgbe_syn_filter_restore(dev);
8486         ixgbe_fdir_filter_restore(dev);
8487         ixgbe_l2_tn_filter_restore(dev);
8488         ixgbe_rss_filter_restore(dev);
8489
8490         return 0;
8491 }
8492
8493 static void
8494 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8495 {
8496         struct ixgbe_l2_tn_info *l2_tn_info =
8497                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8499
8500         if (l2_tn_info->e_tag_en)
8501                 (void)ixgbe_e_tag_enable(hw);
8502
8503         if (l2_tn_info->e_tag_fwd_en)
8504                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8505
8506         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8507 }
8508
8509 /* remove all the n-tuple filters */
8510 void
8511 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8512 {
8513         struct ixgbe_filter_info *filter_info =
8514                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8515         struct ixgbe_5tuple_filter *p_5tuple;
8516
8517         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8518                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8519 }
8520
8521 /* remove all the ether type filters */
8522 void
8523 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8524 {
8525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8526         struct ixgbe_filter_info *filter_info =
8527                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8528         int i;
8529
8530         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8531                 if (filter_info->ethertype_mask & (1 << i) &&
8532                     !filter_info->ethertype_filters[i].conf) {
8533                         (void)ixgbe_ethertype_filter_remove(filter_info,
8534                                                             (uint8_t)i);
8535                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8536                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8537                         IXGBE_WRITE_FLUSH(hw);
8538                 }
8539         }
8540 }
8541
8542 /* remove the SYN filter */
8543 void
8544 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8545 {
8546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8547         struct ixgbe_filter_info *filter_info =
8548                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8549
8550         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8551                 filter_info->syn_info = 0;
8552
8553                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8554                 IXGBE_WRITE_FLUSH(hw);
8555         }
8556 }
8557
8558 /* remove all the L2 tunnel filters */
8559 int
8560 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8561 {
8562         struct ixgbe_l2_tn_info *l2_tn_info =
8563                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8564         struct ixgbe_l2_tn_filter *l2_tn_filter;
8565         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8566         int ret = 0;
8567
8568         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8569                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8570                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8571                 l2_tn_conf.pool           = l2_tn_filter->pool;
8572                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8573                 if (ret < 0)
8574                         return ret;
8575         }
8576
8577         return 0;
8578 }
8579
8580 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8581 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8582 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8583 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8584 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8585 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8586
8587 RTE_INIT(ixgbe_init_log)
8588 {
8589         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8590         if (ixgbe_logtype_init >= 0)
8591                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8592         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8593         if (ixgbe_logtype_driver >= 0)
8594                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8595 }