drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 /*Default value of Max Rx Queue*/
  97 #define IXGBE_MAX_RX_QUEUE_NUM 128
  98
  99 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
 100 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
 101 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 102
 103 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 104 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 105 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 106
 107 /*
 108  *  Default values for RX/TX configuration
 109  */
 110 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_RX_PTHRESH      8
 112 #define IXGBE_DEFAULT_RX_HTHRESH      8
 113 #define IXGBE_DEFAULT_RX_WTHRESH      0
 114
 115 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 116 #define IXGBE_DEFAULT_TX_PTHRESH      32
 117 #define IXGBE_DEFAULT_TX_HTHRESH      0
 118 #define IXGBE_DEFAULT_TX_WTHRESH      0
 119 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 120
 121 /* Bit shift and mask */
 122 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 123 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 124 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 125 #define IXGBE_8_BIT_MASK   UINT8_MAX
 126
 127 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 128
 129 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 130
 131 #define IXGBE_HKEY_MAX_INDEX 10
 132
 133 /* Additional timesync values. */
 134 #define NSEC_PER_SEC             1000000000L
 135 #define IXGBE_INCVAL_10GB        0x66666666
 136 #define IXGBE_INCVAL_1GB         0x40000000
 137 #define IXGBE_INCVAL_100         0x50000000
 138 #define IXGBE_INCVAL_SHIFT_10GB  28
 139 #define IXGBE_INCVAL_SHIFT_1GB   24
 140 #define IXGBE_INCVAL_SHIFT_100   21
 141 #define IXGBE_INCVAL_SHIFT_82599 7
 142 #define IXGBE_INCPER_SHIFT_82599 24
 143
 144 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 145
 146 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 147 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 148 #define DEFAULT_ETAG_ETYPE                     0x893f
 149 #define IXGBE_ETAG_ETYPE                       0x00005084
 150 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 151 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 152 #define IXGBE_RAH_ADTYPE                       0x40000000
 153 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 154 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 155 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 156 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 157 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 158 #define IXGBE_VTEICR_MASK                      0x07
 159
 160 enum ixgbevf_xcast_modes {
 161         IXGBEVF_XCAST_MODE_NONE = 0,
 162         IXGBEVF_XCAST_MODE_MULTI,
 163         IXGBEVF_XCAST_MODE_ALLMULTI,
 164 };
 165
 166 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 167 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 168
 169 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 170 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 171 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 174 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 182                                 int wait_to_complete);
 183 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *stats);
 185 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 188                                   struct rte_eth_xstat *xstats, unsigned n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 196                                              uint16_t queue_id,
 197                                              uint8_t stat_idx,
 198                                              uint8_t is_rx);
 199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 200                                struct rte_eth_dev_info *dev_info);
 201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 203                                  struct rte_eth_dev_info *dev_info);
 204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205
 206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 207                 uint16_t vlan_id, int on);
 208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 209                                enum rte_vlan_type vlan_type,
 210                                uint16_t tpid_id);
 211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 212                 uint16_t queue, bool on);
 213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 214                 int on);
 215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 220
 221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 224                                struct rte_eth_fc_conf *fc_conf);
 225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 226                                struct rte_eth_fc_conf *fc_conf);
 227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 228                 struct rte_eth_pfc_conf *pfc_conf);
 229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 233                         struct rte_eth_rss_reta_entry64 *reta_conf,
 234                         uint16_t reta_size);
 235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 240 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 241                 void *param);
 242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 244                 uint32_t index, uint32_t pool);
 245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 247                                            struct ether_addr *mac_addr);
 248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 249
 250 /* For Virtual Function support */
 251 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 252 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 253 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 254 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 255 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 256                                    int wait_to_complete);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 285                 uint16_t rx_mask, uint8_t on);
 286 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 287 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 288 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 289                 uint64_t pool_mask, uint8_t vlan_on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 306                 uint16_t tx_rate, uint64_t q_msk);
 307
 308 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                  struct ether_addr *mac_addr,
 310                                  uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter,
 316                         bool add);
 317 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 318                         struct rte_eth_syn_filter *filter);
 319 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 320                         enum rte_filter_op filter_op,
 321                         void *arg);
 322 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 325                         struct ixgbe_5tuple_filter *filter);
 326 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter,
 328                         bool add);
 329 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ntuple_filter *filter);
 334 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 335                         struct rte_eth_ethertype_filter *filter,
 336                         bool add);
 337 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 338                                 enum rte_filter_op filter_op,
 339                                 void *arg);
 340 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 341                         struct rte_eth_ethertype_filter *filter);
 342 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 343                      enum rte_filter_type filter_type,
 344                      enum rte_filter_op filter_op,
 345                      void *arg);
 346 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 347
 348 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 349                                       struct ether_addr *mc_addr_set,
 350                                       uint32_t nb_mc_addr);
 351 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 352                                    struct rte_eth_dcb_info *dcb_info);
 353
 354 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 356                             struct rte_dev_reg_info *regs);
 357 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 358 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 361                                 struct rte_dev_eeprom_info *eeprom);
 362
 363 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 364 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 365                                 struct rte_dev_reg_info *regs);
 366
 367 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 368 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 369 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 370                                             struct timespec *timestamp,
 371                                             uint32_t flags);
 372 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 373                                             struct timespec *timestamp);
 374 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 375 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 376                                    struct timespec *timestamp);
 377 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 378                                    const struct timespec *timestamp);
 379 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                           void *param);
 381
 382 static int ixgbe_dev_l2_tunnel_eth_type_conf
 383         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 384 static int ixgbe_dev_l2_tunnel_offload_set
 385         (struct rte_eth_dev *dev,
 386          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 387          uint32_t mask,
 388          uint8_t en);
 389 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 390                                              enum rte_filter_op filter_op,
 391                                              void *arg);
 392
 393 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 396                                          struct rte_eth_udp_tunnel *udp_tunnel);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 492 #ifdef RTE_NIC_BYPASS
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 494 #endif
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 /*
 499  * The set of PCI devices this driver supports (for 82599 VF)
 500  */
 501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 511         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 512         { .vendor_id = 0, /* sentinel */ },
 513 };
 514
 515 static const struct rte_eth_desc_lim rx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_RXD_ALIGN,
 519 };
 520
 521 static const struct rte_eth_desc_lim tx_desc_lim = {
 522         .nb_max = IXGBE_MAX_RING_DESC,
 523         .nb_min = IXGBE_MIN_RING_DESC,
 524         .nb_align = IXGBE_TXD_ALIGN,
 525 };
 526
 527 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 528         .dev_configure        = ixgbe_dev_configure,
 529         .dev_start            = ixgbe_dev_start,
 530         .dev_stop             = ixgbe_dev_stop,
 531         .dev_set_link_up    = ixgbe_dev_set_link_up,
 532         .dev_set_link_down  = ixgbe_dev_set_link_down,
 533         .dev_close            = ixgbe_dev_close,
 534         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 535         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 536         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 537         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 538         .link_update          = ixgbe_dev_link_update,
 539         .stats_get            = ixgbe_dev_stats_get,
 540         .xstats_get           = ixgbe_dev_xstats_get,
 541         .stats_reset          = ixgbe_dev_stats_reset,
 542         .xstats_reset         = ixgbe_dev_xstats_reset,
 543         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .dev_infos_get        = ixgbe_dev_info_get,
 546         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 547         .mtu_set              = ixgbe_dev_mtu_set,
 548         .vlan_filter_set      = ixgbe_vlan_filter_set,
 549         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 550         .vlan_offload_set     = ixgbe_vlan_offload_set,
 551         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 552         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 553         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 554         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 555         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 556         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 557         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 558         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 559         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 560         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 561         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 577         .set_vf_rx            = ixgbe_set_pool_rx,
 578         .set_vf_tx            = ixgbe_set_pool_tx,
 579         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 580         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 581         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584 #ifdef RTE_NIC_BYPASS
 585         .bypass_init          = ixgbe_bypass_init,
 586         .bypass_state_set     = ixgbe_bypass_state_store,
 587         .bypass_state_show    = ixgbe_bypass_state_show,
 588         .bypass_event_set     = ixgbe_bypass_event_store,
 589         .bypass_event_show    = ixgbe_bypass_event_show,
 590         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 591         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 592         .bypass_ver_show      = ixgbe_bypass_ver_show,
 593         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 594 #endif /* RTE_NIC_BYPASS */
 595         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 596         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 597         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .timesync_enable      = ixgbe_timesync_enable,
 602         .timesync_disable     = ixgbe_timesync_disable,
 603         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 604         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 605         .get_reg              = ixgbe_get_regs,
 606         .get_eeprom_length    = ixgbe_get_eeprom_length,
 607         .get_eeprom           = ixgbe_get_eeprom,
 608         .set_eeprom           = ixgbe_set_eeprom,
 609         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 610         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 611         .timesync_read_time   = ixgbe_timesync_read_time,
 612         .timesync_write_time  = ixgbe_timesync_write_time,
 613         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 614         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 615         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 616         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 617 };
 618
 619 /*
 620  * dev_ops for virtual function, bare necessities for basic vf
 621  * operation have been implemented
 622  */
 623 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 624         .dev_configure        = ixgbevf_dev_configure,
 625         .dev_start            = ixgbevf_dev_start,
 626         .dev_stop             = ixgbevf_dev_stop,
 627         .link_update          = ixgbevf_dev_link_update,
 628         .stats_get            = ixgbevf_dev_stats_get,
 629         .xstats_get           = ixgbevf_dev_xstats_get,
 630         .stats_reset          = ixgbevf_dev_stats_reset,
 631         .xstats_reset         = ixgbevf_dev_stats_reset,
 632         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 633         .dev_close            = ixgbevf_dev_close,
 634         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 635         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 636         .dev_infos_get        = ixgbevf_dev_info_get,
 637         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 638         .mtu_set              = ixgbevf_dev_set_mtu,
 639         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 640         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 641         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 642         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 643         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 644         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 645         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 646         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 647         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 648         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 649         .mac_addr_add         = ixgbevf_add_mac_addr,
 650         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 651         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 652         .rxq_info_get         = ixgbe_rxq_info_get,
 653         .txq_info_get         = ixgbe_txq_info_get,
 654         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 655         .get_reg              = ixgbevf_get_regs,
 656         .reta_update          = ixgbe_dev_rss_reta_update,
 657         .reta_query           = ixgbe_dev_rss_reta_query,
 658         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 659         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 660 };
 661
 662 /* store statistics names and its offset in stats structure */
 663 struct rte_ixgbe_xstats_name_off {
 664         char name[RTE_ETH_XSTATS_NAME_SIZE];
 665         unsigned offset;
 666 };
 667
 668 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 669         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 670         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 671         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 672         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 673         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 674         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 675         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 676         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 677         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 678         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 679         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 680         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 681         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 682         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 683         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1023)},
 685         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 686                 prc1522)},
 687         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 688         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 689         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 690         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 691         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 692         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 693         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 694         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 695         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 696         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 697         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 698         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 699         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 700         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 701         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 702         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 703         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1023)},
 705         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 706                 ptc1522)},
 707         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 708         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 709         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 710         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 711
 712         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_add)},
 714         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirustat_remove)},
 716         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fadd)},
 718         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 719                 fdirfstat_fremove)},
 720         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmatch)},
 722         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 723                 fdirmiss)},
 724
 725         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 726         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 727         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 728                 fclast)},
 729         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 730         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 731         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 732         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 733         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 734                 fcoe_noddp)},
 735         {"rx_fcoe_no_direct_data_placement_ext_buff",
 736                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 737
 738         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxontxc)},
 740         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxonrxc)},
 742         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxofftxc)},
 744         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 745                 lxoffrxc)},
 746         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 747 };
 748
 749 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 750                            sizeof(rte_ixgbe_stats_strings[0]))
 751
 752 /* Per-queue statistics */
 753 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 754         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 755         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 756         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 757         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 758 };
 759
 760 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 761                            sizeof(rte_ixgbe_rxq_strings[0]))
 762 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 763
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 765         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 766         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 767         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 768                 pxon2offc)},
 769 };
 770
 771 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 772                            sizeof(rte_ixgbe_txq_strings[0]))
 773 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 776         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 777 };
 778
 779 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 780                 sizeof(rte_ixgbevf_stats_strings[0]))
 781
 782 /**
 783  * Atomically reads the link status information from global
 784  * structure rte_eth_dev.
 785  *
 786  * @param dev
 787  *   - Pointer to the structure rte_eth_dev to read from.
 788  *   - Pointer to the buffer to be saved with the link status.
 789  *
 790  * @return
 791  *   - On success, zero.
 792  *   - On failure, negative value.
 793  */
 794 static inline int
 795 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 796                                 struct rte_eth_link *link)
 797 {
 798         struct rte_eth_link *dst = link;
 799         struct rte_eth_link *src = &(dev->data->dev_link);
 800
 801         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 802                                         *(uint64_t *)src) == 0)
 803                 return -1;
 804
 805         return 0;
 806 }
 807
 808 /**
 809  * Atomically writes the link status information into global
 810  * structure rte_eth_dev.
 811  *
 812  * @param dev
 813  *   - Pointer to the structure rte_eth_dev to read from.
 814  *   - Pointer to the buffer to be saved with the link status.
 815  *
 816  * @return
 817  *   - On success, zero.
 818  *   - On failure, negative value.
 819  */
 820 static inline int
 821 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 822                                 struct rte_eth_link *link)
 823 {
 824         struct rte_eth_link *dst = &(dev->data->dev_link);
 825         struct rte_eth_link *src = link;
 826
 827         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 828                                         *(uint64_t *)src) == 0)
 829                 return -1;
 830
 831         return 0;
 832 }
 833
 834 /*
 835  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 836  */
 837 static inline int
 838 ixgbe_is_sfp(struct ixgbe_hw *hw)
 839 {
 840         switch (hw->phy.type) {
 841         case ixgbe_phy_sfp_avago:
 842         case ixgbe_phy_sfp_ftl:
 843         case ixgbe_phy_sfp_intel:
 844         case ixgbe_phy_sfp_unknown:
 845         case ixgbe_phy_sfp_passive_tyco:
 846         case ixgbe_phy_sfp_passive_unknown:
 847                 return 1;
 848         default:
 849                 return 0;
 850         }
 851 }
 852
 853 static inline int32_t
 854 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 855 {
 856         uint32_t ctrl_ext;
 857         int32_t status;
 858
 859         status = ixgbe_reset_hw(hw);
 860
 861         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 862         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 863         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 864         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 865         IXGBE_WRITE_FLUSH(hw);
 866
 867         return status;
 868 }
 869
 870 static inline void
 871 ixgbe_enable_intr(struct rte_eth_dev *dev)
 872 {
 873         struct ixgbe_interrupt *intr =
 874                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 875         struct ixgbe_hw *hw =
 876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 879         IXGBE_WRITE_FLUSH(hw);
 880 }
 881
 882 /*
 883  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 884  */
 885 static void
 886 ixgbe_disable_intr(struct ixgbe_hw *hw)
 887 {
 888         PMD_INIT_FUNC_TRACE();
 889
 890         if (hw->mac.type == ixgbe_mac_82598EB) {
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 892         } else {
 893                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 894                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 895                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 896         }
 897         IXGBE_WRITE_FLUSH(hw);
 898 }
 899
 900 /*
 901  * This function resets queue statistics mapping registers.
 902  * From Niantic datasheet, Initialization of Statistics section:
 903  * "...if software requires the queue counters, the RQSMR and TQSM registers
 904  * must be re-programmed following a device reset.
 905  */
 906 static void
 907 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 908 {
 909         uint32_t i;
 910
 911         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 912                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 914         }
 915 }
 916
 917
 918 static int
 919 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 920                                   uint16_t queue_id,
 921                                   uint8_t stat_idx,
 922                                   uint8_t is_rx)
 923 {
 924 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 925 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 926 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 927
 928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         struct ixgbe_stat_mapping_registers *stat_mappings =
 930                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 931         uint32_t qsmr_mask = 0;
 932         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 933         uint32_t q_map;
 934         uint8_t n, offset;
 935
 936         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 937                 (hw->mac.type != ixgbe_mac_X540) &&
 938                 (hw->mac.type != ixgbe_mac_X550) &&
 939                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 940                 (hw->mac.type != ixgbe_mac_X550EM_a))
 941                 return -ENOSYS;
 942
 943         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 944                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 945                      queue_id, stat_idx);
 946
 947         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 948         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 949                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 950                 return -EIO;
 951         }
 952         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 953
 954         /* Now clear any previous stat_idx set */
 955         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 956         if (!is_rx)
 957                 stat_mappings->tqsm[n] &= ~clearing_mask;
 958         else
 959                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 960
 961         q_map = (uint32_t)stat_idx;
 962         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 963         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 964         if (!is_rx)
 965                 stat_mappings->tqsm[n] |= qsmr_mask;
 966         else
 967                 stat_mappings->rqsmr[n] |= qsmr_mask;
 968
 969         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 970                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 971                      queue_id, stat_idx);
 972         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 973                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 974
 975         /* Now write the mapping in the appropriate register */
 976         if (is_rx) {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 978                              stat_mappings->rqsmr[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 980         } else {
 981                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 982                              stat_mappings->tqsm[n], n);
 983                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 984         }
 985         return 0;
 986 }
 987
 988 static void
 989 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 990 {
 991         struct ixgbe_stat_mapping_registers *stat_mappings =
 992                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 994         int i;
 995
 996         /* write whatever was in stat mapping table to the NIC */
 997         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 998                 /* rx */
 999                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1000
1001                 /* tx */
1002                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1003         }
1004 }
1005
1006 static void
1007 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1008 {
1009         uint8_t i;
1010         struct ixgbe_dcb_tc_config *tc;
1011         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1012
1013         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1014         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1015         for (i = 0; i < dcb_max_tc; i++) {
1016                 tc = &dcb_config->tc_config[i];
1017                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1018                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1019                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1020                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1021                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1022                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1023                 tc->pfc = ixgbe_dcb_pfc_disabled;
1024         }
1025
1026         /* Initialize default user to priority mapping, UPx->TC0 */
1027         tc = &dcb_config->tc_config[0];
1028         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1029         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1030         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1031                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1032                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1033         }
1034         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1035         dcb_config->pfc_mode_enable = false;
1036         dcb_config->vt_mode = true;
1037         dcb_config->round_robin_enable = false;
1038         /* support all DCB capabilities in 82599 */
1039         dcb_config->support.capabilities = 0xFF;
1040
1041         /*we only support 4 Tcs for X540, X550 */
1042         if (hw->mac.type == ixgbe_mac_X540 ||
1043                 hw->mac.type == ixgbe_mac_X550 ||
1044                 hw->mac.type == ixgbe_mac_X550EM_x ||
1045                 hw->mac.type == ixgbe_mac_X550EM_a) {
1046                 dcb_config->num_tcs.pg_tcs = 4;
1047                 dcb_config->num_tcs.pfc_tcs = 4;
1048         }
1049 }
1050
1051 /*
1052  * Ensure that all locks are released before first NVM or PHY access
1053  */
1054 static void
1055 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1056 {
1057         uint16_t mask;
1058
1059         /*
1060          * Phy lock should not fail in this early stage. If this is the case,
1061          * it is due to an improper exit of the application.
1062          * So force the release of the faulty lock. Release of common lock
1063          * is done automatically by swfw_sync function.
1064          */
1065         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1066         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1068         }
1069         ixgbe_release_swfw_semaphore(hw, mask);
1070
1071         /*
1072          * These ones are more tricky since they are common to all ports; but
1073          * swfw_sync retries last long enough (1s) to be almost sure that if
1074          * lock can not be taken it is due to an improper lock of the
1075          * semaphore.
1076          */
1077         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1078         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1079                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1080         }
1081         ixgbe_release_swfw_semaphore(hw, mask);
1082 }
1083
1084 /*
1085  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1086  * It returns 0 on success.
1087  */
1088 static int
1089 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1090 {
1091         struct rte_pci_device *pci_dev;
1092         struct ixgbe_hw *hw =
1093                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1094         struct ixgbe_vfta *shadow_vfta =
1095                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1096         struct ixgbe_hwstrip *hwstrip =
1097                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1098         struct ixgbe_dcb_config *dcb_config =
1099                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1100         struct ixgbe_filter_info *filter_info =
1101                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1102         uint32_t ctrl_ext;
1103         uint16_t csum;
1104         int diag, i;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1109         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1110         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1111
1112         /*
1113          * For secondary processes, we don't initialise any further as primary
1114          * has already done this work. Only check we don't need a different
1115          * RX and TX function.
1116          */
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118                 struct ixgbe_tx_queue *txq;
1119                 /* TX queue function in primary, set by last queue initialized
1120                  * Tx queue may not initialized by primary process
1121                  */
1122                 if (eth_dev->data->tx_queues) {
1123                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124                         ixgbe_set_tx_function(eth_dev, txq);
1125                 } else {
1126                         /* Use default TX function if we get here */
1127                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128                                      "Using default TX function.");
1129                 }
1130
1131                 ixgbe_set_rx_function(eth_dev);
1132
1133                 return 0;
1134         }
1135         pci_dev = eth_dev->pci_dev;
1136
1137         rte_eth_copy_pci_info(eth_dev, pci_dev);
1138
1139         /* Vendor and Device ID need to be set before init of shared code */
1140         hw->device_id = pci_dev->id.device_id;
1141         hw->vendor_id = pci_dev->id.vendor_id;
1142         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1143         hw->allow_unsupported_sfp = 1;
1144
1145         /* Initialize the shared code (base driver) */
1146 #ifdef RTE_NIC_BYPASS
1147         diag = ixgbe_bypass_init_shared_code(hw);
1148 #else
1149         diag = ixgbe_init_shared_code(hw);
1150 #endif /* RTE_NIC_BYPASS */
1151
1152         if (diag != IXGBE_SUCCESS) {
1153                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1154                 return -EIO;
1155         }
1156
1157         /* pick up the PCI bus settings for reporting later */
1158         ixgbe_get_bus_info(hw);
1159
1160         /* Unlock any pending hardware semaphore */
1161         ixgbe_swfw_lock_reset(hw);
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_full;
1168         hw->fc.current_mode = ixgbe_fc_full;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1243                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(&pci_dev->intr_handle,
1281                                    ixgbe_dev_interrupt_handler,
1282                                    (void *)eth_dev);
1283
1284         /* enable uio/vfio intr/eventfd mapping */
1285         rte_intr_enable(&pci_dev->intr_handle);
1286
1287         /* enable support intr */
1288         ixgbe_enable_intr(eth_dev);
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292         memset(filter_info->fivetuple_mask, 0,
1293                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1294
1295         return 0;
1296 }
1297
1298 static int
1299 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1300 {
1301         struct rte_pci_device *pci_dev;
1302         struct ixgbe_hw *hw;
1303
1304         PMD_INIT_FUNC_TRACE();
1305
1306         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1307                 return -EPERM;
1308
1309         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1310         pci_dev = eth_dev->pci_dev;
1311
1312         if (hw->adapter_stopped == 0)
1313                 ixgbe_dev_close(eth_dev);
1314
1315         eth_dev->dev_ops = NULL;
1316         eth_dev->rx_pkt_burst = NULL;
1317         eth_dev->tx_pkt_burst = NULL;
1318
1319         /* Unlock any pending hardware semaphore */
1320         ixgbe_swfw_lock_reset(hw);
1321
1322         /* disable uio intr before callback unregister */
1323         rte_intr_disable(&(pci_dev->intr_handle));
1324         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1325                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1326
1327         /* uninitialize PF if max_vfs not zero */
1328         ixgbe_pf_host_uninit(eth_dev);
1329
1330         rte_free(eth_dev->data->mac_addrs);
1331         eth_dev->data->mac_addrs = NULL;
1332
1333         rte_free(eth_dev->data->hash_mac_addrs);
1334         eth_dev->data->hash_mac_addrs = NULL;
1335
1336         return 0;
1337 }
1338
1339 /*
1340  * Negotiate mailbox API version with the PF.
1341  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1342  * Then we try to negotiate starting with the most recent one.
1343  * If all negotiation attempts fail, then we will proceed with
1344  * the default one (ixgbe_mbox_api_10).
1345  */
1346 static void
1347 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1348 {
1349         int32_t i;
1350
1351         /* start with highest supported, proceed down */
1352         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1353                 ixgbe_mbox_api_12,
1354                 ixgbe_mbox_api_11,
1355                 ixgbe_mbox_api_10,
1356         };
1357
1358         for (i = 0;
1359                         i != RTE_DIM(sup_ver) &&
1360                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1361                         i++)
1362                 ;
1363 }
1364
1365 static void
1366 generate_random_mac_addr(struct ether_addr *mac_addr)
1367 {
1368         uint64_t random;
1369
1370         /* Set Organizationally Unique Identifier (OUI) prefix. */
1371         mac_addr->addr_bytes[0] = 0x00;
1372         mac_addr->addr_bytes[1] = 0x09;
1373         mac_addr->addr_bytes[2] = 0xC0;
1374         /* Force indication of locally assigned MAC address. */
1375         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1376         /* Generate the last 3 bytes of the MAC address with a random number. */
1377         random = rte_rand();
1378         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1379 }
1380
1381 /*
1382  * Virtual Function device init
1383  */
1384 static int
1385 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1386 {
1387         int diag;
1388         uint32_t tc, tcs;
1389         struct rte_pci_device *pci_dev;
1390         struct ixgbe_hw *hw =
1391                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1392         struct ixgbe_vfta *shadow_vfta =
1393                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1394         struct ixgbe_hwstrip *hwstrip =
1395                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1396         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1401         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1402         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1403
1404         /* for secondary processes, we don't initialise any further as primary
1405          * has already done this work. Only check we don't need a different
1406          * RX function
1407          */
1408         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1409                 struct ixgbe_tx_queue *txq;
1410                 /* TX queue function in primary, set by last queue initialized
1411                  * Tx queue may not initialized by primary process
1412                  */
1413                 if (eth_dev->data->tx_queues) {
1414                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1415                         ixgbe_set_tx_function(eth_dev, txq);
1416                 } else {
1417                         /* Use default TX function if we get here */
1418                         PMD_INIT_LOG(NOTICE,
1419                                      "No TX queues configured yet. Using default TX function.");
1420                 }
1421
1422                 ixgbe_set_rx_function(eth_dev);
1423
1424                 return 0;
1425         }
1426
1427         pci_dev = eth_dev->pci_dev;
1428
1429         rte_eth_copy_pci_info(eth_dev, pci_dev);
1430
1431         hw->device_id = pci_dev->id.device_id;
1432         hw->vendor_id = pci_dev->id.vendor_id;
1433         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1434
1435         /* initialize the vfta */
1436         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1437
1438         /* initialize the hw strip bitmap*/
1439         memset(hwstrip, 0, sizeof(*hwstrip));
1440
1441         /* Initialize the shared code (base driver) */
1442         diag = ixgbe_init_shared_code(hw);
1443         if (diag != IXGBE_SUCCESS) {
1444                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1445                 return -EIO;
1446         }
1447
1448         /* init_mailbox_params */
1449         hw->mbx.ops.init_params(hw);
1450
1451         /* Reset the hw statistics */
1452         ixgbevf_dev_stats_reset(eth_dev);
1453
1454         /* Disable the interrupts for VF */
1455         ixgbevf_intr_disable(hw);
1456
1457         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1458         diag = hw->mac.ops.reset_hw(hw);
1459
1460         /*
1461          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1462          * the underlying PF driver has not assigned a MAC address to the VF.
1463          * In this case, assign a random MAC address.
1464          */
1465         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1466                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1467                 return diag;
1468         }
1469
1470         /* negotiate mailbox API version to use with the PF. */
1471         ixgbevf_negotiate_api(hw);
1472
1473         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1474         ixgbevf_get_queues(hw, &tcs, &tc);
1475
1476         /* Allocate memory for storing MAC addresses */
1477         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1478                                                hw->mac.num_rar_entries, 0);
1479         if (eth_dev->data->mac_addrs == NULL) {
1480                 PMD_INIT_LOG(ERR,
1481                              "Failed to allocate %u bytes needed to store "
1482                              "MAC addresses",
1483                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1484                 return -ENOMEM;
1485         }
1486
1487         /* Generate a random MAC address, if none was assigned by PF. */
1488         if (is_zero_ether_addr(perm_addr)) {
1489                 generate_random_mac_addr(perm_addr);
1490                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1491                 if (diag) {
1492                         rte_free(eth_dev->data->mac_addrs);
1493                         eth_dev->data->mac_addrs = NULL;
1494                         return diag;
1495                 }
1496                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1497                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1498                              "%02x:%02x:%02x:%02x:%02x:%02x",
1499                              perm_addr->addr_bytes[0],
1500                              perm_addr->addr_bytes[1],
1501                              perm_addr->addr_bytes[2],
1502                              perm_addr->addr_bytes[3],
1503                              perm_addr->addr_bytes[4],
1504                              perm_addr->addr_bytes[5]);
1505         }
1506
1507         /* Copy the permanent MAC address */
1508         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1509
1510         /* reset the hardware with the new settings */
1511         diag = hw->mac.ops.start_hw(hw);
1512         switch (diag) {
1513         case  0:
1514                 break;
1515
1516         default:
1517                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1518                 return -EIO;
1519         }
1520
1521         rte_intr_callback_register(&pci_dev->intr_handle,
1522                                    ixgbevf_dev_interrupt_handler,
1523                                    (void *)eth_dev);
1524         rte_intr_enable(&pci_dev->intr_handle);
1525         ixgbevf_intr_enable(hw);
1526
1527         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1528                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1529                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1530
1531         return 0;
1532 }
1533
1534 /* Virtual Function device uninit */
1535
1536 static int
1537 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1538 {
1539         struct ixgbe_hw *hw;
1540         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1541
1542         PMD_INIT_FUNC_TRACE();
1543
1544         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1545                 return -EPERM;
1546
1547         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548
1549         if (hw->adapter_stopped == 0)
1550                 ixgbevf_dev_close(eth_dev);
1551
1552         eth_dev->dev_ops = NULL;
1553         eth_dev->rx_pkt_burst = NULL;
1554         eth_dev->tx_pkt_burst = NULL;
1555
1556         /* Disable the interrupts for VF */
1557         ixgbevf_intr_disable(hw);
1558
1559         rte_free(eth_dev->data->mac_addrs);
1560         eth_dev->data->mac_addrs = NULL;
1561
1562         rte_intr_disable(&pci_dev->intr_handle);
1563         rte_intr_callback_unregister(&pci_dev->intr_handle,
1564                                      ixgbevf_dev_interrupt_handler,
1565                                      (void *)eth_dev);
1566
1567         return 0;
1568 }
1569
1570 static struct eth_driver rte_ixgbe_pmd = {
1571         .pci_drv = {
1572                 .id_table = pci_id_ixgbe_map,
1573                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1574                         RTE_PCI_DRV_DETACHABLE,
1575                 .probe = rte_eth_dev_pci_probe,
1576                 .remove = rte_eth_dev_pci_remove,
1577         },
1578         .eth_dev_init = eth_ixgbe_dev_init,
1579         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1580         .dev_private_size = sizeof(struct ixgbe_adapter),
1581 };
1582
1583 /*
1584  * virtual function driver struct
1585  */
1586 static struct eth_driver rte_ixgbevf_pmd = {
1587         .pci_drv = {
1588                 .id_table = pci_id_ixgbevf_map,
1589                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1590                 .probe = rte_eth_dev_pci_probe,
1591                 .remove = rte_eth_dev_pci_remove,
1592         },
1593         .eth_dev_init = eth_ixgbevf_dev_init,
1594         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1595         .dev_private_size = sizeof(struct ixgbe_adapter),
1596 };
1597
1598 static int
1599 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1600 {
1601         struct ixgbe_hw *hw =
1602                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         struct ixgbe_vfta *shadow_vfta =
1604                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1605         uint32_t vfta;
1606         uint32_t vid_idx;
1607         uint32_t vid_bit;
1608
1609         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1610         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1611         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1612         if (on)
1613                 vfta |= vid_bit;
1614         else
1615                 vfta &= ~vid_bit;
1616         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1617
1618         /* update local VFTA copy */
1619         shadow_vfta->vfta[vid_idx] = vfta;
1620
1621         return 0;
1622 }
1623
1624 static void
1625 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1626 {
1627         if (on)
1628                 ixgbe_vlan_hw_strip_enable(dev, queue);
1629         else
1630                 ixgbe_vlan_hw_strip_disable(dev, queue);
1631 }
1632
1633 static int
1634 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1635                     enum rte_vlan_type vlan_type,
1636                     uint16_t tpid)
1637 {
1638         struct ixgbe_hw *hw =
1639                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         int ret = 0;
1641         uint32_t reg;
1642         uint32_t qinq;
1643
1644         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1645         qinq &= IXGBE_DMATXCTL_GDV;
1646
1647         switch (vlan_type) {
1648         case ETH_VLAN_TYPE_INNER:
1649                 if (qinq) {
1650                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1651                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1652                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1653                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1654                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1655                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1656                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1657                 } else {
1658                         ret = -ENOTSUP;
1659                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1660                                     " by single VLAN");
1661                 }
1662                 break;
1663         case ETH_VLAN_TYPE_OUTER:
1664                 if (qinq) {
1665                         /* Only the high 16-bits is valid */
1666                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1667                                         IXGBE_EXVET_VET_EXT_SHIFT);
1668                 } else {
1669                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1670                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1671                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1672                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1673                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1674                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1675                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1676                 }
1677
1678                 break;
1679         default:
1680                 ret = -EINVAL;
1681                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1682                 break;
1683         }
1684
1685         return ret;
1686 }
1687
1688 void
1689 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1690 {
1691         struct ixgbe_hw *hw =
1692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         uint32_t vlnctrl;
1694
1695         PMD_INIT_FUNC_TRACE();
1696
1697         /* Filter Table Disable */
1698         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1699         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1700
1701         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1702 }
1703
1704 void
1705 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1706 {
1707         struct ixgbe_hw *hw =
1708                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct ixgbe_vfta *shadow_vfta =
1710                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1711         uint32_t vlnctrl;
1712         uint16_t i;
1713
1714         PMD_INIT_FUNC_TRACE();
1715
1716         /* Filter Table Enable */
1717         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1718         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1719         vlnctrl |= IXGBE_VLNCTRL_VFE;
1720
1721         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1722
1723         /* write whatever is in local vfta copy */
1724         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1725                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1726 }
1727
1728 static void
1729 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1730 {
1731         struct ixgbe_hwstrip *hwstrip =
1732                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1733         struct ixgbe_rx_queue *rxq;
1734
1735         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1736                 return;
1737
1738         if (on)
1739                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1740         else
1741                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1742
1743         if (queue >= dev->data->nb_rx_queues)
1744                 return;
1745
1746         rxq = dev->data->rx_queues[queue];
1747
1748         if (on)
1749                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1750         else
1751                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1752 }
1753
1754 static void
1755 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1756 {
1757         struct ixgbe_hw *hw =
1758                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759         uint32_t ctrl;
1760
1761         PMD_INIT_FUNC_TRACE();
1762
1763         if (hw->mac.type == ixgbe_mac_82598EB) {
1764                 /* No queue level support */
1765                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1766                 return;
1767         }
1768
1769         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1770         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1771         ctrl &= ~IXGBE_RXDCTL_VME;
1772         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1773
1774         /* record those setting for HW strip per queue */
1775         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1776 }
1777
1778 static void
1779 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1780 {
1781         struct ixgbe_hw *hw =
1782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783         uint32_t ctrl;
1784
1785         PMD_INIT_FUNC_TRACE();
1786
1787         if (hw->mac.type == ixgbe_mac_82598EB) {
1788                 /* No queue level supported */
1789                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1790                 return;
1791         }
1792
1793         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1794         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1795         ctrl |= IXGBE_RXDCTL_VME;
1796         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1797
1798         /* record those setting for HW strip per queue */
1799         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1800 }
1801
1802 void
1803 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1804 {
1805         struct ixgbe_hw *hw =
1806                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         uint32_t ctrl;
1808         uint16_t i;
1809         struct ixgbe_rx_queue *rxq;
1810
1811         PMD_INIT_FUNC_TRACE();
1812
1813         if (hw->mac.type == ixgbe_mac_82598EB) {
1814                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1815                 ctrl &= ~IXGBE_VLNCTRL_VME;
1816                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1817         } else {
1818                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1819                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1820                         rxq = dev->data->rx_queues[i];
1821                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1822                         ctrl &= ~IXGBE_RXDCTL_VME;
1823                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1824
1825                         /* record those setting for HW strip per queue */
1826                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1827                 }
1828         }
1829 }
1830
1831 void
1832 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         uint32_t ctrl;
1837         uint16_t i;
1838         struct ixgbe_rx_queue *rxq;
1839
1840         PMD_INIT_FUNC_TRACE();
1841
1842         if (hw->mac.type == ixgbe_mac_82598EB) {
1843                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1844                 ctrl |= IXGBE_VLNCTRL_VME;
1845                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1846         } else {
1847                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1848                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1849                         rxq = dev->data->rx_queues[i];
1850                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1851                         ctrl |= IXGBE_RXDCTL_VME;
1852                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1853
1854                         /* record those setting for HW strip per queue */
1855                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1856                 }
1857         }
1858 }
1859
1860 static void
1861 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1862 {
1863         struct ixgbe_hw *hw =
1864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         uint32_t ctrl;
1866
1867         PMD_INIT_FUNC_TRACE();
1868
1869         /* DMATXCTRL: Geric Double VLAN Disable */
1870         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871         ctrl &= ~IXGBE_DMATXCTL_GDV;
1872         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1873
1874         /* CTRL_EXT: Global Double VLAN Disable */
1875         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1876         ctrl &= ~IXGBE_EXTENDED_VLAN;
1877         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1878
1879 }
1880
1881 static void
1882 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1883 {
1884         struct ixgbe_hw *hw =
1885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         uint32_t ctrl;
1887
1888         PMD_INIT_FUNC_TRACE();
1889
1890         /* DMATXCTRL: Geric Double VLAN Enable */
1891         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1892         ctrl |= IXGBE_DMATXCTL_GDV;
1893         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1894
1895         /* CTRL_EXT: Global Double VLAN Enable */
1896         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1897         ctrl |= IXGBE_EXTENDED_VLAN;
1898         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1899
1900         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1901         if (hw->mac.type == ixgbe_mac_X550 ||
1902             hw->mac.type == ixgbe_mac_X550EM_x ||
1903             hw->mac.type == ixgbe_mac_X550EM_a) {
1904                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1905                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1906                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1907         }
1908
1909         /*
1910          * VET EXT field in the EXVET register = 0x8100 by default
1911          * So no need to change. Same to VT field of DMATXCTL register
1912          */
1913 }
1914
1915 static void
1916 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1917 {
1918         if (mask & ETH_VLAN_STRIP_MASK) {
1919                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1920                         ixgbe_vlan_hw_strip_enable_all(dev);
1921                 else
1922                         ixgbe_vlan_hw_strip_disable_all(dev);
1923         }
1924
1925         if (mask & ETH_VLAN_FILTER_MASK) {
1926                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1927                         ixgbe_vlan_hw_filter_enable(dev);
1928                 else
1929                         ixgbe_vlan_hw_filter_disable(dev);
1930         }
1931
1932         if (mask & ETH_VLAN_EXTEND_MASK) {
1933                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1934                         ixgbe_vlan_hw_extend_enable(dev);
1935                 else
1936                         ixgbe_vlan_hw_extend_disable(dev);
1937         }
1938 }
1939
1940 static void
1941 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1942 {
1943         struct ixgbe_hw *hw =
1944                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1946         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947
1948         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1949         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1950 }
1951
1952 static int
1953 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1954 {
1955         switch (nb_rx_q) {
1956         case 1:
1957         case 2:
1958                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1959                 break;
1960         case 4:
1961                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1962                 break;
1963         default:
1964                 return -EINVAL;
1965         }
1966
1967         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1968                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1969         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1970                 dev->pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1971         return 0;
1972 }
1973
1974 static int
1975 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1976 {
1977         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1978         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1980         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1981
1982         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1983                 /* check multi-queue mode */
1984                 switch (dev_conf->rxmode.mq_mode) {
1985                 case ETH_MQ_RX_VMDQ_DCB:
1986                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1987                         break;
1988                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1989                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1990                         PMD_INIT_LOG(ERR, "SRIOV active,"
1991                                         " unsupported mq_mode rx %d.",
1992                                         dev_conf->rxmode.mq_mode);
1993                         return -EINVAL;
1994                 case ETH_MQ_RX_RSS:
1995                 case ETH_MQ_RX_VMDQ_RSS:
1996                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1997                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1998                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1999                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2000                                                 " invalid queue number"
2001                                                 " for VMDQ RSS, allowed"
2002                                                 " value are 1, 2 or 4.");
2003                                         return -EINVAL;
2004                                 }
2005                         break;
2006                 case ETH_MQ_RX_VMDQ_ONLY:
2007                 case ETH_MQ_RX_NONE:
2008                         /* if nothing mq mode configure, use default scheme */
2009                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2010                         break;
2011                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2012                         /* SRIOV only works in VMDq enable mode */
2013                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2014                                         " wrong mq_mode rx %d.",
2015                                         dev_conf->rxmode.mq_mode);
2016                         return -EINVAL;
2017                 }
2018
2019                 switch (dev_conf->txmode.mq_mode) {
2020                 case ETH_MQ_TX_VMDQ_DCB:
2021                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2022                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2023                         break;
2024                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2025                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2026                         break;
2027                 }
2028
2029                 /* check valid queue number */
2030                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2031                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2032                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2033                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2034                                         " must be less than or equal to %d.",
2035                                         nb_rx_q, nb_tx_q,
2036                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2037                         return -EINVAL;
2038                 }
2039         } else {
2040                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2042                                           " not supported.");
2043                         return -EINVAL;
2044                 }
2045                 /* check configuration for vmdb+dcb mode */
2046                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2047                         const struct rte_eth_vmdq_dcb_conf *conf;
2048
2049                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2050                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2051                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2052                                 return -EINVAL;
2053                         }
2054                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2055                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2056                                conf->nb_queue_pools == ETH_32_POOLS)) {
2057                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2058                                                 " nb_queue_pools must be %d or %d.",
2059                                                 ETH_16_POOLS, ETH_32_POOLS);
2060                                 return -EINVAL;
2061                         }
2062                 }
2063                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2064                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2065
2066                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2067                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2068                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2069                                 return -EINVAL;
2070                         }
2071                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2072                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2073                                conf->nb_queue_pools == ETH_32_POOLS)) {
2074                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2075                                                 " nb_queue_pools != %d and"
2076                                                 " nb_queue_pools != %d.",
2077                                                 ETH_16_POOLS, ETH_32_POOLS);
2078                                 return -EINVAL;
2079                         }
2080                 }
2081
2082                 /* For DCB mode check our configuration before we go further */
2083                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2084                         const struct rte_eth_dcb_rx_conf *conf;
2085
2086                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2087                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2088                                                  IXGBE_DCB_NB_QUEUES);
2089                                 return -EINVAL;
2090                         }
2091                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2092                         if (!(conf->nb_tcs == ETH_4_TCS ||
2093                                conf->nb_tcs == ETH_8_TCS)) {
2094                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2095                                                 " and nb_tcs != %d.",
2096                                                 ETH_4_TCS, ETH_8_TCS);
2097                                 return -EINVAL;
2098                         }
2099                 }
2100
2101                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2102                         const struct rte_eth_dcb_tx_conf *conf;
2103
2104                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2105                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2106                                                  IXGBE_DCB_NB_QUEUES);
2107                                 return -EINVAL;
2108                         }
2109                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2110                         if (!(conf->nb_tcs == ETH_4_TCS ||
2111                                conf->nb_tcs == ETH_8_TCS)) {
2112                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2113                                                 " and nb_tcs != %d.",
2114                                                 ETH_4_TCS, ETH_8_TCS);
2115                                 return -EINVAL;
2116                         }
2117                 }
2118
2119                 /*
2120                  * When DCB/VT is off, maximum number of queues changes,
2121                  * except for 82598EB, which remains constant.
2122                  */
2123                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2124                                 hw->mac.type != ixgbe_mac_82598EB) {
2125                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2126                                 PMD_INIT_LOG(ERR,
2127                                              "Neither VT nor DCB are enabled, "
2128                                              "nb_tx_q > %d.",
2129                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2130                                 return -EINVAL;
2131                         }
2132                 }
2133         }
2134         return 0;
2135 }
2136
2137 static int
2138 ixgbe_dev_configure(struct rte_eth_dev *dev)
2139 {
2140         struct ixgbe_interrupt *intr =
2141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2142         struct ixgbe_adapter *adapter =
2143                 (struct ixgbe_adapter *)dev->data->dev_private;
2144         int ret;
2145
2146         PMD_INIT_FUNC_TRACE();
2147         /* multipe queue mode checking */
2148         ret  = ixgbe_check_mq_mode(dev);
2149         if (ret != 0) {
2150                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2151                             ret);
2152                 return ret;
2153         }
2154
2155         /* set flag to update link status after init */
2156         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2157
2158         /*
2159          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2160          * allocation or vector Rx preconditions we will reset it.
2161          */
2162         adapter->rx_bulk_alloc_allowed = true;
2163         adapter->rx_vec_allowed = true;
2164
2165         return 0;
2166 }
2167
2168 static void
2169 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2170 {
2171         struct ixgbe_hw *hw =
2172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct ixgbe_interrupt *intr =
2174                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2175         uint32_t gpie;
2176
2177         /* only set up it on X550EM_X */
2178         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2179                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2180                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2181                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2182                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2183                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2184         }
2185 }
2186
2187 /*
2188  * Configure device link speed and setup link.
2189  * It returns 0 on success.
2190  */
2191 static int
2192 ixgbe_dev_start(struct rte_eth_dev *dev)
2193 {
2194         struct ixgbe_hw *hw =
2195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         struct ixgbe_vf_info *vfinfo =
2197                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2198         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2199         uint32_t intr_vector = 0;
2200         int err, link_up = 0, negotiate = 0;
2201         uint32_t speed = 0;
2202         int mask = 0;
2203         int status;
2204         uint16_t vf, idx;
2205         uint32_t *link_speeds;
2206
2207         PMD_INIT_FUNC_TRACE();
2208
2209         /* IXGBE devices don't support:
2210         *    - half duplex (checked afterwards for valid speeds)
2211         *    - fixed speed: TODO implement
2212         */
2213         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2214                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2215                              dev->data->port_id);
2216                 return -EINVAL;
2217         }
2218
2219         /* disable uio/vfio intr/eventfd mapping */
2220         rte_intr_disable(intr_handle);
2221
2222         /* stop adapter */
2223         hw->adapter_stopped = 0;
2224         ixgbe_stop_adapter(hw);
2225
2226         /* reinitialize adapter
2227          * this calls reset and start
2228          */
2229         status = ixgbe_pf_reset_hw(hw);
2230         if (status != 0)
2231                 return -1;
2232         hw->mac.ops.start_hw(hw);
2233         hw->mac.get_link_status = true;
2234
2235         /* configure PF module if SRIOV enabled */
2236         ixgbe_pf_host_configure(dev);
2237
2238         ixgbe_dev_phy_intr_setup(dev);
2239
2240         /* check and configure queue intr-vector mapping */
2241         if ((rte_intr_cap_multiple(intr_handle) ||
2242              !RTE_ETH_DEV_SRIOV(dev).active) &&
2243             dev->data->dev_conf.intr_conf.rxq != 0) {
2244                 intr_vector = dev->data->nb_rx_queues;
2245                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2246                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2247                                         IXGBE_MAX_INTR_QUEUE_NUM);
2248                         return -ENOTSUP;
2249                 }
2250                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2251                         return -1;
2252         }
2253
2254         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2255                 intr_handle->intr_vec =
2256                         rte_zmalloc("intr_vec",
2257                                     dev->data->nb_rx_queues * sizeof(int), 0);
2258                 if (intr_handle->intr_vec == NULL) {
2259                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2260                                      " intr_vec\n", dev->data->nb_rx_queues);
2261                         return -ENOMEM;
2262                 }
2263         }
2264
2265         /* confiugre msix for sleep until rx interrupt */
2266         ixgbe_configure_msix(dev);
2267
2268         /* initialize transmission unit */
2269         ixgbe_dev_tx_init(dev);
2270
2271         /* This can fail when allocating mbufs for descriptor rings */
2272         err = ixgbe_dev_rx_init(dev);
2273         if (err) {
2274                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2275                 goto error;
2276         }
2277
2278     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2279                 ETH_VLAN_EXTEND_MASK;
2280         ixgbe_vlan_offload_set(dev, mask);
2281
2282         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2283                 /* Enable vlan filtering for VMDq */
2284                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2285         }
2286
2287         /* Configure DCB hw */
2288         ixgbe_configure_dcb(dev);
2289
2290         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2291                 err = ixgbe_fdir_configure(dev);
2292                 if (err)
2293                         goto error;
2294         }
2295
2296         /* Restore vf rate limit */
2297         if (vfinfo != NULL) {
2298                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2299                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2300                                 if (vfinfo[vf].tx_rate[idx] != 0)
2301                                         ixgbe_set_vf_rate_limit(dev, vf,
2302                                                 vfinfo[vf].tx_rate[idx],
2303                                                 1 << idx);
2304         }
2305
2306         ixgbe_restore_statistics_mapping(dev);
2307
2308         err = ixgbe_dev_rxtx_start(dev);
2309         if (err < 0) {
2310                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2311                 goto error;
2312         }
2313
2314         /* Skip link setup if loopback mode is enabled for 82599. */
2315         if (hw->mac.type == ixgbe_mac_82599EB &&
2316                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2317                 goto skip_link_setup;
2318
2319         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2320                 err = hw->mac.ops.setup_sfp(hw);
2321                 if (err)
2322                         goto error;
2323         }
2324
2325         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2326                 /* Turn on the copper */
2327                 ixgbe_set_phy_power(hw, true);
2328         } else {
2329                 /* Turn on the laser */
2330                 ixgbe_enable_tx_laser(hw);
2331         }
2332
2333         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2334         if (err)
2335                 goto error;
2336         dev->data->dev_link.link_status = link_up;
2337
2338         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2339         if (err)
2340                 goto error;
2341
2342         link_speeds = &dev->data->dev_conf.link_speeds;
2343         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2344                         ETH_LINK_SPEED_10G)) {
2345                 PMD_INIT_LOG(ERR, "Invalid link setting");
2346                 goto error;
2347         }
2348
2349         speed = 0x0;
2350         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2351                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2352                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2353                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2354         } else {
2355                 if (*link_speeds & ETH_LINK_SPEED_10G)
2356                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2357                 if (*link_speeds & ETH_LINK_SPEED_1G)
2358                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2359                 if (*link_speeds & ETH_LINK_SPEED_100M)
2360                         speed |= IXGBE_LINK_SPEED_100_FULL;
2361         }
2362
2363         err = ixgbe_setup_link(hw, speed, link_up);
2364         if (err)
2365                 goto error;
2366
2367 skip_link_setup:
2368
2369         if (rte_intr_allow_others(intr_handle)) {
2370                 /* check if lsc interrupt is enabled */
2371                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2372                         ixgbe_dev_lsc_interrupt_setup(dev);
2373         } else {
2374                 rte_intr_callback_unregister(intr_handle,
2375                                              ixgbe_dev_interrupt_handler,
2376                                              (void *)dev);
2377                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2378                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2379                                      " no intr multiplex\n");
2380         }
2381
2382         /* check if rxq interrupt is enabled */
2383         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2384             rte_intr_dp_is_en(intr_handle))
2385                 ixgbe_dev_rxq_interrupt_setup(dev);
2386
2387         /* enable uio/vfio intr/eventfd mapping */
2388         rte_intr_enable(intr_handle);
2389
2390         /* resume enabled intr since hw reset */
2391         ixgbe_enable_intr(dev);
2392
2393         return 0;
2394
2395 error:
2396         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2397         ixgbe_dev_clear_queues(dev);
2398         return -EIO;
2399 }
2400
2401 /*
2402  * Stop device: disable rx and tx functions to allow for reconfiguring.
2403  */
2404 static void
2405 ixgbe_dev_stop(struct rte_eth_dev *dev)
2406 {
2407         struct rte_eth_link link;
2408         struct ixgbe_hw *hw =
2409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410         struct ixgbe_vf_info *vfinfo =
2411                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2412         struct ixgbe_filter_info *filter_info =
2413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2414         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2415         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2416         int vf;
2417
2418         PMD_INIT_FUNC_TRACE();
2419
2420         /* disable interrupts */
2421         ixgbe_disable_intr(hw);
2422
2423         /* reset the NIC */
2424         ixgbe_pf_reset_hw(hw);
2425         hw->adapter_stopped = 0;
2426
2427         /* stop adapter */
2428         ixgbe_stop_adapter(hw);
2429
2430         for (vf = 0; vfinfo != NULL &&
2431                      vf < dev->pci_dev->max_vfs; vf++)
2432                 vfinfo[vf].clear_to_send = false;
2433
2434         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2435                 /* Turn off the copper */
2436                 ixgbe_set_phy_power(hw, false);
2437         } else {
2438                 /* Turn off the laser */
2439                 ixgbe_disable_tx_laser(hw);
2440         }
2441
2442         ixgbe_dev_clear_queues(dev);
2443
2444         /* Clear stored conf */
2445         dev->data->scattered_rx = 0;
2446         dev->data->lro = 0;
2447
2448         /* Clear recorded link status */
2449         memset(&link, 0, sizeof(link));
2450         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2451
2452         /* Remove all ntuple filters of the device */
2453         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2454              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2455                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2456                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2457                              p_5tuple, entries);
2458                 rte_free(p_5tuple);
2459         }
2460         memset(filter_info->fivetuple_mask, 0,
2461                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2462
2463         if (!rte_intr_allow_others(intr_handle))
2464                 /* resume to the default handler */
2465                 rte_intr_callback_register(intr_handle,
2466                                            ixgbe_dev_interrupt_handler,
2467                                            (void *)dev);
2468
2469         /* Clean datapath event and queue/vec mapping */
2470         rte_intr_efd_disable(intr_handle);
2471         if (intr_handle->intr_vec != NULL) {
2472                 rte_free(intr_handle->intr_vec);
2473                 intr_handle->intr_vec = NULL;
2474         }
2475 }
2476
2477 /*
2478  * Set device link up: enable tx.
2479  */
2480 static int
2481 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2482 {
2483         struct ixgbe_hw *hw =
2484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         if (hw->mac.type == ixgbe_mac_82599EB) {
2486 #ifdef RTE_NIC_BYPASS
2487                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2488                         /* Not suported in bypass mode */
2489                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2490                                      "by device id 0x%x", hw->device_id);
2491                         return -ENOTSUP;
2492                 }
2493 #endif
2494         }
2495
2496         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2497                 /* Turn on the copper */
2498                 ixgbe_set_phy_power(hw, true);
2499         } else {
2500                 /* Turn on the laser */
2501                 ixgbe_enable_tx_laser(hw);
2502         }
2503
2504         return 0;
2505 }
2506
2507 /*
2508  * Set device link down: disable tx.
2509  */
2510 static int
2511 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2512 {
2513         struct ixgbe_hw *hw =
2514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         if (hw->mac.type == ixgbe_mac_82599EB) {
2516 #ifdef RTE_NIC_BYPASS
2517                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2518                         /* Not suported in bypass mode */
2519                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2520                                      "by device id 0x%x", hw->device_id);
2521                         return -ENOTSUP;
2522                 }
2523 #endif
2524         }
2525
2526         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2527                 /* Turn off the copper */
2528                 ixgbe_set_phy_power(hw, false);
2529         } else {
2530                 /* Turn off the laser */
2531                 ixgbe_disable_tx_laser(hw);
2532         }
2533
2534         return 0;
2535 }
2536
2537 /*
2538  * Reest and stop device.
2539  */
2540 static void
2541 ixgbe_dev_close(struct rte_eth_dev *dev)
2542 {
2543         struct ixgbe_hw *hw =
2544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545
2546         PMD_INIT_FUNC_TRACE();
2547
2548         ixgbe_pf_reset_hw(hw);
2549
2550         ixgbe_dev_stop(dev);
2551         hw->adapter_stopped = 1;
2552
2553         ixgbe_dev_free_queues(dev);
2554
2555         ixgbe_disable_pcie_master(hw);
2556
2557         /* reprogram the RAR[0] in case user changed it. */
2558         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2559 }
2560
2561 static void
2562 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2563                            struct ixgbe_hw_stats *hw_stats,
2564                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2565                            uint64_t *total_qprc, uint64_t *total_qprdc)
2566 {
2567         uint32_t bprc, lxon, lxoff, total;
2568         uint32_t delta_gprc = 0;
2569         unsigned i;
2570         /* Workaround for RX byte count not including CRC bytes when CRC
2571 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2572          * is disabled.
2573 +        */
2574         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2575                         IXGBE_HLREG0_RXCRCSTRP);
2576
2577         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2578         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2579         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2580         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2581
2582         for (i = 0; i < 8; i++) {
2583                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2584
2585                 /* global total per queue */
2586                 hw_stats->mpc[i] += mp;
2587                 /* Running comprehensive total for stats display */
2588                 *total_missed_rx += hw_stats->mpc[i];
2589                 if (hw->mac.type == ixgbe_mac_82598EB) {
2590                         hw_stats->rnbc[i] +=
2591                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2592                         hw_stats->pxonrxc[i] +=
2593                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2594                         hw_stats->pxoffrxc[i] +=
2595                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2596                 } else {
2597                         hw_stats->pxonrxc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2599                         hw_stats->pxoffrxc[i] +=
2600                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2601                         hw_stats->pxon2offc[i] +=
2602                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2603                 }
2604                 hw_stats->pxontxc[i] +=
2605                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2606                 hw_stats->pxofftxc[i] +=
2607                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2608         }
2609         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2610                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2611                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2612                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2613
2614                 delta_gprc += delta_qprc;
2615
2616                 hw_stats->qprc[i] += delta_qprc;
2617                 hw_stats->qptc[i] += delta_qptc;
2618
2619                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2620                 hw_stats->qbrc[i] +=
2621                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2622                 if (crc_strip == 0)
2623                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2624
2625                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2626                 hw_stats->qbtc[i] +=
2627                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2628
2629                 hw_stats->qprdc[i] += delta_qprdc;
2630                 *total_qprdc += hw_stats->qprdc[i];
2631
2632                 *total_qprc += hw_stats->qprc[i];
2633                 *total_qbrc += hw_stats->qbrc[i];
2634         }
2635         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2636         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2637         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2638
2639         /*
2640          * An errata states that gprc actually counts good + missed packets:
2641          * Workaround to set gprc to summated queue packet receives
2642          */
2643         hw_stats->gprc = *total_qprc;
2644
2645         if (hw->mac.type != ixgbe_mac_82598EB) {
2646                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2647                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2648                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2649                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2650                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2651                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2652                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2653                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2654         } else {
2655                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2656                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2657                 /* 82598 only has a counter in the high register */
2658                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2659                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2660                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2661         }
2662         uint64_t old_tpr = hw_stats->tpr;
2663
2664         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2665         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2666
2667         if (crc_strip == 0)
2668                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2669
2670         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2671         hw_stats->gptc += delta_gptc;
2672         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2673         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2674
2675         /*
2676          * Workaround: mprc hardware is incorrectly counting
2677          * broadcasts, so for now we subtract those.
2678          */
2679         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2680         hw_stats->bprc += bprc;
2681         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2682         if (hw->mac.type == ixgbe_mac_82598EB)
2683                 hw_stats->mprc -= bprc;
2684
2685         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2686         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2687         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2688         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2689         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2690         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2691
2692         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2693         hw_stats->lxontxc += lxon;
2694         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2695         hw_stats->lxofftxc += lxoff;
2696         total = lxon + lxoff;
2697
2698         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2699         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2700         hw_stats->gptc -= total;
2701         hw_stats->mptc -= total;
2702         hw_stats->ptc64 -= total;
2703         hw_stats->gotc -= total * ETHER_MIN_LEN;
2704
2705         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2706         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2707         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2708         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2709         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2710         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2711         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2712         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2713         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2714         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2715         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2716         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2717         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2718         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2719         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2720         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2721         /* Only read FCOE on 82599 */
2722         if (hw->mac.type != ixgbe_mac_82598EB) {
2723                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2724                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2725                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2726                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2727                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2728         }
2729
2730         /* Flow Director Stats registers */
2731         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2732         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2733 }
2734
2735 /*
2736  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2737  */
2738 static void
2739 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2740 {
2741         struct ixgbe_hw *hw =
2742                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct ixgbe_hw_stats *hw_stats =
2744                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2745         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2746         unsigned i;
2747
2748         total_missed_rx = 0;
2749         total_qbrc = 0;
2750         total_qprc = 0;
2751         total_qprdc = 0;
2752
2753         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2754                         &total_qprc, &total_qprdc);
2755
2756         if (stats == NULL)
2757                 return;
2758
2759         /* Fill out the rte_eth_stats statistics structure */
2760         stats->ipackets = total_qprc;
2761         stats->ibytes = total_qbrc;
2762         stats->opackets = hw_stats->gptc;
2763         stats->obytes = hw_stats->gotc;
2764
2765         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2766                 stats->q_ipackets[i] = hw_stats->qprc[i];
2767                 stats->q_opackets[i] = hw_stats->qptc[i];
2768                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2769                 stats->q_obytes[i] = hw_stats->qbtc[i];
2770                 stats->q_errors[i] = hw_stats->qprdc[i];
2771         }
2772
2773         /* Rx Errors */
2774         stats->imissed  = total_missed_rx;
2775         stats->ierrors  = hw_stats->crcerrs +
2776                           hw_stats->mspdc +
2777                           hw_stats->rlec +
2778                           hw_stats->ruc +
2779                           hw_stats->roc +
2780                           hw_stats->illerrc +
2781                           hw_stats->errbc +
2782                           hw_stats->rfc +
2783                           hw_stats->fccrc +
2784                           hw_stats->fclast;
2785
2786         /* Tx Errors */
2787         stats->oerrors  = 0;
2788 }
2789
2790 static void
2791 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_hw_stats *stats =
2794                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2795
2796         /* HW registers are cleared on read */
2797         ixgbe_dev_stats_get(dev, NULL);
2798
2799         /* Reset software totals */
2800         memset(stats, 0, sizeof(*stats));
2801 }
2802
2803 /* This function calculates the number of xstats based on the current config */
2804 static unsigned
2805 ixgbe_xstats_calc_num(void) {
2806         return IXGBE_NB_HW_STATS +
2807                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2808                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2809 }
2810
2811 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2812         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2813 {
2814         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2815         unsigned stat, i, count;
2816
2817         if (xstats_names != NULL) {
2818                 count = 0;
2819
2820                 /* Note: limit >= cnt_stats checked upstream
2821                  * in rte_eth_xstats_names()
2822                  */
2823
2824                 /* Extended stats from ixgbe_hw_stats */
2825                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2826                         snprintf(xstats_names[count].name,
2827                                 sizeof(xstats_names[count].name),
2828                                 "%s",
2829                                 rte_ixgbe_stats_strings[i].name);
2830                         count++;
2831                 }
2832
2833                 /* RX Priority Stats */
2834                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2835                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2836                                 snprintf(xstats_names[count].name,
2837                                         sizeof(xstats_names[count].name),
2838                                         "rx_priority%u_%s", i,
2839                                         rte_ixgbe_rxq_strings[stat].name);
2840                                 count++;
2841                         }
2842                 }
2843
2844                 /* TX Priority Stats */
2845                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2846                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2847                                 snprintf(xstats_names[count].name,
2848                                         sizeof(xstats_names[count].name),
2849                                         "tx_priority%u_%s", i,
2850                                         rte_ixgbe_txq_strings[stat].name);
2851                                 count++;
2852                         }
2853                 }
2854         }
2855         return cnt_stats;
2856 }
2857
2858 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2859         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2860 {
2861         unsigned i;
2862
2863         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2864                 return -ENOMEM;
2865
2866         if (xstats_names != NULL)
2867                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2868                         snprintf(xstats_names[i].name,
2869                                 sizeof(xstats_names[i].name),
2870                                 "%s", rte_ixgbevf_stats_strings[i].name);
2871         return IXGBEVF_NB_XSTATS;
2872 }
2873
2874 static int
2875 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2876                                          unsigned n)
2877 {
2878         struct ixgbe_hw *hw =
2879                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880         struct ixgbe_hw_stats *hw_stats =
2881                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2882         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2883         unsigned i, stat, count = 0;
2884
2885         count = ixgbe_xstats_calc_num();
2886
2887         if (n < count)
2888                 return count;
2889
2890         total_missed_rx = 0;
2891         total_qbrc = 0;
2892         total_qprc = 0;
2893         total_qprdc = 0;
2894
2895         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2896                                    &total_qprc, &total_qprdc);
2897
2898         /* If this is a reset xstats is NULL, and we have cleared the
2899          * registers by reading them.
2900          */
2901         if (!xstats)
2902                 return 0;
2903
2904         /* Extended stats from ixgbe_hw_stats */
2905         count = 0;
2906         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2907                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2908                                 rte_ixgbe_stats_strings[i].offset);
2909                 xstats[count].id = count;
2910                 count++;
2911         }
2912
2913         /* RX Priority Stats */
2914         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2915                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2916                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2917                                         rte_ixgbe_rxq_strings[stat].offset +
2918                                         (sizeof(uint64_t) * i));
2919                         xstats[count].id = count;
2920                         count++;
2921                 }
2922         }
2923
2924         /* TX Priority Stats */
2925         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2926                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2927                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2928                                         rte_ixgbe_txq_strings[stat].offset +
2929                                         (sizeof(uint64_t) * i));
2930                         xstats[count].id = count;
2931                         count++;
2932                 }
2933         }
2934         return count;
2935 }
2936
2937 static void
2938 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw_stats *stats =
2941                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2942
2943         unsigned count = ixgbe_xstats_calc_num();
2944
2945         /* HW registers are cleared on read */
2946         ixgbe_dev_xstats_get(dev, NULL, count);
2947
2948         /* Reset software totals */
2949         memset(stats, 0, sizeof(*stats));
2950 }
2951
2952 static void
2953 ixgbevf_update_stats(struct rte_eth_dev *dev)
2954 {
2955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2957                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2958
2959         /* Good Rx packet, include VF loopback */
2960         UPDATE_VF_STAT(IXGBE_VFGPRC,
2961             hw_stats->last_vfgprc, hw_stats->vfgprc);
2962
2963         /* Good Rx octets, include VF loopback */
2964         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2965             hw_stats->last_vfgorc, hw_stats->vfgorc);
2966
2967         /* Good Tx packet, include VF loopback */
2968         UPDATE_VF_STAT(IXGBE_VFGPTC,
2969             hw_stats->last_vfgptc, hw_stats->vfgptc);
2970
2971         /* Good Tx octets, include VF loopback */
2972         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2973             hw_stats->last_vfgotc, hw_stats->vfgotc);
2974
2975         /* Rx Multicst Packet */
2976         UPDATE_VF_STAT(IXGBE_VFMPRC,
2977             hw_stats->last_vfmprc, hw_stats->vfmprc);
2978 }
2979
2980 static int
2981 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2982                        unsigned n)
2983 {
2984         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2985                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2986         unsigned i;
2987
2988         if (n < IXGBEVF_NB_XSTATS)
2989                 return IXGBEVF_NB_XSTATS;
2990
2991         ixgbevf_update_stats(dev);
2992
2993         if (!xstats)
2994                 return 0;
2995
2996         /* Extended stats */
2997         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2998                 xstats[i].id = i;
2999                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3000                         rte_ixgbevf_stats_strings[i].offset);
3001         }
3002
3003         return IXGBEVF_NB_XSTATS;
3004 }
3005
3006 static void
3007 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3008 {
3009         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3010                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3011
3012         ixgbevf_update_stats(dev);
3013
3014         if (stats == NULL)
3015                 return;
3016
3017         stats->ipackets = hw_stats->vfgprc;
3018         stats->ibytes = hw_stats->vfgorc;
3019         stats->opackets = hw_stats->vfgptc;
3020         stats->obytes = hw_stats->vfgotc;
3021 }
3022
3023 static void
3024 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3025 {
3026         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3027                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3028
3029         /* Sync HW register to the last stats */
3030         ixgbevf_dev_stats_get(dev, NULL);
3031
3032         /* reset HW current stats*/
3033         hw_stats->vfgprc = 0;
3034         hw_stats->vfgorc = 0;
3035         hw_stats->vfgptc = 0;
3036         hw_stats->vfgotc = 0;
3037 }
3038
3039 static void
3040 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3041 {
3042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3044
3045         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3046         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3047         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3048                 /*
3049                  * When DCB/VT is off, maximum number of queues changes,
3050                  * except for 82598EB, which remains constant.
3051                  */
3052                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3053                                 hw->mac.type != ixgbe_mac_82598EB)
3054                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3055         }
3056         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3057         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3058         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3059         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3060         dev_info->max_vfs = dev->pci_dev->max_vfs;
3061         if (hw->mac.type == ixgbe_mac_82598EB)
3062                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3063         else
3064                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3065         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3066         dev_info->rx_offload_capa =
3067                 DEV_RX_OFFLOAD_VLAN_STRIP |
3068                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3069                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3070                 DEV_RX_OFFLOAD_TCP_CKSUM;
3071
3072         /*
3073          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3074          * mode.
3075          */
3076         if ((hw->mac.type == ixgbe_mac_82599EB ||
3077              hw->mac.type == ixgbe_mac_X540) &&
3078             !RTE_ETH_DEV_SRIOV(dev).active)
3079                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3080
3081         if (hw->mac.type == ixgbe_mac_X550 ||
3082             hw->mac.type == ixgbe_mac_X550EM_x ||
3083             hw->mac.type == ixgbe_mac_X550EM_a)
3084                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3085
3086         dev_info->tx_offload_capa =
3087                 DEV_TX_OFFLOAD_VLAN_INSERT |
3088                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3089                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3090                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3091                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3092                 DEV_TX_OFFLOAD_TCP_TSO;
3093
3094         if (hw->mac.type == ixgbe_mac_X550 ||
3095             hw->mac.type == ixgbe_mac_X550EM_x ||
3096             hw->mac.type == ixgbe_mac_X550EM_a)
3097                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3098
3099         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3100                 .rx_thresh = {
3101                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3102                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3103                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3104                 },
3105                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3106                 .rx_drop_en = 0,
3107         };
3108
3109         dev_info->default_txconf = (struct rte_eth_txconf) {
3110                 .tx_thresh = {
3111                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3112                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3113                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3114                 },
3115                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3116                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3117                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3118                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3119         };
3120
3121         dev_info->rx_desc_lim = rx_desc_lim;
3122         dev_info->tx_desc_lim = tx_desc_lim;
3123
3124         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3125         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3126         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3127
3128         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3129         if (hw->mac.type == ixgbe_mac_X540 ||
3130             hw->mac.type == ixgbe_mac_X540_vf ||
3131             hw->mac.type == ixgbe_mac_X550 ||
3132             hw->mac.type == ixgbe_mac_X550_vf) {
3133                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3134         }
3135 }
3136
3137 static const uint32_t *
3138 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3139 {
3140         static const uint32_t ptypes[] = {
3141                 /* For non-vec functions,
3142                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3143                  * for vec functions,
3144                  * refers to _recv_raw_pkts_vec().
3145                  */
3146                 RTE_PTYPE_L2_ETHER,
3147                 RTE_PTYPE_L3_IPV4,
3148                 RTE_PTYPE_L3_IPV4_EXT,
3149                 RTE_PTYPE_L3_IPV6,
3150                 RTE_PTYPE_L3_IPV6_EXT,
3151                 RTE_PTYPE_L4_SCTP,
3152                 RTE_PTYPE_L4_TCP,
3153                 RTE_PTYPE_L4_UDP,
3154                 RTE_PTYPE_TUNNEL_IP,
3155                 RTE_PTYPE_INNER_L3_IPV6,
3156                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3157                 RTE_PTYPE_INNER_L4_TCP,
3158                 RTE_PTYPE_INNER_L4_UDP,
3159                 RTE_PTYPE_UNKNOWN
3160         };
3161
3162         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3163             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3164             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3165             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3166                 return ptypes;
3167         return NULL;
3168 }
3169
3170 static void
3171 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3172                      struct rte_eth_dev_info *dev_info)
3173 {
3174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175
3176         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3177         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3178         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3179         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3180         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3181         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3182         dev_info->max_vfs = dev->pci_dev->max_vfs;
3183         if (hw->mac.type == ixgbe_mac_82598EB)
3184                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3185         else
3186                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3187         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3188                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3189                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3190                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3191         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3192                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3193                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3194                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3195                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3196                                 DEV_TX_OFFLOAD_TCP_TSO;
3197
3198         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3199                 .rx_thresh = {
3200                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3201                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3202                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3203                 },
3204                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3205                 .rx_drop_en = 0,
3206         };
3207
3208         dev_info->default_txconf = (struct rte_eth_txconf) {
3209                 .tx_thresh = {
3210                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3211                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3212                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3213                 },
3214                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3215                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3216                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3217                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3218         };
3219
3220         dev_info->rx_desc_lim = rx_desc_lim;
3221         dev_info->tx_desc_lim = tx_desc_lim;
3222 }
3223
3224 static int
3225 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3226                    int *link_up, int wait_to_complete)
3227 {
3228         /**
3229          * for a quick link status checking, wait_to_compelet == 0,
3230          * skip PF link status checking
3231          */
3232         bool no_pflink_check = wait_to_complete == 0;
3233         struct ixgbe_mbx_info *mbx = &hw->mbx;
3234         struct ixgbe_mac_info *mac = &hw->mac;
3235         uint32_t links_reg, in_msg;
3236         int ret_val = 0;
3237
3238         /* If we were hit with a reset drop the link */
3239         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3240                 mac->get_link_status = true;
3241
3242         if (!mac->get_link_status)
3243                 goto out;
3244
3245         /* if link status is down no point in checking to see if pf is up */
3246         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3247         if (!(links_reg & IXGBE_LINKS_UP))
3248                 goto out;
3249
3250         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3251          * before the link status is correct
3252          */
3253         if (mac->type == ixgbe_mac_82599_vf) {
3254                 int i;
3255
3256                 for (i = 0; i < 5; i++) {
3257                         rte_delay_us(100);
3258                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3259
3260                         if (!(links_reg & IXGBE_LINKS_UP))
3261                                 goto out;
3262                 }
3263         }
3264
3265         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3266         case IXGBE_LINKS_SPEED_10G_82599:
3267                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3268                 if (hw->mac.type >= ixgbe_mac_X550) {
3269                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3270                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3271                 }
3272                 break;
3273         case IXGBE_LINKS_SPEED_1G_82599:
3274                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3275                 break;
3276         case IXGBE_LINKS_SPEED_100_82599:
3277                 *speed = IXGBE_LINK_SPEED_100_FULL;
3278                 if (hw->mac.type == ixgbe_mac_X550) {
3279                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3280                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3281                 }
3282                 break;
3283         case IXGBE_LINKS_SPEED_10_X550EM_A:
3284                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3285                 /* Since Reserved in older MAC's */
3286                 if (hw->mac.type >= ixgbe_mac_X550)
3287                         *speed = IXGBE_LINK_SPEED_10_FULL;
3288                 break;
3289         default:
3290                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3291         }
3292
3293         if (no_pflink_check) {
3294                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3295                         mac->get_link_status = true;
3296                 else
3297                         mac->get_link_status = false;
3298
3299                 goto out;
3300         }
3301         /* if the read failed it could just be a mailbox collision, best wait
3302          * until we are called again and don't report an error
3303          */
3304         if (mbx->ops.read(hw, &in_msg, 1, 0))
3305                 goto out;
3306
3307         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3308                 /* msg is not CTS and is NACK we must have lost CTS status */
3309                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3310                         ret_val = -1;
3311                 goto out;
3312         }
3313
3314         /* the pf is talking, if we timed out in the past we reinit */
3315         if (!mbx->timeout) {
3316                 ret_val = -1;
3317                 goto out;
3318         }
3319
3320         /* if we passed all the tests above then the link is up and we no
3321          * longer need to check for link
3322          */
3323         mac->get_link_status = false;
3324
3325 out:
3326         *link_up = !mac->get_link_status;
3327         return ret_val;
3328 }
3329
3330 /* return 0 means link status changed, -1 means not changed */
3331 static int
3332 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3333                             int wait_to_complete, int vf)
3334 {
3335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336         struct rte_eth_link link, old;
3337         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3338         int link_up;
3339         int diag;
3340         int wait = 1;
3341
3342         link.link_status = ETH_LINK_DOWN;
3343         link.link_speed = 0;
3344         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3345         link.link_autoneg = ETH_LINK_AUTONEG;
3346         memset(&old, 0, sizeof(old));
3347         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3348
3349         hw->mac.get_link_status = true;
3350
3351         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3352         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3353                 wait = 0;
3354
3355         if (vf)
3356                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3357         else
3358                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3359
3360         if (diag != 0) {
3361                 link.link_speed = ETH_SPEED_NUM_100M;
3362                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3363                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3364                 if (link.link_status == old.link_status)
3365                         return -1;
3366                 return 0;
3367         }
3368
3369         if (link_up == 0) {
3370                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3371                 if (link.link_status == old.link_status)
3372                         return -1;
3373                 return 0;
3374         }
3375         link.link_status = ETH_LINK_UP;
3376         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3377
3378         switch (link_speed) {
3379         default:
3380         case IXGBE_LINK_SPEED_UNKNOWN:
3381                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3382                 link.link_speed = ETH_SPEED_NUM_100M;
3383                 break;
3384
3385         case IXGBE_LINK_SPEED_100_FULL:
3386                 link.link_speed = ETH_SPEED_NUM_100M;
3387                 break;
3388
3389         case IXGBE_LINK_SPEED_1GB_FULL:
3390                 link.link_speed = ETH_SPEED_NUM_1G;
3391                 break;
3392
3393         case IXGBE_LINK_SPEED_10GB_FULL:
3394                 link.link_speed = ETH_SPEED_NUM_10G;
3395                 break;
3396         }
3397         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3398
3399         if (link.link_status == old.link_status)
3400                 return -1;
3401
3402         return 0;
3403 }
3404
3405 static int
3406 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3407 {
3408         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3409 }
3410
3411 static int
3412 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3413 {
3414         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3415 }
3416
3417 static void
3418 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3419 {
3420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421         uint32_t fctrl;
3422
3423         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3424         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3425         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3426 }
3427
3428 static void
3429 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3430 {
3431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         uint32_t fctrl;
3433
3434         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3435         fctrl &= (~IXGBE_FCTRL_UPE);
3436         if (dev->data->all_multicast == 1)
3437                 fctrl |= IXGBE_FCTRL_MPE;
3438         else
3439                 fctrl &= (~IXGBE_FCTRL_MPE);
3440         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3441 }
3442
3443 static void
3444 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3445 {
3446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3447         uint32_t fctrl;
3448
3449         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3450         fctrl |= IXGBE_FCTRL_MPE;
3451         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3452 }
3453
3454 static void
3455 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3456 {
3457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         uint32_t fctrl;
3459
3460         if (dev->data->promiscuous == 1)
3461                 return; /* must remain in all_multicast mode */
3462
3463         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3464         fctrl &= (~IXGBE_FCTRL_MPE);
3465         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3466 }
3467
3468 /**
3469  * It clears the interrupt causes and enables the interrupt.
3470  * It will be called once only during nic initialized.
3471  *
3472  * @param dev
3473  *  Pointer to struct rte_eth_dev.
3474  *
3475  * @return
3476  *  - On success, zero.
3477  *  - On failure, a negative value.
3478  */
3479 static int
3480 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3481 {
3482         struct ixgbe_interrupt *intr =
3483                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3484
3485         ixgbe_dev_link_status_print(dev);
3486         intr->mask |= IXGBE_EICR_LSC;
3487
3488         return 0;
3489 }
3490
3491 /**
3492  * It clears the interrupt causes and enables the interrupt.
3493  * It will be called once only during nic initialized.
3494  *
3495  * @param dev
3496  *  Pointer to struct rte_eth_dev.
3497  *
3498  * @return
3499  *  - On success, zero.
3500  *  - On failure, a negative value.
3501  */
3502 static int
3503 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3504 {
3505         struct ixgbe_interrupt *intr =
3506                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3507
3508         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3509
3510         return 0;
3511 }
3512
3513 /*
3514  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3515  *
3516  * @param dev
3517  *  Pointer to struct rte_eth_dev.
3518  *
3519  * @return
3520  *  - On success, zero.
3521  *  - On failure, a negative value.
3522  */
3523 static int
3524 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3525 {
3526         uint32_t eicr;
3527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528         struct ixgbe_interrupt *intr =
3529                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3530
3531         /* clear all cause mask */
3532         ixgbe_disable_intr(hw);
3533
3534         /* read-on-clear nic registers here */
3535         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3536         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3537
3538         intr->flags = 0;
3539
3540         /* set flag for async link update */
3541         if (eicr & IXGBE_EICR_LSC)
3542                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3543
3544         if (eicr & IXGBE_EICR_MAILBOX)
3545                 intr->flags |= IXGBE_FLAG_MAILBOX;
3546
3547         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3548             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3549             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3550                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3551
3552         return 0;
3553 }
3554
3555 /**
3556  * It gets and then prints the link status.
3557  *
3558  * @param dev
3559  *  Pointer to struct rte_eth_dev.
3560  *
3561  * @return
3562  *  - On success, zero.
3563  *  - On failure, a negative value.
3564  */
3565 static void
3566 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3567 {
3568         struct rte_eth_link link;
3569
3570         memset(&link, 0, sizeof(link));
3571         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3572         if (link.link_status) {
3573                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3574                                         (int)(dev->data->port_id),
3575                                         (unsigned)link.link_speed,
3576                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3577                                         "full-duplex" : "half-duplex");
3578         } else {
3579                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3580                                 (int)(dev->data->port_id));
3581         }
3582         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3583                                 dev->pci_dev->addr.domain,
3584                                 dev->pci_dev->addr.bus,
3585                                 dev->pci_dev->addr.devid,
3586                                 dev->pci_dev->addr.function);
3587 }
3588
3589 /*
3590  * It executes link_update after knowing an interrupt occurred.
3591  *
3592  * @param dev
3593  *  Pointer to struct rte_eth_dev.
3594  *
3595  * @return
3596  *  - On success, zero.
3597  *  - On failure, a negative value.
3598  */
3599 static int
3600 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3601 {
3602         struct ixgbe_interrupt *intr =
3603                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3604         int64_t timeout;
3605         struct rte_eth_link link;
3606         struct ixgbe_hw *hw =
3607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608
3609         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3610
3611         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3612                 ixgbe_pf_mbx_process(dev);
3613                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3614         }
3615
3616         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3617                 ixgbe_handle_lasi(hw);
3618                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3619         }
3620
3621         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3622                 /* get the link status before link update, for predicting later */
3623                 memset(&link, 0, sizeof(link));
3624                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3625
3626                 ixgbe_dev_link_update(dev, 0);
3627
3628                 /* likely to up */
3629                 if (!link.link_status)
3630                         /* handle it 1 sec later, wait it being stable */
3631                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3632                 /* likely to down */
3633                 else
3634                         /* handle it 4 sec later, wait it being stable */
3635                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3636
3637                 ixgbe_dev_link_status_print(dev);
3638                 intr->mask_original = intr->mask;
3639                 /* only disable lsc interrupt */
3640                 intr->mask &= ~IXGBE_EIMS_LSC;
3641                 if (rte_eal_alarm_set(timeout * 1000,
3642                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3643                         PMD_DRV_LOG(ERR, "Error setting alarm");
3644                 else
3645                         intr->mask = intr->mask_original;
3646         }
3647
3648         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3649         ixgbe_enable_intr(dev);
3650         rte_intr_enable(&dev->pci_dev->intr_handle);
3651
3652         return 0;
3653 }
3654
3655 /**
3656  * Interrupt handler which shall be registered for alarm callback for delayed
3657  * handling specific interrupt to wait for the stable nic state. As the
3658  * NIC interrupt state is not stable for ixgbe after link is just down,
3659  * it needs to wait 4 seconds to get the stable status.
3660  *
3661  * @param handle
3662  *  Pointer to interrupt handle.
3663  * @param param
3664  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3665  *
3666  * @return
3667  *  void
3668  */
3669 static void
3670 ixgbe_dev_interrupt_delayed_handler(void *param)
3671 {
3672         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3673         struct ixgbe_interrupt *intr =
3674                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3675         struct ixgbe_hw *hw =
3676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3677         uint32_t eicr;
3678
3679         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3680         if (eicr & IXGBE_EICR_MAILBOX)
3681                 ixgbe_pf_mbx_process(dev);
3682
3683         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3684                 ixgbe_handle_lasi(hw);
3685                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3686         }
3687
3688         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3689                 ixgbe_dev_link_update(dev, 0);
3690                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3691                 ixgbe_dev_link_status_print(dev);
3692                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3693         }
3694
3695         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3696         ixgbe_enable_intr(dev);
3697         rte_intr_enable(&(dev->pci_dev->intr_handle));
3698 }
3699
3700 /**
3701  * Interrupt handler triggered by NIC  for handling
3702  * specific interrupt.
3703  *
3704  * @param handle
3705  *  Pointer to interrupt handle.
3706  * @param param
3707  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3708  *
3709  * @return
3710  *  void
3711  */
3712 static void
3713 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3714                             void *param)
3715 {
3716         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3717
3718         ixgbe_dev_interrupt_get_status(dev);
3719         ixgbe_dev_interrupt_action(dev);
3720 }
3721
3722 static int
3723 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3724 {
3725         struct ixgbe_hw *hw;
3726
3727         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3729 }
3730
3731 static int
3732 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3733 {
3734         struct ixgbe_hw *hw;
3735
3736         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3738 }
3739
3740 static int
3741 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3742 {
3743         struct ixgbe_hw *hw;
3744         uint32_t mflcn_reg;
3745         uint32_t fccfg_reg;
3746         int rx_pause;
3747         int tx_pause;
3748
3749         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750
3751         fc_conf->pause_time = hw->fc.pause_time;
3752         fc_conf->high_water = hw->fc.high_water[0];
3753         fc_conf->low_water = hw->fc.low_water[0];
3754         fc_conf->send_xon = hw->fc.send_xon;
3755         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3756
3757         /*
3758          * Return rx_pause status according to actual setting of
3759          * MFLCN register.
3760          */
3761         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3762         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3763                 rx_pause = 1;
3764         else
3765                 rx_pause = 0;
3766
3767         /*
3768          * Return tx_pause status according to actual setting of
3769          * FCCFG register.
3770          */
3771         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3772         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3773                 tx_pause = 1;
3774         else
3775                 tx_pause = 0;
3776
3777         if (rx_pause && tx_pause)
3778                 fc_conf->mode = RTE_FC_FULL;
3779         else if (rx_pause)
3780                 fc_conf->mode = RTE_FC_RX_PAUSE;
3781         else if (tx_pause)
3782                 fc_conf->mode = RTE_FC_TX_PAUSE;
3783         else
3784                 fc_conf->mode = RTE_FC_NONE;
3785
3786         return 0;
3787 }
3788
3789 static int
3790 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3791 {
3792         struct ixgbe_hw *hw;
3793         int err;
3794         uint32_t rx_buf_size;
3795         uint32_t max_high_water;
3796         uint32_t mflcn;
3797         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3798                 ixgbe_fc_none,
3799                 ixgbe_fc_rx_pause,
3800                 ixgbe_fc_tx_pause,
3801                 ixgbe_fc_full
3802         };
3803
3804         PMD_INIT_FUNC_TRACE();
3805
3806         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3808         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3809
3810         /*
3811          * At least reserve one Ethernet frame for watermark
3812          * high_water/low_water in kilo bytes for ixgbe
3813          */
3814         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3815         if ((fc_conf->high_water > max_high_water) ||
3816                 (fc_conf->high_water < fc_conf->low_water)) {
3817                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3818                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3819                 return -EINVAL;
3820         }
3821
3822         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3823         hw->fc.pause_time     = fc_conf->pause_time;
3824         hw->fc.high_water[0]  = fc_conf->high_water;
3825         hw->fc.low_water[0]   = fc_conf->low_water;
3826         hw->fc.send_xon       = fc_conf->send_xon;
3827         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3828
3829         err = ixgbe_fc_enable(hw);
3830
3831         /* Not negotiated is not an error case */
3832         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3833
3834                 /* check if we want to forward MAC frames - driver doesn't have native
3835                  * capability to do that, so we'll write the registers ourselves */
3836
3837                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3838
3839                 /* set or clear MFLCN.PMCF bit depending on configuration */
3840                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3841                         mflcn |= IXGBE_MFLCN_PMCF;
3842                 else
3843                         mflcn &= ~IXGBE_MFLCN_PMCF;
3844
3845                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3846                 IXGBE_WRITE_FLUSH(hw);
3847
3848                 return 0;
3849         }
3850
3851         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3852         return -EIO;
3853 }
3854
3855 /**
3856  *  ixgbe_pfc_enable_generic - Enable flow control
3857  *  @hw: pointer to hardware structure
3858  *  @tc_num: traffic class number
3859  *  Enable flow control according to the current settings.
3860  */
3861 static int
3862 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3863 {
3864         int ret_val = 0;
3865         uint32_t mflcn_reg, fccfg_reg;
3866         uint32_t reg;
3867         uint32_t fcrtl, fcrth;
3868         uint8_t i;
3869         uint8_t nb_rx_en;
3870
3871         /* Validate the water mark configuration */
3872         if (!hw->fc.pause_time) {
3873                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3874                 goto out;
3875         }
3876
3877         /* Low water mark of zero causes XOFF floods */
3878         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3879                  /* High/Low water can not be 0 */
3880                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3881                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3882                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3883                         goto out;
3884                 }
3885
3886                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3887                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3888                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3889                         goto out;
3890                 }
3891         }
3892         /* Negotiate the fc mode to use */
3893         ixgbe_fc_autoneg(hw);
3894
3895         /* Disable any previous flow control settings */
3896         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3897         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3898
3899         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3900         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3901
3902         switch (hw->fc.current_mode) {
3903         case ixgbe_fc_none:
3904                 /*
3905                  * If the count of enabled RX Priority Flow control >1,
3906                  * and the TX pause can not be disabled
3907                  */
3908                 nb_rx_en = 0;
3909                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3910                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3911                         if (reg & IXGBE_FCRTH_FCEN)
3912                                 nb_rx_en++;
3913                 }
3914                 if (nb_rx_en > 1)
3915                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3916                 break;
3917         case ixgbe_fc_rx_pause:
3918                 /*
3919                  * Rx Flow control is enabled and Tx Flow control is
3920                  * disabled by software override. Since there really
3921                  * isn't a way to advertise that we are capable of RX
3922                  * Pause ONLY, we will advertise that we support both
3923                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3924                  * disable the adapter's ability to send PAUSE frames.
3925                  */
3926                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3927                 /*
3928                  * If the count of enabled RX Priority Flow control >1,
3929                  * and the TX pause can not be disabled
3930                  */
3931                 nb_rx_en = 0;
3932                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3933                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3934                         if (reg & IXGBE_FCRTH_FCEN)
3935                                 nb_rx_en++;
3936                 }
3937                 if (nb_rx_en > 1)
3938                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3939                 break;
3940         case ixgbe_fc_tx_pause:
3941                 /*
3942                  * Tx Flow control is enabled, and Rx Flow control is
3943                  * disabled by software override.
3944                  */
3945                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3946                 break;
3947         case ixgbe_fc_full:
3948                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3949                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3950                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3951                 break;
3952         default:
3953                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3954                 ret_val = IXGBE_ERR_CONFIG;
3955                 goto out;
3956         }
3957
3958         /* Set 802.3x based flow control settings. */
3959         mflcn_reg |= IXGBE_MFLCN_DPF;
3960         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3961         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3962
3963         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3964         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3965                 hw->fc.high_water[tc_num]) {
3966                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3967                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3968                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3969         } else {
3970                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3971                 /*
3972                  * In order to prevent Tx hangs when the internal Tx
3973                  * switch is enabled we must set the high water mark
3974                  * to the maximum FCRTH value.  This allows the Tx
3975                  * switch to function even under heavy Rx workloads.
3976                  */
3977                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3978         }
3979         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3980
3981         /* Configure pause time (2 TCs per register) */
3982         reg = hw->fc.pause_time * 0x00010001;
3983         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3984                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3985
3986         /* Configure flow control refresh threshold value */
3987         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3988
3989 out:
3990         return ret_val;
3991 }
3992
3993 static int
3994 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3995 {
3996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3998
3999         if (hw->mac.type != ixgbe_mac_82598EB) {
4000                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4001         }
4002         return ret_val;
4003 }
4004
4005 static int
4006 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4007 {
4008         int err;
4009         uint32_t rx_buf_size;
4010         uint32_t max_high_water;
4011         uint8_t tc_num;
4012         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4013         struct ixgbe_hw *hw =
4014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         struct ixgbe_dcb_config *dcb_config =
4016                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4017
4018         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4019                 ixgbe_fc_none,
4020                 ixgbe_fc_rx_pause,
4021                 ixgbe_fc_tx_pause,
4022                 ixgbe_fc_full
4023         };
4024
4025         PMD_INIT_FUNC_TRACE();
4026
4027         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4028         tc_num = map[pfc_conf->priority];
4029         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4030         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4031         /*
4032          * At least reserve one Ethernet frame for watermark
4033          * high_water/low_water in kilo bytes for ixgbe
4034          */
4035         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4036         if ((pfc_conf->fc.high_water > max_high_water) ||
4037             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4038                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4039                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4040                 return -EINVAL;
4041         }
4042
4043         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4044         hw->fc.pause_time = pfc_conf->fc.pause_time;
4045         hw->fc.send_xon = pfc_conf->fc.send_xon;
4046         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4047         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4048
4049         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4050
4051         /* Not negotiated is not an error case */
4052         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4053                 return 0;
4054
4055         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4056         return -EIO;
4057 }
4058
4059 static int
4060 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4061                           struct rte_eth_rss_reta_entry64 *reta_conf,
4062                           uint16_t reta_size)
4063 {
4064         uint16_t i, sp_reta_size;
4065         uint8_t j, mask;
4066         uint32_t reta, r;
4067         uint16_t idx, shift;
4068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069         uint32_t reta_reg;
4070
4071         PMD_INIT_FUNC_TRACE();
4072
4073         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4074                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4075                         "NIC.");
4076                 return -ENOTSUP;
4077         }
4078
4079         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4080         if (reta_size != sp_reta_size) {
4081                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4082                         "(%d) doesn't match the number hardware can supported "
4083                         "(%d)\n", reta_size, sp_reta_size);
4084                 return -EINVAL;
4085         }
4086
4087         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4088                 idx = i / RTE_RETA_GROUP_SIZE;
4089                 shift = i % RTE_RETA_GROUP_SIZE;
4090                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4091                                                 IXGBE_4_BIT_MASK);
4092                 if (!mask)
4093                         continue;
4094                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4095                 if (mask == IXGBE_4_BIT_MASK)
4096                         r = 0;
4097                 else
4098                         r = IXGBE_READ_REG(hw, reta_reg);
4099                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4100                         if (mask & (0x1 << j))
4101                                 reta |= reta_conf[idx].reta[shift + j] <<
4102                                                         (CHAR_BIT * j);
4103                         else
4104                                 reta |= r & (IXGBE_8_BIT_MASK <<
4105                                                 (CHAR_BIT * j));
4106                 }
4107                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4108         }
4109
4110         return 0;
4111 }
4112
4113 static int
4114 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4115                          struct rte_eth_rss_reta_entry64 *reta_conf,
4116                          uint16_t reta_size)
4117 {
4118         uint16_t i, sp_reta_size;
4119         uint8_t j, mask;
4120         uint32_t reta;
4121         uint16_t idx, shift;
4122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123         uint32_t reta_reg;
4124
4125         PMD_INIT_FUNC_TRACE();
4126         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4127         if (reta_size != sp_reta_size) {
4128                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4129                         "(%d) doesn't match the number hardware can supported "
4130                         "(%d)\n", reta_size, sp_reta_size);
4131                 return -EINVAL;
4132         }
4133
4134         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4135                 idx = i / RTE_RETA_GROUP_SIZE;
4136                 shift = i % RTE_RETA_GROUP_SIZE;
4137                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4138                                                 IXGBE_4_BIT_MASK);
4139                 if (!mask)
4140                         continue;
4141
4142                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4143                 reta = IXGBE_READ_REG(hw, reta_reg);
4144                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4145                         if (mask & (0x1 << j))
4146                                 reta_conf[idx].reta[shift + j] =
4147                                         ((reta >> (CHAR_BIT * j)) &
4148                                                 IXGBE_8_BIT_MASK);
4149                 }
4150         }
4151
4152         return 0;
4153 }
4154
4155 static void
4156 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4157                                 uint32_t index, uint32_t pool)
4158 {
4159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4160         uint32_t enable_addr = 1;
4161
4162         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4163 }
4164
4165 static void
4166 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4167 {
4168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4169
4170         ixgbe_clear_rar(hw, index);
4171 }
4172
4173 static void
4174 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4175 {
4176         ixgbe_remove_rar(dev, 0);
4177
4178         ixgbe_add_rar(dev, addr, 0, 0);
4179 }
4180
4181 int
4182 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4183                 struct ether_addr *mac_addr)
4184 {
4185         struct ixgbe_hw *hw;
4186         struct ixgbe_vf_info *vfinfo;
4187         int rar_entry;
4188         uint8_t *new_mac = (uint8_t *)(mac_addr);
4189         struct rte_eth_dev *dev;
4190         struct rte_eth_dev_info dev_info;
4191
4192         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4193
4194         dev = &rte_eth_devices[port];
4195         rte_eth_dev_info_get(port, &dev_info);
4196
4197         if (vf >= dev_info.max_vfs)
4198                 return -EINVAL;
4199
4200         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4202         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4203
4204         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4205                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4206                                 ETHER_ADDR_LEN);
4207                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4208                                 IXGBE_RAH_AV);
4209         }
4210         return -EINVAL;
4211 }
4212
4213 static int
4214 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4215 {
4216         uint32_t hlreg0;
4217         uint32_t maxfrs;
4218         struct ixgbe_hw *hw;
4219         struct rte_eth_dev_info dev_info;
4220         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4221         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4222
4223         ixgbe_dev_info_get(dev, &dev_info);
4224
4225         /* check that mtu is within the allowed range */
4226         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4227                 return -EINVAL;
4228
4229         /* refuse mtu that requires the support of scattered packets when this
4230          * feature has not been enabled before.
4231          */
4232         if (!rx_conf->enable_scatter &&
4233             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4234              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4235                 return -EINVAL;
4236
4237         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4238         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4239
4240         /* switch to jumbo mode if needed */
4241         if (frame_size > ETHER_MAX_LEN) {
4242                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4243                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4244         } else {
4245                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4246                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4247         }
4248         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4249
4250         /* update max frame size */
4251         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4252
4253         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4254         maxfrs &= 0x0000FFFF;
4255         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4256         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4257
4258         return 0;
4259 }
4260
4261 /*
4262  * Virtual Function operations
4263  */
4264 static void
4265 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4266 {
4267         PMD_INIT_FUNC_TRACE();
4268
4269         /* Clear interrupt mask to stop from interrupts being generated */
4270         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4271
4272         IXGBE_WRITE_FLUSH(hw);
4273 }
4274
4275 static void
4276 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4277 {
4278         PMD_INIT_FUNC_TRACE();
4279
4280         /* VF enable interrupt autoclean */
4281         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4282         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4283         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4284
4285         IXGBE_WRITE_FLUSH(hw);
4286 }
4287
4288 static int
4289 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4290 {
4291         struct rte_eth_conf *conf = &dev->data->dev_conf;
4292         struct ixgbe_adapter *adapter =
4293                         (struct ixgbe_adapter *)dev->data->dev_private;
4294
4295         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4296                      dev->data->port_id);
4297
4298         /*
4299          * VF has no ability to enable/disable HW CRC
4300          * Keep the persistent behavior the same as Host PF
4301          */
4302 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4303         if (!conf->rxmode.hw_strip_crc) {
4304                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4305                 conf->rxmode.hw_strip_crc = 1;
4306         }
4307 #else
4308         if (conf->rxmode.hw_strip_crc) {
4309                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4310                 conf->rxmode.hw_strip_crc = 0;
4311         }
4312 #endif
4313
4314         /*
4315          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4316          * allocation or vector Rx preconditions we will reset it.
4317          */
4318         adapter->rx_bulk_alloc_allowed = true;
4319         adapter->rx_vec_allowed = true;
4320
4321         return 0;
4322 }
4323
4324 static int
4325 ixgbevf_dev_start(struct rte_eth_dev *dev)
4326 {
4327         struct ixgbe_hw *hw =
4328                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329         uint32_t intr_vector = 0;
4330         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4331
4332         int err, mask = 0;
4333
4334         PMD_INIT_FUNC_TRACE();
4335
4336         err = hw->mac.ops.reset_hw(hw);
4337         if (err) {
4338                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4339                 return err;
4340         }
4341         hw->mac.get_link_status = true;
4342
4343         /* negotiate mailbox API version to use with the PF. */
4344         ixgbevf_negotiate_api(hw);
4345
4346         ixgbevf_dev_tx_init(dev);
4347
4348         /* This can fail when allocating mbufs for descriptor rings */
4349         err = ixgbevf_dev_rx_init(dev);
4350         if (err) {
4351                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4352                 ixgbe_dev_clear_queues(dev);
4353                 return err;
4354         }
4355
4356         /* Set vfta */
4357         ixgbevf_set_vfta_all(dev, 1);
4358
4359         /* Set HW strip */
4360         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4361                 ETH_VLAN_EXTEND_MASK;
4362         ixgbevf_vlan_offload_set(dev, mask);
4363
4364         ixgbevf_dev_rxtx_start(dev);
4365
4366         /* check and configure queue intr-vector mapping */
4367         if (rte_intr_cap_multiple(intr_handle) &&
4368             dev->data->dev_conf.intr_conf.rxq != 0) {
4369                 intr_vector = dev->data->nb_rx_queues;
4370                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4371                         return -1;
4372         }
4373
4374         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4375                 intr_handle->intr_vec =
4376                         rte_zmalloc("intr_vec",
4377                                     dev->data->nb_rx_queues * sizeof(int), 0);
4378                 if (intr_handle->intr_vec == NULL) {
4379                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4380                                      " intr_vec\n", dev->data->nb_rx_queues);
4381                         return -ENOMEM;
4382                 }
4383         }
4384         ixgbevf_configure_msix(dev);
4385
4386         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
4387          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
4388          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
4389          * is not cleared, it will fail when following rte_intr_enable( ) tries
4390          * to map Rx queue interrupt to other VFIO vectors.
4391          * So clear uio/vfio intr/evevnfd first to avoid failure.
4392          */
4393         rte_intr_disable(intr_handle);
4394
4395         rte_intr_enable(intr_handle);
4396
4397         /* Re-enable interrupt for VF */
4398         ixgbevf_intr_enable(hw);
4399
4400         return 0;
4401 }
4402
4403 static void
4404 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4405 {
4406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4408
4409         PMD_INIT_FUNC_TRACE();
4410
4411         ixgbevf_intr_disable(hw);
4412
4413         hw->adapter_stopped = 1;
4414         ixgbe_stop_adapter(hw);
4415
4416         /*
4417           * Clear what we set, but we still keep shadow_vfta to
4418           * restore after device starts
4419           */
4420         ixgbevf_set_vfta_all(dev, 0);
4421
4422         /* Clear stored conf */
4423         dev->data->scattered_rx = 0;
4424
4425         ixgbe_dev_clear_queues(dev);
4426
4427         /* Clean datapath event and queue/vec mapping */
4428         rte_intr_efd_disable(intr_handle);
4429         if (intr_handle->intr_vec != NULL) {
4430                 rte_free(intr_handle->intr_vec);
4431                 intr_handle->intr_vec = NULL;
4432         }
4433 }
4434
4435 static void
4436 ixgbevf_dev_close(struct rte_eth_dev *dev)
4437 {
4438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439
4440         PMD_INIT_FUNC_TRACE();
4441
4442         ixgbe_reset_hw(hw);
4443
4444         ixgbevf_dev_stop(dev);
4445
4446         ixgbe_dev_free_queues(dev);
4447
4448         /**
4449          * Remove the VF MAC address ro ensure
4450          * that the VF traffic goes to the PF
4451          * after stop, close and detach of the VF
4452          **/
4453         ixgbevf_remove_mac_addr(dev, 0);
4454 }
4455
4456 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4457 {
4458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459         struct ixgbe_vfta *shadow_vfta =
4460                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4461         int i = 0, j = 0, vfta = 0, mask = 1;
4462
4463         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4464                 vfta = shadow_vfta->vfta[i];
4465                 if (vfta) {
4466                         mask = 1;
4467                         for (j = 0; j < 32; j++) {
4468                                 if (vfta & mask)
4469                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4470                                                        on, false);
4471                                 mask <<= 1;
4472                         }
4473                 }
4474         }
4475
4476 }
4477
4478 static int
4479 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4480 {
4481         struct ixgbe_hw *hw =
4482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483         struct ixgbe_vfta *shadow_vfta =
4484                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4485         uint32_t vid_idx = 0;
4486         uint32_t vid_bit = 0;
4487         int ret = 0;
4488
4489         PMD_INIT_FUNC_TRACE();
4490
4491         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4492         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4493         if (ret) {
4494                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4495                 return ret;
4496         }
4497         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4498         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4499
4500         /* Save what we set and retore it after device reset */
4501         if (on)
4502                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4503         else
4504                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4505
4506         return 0;
4507 }
4508
4509 static void
4510 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4511 {
4512         struct ixgbe_hw *hw =
4513                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514         uint32_t ctrl;
4515
4516         PMD_INIT_FUNC_TRACE();
4517
4518         if (queue >= hw->mac.max_rx_queues)
4519                 return;
4520
4521         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4522         if (on)
4523                 ctrl |= IXGBE_RXDCTL_VME;
4524         else
4525                 ctrl &= ~IXGBE_RXDCTL_VME;
4526         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4527
4528         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4529 }
4530
4531 static void
4532 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4533 {
4534         struct ixgbe_hw *hw =
4535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536         uint16_t i;
4537         int on = 0;
4538
4539         /* VF function only support hw strip feature, others are not support */
4540         if (mask & ETH_VLAN_STRIP_MASK) {
4541                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4542
4543                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4544                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4545         }
4546 }
4547
4548 static int
4549 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4550 {
4551         uint32_t reg_val;
4552
4553         /* we only need to do this if VMDq is enabled */
4554         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4555         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4556                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4557                 return -1;
4558         }
4559
4560         return 0;
4561 }
4562
4563 static uint32_t
4564 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4565 {
4566         uint32_t vector = 0;
4567
4568         switch (hw->mac.mc_filter_type) {
4569         case 0:   /* use bits [47:36] of the address */
4570                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4571                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4572                 break;
4573         case 1:   /* use bits [46:35] of the address */
4574                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4575                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4576                 break;
4577         case 2:   /* use bits [45:34] of the address */
4578                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4579                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4580                 break;
4581         case 3:   /* use bits [43:32] of the address */
4582                 vector = ((uc_addr->addr_bytes[4]) |
4583                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4584                 break;
4585         default:  /* Invalid mc_filter_type */
4586                 break;
4587         }
4588
4589         /* vector can only be 12-bits or boundary will be exceeded */
4590         vector &= 0xFFF;
4591         return vector;
4592 }
4593
4594 static int
4595 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4596                         uint8_t on)
4597 {
4598         uint32_t vector;
4599         uint32_t uta_idx;
4600         uint32_t reg_val;
4601         uint32_t uta_shift;
4602         uint32_t rc;
4603         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4604         const uint32_t ixgbe_uta_bit_shift = 5;
4605         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4606         const uint32_t bit1 = 0x1;
4607
4608         struct ixgbe_hw *hw =
4609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         struct ixgbe_uta_info *uta_info =
4611                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4612
4613         /* The UTA table only exists on 82599 hardware and newer */
4614         if (hw->mac.type < ixgbe_mac_82599EB)
4615                 return -ENOTSUP;
4616
4617         vector = ixgbe_uta_vector(hw, mac_addr);
4618         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4619         uta_shift = vector & ixgbe_uta_bit_mask;
4620
4621         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4622         if (rc == on)
4623                 return 0;
4624
4625         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4626         if (on) {
4627                 uta_info->uta_in_use++;
4628                 reg_val |= (bit1 << uta_shift);
4629                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4630         } else {
4631                 uta_info->uta_in_use--;
4632                 reg_val &= ~(bit1 << uta_shift);
4633                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4634         }
4635
4636         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4637
4638         if (uta_info->uta_in_use > 0)
4639                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4640                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4641         else
4642                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4643
4644         return 0;
4645 }
4646
4647 static int
4648 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4649 {
4650         int i;
4651         struct ixgbe_hw *hw =
4652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653         struct ixgbe_uta_info *uta_info =
4654                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4655
4656         /* The UTA table only exists on 82599 hardware and newer */
4657         if (hw->mac.type < ixgbe_mac_82599EB)
4658                 return -ENOTSUP;
4659
4660         if (on) {
4661                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4662                         uta_info->uta_shadow[i] = ~0;
4663                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4664                 }
4665         } else {
4666                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4667                         uta_info->uta_shadow[i] = 0;
4668                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4669                 }
4670         }
4671         return 0;
4672
4673 }
4674
4675 uint32_t
4676 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4677 {
4678         uint32_t new_val = orig_val;
4679
4680         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4681                 new_val |= IXGBE_VMOLR_AUPE;
4682         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4683                 new_val |= IXGBE_VMOLR_ROMPE;
4684         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4685                 new_val |= IXGBE_VMOLR_ROPE;
4686         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4687                 new_val |= IXGBE_VMOLR_BAM;
4688         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4689                 new_val |= IXGBE_VMOLR_MPE;
4690
4691         return new_val;
4692 }
4693
4694 static int
4695 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4696                                uint16_t rx_mask, uint8_t on)
4697 {
4698         int val = 0;
4699
4700         struct ixgbe_hw *hw =
4701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4703
4704         if (hw->mac.type == ixgbe_mac_82598EB) {
4705                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4706                              " on 82599 hardware and newer");
4707                 return -ENOTSUP;
4708         }
4709         if (ixgbe_vmdq_mode_check(hw) < 0)
4710                 return -ENOTSUP;
4711
4712         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4713
4714         if (on)
4715                 vmolr |= val;
4716         else
4717                 vmolr &= ~val;
4718
4719         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4720
4721         return 0;
4722 }
4723
4724 static int
4725 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4726 {
4727         uint32_t reg, addr;
4728         uint32_t val;
4729         const uint8_t bit1 = 0x1;
4730
4731         struct ixgbe_hw *hw =
4732                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733
4734         if (ixgbe_vmdq_mode_check(hw) < 0)
4735                 return -ENOTSUP;
4736
4737         if (pool >= ETH_64_POOLS)
4738                 return -EINVAL;
4739
4740         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4741         if (pool >= 32) {
4742                 addr = IXGBE_VFRE(1);
4743                 val = bit1 << (pool - 32);
4744         } else {
4745                 addr = IXGBE_VFRE(0);
4746                 val = bit1 << pool;
4747         }
4748
4749         reg = IXGBE_READ_REG(hw, addr);
4750
4751         if (on)
4752                 reg |= val;
4753         else
4754                 reg &= ~val;
4755
4756         IXGBE_WRITE_REG(hw, addr, reg);
4757
4758         return 0;
4759 }
4760
4761 static int
4762 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4763 {
4764         uint32_t reg, addr;
4765         uint32_t val;
4766         const uint8_t bit1 = 0x1;
4767
4768         struct ixgbe_hw *hw =
4769                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770
4771         if (ixgbe_vmdq_mode_check(hw) < 0)
4772                 return -ENOTSUP;
4773
4774         if (pool >= ETH_64_POOLS)
4775                 return -EINVAL;
4776
4777         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4778         if (pool >= 32) {
4779                 addr = IXGBE_VFTE(1);
4780                 val = bit1 << (pool - 32);
4781         } else {
4782                 addr = IXGBE_VFTE(0);
4783                 val = bit1 << pool;
4784         }
4785
4786         reg = IXGBE_READ_REG(hw, addr);
4787
4788         if (on)
4789                 reg |= val;
4790         else
4791                 reg &= ~val;
4792
4793         IXGBE_WRITE_REG(hw, addr, reg);
4794
4795         return 0;
4796 }
4797
4798 static int
4799 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4800                         uint64_t pool_mask, uint8_t vlan_on)
4801 {
4802         int ret = 0;
4803         uint16_t pool_idx;
4804         struct ixgbe_hw *hw =
4805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4806
4807         if (ixgbe_vmdq_mode_check(hw) < 0)
4808                 return -ENOTSUP;
4809         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4810                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4811                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4812                                                    vlan_on, false);
4813                         if (ret < 0)
4814                                 return ret;
4815                 }
4816         }
4817
4818         return ret;
4819 }
4820
4821 int
4822 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4823 {
4824         struct ixgbe_hw *hw;
4825         struct ixgbe_mac_info *mac;
4826         struct rte_eth_dev *dev;
4827         struct rte_eth_dev_info dev_info;
4828
4829         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4830
4831         dev = &rte_eth_devices[port];
4832         rte_eth_dev_info_get(port, &dev_info);
4833
4834         if (vf >= dev_info.max_vfs)
4835                 return -EINVAL;
4836
4837         if (on > 1)
4838                 return -EINVAL;
4839
4840         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841         mac = &hw->mac;
4842
4843         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4844
4845         return 0;
4846 }
4847
4848 int
4849 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4850 {
4851         struct ixgbe_hw *hw;
4852         struct ixgbe_mac_info *mac;
4853         struct rte_eth_dev *dev;
4854         struct rte_eth_dev_info dev_info;
4855
4856         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4857
4858         dev = &rte_eth_devices[port];
4859         rte_eth_dev_info_get(port, &dev_info);
4860
4861         if (vf >= dev_info.max_vfs)
4862                 return -EINVAL;
4863
4864         if (on > 1)
4865                 return -EINVAL;
4866
4867         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4868         mac = &hw->mac;
4869         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4870
4871         return 0;
4872 }
4873
4874 int
4875 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4876 {
4877         struct ixgbe_hw *hw;
4878         uint32_t ctrl;
4879         struct rte_eth_dev *dev;
4880         struct rte_eth_dev_info dev_info;
4881
4882         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4883
4884         dev = &rte_eth_devices[port];
4885         rte_eth_dev_info_get(port, &dev_info);
4886
4887         if (vf >= dev_info.max_vfs)
4888                 return -EINVAL;
4889
4890         if (vlan_id > 4095)
4891                 return -EINVAL;
4892
4893         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4895         if (vlan_id) {
4896                 ctrl = vlan_id;
4897                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4898         } else {
4899                 ctrl = 0;
4900         }
4901
4902         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4903
4904         return 0;
4905 }
4906
4907 int
4908 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4909 {
4910         struct ixgbe_hw *hw;
4911         uint32_t ctrl;
4912         struct rte_eth_dev *dev;
4913
4914         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4915
4916         dev = &rte_eth_devices[port];
4917
4918         if (on > 1)
4919                 return -EINVAL;
4920
4921         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4923         /* enable or disable VMDQ loopback */
4924         if (on)
4925                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4926         else
4927                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4928
4929         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4930
4931         return 0;
4932 }
4933
4934 int
4935 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4936 {
4937         struct ixgbe_hw *hw;
4938         uint32_t reg_value;
4939         int i;
4940         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4941         struct rte_eth_dev *dev;
4942
4943         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4944
4945         dev = &rte_eth_devices[port];
4946
4947         if (on > 1)
4948                 return -EINVAL;
4949
4950         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         for (i = 0; i <= num_queues; i++) {
4952                 reg_value = IXGBE_QDE_WRITE |
4953                                 (i << IXGBE_QDE_IDX_SHIFT) |
4954                                 (on & IXGBE_QDE_ENABLE);
4955                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4956         }
4957
4958         return 0;
4959 }
4960
4961 int
4962 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4963 {
4964         struct ixgbe_hw *hw;
4965         uint32_t reg_value;
4966         struct rte_eth_dev *dev;
4967         struct rte_eth_dev_info dev_info;
4968
4969         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4970
4971         dev = &rte_eth_devices[port];
4972         rte_eth_dev_info_get(port, &dev_info);
4973
4974         /* only support VF's 0 to 63 */
4975         if ((vf >= dev_info.max_vfs) || (vf > 63))
4976                 return -EINVAL;
4977
4978         if (on > 1)
4979                 return -EINVAL;
4980
4981         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4983         if (on)
4984                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4985         else
4986                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4987
4988         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4989
4990         return 0;
4991 }
4992
4993 int
4994 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4995 {
4996         struct rte_eth_dev *dev;
4997         struct rte_eth_dev_info dev_info;
4998         uint16_t queues_per_pool;
4999         uint32_t q;
5000
5001         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5002
5003         dev = &rte_eth_devices[port];
5004         rte_eth_dev_info_get(port, &dev_info);
5005
5006         if (vf >= dev_info.max_vfs)
5007                 return -EINVAL;
5008
5009         if (on > 1)
5010                 return -EINVAL;
5011
5012         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5013
5014         /* The PF has 128 queue pairs and in SRIOV configuration
5015          * those queues will be assigned to VF's, so RXDCTL
5016          * registers will be dealing with queues which will be
5017          * assigned to VF's.
5018          * Let's say we have SRIOV configured with 31 VF's then the
5019          * first 124 queues 0-123 will be allocated to VF's and only
5020          * the last 4 queues 123-127 will be assigned to the PF.
5021          */
5022
5023         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5024
5025         for (q = 0; q < queues_per_pool; q++)
5026                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5027                                 q + vf * queues_per_pool, on);
5028         return 0;
5029 }
5030
5031 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5032 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5033 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5034 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5035 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5036         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5037         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5038
5039 static int
5040 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5041                         struct rte_eth_mirror_conf *mirror_conf,
5042                         uint8_t rule_id, uint8_t on)
5043 {
5044         uint32_t mr_ctl, vlvf;
5045         uint32_t mp_lsb = 0;
5046         uint32_t mv_msb = 0;
5047         uint32_t mv_lsb = 0;
5048         uint32_t mp_msb = 0;
5049         uint8_t i = 0;
5050         int reg_index = 0;
5051         uint64_t vlan_mask = 0;
5052
5053         const uint8_t pool_mask_offset = 32;
5054         const uint8_t vlan_mask_offset = 32;
5055         const uint8_t dst_pool_offset = 8;
5056         const uint8_t rule_mr_offset  = 4;
5057         const uint8_t mirror_rule_mask = 0x0F;
5058
5059         struct ixgbe_mirror_info *mr_info =
5060                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5061         struct ixgbe_hw *hw =
5062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063         uint8_t mirror_type = 0;
5064
5065         if (ixgbe_vmdq_mode_check(hw) < 0)
5066                 return -ENOTSUP;
5067
5068         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5069                 return -EINVAL;
5070
5071         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5072                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5073                         mirror_conf->rule_type);
5074                 return -EINVAL;
5075         }
5076
5077         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5078                 mirror_type |= IXGBE_MRCTL_VLME;
5079                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5080                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5081                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5082                                 /* search vlan id related pool vlan filter index */
5083                                 reg_index = ixgbe_find_vlvf_slot(hw,
5084                                                  mirror_conf->vlan.vlan_id[i],
5085                                                  false);
5086                                 if (reg_index < 0)
5087                                         return -EINVAL;
5088                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5089                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5090                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5091                                       mirror_conf->vlan.vlan_id[i]))
5092                                         vlan_mask |= (1ULL << reg_index);
5093                                 else
5094                                         return -EINVAL;
5095                         }
5096                 }
5097
5098                 if (on) {
5099                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5100                         mv_msb = vlan_mask >> vlan_mask_offset;
5101
5102                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5103                                                 mirror_conf->vlan.vlan_mask;
5104                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5105                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5106                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5107                                                 mirror_conf->vlan.vlan_id[i];
5108                         }
5109                 } else {
5110                         mv_lsb = 0;
5111                         mv_msb = 0;
5112                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5113                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5114                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5115                 }
5116         }
5117
5118         /*
5119          * if enable pool mirror, write related pool mask register,if disable
5120          * pool mirror, clear PFMRVM register
5121          */
5122         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5123                 mirror_type |= IXGBE_MRCTL_VPME;
5124                 if (on) {
5125                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5126                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5127                         mr_info->mr_conf[rule_id].pool_mask =
5128                                         mirror_conf->pool_mask;
5129
5130                 } else {
5131                         mp_lsb = 0;
5132                         mp_msb = 0;
5133                         mr_info->mr_conf[rule_id].pool_mask = 0;
5134                 }
5135         }
5136         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5137                 mirror_type |= IXGBE_MRCTL_UPME;
5138         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5139                 mirror_type |= IXGBE_MRCTL_DPME;
5140
5141         /* read  mirror control register and recalculate it */
5142         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5143
5144         if (on) {
5145                 mr_ctl |= mirror_type;
5146                 mr_ctl &= mirror_rule_mask;
5147                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5148         } else
5149                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5150
5151         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5152         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5153
5154         /* write mirrror control  register */
5155         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5156
5157         /* write pool mirrror control  register */
5158         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5159                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5160                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5161                                 mp_msb);
5162         }
5163         /* write VLAN mirrror control  register */
5164         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5165                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5166                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5167                                 mv_msb);
5168         }
5169
5170         return 0;
5171 }
5172
5173 static int
5174 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5175 {
5176         int mr_ctl = 0;
5177         uint32_t lsb_val = 0;
5178         uint32_t msb_val = 0;
5179         const uint8_t rule_mr_offset = 4;
5180
5181         struct ixgbe_hw *hw =
5182                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183         struct ixgbe_mirror_info *mr_info =
5184                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5185
5186         if (ixgbe_vmdq_mode_check(hw) < 0)
5187                 return -ENOTSUP;
5188
5189         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5190                 return -EINVAL;
5191
5192         memset(&mr_info->mr_conf[rule_id], 0,
5193                 sizeof(struct rte_eth_mirror_conf));
5194
5195         /* clear PFVMCTL register */
5196         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5197
5198         /* clear pool mask register */
5199         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5200         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5201
5202         /* clear vlan mask register */
5203         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5204         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5205
5206         return 0;
5207 }
5208
5209 static int
5210 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5211 {
5212         uint32_t mask;
5213         struct ixgbe_hw *hw =
5214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215
5216         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5217         mask |= (1 << IXGBE_MISC_VEC_ID);
5218         RTE_SET_USED(queue_id);
5219         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5220
5221         rte_intr_enable(&dev->pci_dev->intr_handle);
5222
5223         return 0;
5224 }
5225
5226 static int
5227 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5228 {
5229         uint32_t mask;
5230         struct ixgbe_hw *hw =
5231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5232
5233         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5234         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5235         RTE_SET_USED(queue_id);
5236         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5237
5238         return 0;
5239 }
5240
5241 static int
5242 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5243 {
5244         uint32_t mask;
5245         struct ixgbe_hw *hw =
5246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247         struct ixgbe_interrupt *intr =
5248                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5249
5250         if (queue_id < 16) {
5251                 ixgbe_disable_intr(hw);
5252                 intr->mask |= (1 << queue_id);
5253                 ixgbe_enable_intr(dev);
5254         } else if (queue_id < 32) {
5255                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5256                 mask &= (1 << queue_id);
5257                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5258         } else if (queue_id < 64) {
5259                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5260                 mask &= (1 << (queue_id - 32));
5261                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5262         }
5263         rte_intr_enable(&dev->pci_dev->intr_handle);
5264
5265         return 0;
5266 }
5267
5268 static int
5269 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5270 {
5271         uint32_t mask;
5272         struct ixgbe_hw *hw =
5273                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274         struct ixgbe_interrupt *intr =
5275                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5276
5277         if (queue_id < 16) {
5278                 ixgbe_disable_intr(hw);
5279                 intr->mask &= ~(1 << queue_id);
5280                 ixgbe_enable_intr(dev);
5281         } else if (queue_id < 32) {
5282                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5283                 mask &= ~(1 << queue_id);
5284                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5285         } else if (queue_id < 64) {
5286                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5287                 mask &= ~(1 << (queue_id - 32));
5288                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5289         }
5290
5291         return 0;
5292 }
5293
5294 static void
5295 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5296                      uint8_t queue, uint8_t msix_vector)
5297 {
5298         uint32_t tmp, idx;
5299
5300         if (direction == -1) {
5301                 /* other causes */
5302                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5303                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5304                 tmp &= ~0xFF;
5305                 tmp |= msix_vector;
5306                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5307         } else {
5308                 /* rx or tx cause */
5309                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5310                 idx = ((16 * (queue & 1)) + (8 * direction));
5311                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5312                 tmp &= ~(0xFF << idx);
5313                 tmp |= (msix_vector << idx);
5314                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5315         }
5316 }
5317
5318 /**
5319  * set the IVAR registers, mapping interrupt causes to vectors
5320  * @param hw
5321  *  pointer to ixgbe_hw struct
5322  * @direction
5323  *  0 for Rx, 1 for Tx, -1 for other causes
5324  * @queue
5325  *  queue to map the corresponding interrupt to
5326  * @msix_vector
5327  *  the vector to map to the corresponding queue
5328  */
5329 static void
5330 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5331                    uint8_t queue, uint8_t msix_vector)
5332 {
5333         uint32_t tmp, idx;
5334
5335         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5336         if (hw->mac.type == ixgbe_mac_82598EB) {
5337                 if (direction == -1)
5338                         direction = 0;
5339                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5340                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5341                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5342                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5343                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5344         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5345                         (hw->mac.type == ixgbe_mac_X540) ||
5346                         (hw->mac.type == ixgbe_mac_X550)) {
5347                 if (direction == -1) {
5348                         /* other causes */
5349                         idx = ((queue & 1) * 8);
5350                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5351                         tmp &= ~(0xFF << idx);
5352                         tmp |= (msix_vector << idx);
5353                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5354                 } else {
5355                         /* rx or tx causes */
5356                         idx = ((16 * (queue & 1)) + (8 * direction));
5357                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5358                         tmp &= ~(0xFF << idx);
5359                         tmp |= (msix_vector << idx);
5360                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5361                 }
5362         }
5363 }
5364
5365 static void
5366 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5367 {
5368         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5369         struct ixgbe_hw *hw =
5370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371         uint32_t q_idx;
5372         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5373
5374         /* Configure VF other cause ivar */
5375         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5376
5377         /* won't configure msix register if no mapping is done
5378          * between intr vector and event fd.
5379          */
5380         if (!rte_intr_dp_is_en(intr_handle))
5381                 return;
5382
5383         /* Configure all RX queues of VF */
5384         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5385                 /* Force all queue use vector 0,
5386                  * as IXGBE_VF_MAXMSIVECOTR = 1
5387                  */
5388                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5389                 intr_handle->intr_vec[q_idx] = vector_idx;
5390         }
5391 }
5392
5393 /**
5394  * Sets up the hardware to properly generate MSI-X interrupts
5395  * @hw
5396  *  board private structure
5397  */
5398 static void
5399 ixgbe_configure_msix(struct rte_eth_dev *dev)
5400 {
5401         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5402         struct ixgbe_hw *hw =
5403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5405         uint32_t vec = IXGBE_MISC_VEC_ID;
5406         uint32_t mask;
5407         uint32_t gpie;
5408
5409         /* won't configure msix register if no mapping is done
5410          * between intr vector and event fd
5411          */
5412         if (!rte_intr_dp_is_en(intr_handle))
5413                 return;
5414
5415         if (rte_intr_allow_others(intr_handle))
5416                 vec = base = IXGBE_RX_VEC_START;
5417
5418         /* setup GPIE for MSI-x mode */
5419         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5420         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5421                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5422         /* auto clearing and auto setting corresponding bits in EIMS
5423          * when MSI-X interrupt is triggered
5424          */
5425         if (hw->mac.type == ixgbe_mac_82598EB) {
5426                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5427         } else {
5428                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5429                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5430         }
5431         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5432
5433         /* Populate the IVAR table and set the ITR values to the
5434          * corresponding register.
5435          */
5436         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5437              queue_id++) {
5438                 /* by default, 1:1 mapping */
5439                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5440                 intr_handle->intr_vec[queue_id] = vec;
5441                 if (vec < base + intr_handle->nb_efd - 1)
5442                         vec++;
5443         }
5444
5445         switch (hw->mac.type) {
5446         case ixgbe_mac_82598EB:
5447                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5448                                    IXGBE_MISC_VEC_ID);
5449                 break;
5450         case ixgbe_mac_82599EB:
5451         case ixgbe_mac_X540:
5452         case ixgbe_mac_X550:
5453                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5454                 break;
5455         default:
5456                 break;
5457         }
5458         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5459                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5460
5461         /* set up to autoclear timer, and the vectors */
5462         mask = IXGBE_EIMS_ENABLE_MASK;
5463         mask &= ~(IXGBE_EIMS_OTHER |
5464                   IXGBE_EIMS_MAILBOX |
5465                   IXGBE_EIMS_LSC);
5466
5467         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5468 }
5469
5470 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5471         uint16_t queue_idx, uint16_t tx_rate)
5472 {
5473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         uint32_t rf_dec, rf_int;
5475         uint32_t bcnrc_val;
5476         uint16_t link_speed = dev->data->dev_link.link_speed;
5477
5478         if (queue_idx >= hw->mac.max_tx_queues)
5479                 return -EINVAL;
5480
5481         if (tx_rate != 0) {
5482                 /* Calculate the rate factor values to set */
5483                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5484                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5485                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5486
5487                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5488                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5489                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5490                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5491         } else {
5492                 bcnrc_val = 0;
5493         }
5494
5495         /*
5496          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5497          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5498          * set as 0x4.
5499          */
5500         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5501                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5502                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5503                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5504                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5505         else
5506                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5507                         IXGBE_MMW_SIZE_DEFAULT);
5508
5509         /* Set RTTBCNRC of queue X */
5510         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5511         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5512         IXGBE_WRITE_FLUSH(hw);
5513
5514         return 0;
5515 }
5516
5517 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5518         uint16_t tx_rate, uint64_t q_msk)
5519 {
5520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521         struct ixgbe_vf_info *vfinfo =
5522                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5523         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5524         uint32_t queue_stride =
5525                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5526         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5527         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5528         uint16_t total_rate = 0;
5529
5530         if (queue_end >= hw->mac.max_tx_queues)
5531                 return -EINVAL;
5532
5533         if (vfinfo != NULL) {
5534                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5535                         if (vf_idx == vf)
5536                                 continue;
5537                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5538                                 idx++)
5539                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5540                 }
5541         } else
5542                 return -EINVAL;
5543
5544         /* Store tx_rate for this vf. */
5545         for (idx = 0; idx < nb_q_per_pool; idx++) {
5546                 if (((uint64_t)0x1 << idx) & q_msk) {
5547                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5548                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5549                         total_rate += tx_rate;
5550                 }
5551         }
5552
5553         if (total_rate > dev->data->dev_link.link_speed) {
5554                 /*
5555                  * Reset stored TX rate of the VF if it causes exceed
5556                  * link speed.
5557                  */
5558                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5559                 return -EINVAL;
5560         }
5561
5562         /* Set RTTBCNRC of each queue/pool for vf X  */
5563         for (; queue_idx <= queue_end; queue_idx++) {
5564                 if (0x1 & q_msk)
5565                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5566                 q_msk = q_msk >> 1;
5567         }
5568
5569         return 0;
5570 }
5571
5572 static void
5573 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5574                      __attribute__((unused)) uint32_t index,
5575                      __attribute__((unused)) uint32_t pool)
5576 {
5577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5578         int diag;
5579
5580         /*
5581          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5582          * operation. Trap this case to avoid exhausting the [very limited]
5583          * set of PF resources used to store VF MAC addresses.
5584          */
5585         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5586                 return;
5587         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5588         if (diag == 0)
5589                 return;
5590         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5591 }
5592
5593 static void
5594 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5595 {
5596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5597         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5598         struct ether_addr *mac_addr;
5599         uint32_t i;
5600         int diag;
5601
5602         /*
5603          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5604          * not support the deletion of a given MAC address.
5605          * Instead, it imposes to delete all MAC addresses, then to add again
5606          * all MAC addresses with the exception of the one to be deleted.
5607          */
5608         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5609
5610         /*
5611          * Add again all MAC addresses, with the exception of the deleted one
5612          * and of the permanent MAC address.
5613          */
5614         for (i = 0, mac_addr = dev->data->mac_addrs;
5615              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5616                 /* Skip the deleted MAC address */
5617                 if (i == index)
5618                         continue;
5619                 /* Skip NULL MAC addresses */
5620                 if (is_zero_ether_addr(mac_addr))
5621                         continue;
5622                 /* Skip the permanent MAC address */
5623                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5624                         continue;
5625                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5626                 if (diag != 0)
5627                         PMD_DRV_LOG(ERR,
5628                                     "Adding again MAC address "
5629                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5630                                     "diag=%d",
5631                                     mac_addr->addr_bytes[0],
5632                                     mac_addr->addr_bytes[1],
5633                                     mac_addr->addr_bytes[2],
5634                                     mac_addr->addr_bytes[3],
5635                                     mac_addr->addr_bytes[4],
5636                                     mac_addr->addr_bytes[5],
5637                                     diag);
5638         }
5639 }
5640
5641 static void
5642 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5643 {
5644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5645
5646         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5647 }
5648
5649 #define MAC_TYPE_FILTER_SUP(type)    do {\
5650         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5651                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5652                 (type) != ixgbe_mac_X550EM_a)\
5653                 return -ENOTSUP;\
5654 } while (0)
5655
5656 static int
5657 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5658                         struct rte_eth_syn_filter *filter,
5659                         bool add)
5660 {
5661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         uint32_t synqf;
5663
5664         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5665                 return -EINVAL;
5666
5667         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5668
5669         if (add) {
5670                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5671                         return -EINVAL;
5672                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5673                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5674
5675                 if (filter->hig_pri)
5676                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5677                 else
5678                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5679         } else {
5680                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5681                         return -ENOENT;
5682                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5683         }
5684         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5685         IXGBE_WRITE_FLUSH(hw);
5686         return 0;
5687 }
5688
5689 static int
5690 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5691                         struct rte_eth_syn_filter *filter)
5692 {
5693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5694         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5695
5696         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5697                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5698                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5699                 return 0;
5700         }
5701         return -ENOENT;
5702 }
5703
5704 static int
5705 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5706                         enum rte_filter_op filter_op,
5707                         void *arg)
5708 {
5709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5710         int ret;
5711
5712         MAC_TYPE_FILTER_SUP(hw->mac.type);
5713
5714         if (filter_op == RTE_ETH_FILTER_NOP)
5715                 return 0;
5716
5717         if (arg == NULL) {
5718                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5719                             filter_op);
5720                 return -EINVAL;
5721         }
5722
5723         switch (filter_op) {
5724         case RTE_ETH_FILTER_ADD:
5725                 ret = ixgbe_syn_filter_set(dev,
5726                                 (struct rte_eth_syn_filter *)arg,
5727                                 TRUE);
5728                 break;
5729         case RTE_ETH_FILTER_DELETE:
5730                 ret = ixgbe_syn_filter_set(dev,
5731                                 (struct rte_eth_syn_filter *)arg,
5732                                 FALSE);
5733                 break;
5734         case RTE_ETH_FILTER_GET:
5735                 ret = ixgbe_syn_filter_get(dev,
5736                                 (struct rte_eth_syn_filter *)arg);
5737                 break;
5738         default:
5739                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5740                 ret = -EINVAL;
5741                 break;
5742         }
5743
5744         return ret;
5745 }
5746
5747
5748 static inline enum ixgbe_5tuple_protocol
5749 convert_protocol_type(uint8_t protocol_value)
5750 {
5751         if (protocol_value == IPPROTO_TCP)
5752                 return IXGBE_FILTER_PROTOCOL_TCP;
5753         else if (protocol_value == IPPROTO_UDP)
5754                 return IXGBE_FILTER_PROTOCOL_UDP;
5755         else if (protocol_value == IPPROTO_SCTP)
5756                 return IXGBE_FILTER_PROTOCOL_SCTP;
5757         else
5758                 return IXGBE_FILTER_PROTOCOL_NONE;
5759 }
5760
5761 /*
5762  * add a 5tuple filter
5763  *
5764  * @param
5765  * dev: Pointer to struct rte_eth_dev.
5766  * index: the index the filter allocates.
5767  * filter: ponter to the filter that will be added.
5768  * rx_queue: the queue id the filter assigned to.
5769  *
5770  * @return
5771  *    - On success, zero.
5772  *    - On failure, a negative value.
5773  */
5774 static int
5775 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5776                         struct ixgbe_5tuple_filter *filter)
5777 {
5778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         struct ixgbe_filter_info *filter_info =
5780                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5781         int i, idx, shift;
5782         uint32_t ftqf, sdpqf;
5783         uint32_t l34timir = 0;
5784         uint8_t mask = 0xff;
5785
5786         /*
5787          * look for an unused 5tuple filter index,
5788          * and insert the filter to list.
5789          */
5790         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5791                 idx = i / (sizeof(uint32_t) * NBBY);
5792                 shift = i % (sizeof(uint32_t) * NBBY);
5793                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5794                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5795                         filter->index = i;
5796                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5797                                           filter,
5798                                           entries);
5799                         break;
5800                 }
5801         }
5802         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5803                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5804                 return -ENOSYS;
5805         }
5806
5807         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5808                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5809         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5810
5811         ftqf = (uint32_t)(filter->filter_info.proto &
5812                 IXGBE_FTQF_PROTOCOL_MASK);
5813         ftqf |= (uint32_t)((filter->filter_info.priority &
5814                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5815         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5816                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5817         if (filter->filter_info.dst_ip_mask == 0)
5818                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5819         if (filter->filter_info.src_port_mask == 0)
5820                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5821         if (filter->filter_info.dst_port_mask == 0)
5822                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5823         if (filter->filter_info.proto_mask == 0)
5824                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5825         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5826         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5827         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5828
5829         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5830         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5831         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5832         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5833
5834         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5835         l34timir |= (uint32_t)(filter->queue <<
5836                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5837         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5838         return 0;
5839 }
5840
5841 /*
5842  * remove a 5tuple filter
5843  *
5844  * @param
5845  * dev: Pointer to struct rte_eth_dev.
5846  * filter: the pointer of the filter will be removed.
5847  */
5848 static void
5849 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5850                         struct ixgbe_5tuple_filter *filter)
5851 {
5852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5853         struct ixgbe_filter_info *filter_info =
5854                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5855         uint16_t index = filter->index;
5856
5857         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5858                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5859         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5860         rte_free(filter);
5861
5862         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5863         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5864         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5865         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5866         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5867 }
5868
5869 static int
5870 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5871 {
5872         struct ixgbe_hw *hw;
5873         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5874         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5875
5876         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5877
5878         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5879                 return -EINVAL;
5880
5881         /* refuse mtu that requires the support of scattered packets when this
5882          * feature has not been enabled before.
5883          */
5884         if (!rx_conf->enable_scatter &&
5885             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5886              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5887                 return -EINVAL;
5888
5889         /*
5890          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5891          * request of the version 2.0 of the mailbox API.
5892          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5893          * of the mailbox API.
5894          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5895          * prior to 3.11.33 which contains the following change:
5896          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5897          */
5898         ixgbevf_rlpml_set_vf(hw, max_frame);
5899
5900         /* update max frame size */
5901         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5902         return 0;
5903 }
5904
5905 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5906         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5907                 return -ENOTSUP;\
5908 } while (0)
5909
5910 static inline struct ixgbe_5tuple_filter *
5911 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5912                         struct ixgbe_5tuple_filter_info *key)
5913 {
5914         struct ixgbe_5tuple_filter *it;
5915
5916         TAILQ_FOREACH(it, filter_list, entries) {
5917                 if (memcmp(key, &it->filter_info,
5918                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5919                         return it;
5920                 }
5921         }
5922         return NULL;
5923 }
5924
5925 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5926 static inline int
5927 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5928                         struct ixgbe_5tuple_filter_info *filter_info)
5929 {
5930         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5931                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5932                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5933                 return -EINVAL;
5934
5935         switch (filter->dst_ip_mask) {
5936         case UINT32_MAX:
5937                 filter_info->dst_ip_mask = 0;
5938                 filter_info->dst_ip = filter->dst_ip;
5939                 break;
5940         case 0:
5941                 filter_info->dst_ip_mask = 1;
5942                 break;
5943         default:
5944                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5945                 return -EINVAL;
5946         }
5947
5948         switch (filter->src_ip_mask) {
5949         case UINT32_MAX:
5950                 filter_info->src_ip_mask = 0;
5951                 filter_info->src_ip = filter->src_ip;
5952                 break;
5953         case 0:
5954                 filter_info->src_ip_mask = 1;
5955                 break;
5956         default:
5957                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5958                 return -EINVAL;
5959         }
5960
5961         switch (filter->dst_port_mask) {
5962         case UINT16_MAX:
5963                 filter_info->dst_port_mask = 0;
5964                 filter_info->dst_port = filter->dst_port;
5965                 break;
5966         case 0:
5967                 filter_info->dst_port_mask = 1;
5968                 break;
5969         default:
5970                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5971                 return -EINVAL;
5972         }
5973
5974         switch (filter->src_port_mask) {
5975         case UINT16_MAX:
5976                 filter_info->src_port_mask = 0;
5977                 filter_info->src_port = filter->src_port;
5978                 break;
5979         case 0:
5980                 filter_info->src_port_mask = 1;
5981                 break;
5982         default:
5983                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5984                 return -EINVAL;
5985         }
5986
5987         switch (filter->proto_mask) {
5988         case UINT8_MAX:
5989                 filter_info->proto_mask = 0;
5990                 filter_info->proto =
5991                         convert_protocol_type(filter->proto);
5992                 break;
5993         case 0:
5994                 filter_info->proto_mask = 1;
5995                 break;
5996         default:
5997                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5998                 return -EINVAL;
5999         }
6000
6001         filter_info->priority = (uint8_t)filter->priority;
6002         return 0;
6003 }
6004
6005 /*
6006  * add or delete a ntuple filter
6007  *
6008  * @param
6009  * dev: Pointer to struct rte_eth_dev.
6010  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6011  * add: if true, add filter, if false, remove filter
6012  *
6013  * @return
6014  *    - On success, zero.
6015  *    - On failure, a negative value.
6016  */
6017 static int
6018 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6019                         struct rte_eth_ntuple_filter *ntuple_filter,
6020                         bool add)
6021 {
6022         struct ixgbe_filter_info *filter_info =
6023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6024         struct ixgbe_5tuple_filter_info filter_5tuple;
6025         struct ixgbe_5tuple_filter *filter;
6026         int ret;
6027
6028         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6029                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6030                 return -EINVAL;
6031         }
6032
6033         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6034         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6035         if (ret < 0)
6036                 return ret;
6037
6038         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6039                                          &filter_5tuple);
6040         if (filter != NULL && add) {
6041                 PMD_DRV_LOG(ERR, "filter exists.");
6042                 return -EEXIST;
6043         }
6044         if (filter == NULL && !add) {
6045                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6046                 return -ENOENT;
6047         }
6048
6049         if (add) {
6050                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6051                                 sizeof(struct ixgbe_5tuple_filter), 0);
6052                 if (filter == NULL)
6053                         return -ENOMEM;
6054                 (void)rte_memcpy(&filter->filter_info,
6055                                  &filter_5tuple,
6056                                  sizeof(struct ixgbe_5tuple_filter_info));
6057                 filter->queue = ntuple_filter->queue;
6058                 ret = ixgbe_add_5tuple_filter(dev, filter);
6059                 if (ret < 0) {
6060                         rte_free(filter);
6061                         return ret;
6062                 }
6063         } else
6064                 ixgbe_remove_5tuple_filter(dev, filter);
6065
6066         return 0;
6067 }
6068
6069 /*
6070  * get a ntuple filter
6071  *
6072  * @param
6073  * dev: Pointer to struct rte_eth_dev.
6074  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6075  *
6076  * @return
6077  *    - On success, zero.
6078  *    - On failure, a negative value.
6079  */
6080 static int
6081 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6082                         struct rte_eth_ntuple_filter *ntuple_filter)
6083 {
6084         struct ixgbe_filter_info *filter_info =
6085                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6086         struct ixgbe_5tuple_filter_info filter_5tuple;
6087         struct ixgbe_5tuple_filter *filter;
6088         int ret;
6089
6090         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6091                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6092                 return -EINVAL;
6093         }
6094
6095         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6096         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6097         if (ret < 0)
6098                 return ret;
6099
6100         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6101                                          &filter_5tuple);
6102         if (filter == NULL) {
6103                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6104                 return -ENOENT;
6105         }
6106         ntuple_filter->queue = filter->queue;
6107         return 0;
6108 }
6109
6110 /*
6111  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6112  * @dev: pointer to rte_eth_dev structure
6113  * @filter_op:operation will be taken.
6114  * @arg: a pointer to specific structure corresponding to the filter_op
6115  *
6116  * @return
6117  *    - On success, zero.
6118  *    - On failure, a negative value.
6119  */
6120 static int
6121 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6122                                 enum rte_filter_op filter_op,
6123                                 void *arg)
6124 {
6125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126         int ret;
6127
6128         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6129
6130         if (filter_op == RTE_ETH_FILTER_NOP)
6131                 return 0;
6132
6133         if (arg == NULL) {
6134                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6135                             filter_op);
6136                 return -EINVAL;
6137         }
6138
6139         switch (filter_op) {
6140         case RTE_ETH_FILTER_ADD:
6141                 ret = ixgbe_add_del_ntuple_filter(dev,
6142                         (struct rte_eth_ntuple_filter *)arg,
6143                         TRUE);
6144                 break;
6145         case RTE_ETH_FILTER_DELETE:
6146                 ret = ixgbe_add_del_ntuple_filter(dev,
6147                         (struct rte_eth_ntuple_filter *)arg,
6148                         FALSE);
6149                 break;
6150         case RTE_ETH_FILTER_GET:
6151                 ret = ixgbe_get_ntuple_filter(dev,
6152                         (struct rte_eth_ntuple_filter *)arg);
6153                 break;
6154         default:
6155                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6156                 ret = -EINVAL;
6157                 break;
6158         }
6159         return ret;
6160 }
6161
6162 static inline int
6163 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6164                         uint16_t ethertype)
6165 {
6166         int i;
6167
6168         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6169                 if (filter_info->ethertype_filters[i] == ethertype &&
6170                     (filter_info->ethertype_mask & (1 << i)))
6171                         return i;
6172         }
6173         return -1;
6174 }
6175
6176 static inline int
6177 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6178                         uint16_t ethertype)
6179 {
6180         int i;
6181
6182         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6183                 if (!(filter_info->ethertype_mask & (1 << i))) {
6184                         filter_info->ethertype_mask |= 1 << i;
6185                         filter_info->ethertype_filters[i] = ethertype;
6186                         return i;
6187                 }
6188         }
6189         return -1;
6190 }
6191
6192 static inline int
6193 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6194                         uint8_t idx)
6195 {
6196         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6197                 return -1;
6198         filter_info->ethertype_mask &= ~(1 << idx);
6199         filter_info->ethertype_filters[idx] = 0;
6200         return idx;
6201 }
6202
6203 static int
6204 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6205                         struct rte_eth_ethertype_filter *filter,
6206                         bool add)
6207 {
6208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209         struct ixgbe_filter_info *filter_info =
6210                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6211         uint32_t etqf = 0;
6212         uint32_t etqs = 0;
6213         int ret;
6214
6215         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6216                 return -EINVAL;
6217
6218         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6219                 filter->ether_type == ETHER_TYPE_IPv6) {
6220                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6221                         " ethertype filter.", filter->ether_type);
6222                 return -EINVAL;
6223         }
6224
6225         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6226                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6227                 return -EINVAL;
6228         }
6229         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6230                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6231                 return -EINVAL;
6232         }
6233
6234         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6235         if (ret >= 0 && add) {
6236                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6237                             filter->ether_type);
6238                 return -EEXIST;
6239         }
6240         if (ret < 0 && !add) {
6241                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6242                             filter->ether_type);
6243                 return -ENOENT;
6244         }
6245
6246         if (add) {
6247                 ret = ixgbe_ethertype_filter_insert(filter_info,
6248                         filter->ether_type);
6249                 if (ret < 0) {
6250                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6251                         return -ENOSYS;
6252                 }
6253                 etqf = IXGBE_ETQF_FILTER_EN;
6254                 etqf |= (uint32_t)filter->ether_type;
6255                 etqs |= (uint32_t)((filter->queue <<
6256                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6257                                     IXGBE_ETQS_RX_QUEUE);
6258                 etqs |= IXGBE_ETQS_QUEUE_EN;
6259         } else {
6260                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6261                 if (ret < 0)
6262                         return -ENOSYS;
6263         }
6264         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6265         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6266         IXGBE_WRITE_FLUSH(hw);
6267
6268         return 0;
6269 }
6270
6271 static int
6272 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6273                         struct rte_eth_ethertype_filter *filter)
6274 {
6275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6276         struct ixgbe_filter_info *filter_info =
6277                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6278         uint32_t etqf, etqs;
6279         int ret;
6280
6281         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6282         if (ret < 0) {
6283                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6284                             filter->ether_type);
6285                 return -ENOENT;
6286         }
6287
6288         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6289         if (etqf & IXGBE_ETQF_FILTER_EN) {
6290                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6291                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6292                 filter->flags = 0;
6293                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6294                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6295                 return 0;
6296         }
6297         return -ENOENT;
6298 }
6299
6300 /*
6301  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6302  * @dev: pointer to rte_eth_dev structure
6303  * @filter_op:operation will be taken.
6304  * @arg: a pointer to specific structure corresponding to the filter_op
6305  */
6306 static int
6307 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6308                                 enum rte_filter_op filter_op,
6309                                 void *arg)
6310 {
6311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6312         int ret;
6313
6314         MAC_TYPE_FILTER_SUP(hw->mac.type);
6315
6316         if (filter_op == RTE_ETH_FILTER_NOP)
6317                 return 0;
6318
6319         if (arg == NULL) {
6320                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6321                             filter_op);
6322                 return -EINVAL;
6323         }
6324
6325         switch (filter_op) {
6326         case RTE_ETH_FILTER_ADD:
6327                 ret = ixgbe_add_del_ethertype_filter(dev,
6328                         (struct rte_eth_ethertype_filter *)arg,
6329                         TRUE);
6330                 break;
6331         case RTE_ETH_FILTER_DELETE:
6332                 ret = ixgbe_add_del_ethertype_filter(dev,
6333                         (struct rte_eth_ethertype_filter *)arg,
6334                         FALSE);
6335                 break;
6336         case RTE_ETH_FILTER_GET:
6337                 ret = ixgbe_get_ethertype_filter(dev,
6338                         (struct rte_eth_ethertype_filter *)arg);
6339                 break;
6340         default:
6341                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6342                 ret = -EINVAL;
6343                 break;
6344         }
6345         return ret;
6346 }
6347
6348 static int
6349 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6350                      enum rte_filter_type filter_type,
6351                      enum rte_filter_op filter_op,
6352                      void *arg)
6353 {
6354         int ret = -EINVAL;
6355
6356         switch (filter_type) {
6357         case RTE_ETH_FILTER_NTUPLE:
6358                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6359                 break;
6360         case RTE_ETH_FILTER_ETHERTYPE:
6361                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6362                 break;
6363         case RTE_ETH_FILTER_SYN:
6364                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6365                 break;
6366         case RTE_ETH_FILTER_FDIR:
6367                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6368                 break;
6369         case RTE_ETH_FILTER_L2_TUNNEL:
6370                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6371                 break;
6372         default:
6373                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6374                                                         filter_type);
6375                 break;
6376         }
6377
6378         return ret;
6379 }
6380
6381 static u8 *
6382 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6383                         u8 **mc_addr_ptr, u32 *vmdq)
6384 {
6385         u8 *mc_addr;
6386
6387         *vmdq = 0;
6388         mc_addr = *mc_addr_ptr;
6389         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6390         return mc_addr;
6391 }
6392
6393 static int
6394 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6395                           struct ether_addr *mc_addr_set,
6396                           uint32_t nb_mc_addr)
6397 {
6398         struct ixgbe_hw *hw;
6399         u8 *mc_addr_list;
6400
6401         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6402         mc_addr_list = (u8 *)mc_addr_set;
6403         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6404                                          ixgbe_dev_addr_list_itr, TRUE);
6405 }
6406
6407 static uint64_t
6408 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6409 {
6410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6411         uint64_t systime_cycles;
6412
6413         switch (hw->mac.type) {
6414         case ixgbe_mac_X550:
6415         case ixgbe_mac_X550EM_x:
6416         case ixgbe_mac_X550EM_a:
6417                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6418                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6419                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6420                                 * NSEC_PER_SEC;
6421                 break;
6422         default:
6423                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6424                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6425                                 << 32;
6426         }
6427
6428         return systime_cycles;
6429 }
6430
6431 static uint64_t
6432 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6433 {
6434         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435         uint64_t rx_tstamp_cycles;
6436
6437         switch (hw->mac.type) {
6438         case ixgbe_mac_X550:
6439         case ixgbe_mac_X550EM_x:
6440         case ixgbe_mac_X550EM_a:
6441                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6442                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6443                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6444                                 * NSEC_PER_SEC;
6445                 break;
6446         default:
6447                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6448                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6449                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6450                                 << 32;
6451         }
6452
6453         return rx_tstamp_cycles;
6454 }
6455
6456 static uint64_t
6457 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6458 {
6459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6460         uint64_t tx_tstamp_cycles;
6461
6462         switch (hw->mac.type) {
6463         case ixgbe_mac_X550:
6464         case ixgbe_mac_X550EM_x:
6465         case ixgbe_mac_X550EM_a:
6466                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6467                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6468                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6469                                 * NSEC_PER_SEC;
6470                 break;
6471         default:
6472                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6473                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6474                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6475                                 << 32;
6476         }
6477
6478         return tx_tstamp_cycles;
6479 }
6480
6481 static void
6482 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6483 {
6484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6485         struct ixgbe_adapter *adapter =
6486                 (struct ixgbe_adapter *)dev->data->dev_private;
6487         struct rte_eth_link link;
6488         uint32_t incval = 0;
6489         uint32_t shift = 0;
6490
6491         /* Get current link speed. */
6492         memset(&link, 0, sizeof(link));
6493         ixgbe_dev_link_update(dev, 1);
6494         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6495
6496         switch (link.link_speed) {
6497         case ETH_SPEED_NUM_100M:
6498                 incval = IXGBE_INCVAL_100;
6499                 shift = IXGBE_INCVAL_SHIFT_100;
6500                 break;
6501         case ETH_SPEED_NUM_1G:
6502                 incval = IXGBE_INCVAL_1GB;
6503                 shift = IXGBE_INCVAL_SHIFT_1GB;
6504                 break;
6505         case ETH_SPEED_NUM_10G:
6506         default:
6507                 incval = IXGBE_INCVAL_10GB;
6508                 shift = IXGBE_INCVAL_SHIFT_10GB;
6509                 break;
6510         }
6511
6512         switch (hw->mac.type) {
6513         case ixgbe_mac_X550:
6514         case ixgbe_mac_X550EM_x:
6515         case ixgbe_mac_X550EM_a:
6516                 /* Independent of link speed. */
6517                 incval = 1;
6518                 /* Cycles read will be interpreted as ns. */
6519                 shift = 0;
6520                 /* Fall-through */
6521         case ixgbe_mac_X540:
6522                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6523                 break;
6524         case ixgbe_mac_82599EB:
6525                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6526                 shift -= IXGBE_INCVAL_SHIFT_82599;
6527                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6528                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6529                 break;
6530         default:
6531                 /* Not supported. */
6532                 return;
6533         }
6534
6535         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6536         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6537         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6538
6539         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6540         adapter->systime_tc.cc_shift = shift;
6541         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6542
6543         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6544         adapter->rx_tstamp_tc.cc_shift = shift;
6545         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6546
6547         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6548         adapter->tx_tstamp_tc.cc_shift = shift;
6549         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6550 }
6551
6552 static int
6553 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6554 {
6555         struct ixgbe_adapter *adapter =
6556                         (struct ixgbe_adapter *)dev->data->dev_private;
6557
6558         adapter->systime_tc.nsec += delta;
6559         adapter->rx_tstamp_tc.nsec += delta;
6560         adapter->tx_tstamp_tc.nsec += delta;
6561
6562         return 0;
6563 }
6564
6565 static int
6566 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6567 {
6568         uint64_t ns;
6569         struct ixgbe_adapter *adapter =
6570                         (struct ixgbe_adapter *)dev->data->dev_private;
6571
6572         ns = rte_timespec_to_ns(ts);
6573         /* Set the timecounters to a new value. */
6574         adapter->systime_tc.nsec = ns;
6575         adapter->rx_tstamp_tc.nsec = ns;
6576         adapter->tx_tstamp_tc.nsec = ns;
6577
6578         return 0;
6579 }
6580
6581 static int
6582 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6583 {
6584         uint64_t ns, systime_cycles;
6585         struct ixgbe_adapter *adapter =
6586                         (struct ixgbe_adapter *)dev->data->dev_private;
6587
6588         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6589         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6590         *ts = rte_ns_to_timespec(ns);
6591
6592         return 0;
6593 }
6594
6595 static int
6596 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6597 {
6598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6599         uint32_t tsync_ctl;
6600         uint32_t tsauxc;
6601
6602         /* Stop the timesync system time. */
6603         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6604         /* Reset the timesync system time value. */
6605         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6606         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6607
6608         /* Enable system time for platforms where it isn't on by default. */
6609         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6610         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6611         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6612
6613         ixgbe_start_timecounters(dev);
6614
6615         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6616         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6617                         (ETHER_TYPE_1588 |
6618                          IXGBE_ETQF_FILTER_EN |
6619                          IXGBE_ETQF_1588));
6620
6621         /* Enable timestamping of received PTP packets. */
6622         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6623         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6624         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6625
6626         /* Enable timestamping of transmitted PTP packets. */
6627         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6628         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6629         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6630
6631         IXGBE_WRITE_FLUSH(hw);
6632
6633         return 0;
6634 }
6635
6636 static int
6637 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6638 {
6639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6640         uint32_t tsync_ctl;
6641
6642         /* Disable timestamping of transmitted PTP packets. */
6643         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6644         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6645         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6646
6647         /* Disable timestamping of received PTP packets. */
6648         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6649         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6650         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6651
6652         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6653         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6654
6655         /* Stop incrementating the System Time registers. */
6656         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6657
6658         return 0;
6659 }
6660
6661 static int
6662 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6663                                  struct timespec *timestamp,
6664                                  uint32_t flags __rte_unused)
6665 {
6666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667         struct ixgbe_adapter *adapter =
6668                 (struct ixgbe_adapter *)dev->data->dev_private;
6669         uint32_t tsync_rxctl;
6670         uint64_t rx_tstamp_cycles;
6671         uint64_t ns;
6672
6673         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6674         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6675                 return -EINVAL;
6676
6677         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6678         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6679         *timestamp = rte_ns_to_timespec(ns);
6680
6681         return  0;
6682 }
6683
6684 static int
6685 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6686                                  struct timespec *timestamp)
6687 {
6688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         struct ixgbe_adapter *adapter =
6690                 (struct ixgbe_adapter *)dev->data->dev_private;
6691         uint32_t tsync_txctl;
6692         uint64_t tx_tstamp_cycles;
6693         uint64_t ns;
6694
6695         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6696         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6697                 return -EINVAL;
6698
6699         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6700         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6701         *timestamp = rte_ns_to_timespec(ns);
6702
6703         return 0;
6704 }
6705
6706 static int
6707 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6708 {
6709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6710         int count = 0;
6711         int g_ind = 0;
6712         const struct reg_info *reg_group;
6713         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6714                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6715
6716         while ((reg_group = reg_set[g_ind++]))
6717                 count += ixgbe_regs_group_count(reg_group);
6718
6719         return count;
6720 }
6721
6722 static int
6723 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6724 {
6725         int count = 0;
6726         int g_ind = 0;
6727         const struct reg_info *reg_group;
6728
6729         while ((reg_group = ixgbevf_regs[g_ind++]))
6730                 count += ixgbe_regs_group_count(reg_group);
6731
6732         return count;
6733 }
6734
6735 static int
6736 ixgbe_get_regs(struct rte_eth_dev *dev,
6737               struct rte_dev_reg_info *regs)
6738 {
6739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740         uint32_t *data = regs->data;
6741         int g_ind = 0;
6742         int count = 0;
6743         const struct reg_info *reg_group;
6744         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6745                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6746
6747         if (data == NULL) {
6748                 regs->length = ixgbe_get_reg_length(dev);
6749                 regs->width = sizeof(uint32_t);
6750                 return 0;
6751         }
6752
6753         /* Support only full register dump */
6754         if ((regs->length == 0) ||
6755             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6756                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6757                         hw->device_id;
6758                 while ((reg_group = reg_set[g_ind++]))
6759                         count += ixgbe_read_regs_group(dev, &data[count],
6760                                 reg_group);
6761                 return 0;
6762         }
6763
6764         return -ENOTSUP;
6765 }
6766
6767 static int
6768 ixgbevf_get_regs(struct rte_eth_dev *dev,
6769                 struct rte_dev_reg_info *regs)
6770 {
6771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772         uint32_t *data = regs->data;
6773         int g_ind = 0;
6774         int count = 0;
6775         const struct reg_info *reg_group;
6776
6777         if (data == NULL) {
6778                 regs->length = ixgbevf_get_reg_length(dev);
6779                 regs->width = sizeof(uint32_t);
6780                 return 0;
6781         }
6782
6783         /* Support only full register dump */
6784         if ((regs->length == 0) ||
6785             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6786                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6787                         hw->device_id;
6788                 while ((reg_group = ixgbevf_regs[g_ind++]))
6789                         count += ixgbe_read_regs_group(dev, &data[count],
6790                                                       reg_group);
6791                 return 0;
6792         }
6793
6794         return -ENOTSUP;
6795 }
6796
6797 static int
6798 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6799 {
6800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801
6802         /* Return unit is byte count */
6803         return hw->eeprom.word_size * 2;
6804 }
6805
6806 static int
6807 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6808                 struct rte_dev_eeprom_info *in_eeprom)
6809 {
6810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6812         uint16_t *data = in_eeprom->data;
6813         int first, length;
6814
6815         first = in_eeprom->offset >> 1;
6816         length = in_eeprom->length >> 1;
6817         if ((first > hw->eeprom.word_size) ||
6818             ((first + length) > hw->eeprom.word_size))
6819                 return -EINVAL;
6820
6821         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6822
6823         return eeprom->ops.read_buffer(hw, first, length, data);
6824 }
6825
6826 static int
6827 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6828                 struct rte_dev_eeprom_info *in_eeprom)
6829 {
6830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6832         uint16_t *data = in_eeprom->data;
6833         int first, length;
6834
6835         first = in_eeprom->offset >> 1;
6836         length = in_eeprom->length >> 1;
6837         if ((first > hw->eeprom.word_size) ||
6838             ((first + length) > hw->eeprom.word_size))
6839                 return -EINVAL;
6840
6841         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6842
6843         return eeprom->ops.write_buffer(hw,  first, length, data);
6844 }
6845
6846 uint16_t
6847 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6848         switch (mac_type) {
6849         case ixgbe_mac_X550:
6850         case ixgbe_mac_X550EM_x:
6851         case ixgbe_mac_X550EM_a:
6852                 return ETH_RSS_RETA_SIZE_512;
6853         case ixgbe_mac_X550_vf:
6854         case ixgbe_mac_X550EM_x_vf:
6855         case ixgbe_mac_X550EM_a_vf:
6856                 return ETH_RSS_RETA_SIZE_64;
6857         default:
6858                 return ETH_RSS_RETA_SIZE_128;
6859         }
6860 }
6861
6862 uint32_t
6863 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6864         switch (mac_type) {
6865         case ixgbe_mac_X550:
6866         case ixgbe_mac_X550EM_x:
6867         case ixgbe_mac_X550EM_a:
6868                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6869                         return IXGBE_RETA(reta_idx >> 2);
6870                 else
6871                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6872         case ixgbe_mac_X550_vf:
6873         case ixgbe_mac_X550EM_x_vf:
6874         case ixgbe_mac_X550EM_a_vf:
6875                 return IXGBE_VFRETA(reta_idx >> 2);
6876         default:
6877                 return IXGBE_RETA(reta_idx >> 2);
6878         }
6879 }
6880
6881 uint32_t
6882 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6883         switch (mac_type) {
6884         case ixgbe_mac_X550_vf:
6885         case ixgbe_mac_X550EM_x_vf:
6886         case ixgbe_mac_X550EM_a_vf:
6887                 return IXGBE_VFMRQC;
6888         default:
6889                 return IXGBE_MRQC;
6890         }
6891 }
6892
6893 uint32_t
6894 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6895         switch (mac_type) {
6896         case ixgbe_mac_X550_vf:
6897         case ixgbe_mac_X550EM_x_vf:
6898         case ixgbe_mac_X550EM_a_vf:
6899                 return IXGBE_VFRSSRK(i);
6900         default:
6901                 return IXGBE_RSSRK(i);
6902         }
6903 }
6904
6905 bool
6906 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6907         switch (mac_type) {
6908         case ixgbe_mac_82599_vf:
6909         case ixgbe_mac_X540_vf:
6910                 return 0;
6911         default:
6912                 return 1;
6913         }
6914 }
6915
6916 static int
6917 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6918                         struct rte_eth_dcb_info *dcb_info)
6919 {
6920         struct ixgbe_dcb_config *dcb_config =
6921                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6922         struct ixgbe_dcb_tc_config *tc;
6923         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
6924         uint8_t nb_tcs;
6925         uint8_t i, j;
6926
6927         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6928                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6929         else
6930                 dcb_info->nb_tcs = 1;
6931
6932         tc_queue = &dcb_info->tc_queue;
6933         nb_tcs = dcb_info->nb_tcs;
6934
6935         if (dcb_config->vt_mode) { /* vt is enabled*/
6936                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6937                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6938                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6939                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6940                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
6941                         for (j = 0; j < nb_tcs; j++) {
6942                                 tc_queue->tc_rxq[0][j].base = j;
6943                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
6944                                 tc_queue->tc_txq[0][j].base = j;
6945                                 tc_queue->tc_txq[0][j].nb_queue = 1;
6946                         }
6947                 } else {
6948                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6949                                 for (j = 0; j < nb_tcs; j++) {
6950                                         tc_queue->tc_rxq[i][j].base =
6951                                                 i * nb_tcs + j;
6952                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
6953                                         tc_queue->tc_txq[i][j].base =
6954                                                 i * nb_tcs + j;
6955                                         tc_queue->tc_txq[i][j].nb_queue = 1;
6956                                 }
6957                         }
6958                 }
6959         } else { /* vt is disabled*/
6960                 struct rte_eth_dcb_rx_conf *rx_conf =
6961                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6962                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6963                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6964                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6965                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6966                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6967                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6968                         }
6969                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6970                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6971                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6972                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6973                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6974                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6975                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6976                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6977                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6978                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6979                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6980                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6981                         }
6982                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6983                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6984                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6985                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6986                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6987                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6988                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6989                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6990                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6991                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6992                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6993                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6994                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6995                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6996                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6997                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6998                 }
6999         }
7000         for (i = 0; i < dcb_info->nb_tcs; i++) {
7001                 tc = &dcb_config->tc_config[i];
7002                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7003         }
7004         return 0;
7005 }
7006
7007 /* Update e-tag ether type */
7008 static int
7009 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7010                             uint16_t ether_type)
7011 {
7012         uint32_t etag_etype;
7013
7014         if (hw->mac.type != ixgbe_mac_X550 &&
7015             hw->mac.type != ixgbe_mac_X550EM_x &&
7016             hw->mac.type != ixgbe_mac_X550EM_a) {
7017                 return -ENOTSUP;
7018         }
7019
7020         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7021         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7022         etag_etype |= ether_type;
7023         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7024         IXGBE_WRITE_FLUSH(hw);
7025
7026         return 0;
7027 }
7028
7029 /* Config l2 tunnel ether type */
7030 static int
7031 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7032                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7033 {
7034         int ret = 0;
7035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7036
7037         if (l2_tunnel == NULL)
7038                 return -EINVAL;
7039
7040         switch (l2_tunnel->l2_tunnel_type) {
7041         case RTE_L2_TUNNEL_TYPE_E_TAG:
7042                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7043                 break;
7044         default:
7045                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7046                 ret = -EINVAL;
7047                 break;
7048         }
7049
7050         return ret;
7051 }
7052
7053 /* Enable e-tag tunnel */
7054 static int
7055 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7056 {
7057         uint32_t etag_etype;
7058
7059         if (hw->mac.type != ixgbe_mac_X550 &&
7060             hw->mac.type != ixgbe_mac_X550EM_x &&
7061             hw->mac.type != ixgbe_mac_X550EM_a) {
7062                 return -ENOTSUP;
7063         }
7064
7065         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7066         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7067         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7068         IXGBE_WRITE_FLUSH(hw);
7069
7070         return 0;
7071 }
7072
7073 /* Enable l2 tunnel */
7074 static int
7075 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7076                            enum rte_eth_tunnel_type l2_tunnel_type)
7077 {
7078         int ret = 0;
7079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7080
7081         switch (l2_tunnel_type) {
7082         case RTE_L2_TUNNEL_TYPE_E_TAG:
7083                 ret = ixgbe_e_tag_enable(hw);
7084                 break;
7085         default:
7086                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7087                 ret = -EINVAL;
7088                 break;
7089         }
7090
7091         return ret;
7092 }
7093
7094 /* Disable e-tag tunnel */
7095 static int
7096 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7097 {
7098         uint32_t etag_etype;
7099
7100         if (hw->mac.type != ixgbe_mac_X550 &&
7101             hw->mac.type != ixgbe_mac_X550EM_x &&
7102             hw->mac.type != ixgbe_mac_X550EM_a) {
7103                 return -ENOTSUP;
7104         }
7105
7106         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7107         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7108         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7109         IXGBE_WRITE_FLUSH(hw);
7110
7111         return 0;
7112 }
7113
7114 /* Disable l2 tunnel */
7115 static int
7116 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7117                             enum rte_eth_tunnel_type l2_tunnel_type)
7118 {
7119         int ret = 0;
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121
7122         switch (l2_tunnel_type) {
7123         case RTE_L2_TUNNEL_TYPE_E_TAG:
7124                 ret = ixgbe_e_tag_disable(hw);
7125                 break;
7126         default:
7127                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7128                 ret = -EINVAL;
7129                 break;
7130         }
7131
7132         return ret;
7133 }
7134
7135 static int
7136 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7137                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7138 {
7139         int ret = 0;
7140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141         uint32_t i, rar_entries;
7142         uint32_t rar_low, rar_high;
7143
7144         if (hw->mac.type != ixgbe_mac_X550 &&
7145             hw->mac.type != ixgbe_mac_X550EM_x &&
7146             hw->mac.type != ixgbe_mac_X550EM_a) {
7147                 return -ENOTSUP;
7148         }
7149
7150         rar_entries = ixgbe_get_num_rx_addrs(hw);
7151
7152         for (i = 1; i < rar_entries; i++) {
7153                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7154                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7155                 if ((rar_high & IXGBE_RAH_AV) &&
7156                     (rar_high & IXGBE_RAH_ADTYPE) &&
7157                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7158                      l2_tunnel->tunnel_id)) {
7159                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7160                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7161
7162                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7163
7164                         return ret;
7165                 }
7166         }
7167
7168         return ret;
7169 }
7170
7171 static int
7172 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7173                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7174 {
7175         int ret = 0;
7176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7177         uint32_t i, rar_entries;
7178         uint32_t rar_low, rar_high;
7179
7180         if (hw->mac.type != ixgbe_mac_X550 &&
7181             hw->mac.type != ixgbe_mac_X550EM_x &&
7182             hw->mac.type != ixgbe_mac_X550EM_a) {
7183                 return -ENOTSUP;
7184         }
7185
7186         /* One entry for one tunnel. Try to remove potential existing entry. */
7187         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7188
7189         rar_entries = ixgbe_get_num_rx_addrs(hw);
7190
7191         for (i = 1; i < rar_entries; i++) {
7192                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7193                 if (rar_high & IXGBE_RAH_AV) {
7194                         continue;
7195                 } else {
7196                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7197                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7198                         rar_low = l2_tunnel->tunnel_id;
7199
7200                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7201                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7202
7203                         return ret;
7204                 }
7205         }
7206
7207         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7208                      " Please remove a rule before adding a new one.");
7209         return -EINVAL;
7210 }
7211
7212 /* Add l2 tunnel filter */
7213 static int
7214 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7215                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7216 {
7217         int ret = 0;
7218
7219         switch (l2_tunnel->l2_tunnel_type) {
7220         case RTE_L2_TUNNEL_TYPE_E_TAG:
7221                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7222                 break;
7223         default:
7224                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7225                 ret = -EINVAL;
7226                 break;
7227         }
7228
7229         return ret;
7230 }
7231
7232 /* Delete l2 tunnel filter */
7233 static int
7234 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7235                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7236 {
7237         int ret = 0;
7238
7239         switch (l2_tunnel->l2_tunnel_type) {
7240         case RTE_L2_TUNNEL_TYPE_E_TAG:
7241                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7242                 break;
7243         default:
7244                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7245                 ret = -EINVAL;
7246                 break;
7247         }
7248
7249         return ret;
7250 }
7251
7252 /**
7253  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7254  * @dev: pointer to rte_eth_dev structure
7255  * @filter_op:operation will be taken.
7256  * @arg: a pointer to specific structure corresponding to the filter_op
7257  */
7258 static int
7259 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7260                                   enum rte_filter_op filter_op,
7261                                   void *arg)
7262 {
7263         int ret = 0;
7264
7265         if (filter_op == RTE_ETH_FILTER_NOP)
7266                 return 0;
7267
7268         if (arg == NULL) {
7269                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7270                             filter_op);
7271                 return -EINVAL;
7272         }
7273
7274         switch (filter_op) {
7275         case RTE_ETH_FILTER_ADD:
7276                 ret = ixgbe_dev_l2_tunnel_filter_add
7277                         (dev,
7278                          (struct rte_eth_l2_tunnel_conf *)arg);
7279                 break;
7280         case RTE_ETH_FILTER_DELETE:
7281                 ret = ixgbe_dev_l2_tunnel_filter_del
7282                         (dev,
7283                          (struct rte_eth_l2_tunnel_conf *)arg);
7284                 break;
7285         default:
7286                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7287                 ret = -EINVAL;
7288                 break;
7289         }
7290         return ret;
7291 }
7292
7293 static int
7294 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7295 {
7296         int ret = 0;
7297         uint32_t ctrl;
7298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7299
7300         if (hw->mac.type != ixgbe_mac_X550 &&
7301             hw->mac.type != ixgbe_mac_X550EM_x &&
7302             hw->mac.type != ixgbe_mac_X550EM_a) {
7303                 return -ENOTSUP;
7304         }
7305
7306         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7307         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7308         if (en)
7309                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7310         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7311
7312         return ret;
7313 }
7314
7315 /* Enable l2 tunnel forwarding */
7316 static int
7317 ixgbe_dev_l2_tunnel_forwarding_enable
7318         (struct rte_eth_dev *dev,
7319          enum rte_eth_tunnel_type l2_tunnel_type)
7320 {
7321         int ret = 0;
7322
7323         switch (l2_tunnel_type) {
7324         case RTE_L2_TUNNEL_TYPE_E_TAG:
7325                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7326                 break;
7327         default:
7328                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7329                 ret = -EINVAL;
7330                 break;
7331         }
7332
7333         return ret;
7334 }
7335
7336 /* Disable l2 tunnel forwarding */
7337 static int
7338 ixgbe_dev_l2_tunnel_forwarding_disable
7339         (struct rte_eth_dev *dev,
7340          enum rte_eth_tunnel_type l2_tunnel_type)
7341 {
7342         int ret = 0;
7343
7344         switch (l2_tunnel_type) {
7345         case RTE_L2_TUNNEL_TYPE_E_TAG:
7346                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7347                 break;
7348         default:
7349                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7350                 ret = -EINVAL;
7351                 break;
7352         }
7353
7354         return ret;
7355 }
7356
7357 static int
7358 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7359                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7360                              bool en)
7361 {
7362         int ret = 0;
7363         uint32_t vmtir, vmvir;
7364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365
7366         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7367                 PMD_DRV_LOG(ERR,
7368                             "VF id %u should be less than %u",
7369                             l2_tunnel->vf_id,
7370                             dev->pci_dev->max_vfs);
7371                 return -EINVAL;
7372         }
7373
7374         if (hw->mac.type != ixgbe_mac_X550 &&
7375             hw->mac.type != ixgbe_mac_X550EM_x &&
7376             hw->mac.type != ixgbe_mac_X550EM_a) {
7377                 return -ENOTSUP;
7378         }
7379
7380         if (en)
7381                 vmtir = l2_tunnel->tunnel_id;
7382         else
7383                 vmtir = 0;
7384
7385         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7386
7387         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7388         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7389         if (en)
7390                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7391         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7392
7393         return ret;
7394 }
7395
7396 /* Enable l2 tunnel tag insertion */
7397 static int
7398 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7399                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7400 {
7401         int ret = 0;
7402
7403         switch (l2_tunnel->l2_tunnel_type) {
7404         case RTE_L2_TUNNEL_TYPE_E_TAG:
7405                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7406                 break;
7407         default:
7408                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7409                 ret = -EINVAL;
7410                 break;
7411         }
7412
7413         return ret;
7414 }
7415
7416 /* Disable l2 tunnel tag insertion */
7417 static int
7418 ixgbe_dev_l2_tunnel_insertion_disable
7419         (struct rte_eth_dev *dev,
7420          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7421 {
7422         int ret = 0;
7423
7424         switch (l2_tunnel->l2_tunnel_type) {
7425         case RTE_L2_TUNNEL_TYPE_E_TAG:
7426                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7427                 break;
7428         default:
7429                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7430                 ret = -EINVAL;
7431                 break;
7432         }
7433
7434         return ret;
7435 }
7436
7437 static int
7438 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7439                              bool en)
7440 {
7441         int ret = 0;
7442         uint32_t qde;
7443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444
7445         if (hw->mac.type != ixgbe_mac_X550 &&
7446             hw->mac.type != ixgbe_mac_X550EM_x &&
7447             hw->mac.type != ixgbe_mac_X550EM_a) {
7448                 return -ENOTSUP;
7449         }
7450
7451         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7452         if (en)
7453                 qde |= IXGBE_QDE_STRIP_TAG;
7454         else
7455                 qde &= ~IXGBE_QDE_STRIP_TAG;
7456         qde &= ~IXGBE_QDE_READ;
7457         qde |= IXGBE_QDE_WRITE;
7458         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7459
7460         return ret;
7461 }
7462
7463 /* Enable l2 tunnel tag stripping */
7464 static int
7465 ixgbe_dev_l2_tunnel_stripping_enable
7466         (struct rte_eth_dev *dev,
7467          enum rte_eth_tunnel_type l2_tunnel_type)
7468 {
7469         int ret = 0;
7470
7471         switch (l2_tunnel_type) {
7472         case RTE_L2_TUNNEL_TYPE_E_TAG:
7473                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7474                 break;
7475         default:
7476                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7477                 ret = -EINVAL;
7478                 break;
7479         }
7480
7481         return ret;
7482 }
7483
7484 /* Disable l2 tunnel tag stripping */
7485 static int
7486 ixgbe_dev_l2_tunnel_stripping_disable
7487         (struct rte_eth_dev *dev,
7488          enum rte_eth_tunnel_type l2_tunnel_type)
7489 {
7490         int ret = 0;
7491
7492         switch (l2_tunnel_type) {
7493         case RTE_L2_TUNNEL_TYPE_E_TAG:
7494                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7495                 break;
7496         default:
7497                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7498                 ret = -EINVAL;
7499                 break;
7500         }
7501
7502         return ret;
7503 }
7504
7505 /* Enable/disable l2 tunnel offload functions */
7506 static int
7507 ixgbe_dev_l2_tunnel_offload_set
7508         (struct rte_eth_dev *dev,
7509          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7510          uint32_t mask,
7511          uint8_t en)
7512 {
7513         int ret = 0;
7514
7515         if (l2_tunnel == NULL)
7516                 return -EINVAL;
7517
7518         ret = -EINVAL;
7519         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7520                 if (en)
7521                         ret = ixgbe_dev_l2_tunnel_enable(
7522                                 dev,
7523                                 l2_tunnel->l2_tunnel_type);
7524                 else
7525                         ret = ixgbe_dev_l2_tunnel_disable(
7526                                 dev,
7527                                 l2_tunnel->l2_tunnel_type);
7528         }
7529
7530         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7531                 if (en)
7532                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7533                                 dev,
7534                                 l2_tunnel);
7535                 else
7536                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7537                                 dev,
7538                                 l2_tunnel);
7539         }
7540
7541         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7542                 if (en)
7543                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7544                                 dev,
7545                                 l2_tunnel->l2_tunnel_type);
7546                 else
7547                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7548                                 dev,
7549                                 l2_tunnel->l2_tunnel_type);
7550         }
7551
7552         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7553                 if (en)
7554                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7555                                 dev,
7556                                 l2_tunnel->l2_tunnel_type);
7557                 else
7558                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7559                                 dev,
7560                                 l2_tunnel->l2_tunnel_type);
7561         }
7562
7563         return ret;
7564 }
7565
7566 static int
7567 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7568                         uint16_t port)
7569 {
7570         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7571         IXGBE_WRITE_FLUSH(hw);
7572
7573         return 0;
7574 }
7575
7576 /* There's only one register for VxLAN UDP port.
7577  * So, we cannot add several ports. Will update it.
7578  */
7579 static int
7580 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7581                      uint16_t port)
7582 {
7583         if (port == 0) {
7584                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7585                 return -EINVAL;
7586         }
7587
7588         return ixgbe_update_vxlan_port(hw, port);
7589 }
7590
7591 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7592  * UDP port, it must have a value.
7593  * So, will reset it to the original value 0.
7594  */
7595 static int
7596 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7597                      uint16_t port)
7598 {
7599         uint16_t cur_port;
7600
7601         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7602
7603         if (cur_port != port) {
7604                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7605                 return -EINVAL;
7606         }
7607
7608         return ixgbe_update_vxlan_port(hw, 0);
7609 }
7610
7611 /* Add UDP tunneling port */
7612 static int
7613 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7614                               struct rte_eth_udp_tunnel *udp_tunnel)
7615 {
7616         int ret = 0;
7617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7618
7619         if (hw->mac.type != ixgbe_mac_X550 &&
7620             hw->mac.type != ixgbe_mac_X550EM_x &&
7621             hw->mac.type != ixgbe_mac_X550EM_a) {
7622                 return -ENOTSUP;
7623         }
7624
7625         if (udp_tunnel == NULL)
7626                 return -EINVAL;
7627
7628         switch (udp_tunnel->prot_type) {
7629         case RTE_TUNNEL_TYPE_VXLAN:
7630                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7631                 break;
7632
7633         case RTE_TUNNEL_TYPE_GENEVE:
7634         case RTE_TUNNEL_TYPE_TEREDO:
7635                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7636                 ret = -EINVAL;
7637                 break;
7638
7639         default:
7640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7641                 ret = -EINVAL;
7642                 break;
7643         }
7644
7645         return ret;
7646 }
7647
7648 /* Remove UDP tunneling port */
7649 static int
7650 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7651                               struct rte_eth_udp_tunnel *udp_tunnel)
7652 {
7653         int ret = 0;
7654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7655
7656         if (hw->mac.type != ixgbe_mac_X550 &&
7657             hw->mac.type != ixgbe_mac_X550EM_x &&
7658             hw->mac.type != ixgbe_mac_X550EM_a) {
7659                 return -ENOTSUP;
7660         }
7661
7662         if (udp_tunnel == NULL)
7663                 return -EINVAL;
7664
7665         switch (udp_tunnel->prot_type) {
7666         case RTE_TUNNEL_TYPE_VXLAN:
7667                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7668                 break;
7669         case RTE_TUNNEL_TYPE_GENEVE:
7670         case RTE_TUNNEL_TYPE_TEREDO:
7671                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7672                 ret = -EINVAL;
7673                 break;
7674         default:
7675                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7676                 ret = -EINVAL;
7677                 break;
7678         }
7679
7680         return ret;
7681 }
7682
7683 static void
7684 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7685 {
7686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7687
7688         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7689 }
7690
7691 static void
7692 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7693 {
7694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695
7696         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7697 }
7698
7699 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7700 {
7701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7702         u32 in_msg = 0;
7703
7704         /* peek the message first */
7705         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7706
7707         /* PF reset VF event */
7708         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7709                 /* dummy mbx read to ack pf */
7710                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7711                         return;
7712                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7713                                               NULL);
7714         }
7715 }
7716
7717 static int
7718 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7719 {
7720         uint32_t eicr;
7721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7722         struct ixgbe_interrupt *intr =
7723                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7724         ixgbevf_intr_disable(hw);
7725
7726         /* read-on-clear nic registers here */
7727         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7728         intr->flags = 0;
7729
7730         /* only one misc vector supported - mailbox */
7731         eicr &= IXGBE_VTEICR_MASK;
7732         if (eicr == IXGBE_MISC_VEC_ID)
7733                 intr->flags |= IXGBE_FLAG_MAILBOX;
7734
7735         return 0;
7736 }
7737
7738 static int
7739 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7740 {
7741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7742         struct ixgbe_interrupt *intr =
7743                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7744
7745         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7746                 ixgbevf_mbx_process(dev);
7747                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7748         }
7749
7750         ixgbevf_intr_enable(hw);
7751
7752         return 0;
7753 }
7754
7755 static void
7756 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7757                               void *param)
7758 {
7759         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7760
7761         ixgbevf_dev_interrupt_get_status(dev);
7762         ixgbevf_dev_interrupt_action(dev);
7763 }
7764
7765 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7766 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7767 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7768 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);