drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 /*Default value of Max Rx Queue*/
  97 #define IXGBE_MAX_RX_QUEUE_NUM 128
  98
  99 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
 100 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
 101 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 102
 103 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 104 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 105 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 106
 107 /*
 108  *  Default values for RX/TX configuration
 109  */
 110 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_RX_PTHRESH      8
 112 #define IXGBE_DEFAULT_RX_HTHRESH      8
 113 #define IXGBE_DEFAULT_RX_WTHRESH      0
 114
 115 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 116 #define IXGBE_DEFAULT_TX_PTHRESH      32
 117 #define IXGBE_DEFAULT_TX_HTHRESH      0
 118 #define IXGBE_DEFAULT_TX_WTHRESH      0
 119 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 120
 121 /* Bit shift and mask */
 122 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 123 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 124 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 125 #define IXGBE_8_BIT_MASK   UINT8_MAX
 126
 127 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 128
 129 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 130
 131 #define IXGBE_HKEY_MAX_INDEX 10
 132
 133 /* Additional timesync values. */
 134 #define NSEC_PER_SEC             1000000000L
 135 #define IXGBE_INCVAL_10GB        0x66666666
 136 #define IXGBE_INCVAL_1GB         0x40000000
 137 #define IXGBE_INCVAL_100         0x50000000
 138 #define IXGBE_INCVAL_SHIFT_10GB  28
 139 #define IXGBE_INCVAL_SHIFT_1GB   24
 140 #define IXGBE_INCVAL_SHIFT_100   21
 141 #define IXGBE_INCVAL_SHIFT_82599 7
 142 #define IXGBE_INCPER_SHIFT_82599 24
 143
 144 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 145
 146 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 147 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 148 #define DEFAULT_ETAG_ETYPE                     0x893f
 149 #define IXGBE_ETAG_ETYPE                       0x00005084
 150 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 151 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 152 #define IXGBE_RAH_ADTYPE                       0x40000000
 153 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 154 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 155 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 156 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 157 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 158 #define IXGBE_VTEICR_MASK                      0x07
 159
 160 enum ixgbevf_xcast_modes {
 161         IXGBEVF_XCAST_MODE_NONE = 0,
 162         IXGBEVF_XCAST_MODE_MULTI,
 163         IXGBEVF_XCAST_MODE_ALLMULTI,
 164 };
 165
 166 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 167 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 168
 169 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 170 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 171 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 174 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 182                                 int wait_to_complete);
 183 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_stats *stats);
 185 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_xstat *xstats, unsigned n);
 187 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 188                                   struct rte_eth_xstat *xstats, unsigned n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 196                                              uint16_t queue_id,
 197                                              uint8_t stat_idx,
 198                                              uint8_t is_rx);
 199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 200                                struct rte_eth_dev_info *dev_info);
 201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 203                                  struct rte_eth_dev_info *dev_info);
 204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205
 206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 207                 uint16_t vlan_id, int on);
 208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 209                                enum rte_vlan_type vlan_type,
 210                                uint16_t tpid_id);
 211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 212                 uint16_t queue, bool on);
 213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 214                 int on);
 215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 220
 221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 224                                struct rte_eth_fc_conf *fc_conf);
 225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 226                                struct rte_eth_fc_conf *fc_conf);
 227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 228                 struct rte_eth_pfc_conf *pfc_conf);
 229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 233                         struct rte_eth_rss_reta_entry64 *reta_conf,
 234                         uint16_t reta_size);
 235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 240 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 241                 void *param);
 242 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 243 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 244                 uint32_t index, uint32_t pool);
 245 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 246 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 247                                            struct ether_addr *mac_addr);
 248 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 249
 250 /* For Virtual Function support */
 251 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 252 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 253 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 254 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 255 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 256                                    int wait_to_complete);
 257 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 259 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 260 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 261 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 262                 struct rte_eth_stats *stats);
 263 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 265                 uint16_t vlan_id, int on);
 266 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 267                 uint16_t queue, int on);
 268 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 269 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 270 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 271                                             uint16_t queue_id);
 272 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 273                                              uint16_t queue_id);
 274 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 275                                  uint8_t queue, uint8_t msix_vector);
 276 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 285                 uint16_t rx_mask, uint8_t on);
 286 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 287 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 288 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 289                 uint64_t pool_mask, uint8_t vlan_on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 306                 uint16_t tx_rate, uint64_t q_msk);
 307
 308 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                  struct ether_addr *mac_addr,
 310                                  uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter,
 316                         bool add);
 317 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 318                         struct rte_eth_syn_filter *filter);
 319 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 320                         enum rte_filter_op filter_op,
 321                         void *arg);
 322 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 325                         struct ixgbe_5tuple_filter *filter);
 326 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter,
 328                         bool add);
 329 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ntuple_filter *filter);
 334 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 335                         struct rte_eth_ethertype_filter *filter,
 336                         bool add);
 337 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 338                                 enum rte_filter_op filter_op,
 339                                 void *arg);
 340 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 341                         struct rte_eth_ethertype_filter *filter);
 342 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 343                      enum rte_filter_type filter_type,
 344                      enum rte_filter_op filter_op,
 345                      void *arg);
 346 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 347
 348 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 349                                       struct ether_addr *mc_addr_set,
 350                                       uint32_t nb_mc_addr);
 351 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 352                                    struct rte_eth_dcb_info *dcb_info);
 353
 354 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 356                             struct rte_dev_reg_info *regs);
 357 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 358 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 359                                 struct rte_dev_eeprom_info *eeprom);
 360 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 361                                 struct rte_dev_eeprom_info *eeprom);
 362
 363 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 364 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 365                                 struct rte_dev_reg_info *regs);
 366
 367 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 368 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 369 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 370                                             struct timespec *timestamp,
 371                                             uint32_t flags);
 372 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 373                                             struct timespec *timestamp);
 374 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 375 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 376                                    struct timespec *timestamp);
 377 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 378                                    const struct timespec *timestamp);
 379 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                           void *param);
 381
 382 static int ixgbe_dev_l2_tunnel_eth_type_conf
 383         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 384 static int ixgbe_dev_l2_tunnel_offload_set
 385         (struct rte_eth_dev *dev,
 386          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 387          uint32_t mask,
 388          uint8_t en);
 389 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 390                                              enum rte_filter_op filter_op,
 391                                              void *arg);
 392
 393 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 396                                          struct rte_eth_udp_tunnel *udp_tunnel);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 492 #ifdef RTE_NIC_BYPASS
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 494 #endif
 495         { .vendor_id = 0, /* sentinel */ },
 496 };
 497
 498 /*
 499  * The set of PCI devices this driver supports (for 82599 VF)
 500  */
 501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 511         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 512         { .vendor_id = 0, /* sentinel */ },
 513 };
 514
 515 static const struct rte_eth_desc_lim rx_desc_lim = {
 516         .nb_max = IXGBE_MAX_RING_DESC,
 517         .nb_min = IXGBE_MIN_RING_DESC,
 518         .nb_align = IXGBE_RXD_ALIGN,
 519 };
 520
 521 static const struct rte_eth_desc_lim tx_desc_lim = {
 522         .nb_max = IXGBE_MAX_RING_DESC,
 523         .nb_min = IXGBE_MIN_RING_DESC,
 524         .nb_align = IXGBE_TXD_ALIGN,
 525 };
 526
 527 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 528         .dev_configure        = ixgbe_dev_configure,
 529         .dev_start            = ixgbe_dev_start,
 530         .dev_stop             = ixgbe_dev_stop,
 531         .dev_set_link_up    = ixgbe_dev_set_link_up,
 532         .dev_set_link_down  = ixgbe_dev_set_link_down,
 533         .dev_close            = ixgbe_dev_close,
 534         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 535         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 536         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 537         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 538         .link_update          = ixgbe_dev_link_update,
 539         .stats_get            = ixgbe_dev_stats_get,
 540         .xstats_get           = ixgbe_dev_xstats_get,
 541         .stats_reset          = ixgbe_dev_stats_reset,
 542         .xstats_reset         = ixgbe_dev_xstats_reset,
 543         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .dev_infos_get        = ixgbe_dev_info_get,
 546         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 547         .mtu_set              = ixgbe_dev_mtu_set,
 548         .vlan_filter_set      = ixgbe_vlan_filter_set,
 549         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 550         .vlan_offload_set     = ixgbe_vlan_offload_set,
 551         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 552         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 553         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 554         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 555         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 556         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 557         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 558         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 559         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 560         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 561         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 577         .set_vf_rx            = ixgbe_set_pool_rx,
 578         .set_vf_tx            = ixgbe_set_pool_tx,
 579         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 580         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 581         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584 #ifdef RTE_NIC_BYPASS
 585         .bypass_init          = ixgbe_bypass_init,
 586         .bypass_state_set     = ixgbe_bypass_state_store,
 587         .bypass_state_show    = ixgbe_bypass_state_show,
 588         .bypass_event_set     = ixgbe_bypass_event_store,
 589         .bypass_event_show    = ixgbe_bypass_event_show,
 590         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 591         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 592         .bypass_ver_show      = ixgbe_bypass_ver_show,
 593         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 594 #endif /* RTE_NIC_BYPASS */
 595         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 596         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 597         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 598         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 599         .rxq_info_get         = ixgbe_rxq_info_get,
 600         .txq_info_get         = ixgbe_txq_info_get,
 601         .timesync_enable      = ixgbe_timesync_enable,
 602         .timesync_disable     = ixgbe_timesync_disable,
 603         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 604         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 605         .get_reg              = ixgbe_get_regs,
 606         .get_eeprom_length    = ixgbe_get_eeprom_length,
 607         .get_eeprom           = ixgbe_get_eeprom,
 608         .set_eeprom           = ixgbe_set_eeprom,
 609         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 610         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 611         .timesync_read_time   = ixgbe_timesync_read_time,
 612         .timesync_write_time  = ixgbe_timesync_write_time,
 613         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 614         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 615         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 616         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 617 };
 618
 619 /*
 620  * dev_ops for virtual function, bare necessities for basic vf
 621  * operation have been implemented
 622  */
 623 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 624         .dev_configure        = ixgbevf_dev_configure,
 625         .dev_start            = ixgbevf_dev_start,
 626         .dev_stop             = ixgbevf_dev_stop,
 627         .link_update          = ixgbevf_dev_link_update,
 628         .stats_get            = ixgbevf_dev_stats_get,
 629         .xstats_get           = ixgbevf_dev_xstats_get,
 630         .stats_reset          = ixgbevf_dev_stats_reset,
 631         .xstats_reset         = ixgbevf_dev_stats_reset,
 632         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 633         .dev_close            = ixgbevf_dev_close,
 634         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 635         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 636         .dev_infos_get        = ixgbevf_dev_info_get,
 637         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 638         .mtu_set              = ixgbevf_dev_set_mtu,
 639         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 640         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 641         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 642         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 643         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 644         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 645         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 646         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 647         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 648         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 649         .mac_addr_add         = ixgbevf_add_mac_addr,
 650         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 651         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 652         .rxq_info_get         = ixgbe_rxq_info_get,
 653         .txq_info_get         = ixgbe_txq_info_get,
 654         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 655         .get_reg              = ixgbevf_get_regs,
 656         .reta_update          = ixgbe_dev_rss_reta_update,
 657         .reta_query           = ixgbe_dev_rss_reta_query,
 658         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 659         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 660 };
 661
 662 /* store statistics names and its offset in stats structure */
 663 struct rte_ixgbe_xstats_name_off {
 664         char name[RTE_ETH_XSTATS_NAME_SIZE];
 665         unsigned offset;
 666 };
 667
 668 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 669         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 670         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 671         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 672         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 673         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 674         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 675         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 676         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 677         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 678         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 679         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 680         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 681         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 682         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 683         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1023)},
 685         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 686                 prc1522)},
 687         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 688         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 689         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 690         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 691         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 692         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 693         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 694         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 695         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 696         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 697         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 698         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 699         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 700         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 701         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 702         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 703         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1023)},
 705         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 706                 ptc1522)},
 707         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 708         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 709         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 710         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 711
 712         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_add)},
 714         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirustat_remove)},
 716         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fadd)},
 718         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 719                 fdirfstat_fremove)},
 720         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmatch)},
 722         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 723                 fdirmiss)},
 724
 725         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 726         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 727         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 728                 fclast)},
 729         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 730         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 731         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 732         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 733         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 734                 fcoe_noddp)},
 735         {"rx_fcoe_no_direct_data_placement_ext_buff",
 736                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 737
 738         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxontxc)},
 740         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxonrxc)},
 742         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxofftxc)},
 744         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 745                 lxoffrxc)},
 746         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 747 };
 748
 749 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 750                            sizeof(rte_ixgbe_stats_strings[0]))
 751
 752 /* Per-queue statistics */
 753 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 754         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 755         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 756         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 757         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 758 };
 759
 760 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 761                            sizeof(rte_ixgbe_rxq_strings[0]))
 762 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 763
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 765         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 766         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 767         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 768                 pxon2offc)},
 769 };
 770
 771 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 772                            sizeof(rte_ixgbe_txq_strings[0]))
 773 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 776         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 777 };
 778
 779 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 780                 sizeof(rte_ixgbevf_stats_strings[0]))
 781
 782 /**
 783  * Atomically reads the link status information from global
 784  * structure rte_eth_dev.
 785  *
 786  * @param dev
 787  *   - Pointer to the structure rte_eth_dev to read from.
 788  *   - Pointer to the buffer to be saved with the link status.
 789  *
 790  * @return
 791  *   - On success, zero.
 792  *   - On failure, negative value.
 793  */
 794 static inline int
 795 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 796                                 struct rte_eth_link *link)
 797 {
 798         struct rte_eth_link *dst = link;
 799         struct rte_eth_link *src = &(dev->data->dev_link);
 800
 801         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 802                                         *(uint64_t *)src) == 0)
 803                 return -1;
 804
 805         return 0;
 806 }
 807
 808 /**
 809  * Atomically writes the link status information into global
 810  * structure rte_eth_dev.
 811  *
 812  * @param dev
 813  *   - Pointer to the structure rte_eth_dev to read from.
 814  *   - Pointer to the buffer to be saved with the link status.
 815  *
 816  * @return
 817  *   - On success, zero.
 818  *   - On failure, negative value.
 819  */
 820 static inline int
 821 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 822                                 struct rte_eth_link *link)
 823 {
 824         struct rte_eth_link *dst = &(dev->data->dev_link);
 825         struct rte_eth_link *src = link;
 826
 827         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 828                                         *(uint64_t *)src) == 0)
 829                 return -1;
 830
 831         return 0;
 832 }
 833
 834 /*
 835  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 836  */
 837 static inline int
 838 ixgbe_is_sfp(struct ixgbe_hw *hw)
 839 {
 840         switch (hw->phy.type) {
 841         case ixgbe_phy_sfp_avago:
 842         case ixgbe_phy_sfp_ftl:
 843         case ixgbe_phy_sfp_intel:
 844         case ixgbe_phy_sfp_unknown:
 845         case ixgbe_phy_sfp_passive_tyco:
 846         case ixgbe_phy_sfp_passive_unknown:
 847                 return 1;
 848         default:
 849                 return 0;
 850         }
 851 }
 852
 853 static inline int32_t
 854 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 855 {
 856         uint32_t ctrl_ext;
 857         int32_t status;
 858
 859         status = ixgbe_reset_hw(hw);
 860
 861         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 862         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 863         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 864         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 865         IXGBE_WRITE_FLUSH(hw);
 866
 867         return status;
 868 }
 869
 870 static inline void
 871 ixgbe_enable_intr(struct rte_eth_dev *dev)
 872 {
 873         struct ixgbe_interrupt *intr =
 874                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 875         struct ixgbe_hw *hw =
 876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 879         IXGBE_WRITE_FLUSH(hw);
 880 }
 881
 882 /*
 883  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 884  */
 885 static void
 886 ixgbe_disable_intr(struct ixgbe_hw *hw)
 887 {
 888         PMD_INIT_FUNC_TRACE();
 889
 890         if (hw->mac.type == ixgbe_mac_82598EB) {
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 892         } else {
 893                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 894                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 895                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 896         }
 897         IXGBE_WRITE_FLUSH(hw);
 898 }
 899
 900 /*
 901  * This function resets queue statistics mapping registers.
 902  * From Niantic datasheet, Initialization of Statistics section:
 903  * "...if software requires the queue counters, the RQSMR and TQSM registers
 904  * must be re-programmed following a device reset.
 905  */
 906 static void
 907 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 908 {
 909         uint32_t i;
 910
 911         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 912                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 914         }
 915 }
 916
 917
 918 static int
 919 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 920                                   uint16_t queue_id,
 921                                   uint8_t stat_idx,
 922                                   uint8_t is_rx)
 923 {
 924 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 925 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 926 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 927
 928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         struct ixgbe_stat_mapping_registers *stat_mappings =
 930                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 931         uint32_t qsmr_mask = 0;
 932         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 933         uint32_t q_map;
 934         uint8_t n, offset;
 935
 936         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 937                 (hw->mac.type != ixgbe_mac_X540) &&
 938                 (hw->mac.type != ixgbe_mac_X550) &&
 939                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 940                 (hw->mac.type != ixgbe_mac_X550EM_a))
 941                 return -ENOSYS;
 942
 943         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 944                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 945                      queue_id, stat_idx);
 946
 947         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 948         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 949                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 950                 return -EIO;
 951         }
 952         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 953
 954         /* Now clear any previous stat_idx set */
 955         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 956         if (!is_rx)
 957                 stat_mappings->tqsm[n] &= ~clearing_mask;
 958         else
 959                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 960
 961         q_map = (uint32_t)stat_idx;
 962         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 963         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 964         if (!is_rx)
 965                 stat_mappings->tqsm[n] |= qsmr_mask;
 966         else
 967                 stat_mappings->rqsmr[n] |= qsmr_mask;
 968
 969         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 970                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 971                      queue_id, stat_idx);
 972         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 973                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 974
 975         /* Now write the mapping in the appropriate register */
 976         if (is_rx) {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 978                              stat_mappings->rqsmr[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 980         } else {
 981                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 982                              stat_mappings->tqsm[n], n);
 983                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 984         }
 985         return 0;
 986 }
 987
 988 static void
 989 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 990 {
 991         struct ixgbe_stat_mapping_registers *stat_mappings =
 992                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 994         int i;
 995
 996         /* write whatever was in stat mapping table to the NIC */
 997         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 998                 /* rx */
 999                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1000
1001                 /* tx */
1002                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1003         }
1004 }
1005
1006 static void
1007 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1008 {
1009         uint8_t i;
1010         struct ixgbe_dcb_tc_config *tc;
1011         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1012
1013         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1014         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1015         for (i = 0; i < dcb_max_tc; i++) {
1016                 tc = &dcb_config->tc_config[i];
1017                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1018                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1019                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1020                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1021                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1022                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1023                 tc->pfc = ixgbe_dcb_pfc_disabled;
1024         }
1025
1026         /* Initialize default user to priority mapping, UPx->TC0 */
1027         tc = &dcb_config->tc_config[0];
1028         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1029         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1030         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1031                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1032                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1033         }
1034         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1035         dcb_config->pfc_mode_enable = false;
1036         dcb_config->vt_mode = true;
1037         dcb_config->round_robin_enable = false;
1038         /* support all DCB capabilities in 82599 */
1039         dcb_config->support.capabilities = 0xFF;
1040
1041         /*we only support 4 Tcs for X540, X550 */
1042         if (hw->mac.type == ixgbe_mac_X540 ||
1043                 hw->mac.type == ixgbe_mac_X550 ||
1044                 hw->mac.type == ixgbe_mac_X550EM_x ||
1045                 hw->mac.type == ixgbe_mac_X550EM_a) {
1046                 dcb_config->num_tcs.pg_tcs = 4;
1047                 dcb_config->num_tcs.pfc_tcs = 4;
1048         }
1049 }
1050
1051 /*
1052  * Ensure that all locks are released before first NVM or PHY access
1053  */
1054 static void
1055 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1056 {
1057         uint16_t mask;
1058
1059         /*
1060          * Phy lock should not fail in this early stage. If this is the case,
1061          * it is due to an improper exit of the application.
1062          * So force the release of the faulty lock. Release of common lock
1063          * is done automatically by swfw_sync function.
1064          */
1065         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1066         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1068         }
1069         ixgbe_release_swfw_semaphore(hw, mask);
1070
1071         /*
1072          * These ones are more tricky since they are common to all ports; but
1073          * swfw_sync retries last long enough (1s) to be almost sure that if
1074          * lock can not be taken it is due to an improper lock of the
1075          * semaphore.
1076          */
1077         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1078         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1079                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1080         }
1081         ixgbe_release_swfw_semaphore(hw, mask);
1082 }
1083
1084 /*
1085  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1086  * It returns 0 on success.
1087  */
1088 static int
1089 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1090 {
1091         struct rte_pci_device *pci_dev;
1092         struct ixgbe_hw *hw =
1093                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1094         struct ixgbe_vfta *shadow_vfta =
1095                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1096         struct ixgbe_hwstrip *hwstrip =
1097                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1098         struct ixgbe_dcb_config *dcb_config =
1099                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1100         struct ixgbe_filter_info *filter_info =
1101                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1102         uint32_t ctrl_ext;
1103         uint16_t csum;
1104         int diag, i;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1109         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1110         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1111
1112         /*
1113          * For secondary processes, we don't initialise any further as primary
1114          * has already done this work. Only check we don't need a different
1115          * RX and TX function.
1116          */
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118                 struct ixgbe_tx_queue *txq;
1119                 /* TX queue function in primary, set by last queue initialized
1120                  * Tx queue may not initialized by primary process
1121                  */
1122                 if (eth_dev->data->tx_queues) {
1123                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124                         ixgbe_set_tx_function(eth_dev, txq);
1125                 } else {
1126                         /* Use default TX function if we get here */
1127                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128                                      "Using default TX function.");
1129                 }
1130
1131                 ixgbe_set_rx_function(eth_dev);
1132
1133                 return 0;
1134         }
1135         pci_dev = eth_dev->pci_dev;
1136
1137         rte_eth_copy_pci_info(eth_dev, pci_dev);
1138
1139         /* Vendor and Device ID need to be set before init of shared code */
1140         hw->device_id = pci_dev->id.device_id;
1141         hw->vendor_id = pci_dev->id.vendor_id;
1142         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1143         hw->allow_unsupported_sfp = 1;
1144
1145         /* Initialize the shared code (base driver) */
1146 #ifdef RTE_NIC_BYPASS
1147         diag = ixgbe_bypass_init_shared_code(hw);
1148 #else
1149         diag = ixgbe_init_shared_code(hw);
1150 #endif /* RTE_NIC_BYPASS */
1151
1152         if (diag != IXGBE_SUCCESS) {
1153                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1154                 return -EIO;
1155         }
1156
1157         /* pick up the PCI bus settings for reporting later */
1158         ixgbe_get_bus_info(hw);
1159
1160         /* Unlock any pending hardware semaphore */
1161         ixgbe_swfw_lock_reset(hw);
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_full;
1168         hw->fc.current_mode = ixgbe_fc_full;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1243                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(&pci_dev->intr_handle,
1281                                    ixgbe_dev_interrupt_handler,
1282                                    (void *)eth_dev);
1283
1284         /* enable uio/vfio intr/eventfd mapping */
1285         rte_intr_enable(&pci_dev->intr_handle);
1286
1287         /* enable support intr */
1288         ixgbe_enable_intr(eth_dev);
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292         memset(filter_info->fivetuple_mask, 0,
1293                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1294
1295         return 0;
1296 }
1297
1298 static int
1299 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1300 {
1301         struct rte_pci_device *pci_dev;
1302         struct ixgbe_hw *hw;
1303         int retries = 0;
1304         int ret;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1309                 return -EPERM;
1310
1311         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1312         pci_dev = eth_dev->pci_dev;
1313
1314         if (hw->adapter_stopped == 0)
1315                 ixgbe_dev_close(eth_dev);
1316
1317         eth_dev->dev_ops = NULL;
1318         eth_dev->rx_pkt_burst = NULL;
1319         eth_dev->tx_pkt_burst = NULL;
1320
1321         /* Unlock any pending hardware semaphore */
1322         ixgbe_swfw_lock_reset(hw);
1323
1324         /* disable uio intr before callback unregister */
1325         rte_intr_disable(&(pci_dev->intr_handle));
1326
1327         do {
1328                 ret = rte_intr_callback_unregister(&(pci_dev->intr_handle),
1329                                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1330                 if (ret >= 0) {
1331                         break;
1332                 } else if (ret != -EAGAIN) {
1333                         PMD_INIT_LOG(ERR,
1334                                 "intr callback unregister failed: %d",
1335                                 ret);
1336                         return ret;
1337                 }
1338                 rte_delay_ms(100);
1339         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1340
1341         /* uninitialize PF if max_vfs not zero */
1342         ixgbe_pf_host_uninit(eth_dev);
1343
1344         rte_free(eth_dev->data->mac_addrs);
1345         eth_dev->data->mac_addrs = NULL;
1346
1347         rte_free(eth_dev->data->hash_mac_addrs);
1348         eth_dev->data->hash_mac_addrs = NULL;
1349
1350         return 0;
1351 }
1352
1353 /*
1354  * Negotiate mailbox API version with the PF.
1355  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1356  * Then we try to negotiate starting with the most recent one.
1357  * If all negotiation attempts fail, then we will proceed with
1358  * the default one (ixgbe_mbox_api_10).
1359  */
1360 static void
1361 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1362 {
1363         int32_t i;
1364
1365         /* start with highest supported, proceed down */
1366         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1367                 ixgbe_mbox_api_12,
1368                 ixgbe_mbox_api_11,
1369                 ixgbe_mbox_api_10,
1370         };
1371
1372         for (i = 0;
1373                         i != RTE_DIM(sup_ver) &&
1374                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1375                         i++)
1376                 ;
1377 }
1378
1379 static void
1380 generate_random_mac_addr(struct ether_addr *mac_addr)
1381 {
1382         uint64_t random;
1383
1384         /* Set Organizationally Unique Identifier (OUI) prefix. */
1385         mac_addr->addr_bytes[0] = 0x00;
1386         mac_addr->addr_bytes[1] = 0x09;
1387         mac_addr->addr_bytes[2] = 0xC0;
1388         /* Force indication of locally assigned MAC address. */
1389         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1390         /* Generate the last 3 bytes of the MAC address with a random number. */
1391         random = rte_rand();
1392         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1393 }
1394
1395 /*
1396  * Virtual Function device init
1397  */
1398 static int
1399 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1400 {
1401         int diag;
1402         uint32_t tc, tcs;
1403         struct rte_pci_device *pci_dev;
1404         struct ixgbe_hw *hw =
1405                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1406         struct ixgbe_vfta *shadow_vfta =
1407                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1408         struct ixgbe_hwstrip *hwstrip =
1409                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1410         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1415         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1416         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1417
1418         /* for secondary processes, we don't initialise any further as primary
1419          * has already done this work. Only check we don't need a different
1420          * RX function
1421          */
1422         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1423                 struct ixgbe_tx_queue *txq;
1424                 /* TX queue function in primary, set by last queue initialized
1425                  * Tx queue may not initialized by primary process
1426                  */
1427                 if (eth_dev->data->tx_queues) {
1428                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1429                         ixgbe_set_tx_function(eth_dev, txq);
1430                 } else {
1431                         /* Use default TX function if we get here */
1432                         PMD_INIT_LOG(NOTICE,
1433                                      "No TX queues configured yet. Using default TX function.");
1434                 }
1435
1436                 ixgbe_set_rx_function(eth_dev);
1437
1438                 return 0;
1439         }
1440
1441         pci_dev = eth_dev->pci_dev;
1442
1443         rte_eth_copy_pci_info(eth_dev, pci_dev);
1444
1445         hw->device_id = pci_dev->id.device_id;
1446         hw->vendor_id = pci_dev->id.vendor_id;
1447         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1448
1449         /* initialize the vfta */
1450         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1451
1452         /* initialize the hw strip bitmap*/
1453         memset(hwstrip, 0, sizeof(*hwstrip));
1454
1455         /* Initialize the shared code (base driver) */
1456         diag = ixgbe_init_shared_code(hw);
1457         if (diag != IXGBE_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1459                 return -EIO;
1460         }
1461
1462         /* init_mailbox_params */
1463         hw->mbx.ops.init_params(hw);
1464
1465         /* Reset the hw statistics */
1466         ixgbevf_dev_stats_reset(eth_dev);
1467
1468         /* Disable the interrupts for VF */
1469         ixgbevf_intr_disable(hw);
1470
1471         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1472         diag = hw->mac.ops.reset_hw(hw);
1473
1474         /*
1475          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1476          * the underlying PF driver has not assigned a MAC address to the VF.
1477          * In this case, assign a random MAC address.
1478          */
1479         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1480                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1481                 return diag;
1482         }
1483
1484         /* negotiate mailbox API version to use with the PF. */
1485         ixgbevf_negotiate_api(hw);
1486
1487         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1488         ixgbevf_get_queues(hw, &tcs, &tc);
1489
1490         /* Allocate memory for storing MAC addresses */
1491         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1492                                                hw->mac.num_rar_entries, 0);
1493         if (eth_dev->data->mac_addrs == NULL) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate %u bytes needed to store "
1496                              "MAC addresses",
1497                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1498                 return -ENOMEM;
1499         }
1500
1501         /* Generate a random MAC address, if none was assigned by PF. */
1502         if (is_zero_ether_addr(perm_addr)) {
1503                 generate_random_mac_addr(perm_addr);
1504                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1505                 if (diag) {
1506                         rte_free(eth_dev->data->mac_addrs);
1507                         eth_dev->data->mac_addrs = NULL;
1508                         return diag;
1509                 }
1510                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1511                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1512                              "%02x:%02x:%02x:%02x:%02x:%02x",
1513                              perm_addr->addr_bytes[0],
1514                              perm_addr->addr_bytes[1],
1515                              perm_addr->addr_bytes[2],
1516                              perm_addr->addr_bytes[3],
1517                              perm_addr->addr_bytes[4],
1518                              perm_addr->addr_bytes[5]);
1519         }
1520
1521         /* Copy the permanent MAC address */
1522         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1523
1524         /* reset the hardware with the new settings */
1525         diag = hw->mac.ops.start_hw(hw);
1526         switch (diag) {
1527         case  0:
1528                 break;
1529
1530         default:
1531                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1532                 return -EIO;
1533         }
1534
1535         rte_intr_callback_register(&pci_dev->intr_handle,
1536                                    ixgbevf_dev_interrupt_handler,
1537                                    (void *)eth_dev);
1538         rte_intr_enable(&pci_dev->intr_handle);
1539         ixgbevf_intr_enable(hw);
1540
1541         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1542                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1543                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1544
1545         return 0;
1546 }
1547
1548 /* Virtual Function device uninit */
1549
1550 static int
1551 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1552 {
1553         struct ixgbe_hw *hw;
1554         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1555
1556         PMD_INIT_FUNC_TRACE();
1557
1558         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1559                 return -EPERM;
1560
1561         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1562
1563         if (hw->adapter_stopped == 0)
1564                 ixgbevf_dev_close(eth_dev);
1565
1566         eth_dev->dev_ops = NULL;
1567         eth_dev->rx_pkt_burst = NULL;
1568         eth_dev->tx_pkt_burst = NULL;
1569
1570         /* Disable the interrupts for VF */
1571         ixgbevf_intr_disable(hw);
1572
1573         rte_free(eth_dev->data->mac_addrs);
1574         eth_dev->data->mac_addrs = NULL;
1575
1576         rte_intr_disable(&pci_dev->intr_handle);
1577         rte_intr_callback_unregister(&pci_dev->intr_handle,
1578                                      ixgbevf_dev_interrupt_handler,
1579                                      (void *)eth_dev);
1580
1581         return 0;
1582 }
1583
1584 static struct eth_driver rte_ixgbe_pmd = {
1585         .pci_drv = {
1586                 .id_table = pci_id_ixgbe_map,
1587                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1588                         RTE_PCI_DRV_DETACHABLE,
1589                 .probe = rte_eth_dev_pci_probe,
1590                 .remove = rte_eth_dev_pci_remove,
1591         },
1592         .eth_dev_init = eth_ixgbe_dev_init,
1593         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1594         .dev_private_size = sizeof(struct ixgbe_adapter),
1595 };
1596
1597 /*
1598  * virtual function driver struct
1599  */
1600 static struct eth_driver rte_ixgbevf_pmd = {
1601         .pci_drv = {
1602                 .id_table = pci_id_ixgbevf_map,
1603                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1604                 .probe = rte_eth_dev_pci_probe,
1605                 .remove = rte_eth_dev_pci_remove,
1606         },
1607         .eth_dev_init = eth_ixgbevf_dev_init,
1608         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1609         .dev_private_size = sizeof(struct ixgbe_adapter),
1610 };
1611
1612 static int
1613 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1614 {
1615         struct ixgbe_hw *hw =
1616                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         struct ixgbe_vfta *shadow_vfta =
1618                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1619         uint32_t vfta;
1620         uint32_t vid_idx;
1621         uint32_t vid_bit;
1622
1623         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1624         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1625         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1626         if (on)
1627                 vfta |= vid_bit;
1628         else
1629                 vfta &= ~vid_bit;
1630         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1631
1632         /* update local VFTA copy */
1633         shadow_vfta->vfta[vid_idx] = vfta;
1634
1635         return 0;
1636 }
1637
1638 static void
1639 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1640 {
1641         if (on)
1642                 ixgbe_vlan_hw_strip_enable(dev, queue);
1643         else
1644                 ixgbe_vlan_hw_strip_disable(dev, queue);
1645 }
1646
1647 static int
1648 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1649                     enum rte_vlan_type vlan_type,
1650                     uint16_t tpid)
1651 {
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         int ret = 0;
1655         uint32_t reg;
1656         uint32_t qinq;
1657
1658         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1659         qinq &= IXGBE_DMATXCTL_GDV;
1660
1661         switch (vlan_type) {
1662         case ETH_VLAN_TYPE_INNER:
1663                 if (qinq) {
1664                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1671                 } else {
1672                         ret = -ENOTSUP;
1673                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1674                                     " by single VLAN");
1675                 }
1676                 break;
1677         case ETH_VLAN_TYPE_OUTER:
1678                 if (qinq) {
1679                         /* Only the high 16-bits is valid */
1680                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1681                                         IXGBE_EXVET_VET_EXT_SHIFT);
1682                 } else {
1683                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1684                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1685                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1686                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1687                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1688                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1689                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1690                 }
1691
1692                 break;
1693         default:
1694                 ret = -EINVAL;
1695                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1696                 break;
1697         }
1698
1699         return ret;
1700 }
1701
1702 void
1703 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1704 {
1705         struct ixgbe_hw *hw =
1706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707         uint32_t vlnctrl;
1708
1709         PMD_INIT_FUNC_TRACE();
1710
1711         /* Filter Table Disable */
1712         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1714
1715         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1716 }
1717
1718 void
1719 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1720 {
1721         struct ixgbe_hw *hw =
1722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         struct ixgbe_vfta *shadow_vfta =
1724                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1725         uint32_t vlnctrl;
1726         uint16_t i;
1727
1728         PMD_INIT_FUNC_TRACE();
1729
1730         /* Filter Table Enable */
1731         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1732         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1733         vlnctrl |= IXGBE_VLNCTRL_VFE;
1734
1735         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1736
1737         /* write whatever is in local vfta copy */
1738         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1739                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1740 }
1741
1742 static void
1743 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1744 {
1745         struct ixgbe_hwstrip *hwstrip =
1746                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1747         struct ixgbe_rx_queue *rxq;
1748
1749         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1750                 return;
1751
1752         if (on)
1753                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1754         else
1755                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1756
1757         if (queue >= dev->data->nb_rx_queues)
1758                 return;
1759
1760         rxq = dev->data->rx_queues[queue];
1761
1762         if (on)
1763                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1764         else
1765                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1766 }
1767
1768 static void
1769 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1770 {
1771         struct ixgbe_hw *hw =
1772                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         uint32_t ctrl;
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         if (hw->mac.type == ixgbe_mac_82598EB) {
1778                 /* No queue level support */
1779                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1780                 return;
1781         }
1782
1783         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1784         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1785         ctrl &= ~IXGBE_RXDCTL_VME;
1786         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1787
1788         /* record those setting for HW strip per queue */
1789         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1790 }
1791
1792 static void
1793 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1794 {
1795         struct ixgbe_hw *hw =
1796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         uint32_t ctrl;
1798
1799         PMD_INIT_FUNC_TRACE();
1800
1801         if (hw->mac.type == ixgbe_mac_82598EB) {
1802                 /* No queue level supported */
1803                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1804                 return;
1805         }
1806
1807         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1808         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1809         ctrl |= IXGBE_RXDCTL_VME;
1810         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1811
1812         /* record those setting for HW strip per queue */
1813         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1814 }
1815
1816 void
1817 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1818 {
1819         struct ixgbe_hw *hw =
1820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821         uint32_t ctrl;
1822         uint16_t i;
1823         struct ixgbe_rx_queue *rxq;
1824
1825         PMD_INIT_FUNC_TRACE();
1826
1827         if (hw->mac.type == ixgbe_mac_82598EB) {
1828                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1829                 ctrl &= ~IXGBE_VLNCTRL_VME;
1830                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1831         } else {
1832                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1833                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1834                         rxq = dev->data->rx_queues[i];
1835                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1836                         ctrl &= ~IXGBE_RXDCTL_VME;
1837                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1838
1839                         /* record those setting for HW strip per queue */
1840                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1841                 }
1842         }
1843 }
1844
1845 void
1846 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1847 {
1848         struct ixgbe_hw *hw =
1849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         uint32_t ctrl;
1851         uint16_t i;
1852         struct ixgbe_rx_queue *rxq;
1853
1854         PMD_INIT_FUNC_TRACE();
1855
1856         if (hw->mac.type == ixgbe_mac_82598EB) {
1857                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1858                 ctrl |= IXGBE_VLNCTRL_VME;
1859                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1860         } else {
1861                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1862                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1863                         rxq = dev->data->rx_queues[i];
1864                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1865                         ctrl |= IXGBE_RXDCTL_VME;
1866                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1867
1868                         /* record those setting for HW strip per queue */
1869                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1870                 }
1871         }
1872 }
1873
1874 static void
1875 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* DMATXCTRL: Geric Double VLAN Disable */
1884         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         ctrl &= ~IXGBE_DMATXCTL_GDV;
1886         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1887
1888         /* CTRL_EXT: Global Double VLAN Disable */
1889         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1890         ctrl &= ~IXGBE_EXTENDED_VLAN;
1891         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1892
1893 }
1894
1895 static void
1896 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1897 {
1898         struct ixgbe_hw *hw =
1899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         uint32_t ctrl;
1901
1902         PMD_INIT_FUNC_TRACE();
1903
1904         /* DMATXCTRL: Geric Double VLAN Enable */
1905         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906         ctrl |= IXGBE_DMATXCTL_GDV;
1907         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1908
1909         /* CTRL_EXT: Global Double VLAN Enable */
1910         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1911         ctrl |= IXGBE_EXTENDED_VLAN;
1912         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1913
1914         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1915         if (hw->mac.type == ixgbe_mac_X550 ||
1916             hw->mac.type == ixgbe_mac_X550EM_x ||
1917             hw->mac.type == ixgbe_mac_X550EM_a) {
1918                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1919                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1920                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1921         }
1922
1923         /*
1924          * VET EXT field in the EXVET register = 0x8100 by default
1925          * So no need to change. Same to VT field of DMATXCTL register
1926          */
1927 }
1928
1929 static void
1930 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1931 {
1932         if (mask & ETH_VLAN_STRIP_MASK) {
1933                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1934                         ixgbe_vlan_hw_strip_enable_all(dev);
1935                 else
1936                         ixgbe_vlan_hw_strip_disable_all(dev);
1937         }
1938
1939         if (mask & ETH_VLAN_FILTER_MASK) {
1940                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1941                         ixgbe_vlan_hw_filter_enable(dev);
1942                 else
1943                         ixgbe_vlan_hw_filter_disable(dev);
1944         }
1945
1946         if (mask & ETH_VLAN_EXTEND_MASK) {
1947                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1948                         ixgbe_vlan_hw_extend_enable(dev);
1949                 else
1950                         ixgbe_vlan_hw_extend_disable(dev);
1951         }
1952 }
1953
1954 static void
1955 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1960         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1961
1962         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1964 }
1965
1966 static int
1967 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1968 {
1969         switch (nb_rx_q) {
1970         case 1:
1971         case 2:
1972                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1973                 break;
1974         case 4:
1975                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1976                 break;
1977         default:
1978                 return -EINVAL;
1979         }
1980
1981         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1982                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1983         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1984                 dev->pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1985         return 0;
1986 }
1987
1988 static int
1989 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1990 {
1991         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1994         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1995
1996         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1997                 /* check multi-queue mode */
1998                 switch (dev_conf->rxmode.mq_mode) {
1999                 case ETH_MQ_RX_VMDQ_DCB:
2000                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2001                         break;
2002                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2003                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2004                         PMD_INIT_LOG(ERR, "SRIOV active,"
2005                                         " unsupported mq_mode rx %d.",
2006                                         dev_conf->rxmode.mq_mode);
2007                         return -EINVAL;
2008                 case ETH_MQ_RX_RSS:
2009                 case ETH_MQ_RX_VMDQ_RSS:
2010                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2011                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2012                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2013                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2014                                                 " invalid queue number"
2015                                                 " for VMDQ RSS, allowed"
2016                                                 " value are 1, 2 or 4.");
2017                                         return -EINVAL;
2018                                 }
2019                         break;
2020                 case ETH_MQ_RX_VMDQ_ONLY:
2021                 case ETH_MQ_RX_NONE:
2022                         /* if nothing mq mode configure, use default scheme */
2023                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2024                         break;
2025                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2026                         /* SRIOV only works in VMDq enable mode */
2027                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2028                                         " wrong mq_mode rx %d.",
2029                                         dev_conf->rxmode.mq_mode);
2030                         return -EINVAL;
2031                 }
2032
2033                 switch (dev_conf->txmode.mq_mode) {
2034                 case ETH_MQ_TX_VMDQ_DCB:
2035                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2036                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2037                         break;
2038                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2039                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2040                         break;
2041                 }
2042
2043                 /* check valid queue number */
2044                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2045                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2046                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2047                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2048                                         " must be less than or equal to %d.",
2049                                         nb_rx_q, nb_tx_q,
2050                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2051                         return -EINVAL;
2052                 }
2053         } else {
2054                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2055                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2056                                           " not supported.");
2057                         return -EINVAL;
2058                 }
2059                 /* check configuration for vmdb+dcb mode */
2060                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2061                         const struct rte_eth_vmdq_dcb_conf *conf;
2062
2063                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2064                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2065                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2066                                 return -EINVAL;
2067                         }
2068                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2069                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2070                                conf->nb_queue_pools == ETH_32_POOLS)) {
2071                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2072                                                 " nb_queue_pools must be %d or %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2078                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2079
2080                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2081                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2082                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2083                                 return -EINVAL;
2084                         }
2085                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2086                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2087                                conf->nb_queue_pools == ETH_32_POOLS)) {
2088                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2089                                                 " nb_queue_pools != %d and"
2090                                                 " nb_queue_pools != %d.",
2091                                                 ETH_16_POOLS, ETH_32_POOLS);
2092                                 return -EINVAL;
2093                         }
2094                 }
2095
2096                 /* For DCB mode check our configuration before we go further */
2097                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2098                         const struct rte_eth_dcb_rx_conf *conf;
2099
2100                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2101                         if (!(conf->nb_tcs == ETH_4_TCS ||
2102                                conf->nb_tcs == ETH_8_TCS)) {
2103                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2104                                                 " and nb_tcs != %d.",
2105                                                 ETH_4_TCS, ETH_8_TCS);
2106                                 return -EINVAL;
2107                         }
2108                 }
2109
2110                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2111                         const struct rte_eth_dcb_tx_conf *conf;
2112
2113                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2114                         if (!(conf->nb_tcs == ETH_4_TCS ||
2115                                conf->nb_tcs == ETH_8_TCS)) {
2116                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2117                                                 " and nb_tcs != %d.",
2118                                                 ETH_4_TCS, ETH_8_TCS);
2119                                 return -EINVAL;
2120                         }
2121                 }
2122
2123                 /*
2124                  * When DCB/VT is off, maximum number of queues changes,
2125                  * except for 82598EB, which remains constant.
2126                  */
2127                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2128                                 hw->mac.type != ixgbe_mac_82598EB) {
2129                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2130                                 PMD_INIT_LOG(ERR,
2131                                              "Neither VT nor DCB are enabled, "
2132                                              "nb_tx_q > %d.",
2133                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2134                                 return -EINVAL;
2135                         }
2136                 }
2137         }
2138         return 0;
2139 }
2140
2141 static int
2142 ixgbe_dev_configure(struct rte_eth_dev *dev)
2143 {
2144         struct ixgbe_interrupt *intr =
2145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2146         struct ixgbe_adapter *adapter =
2147                 (struct ixgbe_adapter *)dev->data->dev_private;
2148         int ret;
2149
2150         PMD_INIT_FUNC_TRACE();
2151         /* multipe queue mode checking */
2152         ret  = ixgbe_check_mq_mode(dev);
2153         if (ret != 0) {
2154                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2155                             ret);
2156                 return ret;
2157         }
2158
2159         /* set flag to update link status after init */
2160         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2161
2162         /*
2163          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2164          * allocation or vector Rx preconditions we will reset it.
2165          */
2166         adapter->rx_bulk_alloc_allowed = true;
2167         adapter->rx_vec_allowed = true;
2168
2169         return 0;
2170 }
2171
2172 static void
2173 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2174 {
2175         struct ixgbe_hw *hw =
2176                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         struct ixgbe_interrupt *intr =
2178                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2179         uint32_t gpie;
2180
2181         /* only set up it on X550EM_X */
2182         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2183                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2184                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2185                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2186                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2187                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2188         }
2189 }
2190
2191 /*
2192  * Configure device link speed and setup link.
2193  * It returns 0 on success.
2194  */
2195 static int
2196 ixgbe_dev_start(struct rte_eth_dev *dev)
2197 {
2198         struct ixgbe_hw *hw =
2199                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct ixgbe_vf_info *vfinfo =
2201                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2202         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2203         uint32_t intr_vector = 0;
2204         int err, link_up = 0, negotiate = 0;
2205         uint32_t speed = 0;
2206         int mask = 0;
2207         int status;
2208         uint16_t vf, idx;
2209         uint32_t *link_speeds;
2210
2211         PMD_INIT_FUNC_TRACE();
2212
2213         /* IXGBE devices don't support:
2214         *    - half duplex (checked afterwards for valid speeds)
2215         *    - fixed speed: TODO implement
2216         */
2217         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2218                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2219                              dev->data->port_id);
2220                 return -EINVAL;
2221         }
2222
2223         /* disable uio/vfio intr/eventfd mapping */
2224         rte_intr_disable(intr_handle);
2225
2226         /* stop adapter */
2227         hw->adapter_stopped = 0;
2228         ixgbe_stop_adapter(hw);
2229
2230         /* reinitialize adapter
2231          * this calls reset and start
2232          */
2233         status = ixgbe_pf_reset_hw(hw);
2234         if (status != 0)
2235                 return -1;
2236         hw->mac.ops.start_hw(hw);
2237         hw->mac.get_link_status = true;
2238
2239         /* configure PF module if SRIOV enabled */
2240         ixgbe_pf_host_configure(dev);
2241
2242         ixgbe_dev_phy_intr_setup(dev);
2243
2244         /* check and configure queue intr-vector mapping */
2245         if ((rte_intr_cap_multiple(intr_handle) ||
2246              !RTE_ETH_DEV_SRIOV(dev).active) &&
2247             dev->data->dev_conf.intr_conf.rxq != 0) {
2248                 intr_vector = dev->data->nb_rx_queues;
2249                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2250                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2251                                         IXGBE_MAX_INTR_QUEUE_NUM);
2252                         return -ENOTSUP;
2253                 }
2254                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2255                         return -1;
2256         }
2257
2258         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2259                 intr_handle->intr_vec =
2260                         rte_zmalloc("intr_vec",
2261                                     dev->data->nb_rx_queues * sizeof(int), 0);
2262                 if (intr_handle->intr_vec == NULL) {
2263                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2264                                      " intr_vec\n", dev->data->nb_rx_queues);
2265                         return -ENOMEM;
2266                 }
2267         }
2268
2269         /* confiugre msix for sleep until rx interrupt */
2270         ixgbe_configure_msix(dev);
2271
2272         /* initialize transmission unit */
2273         ixgbe_dev_tx_init(dev);
2274
2275         /* This can fail when allocating mbufs for descriptor rings */
2276         err = ixgbe_dev_rx_init(dev);
2277         if (err) {
2278                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2279                 goto error;
2280         }
2281
2282     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2283                 ETH_VLAN_EXTEND_MASK;
2284         ixgbe_vlan_offload_set(dev, mask);
2285
2286         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2287                 /* Enable vlan filtering for VMDq */
2288                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2289         }
2290
2291         /* Configure DCB hw */
2292         ixgbe_configure_dcb(dev);
2293
2294         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2295                 err = ixgbe_fdir_configure(dev);
2296                 if (err)
2297                         goto error;
2298         }
2299
2300         /* Restore vf rate limit */
2301         if (vfinfo != NULL) {
2302                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2303                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2304                                 if (vfinfo[vf].tx_rate[idx] != 0)
2305                                         ixgbe_set_vf_rate_limit(dev, vf,
2306                                                 vfinfo[vf].tx_rate[idx],
2307                                                 1 << idx);
2308         }
2309
2310         ixgbe_restore_statistics_mapping(dev);
2311
2312         err = ixgbe_dev_rxtx_start(dev);
2313         if (err < 0) {
2314                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2315                 goto error;
2316         }
2317
2318         /* Skip link setup if loopback mode is enabled for 82599. */
2319         if (hw->mac.type == ixgbe_mac_82599EB &&
2320                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2321                 goto skip_link_setup;
2322
2323         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2324                 err = hw->mac.ops.setup_sfp(hw);
2325                 if (err)
2326                         goto error;
2327         }
2328
2329         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2330                 /* Turn on the copper */
2331                 ixgbe_set_phy_power(hw, true);
2332         } else {
2333                 /* Turn on the laser */
2334                 ixgbe_enable_tx_laser(hw);
2335         }
2336
2337         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2338         if (err)
2339                 goto error;
2340         dev->data->dev_link.link_status = link_up;
2341
2342         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2343         if (err)
2344                 goto error;
2345
2346         link_speeds = &dev->data->dev_conf.link_speeds;
2347         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2348                         ETH_LINK_SPEED_10G)) {
2349                 PMD_INIT_LOG(ERR, "Invalid link setting");
2350                 goto error;
2351         }
2352
2353         speed = 0x0;
2354         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2355                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2356                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2357                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2358         } else {
2359                 if (*link_speeds & ETH_LINK_SPEED_10G)
2360                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2361                 if (*link_speeds & ETH_LINK_SPEED_1G)
2362                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2363                 if (*link_speeds & ETH_LINK_SPEED_100M)
2364                         speed |= IXGBE_LINK_SPEED_100_FULL;
2365         }
2366
2367         err = ixgbe_setup_link(hw, speed, link_up);
2368         if (err)
2369                 goto error;
2370
2371 skip_link_setup:
2372
2373         if (rte_intr_allow_others(intr_handle)) {
2374                 /* check if lsc interrupt is enabled */
2375                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2376                         ixgbe_dev_lsc_interrupt_setup(dev);
2377         } else {
2378                 rte_intr_callback_unregister(intr_handle,
2379                                              ixgbe_dev_interrupt_handler,
2380                                              (void *)dev);
2381                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2382                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2383                                      " no intr multiplex\n");
2384         }
2385
2386         /* check if rxq interrupt is enabled */
2387         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2388             rte_intr_dp_is_en(intr_handle))
2389                 ixgbe_dev_rxq_interrupt_setup(dev);
2390
2391         /* enable uio/vfio intr/eventfd mapping */
2392         rte_intr_enable(intr_handle);
2393
2394         /* resume enabled intr since hw reset */
2395         ixgbe_enable_intr(dev);
2396
2397         return 0;
2398
2399 error:
2400         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2401         ixgbe_dev_clear_queues(dev);
2402         return -EIO;
2403 }
2404
2405 /*
2406  * Stop device: disable rx and tx functions to allow for reconfiguring.
2407  */
2408 static void
2409 ixgbe_dev_stop(struct rte_eth_dev *dev)
2410 {
2411         struct rte_eth_link link;
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct ixgbe_vf_info *vfinfo =
2415                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2416         struct ixgbe_filter_info *filter_info =
2417                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2418         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2419         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2420         int vf;
2421
2422         PMD_INIT_FUNC_TRACE();
2423
2424         /* disable interrupts */
2425         ixgbe_disable_intr(hw);
2426
2427         /* reset the NIC */
2428         ixgbe_pf_reset_hw(hw);
2429         hw->adapter_stopped = 0;
2430
2431         /* stop adapter */
2432         ixgbe_stop_adapter(hw);
2433
2434         for (vf = 0; vfinfo != NULL &&
2435                      vf < dev->pci_dev->max_vfs; vf++)
2436                 vfinfo[vf].clear_to_send = false;
2437
2438         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2439                 /* Turn off the copper */
2440                 ixgbe_set_phy_power(hw, false);
2441         } else {
2442                 /* Turn off the laser */
2443                 ixgbe_disable_tx_laser(hw);
2444         }
2445
2446         ixgbe_dev_clear_queues(dev);
2447
2448         /* Clear stored conf */
2449         dev->data->scattered_rx = 0;
2450         dev->data->lro = 0;
2451
2452         /* Clear recorded link status */
2453         memset(&link, 0, sizeof(link));
2454         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2455
2456         /* Remove all ntuple filters of the device */
2457         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2458              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2459                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2460                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2461                              p_5tuple, entries);
2462                 rte_free(p_5tuple);
2463         }
2464         memset(filter_info->fivetuple_mask, 0,
2465                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2466
2467         if (!rte_intr_allow_others(intr_handle))
2468                 /* resume to the default handler */
2469                 rte_intr_callback_register(intr_handle,
2470                                            ixgbe_dev_interrupt_handler,
2471                                            (void *)dev);
2472
2473         /* Clean datapath event and queue/vec mapping */
2474         rte_intr_efd_disable(intr_handle);
2475         if (intr_handle->intr_vec != NULL) {
2476                 rte_free(intr_handle->intr_vec);
2477                 intr_handle->intr_vec = NULL;
2478         }
2479 }
2480
2481 /*
2482  * Set device link up: enable tx.
2483  */
2484 static int
2485 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2486 {
2487         struct ixgbe_hw *hw =
2488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         if (hw->mac.type == ixgbe_mac_82599EB) {
2490 #ifdef RTE_NIC_BYPASS
2491                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2492                         /* Not suported in bypass mode */
2493                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2494                                      "by device id 0x%x", hw->device_id);
2495                         return -ENOTSUP;
2496                 }
2497 #endif
2498         }
2499
2500         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2501                 /* Turn on the copper */
2502                 ixgbe_set_phy_power(hw, true);
2503         } else {
2504                 /* Turn on the laser */
2505                 ixgbe_enable_tx_laser(hw);
2506         }
2507
2508         return 0;
2509 }
2510
2511 /*
2512  * Set device link down: disable tx.
2513  */
2514 static int
2515 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2516 {
2517         struct ixgbe_hw *hw =
2518                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         if (hw->mac.type == ixgbe_mac_82599EB) {
2520 #ifdef RTE_NIC_BYPASS
2521                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2522                         /* Not suported in bypass mode */
2523                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2524                                      "by device id 0x%x", hw->device_id);
2525                         return -ENOTSUP;
2526                 }
2527 #endif
2528         }
2529
2530         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2531                 /* Turn off the copper */
2532                 ixgbe_set_phy_power(hw, false);
2533         } else {
2534                 /* Turn off the laser */
2535                 ixgbe_disable_tx_laser(hw);
2536         }
2537
2538         return 0;
2539 }
2540
2541 /*
2542  * Reest and stop device.
2543  */
2544 static void
2545 ixgbe_dev_close(struct rte_eth_dev *dev)
2546 {
2547         struct ixgbe_hw *hw =
2548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549
2550         PMD_INIT_FUNC_TRACE();
2551
2552         ixgbe_pf_reset_hw(hw);
2553
2554         ixgbe_dev_stop(dev);
2555         hw->adapter_stopped = 1;
2556
2557         ixgbe_dev_free_queues(dev);
2558
2559         ixgbe_disable_pcie_master(hw);
2560
2561         /* reprogram the RAR[0] in case user changed it. */
2562         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2563 }
2564
2565 static void
2566 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2567                            struct ixgbe_hw_stats *hw_stats,
2568                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2569                            uint64_t *total_qprc, uint64_t *total_qprdc)
2570 {
2571         uint32_t bprc, lxon, lxoff, total;
2572         uint32_t delta_gprc = 0;
2573         unsigned i;
2574         /* Workaround for RX byte count not including CRC bytes when CRC
2575 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2576          * is disabled.
2577 +        */
2578         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2579                         IXGBE_HLREG0_RXCRCSTRP);
2580
2581         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2582         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2583         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2584         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2585
2586         for (i = 0; i < 8; i++) {
2587                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2588
2589                 /* global total per queue */
2590                 hw_stats->mpc[i] += mp;
2591                 /* Running comprehensive total for stats display */
2592                 *total_missed_rx += hw_stats->mpc[i];
2593                 if (hw->mac.type == ixgbe_mac_82598EB) {
2594                         hw_stats->rnbc[i] +=
2595                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2596                         hw_stats->pxonrxc[i] +=
2597                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2598                         hw_stats->pxoffrxc[i] +=
2599                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2600                 } else {
2601                         hw_stats->pxonrxc[i] +=
2602                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2603                         hw_stats->pxoffrxc[i] +=
2604                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2605                         hw_stats->pxon2offc[i] +=
2606                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2607                 }
2608                 hw_stats->pxontxc[i] +=
2609                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2610                 hw_stats->pxofftxc[i] +=
2611                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2612         }
2613         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2614                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2615                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2616                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2617
2618                 delta_gprc += delta_qprc;
2619
2620                 hw_stats->qprc[i] += delta_qprc;
2621                 hw_stats->qptc[i] += delta_qptc;
2622
2623                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2624                 hw_stats->qbrc[i] +=
2625                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2626                 if (crc_strip == 0)
2627                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2628
2629                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2630                 hw_stats->qbtc[i] +=
2631                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2632
2633                 hw_stats->qprdc[i] += delta_qprdc;
2634                 *total_qprdc += hw_stats->qprdc[i];
2635
2636                 *total_qprc += hw_stats->qprc[i];
2637                 *total_qbrc += hw_stats->qbrc[i];
2638         }
2639         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2640         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2641         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2642
2643         /*
2644          * An errata states that gprc actually counts good + missed packets:
2645          * Workaround to set gprc to summated queue packet receives
2646          */
2647         hw_stats->gprc = *total_qprc;
2648
2649         if (hw->mac.type != ixgbe_mac_82598EB) {
2650                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2651                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2652                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2653                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2654                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2655                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2656                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2657                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2658         } else {
2659                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2660                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2661                 /* 82598 only has a counter in the high register */
2662                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2663                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2664                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2665         }
2666         uint64_t old_tpr = hw_stats->tpr;
2667
2668         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2669         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2670
2671         if (crc_strip == 0)
2672                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2673
2674         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2675         hw_stats->gptc += delta_gptc;
2676         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2677         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2678
2679         /*
2680          * Workaround: mprc hardware is incorrectly counting
2681          * broadcasts, so for now we subtract those.
2682          */
2683         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2684         hw_stats->bprc += bprc;
2685         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2686         if (hw->mac.type == ixgbe_mac_82598EB)
2687                 hw_stats->mprc -= bprc;
2688
2689         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2690         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2691         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2692         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2693         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2694         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2695
2696         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2697         hw_stats->lxontxc += lxon;
2698         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2699         hw_stats->lxofftxc += lxoff;
2700         total = lxon + lxoff;
2701
2702         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2703         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2704         hw_stats->gptc -= total;
2705         hw_stats->mptc -= total;
2706         hw_stats->ptc64 -= total;
2707         hw_stats->gotc -= total * ETHER_MIN_LEN;
2708
2709         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2710         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2711         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2712         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2713         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2714         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2715         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2716         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2717         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2718         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2719         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2720         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2721         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2722         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2723         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2724         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2725         /* Only read FCOE on 82599 */
2726         if (hw->mac.type != ixgbe_mac_82598EB) {
2727                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2728                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2729                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2730                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2731                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2732         }
2733
2734         /* Flow Director Stats registers */
2735         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2736         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2737 }
2738
2739 /*
2740  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2741  */
2742 static void
2743 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2744 {
2745         struct ixgbe_hw *hw =
2746                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747         struct ixgbe_hw_stats *hw_stats =
2748                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2749         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2750         unsigned i;
2751
2752         total_missed_rx = 0;
2753         total_qbrc = 0;
2754         total_qprc = 0;
2755         total_qprdc = 0;
2756
2757         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2758                         &total_qprc, &total_qprdc);
2759
2760         if (stats == NULL)
2761                 return;
2762
2763         /* Fill out the rte_eth_stats statistics structure */
2764         stats->ipackets = total_qprc;
2765         stats->ibytes = total_qbrc;
2766         stats->opackets = hw_stats->gptc;
2767         stats->obytes = hw_stats->gotc;
2768
2769         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2770                 stats->q_ipackets[i] = hw_stats->qprc[i];
2771                 stats->q_opackets[i] = hw_stats->qptc[i];
2772                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2773                 stats->q_obytes[i] = hw_stats->qbtc[i];
2774                 stats->q_errors[i] = hw_stats->qprdc[i];
2775         }
2776
2777         /* Rx Errors */
2778         stats->imissed  = total_missed_rx;
2779         stats->ierrors  = hw_stats->crcerrs +
2780                           hw_stats->mspdc +
2781                           hw_stats->rlec +
2782                           hw_stats->ruc +
2783                           hw_stats->roc +
2784                           hw_stats->illerrc +
2785                           hw_stats->errbc +
2786                           hw_stats->rfc +
2787                           hw_stats->fccrc +
2788                           hw_stats->fclast;
2789
2790         /* Tx Errors */
2791         stats->oerrors  = 0;
2792 }
2793
2794 static void
2795 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2796 {
2797         struct ixgbe_hw_stats *stats =
2798                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2799
2800         /* HW registers are cleared on read */
2801         ixgbe_dev_stats_get(dev, NULL);
2802
2803         /* Reset software totals */
2804         memset(stats, 0, sizeof(*stats));
2805 }
2806
2807 /* This function calculates the number of xstats based on the current config */
2808 static unsigned
2809 ixgbe_xstats_calc_num(void) {
2810         return IXGBE_NB_HW_STATS +
2811                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2812                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2813 }
2814
2815 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2816         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2817 {
2818         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2819         unsigned stat, i, count;
2820
2821         if (xstats_names != NULL) {
2822                 count = 0;
2823
2824                 /* Note: limit >= cnt_stats checked upstream
2825                  * in rte_eth_xstats_names()
2826                  */
2827
2828                 /* Extended stats from ixgbe_hw_stats */
2829                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2830                         snprintf(xstats_names[count].name,
2831                                 sizeof(xstats_names[count].name),
2832                                 "%s",
2833                                 rte_ixgbe_stats_strings[i].name);
2834                         count++;
2835                 }
2836
2837                 /* RX Priority Stats */
2838                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2839                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2840                                 snprintf(xstats_names[count].name,
2841                                         sizeof(xstats_names[count].name),
2842                                         "rx_priority%u_%s", i,
2843                                         rte_ixgbe_rxq_strings[stat].name);
2844                                 count++;
2845                         }
2846                 }
2847
2848                 /* TX Priority Stats */
2849                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2850                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2851                                 snprintf(xstats_names[count].name,
2852                                         sizeof(xstats_names[count].name),
2853                                         "tx_priority%u_%s", i,
2854                                         rte_ixgbe_txq_strings[stat].name);
2855                                 count++;
2856                         }
2857                 }
2858         }
2859         return cnt_stats;
2860 }
2861
2862 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2863         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2864 {
2865         unsigned i;
2866
2867         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2868                 return -ENOMEM;
2869
2870         if (xstats_names != NULL)
2871                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2872                         snprintf(xstats_names[i].name,
2873                                 sizeof(xstats_names[i].name),
2874                                 "%s", rte_ixgbevf_stats_strings[i].name);
2875         return IXGBEVF_NB_XSTATS;
2876 }
2877
2878 static int
2879 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2880                                          unsigned n)
2881 {
2882         struct ixgbe_hw *hw =
2883                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct ixgbe_hw_stats *hw_stats =
2885                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2886         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2887         unsigned i, stat, count = 0;
2888
2889         count = ixgbe_xstats_calc_num();
2890
2891         if (n < count)
2892                 return count;
2893
2894         total_missed_rx = 0;
2895         total_qbrc = 0;
2896         total_qprc = 0;
2897         total_qprdc = 0;
2898
2899         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2900                                    &total_qprc, &total_qprdc);
2901
2902         /* If this is a reset xstats is NULL, and we have cleared the
2903          * registers by reading them.
2904          */
2905         if (!xstats)
2906                 return 0;
2907
2908         /* Extended stats from ixgbe_hw_stats */
2909         count = 0;
2910         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2911                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2912                                 rte_ixgbe_stats_strings[i].offset);
2913                 xstats[count].id = count;
2914                 count++;
2915         }
2916
2917         /* RX Priority Stats */
2918         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2919                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2920                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2921                                         rte_ixgbe_rxq_strings[stat].offset +
2922                                         (sizeof(uint64_t) * i));
2923                         xstats[count].id = count;
2924                         count++;
2925                 }
2926         }
2927
2928         /* TX Priority Stats */
2929         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2930                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2931                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2932                                         rte_ixgbe_txq_strings[stat].offset +
2933                                         (sizeof(uint64_t) * i));
2934                         xstats[count].id = count;
2935                         count++;
2936                 }
2937         }
2938         return count;
2939 }
2940
2941 static void
2942 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2943 {
2944         struct ixgbe_hw_stats *stats =
2945                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2946
2947         unsigned count = ixgbe_xstats_calc_num();
2948
2949         /* HW registers are cleared on read */
2950         ixgbe_dev_xstats_get(dev, NULL, count);
2951
2952         /* Reset software totals */
2953         memset(stats, 0, sizeof(*stats));
2954 }
2955
2956 static void
2957 ixgbevf_update_stats(struct rte_eth_dev *dev)
2958 {
2959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2961                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2962
2963         /* Good Rx packet, include VF loopback */
2964         UPDATE_VF_STAT(IXGBE_VFGPRC,
2965             hw_stats->last_vfgprc, hw_stats->vfgprc);
2966
2967         /* Good Rx octets, include VF loopback */
2968         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2969             hw_stats->last_vfgorc, hw_stats->vfgorc);
2970
2971         /* Good Tx packet, include VF loopback */
2972         UPDATE_VF_STAT(IXGBE_VFGPTC,
2973             hw_stats->last_vfgptc, hw_stats->vfgptc);
2974
2975         /* Good Tx octets, include VF loopback */
2976         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2977             hw_stats->last_vfgotc, hw_stats->vfgotc);
2978
2979         /* Rx Multicst Packet */
2980         UPDATE_VF_STAT(IXGBE_VFMPRC,
2981             hw_stats->last_vfmprc, hw_stats->vfmprc);
2982 }
2983
2984 static int
2985 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2986                        unsigned n)
2987 {
2988         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2989                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2990         unsigned i;
2991
2992         if (n < IXGBEVF_NB_XSTATS)
2993                 return IXGBEVF_NB_XSTATS;
2994
2995         ixgbevf_update_stats(dev);
2996
2997         if (!xstats)
2998                 return 0;
2999
3000         /* Extended stats */
3001         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3002                 xstats[i].id = i;
3003                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3004                         rte_ixgbevf_stats_strings[i].offset);
3005         }
3006
3007         return IXGBEVF_NB_XSTATS;
3008 }
3009
3010 static void
3011 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3012 {
3013         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3014                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3015
3016         ixgbevf_update_stats(dev);
3017
3018         if (stats == NULL)
3019                 return;
3020
3021         stats->ipackets = hw_stats->vfgprc;
3022         stats->ibytes = hw_stats->vfgorc;
3023         stats->opackets = hw_stats->vfgptc;
3024         stats->obytes = hw_stats->vfgotc;
3025 }
3026
3027 static void
3028 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3029 {
3030         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3031                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3032
3033         /* Sync HW register to the last stats */
3034         ixgbevf_dev_stats_get(dev, NULL);
3035
3036         /* reset HW current stats*/
3037         hw_stats->vfgprc = 0;
3038         hw_stats->vfgorc = 0;
3039         hw_stats->vfgptc = 0;
3040         hw_stats->vfgotc = 0;
3041 }
3042
3043 static void
3044 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3045 {
3046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3048
3049         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3050         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3051         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3052                 /*
3053                  * When DCB/VT is off, maximum number of queues changes,
3054                  * except for 82598EB, which remains constant.
3055                  */
3056                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3057                                 hw->mac.type != ixgbe_mac_82598EB)
3058                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3059         }
3060         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3061         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3062         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3063         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3064         dev_info->max_vfs = dev->pci_dev->max_vfs;
3065         if (hw->mac.type == ixgbe_mac_82598EB)
3066                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3067         else
3068                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3069         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3070         dev_info->rx_offload_capa =
3071                 DEV_RX_OFFLOAD_VLAN_STRIP |
3072                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3073                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3074                 DEV_RX_OFFLOAD_TCP_CKSUM;
3075
3076         /*
3077          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3078          * mode.
3079          */
3080         if ((hw->mac.type == ixgbe_mac_82599EB ||
3081              hw->mac.type == ixgbe_mac_X540) &&
3082             !RTE_ETH_DEV_SRIOV(dev).active)
3083                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3084
3085         if (hw->mac.type == ixgbe_mac_X550 ||
3086             hw->mac.type == ixgbe_mac_X550EM_x ||
3087             hw->mac.type == ixgbe_mac_X550EM_a)
3088                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3089
3090         dev_info->tx_offload_capa =
3091                 DEV_TX_OFFLOAD_VLAN_INSERT |
3092                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3093                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3094                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3095                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3096                 DEV_TX_OFFLOAD_TCP_TSO;
3097
3098         if (hw->mac.type == ixgbe_mac_X550 ||
3099             hw->mac.type == ixgbe_mac_X550EM_x ||
3100             hw->mac.type == ixgbe_mac_X550EM_a)
3101                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3102
3103         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3104                 .rx_thresh = {
3105                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3106                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3107                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3108                 },
3109                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3110                 .rx_drop_en = 0,
3111         };
3112
3113         dev_info->default_txconf = (struct rte_eth_txconf) {
3114                 .tx_thresh = {
3115                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3116                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3117                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3118                 },
3119                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3120                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3121                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3122                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3123         };
3124
3125         dev_info->rx_desc_lim = rx_desc_lim;
3126         dev_info->tx_desc_lim = tx_desc_lim;
3127
3128         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3129         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3130         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3131
3132         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3133         if (hw->mac.type == ixgbe_mac_X540 ||
3134             hw->mac.type == ixgbe_mac_X540_vf ||
3135             hw->mac.type == ixgbe_mac_X550 ||
3136             hw->mac.type == ixgbe_mac_X550_vf) {
3137                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3138         }
3139 }
3140
3141 static const uint32_t *
3142 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3143 {
3144         static const uint32_t ptypes[] = {
3145                 /* For non-vec functions,
3146                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3147                  * for vec functions,
3148                  * refers to _recv_raw_pkts_vec().
3149                  */
3150                 RTE_PTYPE_L2_ETHER,
3151                 RTE_PTYPE_L3_IPV4,
3152                 RTE_PTYPE_L3_IPV4_EXT,
3153                 RTE_PTYPE_L3_IPV6,
3154                 RTE_PTYPE_L3_IPV6_EXT,
3155                 RTE_PTYPE_L4_SCTP,
3156                 RTE_PTYPE_L4_TCP,
3157                 RTE_PTYPE_L4_UDP,
3158                 RTE_PTYPE_TUNNEL_IP,
3159                 RTE_PTYPE_INNER_L3_IPV6,
3160                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3161                 RTE_PTYPE_INNER_L4_TCP,
3162                 RTE_PTYPE_INNER_L4_UDP,
3163                 RTE_PTYPE_UNKNOWN
3164         };
3165
3166         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3167             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3168             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3169             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3170                 return ptypes;
3171         return NULL;
3172 }
3173
3174 static void
3175 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3176                      struct rte_eth_dev_info *dev_info)
3177 {
3178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179
3180         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3181         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3182         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3183         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3184         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3185         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3186         dev_info->max_vfs = dev->pci_dev->max_vfs;
3187         if (hw->mac.type == ixgbe_mac_82598EB)
3188                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3189         else
3190                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3191         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3192                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3193                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3194                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3195         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3196                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3197                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3198                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3199                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3200                                 DEV_TX_OFFLOAD_TCP_TSO;
3201
3202         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3203                 .rx_thresh = {
3204                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3205                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3206                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3207                 },
3208                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3209                 .rx_drop_en = 0,
3210         };
3211
3212         dev_info->default_txconf = (struct rte_eth_txconf) {
3213                 .tx_thresh = {
3214                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3215                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3216                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3217                 },
3218                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3219                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3220                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3221                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3222         };
3223
3224         dev_info->rx_desc_lim = rx_desc_lim;
3225         dev_info->tx_desc_lim = tx_desc_lim;
3226 }
3227
3228 static int
3229 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3230                    int *link_up, int wait_to_complete __rte_unused)
3231 {
3232         struct ixgbe_mbx_info *mbx = &hw->mbx;
3233         struct ixgbe_mac_info *mac = &hw->mac;
3234         uint32_t links_reg, in_msg;
3235         int ret_val = 0;
3236
3237         /* If we were hit with a reset drop the link */
3238         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3239                 mac->get_link_status = true;
3240
3241         if (!mac->get_link_status)
3242                 goto out;
3243
3244         /* if link status is down no point in checking to see if pf is up */
3245         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3246         if (!(links_reg & IXGBE_LINKS_UP))
3247                 goto out;
3248
3249         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3250          * before the link status is correct
3251          */
3252         if (mac->type == ixgbe_mac_82599_vf) {
3253                 int i;
3254
3255                 for (i = 0; i < 5; i++) {
3256                         rte_delay_us(100);
3257                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3258
3259                         if (!(links_reg & IXGBE_LINKS_UP))
3260                                 goto out;
3261                 }
3262         }
3263
3264         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3265         case IXGBE_LINKS_SPEED_10G_82599:
3266                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3267                 if (hw->mac.type >= ixgbe_mac_X550) {
3268                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3269                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3270                 }
3271                 break;
3272         case IXGBE_LINKS_SPEED_1G_82599:
3273                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3274                 break;
3275         case IXGBE_LINKS_SPEED_100_82599:
3276                 *speed = IXGBE_LINK_SPEED_100_FULL;
3277                 if (hw->mac.type == ixgbe_mac_X550) {
3278                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3279                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3280                 }
3281                 break;
3282         case IXGBE_LINKS_SPEED_10_X550EM_A:
3283                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3284                 /* Since Reserved in older MAC's */
3285                 if (hw->mac.type >= ixgbe_mac_X550)
3286                         *speed = IXGBE_LINK_SPEED_10_FULL;
3287                 break;
3288         default:
3289                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3290         }
3291
3292         /* if the read failed it could just be a mailbox collision, best wait
3293          * until we are called again and don't report an error
3294          */
3295         if (mbx->ops.read(hw, &in_msg, 1, 0))
3296                 goto out;
3297
3298         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3299                 /* msg is not CTS and is NACK we must have lost CTS status */
3300                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3301                         mac->get_link_status = false;
3302                 goto out;
3303         }
3304
3305         /* the pf is talking, if we timed out in the past we reinit */
3306         if (!mbx->timeout) {
3307                 ret_val = -1;
3308                 goto out;
3309         }
3310
3311         /* if we passed all the tests above then the link is up and we no
3312          * longer need to check for link
3313          */
3314         mac->get_link_status = false;
3315
3316 out:
3317         *link_up = !mac->get_link_status;
3318         return ret_val;
3319 }
3320
3321 /* return 0 means link status changed, -1 means not changed */
3322 static int
3323 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3324                             int wait_to_complete, int vf)
3325 {
3326         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3327         struct rte_eth_link link, old;
3328         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3329         int link_up;
3330         int diag;
3331         int wait = 1;
3332
3333         link.link_status = ETH_LINK_DOWN;
3334         link.link_speed = 0;
3335         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3336         link.link_autoneg = ETH_LINK_AUTONEG;
3337         memset(&old, 0, sizeof(old));
3338         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3339
3340         hw->mac.get_link_status = true;
3341
3342         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3343         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3344                 wait = 0;
3345
3346         if (vf)
3347                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3348         else
3349                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3350
3351         if (diag != 0) {
3352                 link.link_speed = ETH_SPEED_NUM_100M;
3353                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3354                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3355                 if (link.link_status == old.link_status)
3356                         return -1;
3357                 return 0;
3358         }
3359
3360         if (link_up == 0) {
3361                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3362                 if (link.link_status == old.link_status)
3363                         return -1;
3364                 return 0;
3365         }
3366         link.link_status = ETH_LINK_UP;
3367         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3368
3369         switch (link_speed) {
3370         default:
3371         case IXGBE_LINK_SPEED_UNKNOWN:
3372                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3373                 link.link_speed = ETH_SPEED_NUM_100M;
3374                 break;
3375
3376         case IXGBE_LINK_SPEED_100_FULL:
3377                 link.link_speed = ETH_SPEED_NUM_100M;
3378                 break;
3379
3380         case IXGBE_LINK_SPEED_1GB_FULL:
3381                 link.link_speed = ETH_SPEED_NUM_1G;
3382                 break;
3383
3384         case IXGBE_LINK_SPEED_10GB_FULL:
3385                 link.link_speed = ETH_SPEED_NUM_10G;
3386                 break;
3387         }
3388         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3389
3390         if (link.link_status == old.link_status)
3391                 return -1;
3392
3393         return 0;
3394 }
3395
3396 static int
3397 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3398 {
3399         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3400 }
3401
3402 static int
3403 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3404 {
3405         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3406 }
3407
3408 static void
3409 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3410 {
3411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412         uint32_t fctrl;
3413
3414         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3415         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3416         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3417 }
3418
3419 static void
3420 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3421 {
3422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423         uint32_t fctrl;
3424
3425         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3426         fctrl &= (~IXGBE_FCTRL_UPE);
3427         if (dev->data->all_multicast == 1)
3428                 fctrl |= IXGBE_FCTRL_MPE;
3429         else
3430                 fctrl &= (~IXGBE_FCTRL_MPE);
3431         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3432 }
3433
3434 static void
3435 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3436 {
3437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438         uint32_t fctrl;
3439
3440         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3441         fctrl |= IXGBE_FCTRL_MPE;
3442         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3443 }
3444
3445 static void
3446 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3447 {
3448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         uint32_t fctrl;
3450
3451         if (dev->data->promiscuous == 1)
3452                 return; /* must remain in all_multicast mode */
3453
3454         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3455         fctrl &= (~IXGBE_FCTRL_MPE);
3456         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3457 }
3458
3459 /**
3460  * It clears the interrupt causes and enables the interrupt.
3461  * It will be called once only during nic initialized.
3462  *
3463  * @param dev
3464  *  Pointer to struct rte_eth_dev.
3465  *
3466  * @return
3467  *  - On success, zero.
3468  *  - On failure, a negative value.
3469  */
3470 static int
3471 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3472 {
3473         struct ixgbe_interrupt *intr =
3474                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3475
3476         ixgbe_dev_link_status_print(dev);
3477         intr->mask |= IXGBE_EICR_LSC;
3478
3479         return 0;
3480 }
3481
3482 /**
3483  * It clears the interrupt causes and enables the interrupt.
3484  * It will be called once only during nic initialized.
3485  *
3486  * @param dev
3487  *  Pointer to struct rte_eth_dev.
3488  *
3489  * @return
3490  *  - On success, zero.
3491  *  - On failure, a negative value.
3492  */
3493 static int
3494 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3495 {
3496         struct ixgbe_interrupt *intr =
3497                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3498
3499         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3506  *
3507  * @param dev
3508  *  Pointer to struct rte_eth_dev.
3509  *
3510  * @return
3511  *  - On success, zero.
3512  *  - On failure, a negative value.
3513  */
3514 static int
3515 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3516 {
3517         uint32_t eicr;
3518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         struct ixgbe_interrupt *intr =
3520                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3521
3522         /* clear all cause mask */
3523         ixgbe_disable_intr(hw);
3524
3525         /* read-on-clear nic registers here */
3526         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3527         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3528
3529         intr->flags = 0;
3530
3531         /* set flag for async link update */
3532         if (eicr & IXGBE_EICR_LSC)
3533                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3534
3535         if (eicr & IXGBE_EICR_MAILBOX)
3536                 intr->flags |= IXGBE_FLAG_MAILBOX;
3537
3538         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3539             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3540             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3541                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3542
3543         return 0;
3544 }
3545
3546 /**
3547  * It gets and then prints the link status.
3548  *
3549  * @param dev
3550  *  Pointer to struct rte_eth_dev.
3551  *
3552  * @return
3553  *  - On success, zero.
3554  *  - On failure, a negative value.
3555  */
3556 static void
3557 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3558 {
3559         struct rte_eth_link link;
3560
3561         memset(&link, 0, sizeof(link));
3562         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3563         if (link.link_status) {
3564                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3565                                         (int)(dev->data->port_id),
3566                                         (unsigned)link.link_speed,
3567                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3568                                         "full-duplex" : "half-duplex");
3569         } else {
3570                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3571                                 (int)(dev->data->port_id));
3572         }
3573         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3574                                 dev->pci_dev->addr.domain,
3575                                 dev->pci_dev->addr.bus,
3576                                 dev->pci_dev->addr.devid,
3577                                 dev->pci_dev->addr.function);
3578 }
3579
3580 /*
3581  * It executes link_update after knowing an interrupt occurred.
3582  *
3583  * @param dev
3584  *  Pointer to struct rte_eth_dev.
3585  *
3586  * @return
3587  *  - On success, zero.
3588  *  - On failure, a negative value.
3589  */
3590 static int
3591 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3592 {
3593         struct ixgbe_interrupt *intr =
3594                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3595         int64_t timeout;
3596         struct rte_eth_link link;
3597         struct ixgbe_hw *hw =
3598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599
3600         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3601
3602         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3603                 ixgbe_pf_mbx_process(dev);
3604                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3605         }
3606
3607         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3608                 ixgbe_handle_lasi(hw);
3609                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3610         }
3611
3612         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3613                 /* get the link status before link update, for predicting later */
3614                 memset(&link, 0, sizeof(link));
3615                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3616
3617                 ixgbe_dev_link_update(dev, 0);
3618
3619                 /* likely to up */
3620                 if (!link.link_status)
3621                         /* handle it 1 sec later, wait it being stable */
3622                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3623                 /* likely to down */
3624                 else
3625                         /* handle it 4 sec later, wait it being stable */
3626                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3627
3628                 ixgbe_dev_link_status_print(dev);
3629                 intr->mask_original = intr->mask;
3630                 /* only disable lsc interrupt */
3631                 intr->mask &= ~IXGBE_EIMS_LSC;
3632                 if (rte_eal_alarm_set(timeout * 1000,
3633                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3634                         PMD_DRV_LOG(ERR, "Error setting alarm");
3635                 else
3636                         intr->mask = intr->mask_original;
3637         }
3638
3639         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3640         ixgbe_enable_intr(dev);
3641         rte_intr_enable(&dev->pci_dev->intr_handle);
3642
3643         return 0;
3644 }
3645
3646 /**
3647  * Interrupt handler which shall be registered for alarm callback for delayed
3648  * handling specific interrupt to wait for the stable nic state. As the
3649  * NIC interrupt state is not stable for ixgbe after link is just down,
3650  * it needs to wait 4 seconds to get the stable status.
3651  *
3652  * @param handle
3653  *  Pointer to interrupt handle.
3654  * @param param
3655  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3656  *
3657  * @return
3658  *  void
3659  */
3660 static void
3661 ixgbe_dev_interrupt_delayed_handler(void *param)
3662 {
3663         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3664         struct ixgbe_interrupt *intr =
3665                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3666         struct ixgbe_hw *hw =
3667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668         uint32_t eicr;
3669
3670         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3671         if (eicr & IXGBE_EICR_MAILBOX)
3672                 ixgbe_pf_mbx_process(dev);
3673
3674         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3675                 ixgbe_handle_lasi(hw);
3676                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3677         }
3678
3679         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3680                 ixgbe_dev_link_update(dev, 0);
3681                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3682                 ixgbe_dev_link_status_print(dev);
3683                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3684         }
3685
3686         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3687         ixgbe_enable_intr(dev);
3688         rte_intr_enable(&(dev->pci_dev->intr_handle));
3689 }
3690
3691 /**
3692  * Interrupt handler triggered by NIC  for handling
3693  * specific interrupt.
3694  *
3695  * @param handle
3696  *  Pointer to interrupt handle.
3697  * @param param
3698  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3699  *
3700  * @return
3701  *  void
3702  */
3703 static void
3704 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3705                             void *param)
3706 {
3707         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3708
3709         ixgbe_dev_interrupt_get_status(dev);
3710         ixgbe_dev_interrupt_action(dev);
3711 }
3712
3713 static int
3714 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3715 {
3716         struct ixgbe_hw *hw;
3717
3718         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3720 }
3721
3722 static int
3723 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3724 {
3725         struct ixgbe_hw *hw;
3726
3727         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3729 }
3730
3731 static int
3732 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3733 {
3734         struct ixgbe_hw *hw;
3735         uint32_t mflcn_reg;
3736         uint32_t fccfg_reg;
3737         int rx_pause;
3738         int tx_pause;
3739
3740         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741
3742         fc_conf->pause_time = hw->fc.pause_time;
3743         fc_conf->high_water = hw->fc.high_water[0];
3744         fc_conf->low_water = hw->fc.low_water[0];
3745         fc_conf->send_xon = hw->fc.send_xon;
3746         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3747
3748         /*
3749          * Return rx_pause status according to actual setting of
3750          * MFLCN register.
3751          */
3752         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3753         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3754                 rx_pause = 1;
3755         else
3756                 rx_pause = 0;
3757
3758         /*
3759          * Return tx_pause status according to actual setting of
3760          * FCCFG register.
3761          */
3762         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3763         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3764                 tx_pause = 1;
3765         else
3766                 tx_pause = 0;
3767
3768         if (rx_pause && tx_pause)
3769                 fc_conf->mode = RTE_FC_FULL;
3770         else if (rx_pause)
3771                 fc_conf->mode = RTE_FC_RX_PAUSE;
3772         else if (tx_pause)
3773                 fc_conf->mode = RTE_FC_TX_PAUSE;
3774         else
3775                 fc_conf->mode = RTE_FC_NONE;
3776
3777         return 0;
3778 }
3779
3780 static int
3781 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3782 {
3783         struct ixgbe_hw *hw;
3784         int err;
3785         uint32_t rx_buf_size;
3786         uint32_t max_high_water;
3787         uint32_t mflcn;
3788         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3789                 ixgbe_fc_none,
3790                 ixgbe_fc_rx_pause,
3791                 ixgbe_fc_tx_pause,
3792                 ixgbe_fc_full
3793         };
3794
3795         PMD_INIT_FUNC_TRACE();
3796
3797         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3799         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3800
3801         /*
3802          * At least reserve one Ethernet frame for watermark
3803          * high_water/low_water in kilo bytes for ixgbe
3804          */
3805         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3806         if ((fc_conf->high_water > max_high_water) ||
3807                 (fc_conf->high_water < fc_conf->low_water)) {
3808                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3809                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3810                 return -EINVAL;
3811         }
3812
3813         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3814         hw->fc.pause_time     = fc_conf->pause_time;
3815         hw->fc.high_water[0]  = fc_conf->high_water;
3816         hw->fc.low_water[0]   = fc_conf->low_water;
3817         hw->fc.send_xon       = fc_conf->send_xon;
3818         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3819
3820         err = ixgbe_fc_enable(hw);
3821
3822         /* Not negotiated is not an error case */
3823         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3824
3825                 /* check if we want to forward MAC frames - driver doesn't have native
3826                  * capability to do that, so we'll write the registers ourselves */
3827
3828                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3829
3830                 /* set or clear MFLCN.PMCF bit depending on configuration */
3831                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3832                         mflcn |= IXGBE_MFLCN_PMCF;
3833                 else
3834                         mflcn &= ~IXGBE_MFLCN_PMCF;
3835
3836                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3837                 IXGBE_WRITE_FLUSH(hw);
3838
3839                 return 0;
3840         }
3841
3842         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3843         return -EIO;
3844 }
3845
3846 /**
3847  *  ixgbe_pfc_enable_generic - Enable flow control
3848  *  @hw: pointer to hardware structure
3849  *  @tc_num: traffic class number
3850  *  Enable flow control according to the current settings.
3851  */
3852 static int
3853 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3854 {
3855         int ret_val = 0;
3856         uint32_t mflcn_reg, fccfg_reg;
3857         uint32_t reg;
3858         uint32_t fcrtl, fcrth;
3859         uint8_t i;
3860         uint8_t nb_rx_en;
3861
3862         /* Validate the water mark configuration */
3863         if (!hw->fc.pause_time) {
3864                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3865                 goto out;
3866         }
3867
3868         /* Low water mark of zero causes XOFF floods */
3869         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3870                  /* High/Low water can not be 0 */
3871                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3872                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3873                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3874                         goto out;
3875                 }
3876
3877                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3878                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3879                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3880                         goto out;
3881                 }
3882         }
3883         /* Negotiate the fc mode to use */
3884         ixgbe_fc_autoneg(hw);
3885
3886         /* Disable any previous flow control settings */
3887         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3888         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3889
3890         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3891         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3892
3893         switch (hw->fc.current_mode) {
3894         case ixgbe_fc_none:
3895                 /*
3896                  * If the count of enabled RX Priority Flow control >1,
3897                  * and the TX pause can not be disabled
3898                  */
3899                 nb_rx_en = 0;
3900                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3901                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3902                         if (reg & IXGBE_FCRTH_FCEN)
3903                                 nb_rx_en++;
3904                 }
3905                 if (nb_rx_en > 1)
3906                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3907                 break;
3908         case ixgbe_fc_rx_pause:
3909                 /*
3910                  * Rx Flow control is enabled and Tx Flow control is
3911                  * disabled by software override. Since there really
3912                  * isn't a way to advertise that we are capable of RX
3913                  * Pause ONLY, we will advertise that we support both
3914                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3915                  * disable the adapter's ability to send PAUSE frames.
3916                  */
3917                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3918                 /*
3919                  * If the count of enabled RX Priority Flow control >1,
3920                  * and the TX pause can not be disabled
3921                  */
3922                 nb_rx_en = 0;
3923                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3924                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3925                         if (reg & IXGBE_FCRTH_FCEN)
3926                                 nb_rx_en++;
3927                 }
3928                 if (nb_rx_en > 1)
3929                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3930                 break;
3931         case ixgbe_fc_tx_pause:
3932                 /*
3933                  * Tx Flow control is enabled, and Rx Flow control is
3934                  * disabled by software override.
3935                  */
3936                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3937                 break;
3938         case ixgbe_fc_full:
3939                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3940                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3941                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3942                 break;
3943         default:
3944                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3945                 ret_val = IXGBE_ERR_CONFIG;
3946                 goto out;
3947         }
3948
3949         /* Set 802.3x based flow control settings. */
3950         mflcn_reg |= IXGBE_MFLCN_DPF;
3951         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3952         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3953
3954         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3955         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3956                 hw->fc.high_water[tc_num]) {
3957                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3958                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3959                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3960         } else {
3961                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3962                 /*
3963                  * In order to prevent Tx hangs when the internal Tx
3964                  * switch is enabled we must set the high water mark
3965                  * to the maximum FCRTH value.  This allows the Tx
3966                  * switch to function even under heavy Rx workloads.
3967                  */
3968                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3969         }
3970         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3971
3972         /* Configure pause time (2 TCs per register) */
3973         reg = hw->fc.pause_time * 0x00010001;
3974         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3975                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3976
3977         /* Configure flow control refresh threshold value */
3978         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3979
3980 out:
3981         return ret_val;
3982 }
3983
3984 static int
3985 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3986 {
3987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3989
3990         if (hw->mac.type != ixgbe_mac_82598EB) {
3991                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3992         }
3993         return ret_val;
3994 }
3995
3996 static int
3997 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3998 {
3999         int err;
4000         uint32_t rx_buf_size;
4001         uint32_t max_high_water;
4002         uint8_t tc_num;
4003         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4004         struct ixgbe_hw *hw =
4005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4006         struct ixgbe_dcb_config *dcb_config =
4007                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4008
4009         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4010                 ixgbe_fc_none,
4011                 ixgbe_fc_rx_pause,
4012                 ixgbe_fc_tx_pause,
4013                 ixgbe_fc_full
4014         };
4015
4016         PMD_INIT_FUNC_TRACE();
4017
4018         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4019         tc_num = map[pfc_conf->priority];
4020         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4021         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4022         /*
4023          * At least reserve one Ethernet frame for watermark
4024          * high_water/low_water in kilo bytes for ixgbe
4025          */
4026         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4027         if ((pfc_conf->fc.high_water > max_high_water) ||
4028             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4029                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4030                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4031                 return -EINVAL;
4032         }
4033
4034         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4035         hw->fc.pause_time = pfc_conf->fc.pause_time;
4036         hw->fc.send_xon = pfc_conf->fc.send_xon;
4037         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4038         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4039
4040         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4041
4042         /* Not negotiated is not an error case */
4043         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4044                 return 0;
4045
4046         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4047         return -EIO;
4048 }
4049
4050 static int
4051 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4052                           struct rte_eth_rss_reta_entry64 *reta_conf,
4053                           uint16_t reta_size)
4054 {
4055         uint16_t i, sp_reta_size;
4056         uint8_t j, mask;
4057         uint32_t reta, r;
4058         uint16_t idx, shift;
4059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4060         uint32_t reta_reg;
4061
4062         PMD_INIT_FUNC_TRACE();
4063
4064         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4065                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4066                         "NIC.");
4067                 return -ENOTSUP;
4068         }
4069
4070         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4071         if (reta_size != sp_reta_size) {
4072                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4073                         "(%d) doesn't match the number hardware can supported "
4074                         "(%d)\n", reta_size, sp_reta_size);
4075                 return -EINVAL;
4076         }
4077
4078         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4079                 idx = i / RTE_RETA_GROUP_SIZE;
4080                 shift = i % RTE_RETA_GROUP_SIZE;
4081                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4082                                                 IXGBE_4_BIT_MASK);
4083                 if (!mask)
4084                         continue;
4085                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4086                 if (mask == IXGBE_4_BIT_MASK)
4087                         r = 0;
4088                 else
4089                         r = IXGBE_READ_REG(hw, reta_reg);
4090                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4091                         if (mask & (0x1 << j))
4092                                 reta |= reta_conf[idx].reta[shift + j] <<
4093                                                         (CHAR_BIT * j);
4094                         else
4095                                 reta |= r & (IXGBE_8_BIT_MASK <<
4096                                                 (CHAR_BIT * j));
4097                 }
4098                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4099         }
4100
4101         return 0;
4102 }
4103
4104 static int
4105 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4106                          struct rte_eth_rss_reta_entry64 *reta_conf,
4107                          uint16_t reta_size)
4108 {
4109         uint16_t i, sp_reta_size;
4110         uint8_t j, mask;
4111         uint32_t reta;
4112         uint16_t idx, shift;
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t reta_reg;
4115
4116         PMD_INIT_FUNC_TRACE();
4117         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4118         if (reta_size != sp_reta_size) {
4119                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4120                         "(%d) doesn't match the number hardware can supported "
4121                         "(%d)\n", reta_size, sp_reta_size);
4122                 return -EINVAL;
4123         }
4124
4125         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4126                 idx = i / RTE_RETA_GROUP_SIZE;
4127                 shift = i % RTE_RETA_GROUP_SIZE;
4128                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4129                                                 IXGBE_4_BIT_MASK);
4130                 if (!mask)
4131                         continue;
4132
4133                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4134                 reta = IXGBE_READ_REG(hw, reta_reg);
4135                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4136                         if (mask & (0x1 << j))
4137                                 reta_conf[idx].reta[shift + j] =
4138                                         ((reta >> (CHAR_BIT * j)) &
4139                                                 IXGBE_8_BIT_MASK);
4140                 }
4141         }
4142
4143         return 0;
4144 }
4145
4146 static void
4147 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4148                                 uint32_t index, uint32_t pool)
4149 {
4150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         uint32_t enable_addr = 1;
4152
4153         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4154 }
4155
4156 static void
4157 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4158 {
4159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4160
4161         ixgbe_clear_rar(hw, index);
4162 }
4163
4164 static void
4165 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4166 {
4167         ixgbe_remove_rar(dev, 0);
4168
4169         ixgbe_add_rar(dev, addr, 0, 0);
4170 }
4171
4172 int
4173 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4174                 struct ether_addr *mac_addr)
4175 {
4176         struct ixgbe_hw *hw;
4177         struct ixgbe_vf_info *vfinfo;
4178         int rar_entry;
4179         uint8_t *new_mac = (uint8_t *)(mac_addr);
4180         struct rte_eth_dev *dev;
4181         struct rte_eth_dev_info dev_info;
4182
4183         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4184
4185         dev = &rte_eth_devices[port];
4186         rte_eth_dev_info_get(port, &dev_info);
4187
4188         if (vf >= dev_info.max_vfs)
4189                 return -EINVAL;
4190
4191         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4192         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4193         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4194
4195         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4196                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4197                                 ETHER_ADDR_LEN);
4198                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4199                                 IXGBE_RAH_AV);
4200         }
4201         return -EINVAL;
4202 }
4203
4204 static int
4205 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4206 {
4207         uint32_t hlreg0;
4208         uint32_t maxfrs;
4209         struct ixgbe_hw *hw;
4210         struct rte_eth_dev_info dev_info;
4211         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4212         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4213
4214         ixgbe_dev_info_get(dev, &dev_info);
4215
4216         /* check that mtu is within the allowed range */
4217         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4218                 return -EINVAL;
4219
4220         /* refuse mtu that requires the support of scattered packets when this
4221          * feature has not been enabled before.
4222          */
4223         if (!rx_conf->enable_scatter &&
4224             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4225              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4226                 return -EINVAL;
4227
4228         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4230
4231         /* switch to jumbo mode if needed */
4232         if (frame_size > ETHER_MAX_LEN) {
4233                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4234                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4235         } else {
4236                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4237                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4238         }
4239         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4240
4241         /* update max frame size */
4242         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4243
4244         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4245         maxfrs &= 0x0000FFFF;
4246         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4247         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4248
4249         return 0;
4250 }
4251
4252 /*
4253  * Virtual Function operations
4254  */
4255 static void
4256 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4257 {
4258         PMD_INIT_FUNC_TRACE();
4259
4260         /* Clear interrupt mask to stop from interrupts being generated */
4261         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4262
4263         IXGBE_WRITE_FLUSH(hw);
4264 }
4265
4266 static void
4267 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4268 {
4269         PMD_INIT_FUNC_TRACE();
4270
4271         /* VF enable interrupt autoclean */
4272         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4273         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4274         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4275
4276         IXGBE_WRITE_FLUSH(hw);
4277 }
4278
4279 static int
4280 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4281 {
4282         struct rte_eth_conf *conf = &dev->data->dev_conf;
4283         struct ixgbe_adapter *adapter =
4284                         (struct ixgbe_adapter *)dev->data->dev_private;
4285
4286         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4287                      dev->data->port_id);
4288
4289         /*
4290          * VF has no ability to enable/disable HW CRC
4291          * Keep the persistent behavior the same as Host PF
4292          */
4293 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4294         if (!conf->rxmode.hw_strip_crc) {
4295                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4296                 conf->rxmode.hw_strip_crc = 1;
4297         }
4298 #else
4299         if (conf->rxmode.hw_strip_crc) {
4300                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4301                 conf->rxmode.hw_strip_crc = 0;
4302         }
4303 #endif
4304
4305         /*
4306          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4307          * allocation or vector Rx preconditions we will reset it.
4308          */
4309         adapter->rx_bulk_alloc_allowed = true;
4310         adapter->rx_vec_allowed = true;
4311
4312         return 0;
4313 }
4314
4315 static int
4316 ixgbevf_dev_start(struct rte_eth_dev *dev)
4317 {
4318         struct ixgbe_hw *hw =
4319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         uint32_t intr_vector = 0;
4321         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4322
4323         int err, mask = 0;
4324
4325         PMD_INIT_FUNC_TRACE();
4326
4327         err = hw->mac.ops.reset_hw(hw);
4328         if (err) {
4329                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4330                 return err;
4331         }
4332         hw->mac.get_link_status = true;
4333
4334         /* negotiate mailbox API version to use with the PF. */
4335         ixgbevf_negotiate_api(hw);
4336
4337         ixgbevf_dev_tx_init(dev);
4338
4339         /* This can fail when allocating mbufs for descriptor rings */
4340         err = ixgbevf_dev_rx_init(dev);
4341         if (err) {
4342                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4343                 ixgbe_dev_clear_queues(dev);
4344                 return err;
4345         }
4346
4347         /* Set vfta */
4348         ixgbevf_set_vfta_all(dev, 1);
4349
4350         /* Set HW strip */
4351         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4352                 ETH_VLAN_EXTEND_MASK;
4353         ixgbevf_vlan_offload_set(dev, mask);
4354
4355         ixgbevf_dev_rxtx_start(dev);
4356
4357         /* check and configure queue intr-vector mapping */
4358         if (rte_intr_cap_multiple(intr_handle) &&
4359             dev->data->dev_conf.intr_conf.rxq != 0) {
4360                 intr_vector = dev->data->nb_rx_queues;
4361                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4362                         return -1;
4363         }
4364
4365         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4366                 intr_handle->intr_vec =
4367                         rte_zmalloc("intr_vec",
4368                                     dev->data->nb_rx_queues * sizeof(int), 0);
4369                 if (intr_handle->intr_vec == NULL) {
4370                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4371                                      " intr_vec\n", dev->data->nb_rx_queues);
4372                         return -ENOMEM;
4373                 }
4374         }
4375         ixgbevf_configure_msix(dev);
4376
4377         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
4378          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
4379          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
4380          * is not cleared, it will fail when following rte_intr_enable( ) tries
4381          * to map Rx queue interrupt to other VFIO vectors.
4382          * So clear uio/vfio intr/evevnfd first to avoid failure.
4383          */
4384         rte_intr_disable(intr_handle);
4385
4386         rte_intr_enable(intr_handle);
4387
4388         /* Re-enable interrupt for VF */
4389         ixgbevf_intr_enable(hw);
4390
4391         return 0;
4392 }
4393
4394 static void
4395 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4396 {
4397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4399
4400         PMD_INIT_FUNC_TRACE();
4401
4402         ixgbevf_intr_disable(hw);
4403
4404         hw->adapter_stopped = 1;
4405         ixgbe_stop_adapter(hw);
4406
4407         /*
4408           * Clear what we set, but we still keep shadow_vfta to
4409           * restore after device starts
4410           */
4411         ixgbevf_set_vfta_all(dev, 0);
4412
4413         /* Clear stored conf */
4414         dev->data->scattered_rx = 0;
4415
4416         ixgbe_dev_clear_queues(dev);
4417
4418         /* Clean datapath event and queue/vec mapping */
4419         rte_intr_efd_disable(intr_handle);
4420         if (intr_handle->intr_vec != NULL) {
4421                 rte_free(intr_handle->intr_vec);
4422                 intr_handle->intr_vec = NULL;
4423         }
4424 }
4425
4426 static void
4427 ixgbevf_dev_close(struct rte_eth_dev *dev)
4428 {
4429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430
4431         PMD_INIT_FUNC_TRACE();
4432
4433         ixgbe_reset_hw(hw);
4434
4435         ixgbevf_dev_stop(dev);
4436
4437         ixgbe_dev_free_queues(dev);
4438
4439         /**
4440          * Remove the VF MAC address ro ensure
4441          * that the VF traffic goes to the PF
4442          * after stop, close and detach of the VF
4443          **/
4444         ixgbevf_remove_mac_addr(dev, 0);
4445 }
4446
4447 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4448 {
4449         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4450         struct ixgbe_vfta *shadow_vfta =
4451                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4452         int i = 0, j = 0, vfta = 0, mask = 1;
4453
4454         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4455                 vfta = shadow_vfta->vfta[i];
4456                 if (vfta) {
4457                         mask = 1;
4458                         for (j = 0; j < 32; j++) {
4459                                 if (vfta & mask)
4460                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4461                                                        on, false);
4462                                 mask <<= 1;
4463                         }
4464                 }
4465         }
4466
4467 }
4468
4469 static int
4470 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4471 {
4472         struct ixgbe_hw *hw =
4473                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4474         struct ixgbe_vfta *shadow_vfta =
4475                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4476         uint32_t vid_idx = 0;
4477         uint32_t vid_bit = 0;
4478         int ret = 0;
4479
4480         PMD_INIT_FUNC_TRACE();
4481
4482         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4483         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4484         if (ret) {
4485                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4486                 return ret;
4487         }
4488         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4489         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4490
4491         /* Save what we set and retore it after device reset */
4492         if (on)
4493                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4494         else
4495                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4496
4497         return 0;
4498 }
4499
4500 static void
4501 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4502 {
4503         struct ixgbe_hw *hw =
4504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         uint32_t ctrl;
4506
4507         PMD_INIT_FUNC_TRACE();
4508
4509         if (queue >= hw->mac.max_rx_queues)
4510                 return;
4511
4512         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4513         if (on)
4514                 ctrl |= IXGBE_RXDCTL_VME;
4515         else
4516                 ctrl &= ~IXGBE_RXDCTL_VME;
4517         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4518
4519         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4520 }
4521
4522 static void
4523 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4524 {
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         uint16_t i;
4528         int on = 0;
4529
4530         /* VF function only support hw strip feature, others are not support */
4531         if (mask & ETH_VLAN_STRIP_MASK) {
4532                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4533
4534                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4535                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4536         }
4537 }
4538
4539 static int
4540 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4541 {
4542         uint32_t reg_val;
4543
4544         /* we only need to do this if VMDq is enabled */
4545         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4546         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4547                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4548                 return -1;
4549         }
4550
4551         return 0;
4552 }
4553
4554 static uint32_t
4555 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4556 {
4557         uint32_t vector = 0;
4558
4559         switch (hw->mac.mc_filter_type) {
4560         case 0:   /* use bits [47:36] of the address */
4561                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4562                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4563                 break;
4564         case 1:   /* use bits [46:35] of the address */
4565                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4566                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4567                 break;
4568         case 2:   /* use bits [45:34] of the address */
4569                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4570                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4571                 break;
4572         case 3:   /* use bits [43:32] of the address */
4573                 vector = ((uc_addr->addr_bytes[4]) |
4574                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4575                 break;
4576         default:  /* Invalid mc_filter_type */
4577                 break;
4578         }
4579
4580         /* vector can only be 12-bits or boundary will be exceeded */
4581         vector &= 0xFFF;
4582         return vector;
4583 }
4584
4585 static int
4586 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4587                         uint8_t on)
4588 {
4589         uint32_t vector;
4590         uint32_t uta_idx;
4591         uint32_t reg_val;
4592         uint32_t uta_shift;
4593         uint32_t rc;
4594         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4595         const uint32_t ixgbe_uta_bit_shift = 5;
4596         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4597         const uint32_t bit1 = 0x1;
4598
4599         struct ixgbe_hw *hw =
4600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601         struct ixgbe_uta_info *uta_info =
4602                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4603
4604         /* The UTA table only exists on 82599 hardware and newer */
4605         if (hw->mac.type < ixgbe_mac_82599EB)
4606                 return -ENOTSUP;
4607
4608         vector = ixgbe_uta_vector(hw, mac_addr);
4609         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4610         uta_shift = vector & ixgbe_uta_bit_mask;
4611
4612         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4613         if (rc == on)
4614                 return 0;
4615
4616         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4617         if (on) {
4618                 uta_info->uta_in_use++;
4619                 reg_val |= (bit1 << uta_shift);
4620                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4621         } else {
4622                 uta_info->uta_in_use--;
4623                 reg_val &= ~(bit1 << uta_shift);
4624                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4625         }
4626
4627         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4628
4629         if (uta_info->uta_in_use > 0)
4630                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4631                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4632         else
4633                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4634
4635         return 0;
4636 }
4637
4638 static int
4639 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4640 {
4641         int i;
4642         struct ixgbe_hw *hw =
4643                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644         struct ixgbe_uta_info *uta_info =
4645                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4646
4647         /* The UTA table only exists on 82599 hardware and newer */
4648         if (hw->mac.type < ixgbe_mac_82599EB)
4649                 return -ENOTSUP;
4650
4651         if (on) {
4652                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4653                         uta_info->uta_shadow[i] = ~0;
4654                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4655                 }
4656         } else {
4657                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4658                         uta_info->uta_shadow[i] = 0;
4659                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4660                 }
4661         }
4662         return 0;
4663
4664 }
4665
4666 uint32_t
4667 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4668 {
4669         uint32_t new_val = orig_val;
4670
4671         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4672                 new_val |= IXGBE_VMOLR_AUPE;
4673         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4674                 new_val |= IXGBE_VMOLR_ROMPE;
4675         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4676                 new_val |= IXGBE_VMOLR_ROPE;
4677         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4678                 new_val |= IXGBE_VMOLR_BAM;
4679         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4680                 new_val |= IXGBE_VMOLR_MPE;
4681
4682         return new_val;
4683 }
4684
4685 static int
4686 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4687                                uint16_t rx_mask, uint8_t on)
4688 {
4689         int val = 0;
4690
4691         struct ixgbe_hw *hw =
4692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4694
4695         if (hw->mac.type == ixgbe_mac_82598EB) {
4696                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4697                              " on 82599 hardware and newer");
4698                 return -ENOTSUP;
4699         }
4700         if (ixgbe_vmdq_mode_check(hw) < 0)
4701                 return -ENOTSUP;
4702
4703         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4704
4705         if (on)
4706                 vmolr |= val;
4707         else
4708                 vmolr &= ~val;
4709
4710         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4711
4712         return 0;
4713 }
4714
4715 static int
4716 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4717 {
4718         uint32_t reg, addr;
4719         uint32_t val;
4720         const uint8_t bit1 = 0x1;
4721
4722         struct ixgbe_hw *hw =
4723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724
4725         if (ixgbe_vmdq_mode_check(hw) < 0)
4726                 return -ENOTSUP;
4727
4728         if (pool >= ETH_64_POOLS)
4729                 return -EINVAL;
4730
4731         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4732         if (pool >= 32) {
4733                 addr = IXGBE_VFRE(1);
4734                 val = bit1 << (pool - 32);
4735         } else {
4736                 addr = IXGBE_VFRE(0);
4737                 val = bit1 << pool;
4738         }
4739
4740         reg = IXGBE_READ_REG(hw, addr);
4741
4742         if (on)
4743                 reg |= val;
4744         else
4745                 reg &= ~val;
4746
4747         IXGBE_WRITE_REG(hw, addr, reg);
4748
4749         return 0;
4750 }
4751
4752 static int
4753 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4754 {
4755         uint32_t reg, addr;
4756         uint32_t val;
4757         const uint8_t bit1 = 0x1;
4758
4759         struct ixgbe_hw *hw =
4760                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761
4762         if (ixgbe_vmdq_mode_check(hw) < 0)
4763                 return -ENOTSUP;
4764
4765         if (pool >= ETH_64_POOLS)
4766                 return -EINVAL;
4767
4768         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4769         if (pool >= 32) {
4770                 addr = IXGBE_VFTE(1);
4771                 val = bit1 << (pool - 32);
4772         } else {
4773                 addr = IXGBE_VFTE(0);
4774                 val = bit1 << pool;
4775         }
4776
4777         reg = IXGBE_READ_REG(hw, addr);
4778
4779         if (on)
4780                 reg |= val;
4781         else
4782                 reg &= ~val;
4783
4784         IXGBE_WRITE_REG(hw, addr, reg);
4785
4786         return 0;
4787 }
4788
4789 static int
4790 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4791                         uint64_t pool_mask, uint8_t vlan_on)
4792 {
4793         int ret = 0;
4794         uint16_t pool_idx;
4795         struct ixgbe_hw *hw =
4796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797
4798         if (ixgbe_vmdq_mode_check(hw) < 0)
4799                 return -ENOTSUP;
4800         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4801                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4802                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4803                                                    vlan_on, false);
4804                         if (ret < 0)
4805                                 return ret;
4806                 }
4807         }
4808
4809         return ret;
4810 }
4811
4812 int
4813 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4814 {
4815         struct ixgbe_hw *hw;
4816         struct ixgbe_mac_info *mac;
4817         struct rte_eth_dev *dev;
4818         struct rte_eth_dev_info dev_info;
4819
4820         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4821
4822         dev = &rte_eth_devices[port];
4823         rte_eth_dev_info_get(port, &dev_info);
4824
4825         if (vf >= dev_info.max_vfs)
4826                 return -EINVAL;
4827
4828         if (on > 1)
4829                 return -EINVAL;
4830
4831         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         mac = &hw->mac;
4833
4834         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4835
4836         return 0;
4837 }
4838
4839 int
4840 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4841 {
4842         struct ixgbe_hw *hw;
4843         struct ixgbe_mac_info *mac;
4844         struct rte_eth_dev *dev;
4845         struct rte_eth_dev_info dev_info;
4846
4847         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4848
4849         dev = &rte_eth_devices[port];
4850         rte_eth_dev_info_get(port, &dev_info);
4851
4852         if (vf >= dev_info.max_vfs)
4853                 return -EINVAL;
4854
4855         if (on > 1)
4856                 return -EINVAL;
4857
4858         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859         mac = &hw->mac;
4860         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4861
4862         return 0;
4863 }
4864
4865 int
4866 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4867 {
4868         struct ixgbe_hw *hw;
4869         uint32_t ctrl;
4870         struct rte_eth_dev *dev;
4871         struct rte_eth_dev_info dev_info;
4872
4873         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4874
4875         dev = &rte_eth_devices[port];
4876         rte_eth_dev_info_get(port, &dev_info);
4877
4878         if (vf >= dev_info.max_vfs)
4879                 return -EINVAL;
4880
4881         if (vlan_id > 4095)
4882                 return -EINVAL;
4883
4884         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4886         if (vlan_id) {
4887                 ctrl = vlan_id;
4888                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4889         } else {
4890                 ctrl = 0;
4891         }
4892
4893         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4894
4895         return 0;
4896 }
4897
4898 int
4899 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4900 {
4901         struct ixgbe_hw *hw;
4902         uint32_t ctrl;
4903         struct rte_eth_dev *dev;
4904
4905         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4906
4907         dev = &rte_eth_devices[port];
4908
4909         if (on > 1)
4910                 return -EINVAL;
4911
4912         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4914         /* enable or disable VMDQ loopback */
4915         if (on)
4916                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4917         else
4918                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4919
4920         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4921
4922         return 0;
4923 }
4924
4925 int
4926 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4927 {
4928         struct ixgbe_hw *hw;
4929         uint32_t reg_value;
4930         int i;
4931         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4932         struct rte_eth_dev *dev;
4933
4934         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4935
4936         dev = &rte_eth_devices[port];
4937
4938         if (on > 1)
4939                 return -EINVAL;
4940
4941         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942         for (i = 0; i <= num_queues; i++) {
4943                 reg_value = IXGBE_QDE_WRITE |
4944                                 (i << IXGBE_QDE_IDX_SHIFT) |
4945                                 (on & IXGBE_QDE_ENABLE);
4946                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4947         }
4948
4949         return 0;
4950 }
4951
4952 int
4953 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4954 {
4955         struct ixgbe_hw *hw;
4956         uint32_t reg_value;
4957         struct rte_eth_dev *dev;
4958         struct rte_eth_dev_info dev_info;
4959
4960         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4961
4962         dev = &rte_eth_devices[port];
4963         rte_eth_dev_info_get(port, &dev_info);
4964
4965         /* only support VF's 0 to 63 */
4966         if ((vf >= dev_info.max_vfs) || (vf > 63))
4967                 return -EINVAL;
4968
4969         if (on > 1)
4970                 return -EINVAL;
4971
4972         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4974         if (on)
4975                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4976         else
4977                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4978
4979         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4980
4981         return 0;
4982 }
4983
4984 int
4985 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4986 {
4987         struct rte_eth_dev *dev;
4988         struct rte_eth_dev_info dev_info;
4989         uint16_t queues_per_pool;
4990         uint32_t q;
4991
4992         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4993
4994         dev = &rte_eth_devices[port];
4995         rte_eth_dev_info_get(port, &dev_info);
4996
4997         if (vf >= dev_info.max_vfs)
4998                 return -EINVAL;
4999
5000         if (on > 1)
5001                 return -EINVAL;
5002
5003         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5004
5005         /* The PF has 128 queue pairs and in SRIOV configuration
5006          * those queues will be assigned to VF's, so RXDCTL
5007          * registers will be dealing with queues which will be
5008          * assigned to VF's.
5009          * Let's say we have SRIOV configured with 31 VF's then the
5010          * first 124 queues 0-123 will be allocated to VF's and only
5011          * the last 4 queues 123-127 will be assigned to the PF.
5012          */
5013
5014         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5015
5016         for (q = 0; q < queues_per_pool; q++)
5017                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5018                                 q + vf * queues_per_pool, on);
5019         return 0;
5020 }
5021
5022 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5023 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5024 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5025 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5026 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5027         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5028         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5029
5030 static int
5031 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5032                         struct rte_eth_mirror_conf *mirror_conf,
5033                         uint8_t rule_id, uint8_t on)
5034 {
5035         uint32_t mr_ctl, vlvf;
5036         uint32_t mp_lsb = 0;
5037         uint32_t mv_msb = 0;
5038         uint32_t mv_lsb = 0;
5039         uint32_t mp_msb = 0;
5040         uint8_t i = 0;
5041         int reg_index = 0;
5042         uint64_t vlan_mask = 0;
5043
5044         const uint8_t pool_mask_offset = 32;
5045         const uint8_t vlan_mask_offset = 32;
5046         const uint8_t dst_pool_offset = 8;
5047         const uint8_t rule_mr_offset  = 4;
5048         const uint8_t mirror_rule_mask = 0x0F;
5049
5050         struct ixgbe_mirror_info *mr_info =
5051                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5052         struct ixgbe_hw *hw =
5053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         uint8_t mirror_type = 0;
5055
5056         if (ixgbe_vmdq_mode_check(hw) < 0)
5057                 return -ENOTSUP;
5058
5059         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5060                 return -EINVAL;
5061
5062         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5063                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5064                         mirror_conf->rule_type);
5065                 return -EINVAL;
5066         }
5067
5068         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5069                 mirror_type |= IXGBE_MRCTL_VLME;
5070                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5071                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5072                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5073                                 /* search vlan id related pool vlan filter index */
5074                                 reg_index = ixgbe_find_vlvf_slot(hw,
5075                                                  mirror_conf->vlan.vlan_id[i],
5076                                                  false);
5077                                 if (reg_index < 0)
5078                                         return -EINVAL;
5079                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5080                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5081                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5082                                       mirror_conf->vlan.vlan_id[i]))
5083                                         vlan_mask |= (1ULL << reg_index);
5084                                 else
5085                                         return -EINVAL;
5086                         }
5087                 }
5088
5089                 if (on) {
5090                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5091                         mv_msb = vlan_mask >> vlan_mask_offset;
5092
5093                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5094                                                 mirror_conf->vlan.vlan_mask;
5095                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5096                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5097                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5098                                                 mirror_conf->vlan.vlan_id[i];
5099                         }
5100                 } else {
5101                         mv_lsb = 0;
5102                         mv_msb = 0;
5103                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5104                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5105                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5106                 }
5107         }
5108
5109         /*
5110          * if enable pool mirror, write related pool mask register,if disable
5111          * pool mirror, clear PFMRVM register
5112          */
5113         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5114                 mirror_type |= IXGBE_MRCTL_VPME;
5115                 if (on) {
5116                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5117                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5118                         mr_info->mr_conf[rule_id].pool_mask =
5119                                         mirror_conf->pool_mask;
5120
5121                 } else {
5122                         mp_lsb = 0;
5123                         mp_msb = 0;
5124                         mr_info->mr_conf[rule_id].pool_mask = 0;
5125                 }
5126         }
5127         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5128                 mirror_type |= IXGBE_MRCTL_UPME;
5129         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5130                 mirror_type |= IXGBE_MRCTL_DPME;
5131
5132         /* read  mirror control register and recalculate it */
5133         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5134
5135         if (on) {
5136                 mr_ctl |= mirror_type;
5137                 mr_ctl &= mirror_rule_mask;
5138                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5139         } else
5140                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5141
5142         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5143         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5144
5145         /* write mirrror control  register */
5146         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5147
5148         /* write pool mirrror control  register */
5149         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5150                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5151                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5152                                 mp_msb);
5153         }
5154         /* write VLAN mirrror control  register */
5155         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5156                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5157                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5158                                 mv_msb);
5159         }
5160
5161         return 0;
5162 }
5163
5164 static int
5165 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5166 {
5167         int mr_ctl = 0;
5168         uint32_t lsb_val = 0;
5169         uint32_t msb_val = 0;
5170         const uint8_t rule_mr_offset = 4;
5171
5172         struct ixgbe_hw *hw =
5173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         struct ixgbe_mirror_info *mr_info =
5175                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5176
5177         if (ixgbe_vmdq_mode_check(hw) < 0)
5178                 return -ENOTSUP;
5179
5180         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5181                 return -EINVAL;
5182
5183         memset(&mr_info->mr_conf[rule_id], 0,
5184                 sizeof(struct rte_eth_mirror_conf));
5185
5186         /* clear PFVMCTL register */
5187         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5188
5189         /* clear pool mask register */
5190         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5191         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5192
5193         /* clear vlan mask register */
5194         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5195         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5196
5197         return 0;
5198 }
5199
5200 static int
5201 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5202 {
5203         uint32_t mask;
5204         struct ixgbe_hw *hw =
5205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206
5207         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5208         mask |= (1 << IXGBE_MISC_VEC_ID);
5209         RTE_SET_USED(queue_id);
5210         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5211
5212         rte_intr_enable(&dev->pci_dev->intr_handle);
5213
5214         return 0;
5215 }
5216
5217 static int
5218 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5219 {
5220         uint32_t mask;
5221         struct ixgbe_hw *hw =
5222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223
5224         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5225         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5226         RTE_SET_USED(queue_id);
5227         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5228
5229         return 0;
5230 }
5231
5232 static int
5233 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5234 {
5235         uint32_t mask;
5236         struct ixgbe_hw *hw =
5237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         struct ixgbe_interrupt *intr =
5239                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5240
5241         if (queue_id < 16) {
5242                 ixgbe_disable_intr(hw);
5243                 intr->mask |= (1 << queue_id);
5244                 ixgbe_enable_intr(dev);
5245         } else if (queue_id < 32) {
5246                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5247                 mask &= (1 << queue_id);
5248                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5249         } else if (queue_id < 64) {
5250                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5251                 mask &= (1 << (queue_id - 32));
5252                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5253         }
5254         rte_intr_enable(&dev->pci_dev->intr_handle);
5255
5256         return 0;
5257 }
5258
5259 static int
5260 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5261 {
5262         uint32_t mask;
5263         struct ixgbe_hw *hw =
5264                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265         struct ixgbe_interrupt *intr =
5266                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5267
5268         if (queue_id < 16) {
5269                 ixgbe_disable_intr(hw);
5270                 intr->mask &= ~(1 << queue_id);
5271                 ixgbe_enable_intr(dev);
5272         } else if (queue_id < 32) {
5273                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5274                 mask &= ~(1 << queue_id);
5275                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5276         } else if (queue_id < 64) {
5277                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5278                 mask &= ~(1 << (queue_id - 32));
5279                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5280         }
5281
5282         return 0;
5283 }
5284
5285 static void
5286 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5287                      uint8_t queue, uint8_t msix_vector)
5288 {
5289         uint32_t tmp, idx;
5290
5291         if (direction == -1) {
5292                 /* other causes */
5293                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5294                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5295                 tmp &= ~0xFF;
5296                 tmp |= msix_vector;
5297                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5298         } else {
5299                 /* rx or tx cause */
5300                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5301                 idx = ((16 * (queue & 1)) + (8 * direction));
5302                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5303                 tmp &= ~(0xFF << idx);
5304                 tmp |= (msix_vector << idx);
5305                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5306         }
5307 }
5308
5309 /**
5310  * set the IVAR registers, mapping interrupt causes to vectors
5311  * @param hw
5312  *  pointer to ixgbe_hw struct
5313  * @direction
5314  *  0 for Rx, 1 for Tx, -1 for other causes
5315  * @queue
5316  *  queue to map the corresponding interrupt to
5317  * @msix_vector
5318  *  the vector to map to the corresponding queue
5319  */
5320 static void
5321 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5322                    uint8_t queue, uint8_t msix_vector)
5323 {
5324         uint32_t tmp, idx;
5325
5326         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5327         if (hw->mac.type == ixgbe_mac_82598EB) {
5328                 if (direction == -1)
5329                         direction = 0;
5330                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5331                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5332                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5333                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5334                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5335         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5336                         (hw->mac.type == ixgbe_mac_X540) ||
5337                         (hw->mac.type == ixgbe_mac_X550)) {
5338                 if (direction == -1) {
5339                         /* other causes */
5340                         idx = ((queue & 1) * 8);
5341                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5342                         tmp &= ~(0xFF << idx);
5343                         tmp |= (msix_vector << idx);
5344                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5345                 } else {
5346                         /* rx or tx causes */
5347                         idx = ((16 * (queue & 1)) + (8 * direction));
5348                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5349                         tmp &= ~(0xFF << idx);
5350                         tmp |= (msix_vector << idx);
5351                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5352                 }
5353         }
5354 }
5355
5356 static void
5357 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5358 {
5359         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5360         struct ixgbe_hw *hw =
5361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         uint32_t q_idx;
5363         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5364
5365         /* Configure VF other cause ivar */
5366         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5367
5368         /* won't configure msix register if no mapping is done
5369          * between intr vector and event fd.
5370          */
5371         if (!rte_intr_dp_is_en(intr_handle))
5372                 return;
5373
5374         /* Configure all RX queues of VF */
5375         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5376                 /* Force all queue use vector 0,
5377                  * as IXGBE_VF_MAXMSIVECOTR = 1
5378                  */
5379                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5380                 intr_handle->intr_vec[q_idx] = vector_idx;
5381         }
5382 }
5383
5384 /**
5385  * Sets up the hardware to properly generate MSI-X interrupts
5386  * @hw
5387  *  board private structure
5388  */
5389 static void
5390 ixgbe_configure_msix(struct rte_eth_dev *dev)
5391 {
5392         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5393         struct ixgbe_hw *hw =
5394                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5396         uint32_t vec = IXGBE_MISC_VEC_ID;
5397         uint32_t mask;
5398         uint32_t gpie;
5399
5400         /* won't configure msix register if no mapping is done
5401          * between intr vector and event fd
5402          * but if misx has been enabled already, need to configure
5403          * auto clean, auto mask and throttling.
5404          */
5405         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5406         if (!rte_intr_dp_is_en(intr_handle) &&
5407             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5408                 return;
5409
5410         if (rte_intr_allow_others(intr_handle))
5411                 vec = base = IXGBE_RX_VEC_START;
5412
5413         /* setup GPIE for MSI-x mode */
5414         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5415         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5416                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5417         /* auto clearing and auto setting corresponding bits in EIMS
5418          * when MSI-X interrupt is triggered
5419          */
5420         if (hw->mac.type == ixgbe_mac_82598EB) {
5421                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5422         } else {
5423                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5424                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5425         }
5426         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5427
5428         /* Populate the IVAR table and set the ITR values to the
5429          * corresponding register.
5430          */
5431         if (rte_intr_dp_is_en(intr_handle)) {
5432                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5433                         queue_id++) {
5434                         /* by default, 1:1 mapping */
5435                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5436                         intr_handle->intr_vec[queue_id] = vec;
5437                         if (vec < base + intr_handle->nb_efd - 1)
5438                                 vec++;
5439                 }
5440
5441                 switch (hw->mac.type) {
5442                 case ixgbe_mac_82598EB:
5443                         ixgbe_set_ivar_map(hw, -1,
5444                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5445                                            IXGBE_MISC_VEC_ID);
5446                         break;
5447                 case ixgbe_mac_82599EB:
5448                 case ixgbe_mac_X540:
5449                 case ixgbe_mac_X550:
5450                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5451                         break;
5452                 default:
5453                         break;
5454                 }
5455         }
5456         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5457                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5458
5459         /* set up to autoclear timer, and the vectors */
5460         mask = IXGBE_EIMS_ENABLE_MASK;
5461         mask &= ~(IXGBE_EIMS_OTHER |
5462                   IXGBE_EIMS_MAILBOX |
5463                   IXGBE_EIMS_LSC);
5464
5465         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5466 }
5467
5468 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5469         uint16_t queue_idx, uint16_t tx_rate)
5470 {
5471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5472         uint32_t rf_dec, rf_int;
5473         uint32_t bcnrc_val;
5474         uint16_t link_speed = dev->data->dev_link.link_speed;
5475
5476         if (queue_idx >= hw->mac.max_tx_queues)
5477                 return -EINVAL;
5478
5479         if (tx_rate != 0) {
5480                 /* Calculate the rate factor values to set */
5481                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5482                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5483                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5484
5485                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5486                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5487                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5488                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5489         } else {
5490                 bcnrc_val = 0;
5491         }
5492
5493         /*
5494          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5495          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5496          * set as 0x4.
5497          */
5498         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5499                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5500                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5501                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5502                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5503         else
5504                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5505                         IXGBE_MMW_SIZE_DEFAULT);
5506
5507         /* Set RTTBCNRC of queue X */
5508         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5509         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5510         IXGBE_WRITE_FLUSH(hw);
5511
5512         return 0;
5513 }
5514
5515 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5516         uint16_t tx_rate, uint64_t q_msk)
5517 {
5518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5519         struct ixgbe_vf_info *vfinfo =
5520                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5521         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5522         uint32_t queue_stride =
5523                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5524         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5525         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5526         uint16_t total_rate = 0;
5527
5528         if (queue_end >= hw->mac.max_tx_queues)
5529                 return -EINVAL;
5530
5531         if (vfinfo != NULL) {
5532                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5533                         if (vf_idx == vf)
5534                                 continue;
5535                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5536                                 idx++)
5537                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5538                 }
5539         } else
5540                 return -EINVAL;
5541
5542         /* Store tx_rate for this vf. */
5543         for (idx = 0; idx < nb_q_per_pool; idx++) {
5544                 if (((uint64_t)0x1 << idx) & q_msk) {
5545                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5546                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5547                         total_rate += tx_rate;
5548                 }
5549         }
5550
5551         if (total_rate > dev->data->dev_link.link_speed) {
5552                 /*
5553                  * Reset stored TX rate of the VF if it causes exceed
5554                  * link speed.
5555                  */
5556                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5557                 return -EINVAL;
5558         }
5559
5560         /* Set RTTBCNRC of each queue/pool for vf X  */
5561         for (; queue_idx <= queue_end; queue_idx++) {
5562                 if (0x1 & q_msk)
5563                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5564                 q_msk = q_msk >> 1;
5565         }
5566
5567         return 0;
5568 }
5569
5570 static void
5571 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5572                      __attribute__((unused)) uint32_t index,
5573                      __attribute__((unused)) uint32_t pool)
5574 {
5575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5576         int diag;
5577
5578         /*
5579          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5580          * operation. Trap this case to avoid exhausting the [very limited]
5581          * set of PF resources used to store VF MAC addresses.
5582          */
5583         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5584                 return;
5585         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5586         if (diag == 0)
5587                 return;
5588         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5589 }
5590
5591 static void
5592 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5593 {
5594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5596         struct ether_addr *mac_addr;
5597         uint32_t i;
5598         int diag;
5599
5600         /*
5601          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5602          * not support the deletion of a given MAC address.
5603          * Instead, it imposes to delete all MAC addresses, then to add again
5604          * all MAC addresses with the exception of the one to be deleted.
5605          */
5606         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5607
5608         /*
5609          * Add again all MAC addresses, with the exception of the deleted one
5610          * and of the permanent MAC address.
5611          */
5612         for (i = 0, mac_addr = dev->data->mac_addrs;
5613              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5614                 /* Skip the deleted MAC address */
5615                 if (i == index)
5616                         continue;
5617                 /* Skip NULL MAC addresses */
5618                 if (is_zero_ether_addr(mac_addr))
5619                         continue;
5620                 /* Skip the permanent MAC address */
5621                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5622                         continue;
5623                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5624                 if (diag != 0)
5625                         PMD_DRV_LOG(ERR,
5626                                     "Adding again MAC address "
5627                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5628                                     "diag=%d",
5629                                     mac_addr->addr_bytes[0],
5630                                     mac_addr->addr_bytes[1],
5631                                     mac_addr->addr_bytes[2],
5632                                     mac_addr->addr_bytes[3],
5633                                     mac_addr->addr_bytes[4],
5634                                     mac_addr->addr_bytes[5],
5635                                     diag);
5636         }
5637 }
5638
5639 static void
5640 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5641 {
5642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643
5644         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5645 }
5646
5647 #define MAC_TYPE_FILTER_SUP(type)    do {\
5648         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5649                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5650                 (type) != ixgbe_mac_X550EM_a)\
5651                 return -ENOTSUP;\
5652 } while (0)
5653
5654 static int
5655 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5656                         struct rte_eth_syn_filter *filter,
5657                         bool add)
5658 {
5659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5660         uint32_t synqf;
5661
5662         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5663                 return -EINVAL;
5664
5665         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5666
5667         if (add) {
5668                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5669                         return -EINVAL;
5670                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5671                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5672
5673                 if (filter->hig_pri)
5674                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5675                 else
5676                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5677         } else {
5678                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5679                         return -ENOENT;
5680                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5681         }
5682         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5683         IXGBE_WRITE_FLUSH(hw);
5684         return 0;
5685 }
5686
5687 static int
5688 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5689                         struct rte_eth_syn_filter *filter)
5690 {
5691         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5693
5694         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5695                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5696                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5697                 return 0;
5698         }
5699         return -ENOENT;
5700 }
5701
5702 static int
5703 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5704                         enum rte_filter_op filter_op,
5705                         void *arg)
5706 {
5707         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5708         int ret;
5709
5710         MAC_TYPE_FILTER_SUP(hw->mac.type);
5711
5712         if (filter_op == RTE_ETH_FILTER_NOP)
5713                 return 0;
5714
5715         if (arg == NULL) {
5716                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5717                             filter_op);
5718                 return -EINVAL;
5719         }
5720
5721         switch (filter_op) {
5722         case RTE_ETH_FILTER_ADD:
5723                 ret = ixgbe_syn_filter_set(dev,
5724                                 (struct rte_eth_syn_filter *)arg,
5725                                 TRUE);
5726                 break;
5727         case RTE_ETH_FILTER_DELETE:
5728                 ret = ixgbe_syn_filter_set(dev,
5729                                 (struct rte_eth_syn_filter *)arg,
5730                                 FALSE);
5731                 break;
5732         case RTE_ETH_FILTER_GET:
5733                 ret = ixgbe_syn_filter_get(dev,
5734                                 (struct rte_eth_syn_filter *)arg);
5735                 break;
5736         default:
5737                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5738                 ret = -EINVAL;
5739                 break;
5740         }
5741
5742         return ret;
5743 }
5744
5745
5746 static inline enum ixgbe_5tuple_protocol
5747 convert_protocol_type(uint8_t protocol_value)
5748 {
5749         if (protocol_value == IPPROTO_TCP)
5750                 return IXGBE_FILTER_PROTOCOL_TCP;
5751         else if (protocol_value == IPPROTO_UDP)
5752                 return IXGBE_FILTER_PROTOCOL_UDP;
5753         else if (protocol_value == IPPROTO_SCTP)
5754                 return IXGBE_FILTER_PROTOCOL_SCTP;
5755         else
5756                 return IXGBE_FILTER_PROTOCOL_NONE;
5757 }
5758
5759 /*
5760  * add a 5tuple filter
5761  *
5762  * @param
5763  * dev: Pointer to struct rte_eth_dev.
5764  * index: the index the filter allocates.
5765  * filter: ponter to the filter that will be added.
5766  * rx_queue: the queue id the filter assigned to.
5767  *
5768  * @return
5769  *    - On success, zero.
5770  *    - On failure, a negative value.
5771  */
5772 static int
5773 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5774                         struct ixgbe_5tuple_filter *filter)
5775 {
5776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5777         struct ixgbe_filter_info *filter_info =
5778                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5779         int i, idx, shift;
5780         uint32_t ftqf, sdpqf;
5781         uint32_t l34timir = 0;
5782         uint8_t mask = 0xff;
5783
5784         /*
5785          * look for an unused 5tuple filter index,
5786          * and insert the filter to list.
5787          */
5788         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5789                 idx = i / (sizeof(uint32_t) * NBBY);
5790                 shift = i % (sizeof(uint32_t) * NBBY);
5791                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5792                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5793                         filter->index = i;
5794                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5795                                           filter,
5796                                           entries);
5797                         break;
5798                 }
5799         }
5800         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5801                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5802                 return -ENOSYS;
5803         }
5804
5805         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5806                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5807         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5808
5809         ftqf = (uint32_t)(filter->filter_info.proto &
5810                 IXGBE_FTQF_PROTOCOL_MASK);
5811         ftqf |= (uint32_t)((filter->filter_info.priority &
5812                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5813         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5814                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5815         if (filter->filter_info.dst_ip_mask == 0)
5816                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5817         if (filter->filter_info.src_port_mask == 0)
5818                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5819         if (filter->filter_info.dst_port_mask == 0)
5820                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5821         if (filter->filter_info.proto_mask == 0)
5822                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5823         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5824         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5825         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5826
5827         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5828         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5829         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5830         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5831
5832         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5833         l34timir |= (uint32_t)(filter->queue <<
5834                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5835         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5836         return 0;
5837 }
5838
5839 /*
5840  * remove a 5tuple filter
5841  *
5842  * @param
5843  * dev: Pointer to struct rte_eth_dev.
5844  * filter: the pointer of the filter will be removed.
5845  */
5846 static void
5847 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5848                         struct ixgbe_5tuple_filter *filter)
5849 {
5850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5851         struct ixgbe_filter_info *filter_info =
5852                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5853         uint16_t index = filter->index;
5854
5855         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5856                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5857         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5858         rte_free(filter);
5859
5860         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5861         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5862         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5863         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5864         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5865 }
5866
5867 static int
5868 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5869 {
5870         struct ixgbe_hw *hw;
5871         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5872         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5873
5874         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875
5876         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5877                 return -EINVAL;
5878
5879         /* refuse mtu that requires the support of scattered packets when this
5880          * feature has not been enabled before.
5881          */
5882         if (!rx_conf->enable_scatter &&
5883             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5884              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5885                 return -EINVAL;
5886
5887         /*
5888          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5889          * request of the version 2.0 of the mailbox API.
5890          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5891          * of the mailbox API.
5892          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5893          * prior to 3.11.33 which contains the following change:
5894          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5895          */
5896         ixgbevf_rlpml_set_vf(hw, max_frame);
5897
5898         /* update max frame size */
5899         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5900         return 0;
5901 }
5902
5903 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5904         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5905                 return -ENOTSUP;\
5906 } while (0)
5907
5908 static inline struct ixgbe_5tuple_filter *
5909 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5910                         struct ixgbe_5tuple_filter_info *key)
5911 {
5912         struct ixgbe_5tuple_filter *it;
5913
5914         TAILQ_FOREACH(it, filter_list, entries) {
5915                 if (memcmp(key, &it->filter_info,
5916                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5917                         return it;
5918                 }
5919         }
5920         return NULL;
5921 }
5922
5923 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5924 static inline int
5925 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5926                         struct ixgbe_5tuple_filter_info *filter_info)
5927 {
5928         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5929                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5930                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5931                 return -EINVAL;
5932
5933         switch (filter->dst_ip_mask) {
5934         case UINT32_MAX:
5935                 filter_info->dst_ip_mask = 0;
5936                 filter_info->dst_ip = filter->dst_ip;
5937                 break;
5938         case 0:
5939                 filter_info->dst_ip_mask = 1;
5940                 break;
5941         default:
5942                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5943                 return -EINVAL;
5944         }
5945
5946         switch (filter->src_ip_mask) {
5947         case UINT32_MAX:
5948                 filter_info->src_ip_mask = 0;
5949                 filter_info->src_ip = filter->src_ip;
5950                 break;
5951         case 0:
5952                 filter_info->src_ip_mask = 1;
5953                 break;
5954         default:
5955                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5956                 return -EINVAL;
5957         }
5958
5959         switch (filter->dst_port_mask) {
5960         case UINT16_MAX:
5961                 filter_info->dst_port_mask = 0;
5962                 filter_info->dst_port = filter->dst_port;
5963                 break;
5964         case 0:
5965                 filter_info->dst_port_mask = 1;
5966                 break;
5967         default:
5968                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5969                 return -EINVAL;
5970         }
5971
5972         switch (filter->src_port_mask) {
5973         case UINT16_MAX:
5974                 filter_info->src_port_mask = 0;
5975                 filter_info->src_port = filter->src_port;
5976                 break;
5977         case 0:
5978                 filter_info->src_port_mask = 1;
5979                 break;
5980         default:
5981                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5982                 return -EINVAL;
5983         }
5984
5985         switch (filter->proto_mask) {
5986         case UINT8_MAX:
5987                 filter_info->proto_mask = 0;
5988                 filter_info->proto =
5989                         convert_protocol_type(filter->proto);
5990                 break;
5991         case 0:
5992                 filter_info->proto_mask = 1;
5993                 break;
5994         default:
5995                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5996                 return -EINVAL;
5997         }
5998
5999         filter_info->priority = (uint8_t)filter->priority;
6000         return 0;
6001 }
6002
6003 /*
6004  * add or delete a ntuple filter
6005  *
6006  * @param
6007  * dev: Pointer to struct rte_eth_dev.
6008  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6009  * add: if true, add filter, if false, remove filter
6010  *
6011  * @return
6012  *    - On success, zero.
6013  *    - On failure, a negative value.
6014  */
6015 static int
6016 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6017                         struct rte_eth_ntuple_filter *ntuple_filter,
6018                         bool add)
6019 {
6020         struct ixgbe_filter_info *filter_info =
6021                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6022         struct ixgbe_5tuple_filter_info filter_5tuple;
6023         struct ixgbe_5tuple_filter *filter;
6024         int ret;
6025
6026         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6027                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6028                 return -EINVAL;
6029         }
6030
6031         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6032         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6033         if (ret < 0)
6034                 return ret;
6035
6036         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6037                                          &filter_5tuple);
6038         if (filter != NULL && add) {
6039                 PMD_DRV_LOG(ERR, "filter exists.");
6040                 return -EEXIST;
6041         }
6042         if (filter == NULL && !add) {
6043                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6044                 return -ENOENT;
6045         }
6046
6047         if (add) {
6048                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6049                                 sizeof(struct ixgbe_5tuple_filter), 0);
6050                 if (filter == NULL)
6051                         return -ENOMEM;
6052                 (void)rte_memcpy(&filter->filter_info,
6053                                  &filter_5tuple,
6054                                  sizeof(struct ixgbe_5tuple_filter_info));
6055                 filter->queue = ntuple_filter->queue;
6056                 ret = ixgbe_add_5tuple_filter(dev, filter);
6057                 if (ret < 0) {
6058                         rte_free(filter);
6059                         return ret;
6060                 }
6061         } else
6062                 ixgbe_remove_5tuple_filter(dev, filter);
6063
6064         return 0;
6065 }
6066
6067 /*
6068  * get a ntuple filter
6069  *
6070  * @param
6071  * dev: Pointer to struct rte_eth_dev.
6072  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6073  *
6074  * @return
6075  *    - On success, zero.
6076  *    - On failure, a negative value.
6077  */
6078 static int
6079 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6080                         struct rte_eth_ntuple_filter *ntuple_filter)
6081 {
6082         struct ixgbe_filter_info *filter_info =
6083                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6084         struct ixgbe_5tuple_filter_info filter_5tuple;
6085         struct ixgbe_5tuple_filter *filter;
6086         int ret;
6087
6088         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6089                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6090                 return -EINVAL;
6091         }
6092
6093         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6094         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6095         if (ret < 0)
6096                 return ret;
6097
6098         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6099                                          &filter_5tuple);
6100         if (filter == NULL) {
6101                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6102                 return -ENOENT;
6103         }
6104         ntuple_filter->queue = filter->queue;
6105         return 0;
6106 }
6107
6108 /*
6109  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6110  * @dev: pointer to rte_eth_dev structure
6111  * @filter_op:operation will be taken.
6112  * @arg: a pointer to specific structure corresponding to the filter_op
6113  *
6114  * @return
6115  *    - On success, zero.
6116  *    - On failure, a negative value.
6117  */
6118 static int
6119 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6120                                 enum rte_filter_op filter_op,
6121                                 void *arg)
6122 {
6123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6124         int ret;
6125
6126         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6127
6128         if (filter_op == RTE_ETH_FILTER_NOP)
6129                 return 0;
6130
6131         if (arg == NULL) {
6132                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6133                             filter_op);
6134                 return -EINVAL;
6135         }
6136
6137         switch (filter_op) {
6138         case RTE_ETH_FILTER_ADD:
6139                 ret = ixgbe_add_del_ntuple_filter(dev,
6140                         (struct rte_eth_ntuple_filter *)arg,
6141                         TRUE);
6142                 break;
6143         case RTE_ETH_FILTER_DELETE:
6144                 ret = ixgbe_add_del_ntuple_filter(dev,
6145                         (struct rte_eth_ntuple_filter *)arg,
6146                         FALSE);
6147                 break;
6148         case RTE_ETH_FILTER_GET:
6149                 ret = ixgbe_get_ntuple_filter(dev,
6150                         (struct rte_eth_ntuple_filter *)arg);
6151                 break;
6152         default:
6153                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6154                 ret = -EINVAL;
6155                 break;
6156         }
6157         return ret;
6158 }
6159
6160 static inline int
6161 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6162                         uint16_t ethertype)
6163 {
6164         int i;
6165
6166         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6167                 if (filter_info->ethertype_filters[i] == ethertype &&
6168                     (filter_info->ethertype_mask & (1 << i)))
6169                         return i;
6170         }
6171         return -1;
6172 }
6173
6174 static inline int
6175 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6176                         uint16_t ethertype)
6177 {
6178         int i;
6179
6180         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6181                 if (!(filter_info->ethertype_mask & (1 << i))) {
6182                         filter_info->ethertype_mask |= 1 << i;
6183                         filter_info->ethertype_filters[i] = ethertype;
6184                         return i;
6185                 }
6186         }
6187         return -1;
6188 }
6189
6190 static inline int
6191 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6192                         uint8_t idx)
6193 {
6194         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6195                 return -1;
6196         filter_info->ethertype_mask &= ~(1 << idx);
6197         filter_info->ethertype_filters[idx] = 0;
6198         return idx;
6199 }
6200
6201 static int
6202 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6203                         struct rte_eth_ethertype_filter *filter,
6204                         bool add)
6205 {
6206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6207         struct ixgbe_filter_info *filter_info =
6208                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6209         uint32_t etqf = 0;
6210         uint32_t etqs = 0;
6211         int ret;
6212
6213         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6214                 return -EINVAL;
6215
6216         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6217                 filter->ether_type == ETHER_TYPE_IPv6) {
6218                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6219                         " ethertype filter.", filter->ether_type);
6220                 return -EINVAL;
6221         }
6222
6223         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6224                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6225                 return -EINVAL;
6226         }
6227         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6228                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6229                 return -EINVAL;
6230         }
6231
6232         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6233         if (ret >= 0 && add) {
6234                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6235                             filter->ether_type);
6236                 return -EEXIST;
6237         }
6238         if (ret < 0 && !add) {
6239                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6240                             filter->ether_type);
6241                 return -ENOENT;
6242         }
6243
6244         if (add) {
6245                 ret = ixgbe_ethertype_filter_insert(filter_info,
6246                         filter->ether_type);
6247                 if (ret < 0) {
6248                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6249                         return -ENOSYS;
6250                 }
6251                 etqf = IXGBE_ETQF_FILTER_EN;
6252                 etqf |= (uint32_t)filter->ether_type;
6253                 etqs |= (uint32_t)((filter->queue <<
6254                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6255                                     IXGBE_ETQS_RX_QUEUE);
6256                 etqs |= IXGBE_ETQS_QUEUE_EN;
6257         } else {
6258                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6259                 if (ret < 0)
6260                         return -ENOSYS;
6261         }
6262         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6263         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6264         IXGBE_WRITE_FLUSH(hw);
6265
6266         return 0;
6267 }
6268
6269 static int
6270 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6271                         struct rte_eth_ethertype_filter *filter)
6272 {
6273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6274         struct ixgbe_filter_info *filter_info =
6275                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6276         uint32_t etqf, etqs;
6277         int ret;
6278
6279         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6280         if (ret < 0) {
6281                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6282                             filter->ether_type);
6283                 return -ENOENT;
6284         }
6285
6286         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6287         if (etqf & IXGBE_ETQF_FILTER_EN) {
6288                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6289                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6290                 filter->flags = 0;
6291                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6292                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6293                 return 0;
6294         }
6295         return -ENOENT;
6296 }
6297
6298 /*
6299  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6300  * @dev: pointer to rte_eth_dev structure
6301  * @filter_op:operation will be taken.
6302  * @arg: a pointer to specific structure corresponding to the filter_op
6303  */
6304 static int
6305 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6306                                 enum rte_filter_op filter_op,
6307                                 void *arg)
6308 {
6309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6310         int ret;
6311
6312         MAC_TYPE_FILTER_SUP(hw->mac.type);
6313
6314         if (filter_op == RTE_ETH_FILTER_NOP)
6315                 return 0;
6316
6317         if (arg == NULL) {
6318                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6319                             filter_op);
6320                 return -EINVAL;
6321         }
6322
6323         switch (filter_op) {
6324         case RTE_ETH_FILTER_ADD:
6325                 ret = ixgbe_add_del_ethertype_filter(dev,
6326                         (struct rte_eth_ethertype_filter *)arg,
6327                         TRUE);
6328                 break;
6329         case RTE_ETH_FILTER_DELETE:
6330                 ret = ixgbe_add_del_ethertype_filter(dev,
6331                         (struct rte_eth_ethertype_filter *)arg,
6332                         FALSE);
6333                 break;
6334         case RTE_ETH_FILTER_GET:
6335                 ret = ixgbe_get_ethertype_filter(dev,
6336                         (struct rte_eth_ethertype_filter *)arg);
6337                 break;
6338         default:
6339                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6340                 ret = -EINVAL;
6341                 break;
6342         }
6343         return ret;
6344 }
6345
6346 static int
6347 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6348                      enum rte_filter_type filter_type,
6349                      enum rte_filter_op filter_op,
6350                      void *arg)
6351 {
6352         int ret = -EINVAL;
6353
6354         switch (filter_type) {
6355         case RTE_ETH_FILTER_NTUPLE:
6356                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6357                 break;
6358         case RTE_ETH_FILTER_ETHERTYPE:
6359                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6360                 break;
6361         case RTE_ETH_FILTER_SYN:
6362                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6363                 break;
6364         case RTE_ETH_FILTER_FDIR:
6365                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6366                 break;
6367         case RTE_ETH_FILTER_L2_TUNNEL:
6368                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6369                 break;
6370         default:
6371                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6372                                                         filter_type);
6373                 break;
6374         }
6375
6376         return ret;
6377 }
6378
6379 static u8 *
6380 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6381                         u8 **mc_addr_ptr, u32 *vmdq)
6382 {
6383         u8 *mc_addr;
6384
6385         *vmdq = 0;
6386         mc_addr = *mc_addr_ptr;
6387         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6388         return mc_addr;
6389 }
6390
6391 static int
6392 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6393                           struct ether_addr *mc_addr_set,
6394                           uint32_t nb_mc_addr)
6395 {
6396         struct ixgbe_hw *hw;
6397         u8 *mc_addr_list;
6398
6399         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6400         mc_addr_list = (u8 *)mc_addr_set;
6401         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6402                                          ixgbe_dev_addr_list_itr, TRUE);
6403 }
6404
6405 static uint64_t
6406 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6407 {
6408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6409         uint64_t systime_cycles;
6410
6411         switch (hw->mac.type) {
6412         case ixgbe_mac_X550:
6413         case ixgbe_mac_X550EM_x:
6414         case ixgbe_mac_X550EM_a:
6415                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6416                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6417                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6418                                 * NSEC_PER_SEC;
6419                 break;
6420         default:
6421                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6422                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6423                                 << 32;
6424         }
6425
6426         return systime_cycles;
6427 }
6428
6429 static uint64_t
6430 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6431 {
6432         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6433         uint64_t rx_tstamp_cycles;
6434
6435         switch (hw->mac.type) {
6436         case ixgbe_mac_X550:
6437         case ixgbe_mac_X550EM_x:
6438         case ixgbe_mac_X550EM_a:
6439                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6440                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6441                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6442                                 * NSEC_PER_SEC;
6443                 break;
6444         default:
6445                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6446                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6447                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6448                                 << 32;
6449         }
6450
6451         return rx_tstamp_cycles;
6452 }
6453
6454 static uint64_t
6455 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6456 {
6457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6458         uint64_t tx_tstamp_cycles;
6459
6460         switch (hw->mac.type) {
6461         case ixgbe_mac_X550:
6462         case ixgbe_mac_X550EM_x:
6463         case ixgbe_mac_X550EM_a:
6464                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6465                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6466                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6467                                 * NSEC_PER_SEC;
6468                 break;
6469         default:
6470                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6471                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6472                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6473                                 << 32;
6474         }
6475
6476         return tx_tstamp_cycles;
6477 }
6478
6479 static void
6480 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6481 {
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483         struct ixgbe_adapter *adapter =
6484                 (struct ixgbe_adapter *)dev->data->dev_private;
6485         struct rte_eth_link link;
6486         uint32_t incval = 0;
6487         uint32_t shift = 0;
6488
6489         /* Get current link speed. */
6490         memset(&link, 0, sizeof(link));
6491         ixgbe_dev_link_update(dev, 1);
6492         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6493
6494         switch (link.link_speed) {
6495         case ETH_SPEED_NUM_100M:
6496                 incval = IXGBE_INCVAL_100;
6497                 shift = IXGBE_INCVAL_SHIFT_100;
6498                 break;
6499         case ETH_SPEED_NUM_1G:
6500                 incval = IXGBE_INCVAL_1GB;
6501                 shift = IXGBE_INCVAL_SHIFT_1GB;
6502                 break;
6503         case ETH_SPEED_NUM_10G:
6504         default:
6505                 incval = IXGBE_INCVAL_10GB;
6506                 shift = IXGBE_INCVAL_SHIFT_10GB;
6507                 break;
6508         }
6509
6510         switch (hw->mac.type) {
6511         case ixgbe_mac_X550:
6512         case ixgbe_mac_X550EM_x:
6513         case ixgbe_mac_X550EM_a:
6514                 /* Independent of link speed. */
6515                 incval = 1;
6516                 /* Cycles read will be interpreted as ns. */
6517                 shift = 0;
6518                 /* Fall-through */
6519         case ixgbe_mac_X540:
6520                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6521                 break;
6522         case ixgbe_mac_82599EB:
6523                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6524                 shift -= IXGBE_INCVAL_SHIFT_82599;
6525                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6526                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6527                 break;
6528         default:
6529                 /* Not supported. */
6530                 return;
6531         }
6532
6533         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6534         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6535         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6536
6537         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6538         adapter->systime_tc.cc_shift = shift;
6539         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6540
6541         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6542         adapter->rx_tstamp_tc.cc_shift = shift;
6543         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6544
6545         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6546         adapter->tx_tstamp_tc.cc_shift = shift;
6547         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6548 }
6549
6550 static int
6551 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6552 {
6553         struct ixgbe_adapter *adapter =
6554                         (struct ixgbe_adapter *)dev->data->dev_private;
6555
6556         adapter->systime_tc.nsec += delta;
6557         adapter->rx_tstamp_tc.nsec += delta;
6558         adapter->tx_tstamp_tc.nsec += delta;
6559
6560         return 0;
6561 }
6562
6563 static int
6564 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6565 {
6566         uint64_t ns;
6567         struct ixgbe_adapter *adapter =
6568                         (struct ixgbe_adapter *)dev->data->dev_private;
6569
6570         ns = rte_timespec_to_ns(ts);
6571         /* Set the timecounters to a new value. */
6572         adapter->systime_tc.nsec = ns;
6573         adapter->rx_tstamp_tc.nsec = ns;
6574         adapter->tx_tstamp_tc.nsec = ns;
6575
6576         return 0;
6577 }
6578
6579 static int
6580 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6581 {
6582         uint64_t ns, systime_cycles;
6583         struct ixgbe_adapter *adapter =
6584                         (struct ixgbe_adapter *)dev->data->dev_private;
6585
6586         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6587         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6588         *ts = rte_ns_to_timespec(ns);
6589
6590         return 0;
6591 }
6592
6593 static int
6594 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6595 {
6596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6597         uint32_t tsync_ctl;
6598         uint32_t tsauxc;
6599
6600         /* Stop the timesync system time. */
6601         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6602         /* Reset the timesync system time value. */
6603         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6604         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6605
6606         /* Enable system time for platforms where it isn't on by default. */
6607         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6608         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6609         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6610
6611         ixgbe_start_timecounters(dev);
6612
6613         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6614         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6615                         (ETHER_TYPE_1588 |
6616                          IXGBE_ETQF_FILTER_EN |
6617                          IXGBE_ETQF_1588));
6618
6619         /* Enable timestamping of received PTP packets. */
6620         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6621         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6622         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6623
6624         /* Enable timestamping of transmitted PTP packets. */
6625         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6626         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6627         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6628
6629         IXGBE_WRITE_FLUSH(hw);
6630
6631         return 0;
6632 }
6633
6634 static int
6635 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6636 {
6637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6638         uint32_t tsync_ctl;
6639
6640         /* Disable timestamping of transmitted PTP packets. */
6641         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6642         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6643         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6644
6645         /* Disable timestamping of received PTP packets. */
6646         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6647         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6648         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6649
6650         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6651         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6652
6653         /* Stop incrementating the System Time registers. */
6654         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6655
6656         return 0;
6657 }
6658
6659 static int
6660 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6661                                  struct timespec *timestamp,
6662                                  uint32_t flags __rte_unused)
6663 {
6664         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6665         struct ixgbe_adapter *adapter =
6666                 (struct ixgbe_adapter *)dev->data->dev_private;
6667         uint32_t tsync_rxctl;
6668         uint64_t rx_tstamp_cycles;
6669         uint64_t ns;
6670
6671         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6672         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6673                 return -EINVAL;
6674
6675         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6676         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6677         *timestamp = rte_ns_to_timespec(ns);
6678
6679         return  0;
6680 }
6681
6682 static int
6683 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6684                                  struct timespec *timestamp)
6685 {
6686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687         struct ixgbe_adapter *adapter =
6688                 (struct ixgbe_adapter *)dev->data->dev_private;
6689         uint32_t tsync_txctl;
6690         uint64_t tx_tstamp_cycles;
6691         uint64_t ns;
6692
6693         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6694         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6695                 return -EINVAL;
6696
6697         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6698         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6699         *timestamp = rte_ns_to_timespec(ns);
6700
6701         return 0;
6702 }
6703
6704 static int
6705 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6706 {
6707         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708         int count = 0;
6709         int g_ind = 0;
6710         const struct reg_info *reg_group;
6711         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6712                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6713
6714         while ((reg_group = reg_set[g_ind++]))
6715                 count += ixgbe_regs_group_count(reg_group);
6716
6717         return count;
6718 }
6719
6720 static int
6721 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6722 {
6723         int count = 0;
6724         int g_ind = 0;
6725         const struct reg_info *reg_group;
6726
6727         while ((reg_group = ixgbevf_regs[g_ind++]))
6728                 count += ixgbe_regs_group_count(reg_group);
6729
6730         return count;
6731 }
6732
6733 static int
6734 ixgbe_get_regs(struct rte_eth_dev *dev,
6735               struct rte_dev_reg_info *regs)
6736 {
6737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6738         uint32_t *data = regs->data;
6739         int g_ind = 0;
6740         int count = 0;
6741         const struct reg_info *reg_group;
6742         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6743                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6744
6745         if (data == NULL) {
6746                 regs->length = ixgbe_get_reg_length(dev);
6747                 regs->width = sizeof(uint32_t);
6748                 return 0;
6749         }
6750
6751         /* Support only full register dump */
6752         if ((regs->length == 0) ||
6753             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6754                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6755                         hw->device_id;
6756                 while ((reg_group = reg_set[g_ind++]))
6757                         count += ixgbe_read_regs_group(dev, &data[count],
6758                                 reg_group);
6759                 return 0;
6760         }
6761
6762         return -ENOTSUP;
6763 }
6764
6765 static int
6766 ixgbevf_get_regs(struct rte_eth_dev *dev,
6767                 struct rte_dev_reg_info *regs)
6768 {
6769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770         uint32_t *data = regs->data;
6771         int g_ind = 0;
6772         int count = 0;
6773         const struct reg_info *reg_group;
6774
6775         if (data == NULL) {
6776                 regs->length = ixgbevf_get_reg_length(dev);
6777                 regs->width = sizeof(uint32_t);
6778                 return 0;
6779         }
6780
6781         /* Support only full register dump */
6782         if ((regs->length == 0) ||
6783             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6784                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6785                         hw->device_id;
6786                 while ((reg_group = ixgbevf_regs[g_ind++]))
6787                         count += ixgbe_read_regs_group(dev, &data[count],
6788                                                       reg_group);
6789                 return 0;
6790         }
6791
6792         return -ENOTSUP;
6793 }
6794
6795 static int
6796 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6797 {
6798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799
6800         /* Return unit is byte count */
6801         return hw->eeprom.word_size * 2;
6802 }
6803
6804 static int
6805 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6806                 struct rte_dev_eeprom_info *in_eeprom)
6807 {
6808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6809         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6810         uint16_t *data = in_eeprom->data;
6811         int first, length;
6812
6813         first = in_eeprom->offset >> 1;
6814         length = in_eeprom->length >> 1;
6815         if ((first > hw->eeprom.word_size) ||
6816             ((first + length) > hw->eeprom.word_size))
6817                 return -EINVAL;
6818
6819         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6820
6821         return eeprom->ops.read_buffer(hw, first, length, data);
6822 }
6823
6824 static int
6825 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6826                 struct rte_dev_eeprom_info *in_eeprom)
6827 {
6828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6829         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6830         uint16_t *data = in_eeprom->data;
6831         int first, length;
6832
6833         first = in_eeprom->offset >> 1;
6834         length = in_eeprom->length >> 1;
6835         if ((first > hw->eeprom.word_size) ||
6836             ((first + length) > hw->eeprom.word_size))
6837                 return -EINVAL;
6838
6839         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6840
6841         return eeprom->ops.write_buffer(hw,  first, length, data);
6842 }
6843
6844 uint16_t
6845 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6846         switch (mac_type) {
6847         case ixgbe_mac_X550:
6848         case ixgbe_mac_X550EM_x:
6849         case ixgbe_mac_X550EM_a:
6850                 return ETH_RSS_RETA_SIZE_512;
6851         case ixgbe_mac_X550_vf:
6852         case ixgbe_mac_X550EM_x_vf:
6853         case ixgbe_mac_X550EM_a_vf:
6854                 return ETH_RSS_RETA_SIZE_64;
6855         default:
6856                 return ETH_RSS_RETA_SIZE_128;
6857         }
6858 }
6859
6860 uint32_t
6861 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6862         switch (mac_type) {
6863         case ixgbe_mac_X550:
6864         case ixgbe_mac_X550EM_x:
6865         case ixgbe_mac_X550EM_a:
6866                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6867                         return IXGBE_RETA(reta_idx >> 2);
6868                 else
6869                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6870         case ixgbe_mac_X550_vf:
6871         case ixgbe_mac_X550EM_x_vf:
6872         case ixgbe_mac_X550EM_a_vf:
6873                 return IXGBE_VFRETA(reta_idx >> 2);
6874         default:
6875                 return IXGBE_RETA(reta_idx >> 2);
6876         }
6877 }
6878
6879 uint32_t
6880 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6881         switch (mac_type) {
6882         case ixgbe_mac_X550_vf:
6883         case ixgbe_mac_X550EM_x_vf:
6884         case ixgbe_mac_X550EM_a_vf:
6885                 return IXGBE_VFMRQC;
6886         default:
6887                 return IXGBE_MRQC;
6888         }
6889 }
6890
6891 uint32_t
6892 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6893         switch (mac_type) {
6894         case ixgbe_mac_X550_vf:
6895         case ixgbe_mac_X550EM_x_vf:
6896         case ixgbe_mac_X550EM_a_vf:
6897                 return IXGBE_VFRSSRK(i);
6898         default:
6899                 return IXGBE_RSSRK(i);
6900         }
6901 }
6902
6903 bool
6904 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6905         switch (mac_type) {
6906         case ixgbe_mac_82599_vf:
6907         case ixgbe_mac_X540_vf:
6908                 return 0;
6909         default:
6910                 return 1;
6911         }
6912 }
6913
6914 static int
6915 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6916                         struct rte_eth_dcb_info *dcb_info)
6917 {
6918         struct ixgbe_dcb_config *dcb_config =
6919                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6920         struct ixgbe_dcb_tc_config *tc;
6921         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
6922         uint8_t nb_tcs;
6923         uint8_t i, j;
6924
6925         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6926                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6927         else
6928                 dcb_info->nb_tcs = 1;
6929
6930         tc_queue = &dcb_info->tc_queue;
6931         nb_tcs = dcb_info->nb_tcs;
6932
6933         if (dcb_config->vt_mode) { /* vt is enabled*/
6934                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6935                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6936                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6937                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6938                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
6939                         for (j = 0; j < nb_tcs; j++) {
6940                                 tc_queue->tc_rxq[0][j].base = j;
6941                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
6942                                 tc_queue->tc_txq[0][j].base = j;
6943                                 tc_queue->tc_txq[0][j].nb_queue = 1;
6944                         }
6945                 } else {
6946                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6947                                 for (j = 0; j < nb_tcs; j++) {
6948                                         tc_queue->tc_rxq[i][j].base =
6949                                                 i * nb_tcs + j;
6950                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
6951                                         tc_queue->tc_txq[i][j].base =
6952                                                 i * nb_tcs + j;
6953                                         tc_queue->tc_txq[i][j].nb_queue = 1;
6954                                 }
6955                         }
6956                 }
6957         } else { /* vt is disabled*/
6958                 struct rte_eth_dcb_rx_conf *rx_conf =
6959                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6960                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6961                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6962                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6963                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6964                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6965                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6966                         }
6967                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6968                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6969                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6970                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6971                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6972                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6973                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6974                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6975                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6976                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6977                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6978                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6979                         }
6980                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6981                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6982                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6983                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6984                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6985                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6986                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6987                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6988                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6989                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6990                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6991                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6992                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6993                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6994                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6995                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6996                 }
6997         }
6998         for (i = 0; i < dcb_info->nb_tcs; i++) {
6999                 tc = &dcb_config->tc_config[i];
7000                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7001         }
7002         return 0;
7003 }
7004
7005 /* Update e-tag ether type */
7006 static int
7007 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7008                             uint16_t ether_type)
7009 {
7010         uint32_t etag_etype;
7011
7012         if (hw->mac.type != ixgbe_mac_X550 &&
7013             hw->mac.type != ixgbe_mac_X550EM_x &&
7014             hw->mac.type != ixgbe_mac_X550EM_a) {
7015                 return -ENOTSUP;
7016         }
7017
7018         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7019         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7020         etag_etype |= ether_type;
7021         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7022         IXGBE_WRITE_FLUSH(hw);
7023
7024         return 0;
7025 }
7026
7027 /* Config l2 tunnel ether type */
7028 static int
7029 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7030                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7031 {
7032         int ret = 0;
7033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034
7035         if (l2_tunnel == NULL)
7036                 return -EINVAL;
7037
7038         switch (l2_tunnel->l2_tunnel_type) {
7039         case RTE_L2_TUNNEL_TYPE_E_TAG:
7040                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7041                 break;
7042         default:
7043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7044                 ret = -EINVAL;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 /* Enable e-tag tunnel */
7052 static int
7053 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7054 {
7055         uint32_t etag_etype;
7056
7057         if (hw->mac.type != ixgbe_mac_X550 &&
7058             hw->mac.type != ixgbe_mac_X550EM_x &&
7059             hw->mac.type != ixgbe_mac_X550EM_a) {
7060                 return -ENOTSUP;
7061         }
7062
7063         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7064         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7065         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7066         IXGBE_WRITE_FLUSH(hw);
7067
7068         return 0;
7069 }
7070
7071 /* Enable l2 tunnel */
7072 static int
7073 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7074                            enum rte_eth_tunnel_type l2_tunnel_type)
7075 {
7076         int ret = 0;
7077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7078
7079         switch (l2_tunnel_type) {
7080         case RTE_L2_TUNNEL_TYPE_E_TAG:
7081                 ret = ixgbe_e_tag_enable(hw);
7082                 break;
7083         default:
7084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7085                 ret = -EINVAL;
7086                 break;
7087         }
7088
7089         return ret;
7090 }
7091
7092 /* Disable e-tag tunnel */
7093 static int
7094 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7095 {
7096         uint32_t etag_etype;
7097
7098         if (hw->mac.type != ixgbe_mac_X550 &&
7099             hw->mac.type != ixgbe_mac_X550EM_x &&
7100             hw->mac.type != ixgbe_mac_X550EM_a) {
7101                 return -ENOTSUP;
7102         }
7103
7104         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7105         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7106         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7107         IXGBE_WRITE_FLUSH(hw);
7108
7109         return 0;
7110 }
7111
7112 /* Disable l2 tunnel */
7113 static int
7114 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7115                             enum rte_eth_tunnel_type l2_tunnel_type)
7116 {
7117         int ret = 0;
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119
7120         switch (l2_tunnel_type) {
7121         case RTE_L2_TUNNEL_TYPE_E_TAG:
7122                 ret = ixgbe_e_tag_disable(hw);
7123                 break;
7124         default:
7125                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7126                 ret = -EINVAL;
7127                 break;
7128         }
7129
7130         return ret;
7131 }
7132
7133 static int
7134 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7135                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7136 {
7137         int ret = 0;
7138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139         uint32_t i, rar_entries;
7140         uint32_t rar_low, rar_high;
7141
7142         if (hw->mac.type != ixgbe_mac_X550 &&
7143             hw->mac.type != ixgbe_mac_X550EM_x &&
7144             hw->mac.type != ixgbe_mac_X550EM_a) {
7145                 return -ENOTSUP;
7146         }
7147
7148         rar_entries = ixgbe_get_num_rx_addrs(hw);
7149
7150         for (i = 1; i < rar_entries; i++) {
7151                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7152                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7153                 if ((rar_high & IXGBE_RAH_AV) &&
7154                     (rar_high & IXGBE_RAH_ADTYPE) &&
7155                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7156                      l2_tunnel->tunnel_id)) {
7157                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7158                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7159
7160                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7161
7162                         return ret;
7163                 }
7164         }
7165
7166         return ret;
7167 }
7168
7169 static int
7170 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7171                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7172 {
7173         int ret = 0;
7174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7175         uint32_t i, rar_entries;
7176         uint32_t rar_low, rar_high;
7177
7178         if (hw->mac.type != ixgbe_mac_X550 &&
7179             hw->mac.type != ixgbe_mac_X550EM_x &&
7180             hw->mac.type != ixgbe_mac_X550EM_a) {
7181                 return -ENOTSUP;
7182         }
7183
7184         /* One entry for one tunnel. Try to remove potential existing entry. */
7185         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7186
7187         rar_entries = ixgbe_get_num_rx_addrs(hw);
7188
7189         for (i = 1; i < rar_entries; i++) {
7190                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7191                 if (rar_high & IXGBE_RAH_AV) {
7192                         continue;
7193                 } else {
7194                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7195                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7196                         rar_low = l2_tunnel->tunnel_id;
7197
7198                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7199                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7200
7201                         return ret;
7202                 }
7203         }
7204
7205         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7206                      " Please remove a rule before adding a new one.");
7207         return -EINVAL;
7208 }
7209
7210 /* Add l2 tunnel filter */
7211 static int
7212 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7213                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7214 {
7215         int ret = 0;
7216
7217         switch (l2_tunnel->l2_tunnel_type) {
7218         case RTE_L2_TUNNEL_TYPE_E_TAG:
7219                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7220                 break;
7221         default:
7222                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7223                 ret = -EINVAL;
7224                 break;
7225         }
7226
7227         return ret;
7228 }
7229
7230 /* Delete l2 tunnel filter */
7231 static int
7232 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7233                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7234 {
7235         int ret = 0;
7236
7237         switch (l2_tunnel->l2_tunnel_type) {
7238         case RTE_L2_TUNNEL_TYPE_E_TAG:
7239                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7240                 break;
7241         default:
7242                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7243                 ret = -EINVAL;
7244                 break;
7245         }
7246
7247         return ret;
7248 }
7249
7250 /**
7251  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7252  * @dev: pointer to rte_eth_dev structure
7253  * @filter_op:operation will be taken.
7254  * @arg: a pointer to specific structure corresponding to the filter_op
7255  */
7256 static int
7257 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7258                                   enum rte_filter_op filter_op,
7259                                   void *arg)
7260 {
7261         int ret = 0;
7262
7263         if (filter_op == RTE_ETH_FILTER_NOP)
7264                 return 0;
7265
7266         if (arg == NULL) {
7267                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7268                             filter_op);
7269                 return -EINVAL;
7270         }
7271
7272         switch (filter_op) {
7273         case RTE_ETH_FILTER_ADD:
7274                 ret = ixgbe_dev_l2_tunnel_filter_add
7275                         (dev,
7276                          (struct rte_eth_l2_tunnel_conf *)arg);
7277                 break;
7278         case RTE_ETH_FILTER_DELETE:
7279                 ret = ixgbe_dev_l2_tunnel_filter_del
7280                         (dev,
7281                          (struct rte_eth_l2_tunnel_conf *)arg);
7282                 break;
7283         default:
7284                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7285                 ret = -EINVAL;
7286                 break;
7287         }
7288         return ret;
7289 }
7290
7291 static int
7292 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7293 {
7294         int ret = 0;
7295         uint32_t ctrl;
7296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7297
7298         if (hw->mac.type != ixgbe_mac_X550 &&
7299             hw->mac.type != ixgbe_mac_X550EM_x &&
7300             hw->mac.type != ixgbe_mac_X550EM_a) {
7301                 return -ENOTSUP;
7302         }
7303
7304         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7305         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7306         if (en)
7307                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7308         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7309
7310         return ret;
7311 }
7312
7313 /* Enable l2 tunnel forwarding */
7314 static int
7315 ixgbe_dev_l2_tunnel_forwarding_enable
7316         (struct rte_eth_dev *dev,
7317          enum rte_eth_tunnel_type l2_tunnel_type)
7318 {
7319         int ret = 0;
7320
7321         switch (l2_tunnel_type) {
7322         case RTE_L2_TUNNEL_TYPE_E_TAG:
7323                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7324                 break;
7325         default:
7326                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7327                 ret = -EINVAL;
7328                 break;
7329         }
7330
7331         return ret;
7332 }
7333
7334 /* Disable l2 tunnel forwarding */
7335 static int
7336 ixgbe_dev_l2_tunnel_forwarding_disable
7337         (struct rte_eth_dev *dev,
7338          enum rte_eth_tunnel_type l2_tunnel_type)
7339 {
7340         int ret = 0;
7341
7342         switch (l2_tunnel_type) {
7343         case RTE_L2_TUNNEL_TYPE_E_TAG:
7344                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7345                 break;
7346         default:
7347                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7348                 ret = -EINVAL;
7349                 break;
7350         }
7351
7352         return ret;
7353 }
7354
7355 static int
7356 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7357                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7358                              bool en)
7359 {
7360         int ret = 0;
7361         uint32_t vmtir, vmvir;
7362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363
7364         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7365                 PMD_DRV_LOG(ERR,
7366                             "VF id %u should be less than %u",
7367                             l2_tunnel->vf_id,
7368                             dev->pci_dev->max_vfs);
7369                 return -EINVAL;
7370         }
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         if (en)
7379                 vmtir = l2_tunnel->tunnel_id;
7380         else
7381                 vmtir = 0;
7382
7383         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7384
7385         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7386         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7387         if (en)
7388                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7389         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7390
7391         return ret;
7392 }
7393
7394 /* Enable l2 tunnel tag insertion */
7395 static int
7396 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7397                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7398 {
7399         int ret = 0;
7400
7401         switch (l2_tunnel->l2_tunnel_type) {
7402         case RTE_L2_TUNNEL_TYPE_E_TAG:
7403                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7404                 break;
7405         default:
7406                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7407                 ret = -EINVAL;
7408                 break;
7409         }
7410
7411         return ret;
7412 }
7413
7414 /* Disable l2 tunnel tag insertion */
7415 static int
7416 ixgbe_dev_l2_tunnel_insertion_disable
7417         (struct rte_eth_dev *dev,
7418          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7419 {
7420         int ret = 0;
7421
7422         switch (l2_tunnel->l2_tunnel_type) {
7423         case RTE_L2_TUNNEL_TYPE_E_TAG:
7424                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7425                 break;
7426         default:
7427                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7428                 ret = -EINVAL;
7429                 break;
7430         }
7431
7432         return ret;
7433 }
7434
7435 static int
7436 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7437                              bool en)
7438 {
7439         int ret = 0;
7440         uint32_t qde;
7441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7442
7443         if (hw->mac.type != ixgbe_mac_X550 &&
7444             hw->mac.type != ixgbe_mac_X550EM_x &&
7445             hw->mac.type != ixgbe_mac_X550EM_a) {
7446                 return -ENOTSUP;
7447         }
7448
7449         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7450         if (en)
7451                 qde |= IXGBE_QDE_STRIP_TAG;
7452         else
7453                 qde &= ~IXGBE_QDE_STRIP_TAG;
7454         qde &= ~IXGBE_QDE_READ;
7455         qde |= IXGBE_QDE_WRITE;
7456         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7457
7458         return ret;
7459 }
7460
7461 /* Enable l2 tunnel tag stripping */
7462 static int
7463 ixgbe_dev_l2_tunnel_stripping_enable
7464         (struct rte_eth_dev *dev,
7465          enum rte_eth_tunnel_type l2_tunnel_type)
7466 {
7467         int ret = 0;
7468
7469         switch (l2_tunnel_type) {
7470         case RTE_L2_TUNNEL_TYPE_E_TAG:
7471                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7472                 break;
7473         default:
7474                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7475                 ret = -EINVAL;
7476                 break;
7477         }
7478
7479         return ret;
7480 }
7481
7482 /* Disable l2 tunnel tag stripping */
7483 static int
7484 ixgbe_dev_l2_tunnel_stripping_disable
7485         (struct rte_eth_dev *dev,
7486          enum rte_eth_tunnel_type l2_tunnel_type)
7487 {
7488         int ret = 0;
7489
7490         switch (l2_tunnel_type) {
7491         case RTE_L2_TUNNEL_TYPE_E_TAG:
7492                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7493                 break;
7494         default:
7495                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7496                 ret = -EINVAL;
7497                 break;
7498         }
7499
7500         return ret;
7501 }
7502
7503 /* Enable/disable l2 tunnel offload functions */
7504 static int
7505 ixgbe_dev_l2_tunnel_offload_set
7506         (struct rte_eth_dev *dev,
7507          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7508          uint32_t mask,
7509          uint8_t en)
7510 {
7511         int ret = 0;
7512
7513         if (l2_tunnel == NULL)
7514                 return -EINVAL;
7515
7516         ret = -EINVAL;
7517         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7518                 if (en)
7519                         ret = ixgbe_dev_l2_tunnel_enable(
7520                                 dev,
7521                                 l2_tunnel->l2_tunnel_type);
7522                 else
7523                         ret = ixgbe_dev_l2_tunnel_disable(
7524                                 dev,
7525                                 l2_tunnel->l2_tunnel_type);
7526         }
7527
7528         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7529                 if (en)
7530                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7531                                 dev,
7532                                 l2_tunnel);
7533                 else
7534                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7535                                 dev,
7536                                 l2_tunnel);
7537         }
7538
7539         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7540                 if (en)
7541                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7542                                 dev,
7543                                 l2_tunnel->l2_tunnel_type);
7544                 else
7545                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7546                                 dev,
7547                                 l2_tunnel->l2_tunnel_type);
7548         }
7549
7550         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7551                 if (en)
7552                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7553                                 dev,
7554                                 l2_tunnel->l2_tunnel_type);
7555                 else
7556                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7557                                 dev,
7558                                 l2_tunnel->l2_tunnel_type);
7559         }
7560
7561         return ret;
7562 }
7563
7564 static int
7565 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7566                         uint16_t port)
7567 {
7568         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7569         IXGBE_WRITE_FLUSH(hw);
7570
7571         return 0;
7572 }
7573
7574 /* There's only one register for VxLAN UDP port.
7575  * So, we cannot add several ports. Will update it.
7576  */
7577 static int
7578 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7579                      uint16_t port)
7580 {
7581         if (port == 0) {
7582                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7583                 return -EINVAL;
7584         }
7585
7586         return ixgbe_update_vxlan_port(hw, port);
7587 }
7588
7589 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7590  * UDP port, it must have a value.
7591  * So, will reset it to the original value 0.
7592  */
7593 static int
7594 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7595                      uint16_t port)
7596 {
7597         uint16_t cur_port;
7598
7599         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7600
7601         if (cur_port != port) {
7602                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7603                 return -EINVAL;
7604         }
7605
7606         return ixgbe_update_vxlan_port(hw, 0);
7607 }
7608
7609 /* Add UDP tunneling port */
7610 static int
7611 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7612                               struct rte_eth_udp_tunnel *udp_tunnel)
7613 {
7614         int ret = 0;
7615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7616
7617         if (hw->mac.type != ixgbe_mac_X550 &&
7618             hw->mac.type != ixgbe_mac_X550EM_x &&
7619             hw->mac.type != ixgbe_mac_X550EM_a) {
7620                 return -ENOTSUP;
7621         }
7622
7623         if (udp_tunnel == NULL)
7624                 return -EINVAL;
7625
7626         switch (udp_tunnel->prot_type) {
7627         case RTE_TUNNEL_TYPE_VXLAN:
7628                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7629                 break;
7630
7631         case RTE_TUNNEL_TYPE_GENEVE:
7632         case RTE_TUNNEL_TYPE_TEREDO:
7633                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7634                 ret = -EINVAL;
7635                 break;
7636
7637         default:
7638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7639                 ret = -EINVAL;
7640                 break;
7641         }
7642
7643         return ret;
7644 }
7645
7646 /* Remove UDP tunneling port */
7647 static int
7648 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7649                               struct rte_eth_udp_tunnel *udp_tunnel)
7650 {
7651         int ret = 0;
7652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7653
7654         if (hw->mac.type != ixgbe_mac_X550 &&
7655             hw->mac.type != ixgbe_mac_X550EM_x &&
7656             hw->mac.type != ixgbe_mac_X550EM_a) {
7657                 return -ENOTSUP;
7658         }
7659
7660         if (udp_tunnel == NULL)
7661                 return -EINVAL;
7662
7663         switch (udp_tunnel->prot_type) {
7664         case RTE_TUNNEL_TYPE_VXLAN:
7665                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7666                 break;
7667         case RTE_TUNNEL_TYPE_GENEVE:
7668         case RTE_TUNNEL_TYPE_TEREDO:
7669                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7670                 ret = -EINVAL;
7671                 break;
7672         default:
7673                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7674                 ret = -EINVAL;
7675                 break;
7676         }
7677
7678         return ret;
7679 }
7680
7681 static void
7682 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7683 {
7684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7685
7686         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7687 }
7688
7689 static void
7690 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7691 {
7692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7693
7694         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7695 }
7696
7697 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7698 {
7699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7700         u32 in_msg = 0;
7701
7702         /* peek the message first */
7703         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7704
7705         /* PF reset VF event */
7706         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7707                 /* dummy mbx read to ack pf */
7708                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7709                         return;
7710                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7711                                               NULL);
7712         }
7713 }
7714
7715 static int
7716 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7717 {
7718         uint32_t eicr;
7719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7720         struct ixgbe_interrupt *intr =
7721                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7722         ixgbevf_intr_disable(hw);
7723
7724         /* read-on-clear nic registers here */
7725         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7726         intr->flags = 0;
7727
7728         /* only one misc vector supported - mailbox */
7729         eicr &= IXGBE_VTEICR_MASK;
7730         if (eicr == IXGBE_MISC_VEC_ID)
7731                 intr->flags |= IXGBE_FLAG_MAILBOX;
7732
7733         return 0;
7734 }
7735
7736 static int
7737 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7738 {
7739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7740         struct ixgbe_interrupt *intr =
7741                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7742
7743         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7744                 ixgbevf_mbx_process(dev);
7745                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7746         }
7747
7748         ixgbevf_intr_enable(hw);
7749
7750         return 0;
7751 }
7752
7753 static void
7754 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7755                               void *param)
7756 {
7757         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7758
7759         ixgbevf_dev_interrupt_get_status(dev);
7760         ixgbevf_dev_interrupt_action(dev);
7761 }
7762
7763 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7764 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7765 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7766 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);