drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         __rte_unused unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         __rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 270                 struct rte_eth_stats *stats);
 271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 273                 uint16_t vlan_id, int on);
 274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 275                 uint16_t queue, int on);
 276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                             uint16_t queue_id);
 280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                              uint16_t queue_id);
 282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                  uint8_t queue, uint8_t msix_vector);
 284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 287
 288 /* For Eth VMDQ APIs support */
 289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 290                 ether_addr * mac_addr, uint8_t on);
 291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 293                 struct rte_eth_mirror_conf *mirror_conf,
 294                 uint8_t rule_id, uint8_t on);
 295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 296                 uint8_t rule_id);
 297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 298                                           uint16_t queue_id);
 299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 300                                            uint16_t queue_id);
 301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 302                                uint8_t queue, uint8_t msix_vector);
 303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 304
 305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 306                 uint16_t queue_idx, uint16_t tx_rate);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_NIC_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .fw_version_get       = ixgbe_fw_version_get,
 542         .dev_infos_get        = ixgbe_dev_info_get,
 543         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 544         .mtu_set              = ixgbe_dev_mtu_set,
 545         .vlan_filter_set      = ixgbe_vlan_filter_set,
 546         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 547         .vlan_offload_set     = ixgbe_vlan_offload_set,
 548         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 549         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 550         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 551         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 552         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 553         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 554         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 555         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 556         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 557         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 558         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 559         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 560         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .reta_update          = ixgbe_dev_rss_reta_update,
 577         .reta_query           = ixgbe_dev_rss_reta_query,
 578 #ifdef RTE_NIC_BYPASS
 579         .bypass_init          = ixgbe_bypass_init,
 580         .bypass_state_set     = ixgbe_bypass_state_store,
 581         .bypass_state_show    = ixgbe_bypass_state_show,
 582         .bypass_event_set     = ixgbe_bypass_event_store,
 583         .bypass_event_show    = ixgbe_bypass_event_show,
 584         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 585         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 586         .bypass_ver_show      = ixgbe_bypass_ver_show,
 587         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 588 #endif /* RTE_NIC_BYPASS */
 589         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 590         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 591         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 592         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 593         .rxq_info_get         = ixgbe_rxq_info_get,
 594         .txq_info_get         = ixgbe_txq_info_get,
 595         .timesync_enable      = ixgbe_timesync_enable,
 596         .timesync_disable     = ixgbe_timesync_disable,
 597         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 598         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 599         .get_reg              = ixgbe_get_regs,
 600         .get_eeprom_length    = ixgbe_get_eeprom_length,
 601         .get_eeprom           = ixgbe_get_eeprom,
 602         .set_eeprom           = ixgbe_set_eeprom,
 603         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 604         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 605         .timesync_read_time   = ixgbe_timesync_read_time,
 606         .timesync_write_time  = ixgbe_timesync_write_time,
 607         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 608         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 609         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 610         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 611 };
 612
 613 /*
 614  * dev_ops for virtual function, bare necessities for basic vf
 615  * operation have been implemented
 616  */
 617 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 618         .dev_configure        = ixgbevf_dev_configure,
 619         .dev_start            = ixgbevf_dev_start,
 620         .dev_stop             = ixgbevf_dev_stop,
 621         .link_update          = ixgbe_dev_link_update,
 622         .stats_get            = ixgbevf_dev_stats_get,
 623         .xstats_get           = ixgbevf_dev_xstats_get,
 624         .stats_reset          = ixgbevf_dev_stats_reset,
 625         .xstats_reset         = ixgbevf_dev_stats_reset,
 626         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 627         .dev_close            = ixgbevf_dev_close,
 628         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 629         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 630         .dev_infos_get        = ixgbevf_dev_info_get,
 631         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 632         .mtu_set              = ixgbevf_dev_set_mtu,
 633         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 634         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 635         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 636         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 637         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 638         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 639         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 640         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* MACsec statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 750         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_untagged)},
 752         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_encrypted)},
 754         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_protected)},
 756         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 757                 out_octets_encrypted)},
 758         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_protected)},
 760         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_untagged)},
 762         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_badtag)},
 764         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_nosci)},
 766         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unknownsci)},
 768         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 769                 in_octets_decrypted)},
 770         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_validated)},
 772         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unchecked)},
 774         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_delayed)},
 776         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_late)},
 778         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_ok)},
 780         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_invalid)},
 782         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notvalid)},
 784         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_unusedsa)},
 786         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_notusingsa)},
 788 };
 789
 790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 791                            sizeof(rte_ixgbe_macsec_strings[0]))
 792
 793 /* Per-queue statistics */
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 795         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 796         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 797         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 798         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 799 };
 800
 801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 802                            sizeof(rte_ixgbe_rxq_strings[0]))
 803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 806         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 807         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 808         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 809                 pxon2offc)},
 810 };
 811
 812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 813                            sizeof(rte_ixgbe_txq_strings[0]))
 814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 815
 816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 817         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 818 };
 819
 820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 821                 sizeof(rte_ixgbevf_stats_strings[0]))
 822
 823 /**
 824  * Atomically reads the link status information from global
 825  * structure rte_eth_dev.
 826  *
 827  * @param dev
 828  *   - Pointer to the structure rte_eth_dev to read from.
 829  *   - Pointer to the buffer to be saved with the link status.
 830  *
 831  * @return
 832  *   - On success, zero.
 833  *   - On failure, negative value.
 834  */
 835 static inline int
 836 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 837                                 struct rte_eth_link *link)
 838 {
 839         struct rte_eth_link *dst = link;
 840         struct rte_eth_link *src = &(dev->data->dev_link);
 841
 842         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 843                                         *(uint64_t *)src) == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * Atomically writes the link status information into global
 851  * structure rte_eth_dev.
 852  *
 853  * @param dev
 854  *   - Pointer to the structure rte_eth_dev to read from.
 855  *   - Pointer to the buffer to be saved with the link status.
 856  *
 857  * @return
 858  *   - On success, zero.
 859  *   - On failure, negative value.
 860  */
 861 static inline int
 862 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 863                                 struct rte_eth_link *link)
 864 {
 865         struct rte_eth_link *dst = &(dev->data->dev_link);
 866         struct rte_eth_link *src = link;
 867
 868         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 869                                         *(uint64_t *)src) == 0)
 870                 return -1;
 871
 872         return 0;
 873 }
 874
 875 /*
 876  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 877  */
 878 static inline int
 879 ixgbe_is_sfp(struct ixgbe_hw *hw)
 880 {
 881         switch (hw->phy.type) {
 882         case ixgbe_phy_sfp_avago:
 883         case ixgbe_phy_sfp_ftl:
 884         case ixgbe_phy_sfp_intel:
 885         case ixgbe_phy_sfp_unknown:
 886         case ixgbe_phy_sfp_passive_tyco:
 887         case ixgbe_phy_sfp_passive_unknown:
 888                 return 1;
 889         default:
 890                 return 0;
 891         }
 892 }
 893
 894 static inline int32_t
 895 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 896 {
 897         uint32_t ctrl_ext;
 898         int32_t status;
 899
 900         status = ixgbe_reset_hw(hw);
 901
 902         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 903         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 904         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 905         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 906         IXGBE_WRITE_FLUSH(hw);
 907
 908         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 909                 status = IXGBE_SUCCESS;
 910         return status;
 911 }
 912
 913 static inline void
 914 ixgbe_enable_intr(struct rte_eth_dev *dev)
 915 {
 916         struct ixgbe_interrupt *intr =
 917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 922         IXGBE_WRITE_FLUSH(hw);
 923 }
 924
 925 /*
 926  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 927  */
 928 static void
 929 ixgbe_disable_intr(struct ixgbe_hw *hw)
 930 {
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 935         } else {
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 939         }
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /*
 944  * This function resets queue statistics mapping registers.
 945  * From Niantic datasheet, Initialization of Statistics section:
 946  * "...if software requires the queue counters, the RQSMR and TQSM registers
 947  * must be re-programmed following a device reset.
 948  */
 949 static void
 950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 951 {
 952         uint32_t i;
 953
 954         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 956                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 957         }
 958 }
 959
 960
 961 static int
 962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 963                                   uint16_t queue_id,
 964                                   uint8_t stat_idx,
 965                                   uint8_t is_rx)
 966 {
 967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 970
 971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_stat_mapping_registers *stat_mappings =
 973                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 974         uint32_t qsmr_mask = 0;
 975         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 976         uint32_t q_map;
 977         uint8_t n, offset;
 978
 979         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 980                 (hw->mac.type != ixgbe_mac_X540) &&
 981                 (hw->mac.type != ixgbe_mac_X550) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_a))
 984                 return -ENOSYS;
 985
 986         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 987                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 988                      queue_id, stat_idx);
 989
 990         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 991         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 992                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 993                 return -EIO;
 994         }
 995         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 996
 997         /* Now clear any previous stat_idx set */
 998         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] &= ~clearing_mask;
1001         else
1002                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003
1004         q_map = (uint32_t)stat_idx;
1005         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007         if (!is_rx)
1008                 stat_mappings->tqsm[n] |= qsmr_mask;
1009         else
1010                 stat_mappings->rqsmr[n] |= qsmr_mask;
1011
1012         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014                      queue_id, stat_idx);
1015         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017
1018         /* Now write the mapping in the appropriate register */
1019         if (is_rx) {
1020                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021                              stat_mappings->rqsmr[n], n);
1022                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023         } else {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025                              stat_mappings->tqsm[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 {
1034         struct ixgbe_stat_mapping_registers *stat_mappings =
1035                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         int i;
1038
1039         /* write whatever was in stat mapping table to the NIC */
1040         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041                 /* rx */
1042                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043
1044                 /* tx */
1045                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1046         }
1047 }
1048
1049 static void
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 {
1052         uint8_t i;
1053         struct ixgbe_dcb_tc_config *tc;
1054         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055
1056         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058         for (i = 0; i < dcb_max_tc; i++) {
1059                 tc = &dcb_config->tc_config[i];
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1066                 tc->pfc = ixgbe_dcb_pfc_disabled;
1067         }
1068
1069         /* Initialize default user to priority mapping, UPx->TC0 */
1070         tc = &dcb_config->tc_config[0];
1071         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076         }
1077         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078         dcb_config->pfc_mode_enable = false;
1079         dcb_config->vt_mode = true;
1080         dcb_config->round_robin_enable = false;
1081         /* support all DCB capabilities in 82599 */
1082         dcb_config->support.capabilities = 0xFF;
1083
1084         /*we only support 4 Tcs for X540, X550 */
1085         if (hw->mac.type == ixgbe_mac_X540 ||
1086                 hw->mac.type == ixgbe_mac_X550 ||
1087                 hw->mac.type == ixgbe_mac_X550EM_x ||
1088                 hw->mac.type == ixgbe_mac_X550EM_a) {
1089                 dcb_config->num_tcs.pg_tcs = 4;
1090                 dcb_config->num_tcs.pfc_tcs = 4;
1091         }
1092 }
1093
1094 /*
1095  * Ensure that all locks are released before first NVM or PHY access
1096  */
1097 static void
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1099 {
1100         uint16_t mask;
1101
1102         /*
1103          * Phy lock should not fail in this early stage. If this is the case,
1104          * it is due to an improper exit of the application.
1105          * So force the release of the faulty lock. Release of common lock
1106          * is done automatically by swfw_sync function.
1107          */
1108         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113
1114         /*
1115          * These ones are more tricky since they are common to all ports; but
1116          * swfw_sync retries last long enough (1s) to be almost sure that if
1117          * lock can not be taken it is due to an improper lock of the
1118          * semaphore.
1119          */
1120         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123         }
1124         ixgbe_release_swfw_semaphore(hw, mask);
1125 }
1126
1127 /*
1128  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129  * It returns 0 on success.
1130  */
1131 static int
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138         struct ixgbe_vfta *shadow_vfta =
1139                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140         struct ixgbe_hwstrip *hwstrip =
1141                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142         struct ixgbe_dcb_config *dcb_config =
1143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144         struct ixgbe_filter_info *filter_info =
1145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146         struct ixgbe_bw_conf *bw_conf =
1147                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1148         uint32_t ctrl_ext;
1149         uint16_t csum;
1150         int diag, i;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1155         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1156         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1158
1159         /*
1160          * For secondary processes, we don't initialise any further as primary
1161          * has already done this work. Only check we don't need a different
1162          * RX and TX function.
1163          */
1164         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1165                 struct ixgbe_tx_queue *txq;
1166                 /* TX queue function in primary, set by last queue initialized
1167                  * Tx queue may not initialized by primary process
1168                  */
1169                 if (eth_dev->data->tx_queues) {
1170                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1171                         ixgbe_set_tx_function(eth_dev, txq);
1172                 } else {
1173                         /* Use default TX function if we get here */
1174                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1175                                      "Using default TX function.");
1176                 }
1177
1178                 ixgbe_set_rx_function(eth_dev);
1179
1180                 return 0;
1181         }
1182
1183         rte_eth_copy_pci_info(eth_dev, pci_dev);
1184         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1185
1186         /* Vendor and Device ID need to be set before init of shared code */
1187         hw->device_id = pci_dev->id.device_id;
1188         hw->vendor_id = pci_dev->id.vendor_id;
1189         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1190         hw->allow_unsupported_sfp = 1;
1191
1192         /* Initialize the shared code (base driver) */
1193 #ifdef RTE_NIC_BYPASS
1194         diag = ixgbe_bypass_init_shared_code(hw);
1195 #else
1196         diag = ixgbe_init_shared_code(hw);
1197 #endif /* RTE_NIC_BYPASS */
1198
1199         if (diag != IXGBE_SUCCESS) {
1200                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* pick up the PCI bus settings for reporting later */
1205         ixgbe_get_bus_info(hw);
1206
1207         /* Unlock any pending hardware semaphore */
1208         ixgbe_swfw_lock_reset(hw);
1209
1210         /* Initialize DCB configuration*/
1211         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1212         ixgbe_dcb_init(hw, dcb_config);
1213         /* Get Hardware Flow Control setting */
1214         hw->fc.requested_mode = ixgbe_fc_full;
1215         hw->fc.current_mode = ixgbe_fc_full;
1216         hw->fc.pause_time = IXGBE_FC_PAUSE;
1217         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1218                 hw->fc.low_water[i] = IXGBE_FC_LO;
1219                 hw->fc.high_water[i] = IXGBE_FC_HI;
1220         }
1221         hw->fc.send_xon = 1;
1222
1223         /* Make sure we have a good EEPROM before we read from it */
1224         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1225         if (diag != IXGBE_SUCCESS) {
1226                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1227                 return -EIO;
1228         }
1229
1230 #ifdef RTE_NIC_BYPASS
1231         diag = ixgbe_bypass_init_hw(hw);
1232 #else
1233         diag = ixgbe_init_hw(hw);
1234 #endif /* RTE_NIC_BYPASS */
1235
1236         /*
1237          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1238          * is called too soon after the kernel driver unbinding/binding occurs.
1239          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1240          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1241          * also called. See ixgbe_identify_phy_82599(). The reason for the
1242          * failure is not known, and only occuts when virtualisation features
1243          * are disabled in the bios. A delay of 100ms  was found to be enough by
1244          * trial-and-error, and is doubled to be safe.
1245          */
1246         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1247                 rte_delay_ms(200);
1248                 diag = ixgbe_init_hw(hw);
1249         }
1250
1251         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1252                 diag = IXGBE_SUCCESS;
1253
1254         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1255                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1256                              "LOM.  Please be aware there may be issues associated "
1257                              "with your hardware.");
1258                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1259                              "please contact your Intel or hardware representative "
1260                              "who provided you with this hardware.");
1261         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1262                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1263         if (diag) {
1264                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1265                 return -EIO;
1266         }
1267
1268         /* Reset the hw statistics */
1269         ixgbe_dev_stats_reset(eth_dev);
1270
1271         /* disable interrupt */
1272         ixgbe_disable_intr(hw);
1273
1274         /* reset mappings for queue statistics hw counters*/
1275         ixgbe_reset_qstat_mappings(hw);
1276
1277         /* Allocate memory for storing MAC addresses */
1278         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279                                                hw->mac.num_rar_entries, 0);
1280         if (eth_dev->data->mac_addrs == NULL) {
1281                 PMD_INIT_LOG(ERR,
1282                              "Failed to allocate %u bytes needed to store "
1283                              "MAC addresses",
1284                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1285                 return -ENOMEM;
1286         }
1287         /* Copy the permanent MAC address */
1288         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1289                         &eth_dev->data->mac_addrs[0]);
1290
1291         /* Allocate memory for storing hash filter MAC addresses */
1292         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1293                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1294         if (eth_dev->data->hash_mac_addrs == NULL) {
1295                 PMD_INIT_LOG(ERR,
1296                              "Failed to allocate %d bytes needed to store MAC addresses",
1297                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1298                 return -ENOMEM;
1299         }
1300
1301         /* initialize the vfta */
1302         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1303
1304         /* initialize the hw strip bitmap*/
1305         memset(hwstrip, 0, sizeof(*hwstrip));
1306
1307         /* initialize PF if max_vfs not zero */
1308         ixgbe_pf_host_init(eth_dev);
1309
1310         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1311         /* let hardware know driver is loaded */
1312         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1313         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1314         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1315         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1316         IXGBE_WRITE_FLUSH(hw);
1317
1318         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1319                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1320                              (int) hw->mac.type, (int) hw->phy.type,
1321                              (int) hw->phy.sfp_type);
1322         else
1323                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1324                              (int) hw->mac.type, (int) hw->phy.type);
1325
1326         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1327                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1328                      pci_dev->id.device_id);
1329
1330         rte_intr_callback_register(intr_handle,
1331                                    ixgbe_dev_interrupt_handler, eth_dev);
1332
1333         /* enable uio/vfio intr/eventfd mapping */
1334         rte_intr_enable(intr_handle);
1335
1336         /* enable support intr */
1337         ixgbe_enable_intr(eth_dev);
1338
1339         /* initialize filter info */
1340         memset(filter_info, 0,
1341                sizeof(struct ixgbe_filter_info));
1342
1343         /* initialize 5tuple filter list */
1344         TAILQ_INIT(&filter_info->fivetuple_list);
1345
1346         /* initialize flow director filter list & hash */
1347         ixgbe_fdir_filter_init(eth_dev);
1348
1349         /* initialize l2 tunnel filter list & hash */
1350         ixgbe_l2_tn_filter_init(eth_dev);
1351
1352         TAILQ_INIT(&filter_ntuple_list);
1353         TAILQ_INIT(&filter_ethertype_list);
1354         TAILQ_INIT(&filter_syn_list);
1355         TAILQ_INIT(&filter_fdir_list);
1356         TAILQ_INIT(&filter_l2_tunnel_list);
1357         TAILQ_INIT(&ixgbe_flow_list);
1358
1359         /* initialize bandwidth configuration info */
1360         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1361
1362         return 0;
1363 }
1364
1365 static int
1366 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1370         struct ixgbe_hw *hw;
1371
1372         PMD_INIT_FUNC_TRACE();
1373
1374         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1375                 return -EPERM;
1376
1377         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1378
1379         if (hw->adapter_stopped == 0)
1380                 ixgbe_dev_close(eth_dev);
1381
1382         eth_dev->dev_ops = NULL;
1383         eth_dev->rx_pkt_burst = NULL;
1384         eth_dev->tx_pkt_burst = NULL;
1385
1386         /* Unlock any pending hardware semaphore */
1387         ixgbe_swfw_lock_reset(hw);
1388
1389         /* disable uio intr before callback unregister */
1390         rte_intr_disable(intr_handle);
1391         rte_intr_callback_unregister(intr_handle,
1392                                      ixgbe_dev_interrupt_handler, eth_dev);
1393
1394         /* uninitialize PF if max_vfs not zero */
1395         ixgbe_pf_host_uninit(eth_dev);
1396
1397         rte_free(eth_dev->data->mac_addrs);
1398         eth_dev->data->mac_addrs = NULL;
1399
1400         rte_free(eth_dev->data->hash_mac_addrs);
1401         eth_dev->data->hash_mac_addrs = NULL;
1402
1403         /* remove all the fdir filters & hash */
1404         ixgbe_fdir_filter_uninit(eth_dev);
1405
1406         /* remove all the L2 tunnel filters & hash */
1407         ixgbe_l2_tn_filter_uninit(eth_dev);
1408
1409         /* Remove all ntuple filters of the device */
1410         ixgbe_ntuple_filter_uninit(eth_dev);
1411
1412         /* clear all the filters list */
1413         ixgbe_filterlist_flush();
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_filter_info *filter_info =
1421                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1422         struct ixgbe_5tuple_filter *p_5tuple;
1423
1424         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1425                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1426                              p_5tuple,
1427                              entries);
1428                 rte_free(p_5tuple);
1429         }
1430         memset(filter_info->fivetuple_mask, 0,
1431                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_hw_fdir_info *fdir_info =
1439                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1440         struct ixgbe_fdir_filter *fdir_filter;
1441
1442                 if (fdir_info->hash_map)
1443                 rte_free(fdir_info->hash_map);
1444         if (fdir_info->hash_handle)
1445                 rte_hash_free(fdir_info->hash_handle);
1446
1447         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1448                 TAILQ_REMOVE(&fdir_info->fdir_list,
1449                              fdir_filter,
1450                              entries);
1451                 rte_free(fdir_filter);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         struct ixgbe_l2_tn_filter *l2_tn_filter;
1462
1463         if (l2_tn_info->hash_map)
1464                 rte_free(l2_tn_info->hash_map);
1465         if (l2_tn_info->hash_handle)
1466                 rte_hash_free(l2_tn_info->hash_handle);
1467
1468         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1469                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1470                              l2_tn_filter,
1471                              entries);
1472                 rte_free(l2_tn_filter);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1479 {
1480         struct ixgbe_hw_fdir_info *fdir_info =
1481                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1482         char fdir_hash_name[RTE_HASH_NAMESIZE];
1483         struct rte_hash_parameters fdir_hash_params = {
1484                 .name = fdir_hash_name,
1485                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1486                 .key_len = sizeof(union ixgbe_atr_input),
1487                 .hash_func = rte_hash_crc,
1488                 .hash_func_init_val = 0,
1489                 .socket_id = rte_socket_id(),
1490         };
1491
1492         TAILQ_INIT(&fdir_info->fdir_list);
1493         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1494                  "fdir_%s", eth_dev->data->name);
1495         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1496         if (!fdir_info->hash_handle) {
1497                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1498                 return -EINVAL;
1499         }
1500         fdir_info->hash_map = rte_zmalloc("ixgbe",
1501                                           sizeof(struct ixgbe_fdir_filter *) *
1502                                           IXGBE_MAX_FDIR_FILTER_NUM,
1503                                           0);
1504         if (!fdir_info->hash_map) {
1505                 PMD_INIT_LOG(ERR,
1506                              "Failed to allocate memory for fdir hash map!");
1507                 return -ENOMEM;
1508         }
1509         fdir_info->mask_added = FALSE;
1510
1511         return 0;
1512 }
1513
1514 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1515 {
1516         struct ixgbe_l2_tn_info *l2_tn_info =
1517                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1518         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1519         struct rte_hash_parameters l2_tn_hash_params = {
1520                 .name = l2_tn_hash_name,
1521                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1522                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1523                 .hash_func = rte_hash_crc,
1524                 .hash_func_init_val = 0,
1525                 .socket_id = rte_socket_id(),
1526         };
1527
1528         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1529         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1530                  "l2_tn_%s", eth_dev->data->name);
1531         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1532         if (!l2_tn_info->hash_handle) {
1533                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1534                 return -EINVAL;
1535         }
1536         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1537                                    sizeof(struct ixgbe_l2_tn_filter *) *
1538                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1539                                    0);
1540         if (!l2_tn_info->hash_map) {
1541                 PMD_INIT_LOG(ERR,
1542                         "Failed to allocate memory for L2 TN hash map!");
1543                 return -ENOMEM;
1544         }
1545         l2_tn_info->e_tag_en = FALSE;
1546         l2_tn_info->e_tag_fwd_en = FALSE;
1547         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1548
1549         return 0;
1550 }
1551 /*
1552  * Negotiate mailbox API version with the PF.
1553  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1554  * Then we try to negotiate starting with the most recent one.
1555  * If all negotiation attempts fail, then we will proceed with
1556  * the default one (ixgbe_mbox_api_10).
1557  */
1558 static void
1559 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1560 {
1561         int32_t i;
1562
1563         /* start with highest supported, proceed down */
1564         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1565                 ixgbe_mbox_api_12,
1566                 ixgbe_mbox_api_11,
1567                 ixgbe_mbox_api_10,
1568         };
1569
1570         for (i = 0;
1571                         i != RTE_DIM(sup_ver) &&
1572                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1573                         i++)
1574                 ;
1575 }
1576
1577 static void
1578 generate_random_mac_addr(struct ether_addr *mac_addr)
1579 {
1580         uint64_t random;
1581
1582         /* Set Organizationally Unique Identifier (OUI) prefix. */
1583         mac_addr->addr_bytes[0] = 0x00;
1584         mac_addr->addr_bytes[1] = 0x09;
1585         mac_addr->addr_bytes[2] = 0xC0;
1586         /* Force indication of locally assigned MAC address. */
1587         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1588         /* Generate the last 3 bytes of the MAC address with a random number. */
1589         random = rte_rand();
1590         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1591 }
1592
1593 /*
1594  * Virtual Function device init
1595  */
1596 static int
1597 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1598 {
1599         int diag;
1600         uint32_t tc, tcs;
1601         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603         struct ixgbe_hw *hw =
1604                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1605         struct ixgbe_vfta *shadow_vfta =
1606                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1607         struct ixgbe_hwstrip *hwstrip =
1608                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1609         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1614         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1615         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1616
1617         /* for secondary processes, we don't initialise any further as primary
1618          * has already done this work. Only check we don't need a different
1619          * RX function
1620          */
1621         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1622                 struct ixgbe_tx_queue *txq;
1623                 /* TX queue function in primary, set by last queue initialized
1624                  * Tx queue may not initialized by primary process
1625                  */
1626                 if (eth_dev->data->tx_queues) {
1627                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1628                         ixgbe_set_tx_function(eth_dev, txq);
1629                 } else {
1630                         /* Use default TX function if we get here */
1631                         PMD_INIT_LOG(NOTICE,
1632                                      "No TX queues configured yet. Using default TX function.");
1633                 }
1634
1635                 ixgbe_set_rx_function(eth_dev);
1636
1637                 return 0;
1638         }
1639
1640         rte_eth_copy_pci_info(eth_dev, pci_dev);
1641         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1642
1643         hw->device_id = pci_dev->id.device_id;
1644         hw->vendor_id = pci_dev->id.vendor_id;
1645         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1646
1647         /* initialize the vfta */
1648         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1649
1650         /* initialize the hw strip bitmap*/
1651         memset(hwstrip, 0, sizeof(*hwstrip));
1652
1653         /* Initialize the shared code (base driver) */
1654         diag = ixgbe_init_shared_code(hw);
1655         if (diag != IXGBE_SUCCESS) {
1656                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1657                 return -EIO;
1658         }
1659
1660         /* init_mailbox_params */
1661         hw->mbx.ops.init_params(hw);
1662
1663         /* Reset the hw statistics */
1664         ixgbevf_dev_stats_reset(eth_dev);
1665
1666         /* Disable the interrupts for VF */
1667         ixgbevf_intr_disable(hw);
1668
1669         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1670         diag = hw->mac.ops.reset_hw(hw);
1671
1672         /*
1673          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1674          * the underlying PF driver has not assigned a MAC address to the VF.
1675          * In this case, assign a random MAC address.
1676          */
1677         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1678                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1679                 return diag;
1680         }
1681
1682         /* negotiate mailbox API version to use with the PF. */
1683         ixgbevf_negotiate_api(hw);
1684
1685         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1686         ixgbevf_get_queues(hw, &tcs, &tc);
1687
1688         /* Allocate memory for storing MAC addresses */
1689         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1690                                                hw->mac.num_rar_entries, 0);
1691         if (eth_dev->data->mac_addrs == NULL) {
1692                 PMD_INIT_LOG(ERR,
1693                              "Failed to allocate %u bytes needed to store "
1694                              "MAC addresses",
1695                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1696                 return -ENOMEM;
1697         }
1698
1699         /* Generate a random MAC address, if none was assigned by PF. */
1700         if (is_zero_ether_addr(perm_addr)) {
1701                 generate_random_mac_addr(perm_addr);
1702                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1703                 if (diag) {
1704                         rte_free(eth_dev->data->mac_addrs);
1705                         eth_dev->data->mac_addrs = NULL;
1706                         return diag;
1707                 }
1708                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1709                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1710                              "%02x:%02x:%02x:%02x:%02x:%02x",
1711                              perm_addr->addr_bytes[0],
1712                              perm_addr->addr_bytes[1],
1713                              perm_addr->addr_bytes[2],
1714                              perm_addr->addr_bytes[3],
1715                              perm_addr->addr_bytes[4],
1716                              perm_addr->addr_bytes[5]);
1717         }
1718
1719         /* Copy the permanent MAC address */
1720         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1721
1722         /* reset the hardware with the new settings */
1723         diag = hw->mac.ops.start_hw(hw);
1724         switch (diag) {
1725         case  0:
1726                 break;
1727
1728         default:
1729                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1730                 return -EIO;
1731         }
1732
1733         rte_intr_callback_register(intr_handle,
1734                                    ixgbevf_dev_interrupt_handler, eth_dev);
1735         rte_intr_enable(intr_handle);
1736         ixgbevf_intr_enable(hw);
1737
1738         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1739                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1740                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1741
1742         return 0;
1743 }
1744
1745 /* Virtual Function device uninit */
1746
1747 static int
1748 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1749 {
1750         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1751         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752         struct ixgbe_hw *hw;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1757                 return -EPERM;
1758
1759         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1760
1761         if (hw->adapter_stopped == 0)
1762                 ixgbevf_dev_close(eth_dev);
1763
1764         eth_dev->dev_ops = NULL;
1765         eth_dev->rx_pkt_burst = NULL;
1766         eth_dev->tx_pkt_burst = NULL;
1767
1768         /* Disable the interrupts for VF */
1769         ixgbevf_intr_disable(hw);
1770
1771         rte_free(eth_dev->data->mac_addrs);
1772         eth_dev->data->mac_addrs = NULL;
1773
1774         rte_intr_disable(intr_handle);
1775         rte_intr_callback_unregister(intr_handle,
1776                                      ixgbevf_dev_interrupt_handler, eth_dev);
1777
1778         return 0;
1779 }
1780
1781 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1782         struct rte_pci_device *pci_dev)
1783 {
1784         return rte_eth_dev_pci_generic_probe(pci_dev,
1785                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1786 }
1787
1788 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1789 {
1790         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1791 }
1792
1793 static struct rte_pci_driver rte_ixgbe_pmd = {
1794         .id_table = pci_id_ixgbe_map,
1795         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1796         .probe = eth_ixgbe_pci_probe,
1797         .remove = eth_ixgbe_pci_remove,
1798 };
1799
1800 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1801         struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_probe(pci_dev,
1804                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1805 }
1806
1807 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1808 {
1809         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1810 }
1811
1812 /*
1813  * virtual function driver struct
1814  */
1815 static struct rte_pci_driver rte_ixgbevf_pmd = {
1816         .id_table = pci_id_ixgbevf_map,
1817         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1818         .probe = eth_ixgbevf_pci_probe,
1819         .remove = eth_ixgbevf_pci_remove,
1820 };
1821
1822 static int
1823 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1824 {
1825         struct ixgbe_hw *hw =
1826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct ixgbe_vfta *shadow_vfta =
1828                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1829         uint32_t vfta;
1830         uint32_t vid_idx;
1831         uint32_t vid_bit;
1832
1833         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1834         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1835         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1836         if (on)
1837                 vfta |= vid_bit;
1838         else
1839                 vfta &= ~vid_bit;
1840         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1841
1842         /* update local VFTA copy */
1843         shadow_vfta->vfta[vid_idx] = vfta;
1844
1845         return 0;
1846 }
1847
1848 static void
1849 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1850 {
1851         if (on)
1852                 ixgbe_vlan_hw_strip_enable(dev, queue);
1853         else
1854                 ixgbe_vlan_hw_strip_disable(dev, queue);
1855 }
1856
1857 static int
1858 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1859                     enum rte_vlan_type vlan_type,
1860                     uint16_t tpid)
1861 {
1862         struct ixgbe_hw *hw =
1863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         int ret = 0;
1865         uint32_t reg;
1866         uint32_t qinq;
1867
1868         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869         qinq &= IXGBE_DMATXCTL_GDV;
1870
1871         switch (vlan_type) {
1872         case ETH_VLAN_TYPE_INNER:
1873                 if (qinq) {
1874                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1875                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1876                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1877                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1879                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1880                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881                 } else {
1882                         ret = -ENOTSUP;
1883                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1884                                     " by single VLAN");
1885                 }
1886                 break;
1887         case ETH_VLAN_TYPE_OUTER:
1888                 if (qinq) {
1889                         /* Only the high 16-bits is valid */
1890                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1891                                         IXGBE_EXVET_VET_EXT_SHIFT);
1892                 } else {
1893                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1894                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1895                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1896                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1898                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1899                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1900                 }
1901
1902                 break;
1903         default:
1904                 ret = -EINVAL;
1905                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1906                 break;
1907         }
1908
1909         return ret;
1910 }
1911
1912 void
1913 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1914 {
1915         struct ixgbe_hw *hw =
1916                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         uint32_t vlnctrl;
1918
1919         PMD_INIT_FUNC_TRACE();
1920
1921         /* Filter Table Disable */
1922         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1923         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1924
1925         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1926 }
1927
1928 void
1929 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1930 {
1931         struct ixgbe_hw *hw =
1932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct ixgbe_vfta *shadow_vfta =
1934                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936         uint16_t i;
1937
1938         PMD_INIT_FUNC_TRACE();
1939
1940         /* Filter Table Enable */
1941         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1943         vlnctrl |= IXGBE_VLNCTRL_VFE;
1944
1945         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1946
1947         /* write whatever is in local vfta copy */
1948         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1949                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1950 }
1951
1952 static void
1953 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1954 {
1955         struct ixgbe_hwstrip *hwstrip =
1956                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1957         struct ixgbe_rx_queue *rxq;
1958
1959         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1960                 return;
1961
1962         if (on)
1963                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1964         else
1965                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1966
1967         if (queue >= dev->data->nb_rx_queues)
1968                 return;
1969
1970         rxq = dev->data->rx_queues[queue];
1971
1972         if (on)
1973                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1974         else
1975                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level support */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl &= ~IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2000 }
2001
2002 static void
2003 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 /* No queue level supported */
2013                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014                 return;
2015         }
2016
2017         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019         ctrl |= IXGBE_RXDCTL_VME;
2020         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021
2022         /* record those setting for HW strip per queue */
2023         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2024 }
2025
2026 void
2027 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t ctrl;
2032         uint16_t i;
2033         struct ixgbe_rx_queue *rxq;
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         if (hw->mac.type == ixgbe_mac_82598EB) {
2038                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2039                 ctrl &= ~IXGBE_VLNCTRL_VME;
2040                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2041         } else {
2042                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2044                         rxq = dev->data->rx_queues[i];
2045                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2046                         ctrl &= ~IXGBE_RXDCTL_VME;
2047                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2048
2049                         /* record those setting for HW strip per queue */
2050                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2051                 }
2052         }
2053 }
2054
2055 void
2056 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061         uint16_t i;
2062         struct ixgbe_rx_queue *rxq;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         if (hw->mac.type == ixgbe_mac_82598EB) {
2067                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2068                 ctrl |= IXGBE_VLNCTRL_VME;
2069                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2070         } else {
2071                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2072                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2073                         rxq = dev->data->rx_queues[i];
2074                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2075                         ctrl |= IXGBE_RXDCTL_VME;
2076                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2077
2078                         /* record those setting for HW strip per queue */
2079                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2080                 }
2081         }
2082 }
2083
2084 static void
2085 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw =
2088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t ctrl;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         /* DMATXCTRL: Geric Double VLAN Disable */
2094         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095         ctrl &= ~IXGBE_DMATXCTL_GDV;
2096         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097
2098         /* CTRL_EXT: Global Double VLAN Disable */
2099         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100         ctrl &= ~IXGBE_EXTENDED_VLAN;
2101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102
2103 }
2104
2105 static void
2106 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         uint32_t ctrl;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         /* DMATXCTRL: Geric Double VLAN Enable */
2115         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2116         ctrl |= IXGBE_DMATXCTL_GDV;
2117         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2118
2119         /* CTRL_EXT: Global Double VLAN Enable */
2120         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2121         ctrl |= IXGBE_EXTENDED_VLAN;
2122         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2123
2124         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2125         if (hw->mac.type == ixgbe_mac_X550 ||
2126             hw->mac.type == ixgbe_mac_X550EM_x ||
2127             hw->mac.type == ixgbe_mac_X550EM_a) {
2128                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2129                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2130                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2131         }
2132
2133         /*
2134          * VET EXT field in the EXVET register = 0x8100 by default
2135          * So no need to change. Same to VT field of DMATXCTL register
2136          */
2137 }
2138
2139 static void
2140 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2141 {
2142         if (mask & ETH_VLAN_STRIP_MASK) {
2143                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2144                         ixgbe_vlan_hw_strip_enable_all(dev);
2145                 else
2146                         ixgbe_vlan_hw_strip_disable_all(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_FILTER_MASK) {
2150                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2151                         ixgbe_vlan_hw_filter_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_filter_disable(dev);
2154         }
2155
2156         if (mask & ETH_VLAN_EXTEND_MASK) {
2157                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2158                         ixgbe_vlan_hw_extend_enable(dev);
2159                 else
2160                         ixgbe_vlan_hw_extend_disable(dev);
2161         }
2162 }
2163
2164 static void
2165 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2170         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2171
2172         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2173         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2174 }
2175
2176 static int
2177 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2178 {
2179         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2180
2181         switch (nb_rx_q) {
2182         case 1:
2183         case 2:
2184                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185                 break;
2186         case 4:
2187                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2188                 break;
2189         default:
2190                 return -EINVAL;
2191         }
2192
2193         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2194         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2195
2196         return 0;
2197 }
2198
2199 static int
2200 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2201 {
2202         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2205         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2206
2207         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2208                 /* check multi-queue mode */
2209                 switch (dev_conf->rxmode.mq_mode) {
2210                 case ETH_MQ_RX_VMDQ_DCB:
2211                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2212                         break;
2213                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2214                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2215                         PMD_INIT_LOG(ERR, "SRIOV active,"
2216                                         " unsupported mq_mode rx %d.",
2217                                         dev_conf->rxmode.mq_mode);
2218                         return -EINVAL;
2219                 case ETH_MQ_RX_RSS:
2220                 case ETH_MQ_RX_VMDQ_RSS:
2221                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2222                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2223                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2224                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2225                                                 " invalid queue number"
2226                                                 " for VMDQ RSS, allowed"
2227                                                 " value are 1, 2 or 4.");
2228                                         return -EINVAL;
2229                                 }
2230                         break;
2231                 case ETH_MQ_RX_VMDQ_ONLY:
2232                 case ETH_MQ_RX_NONE:
2233                         /* if nothing mq mode configure, use default scheme */
2234                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2235                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2236                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2237                         break;
2238                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2239                         /* SRIOV only works in VMDq enable mode */
2240                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2241                                         " wrong mq_mode rx %d.",
2242                                         dev_conf->rxmode.mq_mode);
2243                         return -EINVAL;
2244                 }
2245
2246                 switch (dev_conf->txmode.mq_mode) {
2247                 case ETH_MQ_TX_VMDQ_DCB:
2248                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2249                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2250                         break;
2251                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2252                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2253                         break;
2254                 }
2255
2256                 /* check valid queue number */
2257                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2258                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2259                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2261                                         " must be less than or equal to %d.",
2262                                         nb_rx_q, nb_tx_q,
2263                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2264                         return -EINVAL;
2265                 }
2266         } else {
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2268                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2269                                           " not supported.");
2270                         return -EINVAL;
2271                 }
2272                 /* check configuration for vmdb+dcb mode */
2273                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2274                         const struct rte_eth_vmdq_dcb_conf *conf;
2275
2276                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2277                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2278                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2279                                 return -EINVAL;
2280                         }
2281                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2282                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2283                                conf->nb_queue_pools == ETH_32_POOLS)) {
2284                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2285                                                 " nb_queue_pools must be %d or %d.",
2286                                                 ETH_16_POOLS, ETH_32_POOLS);
2287                                 return -EINVAL;
2288                         }
2289                 }
2290                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2291                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2292
2293                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2294                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2295                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2296                                 return -EINVAL;
2297                         }
2298                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2299                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2300                                conf->nb_queue_pools == ETH_32_POOLS)) {
2301                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2302                                                 " nb_queue_pools != %d and"
2303                                                 " nb_queue_pools != %d.",
2304                                                 ETH_16_POOLS, ETH_32_POOLS);
2305                                 return -EINVAL;
2306                         }
2307                 }
2308
2309                 /* For DCB mode check our configuration before we go further */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2311                         const struct rte_eth_dcb_rx_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2315                                                  IXGBE_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2319                         if (!(conf->nb_tcs == ETH_4_TCS ||
2320                                conf->nb_tcs == ETH_8_TCS)) {
2321                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2322                                                 " and nb_tcs != %d.",
2323                                                 ETH_4_TCS, ETH_8_TCS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2329                         const struct rte_eth_dcb_tx_conf *conf;
2330
2331                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2333                                                  IXGBE_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2337                         if (!(conf->nb_tcs == ETH_4_TCS ||
2338                                conf->nb_tcs == ETH_8_TCS)) {
2339                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2340                                                 " and nb_tcs != %d.",
2341                                                 ETH_4_TCS, ETH_8_TCS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /*
2347                  * When DCB/VT is off, maximum number of queues changes,
2348                  * except for 82598EB, which remains constant.
2349                  */
2350                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2351                                 hw->mac.type != ixgbe_mac_82598EB) {
2352                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2353                                 PMD_INIT_LOG(ERR,
2354                                              "Neither VT nor DCB are enabled, "
2355                                              "nb_tx_q > %d.",
2356                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2357                                 return -EINVAL;
2358                         }
2359                 }
2360         }
2361         return 0;
2362 }
2363
2364 static int
2365 ixgbe_dev_configure(struct rte_eth_dev *dev)
2366 {
2367         struct ixgbe_interrupt *intr =
2368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369         struct ixgbe_adapter *adapter =
2370                 (struct ixgbe_adapter *)dev->data->dev_private;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374         /* multipe queue mode checking */
2375         ret  = ixgbe_check_mq_mode(dev);
2376         if (ret != 0) {
2377                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378                             ret);
2379                 return ret;
2380         }
2381
2382         /* set flag to update link status after init */
2383         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384
2385         /*
2386          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2387          * allocation or vector Rx preconditions we will reset it.
2388          */
2389         adapter->rx_bulk_alloc_allowed = true;
2390         adapter->rx_vec_allowed = true;
2391
2392         return 0;
2393 }
2394
2395 static void
2396 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2397 {
2398         struct ixgbe_hw *hw =
2399                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         struct ixgbe_interrupt *intr =
2401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402         uint32_t gpie;
2403
2404         /* only set up it on X550EM_X */
2405         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2406                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2407                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2408                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2409                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2410                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2411         }
2412 }
2413
2414 int
2415 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2416                         uint16_t tx_rate, uint64_t q_msk)
2417 {
2418         struct ixgbe_hw *hw;
2419         struct ixgbe_vf_info *vfinfo;
2420         struct rte_eth_link link;
2421         uint8_t  nb_q_per_pool;
2422         uint32_t queue_stride;
2423         uint32_t queue_idx, idx = 0, vf_idx;
2424         uint32_t queue_end;
2425         uint16_t total_rate = 0;
2426         struct rte_pci_device *pci_dev;
2427
2428         pci_dev = IXGBE_DEV_TO_PCI(dev);
2429         rte_eth_link_get_nowait(dev->data->port_id, &link);
2430
2431         if (vf >= pci_dev->max_vfs)
2432                 return -EINVAL;
2433
2434         if (tx_rate > link.link_speed)
2435                 return -EINVAL;
2436
2437         if (q_msk == 0)
2438                 return 0;
2439
2440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2442         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2443         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2444         queue_idx = vf * queue_stride;
2445         queue_end = queue_idx + nb_q_per_pool - 1;
2446         if (queue_end >= hw->mac.max_tx_queues)
2447                 return -EINVAL;
2448
2449         if (vfinfo) {
2450                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451                         if (vf_idx == vf)
2452                                 continue;
2453                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2454                                 idx++)
2455                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2456                 }
2457         } else {
2458                 return -EINVAL;
2459         }
2460
2461         /* Store tx_rate for this vf. */
2462         for (idx = 0; idx < nb_q_per_pool; idx++) {
2463                 if (((uint64_t)0x1 << idx) & q_msk) {
2464                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2465                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2466                         total_rate += tx_rate;
2467                 }
2468         }
2469
2470         if (total_rate > dev->data->dev_link.link_speed) {
2471                 /* Reset stored TX rate of the VF if it causes exceed
2472                  * link speed.
2473                  */
2474                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2475                 return -EINVAL;
2476         }
2477
2478         /* Set RTTBCNRC of each queue/pool for vf X  */
2479         for (; queue_idx <= queue_end; queue_idx++) {
2480                 if (0x1 & q_msk)
2481                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2482                 q_msk = q_msk >> 1;
2483         }
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Configure device link speed and setup link.
2490  * It returns 0 on success.
2491  */
2492 static int
2493 ixgbe_dev_start(struct rte_eth_dev *dev)
2494 {
2495         struct ixgbe_hw *hw =
2496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         struct ixgbe_vf_info *vfinfo =
2498                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2499         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2500         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2501         uint32_t intr_vector = 0;
2502         int err, link_up = 0, negotiate = 0;
2503         uint32_t speed = 0;
2504         int mask = 0;
2505         int status;
2506         uint16_t vf, idx;
2507         uint32_t *link_speeds;
2508
2509         PMD_INIT_FUNC_TRACE();
2510
2511         /* IXGBE devices don't support:
2512         *    - half duplex (checked afterwards for valid speeds)
2513         *    - fixed speed: TODO implement
2514         */
2515         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2517                              dev->data->port_id);
2518                 return -EINVAL;
2519         }
2520
2521         /* disable uio/vfio intr/eventfd mapping */
2522         rte_intr_disable(intr_handle);
2523
2524         /* stop adapter */
2525         hw->adapter_stopped = 0;
2526         ixgbe_stop_adapter(hw);
2527
2528         /* reinitialize adapter
2529          * this calls reset and start
2530          */
2531         status = ixgbe_pf_reset_hw(hw);
2532         if (status != 0)
2533                 return -1;
2534         hw->mac.ops.start_hw(hw);
2535         hw->mac.get_link_status = true;
2536
2537         /* configure PF module if SRIOV enabled */
2538         ixgbe_pf_host_configure(dev);
2539
2540         ixgbe_dev_phy_intr_setup(dev);
2541
2542         /* check and configure queue intr-vector mapping */
2543         if ((rte_intr_cap_multiple(intr_handle) ||
2544              !RTE_ETH_DEV_SRIOV(dev).active) &&
2545             dev->data->dev_conf.intr_conf.rxq != 0) {
2546                 intr_vector = dev->data->nb_rx_queues;
2547                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2548                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2549                                         IXGBE_MAX_INTR_QUEUE_NUM);
2550                         return -ENOTSUP;
2551                 }
2552                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2553                         return -1;
2554         }
2555
2556         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2557                 intr_handle->intr_vec =
2558                         rte_zmalloc("intr_vec",
2559                                     dev->data->nb_rx_queues * sizeof(int), 0);
2560                 if (intr_handle->intr_vec == NULL) {
2561                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2562                                      " intr_vec", dev->data->nb_rx_queues);
2563                         return -ENOMEM;
2564                 }
2565         }
2566
2567         /* confiugre msix for sleep until rx interrupt */
2568         ixgbe_configure_msix(dev);
2569
2570         /* initialize transmission unit */
2571         ixgbe_dev_tx_init(dev);
2572
2573         /* This can fail when allocating mbufs for descriptor rings */
2574         err = ixgbe_dev_rx_init(dev);
2575         if (err) {
2576                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2577                 goto error;
2578         }
2579
2580     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2581                 ETH_VLAN_EXTEND_MASK;
2582         ixgbe_vlan_offload_set(dev, mask);
2583
2584         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2585                 /* Enable vlan filtering for VMDq */
2586                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2587         }
2588
2589         /* Configure DCB hw */
2590         ixgbe_configure_dcb(dev);
2591
2592         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2593                 err = ixgbe_fdir_configure(dev);
2594                 if (err)
2595                         goto error;
2596         }
2597
2598         /* Restore vf rate limit */
2599         if (vfinfo != NULL) {
2600                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2601                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2602                                 if (vfinfo[vf].tx_rate[idx] != 0)
2603                                         ixgbe_set_vf_rate_limit(
2604                                                 dev, vf,
2605                                                 vfinfo[vf].tx_rate[idx],
2606                                                 1 << idx);
2607         }
2608
2609         ixgbe_restore_statistics_mapping(dev);
2610
2611         err = ixgbe_dev_rxtx_start(dev);
2612         if (err < 0) {
2613                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2614                 goto error;
2615         }
2616
2617         /* Skip link setup if loopback mode is enabled for 82599. */
2618         if (hw->mac.type == ixgbe_mac_82599EB &&
2619                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2620                 goto skip_link_setup;
2621
2622         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2623                 err = hw->mac.ops.setup_sfp(hw);
2624                 if (err)
2625                         goto error;
2626         }
2627
2628         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2629                 /* Turn on the copper */
2630                 ixgbe_set_phy_power(hw, true);
2631         } else {
2632                 /* Turn on the laser */
2633                 ixgbe_enable_tx_laser(hw);
2634         }
2635
2636         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2637         if (err)
2638                 goto error;
2639         dev->data->dev_link.link_status = link_up;
2640
2641         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2642         if (err)
2643                 goto error;
2644
2645         link_speeds = &dev->data->dev_conf.link_speeds;
2646         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2647                         ETH_LINK_SPEED_10G)) {
2648                 PMD_INIT_LOG(ERR, "Invalid link setting");
2649                 goto error;
2650         }
2651
2652         speed = 0x0;
2653         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2654                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2655                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2656                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2657         } else {
2658                 if (*link_speeds & ETH_LINK_SPEED_10G)
2659                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_1G)
2661                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662                 if (*link_speeds & ETH_LINK_SPEED_100M)
2663                         speed |= IXGBE_LINK_SPEED_100_FULL;
2664         }
2665
2666         err = ixgbe_setup_link(hw, speed, link_up);
2667         if (err)
2668                 goto error;
2669
2670 skip_link_setup:
2671
2672         if (rte_intr_allow_others(intr_handle)) {
2673                 /* check if lsc interrupt is enabled */
2674                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2676                 else
2677                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2678                 ixgbe_dev_macsec_interrupt_setup(dev);
2679         } else {
2680                 rte_intr_callback_unregister(intr_handle,
2681                                              ixgbe_dev_interrupt_handler, dev);
2682                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2683                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2684                                      " no intr multiplex");
2685         }
2686
2687         /* check if rxq interrupt is enabled */
2688         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2689             rte_intr_dp_is_en(intr_handle))
2690                 ixgbe_dev_rxq_interrupt_setup(dev);
2691
2692         /* enable uio/vfio intr/eventfd mapping */
2693         rte_intr_enable(intr_handle);
2694
2695         /* resume enabled intr since hw reset */
2696         ixgbe_enable_intr(dev);
2697         ixgbe_l2_tunnel_conf(dev);
2698         ixgbe_filter_restore(dev);
2699
2700         return 0;
2701
2702 error:
2703         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2704         ixgbe_dev_clear_queues(dev);
2705         return -EIO;
2706 }
2707
2708 /*
2709  * Stop device: disable rx and tx functions to allow for reconfiguring.
2710  */
2711 static void
2712 ixgbe_dev_stop(struct rte_eth_dev *dev)
2713 {
2714         struct rte_eth_link link;
2715         struct ixgbe_hw *hw =
2716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2717         struct ixgbe_vf_info *vfinfo =
2718                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2719         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2720         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2721         int vf;
2722
2723         PMD_INIT_FUNC_TRACE();
2724
2725         /* disable interrupts */
2726         ixgbe_disable_intr(hw);
2727
2728         /* reset the NIC */
2729         ixgbe_pf_reset_hw(hw);
2730         hw->adapter_stopped = 0;
2731
2732         /* stop adapter */
2733         ixgbe_stop_adapter(hw);
2734
2735         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2736                 vfinfo[vf].clear_to_send = false;
2737
2738         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2739                 /* Turn off the copper */
2740                 ixgbe_set_phy_power(hw, false);
2741         } else {
2742                 /* Turn off the laser */
2743                 ixgbe_disable_tx_laser(hw);
2744         }
2745
2746         ixgbe_dev_clear_queues(dev);
2747
2748         /* Clear stored conf */
2749         dev->data->scattered_rx = 0;
2750         dev->data->lro = 0;
2751
2752         /* Clear recorded link status */
2753         memset(&link, 0, sizeof(link));
2754         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2755
2756         if (!rte_intr_allow_others(intr_handle))
2757                 /* resume to the default handler */
2758                 rte_intr_callback_register(intr_handle,
2759                                            ixgbe_dev_interrupt_handler,
2760                                            (void *)dev);
2761
2762         /* Clean datapath event and queue/vec mapping */
2763         rte_intr_efd_disable(intr_handle);
2764         if (intr_handle->intr_vec != NULL) {
2765                 rte_free(intr_handle->intr_vec);
2766                 intr_handle->intr_vec = NULL;
2767         }
2768 }
2769
2770 /*
2771  * Set device link up: enable tx.
2772  */
2773 static int
2774 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2775 {
2776         struct ixgbe_hw *hw =
2777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         if (hw->mac.type == ixgbe_mac_82599EB) {
2779 #ifdef RTE_NIC_BYPASS
2780                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2781                         /* Not suported in bypass mode */
2782                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2783                                      "by device id 0x%x", hw->device_id);
2784                         return -ENOTSUP;
2785                 }
2786 #endif
2787         }
2788
2789         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2790                 /* Turn on the copper */
2791                 ixgbe_set_phy_power(hw, true);
2792         } else {
2793                 /* Turn on the laser */
2794                 ixgbe_enable_tx_laser(hw);
2795         }
2796
2797         return 0;
2798 }
2799
2800 /*
2801  * Set device link down: disable tx.
2802  */
2803 static int
2804 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2805 {
2806         struct ixgbe_hw *hw =
2807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         if (hw->mac.type == ixgbe_mac_82599EB) {
2809 #ifdef RTE_NIC_BYPASS
2810                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2811                         /* Not suported in bypass mode */
2812                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2813                                      "by device id 0x%x", hw->device_id);
2814                         return -ENOTSUP;
2815                 }
2816 #endif
2817         }
2818
2819         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2820                 /* Turn off the copper */
2821                 ixgbe_set_phy_power(hw, false);
2822         } else {
2823                 /* Turn off the laser */
2824                 ixgbe_disable_tx_laser(hw);
2825         }
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * Reest and stop device.
2832  */
2833 static void
2834 ixgbe_dev_close(struct rte_eth_dev *dev)
2835 {
2836         struct ixgbe_hw *hw =
2837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         PMD_INIT_FUNC_TRACE();
2840
2841         ixgbe_pf_reset_hw(hw);
2842
2843         ixgbe_dev_stop(dev);
2844         hw->adapter_stopped = 1;
2845
2846         ixgbe_dev_free_queues(dev);
2847
2848         ixgbe_disable_pcie_master(hw);
2849
2850         /* reprogram the RAR[0] in case user changed it. */
2851         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2852 }
2853
2854 static void
2855 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2856                            struct ixgbe_hw_stats *hw_stats,
2857                            struct ixgbe_macsec_stats *macsec_stats,
2858                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2859                            uint64_t *total_qprc, uint64_t *total_qprdc)
2860 {
2861         uint32_t bprc, lxon, lxoff, total;
2862         uint32_t delta_gprc = 0;
2863         unsigned i;
2864         /* Workaround for RX byte count not including CRC bytes when CRC
2865          * strip is enabled. CRC bytes are removed from counters when crc_strip
2866          * is disabled.
2867          */
2868         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2869                         IXGBE_HLREG0_RXCRCSTRP);
2870
2871         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2872         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2873         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2874         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2875
2876         for (i = 0; i < 8; i++) {
2877                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2878
2879                 /* global total per queue */
2880                 hw_stats->mpc[i] += mp;
2881                 /* Running comprehensive total for stats display */
2882                 *total_missed_rx += hw_stats->mpc[i];
2883                 if (hw->mac.type == ixgbe_mac_82598EB) {
2884                         hw_stats->rnbc[i] +=
2885                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2886                         hw_stats->pxonrxc[i] +=
2887                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2888                         hw_stats->pxoffrxc[i] +=
2889                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2890                 } else {
2891                         hw_stats->pxonrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2893                         hw_stats->pxoffrxc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2895                         hw_stats->pxon2offc[i] +=
2896                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2897                 }
2898                 hw_stats->pxontxc[i] +=
2899                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2900                 hw_stats->pxofftxc[i] +=
2901                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2902         }
2903         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2904                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2905                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2906                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2907
2908                 delta_gprc += delta_qprc;
2909
2910                 hw_stats->qprc[i] += delta_qprc;
2911                 hw_stats->qptc[i] += delta_qptc;
2912
2913                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2914                 hw_stats->qbrc[i] +=
2915                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2916                 if (crc_strip == 0)
2917                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2918
2919                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2920                 hw_stats->qbtc[i] +=
2921                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2922
2923                 hw_stats->qprdc[i] += delta_qprdc;
2924                 *total_qprdc += hw_stats->qprdc[i];
2925
2926                 *total_qprc += hw_stats->qprc[i];
2927                 *total_qbrc += hw_stats->qbrc[i];
2928         }
2929         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2930         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2931         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2932
2933         /*
2934          * An errata states that gprc actually counts good + missed packets:
2935          * Workaround to set gprc to summated queue packet receives
2936          */
2937         hw_stats->gprc = *total_qprc;
2938
2939         if (hw->mac.type != ixgbe_mac_82598EB) {
2940                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2941                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2942                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2943                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2944                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2945                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2946                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2947                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2948         } else {
2949                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2950                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2951                 /* 82598 only has a counter in the high register */
2952                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2953                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2954                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2955         }
2956         uint64_t old_tpr = hw_stats->tpr;
2957
2958         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2959         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2960
2961         if (crc_strip == 0)
2962                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2963
2964         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2965         hw_stats->gptc += delta_gptc;
2966         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2967         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2968
2969         /*
2970          * Workaround: mprc hardware is incorrectly counting
2971          * broadcasts, so for now we subtract those.
2972          */
2973         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2974         hw_stats->bprc += bprc;
2975         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2976         if (hw->mac.type == ixgbe_mac_82598EB)
2977                 hw_stats->mprc -= bprc;
2978
2979         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2980         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2981         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2982         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2983         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2984         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2985
2986         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2987         hw_stats->lxontxc += lxon;
2988         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2989         hw_stats->lxofftxc += lxoff;
2990         total = lxon + lxoff;
2991
2992         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2993         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2994         hw_stats->gptc -= total;
2995         hw_stats->mptc -= total;
2996         hw_stats->ptc64 -= total;
2997         hw_stats->gotc -= total * ETHER_MIN_LEN;
2998
2999         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3000         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3001         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3002         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3003         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3004         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3005         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3006         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3007         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3008         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3009         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3010         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3011         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3012         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3013         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3014         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3015         /* Only read FCOE on 82599 */
3016         if (hw->mac.type != ixgbe_mac_82598EB) {
3017                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3018                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3019                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3020                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3021                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3022         }
3023
3024         /* Flow Director Stats registers */
3025         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3026         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3027
3028         /* MACsec Stats registers */
3029         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3030         macsec_stats->out_pkts_encrypted +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3032         macsec_stats->out_pkts_protected +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3034         macsec_stats->out_octets_encrypted +=
3035                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3036         macsec_stats->out_octets_protected +=
3037                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3038         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3039         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3040         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3041         macsec_stats->in_pkts_unknownsci +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3043         macsec_stats->in_octets_decrypted +=
3044                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3045         macsec_stats->in_octets_validated +=
3046                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3047         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3048         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3049         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3050         for (i = 0; i < 2; i++) {
3051                 macsec_stats->in_pkts_ok +=
3052                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3053                 macsec_stats->in_pkts_invalid +=
3054                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3055                 macsec_stats->in_pkts_notvalid +=
3056                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3057         }
3058         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3059         macsec_stats->in_pkts_notusingsa +=
3060                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3061 }
3062
3063 /*
3064  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3065  */
3066 static void
3067 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3068 {
3069         struct ixgbe_hw *hw =
3070                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071         struct ixgbe_hw_stats *hw_stats =
3072                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3073         struct ixgbe_macsec_stats *macsec_stats =
3074                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3075                                 dev->data->dev_private);
3076         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3077         unsigned i;
3078
3079         total_missed_rx = 0;
3080         total_qbrc = 0;
3081         total_qprc = 0;
3082         total_qprdc = 0;
3083
3084         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3085                         &total_qbrc, &total_qprc, &total_qprdc);
3086
3087         if (stats == NULL)
3088                 return;
3089
3090         /* Fill out the rte_eth_stats statistics structure */
3091         stats->ipackets = total_qprc;
3092         stats->ibytes = total_qbrc;
3093         stats->opackets = hw_stats->gptc;
3094         stats->obytes = hw_stats->gotc;
3095
3096         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3097                 stats->q_ipackets[i] = hw_stats->qprc[i];
3098                 stats->q_opackets[i] = hw_stats->qptc[i];
3099                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3100                 stats->q_obytes[i] = hw_stats->qbtc[i];
3101                 stats->q_errors[i] = hw_stats->qprdc[i];
3102         }
3103
3104         /* Rx Errors */
3105         stats->imissed  = total_missed_rx;
3106         stats->ierrors  = hw_stats->crcerrs +
3107                           hw_stats->mspdc +
3108                           hw_stats->rlec +
3109                           hw_stats->ruc +
3110                           hw_stats->roc +
3111                           hw_stats->illerrc +
3112                           hw_stats->errbc +
3113                           hw_stats->rfc +
3114                           hw_stats->fccrc +
3115                           hw_stats->fclast;
3116
3117         /* Tx Errors */
3118         stats->oerrors  = 0;
3119 }
3120
3121 static void
3122 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3123 {
3124         struct ixgbe_hw_stats *stats =
3125                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3126
3127         /* HW registers are cleared on read */
3128         ixgbe_dev_stats_get(dev, NULL);
3129
3130         /* Reset software totals */
3131         memset(stats, 0, sizeof(*stats));
3132 }
3133
3134 /* This function calculates the number of xstats based on the current config */
3135 static unsigned
3136 ixgbe_xstats_calc_num(void) {
3137         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3138                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3139                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3140 }
3141
3142 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3143         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3144 {
3145         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3146         unsigned stat, i, count;
3147
3148         if (xstats_names != NULL) {
3149                 count = 0;
3150
3151                 /* Note: limit >= cnt_stats checked upstream
3152                  * in rte_eth_xstats_names()
3153                  */
3154
3155                 /* Extended stats from ixgbe_hw_stats */
3156                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3157                         snprintf(xstats_names[count].name,
3158                                 sizeof(xstats_names[count].name),
3159                                 "%s",
3160                                 rte_ixgbe_stats_strings[i].name);
3161                         count++;
3162                 }
3163
3164                 /* MACsec Stats */
3165                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3166                         snprintf(xstats_names[count].name,
3167                                 sizeof(xstats_names[count].name),
3168                                 "%s",
3169                                 rte_ixgbe_macsec_strings[i].name);
3170                         count++;
3171                 }
3172
3173                 /* RX Priority Stats */
3174                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3175                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3176                                 snprintf(xstats_names[count].name,
3177                                         sizeof(xstats_names[count].name),
3178                                         "rx_priority%u_%s", i,
3179                                         rte_ixgbe_rxq_strings[stat].name);
3180                                 count++;
3181                         }
3182                 }
3183
3184                 /* TX Priority Stats */
3185                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3186                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3187                                 snprintf(xstats_names[count].name,
3188                                         sizeof(xstats_names[count].name),
3189                                         "tx_priority%u_%s", i,
3190                                         rte_ixgbe_txq_strings[stat].name);
3191                                 count++;
3192                         }
3193                 }
3194         }
3195         return cnt_stats;
3196 }
3197
3198 static int ixgbe_dev_xstats_get_names_by_id(
3199         __rte_unused struct rte_eth_dev *dev,
3200         struct rte_eth_xstat_name *xstats_names,
3201         const uint64_t *ids,
3202         unsigned int limit)
3203 {
3204         if (!ids) {
3205                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3206                 unsigned int stat, i, count;
3207
3208                 if (xstats_names != NULL) {
3209                         count = 0;
3210
3211                         /* Note: limit >= cnt_stats checked upstream
3212                          * in rte_eth_xstats_names()
3213                          */
3214
3215                         /* Extended stats from ixgbe_hw_stats */
3216                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3217                                 snprintf(xstats_names[count].name,
3218                                         sizeof(xstats_names[count].name),
3219                                         "%s",
3220                                         rte_ixgbe_stats_strings[i].name);
3221                                 count++;
3222                         }
3223
3224                         /* MACsec Stats */
3225                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3226                                 snprintf(xstats_names[count].name,
3227                                         sizeof(xstats_names[count].name),
3228                                         "%s",
3229                                         rte_ixgbe_macsec_strings[i].name);
3230                                 count++;
3231                         }
3232
3233                         /* RX Priority Stats */
3234                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3235                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3236                                         snprintf(xstats_names[count].name,
3237                                             sizeof(xstats_names[count].name),
3238                                             "rx_priority%u_%s", i,
3239                                             rte_ixgbe_rxq_strings[stat].name);
3240                                         count++;
3241                                 }
3242                         }
3243
3244                         /* TX Priority Stats */
3245                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3246                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3247                                         snprintf(xstats_names[count].name,
3248                                             sizeof(xstats_names[count].name),
3249                                             "tx_priority%u_%s", i,
3250                                             rte_ixgbe_txq_strings[stat].name);
3251                                         count++;
3252                                 }
3253                         }
3254                 }
3255                 return cnt_stats;
3256         }
3257
3258         uint16_t i;
3259         uint16_t size = ixgbe_xstats_calc_num();
3260         struct rte_eth_xstat_name xstats_names_copy[size];
3261
3262         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3263                         size);
3264
3265         for (i = 0; i < limit; i++) {
3266                 if (ids[i] >= size) {
3267                         PMD_INIT_LOG(ERR, "id value isn't valid");
3268                         return -1;
3269                 }
3270                 strcpy(xstats_names[i].name,
3271                                 xstats_names_copy[ids[i]].name);
3272         }
3273         return limit;
3274 }
3275
3276 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3277         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3278 {
3279         unsigned i;
3280
3281         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3282                 return -ENOMEM;
3283
3284         if (xstats_names != NULL)
3285                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3286                         snprintf(xstats_names[i].name,
3287                                 sizeof(xstats_names[i].name),
3288                                 "%s", rte_ixgbevf_stats_strings[i].name);
3289         return IXGBEVF_NB_XSTATS;
3290 }
3291
3292 static int
3293 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3294                                          unsigned n)
3295 {
3296         struct ixgbe_hw *hw =
3297                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298         struct ixgbe_hw_stats *hw_stats =
3299                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3300         struct ixgbe_macsec_stats *macsec_stats =
3301                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3302                                 dev->data->dev_private);
3303         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3304         unsigned i, stat, count = 0;
3305
3306         count = ixgbe_xstats_calc_num();
3307
3308         if (n < count)
3309                 return count;
3310
3311         total_missed_rx = 0;
3312         total_qbrc = 0;
3313         total_qprc = 0;
3314         total_qprdc = 0;
3315
3316         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3317                         &total_qbrc, &total_qprc, &total_qprdc);
3318
3319         /* If this is a reset xstats is NULL, and we have cleared the
3320          * registers by reading them.
3321          */
3322         if (!xstats)
3323                 return 0;
3324
3325         /* Extended stats from ixgbe_hw_stats */
3326         count = 0;
3327         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3328                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3329                                 rte_ixgbe_stats_strings[i].offset);
3330                 xstats[count].id = count;
3331                 count++;
3332         }
3333
3334         /* MACsec Stats */
3335         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3336                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3337                                 rte_ixgbe_macsec_strings[i].offset);
3338                 xstats[count].id = count;
3339                 count++;
3340         }
3341
3342         /* RX Priority Stats */
3343         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3344                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3345                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3346                                         rte_ixgbe_rxq_strings[stat].offset +
3347                                         (sizeof(uint64_t) * i));
3348                         xstats[count].id = count;
3349                         count++;
3350                 }
3351         }
3352
3353         /* TX Priority Stats */
3354         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3355                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3356                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3357                                         rte_ixgbe_txq_strings[stat].offset +
3358                                         (sizeof(uint64_t) * i));
3359                         xstats[count].id = count;
3360                         count++;
3361                 }
3362         }
3363         return count;
3364 }
3365
3366 static int
3367 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3368                 uint64_t *values, unsigned int n)
3369 {
3370         if (!ids) {
3371                 struct ixgbe_hw *hw =
3372                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373                 struct ixgbe_hw_stats *hw_stats =
3374                                 IXGBE_DEV_PRIVATE_TO_STATS(
3375                                                 dev->data->dev_private);
3376                 struct ixgbe_macsec_stats *macsec_stats =
3377                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3378                                         dev->data->dev_private);
3379                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3380                 unsigned int i, stat, count = 0;
3381
3382                 count = ixgbe_xstats_calc_num();
3383
3384                 if (!ids && n < count)
3385                         return count;
3386
3387                 total_missed_rx = 0;
3388                 total_qbrc = 0;
3389                 total_qprc = 0;
3390                 total_qprdc = 0;
3391
3392                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3393                                 &total_missed_rx, &total_qbrc, &total_qprc,
3394                                 &total_qprdc);
3395
3396                 /* If this is a reset xstats is NULL, and we have cleared the
3397                  * registers by reading them.
3398                  */
3399                 if (!ids && !values)
3400                         return 0;
3401
3402                 /* Extended stats from ixgbe_hw_stats */
3403                 count = 0;
3404                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3405                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3406                                         rte_ixgbe_stats_strings[i].offset);
3407                         count++;
3408                 }
3409
3410                 /* MACsec Stats */
3411                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3412                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3413                                         rte_ixgbe_macsec_strings[i].offset);
3414                         count++;
3415                 }
3416
3417                 /* RX Priority Stats */
3418                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3419                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3420                                 values[count] =
3421                                         *(uint64_t *)(((char *)hw_stats) +
3422                                         rte_ixgbe_rxq_strings[stat].offset +
3423                                         (sizeof(uint64_t) * i));
3424                                 count++;
3425                         }
3426                 }
3427
3428                 /* TX Priority Stats */
3429                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3430                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3431                                 values[count] =
3432                                         *(uint64_t *)(((char *)hw_stats) +
3433                                         rte_ixgbe_txq_strings[stat].offset +
3434                                         (sizeof(uint64_t) * i));
3435                                 count++;
3436                         }
3437                 }
3438                 return count;
3439         }
3440
3441         uint16_t i;
3442         uint16_t size = ixgbe_xstats_calc_num();
3443         uint64_t values_copy[size];
3444
3445         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3446
3447         for (i = 0; i < n; i++) {
3448                 if (ids[i] >= size) {
3449                         PMD_INIT_LOG(ERR, "id value isn't valid");
3450                         return -1;
3451                 }
3452                 values[i] = values_copy[ids[i]];
3453         }
3454         return n;
3455 }
3456
3457 static void
3458 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3459 {
3460         struct ixgbe_hw_stats *stats =
3461                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3462         struct ixgbe_macsec_stats *macsec_stats =
3463                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3464                                 dev->data->dev_private);
3465
3466         unsigned count = ixgbe_xstats_calc_num();
3467
3468         /* HW registers are cleared on read */
3469         ixgbe_dev_xstats_get(dev, NULL, count);
3470
3471         /* Reset software totals */
3472         memset(stats, 0, sizeof(*stats));
3473         memset(macsec_stats, 0, sizeof(*macsec_stats));
3474 }
3475
3476 static void
3477 ixgbevf_update_stats(struct rte_eth_dev *dev)
3478 {
3479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3481                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3482
3483         /* Good Rx packet, include VF loopback */
3484         UPDATE_VF_STAT(IXGBE_VFGPRC,
3485             hw_stats->last_vfgprc, hw_stats->vfgprc);
3486
3487         /* Good Rx octets, include VF loopback */
3488         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3489             hw_stats->last_vfgorc, hw_stats->vfgorc);
3490
3491         /* Good Tx packet, include VF loopback */
3492         UPDATE_VF_STAT(IXGBE_VFGPTC,
3493             hw_stats->last_vfgptc, hw_stats->vfgptc);
3494
3495         /* Good Tx octets, include VF loopback */
3496         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3497             hw_stats->last_vfgotc, hw_stats->vfgotc);
3498
3499         /* Rx Multicst Packet */
3500         UPDATE_VF_STAT(IXGBE_VFMPRC,
3501             hw_stats->last_vfmprc, hw_stats->vfmprc);
3502 }
3503
3504 static int
3505 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3506                        unsigned n)
3507 {
3508         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3509                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3510         unsigned i;
3511
3512         if (n < IXGBEVF_NB_XSTATS)
3513                 return IXGBEVF_NB_XSTATS;
3514
3515         ixgbevf_update_stats(dev);
3516
3517         if (!xstats)
3518                 return 0;
3519
3520         /* Extended stats */
3521         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3522                 xstats[i].id = i;
3523                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3524                         rte_ixgbevf_stats_strings[i].offset);
3525         }
3526
3527         return IXGBEVF_NB_XSTATS;
3528 }
3529
3530 static void
3531 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3532 {
3533         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3534                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3535
3536         ixgbevf_update_stats(dev);
3537
3538         if (stats == NULL)
3539                 return;
3540
3541         stats->ipackets = hw_stats->vfgprc;
3542         stats->ibytes = hw_stats->vfgorc;
3543         stats->opackets = hw_stats->vfgptc;
3544         stats->obytes = hw_stats->vfgotc;
3545 }
3546
3547 static void
3548 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3549 {
3550         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3551                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552
3553         /* Sync HW register to the last stats */
3554         ixgbevf_dev_stats_get(dev, NULL);
3555
3556         /* reset HW current stats*/
3557         hw_stats->vfgprc = 0;
3558         hw_stats->vfgorc = 0;
3559         hw_stats->vfgptc = 0;
3560         hw_stats->vfgotc = 0;
3561 }
3562
3563 static int
3564 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3565 {
3566         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567         u16 eeprom_verh, eeprom_verl;
3568         u32 etrack_id;
3569         int ret;
3570
3571         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3572         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3573
3574         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3575         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3576
3577         ret += 1; /* add the size of '\0' */
3578         if (fw_size < (u32)ret)
3579                 return ret;
3580         else
3581                 return 0;
3582 }
3583
3584 static void
3585 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3586 {
3587         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3590
3591         dev_info->pci_dev = pci_dev;
3592         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3593         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3594         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3595                 /*
3596                  * When DCB/VT is off, maximum number of queues changes,
3597                  * except for 82598EB, which remains constant.
3598                  */
3599                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3600                                 hw->mac.type != ixgbe_mac_82598EB)
3601                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3602         }
3603         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3604         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3605         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3606         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3607         dev_info->max_vfs = pci_dev->max_vfs;
3608         if (hw->mac.type == ixgbe_mac_82598EB)
3609                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3610         else
3611                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3612         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3613         dev_info->rx_offload_capa =
3614                 DEV_RX_OFFLOAD_VLAN_STRIP |
3615                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3616                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3617                 DEV_RX_OFFLOAD_TCP_CKSUM;
3618
3619         /*
3620          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3621          * mode.
3622          */
3623         if ((hw->mac.type == ixgbe_mac_82599EB ||
3624              hw->mac.type == ixgbe_mac_X540) &&
3625             !RTE_ETH_DEV_SRIOV(dev).active)
3626                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3627
3628         if (hw->mac.type == ixgbe_mac_82599EB ||
3629             hw->mac.type == ixgbe_mac_X540)
3630                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3631
3632         if (hw->mac.type == ixgbe_mac_X550 ||
3633             hw->mac.type == ixgbe_mac_X550EM_x ||
3634             hw->mac.type == ixgbe_mac_X550EM_a)
3635                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3636
3637         dev_info->tx_offload_capa =
3638                 DEV_TX_OFFLOAD_VLAN_INSERT |
3639                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3640                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3641                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3642                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3643                 DEV_TX_OFFLOAD_TCP_TSO;
3644
3645         if (hw->mac.type == ixgbe_mac_82599EB ||
3646             hw->mac.type == ixgbe_mac_X540)
3647                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3648
3649         if (hw->mac.type == ixgbe_mac_X550 ||
3650             hw->mac.type == ixgbe_mac_X550EM_x ||
3651             hw->mac.type == ixgbe_mac_X550EM_a)
3652                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3653
3654         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3655                 .rx_thresh = {
3656                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3657                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3658                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3659                 },
3660                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3661                 .rx_drop_en = 0,
3662         };
3663
3664         dev_info->default_txconf = (struct rte_eth_txconf) {
3665                 .tx_thresh = {
3666                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3667                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3668                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3669                 },
3670                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3671                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3672                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3673                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3674         };
3675
3676         dev_info->rx_desc_lim = rx_desc_lim;
3677         dev_info->tx_desc_lim = tx_desc_lim;
3678
3679         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3680         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3681         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3682
3683         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3684         if (hw->mac.type == ixgbe_mac_X540 ||
3685             hw->mac.type == ixgbe_mac_X540_vf ||
3686             hw->mac.type == ixgbe_mac_X550 ||
3687             hw->mac.type == ixgbe_mac_X550_vf) {
3688                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3689         }
3690 }
3691
3692 static const uint32_t *
3693 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3694 {
3695         static const uint32_t ptypes[] = {
3696                 /* For non-vec functions,
3697                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3698                  * for vec functions,
3699                  * refers to _recv_raw_pkts_vec().
3700                  */
3701                 RTE_PTYPE_L2_ETHER,
3702                 RTE_PTYPE_L3_IPV4,
3703                 RTE_PTYPE_L3_IPV4_EXT,
3704                 RTE_PTYPE_L3_IPV6,
3705                 RTE_PTYPE_L3_IPV6_EXT,
3706                 RTE_PTYPE_L4_SCTP,
3707                 RTE_PTYPE_L4_TCP,
3708                 RTE_PTYPE_L4_UDP,
3709                 RTE_PTYPE_TUNNEL_IP,
3710                 RTE_PTYPE_INNER_L3_IPV6,
3711                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3712                 RTE_PTYPE_INNER_L4_TCP,
3713                 RTE_PTYPE_INNER_L4_UDP,
3714                 RTE_PTYPE_UNKNOWN
3715         };
3716
3717         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3718             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3719             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3720             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3721                 return ptypes;
3722         return NULL;
3723 }
3724
3725 static void
3726 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3727                      struct rte_eth_dev_info *dev_info)
3728 {
3729         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3731
3732         dev_info->pci_dev = pci_dev;
3733         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3734         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3735         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3736         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3737         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3738         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3739         dev_info->max_vfs = pci_dev->max_vfs;
3740         if (hw->mac.type == ixgbe_mac_82598EB)
3741                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3742         else
3743                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3744         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3745                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3746                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3747                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3748         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3749                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3750                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3751                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3752                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3753                                 DEV_TX_OFFLOAD_TCP_TSO;
3754
3755         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3756                 .rx_thresh = {
3757                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3758                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3759                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3760                 },
3761                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3762                 .rx_drop_en = 0,
3763         };
3764
3765         dev_info->default_txconf = (struct rte_eth_txconf) {
3766                 .tx_thresh = {
3767                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3768                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3769                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3770                 },
3771                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3772                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3773                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3774                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3775         };
3776
3777         dev_info->rx_desc_lim = rx_desc_lim;
3778         dev_info->tx_desc_lim = tx_desc_lim;
3779 }
3780
3781 /* return 0 means link status changed, -1 means not changed */
3782 static int
3783 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3784 {
3785         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786         struct rte_eth_link link, old;
3787         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3788         struct ixgbe_interrupt *intr =
3789                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3790         int link_up;
3791         int diag;
3792         u32 speed = 0;
3793         bool autoneg = false;
3794
3795         link.link_status = ETH_LINK_DOWN;
3796         link.link_speed = 0;
3797         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3798         memset(&old, 0, sizeof(old));
3799         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3800
3801         hw->mac.get_link_status = true;
3802
3803         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3804                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3805                 speed = hw->phy.autoneg_advertised;
3806                 if (!speed)
3807                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3808                 ixgbe_setup_link(hw, speed, true);
3809         }
3810
3811         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3812         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3813                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3814         else
3815                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3816
3817         if (diag != 0) {
3818                 link.link_speed = ETH_SPEED_NUM_100M;
3819                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3820                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3821                 if (link.link_status == old.link_status)
3822                         return -1;
3823                 return 0;
3824         }
3825
3826         if (link_up == 0) {
3827                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3828                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3829                 if (link.link_status == old.link_status)
3830                         return -1;
3831                 return 0;
3832         }
3833         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3834         link.link_status = ETH_LINK_UP;
3835         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3836
3837         switch (link_speed) {
3838         default:
3839         case IXGBE_LINK_SPEED_UNKNOWN:
3840                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3841                 link.link_speed = ETH_SPEED_NUM_100M;
3842                 break;
3843
3844         case IXGBE_LINK_SPEED_100_FULL:
3845                 link.link_speed = ETH_SPEED_NUM_100M;
3846                 break;
3847
3848         case IXGBE_LINK_SPEED_1GB_FULL:
3849                 link.link_speed = ETH_SPEED_NUM_1G;
3850                 break;
3851
3852         case IXGBE_LINK_SPEED_10GB_FULL:
3853                 link.link_speed = ETH_SPEED_NUM_10G;
3854                 break;
3855         }
3856         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3857
3858         if (link.link_status == old.link_status)
3859                 return -1;
3860
3861         return 0;
3862 }
3863
3864 static void
3865 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3866 {
3867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868         uint32_t fctrl;
3869
3870         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3871         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3872         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3873 }
3874
3875 static void
3876 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3877 {
3878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         uint32_t fctrl;
3880
3881         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3882         fctrl &= (~IXGBE_FCTRL_UPE);
3883         if (dev->data->all_multicast == 1)
3884                 fctrl |= IXGBE_FCTRL_MPE;
3885         else
3886                 fctrl &= (~IXGBE_FCTRL_MPE);
3887         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3888 }
3889
3890 static void
3891 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3892 {
3893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894         uint32_t fctrl;
3895
3896         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3897         fctrl |= IXGBE_FCTRL_MPE;
3898         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3899 }
3900
3901 static void
3902 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3903 {
3904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         uint32_t fctrl;
3906
3907         if (dev->data->promiscuous == 1)
3908                 return; /* must remain in all_multicast mode */
3909
3910         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3911         fctrl &= (~IXGBE_FCTRL_MPE);
3912         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3913 }
3914
3915 /**
3916  * It clears the interrupt causes and enables the interrupt.
3917  * It will be called once only during nic initialized.
3918  *
3919  * @param dev
3920  *  Pointer to struct rte_eth_dev.
3921  * @param on
3922  *  Enable or Disable.
3923  *
3924  * @return
3925  *  - On success, zero.
3926  *  - On failure, a negative value.
3927  */
3928 static int
3929 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
3930 {
3931         struct ixgbe_interrupt *intr =
3932                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3933
3934         ixgbe_dev_link_status_print(dev);
3935         if (on)
3936                 intr->mask |= IXGBE_EICR_LSC;
3937         else
3938                 intr->mask &= ~IXGBE_EICR_LSC;
3939
3940         return 0;
3941 }
3942
3943 /**
3944  * It clears the interrupt causes and enables the interrupt.
3945  * It will be called once only during nic initialized.
3946  *
3947  * @param dev
3948  *  Pointer to struct rte_eth_dev.
3949  *
3950  * @return
3951  *  - On success, zero.
3952  *  - On failure, a negative value.
3953  */
3954 static int
3955 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3956 {
3957         struct ixgbe_interrupt *intr =
3958                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3959
3960         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3961
3962         return 0;
3963 }
3964
3965 /**
3966  * It clears the interrupt causes and enables the interrupt.
3967  * It will be called once only during nic initialized.
3968  *
3969  * @param dev
3970  *  Pointer to struct rte_eth_dev.
3971  *
3972  * @return
3973  *  - On success, zero.
3974  *  - On failure, a negative value.
3975  */
3976 static int
3977 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3978 {
3979         struct ixgbe_interrupt *intr =
3980                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3981
3982         intr->mask |= IXGBE_EICR_LINKSEC;
3983
3984         return 0;
3985 }
3986
3987 /*
3988  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3989  *
3990  * @param dev
3991  *  Pointer to struct rte_eth_dev.
3992  *
3993  * @return
3994  *  - On success, zero.
3995  *  - On failure, a negative value.
3996  */
3997 static int
3998 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3999 {
4000         uint32_t eicr;
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002         struct ixgbe_interrupt *intr =
4003                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4004
4005         /* clear all cause mask */
4006         ixgbe_disable_intr(hw);
4007
4008         /* read-on-clear nic registers here */
4009         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4010         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4011
4012         intr->flags = 0;
4013
4014         /* set flag for async link update */
4015         if (eicr & IXGBE_EICR_LSC)
4016                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4017
4018         if (eicr & IXGBE_EICR_MAILBOX)
4019                 intr->flags |= IXGBE_FLAG_MAILBOX;
4020
4021         if (eicr & IXGBE_EICR_LINKSEC)
4022                 intr->flags |= IXGBE_FLAG_MACSEC;
4023
4024         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4025             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4026             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4027                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4028
4029         return 0;
4030 }
4031
4032 /**
4033  * It gets and then prints the link status.
4034  *
4035  * @param dev
4036  *  Pointer to struct rte_eth_dev.
4037  *
4038  * @return
4039  *  - On success, zero.
4040  *  - On failure, a negative value.
4041  */
4042 static void
4043 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4044 {
4045         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4046         struct rte_eth_link link;
4047
4048         memset(&link, 0, sizeof(link));
4049         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4050         if (link.link_status) {
4051                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4052                                         (int)(dev->data->port_id),
4053                                         (unsigned)link.link_speed,
4054                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4055                                         "full-duplex" : "half-duplex");
4056         } else {
4057                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4058                                 (int)(dev->data->port_id));
4059         }
4060         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4061                                 pci_dev->addr.domain,
4062                                 pci_dev->addr.bus,
4063                                 pci_dev->addr.devid,
4064                                 pci_dev->addr.function);
4065 }
4066
4067 /*
4068  * It executes link_update after knowing an interrupt occurred.
4069  *
4070  * @param dev
4071  *  Pointer to struct rte_eth_dev.
4072  *
4073  * @return
4074  *  - On success, zero.
4075  *  - On failure, a negative value.
4076  */
4077 static int
4078 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4079                            struct rte_intr_handle *intr_handle)
4080 {
4081         struct ixgbe_interrupt *intr =
4082                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4083         int64_t timeout;
4084         struct rte_eth_link link;
4085         struct ixgbe_hw *hw =
4086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087
4088         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4089
4090         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4091                 ixgbe_pf_mbx_process(dev);
4092                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4093         }
4094
4095         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4096                 ixgbe_handle_lasi(hw);
4097                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4098         }
4099
4100         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4101                 /* get the link status before link update, for predicting later */
4102                 memset(&link, 0, sizeof(link));
4103                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4104
4105                 ixgbe_dev_link_update(dev, 0);
4106
4107                 /* likely to up */
4108                 if (!link.link_status)
4109                         /* handle it 1 sec later, wait it being stable */
4110                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4111                 /* likely to down */
4112                 else
4113                         /* handle it 4 sec later, wait it being stable */
4114                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4115
4116                 ixgbe_dev_link_status_print(dev);
4117                 if (rte_eal_alarm_set(timeout * 1000,
4118                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4119                         PMD_DRV_LOG(ERR, "Error setting alarm");
4120                 else {
4121                         /* remember original mask */
4122                         intr->mask_original = intr->mask;
4123                         /* only disable lsc interrupt */
4124                         intr->mask &= ~IXGBE_EIMS_LSC;
4125                 }
4126         }
4127
4128         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4129         ixgbe_enable_intr(dev);
4130         rte_intr_enable(intr_handle);
4131
4132         return 0;
4133 }
4134
4135 /**
4136  * Interrupt handler which shall be registered for alarm callback for delayed
4137  * handling specific interrupt to wait for the stable nic state. As the
4138  * NIC interrupt state is not stable for ixgbe after link is just down,
4139  * it needs to wait 4 seconds to get the stable status.
4140  *
4141  * @param handle
4142  *  Pointer to interrupt handle.
4143  * @param param
4144  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4145  *
4146  * @return
4147  *  void
4148  */
4149 static void
4150 ixgbe_dev_interrupt_delayed_handler(void *param)
4151 {
4152         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4153         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4155         struct ixgbe_interrupt *intr =
4156                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4157         struct ixgbe_hw *hw =
4158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159         uint32_t eicr;
4160
4161         ixgbe_disable_intr(hw);
4162
4163         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4164         if (eicr & IXGBE_EICR_MAILBOX)
4165                 ixgbe_pf_mbx_process(dev);
4166
4167         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4168                 ixgbe_handle_lasi(hw);
4169                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4170         }
4171
4172         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4173                 ixgbe_dev_link_update(dev, 0);
4174                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4175                 ixgbe_dev_link_status_print(dev);
4176                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4177         }
4178
4179         if (intr->flags & IXGBE_FLAG_MACSEC) {
4180                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4181                                               NULL);
4182                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4183         }
4184
4185         /* restore original mask */
4186         intr->mask = intr->mask_original;
4187         intr->mask_original = 0;
4188
4189         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4190         ixgbe_enable_intr(dev);
4191         rte_intr_enable(intr_handle);
4192 }
4193
4194 /**
4195  * Interrupt handler triggered by NIC  for handling
4196  * specific interrupt.
4197  *
4198  * @param handle
4199  *  Pointer to interrupt handle.
4200  * @param param
4201  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4202  *
4203  * @return
4204  *  void
4205  */
4206 static void
4207 ixgbe_dev_interrupt_handler(void *param)
4208 {
4209         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4210
4211         ixgbe_dev_interrupt_get_status(dev);
4212         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4213 }
4214
4215 static int
4216 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4217 {
4218         struct ixgbe_hw *hw;
4219
4220         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4221         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4222 }
4223
4224 static int
4225 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4226 {
4227         struct ixgbe_hw *hw;
4228
4229         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4230         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4231 }
4232
4233 static int
4234 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4235 {
4236         struct ixgbe_hw *hw;
4237         uint32_t mflcn_reg;
4238         uint32_t fccfg_reg;
4239         int rx_pause;
4240         int tx_pause;
4241
4242         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4243
4244         fc_conf->pause_time = hw->fc.pause_time;
4245         fc_conf->high_water = hw->fc.high_water[0];
4246         fc_conf->low_water = hw->fc.low_water[0];
4247         fc_conf->send_xon = hw->fc.send_xon;
4248         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4249
4250         /*
4251          * Return rx_pause status according to actual setting of
4252          * MFLCN register.
4253          */
4254         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4255         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4256                 rx_pause = 1;
4257         else
4258                 rx_pause = 0;
4259
4260         /*
4261          * Return tx_pause status according to actual setting of
4262          * FCCFG register.
4263          */
4264         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4265         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4266                 tx_pause = 1;
4267         else
4268                 tx_pause = 0;
4269
4270         if (rx_pause && tx_pause)
4271                 fc_conf->mode = RTE_FC_FULL;
4272         else if (rx_pause)
4273                 fc_conf->mode = RTE_FC_RX_PAUSE;
4274         else if (tx_pause)
4275                 fc_conf->mode = RTE_FC_TX_PAUSE;
4276         else
4277                 fc_conf->mode = RTE_FC_NONE;
4278
4279         return 0;
4280 }
4281
4282 static int
4283 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4284 {
4285         struct ixgbe_hw *hw;
4286         int err;
4287         uint32_t rx_buf_size;
4288         uint32_t max_high_water;
4289         uint32_t mflcn;
4290         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4291                 ixgbe_fc_none,
4292                 ixgbe_fc_rx_pause,
4293                 ixgbe_fc_tx_pause,
4294                 ixgbe_fc_full
4295         };
4296
4297         PMD_INIT_FUNC_TRACE();
4298
4299         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4301         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4302
4303         /*
4304          * At least reserve one Ethernet frame for watermark
4305          * high_water/low_water in kilo bytes for ixgbe
4306          */
4307         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4308         if ((fc_conf->high_water > max_high_water) ||
4309                 (fc_conf->high_water < fc_conf->low_water)) {
4310                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4311                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4312                 return -EINVAL;
4313         }
4314
4315         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4316         hw->fc.pause_time     = fc_conf->pause_time;
4317         hw->fc.high_water[0]  = fc_conf->high_water;
4318         hw->fc.low_water[0]   = fc_conf->low_water;
4319         hw->fc.send_xon       = fc_conf->send_xon;
4320         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4321
4322         err = ixgbe_fc_enable(hw);
4323
4324         /* Not negotiated is not an error case */
4325         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4326
4327                 /* check if we want to forward MAC frames - driver doesn't have native
4328                  * capability to do that, so we'll write the registers ourselves */
4329
4330                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4331
4332                 /* set or clear MFLCN.PMCF bit depending on configuration */
4333                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4334                         mflcn |= IXGBE_MFLCN_PMCF;
4335                 else
4336                         mflcn &= ~IXGBE_MFLCN_PMCF;
4337
4338                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4339                 IXGBE_WRITE_FLUSH(hw);
4340
4341                 return 0;
4342         }
4343
4344         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4345         return -EIO;
4346 }
4347
4348 /**
4349  *  ixgbe_pfc_enable_generic - Enable flow control
4350  *  @hw: pointer to hardware structure
4351  *  @tc_num: traffic class number
4352  *  Enable flow control according to the current settings.
4353  */
4354 static int
4355 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4356 {
4357         int ret_val = 0;
4358         uint32_t mflcn_reg, fccfg_reg;
4359         uint32_t reg;
4360         uint32_t fcrtl, fcrth;
4361         uint8_t i;
4362         uint8_t nb_rx_en;
4363
4364         /* Validate the water mark configuration */
4365         if (!hw->fc.pause_time) {
4366                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4367                 goto out;
4368         }
4369
4370         /* Low water mark of zero causes XOFF floods */
4371         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4372                  /* High/Low water can not be 0 */
4373                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4374                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4375                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4376                         goto out;
4377                 }
4378
4379                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4380                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4381                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4382                         goto out;
4383                 }
4384         }
4385         /* Negotiate the fc mode to use */
4386         ixgbe_fc_autoneg(hw);
4387
4388         /* Disable any previous flow control settings */
4389         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4390         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4391
4392         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4393         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4394
4395         switch (hw->fc.current_mode) {
4396         case ixgbe_fc_none:
4397                 /*
4398                  * If the count of enabled RX Priority Flow control >1,
4399                  * and the TX pause can not be disabled
4400                  */
4401                 nb_rx_en = 0;
4402                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4403                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4404                         if (reg & IXGBE_FCRTH_FCEN)
4405                                 nb_rx_en++;
4406                 }
4407                 if (nb_rx_en > 1)
4408                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4409                 break;
4410         case ixgbe_fc_rx_pause:
4411                 /*
4412                  * Rx Flow control is enabled and Tx Flow control is
4413                  * disabled by software override. Since there really
4414                  * isn't a way to advertise that we are capable of RX
4415                  * Pause ONLY, we will advertise that we support both
4416                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4417                  * disable the adapter's ability to send PAUSE frames.
4418                  */
4419                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4420                 /*
4421                  * If the count of enabled RX Priority Flow control >1,
4422                  * and the TX pause can not be disabled
4423                  */
4424                 nb_rx_en = 0;
4425                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4426                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4427                         if (reg & IXGBE_FCRTH_FCEN)
4428                                 nb_rx_en++;
4429                 }
4430                 if (nb_rx_en > 1)
4431                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4432                 break;
4433         case ixgbe_fc_tx_pause:
4434                 /*
4435                  * Tx Flow control is enabled, and Rx Flow control is
4436                  * disabled by software override.
4437                  */
4438                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4439                 break;
4440         case ixgbe_fc_full:
4441                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4442                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4443                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4444                 break;
4445         default:
4446                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4447                 ret_val = IXGBE_ERR_CONFIG;
4448                 goto out;
4449         }
4450
4451         /* Set 802.3x based flow control settings. */
4452         mflcn_reg |= IXGBE_MFLCN_DPF;
4453         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4454         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4455
4456         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4457         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4458                 hw->fc.high_water[tc_num]) {
4459                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4460                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4461                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4462         } else {
4463                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4464                 /*
4465                  * In order to prevent Tx hangs when the internal Tx
4466                  * switch is enabled we must set the high water mark
4467                  * to the maximum FCRTH value.  This allows the Tx
4468                  * switch to function even under heavy Rx workloads.
4469                  */
4470                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4471         }
4472         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4473
4474         /* Configure pause time (2 TCs per register) */
4475         reg = hw->fc.pause_time * 0x00010001;
4476         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4477                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4478
4479         /* Configure flow control refresh threshold value */
4480         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4481
4482 out:
4483         return ret_val;
4484 }
4485
4486 static int
4487 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4488 {
4489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4491
4492         if (hw->mac.type != ixgbe_mac_82598EB) {
4493                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4494         }
4495         return ret_val;
4496 }
4497
4498 static int
4499 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4500 {
4501         int err;
4502         uint32_t rx_buf_size;
4503         uint32_t max_high_water;
4504         uint8_t tc_num;
4505         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4506         struct ixgbe_hw *hw =
4507                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         struct ixgbe_dcb_config *dcb_config =
4509                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4510
4511         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4512                 ixgbe_fc_none,
4513                 ixgbe_fc_rx_pause,
4514                 ixgbe_fc_tx_pause,
4515                 ixgbe_fc_full
4516         };
4517
4518         PMD_INIT_FUNC_TRACE();
4519
4520         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4521         tc_num = map[pfc_conf->priority];
4522         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4523         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4524         /*
4525          * At least reserve one Ethernet frame for watermark
4526          * high_water/low_water in kilo bytes for ixgbe
4527          */
4528         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4529         if ((pfc_conf->fc.high_water > max_high_water) ||
4530             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4531                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4532                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4533                 return -EINVAL;
4534         }
4535
4536         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4537         hw->fc.pause_time = pfc_conf->fc.pause_time;
4538         hw->fc.send_xon = pfc_conf->fc.send_xon;
4539         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4540         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4541
4542         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4543
4544         /* Not negotiated is not an error case */
4545         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4546                 return 0;
4547
4548         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4549         return -EIO;
4550 }
4551
4552 static int
4553 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4554                           struct rte_eth_rss_reta_entry64 *reta_conf,
4555                           uint16_t reta_size)
4556 {
4557         uint16_t i, sp_reta_size;
4558         uint8_t j, mask;
4559         uint32_t reta, r;
4560         uint16_t idx, shift;
4561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562         uint32_t reta_reg;
4563
4564         PMD_INIT_FUNC_TRACE();
4565
4566         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4567                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4568                         "NIC.");
4569                 return -ENOTSUP;
4570         }
4571
4572         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4573         if (reta_size != sp_reta_size) {
4574                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4575                         "(%d) doesn't match the number hardware can supported "
4576                         "(%d)", reta_size, sp_reta_size);
4577                 return -EINVAL;
4578         }
4579
4580         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4581                 idx = i / RTE_RETA_GROUP_SIZE;
4582                 shift = i % RTE_RETA_GROUP_SIZE;
4583                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4584                                                 IXGBE_4_BIT_MASK);
4585                 if (!mask)
4586                         continue;
4587                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4588                 if (mask == IXGBE_4_BIT_MASK)
4589                         r = 0;
4590                 else
4591                         r = IXGBE_READ_REG(hw, reta_reg);
4592                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4593                         if (mask & (0x1 << j))
4594                                 reta |= reta_conf[idx].reta[shift + j] <<
4595                                                         (CHAR_BIT * j);
4596                         else
4597                                 reta |= r & (IXGBE_8_BIT_MASK <<
4598                                                 (CHAR_BIT * j));
4599                 }
4600                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4601         }
4602
4603         return 0;
4604 }
4605
4606 static int
4607 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4608                          struct rte_eth_rss_reta_entry64 *reta_conf,
4609                          uint16_t reta_size)
4610 {
4611         uint16_t i, sp_reta_size;
4612         uint8_t j, mask;
4613         uint32_t reta;
4614         uint16_t idx, shift;
4615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         uint32_t reta_reg;
4617
4618         PMD_INIT_FUNC_TRACE();
4619         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4620         if (reta_size != sp_reta_size) {
4621                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4622                         "(%d) doesn't match the number hardware can supported "
4623                         "(%d)", reta_size, sp_reta_size);
4624                 return -EINVAL;
4625         }
4626
4627         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4628                 idx = i / RTE_RETA_GROUP_SIZE;
4629                 shift = i % RTE_RETA_GROUP_SIZE;
4630                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4631                                                 IXGBE_4_BIT_MASK);
4632                 if (!mask)
4633                         continue;
4634
4635                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4636                 reta = IXGBE_READ_REG(hw, reta_reg);
4637                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4638                         if (mask & (0x1 << j))
4639                                 reta_conf[idx].reta[shift + j] =
4640                                         ((reta >> (CHAR_BIT * j)) &
4641                                                 IXGBE_8_BIT_MASK);
4642                 }
4643         }
4644
4645         return 0;
4646 }
4647
4648 static int
4649 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4650                                 uint32_t index, uint32_t pool)
4651 {
4652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653         uint32_t enable_addr = 1;
4654
4655         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4656                              pool, enable_addr);
4657 }
4658
4659 static void
4660 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4661 {
4662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663
4664         ixgbe_clear_rar(hw, index);
4665 }
4666
4667 static void
4668 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4669 {
4670         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4671
4672         ixgbe_remove_rar(dev, 0);
4673
4674         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4675 }
4676
4677 static bool
4678 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4679 {
4680         if (strcmp(dev->data->drv_name, drv->driver.name))
4681                 return false;
4682
4683         return true;
4684 }
4685
4686 bool
4687 is_ixgbe_supported(struct rte_eth_dev *dev)
4688 {
4689         return is_device_supported(dev, &rte_ixgbe_pmd);
4690 }
4691
4692 static int
4693 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4694 {
4695         uint32_t hlreg0;
4696         uint32_t maxfrs;
4697         struct ixgbe_hw *hw;
4698         struct rte_eth_dev_info dev_info;
4699         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4700         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4701
4702         ixgbe_dev_info_get(dev, &dev_info);
4703
4704         /* check that mtu is within the allowed range */
4705         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4706                 return -EINVAL;
4707
4708         /* refuse mtu that requires the support of scattered packets when this
4709          * feature has not been enabled before.
4710          */
4711         if (!rx_conf->enable_scatter &&
4712             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4713              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4714                 return -EINVAL;
4715
4716         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4718
4719         /* switch to jumbo mode if needed */
4720         if (frame_size > ETHER_MAX_LEN) {
4721                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4722                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4723         } else {
4724                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4725                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4726         }
4727         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4728
4729         /* update max frame size */
4730         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4731
4732         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4733         maxfrs &= 0x0000FFFF;
4734         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4735         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4736
4737         return 0;
4738 }
4739
4740 /*
4741  * Virtual Function operations
4742  */
4743 static void
4744 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4745 {
4746         PMD_INIT_FUNC_TRACE();
4747
4748         /* Clear interrupt mask to stop from interrupts being generated */
4749         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4750
4751         IXGBE_WRITE_FLUSH(hw);
4752 }
4753
4754 static void
4755 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4756 {
4757         PMD_INIT_FUNC_TRACE();
4758
4759         /* VF enable interrupt autoclean */
4760         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4761         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4762         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4763
4764         IXGBE_WRITE_FLUSH(hw);
4765 }
4766
4767 static int
4768 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4769 {
4770         struct rte_eth_conf *conf = &dev->data->dev_conf;
4771         struct ixgbe_adapter *adapter =
4772                         (struct ixgbe_adapter *)dev->data->dev_private;
4773
4774         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4775                      dev->data->port_id);
4776
4777         /*
4778          * VF has no ability to enable/disable HW CRC
4779          * Keep the persistent behavior the same as Host PF
4780          */
4781 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4782         if (!conf->rxmode.hw_strip_crc) {
4783                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4784                 conf->rxmode.hw_strip_crc = 1;
4785         }
4786 #else
4787         if (conf->rxmode.hw_strip_crc) {
4788                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4789                 conf->rxmode.hw_strip_crc = 0;
4790         }
4791 #endif
4792
4793         /*
4794          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4795          * allocation or vector Rx preconditions we will reset it.
4796          */
4797         adapter->rx_bulk_alloc_allowed = true;
4798         adapter->rx_vec_allowed = true;
4799
4800         return 0;
4801 }
4802
4803 static int
4804 ixgbevf_dev_start(struct rte_eth_dev *dev)
4805 {
4806         struct ixgbe_hw *hw =
4807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4808         uint32_t intr_vector = 0;
4809         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4810         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4811
4812         int err, mask = 0;
4813
4814         PMD_INIT_FUNC_TRACE();
4815
4816         hw->mac.ops.reset_hw(hw);
4817         hw->mac.get_link_status = true;
4818
4819         /* negotiate mailbox API version to use with the PF. */
4820         ixgbevf_negotiate_api(hw);
4821
4822         ixgbevf_dev_tx_init(dev);
4823
4824         /* This can fail when allocating mbufs for descriptor rings */
4825         err = ixgbevf_dev_rx_init(dev);
4826         if (err) {
4827                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4828                 ixgbe_dev_clear_queues(dev);
4829                 return err;
4830         }
4831
4832         /* Set vfta */
4833         ixgbevf_set_vfta_all(dev, 1);
4834
4835         /* Set HW strip */
4836         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4837                 ETH_VLAN_EXTEND_MASK;
4838         ixgbevf_vlan_offload_set(dev, mask);
4839
4840         ixgbevf_dev_rxtx_start(dev);
4841
4842         /* check and configure queue intr-vector mapping */
4843         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4844                 intr_vector = dev->data->nb_rx_queues;
4845                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4846                         return -1;
4847         }
4848
4849         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4850                 intr_handle->intr_vec =
4851                         rte_zmalloc("intr_vec",
4852                                     dev->data->nb_rx_queues * sizeof(int), 0);
4853                 if (intr_handle->intr_vec == NULL) {
4854                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4855                                      " intr_vec", dev->data->nb_rx_queues);
4856                         return -ENOMEM;
4857                 }
4858         }
4859         ixgbevf_configure_msix(dev);
4860
4861         rte_intr_enable(intr_handle);
4862
4863         /* Re-enable interrupt for VF */
4864         ixgbevf_intr_enable(hw);
4865
4866         return 0;
4867 }
4868
4869 static void
4870 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4871 {
4872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4875
4876         PMD_INIT_FUNC_TRACE();
4877
4878         ixgbevf_intr_disable(hw);
4879
4880         hw->adapter_stopped = 1;
4881         ixgbe_stop_adapter(hw);
4882
4883         /*
4884           * Clear what we set, but we still keep shadow_vfta to
4885           * restore after device starts
4886           */
4887         ixgbevf_set_vfta_all(dev, 0);
4888
4889         /* Clear stored conf */
4890         dev->data->scattered_rx = 0;
4891
4892         ixgbe_dev_clear_queues(dev);
4893
4894         /* Clean datapath event and queue/vec mapping */
4895         rte_intr_efd_disable(intr_handle);
4896         if (intr_handle->intr_vec != NULL) {
4897                 rte_free(intr_handle->intr_vec);
4898                 intr_handle->intr_vec = NULL;
4899         }
4900 }
4901
4902 static void
4903 ixgbevf_dev_close(struct rte_eth_dev *dev)
4904 {
4905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906
4907         PMD_INIT_FUNC_TRACE();
4908
4909         ixgbe_reset_hw(hw);
4910
4911         ixgbevf_dev_stop(dev);
4912
4913         ixgbe_dev_free_queues(dev);
4914
4915         /**
4916          * Remove the VF MAC address ro ensure
4917          * that the VF traffic goes to the PF
4918          * after stop, close and detach of the VF
4919          **/
4920         ixgbevf_remove_mac_addr(dev, 0);
4921 }
4922
4923 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4924 {
4925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         struct ixgbe_vfta *shadow_vfta =
4927                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4928         int i = 0, j = 0, vfta = 0, mask = 1;
4929
4930         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4931                 vfta = shadow_vfta->vfta[i];
4932                 if (vfta) {
4933                         mask = 1;
4934                         for (j = 0; j < 32; j++) {
4935                                 if (vfta & mask)
4936                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4937                                                        on, false);
4938                                 mask <<= 1;
4939                         }
4940                 }
4941         }
4942
4943 }
4944
4945 static int
4946 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4947 {
4948         struct ixgbe_hw *hw =
4949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4950         struct ixgbe_vfta *shadow_vfta =
4951                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4952         uint32_t vid_idx = 0;
4953         uint32_t vid_bit = 0;
4954         int ret = 0;
4955
4956         PMD_INIT_FUNC_TRACE();
4957
4958         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4959         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4960         if (ret) {
4961                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4962                 return ret;
4963         }
4964         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4965         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4966
4967         /* Save what we set and retore it after device reset */
4968         if (on)
4969                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4970         else
4971                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4972
4973         return 0;
4974 }
4975
4976 static void
4977 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4978 {
4979         struct ixgbe_hw *hw =
4980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981         uint32_t ctrl;
4982
4983         PMD_INIT_FUNC_TRACE();
4984
4985         if (queue >= hw->mac.max_rx_queues)
4986                 return;
4987
4988         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4989         if (on)
4990                 ctrl |= IXGBE_RXDCTL_VME;
4991         else
4992                 ctrl &= ~IXGBE_RXDCTL_VME;
4993         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4994
4995         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4996 }
4997
4998 static void
4999 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5000 {
5001         struct ixgbe_hw *hw =
5002                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5003         uint16_t i;
5004         int on = 0;
5005
5006         /* VF function only support hw strip feature, others are not support */
5007         if (mask & ETH_VLAN_STRIP_MASK) {
5008                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5009
5010                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5011                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5012         }
5013 }
5014
5015 int
5016 ixgbe_vt_check(struct ixgbe_hw *hw)
5017 {
5018         uint32_t reg_val;
5019
5020         /* if Virtualization Technology is enabled */
5021         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5022         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5023                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5024                 return -1;
5025         }
5026
5027         return 0;
5028 }
5029
5030 static uint32_t
5031 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5032 {
5033         uint32_t vector = 0;
5034
5035         switch (hw->mac.mc_filter_type) {
5036         case 0:   /* use bits [47:36] of the address */
5037                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5038                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5039                 break;
5040         case 1:   /* use bits [46:35] of the address */
5041                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5042                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5043                 break;
5044         case 2:   /* use bits [45:34] of the address */
5045                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5046                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5047                 break;
5048         case 3:   /* use bits [43:32] of the address */
5049                 vector = ((uc_addr->addr_bytes[4]) |
5050                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5051                 break;
5052         default:  /* Invalid mc_filter_type */
5053                 break;
5054         }
5055
5056         /* vector can only be 12-bits or boundary will be exceeded */
5057         vector &= 0xFFF;
5058         return vector;
5059 }
5060
5061 static int
5062 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5063                         uint8_t on)
5064 {
5065         uint32_t vector;
5066         uint32_t uta_idx;
5067         uint32_t reg_val;
5068         uint32_t uta_shift;
5069         uint32_t rc;
5070         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5071         const uint32_t ixgbe_uta_bit_shift = 5;
5072         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5073         const uint32_t bit1 = 0x1;
5074
5075         struct ixgbe_hw *hw =
5076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077         struct ixgbe_uta_info *uta_info =
5078                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5079
5080         /* The UTA table only exists on 82599 hardware and newer */
5081         if (hw->mac.type < ixgbe_mac_82599EB)
5082                 return -ENOTSUP;
5083
5084         vector = ixgbe_uta_vector(hw, mac_addr);
5085         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5086         uta_shift = vector & ixgbe_uta_bit_mask;
5087
5088         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5089         if (rc == on)
5090                 return 0;
5091
5092         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5093         if (on) {
5094                 uta_info->uta_in_use++;
5095                 reg_val |= (bit1 << uta_shift);
5096                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5097         } else {
5098                 uta_info->uta_in_use--;
5099                 reg_val &= ~(bit1 << uta_shift);
5100                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5101         }
5102
5103         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5104
5105         if (uta_info->uta_in_use > 0)
5106                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5107                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5108         else
5109                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5110
5111         return 0;
5112 }
5113
5114 static int
5115 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5116 {
5117         int i;
5118         struct ixgbe_hw *hw =
5119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         struct ixgbe_uta_info *uta_info =
5121                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5122
5123         /* The UTA table only exists on 82599 hardware and newer */
5124         if (hw->mac.type < ixgbe_mac_82599EB)
5125                 return -ENOTSUP;
5126
5127         if (on) {
5128                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5129                         uta_info->uta_shadow[i] = ~0;
5130                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5131                 }
5132         } else {
5133                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5134                         uta_info->uta_shadow[i] = 0;
5135                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5136                 }
5137         }
5138         return 0;
5139
5140 }
5141
5142 uint32_t
5143 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5144 {
5145         uint32_t new_val = orig_val;
5146
5147         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5148                 new_val |= IXGBE_VMOLR_AUPE;
5149         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5150                 new_val |= IXGBE_VMOLR_ROMPE;
5151         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5152                 new_val |= IXGBE_VMOLR_ROPE;
5153         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5154                 new_val |= IXGBE_VMOLR_BAM;
5155         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5156                 new_val |= IXGBE_VMOLR_MPE;
5157
5158         return new_val;
5159 }
5160
5161 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5162 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5163 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5164 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5165 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5166         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5167         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5168
5169 static int
5170 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5171                       struct rte_eth_mirror_conf *mirror_conf,
5172                       uint8_t rule_id, uint8_t on)
5173 {
5174         uint32_t mr_ctl, vlvf;
5175         uint32_t mp_lsb = 0;
5176         uint32_t mv_msb = 0;
5177         uint32_t mv_lsb = 0;
5178         uint32_t mp_msb = 0;
5179         uint8_t i = 0;
5180         int reg_index = 0;
5181         uint64_t vlan_mask = 0;
5182
5183         const uint8_t pool_mask_offset = 32;
5184         const uint8_t vlan_mask_offset = 32;
5185         const uint8_t dst_pool_offset = 8;
5186         const uint8_t rule_mr_offset  = 4;
5187         const uint8_t mirror_rule_mask = 0x0F;
5188
5189         struct ixgbe_mirror_info *mr_info =
5190                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5191         struct ixgbe_hw *hw =
5192                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5193         uint8_t mirror_type = 0;
5194
5195         if (ixgbe_vt_check(hw) < 0)
5196                 return -ENOTSUP;
5197
5198         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5199                 return -EINVAL;
5200
5201         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5202                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5203                             mirror_conf->rule_type);
5204                 return -EINVAL;
5205         }
5206
5207         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5208                 mirror_type |= IXGBE_MRCTL_VLME;
5209                 /* Check if vlan id is valid and find conresponding VLAN ID
5210                  * index in VLVF
5211                  */
5212                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5213                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5214                                 /* search vlan id related pool vlan filter
5215                                  * index
5216                                  */
5217                                 reg_index = ixgbe_find_vlvf_slot(
5218                                                 hw,
5219                                                 mirror_conf->vlan.vlan_id[i],
5220                                                 false);
5221                                 if (reg_index < 0)
5222                                         return -EINVAL;
5223                                 vlvf = IXGBE_READ_REG(hw,
5224                                                       IXGBE_VLVF(reg_index));
5225                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5226                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5227                                       mirror_conf->vlan.vlan_id[i]))
5228                                         vlan_mask |= (1ULL << reg_index);
5229                                 else
5230                                         return -EINVAL;
5231                         }
5232                 }
5233
5234                 if (on) {
5235                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5236                         mv_msb = vlan_mask >> vlan_mask_offset;
5237
5238                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5239                                                 mirror_conf->vlan.vlan_mask;
5240                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5241                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5242                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5243                                                 mirror_conf->vlan.vlan_id[i];
5244                         }
5245                 } else {
5246                         mv_lsb = 0;
5247                         mv_msb = 0;
5248                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5249                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5250                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5251                 }
5252         }
5253
5254         /**
5255          * if enable pool mirror, write related pool mask register,if disable
5256          * pool mirror, clear PFMRVM register
5257          */
5258         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5259                 mirror_type |= IXGBE_MRCTL_VPME;
5260                 if (on) {
5261                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5262                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5263                         mr_info->mr_conf[rule_id].pool_mask =
5264                                         mirror_conf->pool_mask;
5265
5266                 } else {
5267                         mp_lsb = 0;
5268                         mp_msb = 0;
5269                         mr_info->mr_conf[rule_id].pool_mask = 0;
5270                 }
5271         }
5272         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5273                 mirror_type |= IXGBE_MRCTL_UPME;
5274         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5275                 mirror_type |= IXGBE_MRCTL_DPME;
5276
5277         /* read  mirror control register and recalculate it */
5278         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5279
5280         if (on) {
5281                 mr_ctl |= mirror_type;
5282                 mr_ctl &= mirror_rule_mask;
5283                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5284         } else {
5285                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5286         }
5287
5288         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5289         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5290
5291         /* write mirrror control  register */
5292         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5293
5294         /* write pool mirrror control  register */
5295         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5296                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5297                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5298                                 mp_msb);
5299         }
5300         /* write VLAN mirrror control  register */
5301         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5302                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5303                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5304                                 mv_msb);
5305         }
5306
5307         return 0;
5308 }
5309
5310 static int
5311 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5312 {
5313         int mr_ctl = 0;
5314         uint32_t lsb_val = 0;
5315         uint32_t msb_val = 0;
5316         const uint8_t rule_mr_offset = 4;
5317
5318         struct ixgbe_hw *hw =
5319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5320         struct ixgbe_mirror_info *mr_info =
5321                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5322
5323         if (ixgbe_vt_check(hw) < 0)
5324                 return -ENOTSUP;
5325
5326         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5327                 return -EINVAL;
5328
5329         memset(&mr_info->mr_conf[rule_id], 0,
5330                sizeof(struct rte_eth_mirror_conf));
5331
5332         /* clear PFVMCTL register */
5333         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5334
5335         /* clear pool mask register */
5336         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5337         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5338
5339         /* clear vlan mask register */
5340         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5341         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5342
5343         return 0;
5344 }
5345
5346 static int
5347 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5348 {
5349         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5350         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5351         uint32_t mask;
5352         struct ixgbe_hw *hw =
5353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5354
5355         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5356         mask |= (1 << IXGBE_MISC_VEC_ID);
5357         RTE_SET_USED(queue_id);
5358         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5359
5360         rte_intr_enable(intr_handle);
5361
5362         return 0;
5363 }
5364
5365 static int
5366 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5367 {
5368         uint32_t mask;
5369         struct ixgbe_hw *hw =
5370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371
5372         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5373         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5374         RTE_SET_USED(queue_id);
5375         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5376
5377         return 0;
5378 }
5379
5380 static int
5381 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5382 {
5383         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5384         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5385         uint32_t mask;
5386         struct ixgbe_hw *hw =
5387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388         struct ixgbe_interrupt *intr =
5389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5390
5391         if (queue_id < 16) {
5392                 ixgbe_disable_intr(hw);
5393                 intr->mask |= (1 << queue_id);
5394                 ixgbe_enable_intr(dev);
5395         } else if (queue_id < 32) {
5396                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5397                 mask &= (1 << queue_id);
5398                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5399         } else if (queue_id < 64) {
5400                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5401                 mask &= (1 << (queue_id - 32));
5402                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5403         }
5404         rte_intr_enable(intr_handle);
5405
5406         return 0;
5407 }
5408
5409 static int
5410 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5411 {
5412         uint32_t mask;
5413         struct ixgbe_hw *hw =
5414                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415         struct ixgbe_interrupt *intr =
5416                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5417
5418         if (queue_id < 16) {
5419                 ixgbe_disable_intr(hw);
5420                 intr->mask &= ~(1 << queue_id);
5421                 ixgbe_enable_intr(dev);
5422         } else if (queue_id < 32) {
5423                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5424                 mask &= ~(1 << queue_id);
5425                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5426         } else if (queue_id < 64) {
5427                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5428                 mask &= ~(1 << (queue_id - 32));
5429                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5430         }
5431
5432         return 0;
5433 }
5434
5435 static void
5436 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5437                      uint8_t queue, uint8_t msix_vector)
5438 {
5439         uint32_t tmp, idx;
5440
5441         if (direction == -1) {
5442                 /* other causes */
5443                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5444                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5445                 tmp &= ~0xFF;
5446                 tmp |= msix_vector;
5447                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5448         } else {
5449                 /* rx or tx cause */
5450                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5451                 idx = ((16 * (queue & 1)) + (8 * direction));
5452                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5453                 tmp &= ~(0xFF << idx);
5454                 tmp |= (msix_vector << idx);
5455                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5456         }
5457 }
5458
5459 /**
5460  * set the IVAR registers, mapping interrupt causes to vectors
5461  * @param hw
5462  *  pointer to ixgbe_hw struct
5463  * @direction
5464  *  0 for Rx, 1 for Tx, -1 for other causes
5465  * @queue
5466  *  queue to map the corresponding interrupt to
5467  * @msix_vector
5468  *  the vector to map to the corresponding queue
5469  */
5470 static void
5471 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5472                    uint8_t queue, uint8_t msix_vector)
5473 {
5474         uint32_t tmp, idx;
5475
5476         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5477         if (hw->mac.type == ixgbe_mac_82598EB) {
5478                 if (direction == -1)
5479                         direction = 0;
5480                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5481                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5482                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5483                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5484                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5485         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5486                         (hw->mac.type == ixgbe_mac_X540) ||
5487                         (hw->mac.type == ixgbe_mac_X550)) {
5488                 if (direction == -1) {
5489                         /* other causes */
5490                         idx = ((queue & 1) * 8);
5491                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5492                         tmp &= ~(0xFF << idx);
5493                         tmp |= (msix_vector << idx);
5494                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5495                 } else {
5496                         /* rx or tx causes */
5497                         idx = ((16 * (queue & 1)) + (8 * direction));
5498                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5499                         tmp &= ~(0xFF << idx);
5500                         tmp |= (msix_vector << idx);
5501                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5502                 }
5503         }
5504 }
5505
5506 static void
5507 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5508 {
5509         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5510         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5511         struct ixgbe_hw *hw =
5512                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         uint32_t q_idx;
5514         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5515
5516         /* Configure VF other cause ivar */
5517         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5518
5519         /* won't configure msix register if no mapping is done
5520          * between intr vector and event fd.
5521          */
5522         if (!rte_intr_dp_is_en(intr_handle))
5523                 return;
5524
5525         /* Configure all RX queues of VF */
5526         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5527                 /* Force all queue use vector 0,
5528                  * as IXGBE_VF_MAXMSIVECOTR = 1
5529                  */
5530                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5531                 intr_handle->intr_vec[q_idx] = vector_idx;
5532         }
5533 }
5534
5535 /**
5536  * Sets up the hardware to properly generate MSI-X interrupts
5537  * @hw
5538  *  board private structure
5539  */
5540 static void
5541 ixgbe_configure_msix(struct rte_eth_dev *dev)
5542 {
5543         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5544         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5545         struct ixgbe_hw *hw =
5546                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5547         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5548         uint32_t vec = IXGBE_MISC_VEC_ID;
5549         uint32_t mask;
5550         uint32_t gpie;
5551
5552         /* won't configure msix register if no mapping is done
5553          * between intr vector and event fd
5554          */
5555         if (!rte_intr_dp_is_en(intr_handle))
5556                 return;
5557
5558         if (rte_intr_allow_others(intr_handle))
5559                 vec = base = IXGBE_RX_VEC_START;
5560
5561         /* setup GPIE for MSI-x mode */
5562         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5563         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5564                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5565         /* auto clearing and auto setting corresponding bits in EIMS
5566          * when MSI-X interrupt is triggered
5567          */
5568         if (hw->mac.type == ixgbe_mac_82598EB) {
5569                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5570         } else {
5571                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5572                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5573         }
5574         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5575
5576         /* Populate the IVAR table and set the ITR values to the
5577          * corresponding register.
5578          */
5579         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5580              queue_id++) {
5581                 /* by default, 1:1 mapping */
5582                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5583                 intr_handle->intr_vec[queue_id] = vec;
5584                 if (vec < base + intr_handle->nb_efd - 1)
5585                         vec++;
5586         }
5587
5588         switch (hw->mac.type) {
5589         case ixgbe_mac_82598EB:
5590                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5591                                    IXGBE_MISC_VEC_ID);
5592                 break;
5593         case ixgbe_mac_82599EB:
5594         case ixgbe_mac_X540:
5595         case ixgbe_mac_X550:
5596                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5597                 break;
5598         default:
5599                 break;
5600         }
5601         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5602                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5603
5604         /* set up to autoclear timer, and the vectors */
5605         mask = IXGBE_EIMS_ENABLE_MASK;
5606         mask &= ~(IXGBE_EIMS_OTHER |
5607                   IXGBE_EIMS_MAILBOX |
5608                   IXGBE_EIMS_LSC);
5609
5610         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5611 }
5612
5613 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5614         uint16_t queue_idx, uint16_t tx_rate)
5615 {
5616         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5617         uint32_t rf_dec, rf_int;
5618         uint32_t bcnrc_val;
5619         uint16_t link_speed = dev->data->dev_link.link_speed;
5620
5621         if (queue_idx >= hw->mac.max_tx_queues)
5622                 return -EINVAL;
5623
5624         if (tx_rate != 0) {
5625                 /* Calculate the rate factor values to set */
5626                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5627                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5628                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5629
5630                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5631                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5632                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5633                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5634         } else {
5635                 bcnrc_val = 0;
5636         }
5637
5638         /*
5639          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5640          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5641          * set as 0x4.
5642          */
5643         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5644                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5645                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5646                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5647                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5648         else
5649                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5650                         IXGBE_MMW_SIZE_DEFAULT);
5651
5652         /* Set RTTBCNRC of queue X */
5653         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5654         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5655         IXGBE_WRITE_FLUSH(hw);
5656
5657         return 0;
5658 }
5659
5660 static int
5661 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5662                      __attribute__((unused)) uint32_t index,
5663                      __attribute__((unused)) uint32_t pool)
5664 {
5665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666         int diag;
5667
5668         /*
5669          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5670          * operation. Trap this case to avoid exhausting the [very limited]
5671          * set of PF resources used to store VF MAC addresses.
5672          */
5673         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5674                 return -1;
5675         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5676         if (diag != 0)
5677                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5678                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5679                             mac_addr->addr_bytes[0],
5680                             mac_addr->addr_bytes[1],
5681                             mac_addr->addr_bytes[2],
5682                             mac_addr->addr_bytes[3],
5683                             mac_addr->addr_bytes[4],
5684                             mac_addr->addr_bytes[5],
5685                             diag);
5686         return diag;
5687 }
5688
5689 static void
5690 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5691 {
5692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5694         struct ether_addr *mac_addr;
5695         uint32_t i;
5696         int diag;
5697
5698         /*
5699          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5700          * not support the deletion of a given MAC address.
5701          * Instead, it imposes to delete all MAC addresses, then to add again
5702          * all MAC addresses with the exception of the one to be deleted.
5703          */
5704         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5705
5706         /*
5707          * Add again all MAC addresses, with the exception of the deleted one
5708          * and of the permanent MAC address.
5709          */
5710         for (i = 0, mac_addr = dev->data->mac_addrs;
5711              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5712                 /* Skip the deleted MAC address */
5713                 if (i == index)
5714                         continue;
5715                 /* Skip NULL MAC addresses */
5716                 if (is_zero_ether_addr(mac_addr))
5717                         continue;
5718                 /* Skip the permanent MAC address */
5719                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5720                         continue;
5721                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5722                 if (diag != 0)
5723                         PMD_DRV_LOG(ERR,
5724                                     "Adding again MAC address "
5725                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5726                                     "diag=%d",
5727                                     mac_addr->addr_bytes[0],
5728                                     mac_addr->addr_bytes[1],
5729                                     mac_addr->addr_bytes[2],
5730                                     mac_addr->addr_bytes[3],
5731                                     mac_addr->addr_bytes[4],
5732                                     mac_addr->addr_bytes[5],
5733                                     diag);
5734         }
5735 }
5736
5737 static void
5738 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5739 {
5740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741
5742         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5743 }
5744
5745 int
5746 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5747                         struct rte_eth_syn_filter *filter,
5748                         bool add)
5749 {
5750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751         struct ixgbe_filter_info *filter_info =
5752                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5753         uint32_t syn_info;
5754         uint32_t synqf;
5755
5756         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5757                 return -EINVAL;
5758
5759         syn_info = filter_info->syn_info;
5760
5761         if (add) {
5762                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5763                         return -EINVAL;
5764                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5765                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5766
5767                 if (filter->hig_pri)
5768                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5769                 else
5770                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5771         } else {
5772                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5773                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5774                         return -ENOENT;
5775                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5776         }
5777
5778         filter_info->syn_info = synqf;
5779         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5780         IXGBE_WRITE_FLUSH(hw);
5781         return 0;
5782 }
5783
5784 static int
5785 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5786                         struct rte_eth_syn_filter *filter)
5787 {
5788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5790
5791         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5792                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5793                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5794                 return 0;
5795         }
5796         return -ENOENT;
5797 }
5798
5799 static int
5800 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5801                         enum rte_filter_op filter_op,
5802                         void *arg)
5803 {
5804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805         int ret;
5806
5807         MAC_TYPE_FILTER_SUP(hw->mac.type);
5808
5809         if (filter_op == RTE_ETH_FILTER_NOP)
5810                 return 0;
5811
5812         if (arg == NULL) {
5813                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5814                             filter_op);
5815                 return -EINVAL;
5816         }
5817
5818         switch (filter_op) {
5819         case RTE_ETH_FILTER_ADD:
5820                 ret = ixgbe_syn_filter_set(dev,
5821                                 (struct rte_eth_syn_filter *)arg,
5822                                 TRUE);
5823                 break;
5824         case RTE_ETH_FILTER_DELETE:
5825                 ret = ixgbe_syn_filter_set(dev,
5826                                 (struct rte_eth_syn_filter *)arg,
5827                                 FALSE);
5828                 break;
5829         case RTE_ETH_FILTER_GET:
5830                 ret = ixgbe_syn_filter_get(dev,
5831                                 (struct rte_eth_syn_filter *)arg);
5832                 break;
5833         default:
5834                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5835                 ret = -EINVAL;
5836                 break;
5837         }
5838
5839         return ret;
5840 }
5841
5842
5843 static inline enum ixgbe_5tuple_protocol
5844 convert_protocol_type(uint8_t protocol_value)
5845 {
5846         if (protocol_value == IPPROTO_TCP)
5847                 return IXGBE_FILTER_PROTOCOL_TCP;
5848         else if (protocol_value == IPPROTO_UDP)
5849                 return IXGBE_FILTER_PROTOCOL_UDP;
5850         else if (protocol_value == IPPROTO_SCTP)
5851                 return IXGBE_FILTER_PROTOCOL_SCTP;
5852         else
5853                 return IXGBE_FILTER_PROTOCOL_NONE;
5854 }
5855
5856 /* inject a 5-tuple filter to HW */
5857 static inline void
5858 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5859                            struct ixgbe_5tuple_filter *filter)
5860 {
5861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5862         int i;
5863         uint32_t ftqf, sdpqf;
5864         uint32_t l34timir = 0;
5865         uint8_t mask = 0xff;
5866
5867         i = filter->index;
5868
5869         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5870                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5871         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5872
5873         ftqf = (uint32_t)(filter->filter_info.proto &
5874                 IXGBE_FTQF_PROTOCOL_MASK);
5875         ftqf |= (uint32_t)((filter->filter_info.priority &
5876                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5877         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5878                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5879         if (filter->filter_info.dst_ip_mask == 0)
5880                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5881         if (filter->filter_info.src_port_mask == 0)
5882                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5883         if (filter->filter_info.dst_port_mask == 0)
5884                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5885         if (filter->filter_info.proto_mask == 0)
5886                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5887         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5888         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5889         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5890
5891         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5892         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5893         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5894         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5895
5896         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5897         l34timir |= (uint32_t)(filter->queue <<
5898                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5899         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5900 }
5901
5902 /*
5903  * add a 5tuple filter
5904  *
5905  * @param
5906  * dev: Pointer to struct rte_eth_dev.
5907  * index: the index the filter allocates.
5908  * filter: ponter to the filter that will be added.
5909  * rx_queue: the queue id the filter assigned to.
5910  *
5911  * @return
5912  *    - On success, zero.
5913  *    - On failure, a negative value.
5914  */
5915 static int
5916 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5917                         struct ixgbe_5tuple_filter *filter)
5918 {
5919         struct ixgbe_filter_info *filter_info =
5920                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5921         int i, idx, shift;
5922
5923         /*
5924          * look for an unused 5tuple filter index,
5925          * and insert the filter to list.
5926          */
5927         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5928                 idx = i / (sizeof(uint32_t) * NBBY);
5929                 shift = i % (sizeof(uint32_t) * NBBY);
5930                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5931                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5932                         filter->index = i;
5933                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5934                                           filter,
5935                                           entries);
5936                         break;
5937                 }
5938         }
5939         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5940                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5941                 return -ENOSYS;
5942         }
5943
5944         ixgbe_inject_5tuple_filter(dev, filter);
5945
5946         return 0;
5947 }
5948
5949 /*
5950  * remove a 5tuple filter
5951  *
5952  * @param
5953  * dev: Pointer to struct rte_eth_dev.
5954  * filter: the pointer of the filter will be removed.
5955  */
5956 static void
5957 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5958                         struct ixgbe_5tuple_filter *filter)
5959 {
5960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5961         struct ixgbe_filter_info *filter_info =
5962                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5963         uint16_t index = filter->index;
5964
5965         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5966                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5967         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5968         rte_free(filter);
5969
5970         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5971         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5972         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5973         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5974         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5975 }
5976
5977 static int
5978 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5979 {
5980         struct ixgbe_hw *hw;
5981         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5982         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5983
5984         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5985
5986         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5987                 return -EINVAL;
5988
5989         /* refuse mtu that requires the support of scattered packets when this
5990          * feature has not been enabled before.
5991          */
5992         if (!rx_conf->enable_scatter &&
5993             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5994              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5995                 return -EINVAL;
5996
5997         /*
5998          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5999          * request of the version 2.0 of the mailbox API.
6000          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6001          * of the mailbox API.
6002          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6003          * prior to 3.11.33 which contains the following change:
6004          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6005          */
6006         ixgbevf_rlpml_set_vf(hw, max_frame);
6007
6008         /* update max frame size */
6009         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6010         return 0;
6011 }
6012
6013 static inline struct ixgbe_5tuple_filter *
6014 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6015                         struct ixgbe_5tuple_filter_info *key)
6016 {
6017         struct ixgbe_5tuple_filter *it;
6018
6019         TAILQ_FOREACH(it, filter_list, entries) {
6020                 if (memcmp(key, &it->filter_info,
6021                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6022                         return it;
6023                 }
6024         }
6025         return NULL;
6026 }
6027
6028 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6029 static inline int
6030 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6031                         struct ixgbe_5tuple_filter_info *filter_info)
6032 {
6033         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6034                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6035                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6036                 return -EINVAL;
6037
6038         switch (filter->dst_ip_mask) {
6039         case UINT32_MAX:
6040                 filter_info->dst_ip_mask = 0;
6041                 filter_info->dst_ip = filter->dst_ip;
6042                 break;
6043         case 0:
6044                 filter_info->dst_ip_mask = 1;
6045                 break;
6046         default:
6047                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6048                 return -EINVAL;
6049         }
6050
6051         switch (filter->src_ip_mask) {
6052         case UINT32_MAX:
6053                 filter_info->src_ip_mask = 0;
6054                 filter_info->src_ip = filter->src_ip;
6055                 break;
6056         case 0:
6057                 filter_info->src_ip_mask = 1;
6058                 break;
6059         default:
6060                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6061                 return -EINVAL;
6062         }
6063
6064         switch (filter->dst_port_mask) {
6065         case UINT16_MAX:
6066                 filter_info->dst_port_mask = 0;
6067                 filter_info->dst_port = filter->dst_port;
6068                 break;
6069         case 0:
6070                 filter_info->dst_port_mask = 1;
6071                 break;
6072         default:
6073                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6074                 return -EINVAL;
6075         }
6076
6077         switch (filter->src_port_mask) {
6078         case UINT16_MAX:
6079                 filter_info->src_port_mask = 0;
6080                 filter_info->src_port = filter->src_port;
6081                 break;
6082         case 0:
6083                 filter_info->src_port_mask = 1;
6084                 break;
6085         default:
6086                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6087                 return -EINVAL;
6088         }
6089
6090         switch (filter->proto_mask) {
6091         case UINT8_MAX:
6092                 filter_info->proto_mask = 0;
6093                 filter_info->proto =
6094                         convert_protocol_type(filter->proto);
6095                 break;
6096         case 0:
6097                 filter_info->proto_mask = 1;
6098                 break;
6099         default:
6100                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6101                 return -EINVAL;
6102         }
6103
6104         filter_info->priority = (uint8_t)filter->priority;
6105         return 0;
6106 }
6107
6108 /*
6109  * add or delete a ntuple filter
6110  *
6111  * @param
6112  * dev: Pointer to struct rte_eth_dev.
6113  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6114  * add: if true, add filter, if false, remove filter
6115  *
6116  * @return
6117  *    - On success, zero.
6118  *    - On failure, a negative value.
6119  */
6120 int
6121 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6122                         struct rte_eth_ntuple_filter *ntuple_filter,
6123                         bool add)
6124 {
6125         struct ixgbe_filter_info *filter_info =
6126                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6127         struct ixgbe_5tuple_filter_info filter_5tuple;
6128         struct ixgbe_5tuple_filter *filter;
6129         int ret;
6130
6131         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6132                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6133                 return -EINVAL;
6134         }
6135
6136         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6137         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6138         if (ret < 0)
6139                 return ret;
6140
6141         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6142                                          &filter_5tuple);
6143         if (filter != NULL && add) {
6144                 PMD_DRV_LOG(ERR, "filter exists.");
6145                 return -EEXIST;
6146         }
6147         if (filter == NULL && !add) {
6148                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6149                 return -ENOENT;
6150         }
6151
6152         if (add) {
6153                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6154                                 sizeof(struct ixgbe_5tuple_filter), 0);
6155                 if (filter == NULL)
6156                         return -ENOMEM;
6157                 (void)rte_memcpy(&filter->filter_info,
6158                                  &filter_5tuple,
6159                                  sizeof(struct ixgbe_5tuple_filter_info));
6160                 filter->queue = ntuple_filter->queue;
6161                 ret = ixgbe_add_5tuple_filter(dev, filter);
6162                 if (ret < 0) {
6163                         rte_free(filter);
6164                         return ret;
6165                 }
6166         } else
6167                 ixgbe_remove_5tuple_filter(dev, filter);
6168
6169         return 0;
6170 }
6171
6172 /*
6173  * get a ntuple filter
6174  *
6175  * @param
6176  * dev: Pointer to struct rte_eth_dev.
6177  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6178  *
6179  * @return
6180  *    - On success, zero.
6181  *    - On failure, a negative value.
6182  */
6183 static int
6184 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6185                         struct rte_eth_ntuple_filter *ntuple_filter)
6186 {
6187         struct ixgbe_filter_info *filter_info =
6188                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6189         struct ixgbe_5tuple_filter_info filter_5tuple;
6190         struct ixgbe_5tuple_filter *filter;
6191         int ret;
6192
6193         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6194                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6195                 return -EINVAL;
6196         }
6197
6198         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6199         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6200         if (ret < 0)
6201                 return ret;
6202
6203         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6204                                          &filter_5tuple);
6205         if (filter == NULL) {
6206                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6207                 return -ENOENT;
6208         }
6209         ntuple_filter->queue = filter->queue;
6210         return 0;
6211 }
6212
6213 /*
6214  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6215  * @dev: pointer to rte_eth_dev structure
6216  * @filter_op:operation will be taken.
6217  * @arg: a pointer to specific structure corresponding to the filter_op
6218  *
6219  * @return
6220  *    - On success, zero.
6221  *    - On failure, a negative value.
6222  */
6223 static int
6224 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6225                                 enum rte_filter_op filter_op,
6226                                 void *arg)
6227 {
6228         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6229         int ret;
6230
6231         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6232
6233         if (filter_op == RTE_ETH_FILTER_NOP)
6234                 return 0;
6235
6236         if (arg == NULL) {
6237                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6238                             filter_op);
6239                 return -EINVAL;
6240         }
6241
6242         switch (filter_op) {
6243         case RTE_ETH_FILTER_ADD:
6244                 ret = ixgbe_add_del_ntuple_filter(dev,
6245                         (struct rte_eth_ntuple_filter *)arg,
6246                         TRUE);
6247                 break;
6248         case RTE_ETH_FILTER_DELETE:
6249                 ret = ixgbe_add_del_ntuple_filter(dev,
6250                         (struct rte_eth_ntuple_filter *)arg,
6251                         FALSE);
6252                 break;
6253         case RTE_ETH_FILTER_GET:
6254                 ret = ixgbe_get_ntuple_filter(dev,
6255                         (struct rte_eth_ntuple_filter *)arg);
6256                 break;
6257         default:
6258                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6259                 ret = -EINVAL;
6260                 break;
6261         }
6262         return ret;
6263 }
6264
6265 int
6266 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6267                         struct rte_eth_ethertype_filter *filter,
6268                         bool add)
6269 {
6270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6271         struct ixgbe_filter_info *filter_info =
6272                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6273         uint32_t etqf = 0;
6274         uint32_t etqs = 0;
6275         int ret;
6276         struct ixgbe_ethertype_filter ethertype_filter;
6277
6278         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6279                 return -EINVAL;
6280
6281         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6282                 filter->ether_type == ETHER_TYPE_IPv6) {
6283                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6284                         " ethertype filter.", filter->ether_type);
6285                 return -EINVAL;
6286         }
6287
6288         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6289                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6290                 return -EINVAL;
6291         }
6292         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6293                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6294                 return -EINVAL;
6295         }
6296
6297         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6298         if (ret >= 0 && add) {
6299                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6300                             filter->ether_type);
6301                 return -EEXIST;
6302         }
6303         if (ret < 0 && !add) {
6304                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6305                             filter->ether_type);
6306                 return -ENOENT;
6307         }
6308
6309         if (add) {
6310                 etqf = IXGBE_ETQF_FILTER_EN;
6311                 etqf |= (uint32_t)filter->ether_type;
6312                 etqs |= (uint32_t)((filter->queue <<
6313                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6314                                     IXGBE_ETQS_RX_QUEUE);
6315                 etqs |= IXGBE_ETQS_QUEUE_EN;
6316
6317                 ethertype_filter.ethertype = filter->ether_type;
6318                 ethertype_filter.etqf = etqf;
6319                 ethertype_filter.etqs = etqs;
6320                 ethertype_filter.conf = FALSE;
6321                 ret = ixgbe_ethertype_filter_insert(filter_info,
6322                                                     &ethertype_filter);
6323                 if (ret < 0) {
6324                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6325                         return -ENOSPC;
6326                 }
6327         } else {
6328                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6329                 if (ret < 0)
6330                         return -ENOSYS;
6331         }
6332         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6333         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6334         IXGBE_WRITE_FLUSH(hw);
6335
6336         return 0;
6337 }
6338
6339 static int
6340 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6341                         struct rte_eth_ethertype_filter *filter)
6342 {
6343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6344         struct ixgbe_filter_info *filter_info =
6345                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6346         uint32_t etqf, etqs;
6347         int ret;
6348
6349         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6350         if (ret < 0) {
6351                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6352                             filter->ether_type);
6353                 return -ENOENT;
6354         }
6355
6356         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6357         if (etqf & IXGBE_ETQF_FILTER_EN) {
6358                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6359                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6360                 filter->flags = 0;
6361                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6362                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6363                 return 0;
6364         }
6365         return -ENOENT;
6366 }
6367
6368 /*
6369  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6370  * @dev: pointer to rte_eth_dev structure
6371  * @filter_op:operation will be taken.
6372  * @arg: a pointer to specific structure corresponding to the filter_op
6373  */
6374 static int
6375 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6376                                 enum rte_filter_op filter_op,
6377                                 void *arg)
6378 {
6379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6380         int ret;
6381
6382         MAC_TYPE_FILTER_SUP(hw->mac.type);
6383
6384         if (filter_op == RTE_ETH_FILTER_NOP)
6385                 return 0;
6386
6387         if (arg == NULL) {
6388                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6389                             filter_op);
6390                 return -EINVAL;
6391         }
6392
6393         switch (filter_op) {
6394         case RTE_ETH_FILTER_ADD:
6395                 ret = ixgbe_add_del_ethertype_filter(dev,
6396                         (struct rte_eth_ethertype_filter *)arg,
6397                         TRUE);
6398                 break;
6399         case RTE_ETH_FILTER_DELETE:
6400                 ret = ixgbe_add_del_ethertype_filter(dev,
6401                         (struct rte_eth_ethertype_filter *)arg,
6402                         FALSE);
6403                 break;
6404         case RTE_ETH_FILTER_GET:
6405                 ret = ixgbe_get_ethertype_filter(dev,
6406                         (struct rte_eth_ethertype_filter *)arg);
6407                 break;
6408         default:
6409                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6410                 ret = -EINVAL;
6411                 break;
6412         }
6413         return ret;
6414 }
6415
6416 static int
6417 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6418                      enum rte_filter_type filter_type,
6419                      enum rte_filter_op filter_op,
6420                      void *arg)
6421 {
6422         int ret = 0;
6423
6424         switch (filter_type) {
6425         case RTE_ETH_FILTER_NTUPLE:
6426                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6427                 break;
6428         case RTE_ETH_FILTER_ETHERTYPE:
6429                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6430                 break;
6431         case RTE_ETH_FILTER_SYN:
6432                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6433                 break;
6434         case RTE_ETH_FILTER_FDIR:
6435                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6436                 break;
6437         case RTE_ETH_FILTER_L2_TUNNEL:
6438                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6439                 break;
6440         case RTE_ETH_FILTER_GENERIC:
6441                 if (filter_op != RTE_ETH_FILTER_GET)
6442                         return -EINVAL;
6443                 *(const void **)arg = &ixgbe_flow_ops;
6444                 break;
6445         default:
6446                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6447                                                         filter_type);
6448                 ret = -EINVAL;
6449                 break;
6450         }
6451
6452         return ret;
6453 }
6454
6455 static u8 *
6456 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6457                         u8 **mc_addr_ptr, u32 *vmdq)
6458 {
6459         u8 *mc_addr;
6460
6461         *vmdq = 0;
6462         mc_addr = *mc_addr_ptr;
6463         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6464         return mc_addr;
6465 }
6466
6467 static int
6468 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6469                           struct ether_addr *mc_addr_set,
6470                           uint32_t nb_mc_addr)
6471 {
6472         struct ixgbe_hw *hw;
6473         u8 *mc_addr_list;
6474
6475         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6476         mc_addr_list = (u8 *)mc_addr_set;
6477         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6478                                          ixgbe_dev_addr_list_itr, TRUE);
6479 }
6480
6481 static uint64_t
6482 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6483 {
6484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6485         uint64_t systime_cycles;
6486
6487         switch (hw->mac.type) {
6488         case ixgbe_mac_X550:
6489         case ixgbe_mac_X550EM_x:
6490         case ixgbe_mac_X550EM_a:
6491                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6492                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6493                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6494                                 * NSEC_PER_SEC;
6495                 break;
6496         default:
6497                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6498                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6499                                 << 32;
6500         }
6501
6502         return systime_cycles;
6503 }
6504
6505 static uint64_t
6506 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6507 {
6508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6509         uint64_t rx_tstamp_cycles;
6510
6511         switch (hw->mac.type) {
6512         case ixgbe_mac_X550:
6513         case ixgbe_mac_X550EM_x:
6514         case ixgbe_mac_X550EM_a:
6515                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6516                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6517                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6518                                 * NSEC_PER_SEC;
6519                 break;
6520         default:
6521                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6522                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6523                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6524                                 << 32;
6525         }
6526
6527         return rx_tstamp_cycles;
6528 }
6529
6530 static uint64_t
6531 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6532 {
6533         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6534         uint64_t tx_tstamp_cycles;
6535
6536         switch (hw->mac.type) {
6537         case ixgbe_mac_X550:
6538         case ixgbe_mac_X550EM_x:
6539         case ixgbe_mac_X550EM_a:
6540                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6541                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6542                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6543                                 * NSEC_PER_SEC;
6544                 break;
6545         default:
6546                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6547                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6548                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6549                                 << 32;
6550         }
6551
6552         return tx_tstamp_cycles;
6553 }
6554
6555 static void
6556 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6557 {
6558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559         struct ixgbe_adapter *adapter =
6560                 (struct ixgbe_adapter *)dev->data->dev_private;
6561         struct rte_eth_link link;
6562         uint32_t incval = 0;
6563         uint32_t shift = 0;
6564
6565         /* Get current link speed. */
6566         memset(&link, 0, sizeof(link));
6567         ixgbe_dev_link_update(dev, 1);
6568         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6569
6570         switch (link.link_speed) {
6571         case ETH_SPEED_NUM_100M:
6572                 incval = IXGBE_INCVAL_100;
6573                 shift = IXGBE_INCVAL_SHIFT_100;
6574                 break;
6575         case ETH_SPEED_NUM_1G:
6576                 incval = IXGBE_INCVAL_1GB;
6577                 shift = IXGBE_INCVAL_SHIFT_1GB;
6578                 break;
6579         case ETH_SPEED_NUM_10G:
6580         default:
6581                 incval = IXGBE_INCVAL_10GB;
6582                 shift = IXGBE_INCVAL_SHIFT_10GB;
6583                 break;
6584         }
6585
6586         switch (hw->mac.type) {
6587         case ixgbe_mac_X550:
6588         case ixgbe_mac_X550EM_x:
6589         case ixgbe_mac_X550EM_a:
6590                 /* Independent of link speed. */
6591                 incval = 1;
6592                 /* Cycles read will be interpreted as ns. */
6593                 shift = 0;
6594                 /* Fall-through */
6595         case ixgbe_mac_X540:
6596                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6597                 break;
6598         case ixgbe_mac_82599EB:
6599                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6600                 shift -= IXGBE_INCVAL_SHIFT_82599;
6601                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6602                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6603                 break;
6604         default:
6605                 /* Not supported. */
6606                 return;
6607         }
6608
6609         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6610         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6611         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6612
6613         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6614         adapter->systime_tc.cc_shift = shift;
6615         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6616
6617         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6618         adapter->rx_tstamp_tc.cc_shift = shift;
6619         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6620
6621         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6622         adapter->tx_tstamp_tc.cc_shift = shift;
6623         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6624 }
6625
6626 static int
6627 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6628 {
6629         struct ixgbe_adapter *adapter =
6630                         (struct ixgbe_adapter *)dev->data->dev_private;
6631
6632         adapter->systime_tc.nsec += delta;
6633         adapter->rx_tstamp_tc.nsec += delta;
6634         adapter->tx_tstamp_tc.nsec += delta;
6635
6636         return 0;
6637 }
6638
6639 static int
6640 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6641 {
6642         uint64_t ns;
6643         struct ixgbe_adapter *adapter =
6644                         (struct ixgbe_adapter *)dev->data->dev_private;
6645
6646         ns = rte_timespec_to_ns(ts);
6647         /* Set the timecounters to a new value. */
6648         adapter->systime_tc.nsec = ns;
6649         adapter->rx_tstamp_tc.nsec = ns;
6650         adapter->tx_tstamp_tc.nsec = ns;
6651
6652         return 0;
6653 }
6654
6655 static int
6656 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6657 {
6658         uint64_t ns, systime_cycles;
6659         struct ixgbe_adapter *adapter =
6660                         (struct ixgbe_adapter *)dev->data->dev_private;
6661
6662         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6663         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6664         *ts = rte_ns_to_timespec(ns);
6665
6666         return 0;
6667 }
6668
6669 static int
6670 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6671 {
6672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6673         uint32_t tsync_ctl;
6674         uint32_t tsauxc;
6675
6676         /* Stop the timesync system time. */
6677         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6678         /* Reset the timesync system time value. */
6679         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6680         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6681
6682         /* Enable system time for platforms where it isn't on by default. */
6683         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6684         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6685         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6686
6687         ixgbe_start_timecounters(dev);
6688
6689         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6690         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6691                         (ETHER_TYPE_1588 |
6692                          IXGBE_ETQF_FILTER_EN |
6693                          IXGBE_ETQF_1588));
6694
6695         /* Enable timestamping of received PTP packets. */
6696         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6697         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6698         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6699
6700         /* Enable timestamping of transmitted PTP packets. */
6701         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6702         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6703         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6704
6705         IXGBE_WRITE_FLUSH(hw);
6706
6707         return 0;
6708 }
6709
6710 static int
6711 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6712 {
6713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6714         uint32_t tsync_ctl;
6715
6716         /* Disable timestamping of transmitted PTP packets. */
6717         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6718         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6719         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6720
6721         /* Disable timestamping of received PTP packets. */
6722         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6723         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6724         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6725
6726         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6727         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6728
6729         /* Stop incrementating the System Time registers. */
6730         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6731
6732         return 0;
6733 }
6734
6735 static int
6736 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6737                                  struct timespec *timestamp,
6738                                  uint32_t flags __rte_unused)
6739 {
6740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741         struct ixgbe_adapter *adapter =
6742                 (struct ixgbe_adapter *)dev->data->dev_private;
6743         uint32_t tsync_rxctl;
6744         uint64_t rx_tstamp_cycles;
6745         uint64_t ns;
6746
6747         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6748         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6749                 return -EINVAL;
6750
6751         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6752         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6753         *timestamp = rte_ns_to_timespec(ns);
6754
6755         return  0;
6756 }
6757
6758 static int
6759 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6760                                  struct timespec *timestamp)
6761 {
6762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6763         struct ixgbe_adapter *adapter =
6764                 (struct ixgbe_adapter *)dev->data->dev_private;
6765         uint32_t tsync_txctl;
6766         uint64_t tx_tstamp_cycles;
6767         uint64_t ns;
6768
6769         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6770         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6771                 return -EINVAL;
6772
6773         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6774         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6775         *timestamp = rte_ns_to_timespec(ns);
6776
6777         return 0;
6778 }
6779
6780 static int
6781 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6782 {
6783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784         int count = 0;
6785         int g_ind = 0;
6786         const struct reg_info *reg_group;
6787         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6788                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6789
6790         while ((reg_group = reg_set[g_ind++]))
6791                 count += ixgbe_regs_group_count(reg_group);
6792
6793         return count;
6794 }
6795
6796 static int
6797 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6798 {
6799         int count = 0;
6800         int g_ind = 0;
6801         const struct reg_info *reg_group;
6802
6803         while ((reg_group = ixgbevf_regs[g_ind++]))
6804                 count += ixgbe_regs_group_count(reg_group);
6805
6806         return count;
6807 }
6808
6809 static int
6810 ixgbe_get_regs(struct rte_eth_dev *dev,
6811               struct rte_dev_reg_info *regs)
6812 {
6813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6814         uint32_t *data = regs->data;
6815         int g_ind = 0;
6816         int count = 0;
6817         const struct reg_info *reg_group;
6818         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6819                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6820
6821         if (data == NULL) {
6822                 regs->length = ixgbe_get_reg_length(dev);
6823                 regs->width = sizeof(uint32_t);
6824                 return 0;
6825         }
6826
6827         /* Support only full register dump */
6828         if ((regs->length == 0) ||
6829             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6830                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6831                         hw->device_id;
6832                 while ((reg_group = reg_set[g_ind++]))
6833                         count += ixgbe_read_regs_group(dev, &data[count],
6834                                 reg_group);
6835                 return 0;
6836         }
6837
6838         return -ENOTSUP;
6839 }
6840
6841 static int
6842 ixgbevf_get_regs(struct rte_eth_dev *dev,
6843                 struct rte_dev_reg_info *regs)
6844 {
6845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6846         uint32_t *data = regs->data;
6847         int g_ind = 0;
6848         int count = 0;
6849         const struct reg_info *reg_group;
6850
6851         if (data == NULL) {
6852                 regs->length = ixgbevf_get_reg_length(dev);
6853                 regs->width = sizeof(uint32_t);
6854                 return 0;
6855         }
6856
6857         /* Support only full register dump */
6858         if ((regs->length == 0) ||
6859             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6860                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6861                         hw->device_id;
6862                 while ((reg_group = ixgbevf_regs[g_ind++]))
6863                         count += ixgbe_read_regs_group(dev, &data[count],
6864                                                       reg_group);
6865                 return 0;
6866         }
6867
6868         return -ENOTSUP;
6869 }
6870
6871 static int
6872 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6873 {
6874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875
6876         /* Return unit is byte count */
6877         return hw->eeprom.word_size * 2;
6878 }
6879
6880 static int
6881 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6882                 struct rte_dev_eeprom_info *in_eeprom)
6883 {
6884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6886         uint16_t *data = in_eeprom->data;
6887         int first, length;
6888
6889         first = in_eeprom->offset >> 1;
6890         length = in_eeprom->length >> 1;
6891         if ((first > hw->eeprom.word_size) ||
6892             ((first + length) > hw->eeprom.word_size))
6893                 return -EINVAL;
6894
6895         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6896
6897         return eeprom->ops.read_buffer(hw, first, length, data);
6898 }
6899
6900 static int
6901 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6902                 struct rte_dev_eeprom_info *in_eeprom)
6903 {
6904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6906         uint16_t *data = in_eeprom->data;
6907         int first, length;
6908
6909         first = in_eeprom->offset >> 1;
6910         length = in_eeprom->length >> 1;
6911         if ((first > hw->eeprom.word_size) ||
6912             ((first + length) > hw->eeprom.word_size))
6913                 return -EINVAL;
6914
6915         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6916
6917         return eeprom->ops.write_buffer(hw,  first, length, data);
6918 }
6919
6920 uint16_t
6921 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6922         switch (mac_type) {
6923         case ixgbe_mac_X550:
6924         case ixgbe_mac_X550EM_x:
6925         case ixgbe_mac_X550EM_a:
6926                 return ETH_RSS_RETA_SIZE_512;
6927         case ixgbe_mac_X550_vf:
6928         case ixgbe_mac_X550EM_x_vf:
6929         case ixgbe_mac_X550EM_a_vf:
6930                 return ETH_RSS_RETA_SIZE_64;
6931         default:
6932                 return ETH_RSS_RETA_SIZE_128;
6933         }
6934 }
6935
6936 uint32_t
6937 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6938         switch (mac_type) {
6939         case ixgbe_mac_X550:
6940         case ixgbe_mac_X550EM_x:
6941         case ixgbe_mac_X550EM_a:
6942                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6943                         return IXGBE_RETA(reta_idx >> 2);
6944                 else
6945                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6946         case ixgbe_mac_X550_vf:
6947         case ixgbe_mac_X550EM_x_vf:
6948         case ixgbe_mac_X550EM_a_vf:
6949                 return IXGBE_VFRETA(reta_idx >> 2);
6950         default:
6951                 return IXGBE_RETA(reta_idx >> 2);
6952         }
6953 }
6954
6955 uint32_t
6956 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6957         switch (mac_type) {
6958         case ixgbe_mac_X550_vf:
6959         case ixgbe_mac_X550EM_x_vf:
6960         case ixgbe_mac_X550EM_a_vf:
6961                 return IXGBE_VFMRQC;
6962         default:
6963                 return IXGBE_MRQC;
6964         }
6965 }
6966
6967 uint32_t
6968 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6969         switch (mac_type) {
6970         case ixgbe_mac_X550_vf:
6971         case ixgbe_mac_X550EM_x_vf:
6972         case ixgbe_mac_X550EM_a_vf:
6973                 return IXGBE_VFRSSRK(i);
6974         default:
6975                 return IXGBE_RSSRK(i);
6976         }
6977 }
6978
6979 bool
6980 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6981         switch (mac_type) {
6982         case ixgbe_mac_82599_vf:
6983         case ixgbe_mac_X540_vf:
6984                 return 0;
6985         default:
6986                 return 1;
6987         }
6988 }
6989
6990 static int
6991 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6992                         struct rte_eth_dcb_info *dcb_info)
6993 {
6994         struct ixgbe_dcb_config *dcb_config =
6995                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6996         struct ixgbe_dcb_tc_config *tc;
6997         uint8_t i, j;
6998
6999         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7000                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7001         else
7002                 dcb_info->nb_tcs = 1;
7003
7004         if (dcb_config->vt_mode) { /* vt is enabled*/
7005                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7006                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7007                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7008                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7009                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7010                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7011                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7012                                                 i * dcb_info->nb_tcs + j;
7013                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7014                                 dcb_info->tc_queue.tc_txq[i][j].base =
7015                                                 i * dcb_info->nb_tcs + j;
7016                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7017                         }
7018                 }
7019         } else { /* vt is disabled*/
7020                 struct rte_eth_dcb_rx_conf *rx_conf =
7021                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7022                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7023                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7024                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7025                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7026                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7027                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7028                         }
7029                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7030                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7031                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7032                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7033                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7034                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7035                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7036                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7037                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7038                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7039                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7040                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7041                         }
7042                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7043                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7044                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7045                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7046                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7047                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7048                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7049                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7050                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7051                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7052                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7053                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7054                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7055                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7056                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7057                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7058                 }
7059         }
7060         for (i = 0; i < dcb_info->nb_tcs; i++) {
7061                 tc = &dcb_config->tc_config[i];
7062                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7063         }
7064         return 0;
7065 }
7066
7067 /* Update e-tag ether type */
7068 static int
7069 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7070                             uint16_t ether_type)
7071 {
7072         uint32_t etag_etype;
7073
7074         if (hw->mac.type != ixgbe_mac_X550 &&
7075             hw->mac.type != ixgbe_mac_X550EM_x &&
7076             hw->mac.type != ixgbe_mac_X550EM_a) {
7077                 return -ENOTSUP;
7078         }
7079
7080         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7081         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7082         etag_etype |= ether_type;
7083         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7084         IXGBE_WRITE_FLUSH(hw);
7085
7086         return 0;
7087 }
7088
7089 /* Config l2 tunnel ether type */
7090 static int
7091 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7092                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7093 {
7094         int ret = 0;
7095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096         struct ixgbe_l2_tn_info *l2_tn_info =
7097                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7098
7099         if (l2_tunnel == NULL)
7100                 return -EINVAL;
7101
7102         switch (l2_tunnel->l2_tunnel_type) {
7103         case RTE_L2_TUNNEL_TYPE_E_TAG:
7104                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7105                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7106                 break;
7107         default:
7108                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7109                 ret = -EINVAL;
7110                 break;
7111         }
7112
7113         return ret;
7114 }
7115
7116 /* Enable e-tag tunnel */
7117 static int
7118 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7119 {
7120         uint32_t etag_etype;
7121
7122         if (hw->mac.type != ixgbe_mac_X550 &&
7123             hw->mac.type != ixgbe_mac_X550EM_x &&
7124             hw->mac.type != ixgbe_mac_X550EM_a) {
7125                 return -ENOTSUP;
7126         }
7127
7128         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7129         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7130         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7131         IXGBE_WRITE_FLUSH(hw);
7132
7133         return 0;
7134 }
7135
7136 /* Enable l2 tunnel */
7137 static int
7138 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7139                            enum rte_eth_tunnel_type l2_tunnel_type)
7140 {
7141         int ret = 0;
7142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7143         struct ixgbe_l2_tn_info *l2_tn_info =
7144                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7145
7146         switch (l2_tunnel_type) {
7147         case RTE_L2_TUNNEL_TYPE_E_TAG:
7148                 l2_tn_info->e_tag_en = TRUE;
7149                 ret = ixgbe_e_tag_enable(hw);
7150                 break;
7151         default:
7152                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7153                 ret = -EINVAL;
7154                 break;
7155         }
7156
7157         return ret;
7158 }
7159
7160 /* Disable e-tag tunnel */
7161 static int
7162 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7163 {
7164         uint32_t etag_etype;
7165
7166         if (hw->mac.type != ixgbe_mac_X550 &&
7167             hw->mac.type != ixgbe_mac_X550EM_x &&
7168             hw->mac.type != ixgbe_mac_X550EM_a) {
7169                 return -ENOTSUP;
7170         }
7171
7172         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7173         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7174         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7175         IXGBE_WRITE_FLUSH(hw);
7176
7177         return 0;
7178 }
7179
7180 /* Disable l2 tunnel */
7181 static int
7182 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7183                             enum rte_eth_tunnel_type l2_tunnel_type)
7184 {
7185         int ret = 0;
7186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7187         struct ixgbe_l2_tn_info *l2_tn_info =
7188                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7189
7190         switch (l2_tunnel_type) {
7191         case RTE_L2_TUNNEL_TYPE_E_TAG:
7192                 l2_tn_info->e_tag_en = FALSE;
7193                 ret = ixgbe_e_tag_disable(hw);
7194                 break;
7195         default:
7196                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7197                 ret = -EINVAL;
7198                 break;
7199         }
7200
7201         return ret;
7202 }
7203
7204 static int
7205 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7206                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7207 {
7208         int ret = 0;
7209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7210         uint32_t i, rar_entries;
7211         uint32_t rar_low, rar_high;
7212
7213         if (hw->mac.type != ixgbe_mac_X550 &&
7214             hw->mac.type != ixgbe_mac_X550EM_x &&
7215             hw->mac.type != ixgbe_mac_X550EM_a) {
7216                 return -ENOTSUP;
7217         }
7218
7219         rar_entries = ixgbe_get_num_rx_addrs(hw);
7220
7221         for (i = 1; i < rar_entries; i++) {
7222                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7223                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7224                 if ((rar_high & IXGBE_RAH_AV) &&
7225                     (rar_high & IXGBE_RAH_ADTYPE) &&
7226                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7227                      l2_tunnel->tunnel_id)) {
7228                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7229                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7230
7231                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7232
7233                         return ret;
7234                 }
7235         }
7236
7237         return ret;
7238 }
7239
7240 static int
7241 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7242                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7243 {
7244         int ret = 0;
7245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7246         uint32_t i, rar_entries;
7247         uint32_t rar_low, rar_high;
7248
7249         if (hw->mac.type != ixgbe_mac_X550 &&
7250             hw->mac.type != ixgbe_mac_X550EM_x &&
7251             hw->mac.type != ixgbe_mac_X550EM_a) {
7252                 return -ENOTSUP;
7253         }
7254
7255         /* One entry for one tunnel. Try to remove potential existing entry. */
7256         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7257
7258         rar_entries = ixgbe_get_num_rx_addrs(hw);
7259
7260         for (i = 1; i < rar_entries; i++) {
7261                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7262                 if (rar_high & IXGBE_RAH_AV) {
7263                         continue;
7264                 } else {
7265                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7266                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7267                         rar_low = l2_tunnel->tunnel_id;
7268
7269                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7270                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7271
7272                         return ret;
7273                 }
7274         }
7275
7276         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7277                      " Please remove a rule before adding a new one.");
7278         return -EINVAL;
7279 }
7280
7281 static inline struct ixgbe_l2_tn_filter *
7282 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7283                           struct ixgbe_l2_tn_key *key)
7284 {
7285         int ret;
7286
7287         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7288         if (ret < 0)
7289                 return NULL;
7290
7291         return l2_tn_info->hash_map[ret];
7292 }
7293
7294 static inline int
7295 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7296                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7297 {
7298         int ret;
7299
7300         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7301                                &l2_tn_filter->key);
7302
7303         if (ret < 0) {
7304                 PMD_DRV_LOG(ERR,
7305                             "Failed to insert L2 tunnel filter"
7306                             " to hash table %d!",
7307                             ret);
7308                 return ret;
7309         }
7310
7311         l2_tn_info->hash_map[ret] = l2_tn_filter;
7312
7313         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7314
7315         return 0;
7316 }
7317
7318 static inline int
7319 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7320                           struct ixgbe_l2_tn_key *key)
7321 {
7322         int ret;
7323         struct ixgbe_l2_tn_filter *l2_tn_filter;
7324
7325         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7326
7327         if (ret < 0) {
7328                 PMD_DRV_LOG(ERR,
7329                             "No such L2 tunnel filter to delete %d!",
7330                             ret);
7331                 return ret;
7332         }
7333
7334         l2_tn_filter = l2_tn_info->hash_map[ret];
7335         l2_tn_info->hash_map[ret] = NULL;
7336
7337         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7338         rte_free(l2_tn_filter);
7339
7340         return 0;
7341 }
7342
7343 /* Add l2 tunnel filter */
7344 int
7345 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7346                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7347                                bool restore)
7348 {
7349         int ret;
7350         struct ixgbe_l2_tn_info *l2_tn_info =
7351                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7352         struct ixgbe_l2_tn_key key;
7353         struct ixgbe_l2_tn_filter *node;
7354
7355         if (!restore) {
7356                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7357                 key.tn_id = l2_tunnel->tunnel_id;
7358
7359                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7360
7361                 if (node) {
7362                         PMD_DRV_LOG(ERR,
7363                                     "The L2 tunnel filter already exists!");
7364                         return -EINVAL;
7365                 }
7366
7367                 node = rte_zmalloc("ixgbe_l2_tn",
7368                                    sizeof(struct ixgbe_l2_tn_filter),
7369                                    0);
7370                 if (!node)
7371                         return -ENOMEM;
7372
7373                 (void)rte_memcpy(&node->key,
7374                                  &key,
7375                                  sizeof(struct ixgbe_l2_tn_key));
7376                 node->pool = l2_tunnel->pool;
7377                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7378                 if (ret < 0) {
7379                         rte_free(node);
7380                         return ret;
7381                 }
7382         }
7383
7384         switch (l2_tunnel->l2_tunnel_type) {
7385         case RTE_L2_TUNNEL_TYPE_E_TAG:
7386                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7387                 break;
7388         default:
7389                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7390                 ret = -EINVAL;
7391                 break;
7392         }
7393
7394         if ((!restore) && (ret < 0))
7395                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7396
7397         return ret;
7398 }
7399
7400 /* Delete l2 tunnel filter */
7401 int
7402 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7403                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7404 {
7405         int ret;
7406         struct ixgbe_l2_tn_info *l2_tn_info =
7407                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7408         struct ixgbe_l2_tn_key key;
7409
7410         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7411         key.tn_id = l2_tunnel->tunnel_id;
7412         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7413         if (ret < 0)
7414                 return ret;
7415
7416         switch (l2_tunnel->l2_tunnel_type) {
7417         case RTE_L2_TUNNEL_TYPE_E_TAG:
7418                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7419                 break;
7420         default:
7421                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7422                 ret = -EINVAL;
7423                 break;
7424         }
7425
7426         return ret;
7427 }
7428
7429 /**
7430  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7431  * @dev: pointer to rte_eth_dev structure
7432  * @filter_op:operation will be taken.
7433  * @arg: a pointer to specific structure corresponding to the filter_op
7434  */
7435 static int
7436 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7437                                   enum rte_filter_op filter_op,
7438                                   void *arg)
7439 {
7440         int ret;
7441
7442         if (filter_op == RTE_ETH_FILTER_NOP)
7443                 return 0;
7444
7445         if (arg == NULL) {
7446                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7447                             filter_op);
7448                 return -EINVAL;
7449         }
7450
7451         switch (filter_op) {
7452         case RTE_ETH_FILTER_ADD:
7453                 ret = ixgbe_dev_l2_tunnel_filter_add
7454                         (dev,
7455                          (struct rte_eth_l2_tunnel_conf *)arg,
7456                          FALSE);
7457                 break;
7458         case RTE_ETH_FILTER_DELETE:
7459                 ret = ixgbe_dev_l2_tunnel_filter_del
7460                         (dev,
7461                          (struct rte_eth_l2_tunnel_conf *)arg);
7462                 break;
7463         default:
7464                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7465                 ret = -EINVAL;
7466                 break;
7467         }
7468         return ret;
7469 }
7470
7471 static int
7472 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7473 {
7474         int ret = 0;
7475         uint32_t ctrl;
7476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477
7478         if (hw->mac.type != ixgbe_mac_X550 &&
7479             hw->mac.type != ixgbe_mac_X550EM_x &&
7480             hw->mac.type != ixgbe_mac_X550EM_a) {
7481                 return -ENOTSUP;
7482         }
7483
7484         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7485         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7486         if (en)
7487                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7488         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7489
7490         return ret;
7491 }
7492
7493 /* Enable l2 tunnel forwarding */
7494 static int
7495 ixgbe_dev_l2_tunnel_forwarding_enable
7496         (struct rte_eth_dev *dev,
7497          enum rte_eth_tunnel_type l2_tunnel_type)
7498 {
7499         struct ixgbe_l2_tn_info *l2_tn_info =
7500                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7501         int ret = 0;
7502
7503         switch (l2_tunnel_type) {
7504         case RTE_L2_TUNNEL_TYPE_E_TAG:
7505                 l2_tn_info->e_tag_fwd_en = TRUE;
7506                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7507                 break;
7508         default:
7509                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7510                 ret = -EINVAL;
7511                 break;
7512         }
7513
7514         return ret;
7515 }
7516
7517 /* Disable l2 tunnel forwarding */
7518 static int
7519 ixgbe_dev_l2_tunnel_forwarding_disable
7520         (struct rte_eth_dev *dev,
7521          enum rte_eth_tunnel_type l2_tunnel_type)
7522 {
7523         struct ixgbe_l2_tn_info *l2_tn_info =
7524                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7525         int ret = 0;
7526
7527         switch (l2_tunnel_type) {
7528         case RTE_L2_TUNNEL_TYPE_E_TAG:
7529                 l2_tn_info->e_tag_fwd_en = FALSE;
7530                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7531                 break;
7532         default:
7533                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7534                 ret = -EINVAL;
7535                 break;
7536         }
7537
7538         return ret;
7539 }
7540
7541 static int
7542 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7543                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7544                              bool en)
7545 {
7546         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7547         int ret = 0;
7548         uint32_t vmtir, vmvir;
7549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7550
7551         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7552                 PMD_DRV_LOG(ERR,
7553                             "VF id %u should be less than %u",
7554                             l2_tunnel->vf_id,
7555                             pci_dev->max_vfs);
7556                 return -EINVAL;
7557         }
7558
7559         if (hw->mac.type != ixgbe_mac_X550 &&
7560             hw->mac.type != ixgbe_mac_X550EM_x &&
7561             hw->mac.type != ixgbe_mac_X550EM_a) {
7562                 return -ENOTSUP;
7563         }
7564
7565         if (en)
7566                 vmtir = l2_tunnel->tunnel_id;
7567         else
7568                 vmtir = 0;
7569
7570         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7571
7572         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7573         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7574         if (en)
7575                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7576         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7577
7578         return ret;
7579 }
7580
7581 /* Enable l2 tunnel tag insertion */
7582 static int
7583 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7584                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7585 {
7586         int ret = 0;
7587
7588         switch (l2_tunnel->l2_tunnel_type) {
7589         case RTE_L2_TUNNEL_TYPE_E_TAG:
7590                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7591                 break;
7592         default:
7593                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7594                 ret = -EINVAL;
7595                 break;
7596         }
7597
7598         return ret;
7599 }
7600
7601 /* Disable l2 tunnel tag insertion */
7602 static int
7603 ixgbe_dev_l2_tunnel_insertion_disable
7604         (struct rte_eth_dev *dev,
7605          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7606 {
7607         int ret = 0;
7608
7609         switch (l2_tunnel->l2_tunnel_type) {
7610         case RTE_L2_TUNNEL_TYPE_E_TAG:
7611                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7612                 break;
7613         default:
7614                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7615                 ret = -EINVAL;
7616                 break;
7617         }
7618
7619         return ret;
7620 }
7621
7622 static int
7623 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7624                              bool en)
7625 {
7626         int ret = 0;
7627         uint32_t qde;
7628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7629
7630         if (hw->mac.type != ixgbe_mac_X550 &&
7631             hw->mac.type != ixgbe_mac_X550EM_x &&
7632             hw->mac.type != ixgbe_mac_X550EM_a) {
7633                 return -ENOTSUP;
7634         }
7635
7636         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7637         if (en)
7638                 qde |= IXGBE_QDE_STRIP_TAG;
7639         else
7640                 qde &= ~IXGBE_QDE_STRIP_TAG;
7641         qde &= ~IXGBE_QDE_READ;
7642         qde |= IXGBE_QDE_WRITE;
7643         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7644
7645         return ret;
7646 }
7647
7648 /* Enable l2 tunnel tag stripping */
7649 static int
7650 ixgbe_dev_l2_tunnel_stripping_enable
7651         (struct rte_eth_dev *dev,
7652          enum rte_eth_tunnel_type l2_tunnel_type)
7653 {
7654         int ret = 0;
7655
7656         switch (l2_tunnel_type) {
7657         case RTE_L2_TUNNEL_TYPE_E_TAG:
7658                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7659                 break;
7660         default:
7661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7662                 ret = -EINVAL;
7663                 break;
7664         }
7665
7666         return ret;
7667 }
7668
7669 /* Disable l2 tunnel tag stripping */
7670 static int
7671 ixgbe_dev_l2_tunnel_stripping_disable
7672         (struct rte_eth_dev *dev,
7673          enum rte_eth_tunnel_type l2_tunnel_type)
7674 {
7675         int ret = 0;
7676
7677         switch (l2_tunnel_type) {
7678         case RTE_L2_TUNNEL_TYPE_E_TAG:
7679                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7680                 break;
7681         default:
7682                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7683                 ret = -EINVAL;
7684                 break;
7685         }
7686
7687         return ret;
7688 }
7689
7690 /* Enable/disable l2 tunnel offload functions */
7691 static int
7692 ixgbe_dev_l2_tunnel_offload_set
7693         (struct rte_eth_dev *dev,
7694          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7695          uint32_t mask,
7696          uint8_t en)
7697 {
7698         int ret = 0;
7699
7700         if (l2_tunnel == NULL)
7701                 return -EINVAL;
7702
7703         ret = -EINVAL;
7704         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7705                 if (en)
7706                         ret = ixgbe_dev_l2_tunnel_enable(
7707                                 dev,
7708                                 l2_tunnel->l2_tunnel_type);
7709                 else
7710                         ret = ixgbe_dev_l2_tunnel_disable(
7711                                 dev,
7712                                 l2_tunnel->l2_tunnel_type);
7713         }
7714
7715         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7716                 if (en)
7717                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7718                                 dev,
7719                                 l2_tunnel);
7720                 else
7721                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7722                                 dev,
7723                                 l2_tunnel);
7724         }
7725
7726         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7727                 if (en)
7728                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7729                                 dev,
7730                                 l2_tunnel->l2_tunnel_type);
7731                 else
7732                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7733                                 dev,
7734                                 l2_tunnel->l2_tunnel_type);
7735         }
7736
7737         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7738                 if (en)
7739                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7740                                 dev,
7741                                 l2_tunnel->l2_tunnel_type);
7742                 else
7743                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7744                                 dev,
7745                                 l2_tunnel->l2_tunnel_type);
7746         }
7747
7748         return ret;
7749 }
7750
7751 static int
7752 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7753                         uint16_t port)
7754 {
7755         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7756         IXGBE_WRITE_FLUSH(hw);
7757
7758         return 0;
7759 }
7760
7761 /* There's only one register for VxLAN UDP port.
7762  * So, we cannot add several ports. Will update it.
7763  */
7764 static int
7765 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7766                      uint16_t port)
7767 {
7768         if (port == 0) {
7769                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7770                 return -EINVAL;
7771         }
7772
7773         return ixgbe_update_vxlan_port(hw, port);
7774 }
7775
7776 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7777  * UDP port, it must have a value.
7778  * So, will reset it to the original value 0.
7779  */
7780 static int
7781 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7782                      uint16_t port)
7783 {
7784         uint16_t cur_port;
7785
7786         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7787
7788         if (cur_port != port) {
7789                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7790                 return -EINVAL;
7791         }
7792
7793         return ixgbe_update_vxlan_port(hw, 0);
7794 }
7795
7796 /* Add UDP tunneling port */
7797 static int
7798 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7799                               struct rte_eth_udp_tunnel *udp_tunnel)
7800 {
7801         int ret = 0;
7802         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7803
7804         if (hw->mac.type != ixgbe_mac_X550 &&
7805             hw->mac.type != ixgbe_mac_X550EM_x &&
7806             hw->mac.type != ixgbe_mac_X550EM_a) {
7807                 return -ENOTSUP;
7808         }
7809
7810         if (udp_tunnel == NULL)
7811                 return -EINVAL;
7812
7813         switch (udp_tunnel->prot_type) {
7814         case RTE_TUNNEL_TYPE_VXLAN:
7815                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7816                 break;
7817
7818         case RTE_TUNNEL_TYPE_GENEVE:
7819         case RTE_TUNNEL_TYPE_TEREDO:
7820                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7821                 ret = -EINVAL;
7822                 break;
7823
7824         default:
7825                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7826                 ret = -EINVAL;
7827                 break;
7828         }
7829
7830         return ret;
7831 }
7832
7833 /* Remove UDP tunneling port */
7834 static int
7835 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7836                               struct rte_eth_udp_tunnel *udp_tunnel)
7837 {
7838         int ret = 0;
7839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7840
7841         if (hw->mac.type != ixgbe_mac_X550 &&
7842             hw->mac.type != ixgbe_mac_X550EM_x &&
7843             hw->mac.type != ixgbe_mac_X550EM_a) {
7844                 return -ENOTSUP;
7845         }
7846
7847         if (udp_tunnel == NULL)
7848                 return -EINVAL;
7849
7850         switch (udp_tunnel->prot_type) {
7851         case RTE_TUNNEL_TYPE_VXLAN:
7852                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7853                 break;
7854         case RTE_TUNNEL_TYPE_GENEVE:
7855         case RTE_TUNNEL_TYPE_TEREDO:
7856                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7857                 ret = -EINVAL;
7858                 break;
7859         default:
7860                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7861                 ret = -EINVAL;
7862                 break;
7863         }
7864
7865         return ret;
7866 }
7867
7868 static void
7869 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7870 {
7871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7872
7873         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7874 }
7875
7876 static void
7877 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7878 {
7879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7880
7881         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7882 }
7883
7884 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7885 {
7886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887         u32 in_msg = 0;
7888
7889         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7890                 return;
7891
7892         /* PF reset VF event */
7893         if (in_msg == IXGBE_PF_CONTROL_MSG)
7894                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7895 }
7896
7897 static int
7898 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7899 {
7900         uint32_t eicr;
7901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7902         struct ixgbe_interrupt *intr =
7903                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7904         ixgbevf_intr_disable(hw);
7905
7906         /* read-on-clear nic registers here */
7907         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7908         intr->flags = 0;
7909
7910         /* only one misc vector supported - mailbox */
7911         eicr &= IXGBE_VTEICR_MASK;
7912         if (eicr == IXGBE_MISC_VEC_ID)
7913                 intr->flags |= IXGBE_FLAG_MAILBOX;
7914
7915         return 0;
7916 }
7917
7918 static int
7919 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7920 {
7921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7922         struct ixgbe_interrupt *intr =
7923                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7924
7925         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7926                 ixgbevf_mbx_process(dev);
7927                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7928         }
7929
7930         ixgbevf_intr_enable(hw);
7931
7932         return 0;
7933 }
7934
7935 static void
7936 ixgbevf_dev_interrupt_handler(void *param)
7937 {
7938         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7939
7940         ixgbevf_dev_interrupt_get_status(dev);
7941         ixgbevf_dev_interrupt_action(dev);
7942 }
7943
7944 /**
7945  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7946  *  @hw: pointer to hardware structure
7947  *
7948  *  Stops the transmit data path and waits for the HW to internally empty
7949  *  the Tx security block
7950  **/
7951 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7952 {
7953 #define IXGBE_MAX_SECTX_POLL 40
7954
7955         int i;
7956         int sectxreg;
7957
7958         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7959         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7960         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7961         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7962                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7963                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7964                         break;
7965                 /* Use interrupt-safe sleep just in case */
7966                 usec_delay(1000);
7967         }
7968
7969         /* For informational purposes only */
7970         if (i >= IXGBE_MAX_SECTX_POLL)
7971                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7972                          "path fully disabled.  Continuing with init.");
7973
7974         return IXGBE_SUCCESS;
7975 }
7976
7977 /**
7978  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7979  *  @hw: pointer to hardware structure
7980  *
7981  *  Enables the transmit data path.
7982  **/
7983 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7984 {
7985         uint32_t sectxreg;
7986
7987         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7988         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7989         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7990         IXGBE_WRITE_FLUSH(hw);
7991
7992         return IXGBE_SUCCESS;
7993 }
7994
7995 /* restore n-tuple filter */
7996 static inline void
7997 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7998 {
7999         struct ixgbe_filter_info *filter_info =
8000                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8001         struct ixgbe_5tuple_filter *node;
8002
8003         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8004                 ixgbe_inject_5tuple_filter(dev, node);
8005         }
8006 }
8007
8008 /* restore ethernet type filter */
8009 static inline void
8010 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8011 {
8012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8013         struct ixgbe_filter_info *filter_info =
8014                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8015         int i;
8016
8017         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8018                 if (filter_info->ethertype_mask & (1 << i)) {
8019                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8020                                         filter_info->ethertype_filters[i].etqf);
8021                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8022                                         filter_info->ethertype_filters[i].etqs);
8023                         IXGBE_WRITE_FLUSH(hw);
8024                 }
8025         }
8026 }
8027
8028 /* restore SYN filter */
8029 static inline void
8030 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8031 {
8032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8033         struct ixgbe_filter_info *filter_info =
8034                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8035         uint32_t synqf;
8036
8037         synqf = filter_info->syn_info;
8038
8039         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8040                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8041                 IXGBE_WRITE_FLUSH(hw);
8042         }
8043 }
8044
8045 /* restore L2 tunnel filter */
8046 static inline void
8047 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8048 {
8049         struct ixgbe_l2_tn_info *l2_tn_info =
8050                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8051         struct ixgbe_l2_tn_filter *node;
8052         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8053
8054         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8055                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8056                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8057                 l2_tn_conf.pool           = node->pool;
8058                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8059         }
8060 }
8061
8062 static int
8063 ixgbe_filter_restore(struct rte_eth_dev *dev)
8064 {
8065         ixgbe_ntuple_filter_restore(dev);
8066         ixgbe_ethertype_filter_restore(dev);
8067         ixgbe_syn_filter_restore(dev);
8068         ixgbe_fdir_filter_restore(dev);
8069         ixgbe_l2_tn_filter_restore(dev);
8070
8071         return 0;
8072 }
8073
8074 static void
8075 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8076 {
8077         struct ixgbe_l2_tn_info *l2_tn_info =
8078                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8080
8081         if (l2_tn_info->e_tag_en)
8082                 (void)ixgbe_e_tag_enable(hw);
8083
8084         if (l2_tn_info->e_tag_fwd_en)
8085                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8086
8087         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8088 }
8089
8090 /* remove all the n-tuple filters */
8091 void
8092 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8093 {
8094         struct ixgbe_filter_info *filter_info =
8095                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8096         struct ixgbe_5tuple_filter *p_5tuple;
8097
8098         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8099                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8100 }
8101
8102 /* remove all the ether type filters */
8103 void
8104 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8105 {
8106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8107         struct ixgbe_filter_info *filter_info =
8108                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8109         int i;
8110
8111         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8112                 if (filter_info->ethertype_mask & (1 << i) &&
8113                     !filter_info->ethertype_filters[i].conf) {
8114                         (void)ixgbe_ethertype_filter_remove(filter_info,
8115                                                             (uint8_t)i);
8116                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8117                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8118                         IXGBE_WRITE_FLUSH(hw);
8119                 }
8120         }
8121 }
8122
8123 /* remove the SYN filter */
8124 void
8125 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8126 {
8127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8128         struct ixgbe_filter_info *filter_info =
8129                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8130
8131         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8132                 filter_info->syn_info = 0;
8133
8134                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8135                 IXGBE_WRITE_FLUSH(hw);
8136         }
8137 }
8138
8139 /* remove all the L2 tunnel filters */
8140 int
8141 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8142 {
8143         struct ixgbe_l2_tn_info *l2_tn_info =
8144                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8145         struct ixgbe_l2_tn_filter *l2_tn_filter;
8146         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8147         int ret = 0;
8148
8149         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8150                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8151                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8152                 l2_tn_conf.pool           = l2_tn_filter->pool;
8153                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8154                 if (ret < 0)
8155                         return ret;
8156         }
8157
8158         return 0;
8159 }
8160
8161 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8162 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8163 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8164 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8165 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8166 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");