4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
75 #include "rte_pmd_ixgbe.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 enum ixgbevf_xcast_modes {
158 IXGBEVF_XCAST_MODE_NONE = 0,
159 IXGBEVF_XCAST_MODE_MULTI,
160 IXGBEVF_XCAST_MODE_ALLMULTI,
163 #define IXGBE_EXVET_VET_EXT_SHIFT 16
164 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
168 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
169 static int ixgbe_dev_start(struct rte_eth_dev *dev);
170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
172 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
189 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
197 struct rte_eth_dev_info *dev_info);
198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
200 struct rte_eth_dev_info *dev_info);
201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
204 uint16_t vlan_id, int on);
205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
206 enum rte_vlan_type vlan_type,
208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
209 uint16_t queue, bool on);
210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
221 struct rte_eth_fc_conf *fc_conf);
222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
223 struct rte_eth_fc_conf *fc_conf);
224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
225 struct rte_eth_pfc_conf *pfc_conf);
226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
227 struct rte_eth_rss_reta_entry64 *reta_conf,
229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
230 struct rte_eth_rss_reta_entry64 *reta_conf,
232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
237 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
239 static void ixgbe_dev_interrupt_delayed_handler(void *param);
240 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
241 uint32_t index, uint32_t pool);
242 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
243 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
244 struct ether_addr *mac_addr);
245 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
247 /* For Virtual Function support */
248 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
249 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
250 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
251 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
253 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
255 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
256 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
264 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
265 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
267 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
269 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
270 uint8_t queue, uint8_t msix_vector);
271 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
272 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
273 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
275 /* For Eth VMDQ APIs support */
276 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
277 ether_addr * mac_addr, uint8_t on);
278 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
279 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
280 uint16_t rx_mask, uint8_t on);
281 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
282 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
283 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
284 uint64_t pool_mask, uint8_t vlan_on);
285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
286 struct rte_eth_mirror_conf *mirror_conf,
287 uint8_t rule_id, uint8_t on);
288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
295 uint8_t queue, uint8_t msix_vector);
296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
299 uint16_t queue_idx, uint16_t tx_rate);
300 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
301 uint16_t tx_rate, uint64_t q_msk);
303 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
304 struct ether_addr *mac_addr,
305 uint32_t index, uint32_t pool);
306 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
307 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
308 struct ether_addr *mac_addr);
309 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
310 struct rte_eth_syn_filter *filter,
312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
322 struct rte_eth_ntuple_filter *filter,
324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ntuple_filter *filter);
329 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter,
332 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
333 enum rte_filter_op filter_op,
335 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
336 struct rte_eth_ethertype_filter *filter);
337 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
338 enum rte_filter_type filter_type,
339 enum rte_filter_op filter_op,
341 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
343 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
344 struct ether_addr *mc_addr_set,
345 uint32_t nb_mc_addr);
346 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
347 struct rte_eth_dcb_info *dcb_info);
349 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
350 static int ixgbe_get_regs(struct rte_eth_dev *dev,
351 struct rte_dev_reg_info *regs);
352 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
353 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
354 struct rte_dev_eeprom_info *eeprom);
355 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
356 struct rte_dev_eeprom_info *eeprom);
358 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
359 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
360 struct rte_dev_reg_info *regs);
362 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
363 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
364 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
365 struct timespec *timestamp,
367 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
368 struct timespec *timestamp);
369 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
370 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
371 struct timespec *timestamp);
372 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
373 const struct timespec *timestamp);
374 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
377 static int ixgbe_dev_l2_tunnel_eth_type_conf
378 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
379 static int ixgbe_dev_l2_tunnel_offload_set
380 (struct rte_eth_dev *dev,
381 struct rte_eth_l2_tunnel_conf *l2_tunnel,
384 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
385 enum rte_filter_op filter_op,
388 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
389 struct rte_eth_udp_tunnel *udp_tunnel);
390 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
391 struct rte_eth_udp_tunnel *udp_tunnel);
394 * Define VF Stats MACRO for Non "cleared on read" register
396 #define UPDATE_VF_STAT(reg, last, cur) \
398 uint32_t latest = IXGBE_READ_REG(hw, reg); \
399 cur += (latest - last) & UINT_MAX; \
403 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
405 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
406 u64 new_msb = IXGBE_READ_REG(hw, msb); \
407 u64 latest = ((new_msb << 32) | new_lsb); \
408 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
412 #define IXGBE_SET_HWSTRIP(h, q) do {\
413 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
415 (h)->bitmap[idx] |= 1 << bit;\
418 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
419 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
420 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
421 (h)->bitmap[idx] &= ~(1 << bit);\
424 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
425 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
426 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
427 (r) = (h)->bitmap[idx] >> bit & 1;\
431 * The set of PCI devices this driver supports
433 static const struct rte_pci_id pci_id_ixgbe_map[] = {
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
487 #ifdef RTE_NIC_BYPASS
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
490 { .vendor_id = 0, /* sentinel */ },
494 * The set of PCI devices this driver supports (for 82599 VF)
496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
507 { .vendor_id = 0, /* sentinel */ },
510 static const struct rte_eth_desc_lim rx_desc_lim = {
511 .nb_max = IXGBE_MAX_RING_DESC,
512 .nb_min = IXGBE_MIN_RING_DESC,
513 .nb_align = IXGBE_RXD_ALIGN,
516 static const struct rte_eth_desc_lim tx_desc_lim = {
517 .nb_max = IXGBE_MAX_RING_DESC,
518 .nb_min = IXGBE_MIN_RING_DESC,
519 .nb_align = IXGBE_TXD_ALIGN,
522 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
523 .dev_configure = ixgbe_dev_configure,
524 .dev_start = ixgbe_dev_start,
525 .dev_stop = ixgbe_dev_stop,
526 .dev_set_link_up = ixgbe_dev_set_link_up,
527 .dev_set_link_down = ixgbe_dev_set_link_down,
528 .dev_close = ixgbe_dev_close,
529 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
530 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
531 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
532 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
533 .link_update = ixgbe_dev_link_update,
534 .stats_get = ixgbe_dev_stats_get,
535 .xstats_get = ixgbe_dev_xstats_get,
536 .stats_reset = ixgbe_dev_stats_reset,
537 .xstats_reset = ixgbe_dev_xstats_reset,
538 .xstats_get_names = ixgbe_dev_xstats_get_names,
539 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
540 .dev_infos_get = ixgbe_dev_info_get,
541 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
542 .mtu_set = ixgbe_dev_mtu_set,
543 .vlan_filter_set = ixgbe_vlan_filter_set,
544 .vlan_tpid_set = ixgbe_vlan_tpid_set,
545 .vlan_offload_set = ixgbe_vlan_offload_set,
546 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
547 .rx_queue_start = ixgbe_dev_rx_queue_start,
548 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
549 .tx_queue_start = ixgbe_dev_tx_queue_start,
550 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
551 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
552 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
553 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
554 .rx_queue_release = ixgbe_dev_rx_queue_release,
555 .rx_queue_count = ixgbe_dev_rx_queue_count,
556 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
557 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
558 .tx_queue_release = ixgbe_dev_tx_queue_release,
559 .dev_led_on = ixgbe_dev_led_on,
560 .dev_led_off = ixgbe_dev_led_off,
561 .flow_ctrl_get = ixgbe_flow_ctrl_get,
562 .flow_ctrl_set = ixgbe_flow_ctrl_set,
563 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
564 .mac_addr_add = ixgbe_add_rar,
565 .mac_addr_remove = ixgbe_remove_rar,
566 .mac_addr_set = ixgbe_set_default_mac_addr,
567 .uc_hash_table_set = ixgbe_uc_hash_table_set,
568 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
569 .mirror_rule_set = ixgbe_mirror_rule_set,
570 .mirror_rule_reset = ixgbe_mirror_rule_reset,
571 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
572 .set_vf_rx = ixgbe_set_pool_rx,
573 .set_vf_tx = ixgbe_set_pool_tx,
574 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
575 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
576 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
577 .reta_update = ixgbe_dev_rss_reta_update,
578 .reta_query = ixgbe_dev_rss_reta_query,
579 #ifdef RTE_NIC_BYPASS
580 .bypass_init = ixgbe_bypass_init,
581 .bypass_state_set = ixgbe_bypass_state_store,
582 .bypass_state_show = ixgbe_bypass_state_show,
583 .bypass_event_set = ixgbe_bypass_event_store,
584 .bypass_event_show = ixgbe_bypass_event_show,
585 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
586 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
587 .bypass_ver_show = ixgbe_bypass_ver_show,
588 .bypass_wd_reset = ixgbe_bypass_wd_reset,
589 #endif /* RTE_NIC_BYPASS */
590 .rss_hash_update = ixgbe_dev_rss_hash_update,
591 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
592 .filter_ctrl = ixgbe_dev_filter_ctrl,
593 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
594 .rxq_info_get = ixgbe_rxq_info_get,
595 .txq_info_get = ixgbe_txq_info_get,
596 .timesync_enable = ixgbe_timesync_enable,
597 .timesync_disable = ixgbe_timesync_disable,
598 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
599 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
600 .get_reg = ixgbe_get_regs,
601 .get_eeprom_length = ixgbe_get_eeprom_length,
602 .get_eeprom = ixgbe_get_eeprom,
603 .set_eeprom = ixgbe_set_eeprom,
604 .get_dcb_info = ixgbe_dev_get_dcb_info,
605 .timesync_adjust_time = ixgbe_timesync_adjust_time,
606 .timesync_read_time = ixgbe_timesync_read_time,
607 .timesync_write_time = ixgbe_timesync_write_time,
608 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
609 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
610 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
611 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
615 * dev_ops for virtual function, bare necessities for basic vf
616 * operation have been implemented
618 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
619 .dev_configure = ixgbevf_dev_configure,
620 .dev_start = ixgbevf_dev_start,
621 .dev_stop = ixgbevf_dev_stop,
622 .link_update = ixgbe_dev_link_update,
623 .stats_get = ixgbevf_dev_stats_get,
624 .xstats_get = ixgbevf_dev_xstats_get,
625 .stats_reset = ixgbevf_dev_stats_reset,
626 .xstats_reset = ixgbevf_dev_stats_reset,
627 .xstats_get_names = ixgbevf_dev_xstats_get_names,
628 .dev_close = ixgbevf_dev_close,
629 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
630 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
631 .dev_infos_get = ixgbevf_dev_info_get,
632 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
633 .mtu_set = ixgbevf_dev_set_mtu,
634 .vlan_filter_set = ixgbevf_vlan_filter_set,
635 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
636 .vlan_offload_set = ixgbevf_vlan_offload_set,
637 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
638 .rx_queue_release = ixgbe_dev_rx_queue_release,
639 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
640 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
641 .tx_queue_release = ixgbe_dev_tx_queue_release,
642 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
643 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
644 .mac_addr_add = ixgbevf_add_mac_addr,
645 .mac_addr_remove = ixgbevf_remove_mac_addr,
646 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
647 .rxq_info_get = ixgbe_rxq_info_get,
648 .txq_info_get = ixgbe_txq_info_get,
649 .mac_addr_set = ixgbevf_set_default_mac_addr,
650 .get_reg = ixgbevf_get_regs,
651 .reta_update = ixgbe_dev_rss_reta_update,
652 .reta_query = ixgbe_dev_rss_reta_query,
653 .rss_hash_update = ixgbe_dev_rss_hash_update,
654 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
657 /* store statistics names and its offset in stats structure */
658 struct rte_ixgbe_xstats_name_off {
659 char name[RTE_ETH_XSTATS_NAME_SIZE];
663 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
664 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
665 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
666 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
667 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
668 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
669 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
670 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
671 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
672 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
673 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
674 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
675 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
676 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
677 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
678 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
680 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
682 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
683 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
684 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
685 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
686 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
687 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
688 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
689 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
690 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
691 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
692 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
693 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
694 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
695 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
696 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
697 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
698 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
700 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
702 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
703 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
704 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
705 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
707 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
709 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
711 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
713 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
715 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
717 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
720 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
721 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
722 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
724 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
725 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
726 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
727 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
728 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
730 {"rx_fcoe_no_direct_data_placement_ext_buff",
731 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
733 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
735 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
737 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
739 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
741 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
744 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
745 sizeof(rte_ixgbe_stats_strings[0]))
747 /* Per-queue statistics */
748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
749 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
750 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
751 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
752 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
755 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
756 sizeof(rte_ixgbe_rxq_strings[0]))
757 #define IXGBE_NB_RXQ_PRIO_VALUES 8
759 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
760 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
761 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
762 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
766 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
767 sizeof(rte_ixgbe_txq_strings[0]))
768 #define IXGBE_NB_TXQ_PRIO_VALUES 8
770 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
771 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
774 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
775 sizeof(rte_ixgbevf_stats_strings[0]))
778 * Atomically reads the link status information from global
779 * structure rte_eth_dev.
782 * - Pointer to the structure rte_eth_dev to read from.
783 * - Pointer to the buffer to be saved with the link status.
786 * - On success, zero.
787 * - On failure, negative value.
790 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
791 struct rte_eth_link *link)
793 struct rte_eth_link *dst = link;
794 struct rte_eth_link *src = &(dev->data->dev_link);
796 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
797 *(uint64_t *)src) == 0)
804 * Atomically writes the link status information into global
805 * structure rte_eth_dev.
808 * - Pointer to the structure rte_eth_dev to read from.
809 * - Pointer to the buffer to be saved with the link status.
812 * - On success, zero.
813 * - On failure, negative value.
816 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
817 struct rte_eth_link *link)
819 struct rte_eth_link *dst = &(dev->data->dev_link);
820 struct rte_eth_link *src = link;
822 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
823 *(uint64_t *)src) == 0)
830 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
833 ixgbe_is_sfp(struct ixgbe_hw *hw)
835 switch (hw->phy.type) {
836 case ixgbe_phy_sfp_avago:
837 case ixgbe_phy_sfp_ftl:
838 case ixgbe_phy_sfp_intel:
839 case ixgbe_phy_sfp_unknown:
840 case ixgbe_phy_sfp_passive_tyco:
841 case ixgbe_phy_sfp_passive_unknown:
848 static inline int32_t
849 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
854 status = ixgbe_reset_hw(hw);
856 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
857 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
858 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
859 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
860 IXGBE_WRITE_FLUSH(hw);
866 ixgbe_enable_intr(struct rte_eth_dev *dev)
868 struct ixgbe_interrupt *intr =
869 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
870 struct ixgbe_hw *hw =
871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
874 IXGBE_WRITE_FLUSH(hw);
878 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
881 ixgbe_disable_intr(struct ixgbe_hw *hw)
883 PMD_INIT_FUNC_TRACE();
885 if (hw->mac.type == ixgbe_mac_82598EB) {
886 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
888 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
889 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
890 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
892 IXGBE_WRITE_FLUSH(hw);
896 * This function resets queue statistics mapping registers.
897 * From Niantic datasheet, Initialization of Statistics section:
898 * "...if software requires the queue counters, the RQSMR and TQSM registers
899 * must be re-programmed following a device reset.
902 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
906 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
907 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
908 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
914 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
919 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
920 #define NB_QMAP_FIELDS_PER_QSM_REG 4
921 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
923 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
924 struct ixgbe_stat_mapping_registers *stat_mappings =
925 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
926 uint32_t qsmr_mask = 0;
927 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
931 if ((hw->mac.type != ixgbe_mac_82599EB) &&
932 (hw->mac.type != ixgbe_mac_X540) &&
933 (hw->mac.type != ixgbe_mac_X550) &&
934 (hw->mac.type != ixgbe_mac_X550EM_x) &&
935 (hw->mac.type != ixgbe_mac_X550EM_a))
938 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
939 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
942 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
943 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
944 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
947 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
949 /* Now clear any previous stat_idx set */
950 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
952 stat_mappings->tqsm[n] &= ~clearing_mask;
954 stat_mappings->rqsmr[n] &= ~clearing_mask;
956 q_map = (uint32_t)stat_idx;
957 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
958 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
960 stat_mappings->tqsm[n] |= qsmr_mask;
962 stat_mappings->rqsmr[n] |= qsmr_mask;
964 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
965 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
967 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
968 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
970 /* Now write the mapping in the appropriate register */
972 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
973 stat_mappings->rqsmr[n], n);
974 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
976 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
977 stat_mappings->tqsm[n], n);
978 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
984 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
986 struct ixgbe_stat_mapping_registers *stat_mappings =
987 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
991 /* write whatever was in stat mapping table to the NIC */
992 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
994 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
997 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1002 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1005 struct ixgbe_dcb_tc_config *tc;
1006 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1008 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1009 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1010 for (i = 0; i < dcb_max_tc; i++) {
1011 tc = &dcb_config->tc_config[i];
1012 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1013 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1014 (uint8_t)(100/dcb_max_tc + (i & 1));
1015 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1016 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1017 (uint8_t)(100/dcb_max_tc + (i & 1));
1018 tc->pfc = ixgbe_dcb_pfc_disabled;
1021 /* Initialize default user to priority mapping, UPx->TC0 */
1022 tc = &dcb_config->tc_config[0];
1023 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1024 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1025 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1026 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1027 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1029 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1030 dcb_config->pfc_mode_enable = false;
1031 dcb_config->vt_mode = true;
1032 dcb_config->round_robin_enable = false;
1033 /* support all DCB capabilities in 82599 */
1034 dcb_config->support.capabilities = 0xFF;
1036 /*we only support 4 Tcs for X540, X550 */
1037 if (hw->mac.type == ixgbe_mac_X540 ||
1038 hw->mac.type == ixgbe_mac_X550 ||
1039 hw->mac.type == ixgbe_mac_X550EM_x ||
1040 hw->mac.type == ixgbe_mac_X550EM_a) {
1041 dcb_config->num_tcs.pg_tcs = 4;
1042 dcb_config->num_tcs.pfc_tcs = 4;
1047 * Ensure that all locks are released before first NVM or PHY access
1050 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1055 * Phy lock should not fail in this early stage. If this is the case,
1056 * it is due to an improper exit of the application.
1057 * So force the release of the faulty lock. Release of common lock
1058 * is done automatically by swfw_sync function.
1060 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1061 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1062 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1064 ixgbe_release_swfw_semaphore(hw, mask);
1067 * These ones are more tricky since they are common to all ports; but
1068 * swfw_sync retries last long enough (1s) to be almost sure that if
1069 * lock can not be taken it is due to an improper lock of the
1072 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1073 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1074 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1076 ixgbe_release_swfw_semaphore(hw, mask);
1080 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1081 * It returns 0 on success.
1084 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1086 struct rte_pci_device *pci_dev;
1087 struct ixgbe_hw *hw =
1088 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1089 struct ixgbe_vfta *shadow_vfta =
1090 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1091 struct ixgbe_hwstrip *hwstrip =
1092 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1093 struct ixgbe_dcb_config *dcb_config =
1094 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1095 struct ixgbe_filter_info *filter_info =
1096 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1101 PMD_INIT_FUNC_TRACE();
1103 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1104 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1105 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108 * For secondary processes, we don't initialise any further as primary
1109 * has already done this work. Only check we don't need a different
1110 * RX and TX function.
1112 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1113 struct ixgbe_tx_queue *txq;
1114 /* TX queue function in primary, set by last queue initialized
1115 * Tx queue may not initialized by primary process
1117 if (eth_dev->data->tx_queues) {
1118 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1119 ixgbe_set_tx_function(eth_dev, txq);
1121 /* Use default TX function if we get here */
1122 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1123 "Using default TX function.");
1126 ixgbe_set_rx_function(eth_dev);
1130 pci_dev = eth_dev->pci_dev;
1132 rte_eth_copy_pci_info(eth_dev, pci_dev);
1134 /* Vendor and Device ID need to be set before init of shared code */
1135 hw->device_id = pci_dev->id.device_id;
1136 hw->vendor_id = pci_dev->id.vendor_id;
1137 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1138 hw->allow_unsupported_sfp = 1;
1140 /* Initialize the shared code (base driver) */
1141 #ifdef RTE_NIC_BYPASS
1142 diag = ixgbe_bypass_init_shared_code(hw);
1144 diag = ixgbe_init_shared_code(hw);
1145 #endif /* RTE_NIC_BYPASS */
1147 if (diag != IXGBE_SUCCESS) {
1148 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1152 /* pick up the PCI bus settings for reporting later */
1153 ixgbe_get_bus_info(hw);
1155 /* Unlock any pending hardware semaphore */
1156 ixgbe_swfw_lock_reset(hw);
1158 /* Initialize DCB configuration*/
1159 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1160 ixgbe_dcb_init(hw, dcb_config);
1161 /* Get Hardware Flow Control setting */
1162 hw->fc.requested_mode = ixgbe_fc_full;
1163 hw->fc.current_mode = ixgbe_fc_full;
1164 hw->fc.pause_time = IXGBE_FC_PAUSE;
1165 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1166 hw->fc.low_water[i] = IXGBE_FC_LO;
1167 hw->fc.high_water[i] = IXGBE_FC_HI;
1169 hw->fc.send_xon = 1;
1171 /* Make sure we have a good EEPROM before we read from it */
1172 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1173 if (diag != IXGBE_SUCCESS) {
1174 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1178 #ifdef RTE_NIC_BYPASS
1179 diag = ixgbe_bypass_init_hw(hw);
1181 diag = ixgbe_init_hw(hw);
1182 #endif /* RTE_NIC_BYPASS */
1185 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1186 * is called too soon after the kernel driver unbinding/binding occurs.
1187 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1188 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1189 * also called. See ixgbe_identify_phy_82599(). The reason for the
1190 * failure is not known, and only occuts when virtualisation features
1191 * are disabled in the bios. A delay of 100ms was found to be enough by
1192 * trial-and-error, and is doubled to be safe.
1194 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1196 diag = ixgbe_init_hw(hw);
1199 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1200 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1201 "LOM. Please be aware there may be issues associated "
1202 "with your hardware.");
1203 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1204 "please contact your Intel or hardware representative "
1205 "who provided you with this hardware.");
1206 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1207 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1209 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1213 /* Reset the hw statistics */
1214 ixgbe_dev_stats_reset(eth_dev);
1216 /* disable interrupt */
1217 ixgbe_disable_intr(hw);
1219 /* reset mappings for queue statistics hw counters*/
1220 ixgbe_reset_qstat_mappings(hw);
1222 /* Allocate memory for storing MAC addresses */
1223 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1224 hw->mac.num_rar_entries, 0);
1225 if (eth_dev->data->mac_addrs == NULL) {
1227 "Failed to allocate %u bytes needed to store "
1229 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1232 /* Copy the permanent MAC address */
1233 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1234 ð_dev->data->mac_addrs[0]);
1236 /* Allocate memory for storing hash filter MAC addresses */
1237 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1238 IXGBE_VMDQ_NUM_UC_MAC, 0);
1239 if (eth_dev->data->hash_mac_addrs == NULL) {
1241 "Failed to allocate %d bytes needed to store MAC addresses",
1242 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1246 /* initialize the vfta */
1247 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249 /* initialize the hw strip bitmap*/
1250 memset(hwstrip, 0, sizeof(*hwstrip));
1252 /* initialize PF if max_vfs not zero */
1253 ixgbe_pf_host_init(eth_dev);
1255 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1256 /* let hardware know driver is loaded */
1257 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1258 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1259 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1260 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1261 IXGBE_WRITE_FLUSH(hw);
1263 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1264 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1265 (int) hw->mac.type, (int) hw->phy.type,
1266 (int) hw->phy.sfp_type);
1268 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1269 (int) hw->mac.type, (int) hw->phy.type);
1271 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1272 eth_dev->data->port_id, pci_dev->id.vendor_id,
1273 pci_dev->id.device_id);
1275 rte_intr_callback_register(&pci_dev->intr_handle,
1276 ixgbe_dev_interrupt_handler,
1279 /* enable uio/vfio intr/eventfd mapping */
1280 rte_intr_enable(&pci_dev->intr_handle);
1282 /* enable support intr */
1283 ixgbe_enable_intr(eth_dev);
1285 /* initialize 5tuple filter list */
1286 TAILQ_INIT(&filter_info->fivetuple_list);
1287 memset(filter_info->fivetuple_mask, 0,
1288 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1296 struct rte_pci_device *pci_dev;
1297 struct ixgbe_hw *hw;
1299 PMD_INIT_FUNC_TRACE();
1301 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1304 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1305 pci_dev = eth_dev->pci_dev;
1307 if (hw->adapter_stopped == 0)
1308 ixgbe_dev_close(eth_dev);
1310 eth_dev->dev_ops = NULL;
1311 eth_dev->rx_pkt_burst = NULL;
1312 eth_dev->tx_pkt_burst = NULL;
1314 /* Unlock any pending hardware semaphore */
1315 ixgbe_swfw_lock_reset(hw);
1317 /* disable uio intr before callback unregister */
1318 rte_intr_disable(&(pci_dev->intr_handle));
1319 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1320 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1322 /* uninitialize PF if max_vfs not zero */
1323 ixgbe_pf_host_uninit(eth_dev);
1325 rte_free(eth_dev->data->mac_addrs);
1326 eth_dev->data->mac_addrs = NULL;
1328 rte_free(eth_dev->data->hash_mac_addrs);
1329 eth_dev->data->hash_mac_addrs = NULL;
1335 * Negotiate mailbox API version with the PF.
1336 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337 * Then we try to negotiate starting with the most recent one.
1338 * If all negotiation attempts fail, then we will proceed with
1339 * the default one (ixgbe_mbox_api_10).
1342 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1346 /* start with highest supported, proceed down */
1347 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1354 i != RTE_DIM(sup_ver) &&
1355 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1361 generate_random_mac_addr(struct ether_addr *mac_addr)
1365 /* Set Organizationally Unique Identifier (OUI) prefix. */
1366 mac_addr->addr_bytes[0] = 0x00;
1367 mac_addr->addr_bytes[1] = 0x09;
1368 mac_addr->addr_bytes[2] = 0xC0;
1369 /* Force indication of locally assigned MAC address. */
1370 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371 /* Generate the last 3 bytes of the MAC address with a random number. */
1372 random = rte_rand();
1373 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1377 * Virtual Function device init
1380 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1384 struct rte_pci_device *pci_dev;
1385 struct ixgbe_hw *hw =
1386 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1387 struct ixgbe_vfta *shadow_vfta =
1388 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1389 struct ixgbe_hwstrip *hwstrip =
1390 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1391 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1393 PMD_INIT_FUNC_TRACE();
1395 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1396 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1397 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1399 /* for secondary processes, we don't initialise any further as primary
1400 * has already done this work. Only check we don't need a different
1403 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1404 struct ixgbe_tx_queue *txq;
1405 /* TX queue function in primary, set by last queue initialized
1406 * Tx queue may not initialized by primary process
1408 if (eth_dev->data->tx_queues) {
1409 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1410 ixgbe_set_tx_function(eth_dev, txq);
1412 /* Use default TX function if we get here */
1413 PMD_INIT_LOG(NOTICE,
1414 "No TX queues configured yet. Using default TX function.");
1417 ixgbe_set_rx_function(eth_dev);
1422 pci_dev = eth_dev->pci_dev;
1424 rte_eth_copy_pci_info(eth_dev, pci_dev);
1426 hw->device_id = pci_dev->id.device_id;
1427 hw->vendor_id = pci_dev->id.vendor_id;
1428 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1430 /* initialize the vfta */
1431 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1433 /* initialize the hw strip bitmap*/
1434 memset(hwstrip, 0, sizeof(*hwstrip));
1436 /* Initialize the shared code (base driver) */
1437 diag = ixgbe_init_shared_code(hw);
1438 if (diag != IXGBE_SUCCESS) {
1439 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1443 /* init_mailbox_params */
1444 hw->mbx.ops.init_params(hw);
1446 /* Reset the hw statistics */
1447 ixgbevf_dev_stats_reset(eth_dev);
1449 /* Disable the interrupts for VF */
1450 ixgbevf_intr_disable(hw);
1452 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1453 diag = hw->mac.ops.reset_hw(hw);
1456 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1457 * the underlying PF driver has not assigned a MAC address to the VF.
1458 * In this case, assign a random MAC address.
1460 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1461 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1465 /* negotiate mailbox API version to use with the PF. */
1466 ixgbevf_negotiate_api(hw);
1468 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1469 ixgbevf_get_queues(hw, &tcs, &tc);
1471 /* Allocate memory for storing MAC addresses */
1472 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1473 hw->mac.num_rar_entries, 0);
1474 if (eth_dev->data->mac_addrs == NULL) {
1476 "Failed to allocate %u bytes needed to store "
1478 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1482 /* Generate a random MAC address, if none was assigned by PF. */
1483 if (is_zero_ether_addr(perm_addr)) {
1484 generate_random_mac_addr(perm_addr);
1485 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1487 rte_free(eth_dev->data->mac_addrs);
1488 eth_dev->data->mac_addrs = NULL;
1491 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1492 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1493 "%02x:%02x:%02x:%02x:%02x:%02x",
1494 perm_addr->addr_bytes[0],
1495 perm_addr->addr_bytes[1],
1496 perm_addr->addr_bytes[2],
1497 perm_addr->addr_bytes[3],
1498 perm_addr->addr_bytes[4],
1499 perm_addr->addr_bytes[5]);
1502 /* Copy the permanent MAC address */
1503 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1505 /* reset the hardware with the new settings */
1506 diag = hw->mac.ops.start_hw(hw);
1512 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1516 rte_intr_callback_register(&pci_dev->intr_handle,
1517 ixgbevf_dev_interrupt_handler,
1519 rte_intr_enable(&pci_dev->intr_handle);
1520 ixgbevf_intr_enable(hw);
1522 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1523 eth_dev->data->port_id, pci_dev->id.vendor_id,
1524 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1529 /* Virtual Function device uninit */
1532 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1534 struct ixgbe_hw *hw;
1535 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1537 PMD_INIT_FUNC_TRACE();
1539 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1542 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544 if (hw->adapter_stopped == 0)
1545 ixgbevf_dev_close(eth_dev);
1547 eth_dev->dev_ops = NULL;
1548 eth_dev->rx_pkt_burst = NULL;
1549 eth_dev->tx_pkt_burst = NULL;
1551 /* Disable the interrupts for VF */
1552 ixgbevf_intr_disable(hw);
1554 rte_free(eth_dev->data->mac_addrs);
1555 eth_dev->data->mac_addrs = NULL;
1557 rte_intr_disable(&pci_dev->intr_handle);
1558 rte_intr_callback_unregister(&pci_dev->intr_handle,
1559 ixgbevf_dev_interrupt_handler,
1565 static struct eth_driver rte_ixgbe_pmd = {
1567 .id_table = pci_id_ixgbe_map,
1568 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1569 RTE_PCI_DRV_DETACHABLE,
1570 .probe = rte_eth_dev_pci_probe,
1571 .remove = rte_eth_dev_pci_remove,
1573 .eth_dev_init = eth_ixgbe_dev_init,
1574 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1575 .dev_private_size = sizeof(struct ixgbe_adapter),
1579 * virtual function driver struct
1581 static struct eth_driver rte_ixgbevf_pmd = {
1583 .id_table = pci_id_ixgbevf_map,
1584 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1585 .probe = rte_eth_dev_pci_probe,
1586 .remove = rte_eth_dev_pci_remove,
1588 .eth_dev_init = eth_ixgbevf_dev_init,
1589 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1590 .dev_private_size = sizeof(struct ixgbe_adapter),
1594 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 struct ixgbe_vfta *shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1604 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1605 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1606 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1611 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1613 /* update local VFTA copy */
1614 shadow_vfta->vfta[vid_idx] = vfta;
1620 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1623 ixgbe_vlan_hw_strip_enable(dev, queue);
1625 ixgbe_vlan_hw_strip_disable(dev, queue);
1629 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1630 enum rte_vlan_type vlan_type,
1633 struct ixgbe_hw *hw =
1634 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1640 qinq &= IXGBE_DMATXCTL_GDV;
1642 switch (vlan_type) {
1643 case ETH_VLAN_TYPE_INNER:
1645 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1646 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1648 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1649 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1650 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1651 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1654 PMD_DRV_LOG(ERR, "Inner type is not supported"
1658 case ETH_VLAN_TYPE_OUTER:
1660 /* Only the high 16-bits is valid */
1661 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1662 IXGBE_EXVET_VET_EXT_SHIFT);
1664 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1676 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1684 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1686 struct ixgbe_hw *hw =
1687 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690 PMD_INIT_FUNC_TRACE();
1692 /* Filter Table Disable */
1693 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1696 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1700 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1702 struct ixgbe_hw *hw =
1703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 struct ixgbe_vfta *shadow_vfta =
1705 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1709 PMD_INIT_FUNC_TRACE();
1711 /* Filter Table Enable */
1712 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1714 vlnctrl |= IXGBE_VLNCTRL_VFE;
1716 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1718 /* write whatever is in local vfta copy */
1719 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1720 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1724 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1726 struct ixgbe_hwstrip *hwstrip =
1727 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1728 struct ixgbe_rx_queue *rxq;
1730 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1734 IXGBE_SET_HWSTRIP(hwstrip, queue);
1736 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1738 if (queue >= dev->data->nb_rx_queues)
1741 rxq = dev->data->rx_queues[queue];
1744 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1746 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1750 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1752 struct ixgbe_hw *hw =
1753 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 PMD_INIT_FUNC_TRACE();
1758 if (hw->mac.type == ixgbe_mac_82598EB) {
1759 /* No queue level support */
1760 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1764 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1765 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1766 ctrl &= ~IXGBE_RXDCTL_VME;
1767 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1769 /* record those setting for HW strip per queue */
1770 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1774 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1776 struct ixgbe_hw *hw =
1777 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780 PMD_INIT_FUNC_TRACE();
1782 if (hw->mac.type == ixgbe_mac_82598EB) {
1783 /* No queue level supported */
1784 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1788 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1789 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1790 ctrl |= IXGBE_RXDCTL_VME;
1791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1793 /* record those setting for HW strip per queue */
1794 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1798 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1800 struct ixgbe_hw *hw =
1801 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 struct ixgbe_rx_queue *rxq;
1806 PMD_INIT_FUNC_TRACE();
1808 if (hw->mac.type == ixgbe_mac_82598EB) {
1809 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1810 ctrl &= ~IXGBE_VLNCTRL_VME;
1811 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1813 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1814 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1815 rxq = dev->data->rx_queues[i];
1816 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1817 ctrl &= ~IXGBE_RXDCTL_VME;
1818 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1820 /* record those setting for HW strip per queue */
1821 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1827 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1829 struct ixgbe_hw *hw =
1830 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 struct ixgbe_rx_queue *rxq;
1835 PMD_INIT_FUNC_TRACE();
1837 if (hw->mac.type == ixgbe_mac_82598EB) {
1838 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839 ctrl |= IXGBE_VLNCTRL_VME;
1840 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1842 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1843 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1844 rxq = dev->data->rx_queues[i];
1845 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1846 ctrl |= IXGBE_RXDCTL_VME;
1847 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1849 /* record those setting for HW strip per queue */
1850 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1856 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 PMD_INIT_FUNC_TRACE();
1864 /* DMATXCTRL: Geric Double VLAN Disable */
1865 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866 ctrl &= ~IXGBE_DMATXCTL_GDV;
1867 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1869 /* CTRL_EXT: Global Double VLAN Disable */
1870 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1871 ctrl &= ~IXGBE_EXTENDED_VLAN;
1872 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1877 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1879 struct ixgbe_hw *hw =
1880 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883 PMD_INIT_FUNC_TRACE();
1885 /* DMATXCTRL: Geric Double VLAN Enable */
1886 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887 ctrl |= IXGBE_DMATXCTL_GDV;
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1890 /* CTRL_EXT: Global Double VLAN Enable */
1891 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1892 ctrl |= IXGBE_EXTENDED_VLAN;
1893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1895 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1896 if (hw->mac.type == ixgbe_mac_X550 ||
1897 hw->mac.type == ixgbe_mac_X550EM_x ||
1898 hw->mac.type == ixgbe_mac_X550EM_a) {
1899 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1900 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1901 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1905 * VET EXT field in the EXVET register = 0x8100 by default
1906 * So no need to change. Same to VT field of DMATXCTL register
1911 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1913 if (mask & ETH_VLAN_STRIP_MASK) {
1914 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1915 ixgbe_vlan_hw_strip_enable_all(dev);
1917 ixgbe_vlan_hw_strip_disable_all(dev);
1920 if (mask & ETH_VLAN_FILTER_MASK) {
1921 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1922 ixgbe_vlan_hw_filter_enable(dev);
1924 ixgbe_vlan_hw_filter_disable(dev);
1927 if (mask & ETH_VLAN_EXTEND_MASK) {
1928 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1929 ixgbe_vlan_hw_extend_enable(dev);
1931 ixgbe_vlan_hw_extend_disable(dev);
1936 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 struct ixgbe_hw *hw =
1939 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1941 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1944 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1948 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1953 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1956 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1962 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1969 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1971 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1976 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977 /* check multi-queue mode */
1978 switch (dev_conf->rxmode.mq_mode) {
1979 case ETH_MQ_RX_VMDQ_DCB:
1980 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1982 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984 PMD_INIT_LOG(ERR, "SRIOV active,"
1985 " unsupported mq_mode rx %d.",
1986 dev_conf->rxmode.mq_mode);
1989 case ETH_MQ_RX_VMDQ_RSS:
1990 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993 PMD_INIT_LOG(ERR, "SRIOV is active,"
1994 " invalid queue number"
1995 " for VMDQ RSS, allowed"
1996 " value are 1, 2 or 4.");
2000 case ETH_MQ_RX_VMDQ_ONLY:
2001 case ETH_MQ_RX_NONE:
2002 /* if nothing mq mode configure, use default scheme */
2003 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2007 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008 /* SRIOV only works in VMDq enable mode */
2009 PMD_INIT_LOG(ERR, "SRIOV is active,"
2010 " wrong mq_mode rx %d.",
2011 dev_conf->rxmode.mq_mode);
2015 switch (dev_conf->txmode.mq_mode) {
2016 case ETH_MQ_TX_VMDQ_DCB:
2017 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2020 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2025 /* check valid queue number */
2026 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028 PMD_INIT_LOG(ERR, "SRIOV is active,"
2029 " nb_rx_q=%d nb_tx_q=%d queue number"
2030 " must be less than or equal to %d.",
2032 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2036 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2041 /* check configuration for vmdb+dcb mode */
2042 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043 const struct rte_eth_vmdq_dcb_conf *conf;
2045 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047 IXGBE_VMDQ_DCB_NB_QUEUES);
2050 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052 conf->nb_queue_pools == ETH_32_POOLS)) {
2053 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054 " nb_queue_pools must be %d or %d.",
2055 ETH_16_POOLS, ETH_32_POOLS);
2059 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2062 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064 IXGBE_VMDQ_DCB_NB_QUEUES);
2067 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069 conf->nb_queue_pools == ETH_32_POOLS)) {
2070 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071 " nb_queue_pools != %d and"
2072 " nb_queue_pools != %d.",
2073 ETH_16_POOLS, ETH_32_POOLS);
2078 /* For DCB mode check our configuration before we go further */
2079 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080 const struct rte_eth_dcb_rx_conf *conf;
2082 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084 IXGBE_DCB_NB_QUEUES);
2087 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088 if (!(conf->nb_tcs == ETH_4_TCS ||
2089 conf->nb_tcs == ETH_8_TCS)) {
2090 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091 " and nb_tcs != %d.",
2092 ETH_4_TCS, ETH_8_TCS);
2097 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098 const struct rte_eth_dcb_tx_conf *conf;
2100 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102 IXGBE_DCB_NB_QUEUES);
2105 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106 if (!(conf->nb_tcs == ETH_4_TCS ||
2107 conf->nb_tcs == ETH_8_TCS)) {
2108 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109 " and nb_tcs != %d.",
2110 ETH_4_TCS, ETH_8_TCS);
2116 * When DCB/VT is off, maximum number of queues changes,
2117 * except for 82598EB, which remains constant.
2119 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120 hw->mac.type != ixgbe_mac_82598EB) {
2121 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2123 "Neither VT nor DCB are enabled, "
2125 IXGBE_NONE_MODE_TX_NB_QUEUES);
2134 ixgbe_dev_configure(struct rte_eth_dev *dev)
2136 struct ixgbe_interrupt *intr =
2137 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138 struct ixgbe_adapter *adapter =
2139 (struct ixgbe_adapter *)dev->data->dev_private;
2142 PMD_INIT_FUNC_TRACE();
2143 /* multipe queue mode checking */
2144 ret = ixgbe_check_mq_mode(dev);
2146 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2151 /* set flag to update link status after init */
2152 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2155 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156 * allocation or vector Rx preconditions we will reset it.
2158 adapter->rx_bulk_alloc_allowed = true;
2159 adapter->rx_vec_allowed = true;
2165 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2167 struct ixgbe_hw *hw =
2168 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 struct ixgbe_interrupt *intr =
2170 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2173 /* only set up it on X550EM_X */
2174 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2184 * Configure device link speed and setup link.
2185 * It returns 0 on success.
2188 ixgbe_dev_start(struct rte_eth_dev *dev)
2190 struct ixgbe_hw *hw =
2191 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192 struct ixgbe_vf_info *vfinfo =
2193 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2195 uint32_t intr_vector = 0;
2196 int err, link_up = 0, negotiate = 0;
2201 uint32_t *link_speeds;
2203 PMD_INIT_FUNC_TRACE();
2205 /* IXGBE devices don't support:
2206 * - half duplex (checked afterwards for valid speeds)
2207 * - fixed speed: TODO implement
2209 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2210 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2211 dev->data->port_id);
2215 /* disable uio/vfio intr/eventfd mapping */
2216 rte_intr_disable(intr_handle);
2219 hw->adapter_stopped = 0;
2220 ixgbe_stop_adapter(hw);
2222 /* reinitialize adapter
2223 * this calls reset and start
2225 status = ixgbe_pf_reset_hw(hw);
2228 hw->mac.ops.start_hw(hw);
2229 hw->mac.get_link_status = true;
2231 /* configure PF module if SRIOV enabled */
2232 ixgbe_pf_host_configure(dev);
2234 ixgbe_dev_phy_intr_setup(dev);
2236 /* check and configure queue intr-vector mapping */
2237 if ((rte_intr_cap_multiple(intr_handle) ||
2238 !RTE_ETH_DEV_SRIOV(dev).active) &&
2239 dev->data->dev_conf.intr_conf.rxq != 0) {
2240 intr_vector = dev->data->nb_rx_queues;
2241 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2242 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2243 IXGBE_MAX_INTR_QUEUE_NUM);
2246 if (rte_intr_efd_enable(intr_handle, intr_vector))
2250 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2251 intr_handle->intr_vec =
2252 rte_zmalloc("intr_vec",
2253 dev->data->nb_rx_queues * sizeof(int), 0);
2254 if (intr_handle->intr_vec == NULL) {
2255 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2256 " intr_vec\n", dev->data->nb_rx_queues);
2261 /* confiugre msix for sleep until rx interrupt */
2262 ixgbe_configure_msix(dev);
2264 /* initialize transmission unit */
2265 ixgbe_dev_tx_init(dev);
2267 /* This can fail when allocating mbufs for descriptor rings */
2268 err = ixgbe_dev_rx_init(dev);
2270 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2274 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2275 ETH_VLAN_EXTEND_MASK;
2276 ixgbe_vlan_offload_set(dev, mask);
2278 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2279 /* Enable vlan filtering for VMDq */
2280 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2283 /* Configure DCB hw */
2284 ixgbe_configure_dcb(dev);
2286 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2287 err = ixgbe_fdir_configure(dev);
2292 /* Restore vf rate limit */
2293 if (vfinfo != NULL) {
2294 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2295 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2296 if (vfinfo[vf].tx_rate[idx] != 0)
2297 ixgbe_set_vf_rate_limit(dev, vf,
2298 vfinfo[vf].tx_rate[idx],
2302 ixgbe_restore_statistics_mapping(dev);
2304 err = ixgbe_dev_rxtx_start(dev);
2306 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2310 /* Skip link setup if loopback mode is enabled for 82599. */
2311 if (hw->mac.type == ixgbe_mac_82599EB &&
2312 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2313 goto skip_link_setup;
2315 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2316 err = hw->mac.ops.setup_sfp(hw);
2321 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2322 /* Turn on the copper */
2323 ixgbe_set_phy_power(hw, true);
2325 /* Turn on the laser */
2326 ixgbe_enable_tx_laser(hw);
2329 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2332 dev->data->dev_link.link_status = link_up;
2334 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2338 link_speeds = &dev->data->dev_conf.link_speeds;
2339 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2340 ETH_LINK_SPEED_10G)) {
2341 PMD_INIT_LOG(ERR, "Invalid link setting");
2346 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2347 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2348 IXGBE_LINK_SPEED_82599_AUTONEG :
2349 IXGBE_LINK_SPEED_82598_AUTONEG;
2351 if (*link_speeds & ETH_LINK_SPEED_10G)
2352 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2353 if (*link_speeds & ETH_LINK_SPEED_1G)
2354 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2355 if (*link_speeds & ETH_LINK_SPEED_100M)
2356 speed |= IXGBE_LINK_SPEED_100_FULL;
2359 err = ixgbe_setup_link(hw, speed, link_up);
2365 if (rte_intr_allow_others(intr_handle)) {
2366 /* check if lsc interrupt is enabled */
2367 if (dev->data->dev_conf.intr_conf.lsc != 0)
2368 ixgbe_dev_lsc_interrupt_setup(dev);
2370 rte_intr_callback_unregister(intr_handle,
2371 ixgbe_dev_interrupt_handler,
2373 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375 " no intr multiplex\n");
2378 /* check if rxq interrupt is enabled */
2379 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380 rte_intr_dp_is_en(intr_handle))
2381 ixgbe_dev_rxq_interrupt_setup(dev);
2383 /* enable uio/vfio intr/eventfd mapping */
2384 rte_intr_enable(intr_handle);
2386 /* resume enabled intr since hw reset */
2387 ixgbe_enable_intr(dev);
2392 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393 ixgbe_dev_clear_queues(dev);
2398 * Stop device: disable rx and tx functions to allow for reconfiguring.
2401 ixgbe_dev_stop(struct rte_eth_dev *dev)
2403 struct rte_eth_link link;
2404 struct ixgbe_hw *hw =
2405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 struct ixgbe_vf_info *vfinfo =
2407 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408 struct ixgbe_filter_info *filter_info =
2409 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2414 PMD_INIT_FUNC_TRACE();
2416 /* disable interrupts */
2417 ixgbe_disable_intr(hw);
2420 ixgbe_pf_reset_hw(hw);
2421 hw->adapter_stopped = 0;
2424 ixgbe_stop_adapter(hw);
2426 for (vf = 0; vfinfo != NULL &&
2427 vf < dev->pci_dev->max_vfs; vf++)
2428 vfinfo[vf].clear_to_send = false;
2430 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431 /* Turn off the copper */
2432 ixgbe_set_phy_power(hw, false);
2434 /* Turn off the laser */
2435 ixgbe_disable_tx_laser(hw);
2438 ixgbe_dev_clear_queues(dev);
2440 /* Clear stored conf */
2441 dev->data->scattered_rx = 0;
2444 /* Clear recorded link status */
2445 memset(&link, 0, sizeof(link));
2446 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2448 /* Remove all ntuple filters of the device */
2449 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452 TAILQ_REMOVE(&filter_info->fivetuple_list,
2456 memset(filter_info->fivetuple_mask, 0,
2457 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2459 if (!rte_intr_allow_others(intr_handle))
2460 /* resume to the default handler */
2461 rte_intr_callback_register(intr_handle,
2462 ixgbe_dev_interrupt_handler,
2465 /* Clean datapath event and queue/vec mapping */
2466 rte_intr_efd_disable(intr_handle);
2467 if (intr_handle->intr_vec != NULL) {
2468 rte_free(intr_handle->intr_vec);
2469 intr_handle->intr_vec = NULL;
2474 * Set device link up: enable tx.
2477 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2479 struct ixgbe_hw *hw =
2480 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481 if (hw->mac.type == ixgbe_mac_82599EB) {
2482 #ifdef RTE_NIC_BYPASS
2483 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484 /* Not suported in bypass mode */
2485 PMD_INIT_LOG(ERR, "Set link up is not supported "
2486 "by device id 0x%x", hw->device_id);
2492 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493 /* Turn on the copper */
2494 ixgbe_set_phy_power(hw, true);
2496 /* Turn on the laser */
2497 ixgbe_enable_tx_laser(hw);
2504 * Set device link down: disable tx.
2507 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2509 struct ixgbe_hw *hw =
2510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511 if (hw->mac.type == ixgbe_mac_82599EB) {
2512 #ifdef RTE_NIC_BYPASS
2513 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514 /* Not suported in bypass mode */
2515 PMD_INIT_LOG(ERR, "Set link down is not supported "
2516 "by device id 0x%x", hw->device_id);
2522 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523 /* Turn off the copper */
2524 ixgbe_set_phy_power(hw, false);
2526 /* Turn off the laser */
2527 ixgbe_disable_tx_laser(hw);
2534 * Reest and stop device.
2537 ixgbe_dev_close(struct rte_eth_dev *dev)
2539 struct ixgbe_hw *hw =
2540 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542 PMD_INIT_FUNC_TRACE();
2544 ixgbe_pf_reset_hw(hw);
2546 ixgbe_dev_stop(dev);
2547 hw->adapter_stopped = 1;
2549 ixgbe_dev_free_queues(dev);
2551 ixgbe_disable_pcie_master(hw);
2553 /* reprogram the RAR[0] in case user changed it. */
2554 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2558 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559 struct ixgbe_hw_stats *hw_stats,
2560 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561 uint64_t *total_qprc, uint64_t *total_qprdc)
2563 uint32_t bprc, lxon, lxoff, total;
2564 uint32_t delta_gprc = 0;
2566 /* Workaround for RX byte count not including CRC bytes when CRC
2567 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2570 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571 IXGBE_HLREG0_RXCRCSTRP);
2573 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2578 for (i = 0; i < 8; i++) {
2579 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2581 /* global total per queue */
2582 hw_stats->mpc[i] += mp;
2583 /* Running comprehensive total for stats display */
2584 *total_missed_rx += hw_stats->mpc[i];
2585 if (hw->mac.type == ixgbe_mac_82598EB) {
2586 hw_stats->rnbc[i] +=
2587 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588 hw_stats->pxonrxc[i] +=
2589 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590 hw_stats->pxoffrxc[i] +=
2591 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2593 hw_stats->pxonrxc[i] +=
2594 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595 hw_stats->pxoffrxc[i] +=
2596 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597 hw_stats->pxon2offc[i] +=
2598 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2600 hw_stats->pxontxc[i] +=
2601 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602 hw_stats->pxofftxc[i] +=
2603 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2605 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2610 delta_gprc += delta_qprc;
2612 hw_stats->qprc[i] += delta_qprc;
2613 hw_stats->qptc[i] += delta_qptc;
2615 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616 hw_stats->qbrc[i] +=
2617 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2619 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2621 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622 hw_stats->qbtc[i] +=
2623 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2625 hw_stats->qprdc[i] += delta_qprdc;
2626 *total_qprdc += hw_stats->qprdc[i];
2628 *total_qprc += hw_stats->qprc[i];
2629 *total_qbrc += hw_stats->qbrc[i];
2631 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2636 * An errata states that gprc actually counts good + missed packets:
2637 * Workaround to set gprc to summated queue packet receives
2639 hw_stats->gprc = *total_qprc;
2641 if (hw->mac.type != ixgbe_mac_82598EB) {
2642 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2651 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653 /* 82598 only has a counter in the high register */
2654 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2658 uint64_t old_tpr = hw_stats->tpr;
2660 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2664 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2666 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667 hw_stats->gptc += delta_gptc;
2668 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2672 * Workaround: mprc hardware is incorrectly counting
2673 * broadcasts, so for now we subtract those.
2675 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676 hw_stats->bprc += bprc;
2677 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678 if (hw->mac.type == ixgbe_mac_82598EB)
2679 hw_stats->mprc -= bprc;
2681 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2688 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689 hw_stats->lxontxc += lxon;
2690 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691 hw_stats->lxofftxc += lxoff;
2692 total = lxon + lxoff;
2694 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696 hw_stats->gptc -= total;
2697 hw_stats->mptc -= total;
2698 hw_stats->ptc64 -= total;
2699 hw_stats->gotc -= total * ETHER_MIN_LEN;
2701 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717 /* Only read FCOE on 82599 */
2718 if (hw->mac.type != ixgbe_mac_82598EB) {
2719 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2726 /* Flow Director Stats registers */
2727 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2732 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2735 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2737 struct ixgbe_hw *hw =
2738 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739 struct ixgbe_hw_stats *hw_stats =
2740 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2744 total_missed_rx = 0;
2749 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750 &total_qprc, &total_qprdc);
2755 /* Fill out the rte_eth_stats statistics structure */
2756 stats->ipackets = total_qprc;
2757 stats->ibytes = total_qbrc;
2758 stats->opackets = hw_stats->gptc;
2759 stats->obytes = hw_stats->gotc;
2761 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762 stats->q_ipackets[i] = hw_stats->qprc[i];
2763 stats->q_opackets[i] = hw_stats->qptc[i];
2764 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765 stats->q_obytes[i] = hw_stats->qbtc[i];
2766 stats->q_errors[i] = hw_stats->qprdc[i];
2770 stats->imissed = total_missed_rx;
2771 stats->ierrors = hw_stats->crcerrs +
2787 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2789 struct ixgbe_hw_stats *stats =
2790 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2792 /* HW registers are cleared on read */
2793 ixgbe_dev_stats_get(dev, NULL);
2795 /* Reset software totals */
2796 memset(stats, 0, sizeof(*stats));
2799 /* This function calculates the number of xstats based on the current config */
2801 ixgbe_xstats_calc_num(void) {
2802 return IXGBE_NB_HW_STATS +
2803 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2807 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2810 const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811 unsigned stat, i, count;
2813 if (xstats_names != NULL) {
2816 /* Note: limit >= cnt_stats checked upstream
2817 * in rte_eth_xstats_names()
2820 /* Extended stats from ixgbe_hw_stats */
2821 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822 snprintf(xstats_names[count].name,
2823 sizeof(xstats_names[count].name),
2825 rte_ixgbe_stats_strings[i].name);
2829 /* RX Priority Stats */
2830 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832 snprintf(xstats_names[count].name,
2833 sizeof(xstats_names[count].name),
2834 "rx_priority%u_%s", i,
2835 rte_ixgbe_rxq_strings[stat].name);
2840 /* TX Priority Stats */
2841 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843 snprintf(xstats_names[count].name,
2844 sizeof(xstats_names[count].name),
2845 "tx_priority%u_%s", i,
2846 rte_ixgbe_txq_strings[stat].name);
2854 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855 struct rte_eth_xstat_name *xstats_names, unsigned limit)
2859 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2862 if (xstats_names != NULL)
2863 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864 snprintf(xstats_names[i].name,
2865 sizeof(xstats_names[i].name),
2866 "%s", rte_ixgbevf_stats_strings[i].name);
2867 return IXGBEVF_NB_XSTATS;
2871 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2874 struct ixgbe_hw *hw =
2875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 struct ixgbe_hw_stats *hw_stats =
2877 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879 unsigned i, stat, count = 0;
2881 count = ixgbe_xstats_calc_num();
2886 total_missed_rx = 0;
2891 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892 &total_qprc, &total_qprdc);
2894 /* If this is a reset xstats is NULL, and we have cleared the
2895 * registers by reading them.
2900 /* Extended stats from ixgbe_hw_stats */
2902 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904 rte_ixgbe_stats_strings[i].offset);
2905 xstats[count].id = count;
2909 /* RX Priority Stats */
2910 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2911 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2912 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2913 rte_ixgbe_rxq_strings[stat].offset +
2914 (sizeof(uint64_t) * i));
2915 xstats[count].id = count;
2920 /* TX Priority Stats */
2921 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2922 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2923 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2924 rte_ixgbe_txq_strings[stat].offset +
2925 (sizeof(uint64_t) * i));
2926 xstats[count].id = count;
2934 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2936 struct ixgbe_hw_stats *stats =
2937 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2939 unsigned count = ixgbe_xstats_calc_num();
2941 /* HW registers are cleared on read */
2942 ixgbe_dev_xstats_get(dev, NULL, count);
2944 /* Reset software totals */
2945 memset(stats, 0, sizeof(*stats));
2949 ixgbevf_update_stats(struct rte_eth_dev *dev)
2951 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2953 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2955 /* Good Rx packet, include VF loopback */
2956 UPDATE_VF_STAT(IXGBE_VFGPRC,
2957 hw_stats->last_vfgprc, hw_stats->vfgprc);
2959 /* Good Rx octets, include VF loopback */
2960 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2961 hw_stats->last_vfgorc, hw_stats->vfgorc);
2963 /* Good Tx packet, include VF loopback */
2964 UPDATE_VF_STAT(IXGBE_VFGPTC,
2965 hw_stats->last_vfgptc, hw_stats->vfgptc);
2967 /* Good Tx octets, include VF loopback */
2968 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2969 hw_stats->last_vfgotc, hw_stats->vfgotc);
2971 /* Rx Multicst Packet */
2972 UPDATE_VF_STAT(IXGBE_VFMPRC,
2973 hw_stats->last_vfmprc, hw_stats->vfmprc);
2977 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2980 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2981 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2984 if (n < IXGBEVF_NB_XSTATS)
2985 return IXGBEVF_NB_XSTATS;
2987 ixgbevf_update_stats(dev);
2992 /* Extended stats */
2993 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2995 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2996 rte_ixgbevf_stats_strings[i].offset);
2999 return IXGBEVF_NB_XSTATS;
3003 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3005 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3006 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3008 ixgbevf_update_stats(dev);
3013 stats->ipackets = hw_stats->vfgprc;
3014 stats->ibytes = hw_stats->vfgorc;
3015 stats->opackets = hw_stats->vfgptc;
3016 stats->obytes = hw_stats->vfgotc;
3020 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3022 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3023 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3025 /* Sync HW register to the last stats */
3026 ixgbevf_dev_stats_get(dev, NULL);
3028 /* reset HW current stats*/
3029 hw_stats->vfgprc = 0;
3030 hw_stats->vfgorc = 0;
3031 hw_stats->vfgptc = 0;
3032 hw_stats->vfgotc = 0;
3036 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3041 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3042 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3043 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3045 * When DCB/VT is off, maximum number of queues changes,
3046 * except for 82598EB, which remains constant.
3048 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3049 hw->mac.type != ixgbe_mac_82598EB)
3050 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3052 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3053 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3054 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3055 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3056 dev_info->max_vfs = dev->pci_dev->max_vfs;
3057 if (hw->mac.type == ixgbe_mac_82598EB)
3058 dev_info->max_vmdq_pools = ETH_16_POOLS;
3060 dev_info->max_vmdq_pools = ETH_64_POOLS;
3061 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3062 dev_info->rx_offload_capa =
3063 DEV_RX_OFFLOAD_VLAN_STRIP |
3064 DEV_RX_OFFLOAD_IPV4_CKSUM |
3065 DEV_RX_OFFLOAD_UDP_CKSUM |
3066 DEV_RX_OFFLOAD_TCP_CKSUM;
3069 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3072 if ((hw->mac.type == ixgbe_mac_82599EB ||
3073 hw->mac.type == ixgbe_mac_X540) &&
3074 !RTE_ETH_DEV_SRIOV(dev).active)
3075 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3077 if (hw->mac.type == ixgbe_mac_X550 ||
3078 hw->mac.type == ixgbe_mac_X550EM_x ||
3079 hw->mac.type == ixgbe_mac_X550EM_a)
3080 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3082 dev_info->tx_offload_capa =
3083 DEV_TX_OFFLOAD_VLAN_INSERT |
3084 DEV_TX_OFFLOAD_IPV4_CKSUM |
3085 DEV_TX_OFFLOAD_UDP_CKSUM |
3086 DEV_TX_OFFLOAD_TCP_CKSUM |
3087 DEV_TX_OFFLOAD_SCTP_CKSUM |
3088 DEV_TX_OFFLOAD_TCP_TSO;
3090 if (hw->mac.type == ixgbe_mac_X550 ||
3091 hw->mac.type == ixgbe_mac_X550EM_x ||
3092 hw->mac.type == ixgbe_mac_X550EM_a)
3093 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3095 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3097 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3098 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3099 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3101 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3105 dev_info->default_txconf = (struct rte_eth_txconf) {
3107 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3108 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3109 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3111 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3112 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3113 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3114 ETH_TXQ_FLAGS_NOOFFLOADS,
3117 dev_info->rx_desc_lim = rx_desc_lim;
3118 dev_info->tx_desc_lim = tx_desc_lim;
3120 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3121 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3122 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3124 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3125 if (hw->mac.type == ixgbe_mac_X540 ||
3126 hw->mac.type == ixgbe_mac_X540_vf ||
3127 hw->mac.type == ixgbe_mac_X550 ||
3128 hw->mac.type == ixgbe_mac_X550_vf) {
3129 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3133 static const uint32_t *
3134 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3136 static const uint32_t ptypes[] = {
3137 /* For non-vec functions,
3138 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3139 * for vec functions,
3140 * refers to _recv_raw_pkts_vec().
3144 RTE_PTYPE_L3_IPV4_EXT,
3146 RTE_PTYPE_L3_IPV6_EXT,
3150 RTE_PTYPE_TUNNEL_IP,
3151 RTE_PTYPE_INNER_L3_IPV6,
3152 RTE_PTYPE_INNER_L3_IPV6_EXT,
3153 RTE_PTYPE_INNER_L4_TCP,
3154 RTE_PTYPE_INNER_L4_UDP,
3158 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3159 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3160 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3161 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3167 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3168 struct rte_eth_dev_info *dev_info)
3170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3172 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3173 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3174 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3175 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3176 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3177 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3178 dev_info->max_vfs = dev->pci_dev->max_vfs;
3179 if (hw->mac.type == ixgbe_mac_82598EB)
3180 dev_info->max_vmdq_pools = ETH_16_POOLS;
3182 dev_info->max_vmdq_pools = ETH_64_POOLS;
3183 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3184 DEV_RX_OFFLOAD_IPV4_CKSUM |
3185 DEV_RX_OFFLOAD_UDP_CKSUM |
3186 DEV_RX_OFFLOAD_TCP_CKSUM;
3187 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3188 DEV_TX_OFFLOAD_IPV4_CKSUM |
3189 DEV_TX_OFFLOAD_UDP_CKSUM |
3190 DEV_TX_OFFLOAD_TCP_CKSUM |
3191 DEV_TX_OFFLOAD_SCTP_CKSUM |
3192 DEV_TX_OFFLOAD_TCP_TSO;
3194 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3196 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3197 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3198 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3200 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3204 dev_info->default_txconf = (struct rte_eth_txconf) {
3206 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3207 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3208 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3210 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3211 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3212 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3213 ETH_TXQ_FLAGS_NOOFFLOADS,
3216 dev_info->rx_desc_lim = rx_desc_lim;
3217 dev_info->tx_desc_lim = tx_desc_lim;
3220 /* return 0 means link status changed, -1 means not changed */
3222 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3224 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225 struct rte_eth_link link, old;
3226 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3230 link.link_status = ETH_LINK_DOWN;
3231 link.link_speed = 0;
3232 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3233 link.link_autoneg = ETH_LINK_AUTONEG;
3234 memset(&old, 0, sizeof(old));
3235 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3237 hw->mac.get_link_status = true;
3239 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3240 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3241 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3243 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3246 link.link_speed = ETH_SPEED_NUM_100M;
3247 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3248 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3249 if (link.link_status == old.link_status)
3255 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3256 if (link.link_status == old.link_status)
3260 link.link_status = ETH_LINK_UP;
3261 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3263 switch (link_speed) {
3265 case IXGBE_LINK_SPEED_UNKNOWN:
3266 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3267 link.link_speed = ETH_SPEED_NUM_100M;
3270 case IXGBE_LINK_SPEED_100_FULL:
3271 link.link_speed = ETH_SPEED_NUM_100M;
3274 case IXGBE_LINK_SPEED_1GB_FULL:
3275 link.link_speed = ETH_SPEED_NUM_1G;
3278 case IXGBE_LINK_SPEED_10GB_FULL:
3279 link.link_speed = ETH_SPEED_NUM_10G;
3282 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3284 if (link.link_status == old.link_status)
3291 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3297 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3298 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3302 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3304 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3308 fctrl &= (~IXGBE_FCTRL_UPE);
3309 if (dev->data->all_multicast == 1)
3310 fctrl |= IXGBE_FCTRL_MPE;
3312 fctrl &= (~IXGBE_FCTRL_MPE);
3313 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3317 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3319 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3323 fctrl |= IXGBE_FCTRL_MPE;
3324 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3328 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333 if (dev->data->promiscuous == 1)
3334 return; /* must remain in all_multicast mode */
3336 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3337 fctrl &= (~IXGBE_FCTRL_MPE);
3338 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3342 * It clears the interrupt causes and enables the interrupt.
3343 * It will be called once only during nic initialized.
3346 * Pointer to struct rte_eth_dev.
3349 * - On success, zero.
3350 * - On failure, a negative value.
3353 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3355 struct ixgbe_interrupt *intr =
3356 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3358 ixgbe_dev_link_status_print(dev);
3359 intr->mask |= IXGBE_EICR_LSC;
3365 * It clears the interrupt causes and enables the interrupt.
3366 * It will be called once only during nic initialized.
3369 * Pointer to struct rte_eth_dev.
3372 * - On success, zero.
3373 * - On failure, a negative value.
3376 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3378 struct ixgbe_interrupt *intr =
3379 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3381 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3387 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3390 * Pointer to struct rte_eth_dev.
3393 * - On success, zero.
3394 * - On failure, a negative value.
3397 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3400 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401 struct ixgbe_interrupt *intr =
3402 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3404 /* clear all cause mask */
3405 ixgbe_disable_intr(hw);
3407 /* read-on-clear nic registers here */
3408 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3409 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3413 /* set flag for async link update */
3414 if (eicr & IXGBE_EICR_LSC)
3415 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3417 if (eicr & IXGBE_EICR_MAILBOX)
3418 intr->flags |= IXGBE_FLAG_MAILBOX;
3420 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3421 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3422 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3423 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3429 * It gets and then prints the link status.
3432 * Pointer to struct rte_eth_dev.
3435 * - On success, zero.
3436 * - On failure, a negative value.
3439 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3441 struct rte_eth_link link;
3443 memset(&link, 0, sizeof(link));
3444 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3445 if (link.link_status) {
3446 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3447 (int)(dev->data->port_id),
3448 (unsigned)link.link_speed,
3449 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3450 "full-duplex" : "half-duplex");
3452 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3453 (int)(dev->data->port_id));
3455 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3456 dev->pci_dev->addr.domain,
3457 dev->pci_dev->addr.bus,
3458 dev->pci_dev->addr.devid,
3459 dev->pci_dev->addr.function);
3463 * It executes link_update after knowing an interrupt occurred.
3466 * Pointer to struct rte_eth_dev.
3469 * - On success, zero.
3470 * - On failure, a negative value.
3473 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3475 struct ixgbe_interrupt *intr =
3476 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3478 struct rte_eth_link link;
3479 struct ixgbe_hw *hw =
3480 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3482 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3484 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3485 ixgbe_pf_mbx_process(dev);
3486 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3489 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3490 ixgbe_handle_lasi(hw);
3491 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3494 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3495 /* get the link status before link update, for predicting later */
3496 memset(&link, 0, sizeof(link));
3497 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3499 ixgbe_dev_link_update(dev, 0);
3502 if (!link.link_status)
3503 /* handle it 1 sec later, wait it being stable */
3504 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3505 /* likely to down */
3507 /* handle it 4 sec later, wait it being stable */
3508 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3510 ixgbe_dev_link_status_print(dev);
3511 intr->mask_original = intr->mask;
3512 /* only disable lsc interrupt */
3513 intr->mask &= ~IXGBE_EIMS_LSC;
3514 if (rte_eal_alarm_set(timeout * 1000,
3515 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3516 PMD_DRV_LOG(ERR, "Error setting alarm");
3518 intr->mask = intr->mask_original;
3521 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3522 ixgbe_enable_intr(dev);
3523 rte_intr_enable(&dev->pci_dev->intr_handle);
3529 * Interrupt handler which shall be registered for alarm callback for delayed
3530 * handling specific interrupt to wait for the stable nic state. As the
3531 * NIC interrupt state is not stable for ixgbe after link is just down,
3532 * it needs to wait 4 seconds to get the stable status.
3535 * Pointer to interrupt handle.
3537 * The address of parameter (struct rte_eth_dev *) regsitered before.
3543 ixgbe_dev_interrupt_delayed_handler(void *param)
3545 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3546 struct ixgbe_interrupt *intr =
3547 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3548 struct ixgbe_hw *hw =
3549 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3553 if (eicr & IXGBE_EICR_MAILBOX)
3554 ixgbe_pf_mbx_process(dev);
3556 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3557 ixgbe_handle_lasi(hw);
3558 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3561 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3562 ixgbe_dev_link_update(dev, 0);
3563 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3564 ixgbe_dev_link_status_print(dev);
3565 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3568 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3569 ixgbe_enable_intr(dev);
3570 rte_intr_enable(&(dev->pci_dev->intr_handle));
3574 * Interrupt handler triggered by NIC for handling
3575 * specific interrupt.
3578 * Pointer to interrupt handle.
3580 * The address of parameter (struct rte_eth_dev *) regsitered before.
3586 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3589 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3591 ixgbe_dev_interrupt_get_status(dev);
3592 ixgbe_dev_interrupt_action(dev);
3596 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3598 struct ixgbe_hw *hw;
3600 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3605 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3607 struct ixgbe_hw *hw;
3609 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3614 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3616 struct ixgbe_hw *hw;
3622 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624 fc_conf->pause_time = hw->fc.pause_time;
3625 fc_conf->high_water = hw->fc.high_water[0];
3626 fc_conf->low_water = hw->fc.low_water[0];
3627 fc_conf->send_xon = hw->fc.send_xon;
3628 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3631 * Return rx_pause status according to actual setting of
3634 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3635 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3641 * Return tx_pause status according to actual setting of
3644 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3645 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3650 if (rx_pause && tx_pause)
3651 fc_conf->mode = RTE_FC_FULL;
3653 fc_conf->mode = RTE_FC_RX_PAUSE;
3655 fc_conf->mode = RTE_FC_TX_PAUSE;
3657 fc_conf->mode = RTE_FC_NONE;
3663 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3665 struct ixgbe_hw *hw;
3667 uint32_t rx_buf_size;
3668 uint32_t max_high_water;
3670 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3677 PMD_INIT_FUNC_TRACE();
3679 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3681 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3684 * At least reserve one Ethernet frame for watermark
3685 * high_water/low_water in kilo bytes for ixgbe
3687 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3688 if ((fc_conf->high_water > max_high_water) ||
3689 (fc_conf->high_water < fc_conf->low_water)) {
3690 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3691 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3695 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3696 hw->fc.pause_time = fc_conf->pause_time;
3697 hw->fc.high_water[0] = fc_conf->high_water;
3698 hw->fc.low_water[0] = fc_conf->low_water;
3699 hw->fc.send_xon = fc_conf->send_xon;
3700 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3702 err = ixgbe_fc_enable(hw);
3704 /* Not negotiated is not an error case */
3705 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3707 /* check if we want to forward MAC frames - driver doesn't have native
3708 * capability to do that, so we'll write the registers ourselves */
3710 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3712 /* set or clear MFLCN.PMCF bit depending on configuration */
3713 if (fc_conf->mac_ctrl_frame_fwd != 0)
3714 mflcn |= IXGBE_MFLCN_PMCF;
3716 mflcn &= ~IXGBE_MFLCN_PMCF;
3718 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3719 IXGBE_WRITE_FLUSH(hw);
3724 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3729 * ixgbe_pfc_enable_generic - Enable flow control
3730 * @hw: pointer to hardware structure
3731 * @tc_num: traffic class number
3732 * Enable flow control according to the current settings.
3735 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3738 uint32_t mflcn_reg, fccfg_reg;
3740 uint32_t fcrtl, fcrth;
3744 /* Validate the water mark configuration */
3745 if (!hw->fc.pause_time) {
3746 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3750 /* Low water mark of zero causes XOFF floods */
3751 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3752 /* High/Low water can not be 0 */
3753 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3754 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3755 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3759 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3760 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3761 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3765 /* Negotiate the fc mode to use */
3766 ixgbe_fc_autoneg(hw);
3768 /* Disable any previous flow control settings */
3769 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3770 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3772 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3773 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3775 switch (hw->fc.current_mode) {
3778 * If the count of enabled RX Priority Flow control >1,
3779 * and the TX pause can not be disabled
3782 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3783 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3784 if (reg & IXGBE_FCRTH_FCEN)
3788 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3790 case ixgbe_fc_rx_pause:
3792 * Rx Flow control is enabled and Tx Flow control is
3793 * disabled by software override. Since there really
3794 * isn't a way to advertise that we are capable of RX
3795 * Pause ONLY, we will advertise that we support both
3796 * symmetric and asymmetric Rx PAUSE. Later, we will
3797 * disable the adapter's ability to send PAUSE frames.
3799 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3801 * If the count of enabled RX Priority Flow control >1,
3802 * and the TX pause can not be disabled
3805 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3806 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3807 if (reg & IXGBE_FCRTH_FCEN)
3811 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3813 case ixgbe_fc_tx_pause:
3815 * Tx Flow control is enabled, and Rx Flow control is
3816 * disabled by software override.
3818 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3821 /* Flow control (both Rx and Tx) is enabled by SW override. */
3822 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3823 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3826 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3827 ret_val = IXGBE_ERR_CONFIG;
3831 /* Set 802.3x based flow control settings. */
3832 mflcn_reg |= IXGBE_MFLCN_DPF;
3833 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3834 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3836 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3837 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3838 hw->fc.high_water[tc_num]) {
3839 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3840 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3841 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3843 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3845 * In order to prevent Tx hangs when the internal Tx
3846 * switch is enabled we must set the high water mark
3847 * to the maximum FCRTH value. This allows the Tx
3848 * switch to function even under heavy Rx workloads.
3850 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3852 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3854 /* Configure pause time (2 TCs per register) */
3855 reg = hw->fc.pause_time * 0x00010001;
3856 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3857 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3859 /* Configure flow control refresh threshold value */
3860 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3867 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3869 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3872 if (hw->mac.type != ixgbe_mac_82598EB) {
3873 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3879 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3882 uint32_t rx_buf_size;
3883 uint32_t max_high_water;
3885 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3886 struct ixgbe_hw *hw =
3887 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 struct ixgbe_dcb_config *dcb_config =
3889 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3891 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3898 PMD_INIT_FUNC_TRACE();
3900 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3901 tc_num = map[pfc_conf->priority];
3902 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3903 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3905 * At least reserve one Ethernet frame for watermark
3906 * high_water/low_water in kilo bytes for ixgbe
3908 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3909 if ((pfc_conf->fc.high_water > max_high_water) ||
3910 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3911 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3912 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3916 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3917 hw->fc.pause_time = pfc_conf->fc.pause_time;
3918 hw->fc.send_xon = pfc_conf->fc.send_xon;
3919 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3920 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3922 err = ixgbe_dcb_pfc_enable(dev, tc_num);
3924 /* Not negotiated is not an error case */
3925 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3928 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3933 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3934 struct rte_eth_rss_reta_entry64 *reta_conf,
3937 uint16_t i, sp_reta_size;
3940 uint16_t idx, shift;
3941 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944 PMD_INIT_FUNC_TRACE();
3946 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3947 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3952 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3953 if (reta_size != sp_reta_size) {
3954 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3955 "(%d) doesn't match the number hardware can supported "
3956 "(%d)\n", reta_size, sp_reta_size);
3960 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3961 idx = i / RTE_RETA_GROUP_SIZE;
3962 shift = i % RTE_RETA_GROUP_SIZE;
3963 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3967 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3968 if (mask == IXGBE_4_BIT_MASK)
3971 r = IXGBE_READ_REG(hw, reta_reg);
3972 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3973 if (mask & (0x1 << j))
3974 reta |= reta_conf[idx].reta[shift + j] <<
3977 reta |= r & (IXGBE_8_BIT_MASK <<
3980 IXGBE_WRITE_REG(hw, reta_reg, reta);
3987 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3988 struct rte_eth_rss_reta_entry64 *reta_conf,
3991 uint16_t i, sp_reta_size;
3994 uint16_t idx, shift;
3995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998 PMD_INIT_FUNC_TRACE();
3999 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4000 if (reta_size != sp_reta_size) {
4001 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4002 "(%d) doesn't match the number hardware can supported "
4003 "(%d)\n", reta_size, sp_reta_size);
4007 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4008 idx = i / RTE_RETA_GROUP_SIZE;
4009 shift = i % RTE_RETA_GROUP_SIZE;
4010 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4015 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4016 reta = IXGBE_READ_REG(hw, reta_reg);
4017 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4018 if (mask & (0x1 << j))
4019 reta_conf[idx].reta[shift + j] =
4020 ((reta >> (CHAR_BIT * j)) &
4029 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4030 uint32_t index, uint32_t pool)
4032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4033 uint32_t enable_addr = 1;
4035 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4039 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4043 ixgbe_clear_rar(hw, index);
4047 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4049 ixgbe_remove_rar(dev, 0);
4051 ixgbe_add_rar(dev, addr, 0, 0);
4055 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4056 struct ether_addr *mac_addr)
4058 struct ixgbe_hw *hw;
4059 struct ixgbe_vf_info *vfinfo;
4061 uint8_t *new_mac = (uint8_t *)(mac_addr);
4062 struct rte_eth_dev *dev;
4063 struct rte_eth_dev_info dev_info;
4065 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4067 dev = &rte_eth_devices[port];
4068 rte_eth_dev_info_get(port, &dev_info);
4070 if (vf >= dev_info.max_vfs)
4073 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4074 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4075 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4077 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4078 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4080 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4087 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4091 struct ixgbe_hw *hw;
4092 struct rte_eth_dev_info dev_info;
4093 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4094 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4096 ixgbe_dev_info_get(dev, &dev_info);
4098 /* check that mtu is within the allowed range */
4099 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4102 /* refuse mtu that requires the support of scattered packets when this
4103 * feature has not been enabled before.
4105 if (!rx_conf->enable_scatter &&
4106 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4107 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4110 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4111 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4113 /* switch to jumbo mode if needed */
4114 if (frame_size > ETHER_MAX_LEN) {
4115 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4116 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4118 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4119 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4121 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4123 /* update max frame size */
4124 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4126 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4127 maxfrs &= 0x0000FFFF;
4128 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4129 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4135 * Virtual Function operations
4138 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4140 PMD_INIT_FUNC_TRACE();
4142 /* Clear interrupt mask to stop from interrupts being generated */
4143 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4145 IXGBE_WRITE_FLUSH(hw);
4149 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4151 PMD_INIT_FUNC_TRACE();
4153 /* VF enable interrupt autoclean */
4154 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4155 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4156 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4158 IXGBE_WRITE_FLUSH(hw);
4162 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4164 struct rte_eth_conf *conf = &dev->data->dev_conf;
4165 struct ixgbe_adapter *adapter =
4166 (struct ixgbe_adapter *)dev->data->dev_private;
4168 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4169 dev->data->port_id);
4172 * VF has no ability to enable/disable HW CRC
4173 * Keep the persistent behavior the same as Host PF
4175 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4176 if (!conf->rxmode.hw_strip_crc) {
4177 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4178 conf->rxmode.hw_strip_crc = 1;
4181 if (conf->rxmode.hw_strip_crc) {
4182 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4183 conf->rxmode.hw_strip_crc = 0;
4188 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4189 * allocation or vector Rx preconditions we will reset it.
4191 adapter->rx_bulk_alloc_allowed = true;
4192 adapter->rx_vec_allowed = true;
4198 ixgbevf_dev_start(struct rte_eth_dev *dev)
4200 struct ixgbe_hw *hw =
4201 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202 uint32_t intr_vector = 0;
4203 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4207 PMD_INIT_FUNC_TRACE();
4209 hw->mac.ops.reset_hw(hw);
4210 hw->mac.get_link_status = true;
4212 /* negotiate mailbox API version to use with the PF. */
4213 ixgbevf_negotiate_api(hw);
4215 ixgbevf_dev_tx_init(dev);
4217 /* This can fail when allocating mbufs for descriptor rings */
4218 err = ixgbevf_dev_rx_init(dev);
4220 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4221 ixgbe_dev_clear_queues(dev);
4226 ixgbevf_set_vfta_all(dev, 1);
4229 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4230 ETH_VLAN_EXTEND_MASK;
4231 ixgbevf_vlan_offload_set(dev, mask);
4233 ixgbevf_dev_rxtx_start(dev);
4235 /* check and configure queue intr-vector mapping */
4236 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4237 intr_vector = dev->data->nb_rx_queues;
4238 if (rte_intr_efd_enable(intr_handle, intr_vector))
4242 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4243 intr_handle->intr_vec =
4244 rte_zmalloc("intr_vec",
4245 dev->data->nb_rx_queues * sizeof(int), 0);
4246 if (intr_handle->intr_vec == NULL) {
4247 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4248 " intr_vec\n", dev->data->nb_rx_queues);
4252 ixgbevf_configure_msix(dev);
4254 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
4255 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
4256 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
4257 * is not cleared, it will fail when following rte_intr_enable( ) tries
4258 * to map Rx queue interrupt to other VFIO vectors.
4259 * So clear uio/vfio intr/evevnfd first to avoid failure.
4261 rte_intr_disable(intr_handle);
4263 rte_intr_enable(intr_handle);
4265 /* Re-enable interrupt for VF */
4266 ixgbevf_intr_enable(hw);
4272 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4274 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4275 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4277 PMD_INIT_FUNC_TRACE();
4279 ixgbevf_intr_disable(hw);
4281 hw->adapter_stopped = 1;
4282 ixgbe_stop_adapter(hw);
4285 * Clear what we set, but we still keep shadow_vfta to
4286 * restore after device starts
4288 ixgbevf_set_vfta_all(dev, 0);
4290 /* Clear stored conf */
4291 dev->data->scattered_rx = 0;
4293 ixgbe_dev_clear_queues(dev);
4295 /* Clean datapath event and queue/vec mapping */
4296 rte_intr_efd_disable(intr_handle);
4297 if (intr_handle->intr_vec != NULL) {
4298 rte_free(intr_handle->intr_vec);
4299 intr_handle->intr_vec = NULL;
4304 ixgbevf_dev_close(struct rte_eth_dev *dev)
4306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4308 PMD_INIT_FUNC_TRACE();
4312 ixgbevf_dev_stop(dev);
4314 ixgbe_dev_free_queues(dev);
4317 * Remove the VF MAC address ro ensure
4318 * that the VF traffic goes to the PF
4319 * after stop, close and detach of the VF
4321 ixgbevf_remove_mac_addr(dev, 0);
4324 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327 struct ixgbe_vfta *shadow_vfta =
4328 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4329 int i = 0, j = 0, vfta = 0, mask = 1;
4331 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4332 vfta = shadow_vfta->vfta[i];
4335 for (j = 0; j < 32; j++) {
4337 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4347 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4349 struct ixgbe_hw *hw =
4350 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351 struct ixgbe_vfta *shadow_vfta =
4352 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4353 uint32_t vid_idx = 0;
4354 uint32_t vid_bit = 0;
4357 PMD_INIT_FUNC_TRACE();
4359 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4360 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4362 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4365 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4366 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4368 /* Save what we set and retore it after device reset */
4370 shadow_vfta->vfta[vid_idx] |= vid_bit;
4372 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4378 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4380 struct ixgbe_hw *hw =
4381 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384 PMD_INIT_FUNC_TRACE();
4386 if (queue >= hw->mac.max_rx_queues)
4389 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4391 ctrl |= IXGBE_RXDCTL_VME;
4393 ctrl &= ~IXGBE_RXDCTL_VME;
4394 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4396 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4400 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4402 struct ixgbe_hw *hw =
4403 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407 /* VF function only support hw strip feature, others are not support */
4408 if (mask & ETH_VLAN_STRIP_MASK) {
4409 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4411 for (i = 0; i < hw->mac.max_rx_queues; i++)
4412 ixgbevf_vlan_strip_queue_set(dev, i, on);
4417 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4421 /* we only need to do this if VMDq is enabled */
4422 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4423 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4424 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4432 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4434 uint32_t vector = 0;
4436 switch (hw->mac.mc_filter_type) {
4437 case 0: /* use bits [47:36] of the address */
4438 vector = ((uc_addr->addr_bytes[4] >> 4) |
4439 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4441 case 1: /* use bits [46:35] of the address */
4442 vector = ((uc_addr->addr_bytes[4] >> 3) |
4443 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4445 case 2: /* use bits [45:34] of the address */
4446 vector = ((uc_addr->addr_bytes[4] >> 2) |
4447 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4449 case 3: /* use bits [43:32] of the address */
4450 vector = ((uc_addr->addr_bytes[4]) |
4451 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4453 default: /* Invalid mc_filter_type */
4457 /* vector can only be 12-bits or boundary will be exceeded */
4463 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4471 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4472 const uint32_t ixgbe_uta_bit_shift = 5;
4473 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4474 const uint32_t bit1 = 0x1;
4476 struct ixgbe_hw *hw =
4477 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478 struct ixgbe_uta_info *uta_info =
4479 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4481 /* The UTA table only exists on 82599 hardware and newer */
4482 if (hw->mac.type < ixgbe_mac_82599EB)
4485 vector = ixgbe_uta_vector(hw, mac_addr);
4486 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4487 uta_shift = vector & ixgbe_uta_bit_mask;
4489 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4493 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4495 uta_info->uta_in_use++;
4496 reg_val |= (bit1 << uta_shift);
4497 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4499 uta_info->uta_in_use--;
4500 reg_val &= ~(bit1 << uta_shift);
4501 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4504 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4506 if (uta_info->uta_in_use > 0)
4507 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4508 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4510 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4516 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4519 struct ixgbe_hw *hw =
4520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521 struct ixgbe_uta_info *uta_info =
4522 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4524 /* The UTA table only exists on 82599 hardware and newer */
4525 if (hw->mac.type < ixgbe_mac_82599EB)
4529 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4530 uta_info->uta_shadow[i] = ~0;
4531 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4534 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4535 uta_info->uta_shadow[i] = 0;
4536 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4544 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4546 uint32_t new_val = orig_val;
4548 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4549 new_val |= IXGBE_VMOLR_AUPE;
4550 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4551 new_val |= IXGBE_VMOLR_ROMPE;
4552 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4553 new_val |= IXGBE_VMOLR_ROPE;
4554 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4555 new_val |= IXGBE_VMOLR_BAM;
4556 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4557 new_val |= IXGBE_VMOLR_MPE;
4563 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4564 uint16_t rx_mask, uint8_t on)
4568 struct ixgbe_hw *hw =
4569 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4572 if (hw->mac.type == ixgbe_mac_82598EB) {
4573 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4574 " on 82599 hardware and newer");
4577 if (ixgbe_vmdq_mode_check(hw) < 0)
4580 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4587 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4593 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4597 const uint8_t bit1 = 0x1;
4599 struct ixgbe_hw *hw =
4600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602 if (ixgbe_vmdq_mode_check(hw) < 0)
4605 if (pool >= ETH_64_POOLS)
4608 /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4610 addr = IXGBE_VFRE(1);
4611 val = bit1 << (pool - 32);
4613 addr = IXGBE_VFRE(0);
4617 reg = IXGBE_READ_REG(hw, addr);
4624 IXGBE_WRITE_REG(hw, addr, reg);
4630 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4634 const uint8_t bit1 = 0x1;
4636 struct ixgbe_hw *hw =
4637 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639 if (ixgbe_vmdq_mode_check(hw) < 0)
4642 if (pool >= ETH_64_POOLS)
4645 /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4647 addr = IXGBE_VFTE(1);
4648 val = bit1 << (pool - 32);
4650 addr = IXGBE_VFTE(0);
4654 reg = IXGBE_READ_REG(hw, addr);
4661 IXGBE_WRITE_REG(hw, addr, reg);
4667 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4668 uint64_t pool_mask, uint8_t vlan_on)
4672 struct ixgbe_hw *hw =
4673 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4675 if (ixgbe_vmdq_mode_check(hw) < 0)
4677 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4678 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4679 ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4690 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4692 struct ixgbe_hw *hw;
4693 struct ixgbe_mac_info *mac;
4694 struct rte_eth_dev *dev;
4695 struct rte_eth_dev_info dev_info;
4697 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4699 dev = &rte_eth_devices[port];
4700 rte_eth_dev_info_get(port, &dev_info);
4702 if (vf >= dev_info.max_vfs)
4708 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4717 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4719 struct ixgbe_hw *hw;
4720 struct ixgbe_mac_info *mac;
4721 struct rte_eth_dev *dev;
4722 struct rte_eth_dev_info dev_info;
4724 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4726 dev = &rte_eth_devices[port];
4727 rte_eth_dev_info_get(port, &dev_info);
4729 if (vf >= dev_info.max_vfs)
4735 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4743 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4745 struct ixgbe_hw *hw;
4747 struct rte_eth_dev *dev;
4748 struct rte_eth_dev_info dev_info;
4750 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4752 dev = &rte_eth_devices[port];
4753 rte_eth_dev_info_get(port, &dev_info);
4755 if (vf >= dev_info.max_vfs)
4761 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4762 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4765 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4770 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4776 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4778 struct ixgbe_hw *hw;
4780 struct rte_eth_dev *dev;
4782 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4784 dev = &rte_eth_devices[port];
4789 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4791 /* enable or disable VMDQ loopback */
4793 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4795 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4797 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4803 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4805 struct ixgbe_hw *hw;
4808 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4809 struct rte_eth_dev *dev;
4811 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4813 dev = &rte_eth_devices[port];
4818 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4819 for (i = 0; i <= num_queues; i++) {
4820 reg_value = IXGBE_QDE_WRITE |
4821 (i << IXGBE_QDE_IDX_SHIFT) |
4822 (on & IXGBE_QDE_ENABLE);
4823 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4830 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4832 struct ixgbe_hw *hw;
4834 struct rte_eth_dev *dev;
4835 struct rte_eth_dev_info dev_info;
4837 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4839 dev = &rte_eth_devices[port];
4840 rte_eth_dev_info_get(port, &dev_info);
4842 /* only support VF's 0 to 63 */
4843 if ((vf >= dev_info.max_vfs) || (vf > 63))
4849 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4852 reg_value |= IXGBE_SRRCTL_DROP_EN;
4854 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4856 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4862 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4864 struct rte_eth_dev *dev;
4865 struct rte_eth_dev_info dev_info;
4866 uint16_t queues_per_pool;
4869 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4871 dev = &rte_eth_devices[port];
4872 rte_eth_dev_info_get(port, &dev_info);
4874 if (vf >= dev_info.max_vfs)
4880 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4882 /* The PF has 128 queue pairs and in SRIOV configuration
4883 * those queues will be assigned to VF's, so RXDCTL
4884 * registers will be dealing with queues which will be
4886 * Let's say we have SRIOV configured with 31 VF's then the
4887 * first 124 queues 0-123 will be allocated to VF's and only
4888 * the last 4 queues 123-127 will be assigned to the PF.
4891 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4893 for (q = 0; q < queues_per_pool; q++)
4894 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4895 q + vf * queues_per_pool, on);
4899 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4900 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4901 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4902 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4903 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4904 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4905 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4908 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4909 struct rte_eth_mirror_conf *mirror_conf,
4910 uint8_t rule_id, uint8_t on)
4912 uint32_t mr_ctl, vlvf;
4913 uint32_t mp_lsb = 0;
4914 uint32_t mv_msb = 0;
4915 uint32_t mv_lsb = 0;
4916 uint32_t mp_msb = 0;
4919 uint64_t vlan_mask = 0;
4921 const uint8_t pool_mask_offset = 32;
4922 const uint8_t vlan_mask_offset = 32;
4923 const uint8_t dst_pool_offset = 8;
4924 const uint8_t rule_mr_offset = 4;
4925 const uint8_t mirror_rule_mask = 0x0F;
4927 struct ixgbe_mirror_info *mr_info =
4928 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4929 struct ixgbe_hw *hw =
4930 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4931 uint8_t mirror_type = 0;
4933 if (ixgbe_vmdq_mode_check(hw) < 0)
4936 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4939 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4940 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4941 mirror_conf->rule_type);
4945 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4946 mirror_type |= IXGBE_MRCTL_VLME;
4947 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4948 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4949 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4950 /* search vlan id related pool vlan filter index */
4951 reg_index = ixgbe_find_vlvf_slot(hw,
4952 mirror_conf->vlan.vlan_id[i],
4956 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4957 if ((vlvf & IXGBE_VLVF_VIEN) &&
4958 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4959 mirror_conf->vlan.vlan_id[i]))
4960 vlan_mask |= (1ULL << reg_index);
4967 mv_lsb = vlan_mask & 0xFFFFFFFF;
4968 mv_msb = vlan_mask >> vlan_mask_offset;
4970 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4971 mirror_conf->vlan.vlan_mask;
4972 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4973 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4974 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4975 mirror_conf->vlan.vlan_id[i];
4980 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4981 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4982 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4987 * if enable pool mirror, write related pool mask register,if disable
4988 * pool mirror, clear PFMRVM register
4990 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4991 mirror_type |= IXGBE_MRCTL_VPME;
4993 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4994 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4995 mr_info->mr_conf[rule_id].pool_mask =
4996 mirror_conf->pool_mask;
5001 mr_info->mr_conf[rule_id].pool_mask = 0;
5004 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5005 mirror_type |= IXGBE_MRCTL_UPME;
5006 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5007 mirror_type |= IXGBE_MRCTL_DPME;
5009 /* read mirror control register and recalculate it */
5010 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5013 mr_ctl |= mirror_type;
5014 mr_ctl &= mirror_rule_mask;
5015 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5017 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5019 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5020 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5022 /* write mirrror control register */
5023 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5025 /* write pool mirrror control register */
5026 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5027 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5028 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5031 /* write VLAN mirrror control register */
5032 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5033 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5034 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5042 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5045 uint32_t lsb_val = 0;
5046 uint32_t msb_val = 0;
5047 const uint8_t rule_mr_offset = 4;
5049 struct ixgbe_hw *hw =
5050 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051 struct ixgbe_mirror_info *mr_info =
5052 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5054 if (ixgbe_vmdq_mode_check(hw) < 0)
5057 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5060 memset(&mr_info->mr_conf[rule_id], 0,
5061 sizeof(struct rte_eth_mirror_conf));
5063 /* clear PFVMCTL register */
5064 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5066 /* clear pool mask register */
5067 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5068 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5070 /* clear vlan mask register */
5071 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5072 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5078 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5081 struct ixgbe_hw *hw =
5082 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5085 mask |= (1 << IXGBE_MISC_VEC_ID);
5086 RTE_SET_USED(queue_id);
5087 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5089 rte_intr_enable(&dev->pci_dev->intr_handle);
5095 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5098 struct ixgbe_hw *hw =
5099 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5101 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5102 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5103 RTE_SET_USED(queue_id);
5104 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5110 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5113 struct ixgbe_hw *hw =
5114 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115 struct ixgbe_interrupt *intr =
5116 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5118 if (queue_id < 16) {
5119 ixgbe_disable_intr(hw);
5120 intr->mask |= (1 << queue_id);
5121 ixgbe_enable_intr(dev);
5122 } else if (queue_id < 32) {
5123 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5124 mask &= (1 << queue_id);
5125 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5126 } else if (queue_id < 64) {
5127 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5128 mask &= (1 << (queue_id - 32));
5129 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5131 rte_intr_enable(&dev->pci_dev->intr_handle);
5137 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5140 struct ixgbe_hw *hw =
5141 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142 struct ixgbe_interrupt *intr =
5143 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5145 if (queue_id < 16) {
5146 ixgbe_disable_intr(hw);
5147 intr->mask &= ~(1 << queue_id);
5148 ixgbe_enable_intr(dev);
5149 } else if (queue_id < 32) {
5150 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5151 mask &= ~(1 << queue_id);
5152 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5153 } else if (queue_id < 64) {
5154 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5155 mask &= ~(1 << (queue_id - 32));
5156 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5163 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5164 uint8_t queue, uint8_t msix_vector)
5168 if (direction == -1) {
5170 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5171 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5174 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5176 /* rx or tx cause */
5177 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5178 idx = ((16 * (queue & 1)) + (8 * direction));
5179 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5180 tmp &= ~(0xFF << idx);
5181 tmp |= (msix_vector << idx);
5182 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5187 * set the IVAR registers, mapping interrupt causes to vectors
5189 * pointer to ixgbe_hw struct
5191 * 0 for Rx, 1 for Tx, -1 for other causes
5193 * queue to map the corresponding interrupt to
5195 * the vector to map to the corresponding queue
5198 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5199 uint8_t queue, uint8_t msix_vector)
5203 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5204 if (hw->mac.type == ixgbe_mac_82598EB) {
5205 if (direction == -1)
5207 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5208 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5209 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5210 tmp |= (msix_vector << (8 * (queue & 0x3)));
5211 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5212 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5213 (hw->mac.type == ixgbe_mac_X540) ||
5214 (hw->mac.type == ixgbe_mac_X550)) {
5215 if (direction == -1) {
5217 idx = ((queue & 1) * 8);
5218 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5219 tmp &= ~(0xFF << idx);
5220 tmp |= (msix_vector << idx);
5221 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5223 /* rx or tx causes */
5224 idx = ((16 * (queue & 1)) + (8 * direction));
5225 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5226 tmp &= ~(0xFF << idx);
5227 tmp |= (msix_vector << idx);
5228 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5234 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5236 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5237 struct ixgbe_hw *hw =
5238 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5242 /* Configure VF other cause ivar */
5243 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5245 /* won't configure msix register if no mapping is done
5246 * between intr vector and event fd.
5248 if (!rte_intr_dp_is_en(intr_handle))
5251 /* Configure all RX queues of VF */
5252 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5253 /* Force all queue use vector 0,
5254 * as IXGBE_VF_MAXMSIVECOTR = 1
5256 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5257 intr_handle->intr_vec[q_idx] = vector_idx;
5262 * Sets up the hardware to properly generate MSI-X interrupts
5264 * board private structure
5267 ixgbe_configure_msix(struct rte_eth_dev *dev)
5269 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5270 struct ixgbe_hw *hw =
5271 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5273 uint32_t vec = IXGBE_MISC_VEC_ID;
5277 /* won't configure msix register if no mapping is done
5278 * between intr vector and event fd
5280 if (!rte_intr_dp_is_en(intr_handle))
5283 if (rte_intr_allow_others(intr_handle))
5284 vec = base = IXGBE_RX_VEC_START;
5286 /* setup GPIE for MSI-x mode */
5287 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5288 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5289 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5290 /* auto clearing and auto setting corresponding bits in EIMS
5291 * when MSI-X interrupt is triggered
5293 if (hw->mac.type == ixgbe_mac_82598EB) {
5294 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5296 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5297 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5299 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5301 /* Populate the IVAR table and set the ITR values to the
5302 * corresponding register.
5304 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5306 /* by default, 1:1 mapping */
5307 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5308 intr_handle->intr_vec[queue_id] = vec;
5309 if (vec < base + intr_handle->nb_efd - 1)
5313 switch (hw->mac.type) {
5314 case ixgbe_mac_82598EB:
5315 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5318 case ixgbe_mac_82599EB:
5319 case ixgbe_mac_X540:
5320 case ixgbe_mac_X550:
5321 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5326 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5327 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5329 /* set up to autoclear timer, and the vectors */
5330 mask = IXGBE_EIMS_ENABLE_MASK;
5331 mask &= ~(IXGBE_EIMS_OTHER |
5332 IXGBE_EIMS_MAILBOX |
5335 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5338 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5339 uint16_t queue_idx, uint16_t tx_rate)
5341 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5342 uint32_t rf_dec, rf_int;
5344 uint16_t link_speed = dev->data->dev_link.link_speed;
5346 if (queue_idx >= hw->mac.max_tx_queues)
5350 /* Calculate the rate factor values to set */
5351 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5352 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5353 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5355 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5356 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5357 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5358 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5364 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5365 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5368 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5369 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5370 IXGBE_MAX_JUMBO_FRAME_SIZE))
5371 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5372 IXGBE_MMW_SIZE_JUMBO_FRAME);
5374 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5375 IXGBE_MMW_SIZE_DEFAULT);
5377 /* Set RTTBCNRC of queue X */
5378 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5379 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5380 IXGBE_WRITE_FLUSH(hw);
5385 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5386 uint16_t tx_rate, uint64_t q_msk)
5388 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389 struct ixgbe_vf_info *vfinfo =
5390 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5391 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5392 uint32_t queue_stride =
5393 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5394 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5395 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5396 uint16_t total_rate = 0;
5398 if (queue_end >= hw->mac.max_tx_queues)
5401 if (vfinfo != NULL) {
5402 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5405 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5407 total_rate += vfinfo[vf_idx].tx_rate[idx];
5412 /* Store tx_rate for this vf. */
5413 for (idx = 0; idx < nb_q_per_pool; idx++) {
5414 if (((uint64_t)0x1 << idx) & q_msk) {
5415 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5416 vfinfo[vf].tx_rate[idx] = tx_rate;
5417 total_rate += tx_rate;
5421 if (total_rate > dev->data->dev_link.link_speed) {
5423 * Reset stored TX rate of the VF if it causes exceed
5426 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5430 /* Set RTTBCNRC of each queue/pool for vf X */
5431 for (; queue_idx <= queue_end; queue_idx++) {
5433 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5441 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5442 __attribute__((unused)) uint32_t index,
5443 __attribute__((unused)) uint32_t pool)
5445 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5449 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5450 * operation. Trap this case to avoid exhausting the [very limited]
5451 * set of PF resources used to store VF MAC addresses.
5453 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5455 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5458 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5462 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5464 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5465 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5466 struct ether_addr *mac_addr;
5471 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5472 * not support the deletion of a given MAC address.
5473 * Instead, it imposes to delete all MAC addresses, then to add again
5474 * all MAC addresses with the exception of the one to be deleted.
5476 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5479 * Add again all MAC addresses, with the exception of the deleted one
5480 * and of the permanent MAC address.
5482 for (i = 0, mac_addr = dev->data->mac_addrs;
5483 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5484 /* Skip the deleted MAC address */
5487 /* Skip NULL MAC addresses */
5488 if (is_zero_ether_addr(mac_addr))
5490 /* Skip the permanent MAC address */
5491 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5493 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5496 "Adding again MAC address "
5497 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5499 mac_addr->addr_bytes[0],
5500 mac_addr->addr_bytes[1],
5501 mac_addr->addr_bytes[2],
5502 mac_addr->addr_bytes[3],
5503 mac_addr->addr_bytes[4],
5504 mac_addr->addr_bytes[5],
5510 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5512 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5517 #define MAC_TYPE_FILTER_SUP(type) do {\
5518 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5519 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5520 (type) != ixgbe_mac_X550EM_a)\
5525 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5526 struct rte_eth_syn_filter *filter,
5529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5535 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5538 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5540 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5541 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5543 if (filter->hig_pri)
5544 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5546 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5548 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5550 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5552 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5553 IXGBE_WRITE_FLUSH(hw);
5558 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5559 struct rte_eth_syn_filter *filter)
5561 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5562 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5564 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5565 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5566 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5573 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5574 enum rte_filter_op filter_op,
5577 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5580 MAC_TYPE_FILTER_SUP(hw->mac.type);
5582 if (filter_op == RTE_ETH_FILTER_NOP)
5586 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5591 switch (filter_op) {
5592 case RTE_ETH_FILTER_ADD:
5593 ret = ixgbe_syn_filter_set(dev,
5594 (struct rte_eth_syn_filter *)arg,
5597 case RTE_ETH_FILTER_DELETE:
5598 ret = ixgbe_syn_filter_set(dev,
5599 (struct rte_eth_syn_filter *)arg,
5602 case RTE_ETH_FILTER_GET:
5603 ret = ixgbe_syn_filter_get(dev,
5604 (struct rte_eth_syn_filter *)arg);
5607 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5616 static inline enum ixgbe_5tuple_protocol
5617 convert_protocol_type(uint8_t protocol_value)
5619 if (protocol_value == IPPROTO_TCP)
5620 return IXGBE_FILTER_PROTOCOL_TCP;
5621 else if (protocol_value == IPPROTO_UDP)
5622 return IXGBE_FILTER_PROTOCOL_UDP;
5623 else if (protocol_value == IPPROTO_SCTP)
5624 return IXGBE_FILTER_PROTOCOL_SCTP;
5626 return IXGBE_FILTER_PROTOCOL_NONE;
5630 * add a 5tuple filter
5633 * dev: Pointer to struct rte_eth_dev.
5634 * index: the index the filter allocates.
5635 * filter: ponter to the filter that will be added.
5636 * rx_queue: the queue id the filter assigned to.
5639 * - On success, zero.
5640 * - On failure, a negative value.
5643 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5644 struct ixgbe_5tuple_filter *filter)
5646 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5647 struct ixgbe_filter_info *filter_info =
5648 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5650 uint32_t ftqf, sdpqf;
5651 uint32_t l34timir = 0;
5652 uint8_t mask = 0xff;
5655 * look for an unused 5tuple filter index,
5656 * and insert the filter to list.
5658 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5659 idx = i / (sizeof(uint32_t) * NBBY);
5660 shift = i % (sizeof(uint32_t) * NBBY);
5661 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5662 filter_info->fivetuple_mask[idx] |= 1 << shift;
5664 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5670 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5671 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5675 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5676 IXGBE_SDPQF_DSTPORT_SHIFT);
5677 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5679 ftqf = (uint32_t)(filter->filter_info.proto &
5680 IXGBE_FTQF_PROTOCOL_MASK);
5681 ftqf |= (uint32_t)((filter->filter_info.priority &
5682 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5683 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5684 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5685 if (filter->filter_info.dst_ip_mask == 0)
5686 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5687 if (filter->filter_info.src_port_mask == 0)
5688 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5689 if (filter->filter_info.dst_port_mask == 0)
5690 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5691 if (filter->filter_info.proto_mask == 0)
5692 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5693 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5694 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5695 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5697 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5698 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5699 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5700 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5702 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5703 l34timir |= (uint32_t)(filter->queue <<
5704 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5705 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5710 * remove a 5tuple filter
5713 * dev: Pointer to struct rte_eth_dev.
5714 * filter: the pointer of the filter will be removed.
5717 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5718 struct ixgbe_5tuple_filter *filter)
5720 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721 struct ixgbe_filter_info *filter_info =
5722 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5723 uint16_t index = filter->index;
5725 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5726 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5727 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5730 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5731 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5732 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5733 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5734 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5738 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5740 struct ixgbe_hw *hw;
5741 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5742 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5744 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5749 /* refuse mtu that requires the support of scattered packets when this
5750 * feature has not been enabled before.
5752 if (!rx_conf->enable_scatter &&
5753 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5754 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5758 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5759 * request of the version 2.0 of the mailbox API.
5760 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5761 * of the mailbox API.
5762 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5763 * prior to 3.11.33 which contains the following change:
5764 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5766 ixgbevf_rlpml_set_vf(hw, max_frame);
5768 /* update max frame size */
5769 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5773 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5774 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5778 static inline struct ixgbe_5tuple_filter *
5779 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5780 struct ixgbe_5tuple_filter_info *key)
5782 struct ixgbe_5tuple_filter *it;
5784 TAILQ_FOREACH(it, filter_list, entries) {
5785 if (memcmp(key, &it->filter_info,
5786 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5793 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5795 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5796 struct ixgbe_5tuple_filter_info *filter_info)
5798 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5799 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5800 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5803 switch (filter->dst_ip_mask) {
5805 filter_info->dst_ip_mask = 0;
5806 filter_info->dst_ip = filter->dst_ip;
5809 filter_info->dst_ip_mask = 1;
5812 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5816 switch (filter->src_ip_mask) {
5818 filter_info->src_ip_mask = 0;
5819 filter_info->src_ip = filter->src_ip;
5822 filter_info->src_ip_mask = 1;
5825 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5829 switch (filter->dst_port_mask) {
5831 filter_info->dst_port_mask = 0;
5832 filter_info->dst_port = filter->dst_port;
5835 filter_info->dst_port_mask = 1;
5838 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5842 switch (filter->src_port_mask) {
5844 filter_info->src_port_mask = 0;
5845 filter_info->src_port = filter->src_port;
5848 filter_info->src_port_mask = 1;
5851 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5855 switch (filter->proto_mask) {
5857 filter_info->proto_mask = 0;
5858 filter_info->proto =
5859 convert_protocol_type(filter->proto);
5862 filter_info->proto_mask = 1;
5865 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5869 filter_info->priority = (uint8_t)filter->priority;
5874 * add or delete a ntuple filter
5877 * dev: Pointer to struct rte_eth_dev.
5878 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5879 * add: if true, add filter, if false, remove filter
5882 * - On success, zero.
5883 * - On failure, a negative value.
5886 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5887 struct rte_eth_ntuple_filter *ntuple_filter,
5890 struct ixgbe_filter_info *filter_info =
5891 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5892 struct ixgbe_5tuple_filter_info filter_5tuple;
5893 struct ixgbe_5tuple_filter *filter;
5896 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5897 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5901 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5902 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5906 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5908 if (filter != NULL && add) {
5909 PMD_DRV_LOG(ERR, "filter exists.");
5912 if (filter == NULL && !add) {
5913 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5918 filter = rte_zmalloc("ixgbe_5tuple_filter",
5919 sizeof(struct ixgbe_5tuple_filter), 0);
5922 (void)rte_memcpy(&filter->filter_info,
5924 sizeof(struct ixgbe_5tuple_filter_info));
5925 filter->queue = ntuple_filter->queue;
5926 ret = ixgbe_add_5tuple_filter(dev, filter);
5932 ixgbe_remove_5tuple_filter(dev, filter);
5938 * get a ntuple filter
5941 * dev: Pointer to struct rte_eth_dev.
5942 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5945 * - On success, zero.
5946 * - On failure, a negative value.
5949 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5950 struct rte_eth_ntuple_filter *ntuple_filter)
5952 struct ixgbe_filter_info *filter_info =
5953 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5954 struct ixgbe_5tuple_filter_info filter_5tuple;
5955 struct ixgbe_5tuple_filter *filter;
5958 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5959 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5963 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5964 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5968 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5970 if (filter == NULL) {
5971 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5974 ntuple_filter->queue = filter->queue;
5979 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5980 * @dev: pointer to rte_eth_dev structure
5981 * @filter_op:operation will be taken.
5982 * @arg: a pointer to specific structure corresponding to the filter_op
5985 * - On success, zero.
5986 * - On failure, a negative value.
5989 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5990 enum rte_filter_op filter_op,
5993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5998 if (filter_op == RTE_ETH_FILTER_NOP)
6002 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6007 switch (filter_op) {
6008 case RTE_ETH_FILTER_ADD:
6009 ret = ixgbe_add_del_ntuple_filter(dev,
6010 (struct rte_eth_ntuple_filter *)arg,
6013 case RTE_ETH_FILTER_DELETE:
6014 ret = ixgbe_add_del_ntuple_filter(dev,
6015 (struct rte_eth_ntuple_filter *)arg,
6018 case RTE_ETH_FILTER_GET:
6019 ret = ixgbe_get_ntuple_filter(dev,
6020 (struct rte_eth_ntuple_filter *)arg);
6023 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6031 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6036 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6037 if (filter_info->ethertype_filters[i] == ethertype &&
6038 (filter_info->ethertype_mask & (1 << i)))
6045 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6050 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6051 if (!(filter_info->ethertype_mask & (1 << i))) {
6052 filter_info->ethertype_mask |= 1 << i;
6053 filter_info->ethertype_filters[i] = ethertype;
6061 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6064 if (idx >= IXGBE_MAX_ETQF_FILTERS)
6066 filter_info->ethertype_mask &= ~(1 << idx);
6067 filter_info->ethertype_filters[idx] = 0;
6072 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6073 struct rte_eth_ethertype_filter *filter,
6076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077 struct ixgbe_filter_info *filter_info =
6078 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6083 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6086 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6087 filter->ether_type == ETHER_TYPE_IPv6) {
6088 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6089 " ethertype filter.", filter->ether_type);
6093 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6094 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6097 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6098 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6102 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6103 if (ret >= 0 && add) {
6104 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6105 filter->ether_type);
6108 if (ret < 0 && !add) {
6109 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6110 filter->ether_type);
6115 ret = ixgbe_ethertype_filter_insert(filter_info,
6116 filter->ether_type);
6118 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6121 etqf = IXGBE_ETQF_FILTER_EN;
6122 etqf |= (uint32_t)filter->ether_type;
6123 etqs |= (uint32_t)((filter->queue <<
6124 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6125 IXGBE_ETQS_RX_QUEUE);
6126 etqs |= IXGBE_ETQS_QUEUE_EN;
6128 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6132 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6133 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6134 IXGBE_WRITE_FLUSH(hw);
6140 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6141 struct rte_eth_ethertype_filter *filter)
6143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6144 struct ixgbe_filter_info *filter_info =
6145 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6146 uint32_t etqf, etqs;
6149 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6151 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6152 filter->ether_type);
6156 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6157 if (etqf & IXGBE_ETQF_FILTER_EN) {
6158 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6159 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6161 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6162 IXGBE_ETQS_RX_QUEUE_SHIFT;
6169 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6170 * @dev: pointer to rte_eth_dev structure
6171 * @filter_op:operation will be taken.
6172 * @arg: a pointer to specific structure corresponding to the filter_op
6175 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6176 enum rte_filter_op filter_op,
6179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6182 MAC_TYPE_FILTER_SUP(hw->mac.type);
6184 if (filter_op == RTE_ETH_FILTER_NOP)
6188 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6193 switch (filter_op) {
6194 case RTE_ETH_FILTER_ADD:
6195 ret = ixgbe_add_del_ethertype_filter(dev,
6196 (struct rte_eth_ethertype_filter *)arg,
6199 case RTE_ETH_FILTER_DELETE:
6200 ret = ixgbe_add_del_ethertype_filter(dev,
6201 (struct rte_eth_ethertype_filter *)arg,
6204 case RTE_ETH_FILTER_GET:
6205 ret = ixgbe_get_ethertype_filter(dev,
6206 (struct rte_eth_ethertype_filter *)arg);
6209 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6217 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6218 enum rte_filter_type filter_type,
6219 enum rte_filter_op filter_op,
6224 switch (filter_type) {
6225 case RTE_ETH_FILTER_NTUPLE:
6226 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6228 case RTE_ETH_FILTER_ETHERTYPE:
6229 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6231 case RTE_ETH_FILTER_SYN:
6232 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6234 case RTE_ETH_FILTER_FDIR:
6235 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6237 case RTE_ETH_FILTER_L2_TUNNEL:
6238 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6241 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6250 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6251 u8 **mc_addr_ptr, u32 *vmdq)
6256 mc_addr = *mc_addr_ptr;
6257 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6262 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6263 struct ether_addr *mc_addr_set,
6264 uint32_t nb_mc_addr)
6266 struct ixgbe_hw *hw;
6269 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6270 mc_addr_list = (u8 *)mc_addr_set;
6271 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6272 ixgbe_dev_addr_list_itr, TRUE);
6276 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6279 uint64_t systime_cycles;
6281 switch (hw->mac.type) {
6282 case ixgbe_mac_X550:
6283 case ixgbe_mac_X550EM_x:
6284 case ixgbe_mac_X550EM_a:
6285 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6286 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6287 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6291 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6292 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6296 return systime_cycles;
6300 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6303 uint64_t rx_tstamp_cycles;
6305 switch (hw->mac.type) {
6306 case ixgbe_mac_X550:
6307 case ixgbe_mac_X550EM_x:
6308 case ixgbe_mac_X550EM_a:
6309 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6310 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6311 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6315 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6316 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6317 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6321 return rx_tstamp_cycles;
6325 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6328 uint64_t tx_tstamp_cycles;
6330 switch (hw->mac.type) {
6331 case ixgbe_mac_X550:
6332 case ixgbe_mac_X550EM_x:
6333 case ixgbe_mac_X550EM_a:
6334 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6335 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6336 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6340 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6341 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6342 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6346 return tx_tstamp_cycles;
6350 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6352 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6353 struct ixgbe_adapter *adapter =
6354 (struct ixgbe_adapter *)dev->data->dev_private;
6355 struct rte_eth_link link;
6356 uint32_t incval = 0;
6359 /* Get current link speed. */
6360 memset(&link, 0, sizeof(link));
6361 ixgbe_dev_link_update(dev, 1);
6362 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6364 switch (link.link_speed) {
6365 case ETH_SPEED_NUM_100M:
6366 incval = IXGBE_INCVAL_100;
6367 shift = IXGBE_INCVAL_SHIFT_100;
6369 case ETH_SPEED_NUM_1G:
6370 incval = IXGBE_INCVAL_1GB;
6371 shift = IXGBE_INCVAL_SHIFT_1GB;
6373 case ETH_SPEED_NUM_10G:
6375 incval = IXGBE_INCVAL_10GB;
6376 shift = IXGBE_INCVAL_SHIFT_10GB;
6380 switch (hw->mac.type) {
6381 case ixgbe_mac_X550:
6382 case ixgbe_mac_X550EM_x:
6383 case ixgbe_mac_X550EM_a:
6384 /* Independent of link speed. */
6386 /* Cycles read will be interpreted as ns. */
6389 case ixgbe_mac_X540:
6390 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6392 case ixgbe_mac_82599EB:
6393 incval >>= IXGBE_INCVAL_SHIFT_82599;
6394 shift -= IXGBE_INCVAL_SHIFT_82599;
6395 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6396 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6399 /* Not supported. */
6403 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6404 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6405 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6407 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6408 adapter->systime_tc.cc_shift = shift;
6409 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6411 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6412 adapter->rx_tstamp_tc.cc_shift = shift;
6413 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6415 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6416 adapter->tx_tstamp_tc.cc_shift = shift;
6417 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6421 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6423 struct ixgbe_adapter *adapter =
6424 (struct ixgbe_adapter *)dev->data->dev_private;
6426 adapter->systime_tc.nsec += delta;
6427 adapter->rx_tstamp_tc.nsec += delta;
6428 adapter->tx_tstamp_tc.nsec += delta;
6434 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6437 struct ixgbe_adapter *adapter =
6438 (struct ixgbe_adapter *)dev->data->dev_private;
6440 ns = rte_timespec_to_ns(ts);
6441 /* Set the timecounters to a new value. */
6442 adapter->systime_tc.nsec = ns;
6443 adapter->rx_tstamp_tc.nsec = ns;
6444 adapter->tx_tstamp_tc.nsec = ns;
6450 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6452 uint64_t ns, systime_cycles;
6453 struct ixgbe_adapter *adapter =
6454 (struct ixgbe_adapter *)dev->data->dev_private;
6456 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6457 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6458 *ts = rte_ns_to_timespec(ns);
6464 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6466 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470 /* Stop the timesync system time. */
6471 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6472 /* Reset the timesync system time value. */
6473 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6474 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6476 /* Enable system time for platforms where it isn't on by default. */
6477 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6478 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6479 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6481 ixgbe_start_timecounters(dev);
6483 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6484 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6486 IXGBE_ETQF_FILTER_EN |
6489 /* Enable timestamping of received PTP packets. */
6490 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6491 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6492 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6494 /* Enable timestamping of transmitted PTP packets. */
6495 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6496 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6497 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6499 IXGBE_WRITE_FLUSH(hw);
6505 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6507 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6510 /* Disable timestamping of transmitted PTP packets. */
6511 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6512 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6513 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6515 /* Disable timestamping of received PTP packets. */
6516 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6517 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6518 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6520 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6521 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6523 /* Stop incrementating the System Time registers. */
6524 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6530 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6531 struct timespec *timestamp,
6532 uint32_t flags __rte_unused)
6534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6535 struct ixgbe_adapter *adapter =
6536 (struct ixgbe_adapter *)dev->data->dev_private;
6537 uint32_t tsync_rxctl;
6538 uint64_t rx_tstamp_cycles;
6541 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6542 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6545 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6546 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6547 *timestamp = rte_ns_to_timespec(ns);
6553 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6554 struct timespec *timestamp)
6556 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6557 struct ixgbe_adapter *adapter =
6558 (struct ixgbe_adapter *)dev->data->dev_private;
6559 uint32_t tsync_txctl;
6560 uint64_t tx_tstamp_cycles;
6563 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6564 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6567 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6568 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6569 *timestamp = rte_ns_to_timespec(ns);
6575 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6577 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580 const struct reg_info *reg_group;
6581 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6582 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6584 while ((reg_group = reg_set[g_ind++]))
6585 count += ixgbe_regs_group_count(reg_group);
6591 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6595 const struct reg_info *reg_group;
6597 while ((reg_group = ixgbevf_regs[g_ind++]))
6598 count += ixgbe_regs_group_count(reg_group);
6604 ixgbe_get_regs(struct rte_eth_dev *dev,
6605 struct rte_dev_reg_info *regs)
6607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608 uint32_t *data = regs->data;
6611 const struct reg_info *reg_group;
6612 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6613 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6616 regs->length = ixgbe_get_reg_length(dev);
6617 regs->width = sizeof(uint32_t);
6621 /* Support only full register dump */
6622 if ((regs->length == 0) ||
6623 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6624 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6626 while ((reg_group = reg_set[g_ind++]))
6627 count += ixgbe_read_regs_group(dev, &data[count],
6636 ixgbevf_get_regs(struct rte_eth_dev *dev,
6637 struct rte_dev_reg_info *regs)
6639 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6640 uint32_t *data = regs->data;
6643 const struct reg_info *reg_group;
6646 regs->length = ixgbevf_get_reg_length(dev);
6647 regs->width = sizeof(uint32_t);
6651 /* Support only full register dump */
6652 if ((regs->length == 0) ||
6653 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6654 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6656 while ((reg_group = ixgbevf_regs[g_ind++]))
6657 count += ixgbe_read_regs_group(dev, &data[count],
6666 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6668 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670 /* Return unit is byte count */
6671 return hw->eeprom.word_size * 2;
6675 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6676 struct rte_dev_eeprom_info *in_eeprom)
6678 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6679 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6680 uint16_t *data = in_eeprom->data;
6683 first = in_eeprom->offset >> 1;
6684 length = in_eeprom->length >> 1;
6685 if ((first > hw->eeprom.word_size) ||
6686 ((first + length) > hw->eeprom.word_size))
6689 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6691 return eeprom->ops.read_buffer(hw, first, length, data);
6695 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6696 struct rte_dev_eeprom_info *in_eeprom)
6698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6699 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6700 uint16_t *data = in_eeprom->data;
6703 first = in_eeprom->offset >> 1;
6704 length = in_eeprom->length >> 1;
6705 if ((first > hw->eeprom.word_size) ||
6706 ((first + length) > hw->eeprom.word_size))
6709 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6711 return eeprom->ops.write_buffer(hw, first, length, data);
6715 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6717 case ixgbe_mac_X550:
6718 case ixgbe_mac_X550EM_x:
6719 case ixgbe_mac_X550EM_a:
6720 return ETH_RSS_RETA_SIZE_512;
6721 case ixgbe_mac_X550_vf:
6722 case ixgbe_mac_X550EM_x_vf:
6723 case ixgbe_mac_X550EM_a_vf:
6724 return ETH_RSS_RETA_SIZE_64;
6726 return ETH_RSS_RETA_SIZE_128;
6731 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6733 case ixgbe_mac_X550:
6734 case ixgbe_mac_X550EM_x:
6735 case ixgbe_mac_X550EM_a:
6736 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6737 return IXGBE_RETA(reta_idx >> 2);
6739 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6740 case ixgbe_mac_X550_vf:
6741 case ixgbe_mac_X550EM_x_vf:
6742 case ixgbe_mac_X550EM_a_vf:
6743 return IXGBE_VFRETA(reta_idx >> 2);
6745 return IXGBE_RETA(reta_idx >> 2);
6750 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6752 case ixgbe_mac_X550_vf:
6753 case ixgbe_mac_X550EM_x_vf:
6754 case ixgbe_mac_X550EM_a_vf:
6755 return IXGBE_VFMRQC;
6762 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6764 case ixgbe_mac_X550_vf:
6765 case ixgbe_mac_X550EM_x_vf:
6766 case ixgbe_mac_X550EM_a_vf:
6767 return IXGBE_VFRSSRK(i);
6769 return IXGBE_RSSRK(i);
6774 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6776 case ixgbe_mac_82599_vf:
6777 case ixgbe_mac_X540_vf:
6785 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6786 struct rte_eth_dcb_info *dcb_info)
6788 struct ixgbe_dcb_config *dcb_config =
6789 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6790 struct ixgbe_dcb_tc_config *tc;
6791 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
6795 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6796 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6798 dcb_info->nb_tcs = 1;
6800 tc_queue = &dcb_info->tc_queue;
6801 nb_tcs = dcb_info->nb_tcs;
6803 if (dcb_config->vt_mode) { /* vt is enabled*/
6804 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6805 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6806 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6807 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6808 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
6809 for (j = 0; j < nb_tcs; j++) {
6810 tc_queue->tc_rxq[0][j].base = j;
6811 tc_queue->tc_rxq[0][j].nb_queue = 1;
6812 tc_queue->tc_txq[0][j].base = j;
6813 tc_queue->tc_txq[0][j].nb_queue = 1;
6816 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6817 for (j = 0; j < nb_tcs; j++) {
6818 tc_queue->tc_rxq[i][j].base =
6820 tc_queue->tc_rxq[i][j].nb_queue = 1;
6821 tc_queue->tc_txq[i][j].base =
6823 tc_queue->tc_txq[i][j].nb_queue = 1;
6827 } else { /* vt is disabled*/
6828 struct rte_eth_dcb_rx_conf *rx_conf =
6829 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6830 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6831 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6832 if (dcb_info->nb_tcs == ETH_4_TCS) {
6833 for (i = 0; i < dcb_info->nb_tcs; i++) {
6834 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6835 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6837 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6838 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6839 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6840 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6841 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6842 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6843 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6844 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6845 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6846 for (i = 0; i < dcb_info->nb_tcs; i++) {
6847 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6848 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6850 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6851 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6852 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6853 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6854 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6855 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6856 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6857 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6858 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6859 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6860 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6861 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6862 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6863 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6864 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6865 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6868 for (i = 0; i < dcb_info->nb_tcs; i++) {
6869 tc = &dcb_config->tc_config[i];
6870 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6875 /* Update e-tag ether type */
6877 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6878 uint16_t ether_type)
6880 uint32_t etag_etype;
6882 if (hw->mac.type != ixgbe_mac_X550 &&
6883 hw->mac.type != ixgbe_mac_X550EM_x &&
6884 hw->mac.type != ixgbe_mac_X550EM_a) {
6888 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6889 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6890 etag_etype |= ether_type;
6891 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6892 IXGBE_WRITE_FLUSH(hw);
6897 /* Config l2 tunnel ether type */
6899 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6900 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6903 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905 if (l2_tunnel == NULL)
6908 switch (l2_tunnel->l2_tunnel_type) {
6909 case RTE_L2_TUNNEL_TYPE_E_TAG:
6910 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6913 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6921 /* Enable e-tag tunnel */
6923 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6925 uint32_t etag_etype;
6927 if (hw->mac.type != ixgbe_mac_X550 &&
6928 hw->mac.type != ixgbe_mac_X550EM_x &&
6929 hw->mac.type != ixgbe_mac_X550EM_a) {
6933 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6934 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6935 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6936 IXGBE_WRITE_FLUSH(hw);
6941 /* Enable l2 tunnel */
6943 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6944 enum rte_eth_tunnel_type l2_tunnel_type)
6947 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6949 switch (l2_tunnel_type) {
6950 case RTE_L2_TUNNEL_TYPE_E_TAG:
6951 ret = ixgbe_e_tag_enable(hw);
6954 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6962 /* Disable e-tag tunnel */
6964 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6966 uint32_t etag_etype;
6968 if (hw->mac.type != ixgbe_mac_X550 &&
6969 hw->mac.type != ixgbe_mac_X550EM_x &&
6970 hw->mac.type != ixgbe_mac_X550EM_a) {
6974 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6975 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6976 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6977 IXGBE_WRITE_FLUSH(hw);
6982 /* Disable l2 tunnel */
6984 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6985 enum rte_eth_tunnel_type l2_tunnel_type)
6988 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990 switch (l2_tunnel_type) {
6991 case RTE_L2_TUNNEL_TYPE_E_TAG:
6992 ret = ixgbe_e_tag_disable(hw);
6995 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7004 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7005 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009 uint32_t i, rar_entries;
7010 uint32_t rar_low, rar_high;
7012 if (hw->mac.type != ixgbe_mac_X550 &&
7013 hw->mac.type != ixgbe_mac_X550EM_x &&
7014 hw->mac.type != ixgbe_mac_X550EM_a) {
7018 rar_entries = ixgbe_get_num_rx_addrs(hw);
7020 for (i = 1; i < rar_entries; i++) {
7021 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7022 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7023 if ((rar_high & IXGBE_RAH_AV) &&
7024 (rar_high & IXGBE_RAH_ADTYPE) &&
7025 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7026 l2_tunnel->tunnel_id)) {
7027 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7028 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7030 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7040 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7041 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7044 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045 uint32_t i, rar_entries;
7046 uint32_t rar_low, rar_high;
7048 if (hw->mac.type != ixgbe_mac_X550 &&
7049 hw->mac.type != ixgbe_mac_X550EM_x &&
7050 hw->mac.type != ixgbe_mac_X550EM_a) {
7054 /* One entry for one tunnel. Try to remove potential existing entry. */
7055 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7057 rar_entries = ixgbe_get_num_rx_addrs(hw);
7059 for (i = 1; i < rar_entries; i++) {
7060 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7061 if (rar_high & IXGBE_RAH_AV) {
7064 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7065 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7066 rar_low = l2_tunnel->tunnel_id;
7068 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7069 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7075 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7076 " Please remove a rule before adding a new one.");
7080 /* Add l2 tunnel filter */
7082 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7083 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7087 switch (l2_tunnel->l2_tunnel_type) {
7088 case RTE_L2_TUNNEL_TYPE_E_TAG:
7089 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7092 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7100 /* Delete l2 tunnel filter */
7102 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7103 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7107 switch (l2_tunnel->l2_tunnel_type) {
7108 case RTE_L2_TUNNEL_TYPE_E_TAG:
7109 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7112 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7121 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7122 * @dev: pointer to rte_eth_dev structure
7123 * @filter_op:operation will be taken.
7124 * @arg: a pointer to specific structure corresponding to the filter_op
7127 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7128 enum rte_filter_op filter_op,
7133 if (filter_op == RTE_ETH_FILTER_NOP)
7137 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7142 switch (filter_op) {
7143 case RTE_ETH_FILTER_ADD:
7144 ret = ixgbe_dev_l2_tunnel_filter_add
7146 (struct rte_eth_l2_tunnel_conf *)arg);
7148 case RTE_ETH_FILTER_DELETE:
7149 ret = ixgbe_dev_l2_tunnel_filter_del
7151 (struct rte_eth_l2_tunnel_conf *)arg);
7154 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7162 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7166 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7168 if (hw->mac.type != ixgbe_mac_X550 &&
7169 hw->mac.type != ixgbe_mac_X550EM_x &&
7170 hw->mac.type != ixgbe_mac_X550EM_a) {
7174 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7175 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7177 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7178 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7183 /* Enable l2 tunnel forwarding */
7185 ixgbe_dev_l2_tunnel_forwarding_enable
7186 (struct rte_eth_dev *dev,
7187 enum rte_eth_tunnel_type l2_tunnel_type)
7191 switch (l2_tunnel_type) {
7192 case RTE_L2_TUNNEL_TYPE_E_TAG:
7193 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7196 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7204 /* Disable l2 tunnel forwarding */
7206 ixgbe_dev_l2_tunnel_forwarding_disable
7207 (struct rte_eth_dev *dev,
7208 enum rte_eth_tunnel_type l2_tunnel_type)
7212 switch (l2_tunnel_type) {
7213 case RTE_L2_TUNNEL_TYPE_E_TAG:
7214 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7217 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7226 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7227 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7231 uint32_t vmtir, vmvir;
7232 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7236 "VF id %u should be less than %u",
7238 dev->pci_dev->max_vfs);
7242 if (hw->mac.type != ixgbe_mac_X550 &&
7243 hw->mac.type != ixgbe_mac_X550EM_x &&
7244 hw->mac.type != ixgbe_mac_X550EM_a) {
7249 vmtir = l2_tunnel->tunnel_id;
7253 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7255 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7256 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7258 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7259 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7264 /* Enable l2 tunnel tag insertion */
7266 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7267 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7271 switch (l2_tunnel->l2_tunnel_type) {
7272 case RTE_L2_TUNNEL_TYPE_E_TAG:
7273 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7276 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7284 /* Disable l2 tunnel tag insertion */
7286 ixgbe_dev_l2_tunnel_insertion_disable
7287 (struct rte_eth_dev *dev,
7288 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7292 switch (l2_tunnel->l2_tunnel_type) {
7293 case RTE_L2_TUNNEL_TYPE_E_TAG:
7294 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7297 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7306 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7313 if (hw->mac.type != ixgbe_mac_X550 &&
7314 hw->mac.type != ixgbe_mac_X550EM_x &&
7315 hw->mac.type != ixgbe_mac_X550EM_a) {
7319 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7321 qde |= IXGBE_QDE_STRIP_TAG;
7323 qde &= ~IXGBE_QDE_STRIP_TAG;
7324 qde &= ~IXGBE_QDE_READ;
7325 qde |= IXGBE_QDE_WRITE;
7326 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7331 /* Enable l2 tunnel tag stripping */
7333 ixgbe_dev_l2_tunnel_stripping_enable
7334 (struct rte_eth_dev *dev,
7335 enum rte_eth_tunnel_type l2_tunnel_type)
7339 switch (l2_tunnel_type) {
7340 case RTE_L2_TUNNEL_TYPE_E_TAG:
7341 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7344 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7352 /* Disable l2 tunnel tag stripping */
7354 ixgbe_dev_l2_tunnel_stripping_disable
7355 (struct rte_eth_dev *dev,
7356 enum rte_eth_tunnel_type l2_tunnel_type)
7360 switch (l2_tunnel_type) {
7361 case RTE_L2_TUNNEL_TYPE_E_TAG:
7362 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7365 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7373 /* Enable/disable l2 tunnel offload functions */
7375 ixgbe_dev_l2_tunnel_offload_set
7376 (struct rte_eth_dev *dev,
7377 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7383 if (l2_tunnel == NULL)
7387 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7389 ret = ixgbe_dev_l2_tunnel_enable(
7391 l2_tunnel->l2_tunnel_type);
7393 ret = ixgbe_dev_l2_tunnel_disable(
7395 l2_tunnel->l2_tunnel_type);
7398 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7400 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7404 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7409 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7411 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7413 l2_tunnel->l2_tunnel_type);
7415 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7417 l2_tunnel->l2_tunnel_type);
7420 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7422 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7424 l2_tunnel->l2_tunnel_type);
7426 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7428 l2_tunnel->l2_tunnel_type);
7435 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7438 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7439 IXGBE_WRITE_FLUSH(hw);
7444 /* There's only one register for VxLAN UDP port.
7445 * So, we cannot add several ports. Will update it.
7448 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7452 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7456 return ixgbe_update_vxlan_port(hw, port);
7459 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7460 * UDP port, it must have a value.
7461 * So, will reset it to the original value 0.
7464 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7469 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7471 if (cur_port != port) {
7472 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7476 return ixgbe_update_vxlan_port(hw, 0);
7479 /* Add UDP tunneling port */
7481 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7482 struct rte_eth_udp_tunnel *udp_tunnel)
7485 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7487 if (hw->mac.type != ixgbe_mac_X550 &&
7488 hw->mac.type != ixgbe_mac_X550EM_x &&
7489 hw->mac.type != ixgbe_mac_X550EM_a) {
7493 if (udp_tunnel == NULL)
7496 switch (udp_tunnel->prot_type) {
7497 case RTE_TUNNEL_TYPE_VXLAN:
7498 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7501 case RTE_TUNNEL_TYPE_GENEVE:
7502 case RTE_TUNNEL_TYPE_TEREDO:
7503 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7508 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7516 /* Remove UDP tunneling port */
7518 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7519 struct rte_eth_udp_tunnel *udp_tunnel)
7522 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7524 if (hw->mac.type != ixgbe_mac_X550 &&
7525 hw->mac.type != ixgbe_mac_X550EM_x &&
7526 hw->mac.type != ixgbe_mac_X550EM_a) {
7530 if (udp_tunnel == NULL)
7533 switch (udp_tunnel->prot_type) {
7534 case RTE_TUNNEL_TYPE_VXLAN:
7535 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7537 case RTE_TUNNEL_TYPE_GENEVE:
7538 case RTE_TUNNEL_TYPE_TEREDO:
7539 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7543 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7552 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7554 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7556 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7560 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7564 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7567 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7569 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7575 /* PF reset VF event */
7576 if (in_msg == IXGBE_PF_CONTROL_MSG)
7577 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7581 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7585 struct ixgbe_interrupt *intr =
7586 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7587 ixgbevf_intr_disable(hw);
7589 /* read-on-clear nic registers here */
7590 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7593 /* only one misc vector supported - mailbox */
7594 eicr &= IXGBE_VTEICR_MASK;
7595 if (eicr == IXGBE_MISC_VEC_ID)
7596 intr->flags |= IXGBE_FLAG_MAILBOX;
7602 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7605 struct ixgbe_interrupt *intr =
7606 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7608 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7609 ixgbevf_mbx_process(dev);
7610 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7613 ixgbevf_intr_enable(hw);
7619 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7622 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7624 ixgbevf_dev_interrupt_get_status(dev);
7625 ixgbevf_dev_interrupt_action(dev);
7628 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7629 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7630 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7631 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);