drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 237 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 238                 void *param);
 239 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 240 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 241                 uint32_t index, uint32_t pool);
 242 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 243 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 244                                            struct ether_addr *mac_addr);
 245 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 246
 247 /* For Virtual Function support */
 248 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 249 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 250 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 251 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 255 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 256 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 264 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 265 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id);
 267 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 268                                              uint16_t queue_id);
 269 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 270                                  uint8_t queue, uint8_t msix_vector);
 271 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 272 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 274
 275 /* For Eth VMDQ APIs support */
 276 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 277                 ether_addr * mac_addr, uint8_t on);
 278 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 279 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 280                 uint16_t rx_mask, uint8_t on);
 281 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 282 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 284                 uint64_t pool_mask, uint8_t vlan_on);
 285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 286                 struct rte_eth_mirror_conf *mirror_conf,
 287                 uint8_t rule_id, uint8_t on);
 288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 289                 uint8_t rule_id);
 290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 291                                           uint16_t queue_id);
 292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 293                                            uint16_t queue_id);
 294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 295                                uint8_t queue, uint8_t msix_vector);
 296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 297
 298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 299                 uint16_t queue_idx, uint16_t tx_rate);
 300 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 301                 uint16_t tx_rate, uint64_t q_msk);
 302
 303 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 304                                  struct ether_addr *mac_addr,
 305                                  uint32_t index, uint32_t pool);
 306 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 307 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 308                                              struct ether_addr *mac_addr);
 309 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 310                         struct rte_eth_syn_filter *filter,
 311                         bool add);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 322                         struct rte_eth_ntuple_filter *filter,
 323                         bool add);
 324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ntuple_filter *filter);
 329 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter,
 331                         bool add);
 332 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 333                                 enum rte_filter_op filter_op,
 334                                 void *arg);
 335 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 336                         struct rte_eth_ethertype_filter *filter);
 337 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 338                      enum rte_filter_type filter_type,
 339                      enum rte_filter_op filter_op,
 340                      void *arg);
 341 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 342
 343 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 344                                       struct ether_addr *mc_addr_set,
 345                                       uint32_t nb_mc_addr);
 346 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 347                                    struct rte_eth_dcb_info *dcb_info);
 348
 349 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 351                             struct rte_dev_reg_info *regs);
 352 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 353 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 356                                 struct rte_dev_eeprom_info *eeprom);
 357
 358 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 359 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 360                                 struct rte_dev_reg_info *regs);
 361
 362 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 363 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp,
 366                                             uint32_t flags);
 367 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 368                                             struct timespec *timestamp);
 369 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 370 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 371                                    struct timespec *timestamp);
 372 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 373                                    const struct timespec *timestamp);
 374 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 375                                           void *param);
 376
 377 static int ixgbe_dev_l2_tunnel_eth_type_conf
 378         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 379 static int ixgbe_dev_l2_tunnel_offload_set
 380         (struct rte_eth_dev *dev,
 381          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 382          uint32_t mask,
 383          uint8_t en);
 384 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 385                                              enum rte_filter_op filter_op,
 386                                              void *arg);
 387
 388 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 391                                          struct rte_eth_udp_tunnel *udp_tunnel);
 392
 393 /*
 394  * Define VF Stats MACRO for Non "cleared on read" register
 395  */
 396 #define UPDATE_VF_STAT(reg, last, cur)                          \
 397 {                                                               \
 398         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 399         cur += (latest - last) & UINT_MAX;                      \
 400         last = latest;                                          \
 401 }
 402
 403 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 404 {                                                                \
 405         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 406         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 407         u64 latest = ((new_msb << 32) | new_lsb);                \
 408         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 409         last = latest;                                           \
 410 }
 411
 412 #define IXGBE_SET_HWSTRIP(h, q) do {\
 413                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 415                 (h)->bitmap[idx] |= 1 << bit;\
 416         } while (0)
 417
 418 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 419                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 420                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 421                 (h)->bitmap[idx] &= ~(1 << bit);\
 422         } while (0)
 423
 424 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 425                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 426                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 427                 (r) = (h)->bitmap[idx] >> bit & 1;\
 428         } while (0)
 429
 430 /*
 431  * The set of PCI devices this driver supports
 432  */
 433 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 487 #ifdef RTE_NIC_BYPASS
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 489 #endif
 490         { .vendor_id = 0, /* sentinel */ },
 491 };
 492
 493 /*
 494  * The set of PCI devices this driver supports (for 82599 VF)
 495  */
 496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 507         { .vendor_id = 0, /* sentinel */ },
 508 };
 509
 510 static const struct rte_eth_desc_lim rx_desc_lim = {
 511         .nb_max = IXGBE_MAX_RING_DESC,
 512         .nb_min = IXGBE_MIN_RING_DESC,
 513         .nb_align = IXGBE_RXD_ALIGN,
 514 };
 515
 516 static const struct rte_eth_desc_lim tx_desc_lim = {
 517         .nb_max = IXGBE_MAX_RING_DESC,
 518         .nb_min = IXGBE_MIN_RING_DESC,
 519         .nb_align = IXGBE_TXD_ALIGN,
 520 };
 521
 522 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 523         .dev_configure        = ixgbe_dev_configure,
 524         .dev_start            = ixgbe_dev_start,
 525         .dev_stop             = ixgbe_dev_stop,
 526         .dev_set_link_up    = ixgbe_dev_set_link_up,
 527         .dev_set_link_down  = ixgbe_dev_set_link_down,
 528         .dev_close            = ixgbe_dev_close,
 529         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 530         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 531         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 532         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 533         .link_update          = ixgbe_dev_link_update,
 534         .stats_get            = ixgbe_dev_stats_get,
 535         .xstats_get           = ixgbe_dev_xstats_get,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 540         .dev_infos_get        = ixgbe_dev_info_get,
 541         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 542         .mtu_set              = ixgbe_dev_mtu_set,
 543         .vlan_filter_set      = ixgbe_vlan_filter_set,
 544         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 545         .vlan_offload_set     = ixgbe_vlan_offload_set,
 546         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 547         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 548         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 549         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 550         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 551         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 552         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 553         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 554         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 555         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .dev_led_on           = ixgbe_dev_led_on,
 560         .dev_led_off          = ixgbe_dev_led_off,
 561         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 562         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 563         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 564         .mac_addr_add         = ixgbe_add_rar,
 565         .mac_addr_remove      = ixgbe_remove_rar,
 566         .mac_addr_set         = ixgbe_set_default_mac_addr,
 567         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 568         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 569         .mirror_rule_set      = ixgbe_mirror_rule_set,
 570         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 571         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 572         .set_vf_rx            = ixgbe_set_pool_rx,
 573         .set_vf_tx            = ixgbe_set_pool_tx,
 574         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 577         .reta_update          = ixgbe_dev_rss_reta_update,
 578         .reta_query           = ixgbe_dev_rss_reta_query,
 579 #ifdef RTE_NIC_BYPASS
 580         .bypass_init          = ixgbe_bypass_init,
 581         .bypass_state_set     = ixgbe_bypass_state_store,
 582         .bypass_state_show    = ixgbe_bypass_state_show,
 583         .bypass_event_set     = ixgbe_bypass_event_store,
 584         .bypass_event_show    = ixgbe_bypass_event_show,
 585         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 586         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 587         .bypass_ver_show      = ixgbe_bypass_ver_show,
 588         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 589 #endif /* RTE_NIC_BYPASS */
 590         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 591         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 592         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 593         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 594         .rxq_info_get         = ixgbe_rxq_info_get,
 595         .txq_info_get         = ixgbe_txq_info_get,
 596         .timesync_enable      = ixgbe_timesync_enable,
 597         .timesync_disable     = ixgbe_timesync_disable,
 598         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 599         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 600         .get_reg              = ixgbe_get_regs,
 601         .get_eeprom_length    = ixgbe_get_eeprom_length,
 602         .get_eeprom           = ixgbe_get_eeprom,
 603         .set_eeprom           = ixgbe_set_eeprom,
 604         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 605         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 606         .timesync_read_time   = ixgbe_timesync_read_time,
 607         .timesync_write_time  = ixgbe_timesync_write_time,
 608         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 609         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 610         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 611         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 612 };
 613
 614 /*
 615  * dev_ops for virtual function, bare necessities for basic vf
 616  * operation have been implemented
 617  */
 618 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 619         .dev_configure        = ixgbevf_dev_configure,
 620         .dev_start            = ixgbevf_dev_start,
 621         .dev_stop             = ixgbevf_dev_stop,
 622         .link_update          = ixgbe_dev_link_update,
 623         .stats_get            = ixgbevf_dev_stats_get,
 624         .xstats_get           = ixgbevf_dev_xstats_get,
 625         .stats_reset          = ixgbevf_dev_stats_reset,
 626         .xstats_reset         = ixgbevf_dev_stats_reset,
 627         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 628         .dev_close            = ixgbevf_dev_close,
 629         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 630         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 631         .dev_infos_get        = ixgbevf_dev_info_get,
 632         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 633         .mtu_set              = ixgbevf_dev_set_mtu,
 634         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 635         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 636         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 637         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 638         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 639         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 640         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 641         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 642         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 643         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 644         .mac_addr_add         = ixgbevf_add_mac_addr,
 645         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 646         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 647         .rxq_info_get         = ixgbe_rxq_info_get,
 648         .txq_info_get         = ixgbe_txq_info_get,
 649         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 650         .get_reg              = ixgbevf_get_regs,
 651         .reta_update          = ixgbe_dev_rss_reta_update,
 652         .reta_query           = ixgbe_dev_rss_reta_query,
 653         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 654         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 655 };
 656
 657 /* store statistics names and its offset in stats structure */
 658 struct rte_ixgbe_xstats_name_off {
 659         char name[RTE_ETH_XSTATS_NAME_SIZE];
 660         unsigned offset;
 661 };
 662
 663 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 664         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 665         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 666         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 667         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 668         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 669         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 670         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 671         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 672         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 673         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 674         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 675         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 676         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 677         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 678         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1023)},
 680         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 681                 prc1522)},
 682         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 683         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 684         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 685         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 686         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 687         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 688         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 689         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 690         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 691         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 692         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 693         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 694         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 695         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 696         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 697         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 698         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1023)},
 700         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 701                 ptc1522)},
 702         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 703         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 704         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 705         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 706
 707         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_add)},
 709         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirustat_remove)},
 711         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fadd)},
 713         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 714                 fdirfstat_fremove)},
 715         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmatch)},
 717         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 718                 fdirmiss)},
 719
 720         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 721         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 722         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 723                 fclast)},
 724         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 725         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 726         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 727         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 728         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 729                 fcoe_noddp)},
 730         {"rx_fcoe_no_direct_data_placement_ext_buff",
 731                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 732
 733         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxontxc)},
 735         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxonrxc)},
 737         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxofftxc)},
 739         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxoffrxc)},
 741         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 742 };
 743
 744 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 745                            sizeof(rte_ixgbe_stats_strings[0]))
 746
 747 /* Per-queue statistics */
 748 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 749         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 750         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 751         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 752         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 753 };
 754
 755 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 756                            sizeof(rte_ixgbe_rxq_strings[0]))
 757 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 758
 759 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 760         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 761         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 762         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 763                 pxon2offc)},
 764 };
 765
 766 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 767                            sizeof(rte_ixgbe_txq_strings[0]))
 768 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 769
 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 771         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 772 };
 773
 774 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 775                 sizeof(rte_ixgbevf_stats_strings[0]))
 776
 777 /**
 778  * Atomically reads the link status information from global
 779  * structure rte_eth_dev.
 780  *
 781  * @param dev
 782  *   - Pointer to the structure rte_eth_dev to read from.
 783  *   - Pointer to the buffer to be saved with the link status.
 784  *
 785  * @return
 786  *   - On success, zero.
 787  *   - On failure, negative value.
 788  */
 789 static inline int
 790 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 791                                 struct rte_eth_link *link)
 792 {
 793         struct rte_eth_link *dst = link;
 794         struct rte_eth_link *src = &(dev->data->dev_link);
 795
 796         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 797                                         *(uint64_t *)src) == 0)
 798                 return -1;
 799
 800         return 0;
 801 }
 802
 803 /**
 804  * Atomically writes the link status information into global
 805  * structure rte_eth_dev.
 806  *
 807  * @param dev
 808  *   - Pointer to the structure rte_eth_dev to read from.
 809  *   - Pointer to the buffer to be saved with the link status.
 810  *
 811  * @return
 812  *   - On success, zero.
 813  *   - On failure, negative value.
 814  */
 815 static inline int
 816 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 817                                 struct rte_eth_link *link)
 818 {
 819         struct rte_eth_link *dst = &(dev->data->dev_link);
 820         struct rte_eth_link *src = link;
 821
 822         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 823                                         *(uint64_t *)src) == 0)
 824                 return -1;
 825
 826         return 0;
 827 }
 828
 829 /*
 830  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 831  */
 832 static inline int
 833 ixgbe_is_sfp(struct ixgbe_hw *hw)
 834 {
 835         switch (hw->phy.type) {
 836         case ixgbe_phy_sfp_avago:
 837         case ixgbe_phy_sfp_ftl:
 838         case ixgbe_phy_sfp_intel:
 839         case ixgbe_phy_sfp_unknown:
 840         case ixgbe_phy_sfp_passive_tyco:
 841         case ixgbe_phy_sfp_passive_unknown:
 842                 return 1;
 843         default:
 844                 return 0;
 845         }
 846 }
 847
 848 static inline int32_t
 849 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 850 {
 851         uint32_t ctrl_ext;
 852         int32_t status;
 853
 854         status = ixgbe_reset_hw(hw);
 855
 856         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 857         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 858         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 859         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 860         IXGBE_WRITE_FLUSH(hw);
 861
 862         return status;
 863 }
 864
 865 static inline void
 866 ixgbe_enable_intr(struct rte_eth_dev *dev)
 867 {
 868         struct ixgbe_interrupt *intr =
 869                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 870         struct ixgbe_hw *hw =
 871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 872
 873         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 874         IXGBE_WRITE_FLUSH(hw);
 875 }
 876
 877 /*
 878  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 879  */
 880 static void
 881 ixgbe_disable_intr(struct ixgbe_hw *hw)
 882 {
 883         PMD_INIT_FUNC_TRACE();
 884
 885         if (hw->mac.type == ixgbe_mac_82598EB) {
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 887         } else {
 888                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 890                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 891         }
 892         IXGBE_WRITE_FLUSH(hw);
 893 }
 894
 895 /*
 896  * This function resets queue statistics mapping registers.
 897  * From Niantic datasheet, Initialization of Statistics section:
 898  * "...if software requires the queue counters, the RQSMR and TQSM registers
 899  * must be re-programmed following a device reset.
 900  */
 901 static void
 902 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 903 {
 904         uint32_t i;
 905
 906         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 907                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 909         }
 910 }
 911
 912
 913 static int
 914 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 915                                   uint16_t queue_id,
 916                                   uint8_t stat_idx,
 917                                   uint8_t is_rx)
 918 {
 919 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 920 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 921 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 922
 923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 924         struct ixgbe_stat_mapping_registers *stat_mappings =
 925                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 926         uint32_t qsmr_mask = 0;
 927         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 928         uint32_t q_map;
 929         uint8_t n, offset;
 930
 931         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 932                 (hw->mac.type != ixgbe_mac_X540) &&
 933                 (hw->mac.type != ixgbe_mac_X550) &&
 934                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 935                 (hw->mac.type != ixgbe_mac_X550EM_a))
 936                 return -ENOSYS;
 937
 938         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 939                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 940                      queue_id, stat_idx);
 941
 942         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 943         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 944                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 945                 return -EIO;
 946         }
 947         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 948
 949         /* Now clear any previous stat_idx set */
 950         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 951         if (!is_rx)
 952                 stat_mappings->tqsm[n] &= ~clearing_mask;
 953         else
 954                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 955
 956         q_map = (uint32_t)stat_idx;
 957         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 958         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 959         if (!is_rx)
 960                 stat_mappings->tqsm[n] |= qsmr_mask;
 961         else
 962                 stat_mappings->rqsmr[n] |= qsmr_mask;
 963
 964         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 965                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 966                      queue_id, stat_idx);
 967         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 968                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 969
 970         /* Now write the mapping in the appropriate register */
 971         if (is_rx) {
 972                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 973                              stat_mappings->rqsmr[n], n);
 974                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 975         } else {
 976                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 977                              stat_mappings->tqsm[n], n);
 978                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 979         }
 980         return 0;
 981 }
 982
 983 static void
 984 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 985 {
 986         struct ixgbe_stat_mapping_registers *stat_mappings =
 987                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989         int i;
 990
 991         /* write whatever was in stat mapping table to the NIC */
 992         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 993                 /* rx */
 994                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 995
 996                 /* tx */
 997                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 998         }
 999 }
1000
1001 static void
1002 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1003 {
1004         uint8_t i;
1005         struct ixgbe_dcb_tc_config *tc;
1006         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1007
1008         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1009         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1010         for (i = 0; i < dcb_max_tc; i++) {
1011                 tc = &dcb_config->tc_config[i];
1012                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1013                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1014                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1015                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1016                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1017                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1018                 tc->pfc = ixgbe_dcb_pfc_disabled;
1019         }
1020
1021         /* Initialize default user to priority mapping, UPx->TC0 */
1022         tc = &dcb_config->tc_config[0];
1023         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1024         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1025         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1026                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1027                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1028         }
1029         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1030         dcb_config->pfc_mode_enable = false;
1031         dcb_config->vt_mode = true;
1032         dcb_config->round_robin_enable = false;
1033         /* support all DCB capabilities in 82599 */
1034         dcb_config->support.capabilities = 0xFF;
1035
1036         /*we only support 4 Tcs for X540, X550 */
1037         if (hw->mac.type == ixgbe_mac_X540 ||
1038                 hw->mac.type == ixgbe_mac_X550 ||
1039                 hw->mac.type == ixgbe_mac_X550EM_x ||
1040                 hw->mac.type == ixgbe_mac_X550EM_a) {
1041                 dcb_config->num_tcs.pg_tcs = 4;
1042                 dcb_config->num_tcs.pfc_tcs = 4;
1043         }
1044 }
1045
1046 /*
1047  * Ensure that all locks are released before first NVM or PHY access
1048  */
1049 static void
1050 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1051 {
1052         uint16_t mask;
1053
1054         /*
1055          * Phy lock should not fail in this early stage. If this is the case,
1056          * it is due to an improper exit of the application.
1057          * So force the release of the faulty lock. Release of common lock
1058          * is done automatically by swfw_sync function.
1059          */
1060         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1061         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1062                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1063         }
1064         ixgbe_release_swfw_semaphore(hw, mask);
1065
1066         /*
1067          * These ones are more tricky since they are common to all ports; but
1068          * swfw_sync retries last long enough (1s) to be almost sure that if
1069          * lock can not be taken it is due to an improper lock of the
1070          * semaphore.
1071          */
1072         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1073         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1074                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1075         }
1076         ixgbe_release_swfw_semaphore(hw, mask);
1077 }
1078
1079 /*
1080  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1081  * It returns 0 on success.
1082  */
1083 static int
1084 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1085 {
1086         struct rte_pci_device *pci_dev;
1087         struct ixgbe_hw *hw =
1088                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1089         struct ixgbe_vfta *shadow_vfta =
1090                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1091         struct ixgbe_hwstrip *hwstrip =
1092                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1093         struct ixgbe_dcb_config *dcb_config =
1094                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1095         struct ixgbe_filter_info *filter_info =
1096                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1097         uint32_t ctrl_ext;
1098         uint16_t csum;
1099         int diag, i;
1100
1101         PMD_INIT_FUNC_TRACE();
1102
1103         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1104         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1105         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1106
1107         /*
1108          * For secondary processes, we don't initialise any further as primary
1109          * has already done this work. Only check we don't need a different
1110          * RX and TX function.
1111          */
1112         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1113                 struct ixgbe_tx_queue *txq;
1114                 /* TX queue function in primary, set by last queue initialized
1115                  * Tx queue may not initialized by primary process
1116                  */
1117                 if (eth_dev->data->tx_queues) {
1118                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1119                         ixgbe_set_tx_function(eth_dev, txq);
1120                 } else {
1121                         /* Use default TX function if we get here */
1122                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1123                                      "Using default TX function.");
1124                 }
1125
1126                 ixgbe_set_rx_function(eth_dev);
1127
1128                 return 0;
1129         }
1130         pci_dev = eth_dev->pci_dev;
1131
1132         rte_eth_copy_pci_info(eth_dev, pci_dev);
1133
1134         /* Vendor and Device ID need to be set before init of shared code */
1135         hw->device_id = pci_dev->id.device_id;
1136         hw->vendor_id = pci_dev->id.vendor_id;
1137         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1138         hw->allow_unsupported_sfp = 1;
1139
1140         /* Initialize the shared code (base driver) */
1141 #ifdef RTE_NIC_BYPASS
1142         diag = ixgbe_bypass_init_shared_code(hw);
1143 #else
1144         diag = ixgbe_init_shared_code(hw);
1145 #endif /* RTE_NIC_BYPASS */
1146
1147         if (diag != IXGBE_SUCCESS) {
1148                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1149                 return -EIO;
1150         }
1151
1152         /* pick up the PCI bus settings for reporting later */
1153         ixgbe_get_bus_info(hw);
1154
1155         /* Unlock any pending hardware semaphore */
1156         ixgbe_swfw_lock_reset(hw);
1157
1158         /* Initialize DCB configuration*/
1159         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1160         ixgbe_dcb_init(hw, dcb_config);
1161         /* Get Hardware Flow Control setting */
1162         hw->fc.requested_mode = ixgbe_fc_full;
1163         hw->fc.current_mode = ixgbe_fc_full;
1164         hw->fc.pause_time = IXGBE_FC_PAUSE;
1165         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1166                 hw->fc.low_water[i] = IXGBE_FC_LO;
1167                 hw->fc.high_water[i] = IXGBE_FC_HI;
1168         }
1169         hw->fc.send_xon = 1;
1170
1171         /* Make sure we have a good EEPROM before we read from it */
1172         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1173         if (diag != IXGBE_SUCCESS) {
1174                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1175                 return -EIO;
1176         }
1177
1178 #ifdef RTE_NIC_BYPASS
1179         diag = ixgbe_bypass_init_hw(hw);
1180 #else
1181         diag = ixgbe_init_hw(hw);
1182 #endif /* RTE_NIC_BYPASS */
1183
1184         /*
1185          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1186          * is called too soon after the kernel driver unbinding/binding occurs.
1187          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1188          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1189          * also called. See ixgbe_identify_phy_82599(). The reason for the
1190          * failure is not known, and only occuts when virtualisation features
1191          * are disabled in the bios. A delay of 100ms  was found to be enough by
1192          * trial-and-error, and is doubled to be safe.
1193          */
1194         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1195                 rte_delay_ms(200);
1196                 diag = ixgbe_init_hw(hw);
1197         }
1198
1199         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1200                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1201                              "LOM.  Please be aware there may be issues associated "
1202                              "with your hardware.");
1203                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1204                              "please contact your Intel or hardware representative "
1205                              "who provided you with this hardware.");
1206         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1207                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1208         if (diag) {
1209                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1210                 return -EIO;
1211         }
1212
1213         /* Reset the hw statistics */
1214         ixgbe_dev_stats_reset(eth_dev);
1215
1216         /* disable interrupt */
1217         ixgbe_disable_intr(hw);
1218
1219         /* reset mappings for queue statistics hw counters*/
1220         ixgbe_reset_qstat_mappings(hw);
1221
1222         /* Allocate memory for storing MAC addresses */
1223         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1224                                                hw->mac.num_rar_entries, 0);
1225         if (eth_dev->data->mac_addrs == NULL) {
1226                 PMD_INIT_LOG(ERR,
1227                              "Failed to allocate %u bytes needed to store "
1228                              "MAC addresses",
1229                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1230                 return -ENOMEM;
1231         }
1232         /* Copy the permanent MAC address */
1233         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1234                         &eth_dev->data->mac_addrs[0]);
1235
1236         /* Allocate memory for storing hash filter MAC addresses */
1237         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1238                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1239         if (eth_dev->data->hash_mac_addrs == NULL) {
1240                 PMD_INIT_LOG(ERR,
1241                              "Failed to allocate %d bytes needed to store MAC addresses",
1242                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1243                 return -ENOMEM;
1244         }
1245
1246         /* initialize the vfta */
1247         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1248
1249         /* initialize the hw strip bitmap*/
1250         memset(hwstrip, 0, sizeof(*hwstrip));
1251
1252         /* initialize PF if max_vfs not zero */
1253         ixgbe_pf_host_init(eth_dev);
1254
1255         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1256         /* let hardware know driver is loaded */
1257         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1258         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1259         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1260         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1261         IXGBE_WRITE_FLUSH(hw);
1262
1263         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1264                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1265                              (int) hw->mac.type, (int) hw->phy.type,
1266                              (int) hw->phy.sfp_type);
1267         else
1268                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1269                              (int) hw->mac.type, (int) hw->phy.type);
1270
1271         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1272                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1273                      pci_dev->id.device_id);
1274
1275         rte_intr_callback_register(&pci_dev->intr_handle,
1276                                    ixgbe_dev_interrupt_handler,
1277                                    (void *)eth_dev);
1278
1279         /* enable uio/vfio intr/eventfd mapping */
1280         rte_intr_enable(&pci_dev->intr_handle);
1281
1282         /* enable support intr */
1283         ixgbe_enable_intr(eth_dev);
1284
1285         /* initialize 5tuple filter list */
1286         TAILQ_INIT(&filter_info->fivetuple_list);
1287         memset(filter_info->fivetuple_mask, 0,
1288                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295 {
1296         struct rte_pci_device *pci_dev;
1297         struct ixgbe_hw *hw;
1298
1299         PMD_INIT_FUNC_TRACE();
1300
1301         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302                 return -EPERM;
1303
1304         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1305         pci_dev = eth_dev->pci_dev;
1306
1307         if (hw->adapter_stopped == 0)
1308                 ixgbe_dev_close(eth_dev);
1309
1310         eth_dev->dev_ops = NULL;
1311         eth_dev->rx_pkt_burst = NULL;
1312         eth_dev->tx_pkt_burst = NULL;
1313
1314         /* Unlock any pending hardware semaphore */
1315         ixgbe_swfw_lock_reset(hw);
1316
1317         /* disable uio intr before callback unregister */
1318         rte_intr_disable(&(pci_dev->intr_handle));
1319         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1320                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1321
1322         /* uninitialize PF if max_vfs not zero */
1323         ixgbe_pf_host_uninit(eth_dev);
1324
1325         rte_free(eth_dev->data->mac_addrs);
1326         eth_dev->data->mac_addrs = NULL;
1327
1328         rte_free(eth_dev->data->hash_mac_addrs);
1329         eth_dev->data->hash_mac_addrs = NULL;
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * Negotiate mailbox API version with the PF.
1336  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337  * Then we try to negotiate starting with the most recent one.
1338  * If all negotiation attempts fail, then we will proceed with
1339  * the default one (ixgbe_mbox_api_10).
1340  */
1341 static void
1342 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1343 {
1344         int32_t i;
1345
1346         /* start with highest supported, proceed down */
1347         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1348                 ixgbe_mbox_api_12,
1349                 ixgbe_mbox_api_11,
1350                 ixgbe_mbox_api_10,
1351         };
1352
1353         for (i = 0;
1354                         i != RTE_DIM(sup_ver) &&
1355                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1356                         i++)
1357                 ;
1358 }
1359
1360 static void
1361 generate_random_mac_addr(struct ether_addr *mac_addr)
1362 {
1363         uint64_t random;
1364
1365         /* Set Organizationally Unique Identifier (OUI) prefix. */
1366         mac_addr->addr_bytes[0] = 0x00;
1367         mac_addr->addr_bytes[1] = 0x09;
1368         mac_addr->addr_bytes[2] = 0xC0;
1369         /* Force indication of locally assigned MAC address. */
1370         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371         /* Generate the last 3 bytes of the MAC address with a random number. */
1372         random = rte_rand();
1373         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1374 }
1375
1376 /*
1377  * Virtual Function device init
1378  */
1379 static int
1380 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1381 {
1382         int diag;
1383         uint32_t tc, tcs;
1384         struct rte_pci_device *pci_dev;
1385         struct ixgbe_hw *hw =
1386                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1387         struct ixgbe_vfta *shadow_vfta =
1388                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1389         struct ixgbe_hwstrip *hwstrip =
1390                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1391         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1392
1393         PMD_INIT_FUNC_TRACE();
1394
1395         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1396         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1397         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1398
1399         /* for secondary processes, we don't initialise any further as primary
1400          * has already done this work. Only check we don't need a different
1401          * RX function
1402          */
1403         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1404                 struct ixgbe_tx_queue *txq;
1405                 /* TX queue function in primary, set by last queue initialized
1406                  * Tx queue may not initialized by primary process
1407                  */
1408                 if (eth_dev->data->tx_queues) {
1409                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1410                         ixgbe_set_tx_function(eth_dev, txq);
1411                 } else {
1412                         /* Use default TX function if we get here */
1413                         PMD_INIT_LOG(NOTICE,
1414                                      "No TX queues configured yet. Using default TX function.");
1415                 }
1416
1417                 ixgbe_set_rx_function(eth_dev);
1418
1419                 return 0;
1420         }
1421
1422         pci_dev = eth_dev->pci_dev;
1423
1424         rte_eth_copy_pci_info(eth_dev, pci_dev);
1425
1426         hw->device_id = pci_dev->id.device_id;
1427         hw->vendor_id = pci_dev->id.vendor_id;
1428         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1429
1430         /* initialize the vfta */
1431         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1432
1433         /* initialize the hw strip bitmap*/
1434         memset(hwstrip, 0, sizeof(*hwstrip));
1435
1436         /* Initialize the shared code (base driver) */
1437         diag = ixgbe_init_shared_code(hw);
1438         if (diag != IXGBE_SUCCESS) {
1439                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1440                 return -EIO;
1441         }
1442
1443         /* init_mailbox_params */
1444         hw->mbx.ops.init_params(hw);
1445
1446         /* Reset the hw statistics */
1447         ixgbevf_dev_stats_reset(eth_dev);
1448
1449         /* Disable the interrupts for VF */
1450         ixgbevf_intr_disable(hw);
1451
1452         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1453         diag = hw->mac.ops.reset_hw(hw);
1454
1455         /*
1456          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1457          * the underlying PF driver has not assigned a MAC address to the VF.
1458          * In this case, assign a random MAC address.
1459          */
1460         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1461                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1462                 return diag;
1463         }
1464
1465         /* negotiate mailbox API version to use with the PF. */
1466         ixgbevf_negotiate_api(hw);
1467
1468         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1469         ixgbevf_get_queues(hw, &tcs, &tc);
1470
1471         /* Allocate memory for storing MAC addresses */
1472         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1473                                                hw->mac.num_rar_entries, 0);
1474         if (eth_dev->data->mac_addrs == NULL) {
1475                 PMD_INIT_LOG(ERR,
1476                              "Failed to allocate %u bytes needed to store "
1477                              "MAC addresses",
1478                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1479                 return -ENOMEM;
1480         }
1481
1482         /* Generate a random MAC address, if none was assigned by PF. */
1483         if (is_zero_ether_addr(perm_addr)) {
1484                 generate_random_mac_addr(perm_addr);
1485                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1486                 if (diag) {
1487                         rte_free(eth_dev->data->mac_addrs);
1488                         eth_dev->data->mac_addrs = NULL;
1489                         return diag;
1490                 }
1491                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1492                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1493                              "%02x:%02x:%02x:%02x:%02x:%02x",
1494                              perm_addr->addr_bytes[0],
1495                              perm_addr->addr_bytes[1],
1496                              perm_addr->addr_bytes[2],
1497                              perm_addr->addr_bytes[3],
1498                              perm_addr->addr_bytes[4],
1499                              perm_addr->addr_bytes[5]);
1500         }
1501
1502         /* Copy the permanent MAC address */
1503         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1504
1505         /* reset the hardware with the new settings */
1506         diag = hw->mac.ops.start_hw(hw);
1507         switch (diag) {
1508         case  0:
1509                 break;
1510
1511         default:
1512                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1513                 return -EIO;
1514         }
1515
1516         rte_intr_callback_register(&pci_dev->intr_handle,
1517                                    ixgbevf_dev_interrupt_handler,
1518                                    (void *)eth_dev);
1519         rte_intr_enable(&pci_dev->intr_handle);
1520         ixgbevf_intr_enable(hw);
1521
1522         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1523                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1524                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1525
1526         return 0;
1527 }
1528
1529 /* Virtual Function device uninit */
1530
1531 static int
1532 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1533 {
1534         struct ixgbe_hw *hw;
1535         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540                 return -EPERM;
1541
1542         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1543
1544         if (hw->adapter_stopped == 0)
1545                 ixgbevf_dev_close(eth_dev);
1546
1547         eth_dev->dev_ops = NULL;
1548         eth_dev->rx_pkt_burst = NULL;
1549         eth_dev->tx_pkt_burst = NULL;
1550
1551         /* Disable the interrupts for VF */
1552         ixgbevf_intr_disable(hw);
1553
1554         rte_free(eth_dev->data->mac_addrs);
1555         eth_dev->data->mac_addrs = NULL;
1556
1557         rte_intr_disable(&pci_dev->intr_handle);
1558         rte_intr_callback_unregister(&pci_dev->intr_handle,
1559                                      ixgbevf_dev_interrupt_handler,
1560                                      (void *)eth_dev);
1561
1562         return 0;
1563 }
1564
1565 static struct eth_driver rte_ixgbe_pmd = {
1566         .pci_drv = {
1567                 .id_table = pci_id_ixgbe_map,
1568                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1569                         RTE_PCI_DRV_DETACHABLE,
1570                 .probe = rte_eth_dev_pci_probe,
1571                 .remove = rte_eth_dev_pci_remove,
1572         },
1573         .eth_dev_init = eth_ixgbe_dev_init,
1574         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1575         .dev_private_size = sizeof(struct ixgbe_adapter),
1576 };
1577
1578 /*
1579  * virtual function driver struct
1580  */
1581 static struct eth_driver rte_ixgbevf_pmd = {
1582         .pci_drv = {
1583                 .id_table = pci_id_ixgbevf_map,
1584                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1585                 .probe = rte_eth_dev_pci_probe,
1586                 .remove = rte_eth_dev_pci_remove,
1587         },
1588         .eth_dev_init = eth_ixgbevf_dev_init,
1589         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1590         .dev_private_size = sizeof(struct ixgbe_adapter),
1591 };
1592
1593 static int
1594 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         struct ixgbe_vfta *shadow_vfta =
1599                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1600         uint32_t vfta;
1601         uint32_t vid_idx;
1602         uint32_t vid_bit;
1603
1604         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1605         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1606         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1607         if (on)
1608                 vfta |= vid_bit;
1609         else
1610                 vfta &= ~vid_bit;
1611         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1612
1613         /* update local VFTA copy */
1614         shadow_vfta->vfta[vid_idx] = vfta;
1615
1616         return 0;
1617 }
1618
1619 static void
1620 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1621 {
1622         if (on)
1623                 ixgbe_vlan_hw_strip_enable(dev, queue);
1624         else
1625                 ixgbe_vlan_hw_strip_disable(dev, queue);
1626 }
1627
1628 static int
1629 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1630                     enum rte_vlan_type vlan_type,
1631                     uint16_t tpid)
1632 {
1633         struct ixgbe_hw *hw =
1634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         int ret = 0;
1636         uint32_t reg;
1637         uint32_t qinq;
1638
1639         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1640         qinq &= IXGBE_DMATXCTL_GDV;
1641
1642         switch (vlan_type) {
1643         case ETH_VLAN_TYPE_INNER:
1644                 if (qinq) {
1645                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1646                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1647                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1648                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1649                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1650                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1651                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1652                 } else {
1653                         ret = -ENOTSUP;
1654                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1655                                     " by single VLAN");
1656                 }
1657                 break;
1658         case ETH_VLAN_TYPE_OUTER:
1659                 if (qinq) {
1660                         /* Only the high 16-bits is valid */
1661                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1662                                         IXGBE_EXVET_VET_EXT_SHIFT);
1663                 } else {
1664                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1665                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1666                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1667                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1668                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1669                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1670                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1671                 }
1672
1673                 break;
1674         default:
1675                 ret = -EINVAL;
1676                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1677                 break;
1678         }
1679
1680         return ret;
1681 }
1682
1683 void
1684 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1685 {
1686         struct ixgbe_hw *hw =
1687                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688         uint32_t vlnctrl;
1689
1690         PMD_INIT_FUNC_TRACE();
1691
1692         /* Filter Table Disable */
1693         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1695
1696         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1697 }
1698
1699 void
1700 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1701 {
1702         struct ixgbe_hw *hw =
1703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704         struct ixgbe_vfta *shadow_vfta =
1705                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1706         uint32_t vlnctrl;
1707         uint16_t i;
1708
1709         PMD_INIT_FUNC_TRACE();
1710
1711         /* Filter Table Enable */
1712         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1713         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1714         vlnctrl |= IXGBE_VLNCTRL_VFE;
1715
1716         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1717
1718         /* write whatever is in local vfta copy */
1719         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1720                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1721 }
1722
1723 static void
1724 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1725 {
1726         struct ixgbe_hwstrip *hwstrip =
1727                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1728         struct ixgbe_rx_queue *rxq;
1729
1730         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1731                 return;
1732
1733         if (on)
1734                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1735         else
1736                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1737
1738         if (queue >= dev->data->nb_rx_queues)
1739                 return;
1740
1741         rxq = dev->data->rx_queues[queue];
1742
1743         if (on)
1744                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1745         else
1746                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1747 }
1748
1749 static void
1750 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1751 {
1752         struct ixgbe_hw *hw =
1753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         uint32_t ctrl;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         if (hw->mac.type == ixgbe_mac_82598EB) {
1759                 /* No queue level support */
1760                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1761                 return;
1762         }
1763
1764         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1765         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1766         ctrl &= ~IXGBE_RXDCTL_VME;
1767         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1768
1769         /* record those setting for HW strip per queue */
1770         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         if (hw->mac.type == ixgbe_mac_82598EB) {
1783                 /* No queue level supported */
1784                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1785                 return;
1786         }
1787
1788         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1789         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1790         ctrl |= IXGBE_RXDCTL_VME;
1791         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1792
1793         /* record those setting for HW strip per queue */
1794         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1795 }
1796
1797 void
1798 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1799 {
1800         struct ixgbe_hw *hw =
1801                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802         uint32_t ctrl;
1803         uint16_t i;
1804         struct ixgbe_rx_queue *rxq;
1805
1806         PMD_INIT_FUNC_TRACE();
1807
1808         if (hw->mac.type == ixgbe_mac_82598EB) {
1809                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1810                 ctrl &= ~IXGBE_VLNCTRL_VME;
1811                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1812         } else {
1813                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1814                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1815                         rxq = dev->data->rx_queues[i];
1816                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1817                         ctrl &= ~IXGBE_RXDCTL_VME;
1818                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1819
1820                         /* record those setting for HW strip per queue */
1821                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1822                 }
1823         }
1824 }
1825
1826 void
1827 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1828 {
1829         struct ixgbe_hw *hw =
1830                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831         uint32_t ctrl;
1832         uint16_t i;
1833         struct ixgbe_rx_queue *rxq;
1834
1835         PMD_INIT_FUNC_TRACE();
1836
1837         if (hw->mac.type == ixgbe_mac_82598EB) {
1838                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1839                 ctrl |= IXGBE_VLNCTRL_VME;
1840                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1841         } else {
1842                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1843                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1844                         rxq = dev->data->rx_queues[i];
1845                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1846                         ctrl |= IXGBE_RXDCTL_VME;
1847                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1848
1849                         /* record those setting for HW strip per queue */
1850                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1851                 }
1852         }
1853 }
1854
1855 static void
1856 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         uint32_t ctrl;
1861
1862         PMD_INIT_FUNC_TRACE();
1863
1864         /* DMATXCTRL: Geric Double VLAN Disable */
1865         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866         ctrl &= ~IXGBE_DMATXCTL_GDV;
1867         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1868
1869         /* CTRL_EXT: Global Double VLAN Disable */
1870         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1871         ctrl &= ~IXGBE_EXTENDED_VLAN;
1872         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1873
1874 }
1875
1876 static void
1877 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1878 {
1879         struct ixgbe_hw *hw =
1880                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881         uint32_t ctrl;
1882
1883         PMD_INIT_FUNC_TRACE();
1884
1885         /* DMATXCTRL: Geric Double VLAN Enable */
1886         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         ctrl |= IXGBE_DMATXCTL_GDV;
1888         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1889
1890         /* CTRL_EXT: Global Double VLAN Enable */
1891         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1892         ctrl |= IXGBE_EXTENDED_VLAN;
1893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1894
1895         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1896         if (hw->mac.type == ixgbe_mac_X550 ||
1897             hw->mac.type == ixgbe_mac_X550EM_x ||
1898             hw->mac.type == ixgbe_mac_X550EM_a) {
1899                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1900                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1901                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1902         }
1903
1904         /*
1905          * VET EXT field in the EXVET register = 0x8100 by default
1906          * So no need to change. Same to VT field of DMATXCTL register
1907          */
1908 }
1909
1910 static void
1911 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1912 {
1913         if (mask & ETH_VLAN_STRIP_MASK) {
1914                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1915                         ixgbe_vlan_hw_strip_enable_all(dev);
1916                 else
1917                         ixgbe_vlan_hw_strip_disable_all(dev);
1918         }
1919
1920         if (mask & ETH_VLAN_FILTER_MASK) {
1921                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1922                         ixgbe_vlan_hw_filter_enable(dev);
1923                 else
1924                         ixgbe_vlan_hw_filter_disable(dev);
1925         }
1926
1927         if (mask & ETH_VLAN_EXTEND_MASK) {
1928                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1929                         ixgbe_vlan_hw_extend_enable(dev);
1930                 else
1931                         ixgbe_vlan_hw_extend_disable(dev);
1932         }
1933 }
1934
1935 static void
1936 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1937 {
1938         struct ixgbe_hw *hw =
1939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1941         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942
1943         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1944         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1945 }
1946
1947 static int
1948 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1949 {
1950         switch (nb_rx_q) {
1951         case 1:
1952         case 2:
1953                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1954                 break;
1955         case 4:
1956                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1964
1965         return 0;
1966 }
1967
1968 static int
1969 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1970 {
1971         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1975
1976         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977                 /* check multi-queue mode */
1978                 switch (dev_conf->rxmode.mq_mode) {
1979                 case ETH_MQ_RX_VMDQ_DCB:
1980                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1981                         break;
1982                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984                         PMD_INIT_LOG(ERR, "SRIOV active,"
1985                                         " unsupported mq_mode rx %d.",
1986                                         dev_conf->rxmode.mq_mode);
1987                         return -EINVAL;
1988                 case ETH_MQ_RX_RSS:
1989                 case ETH_MQ_RX_VMDQ_RSS:
1990                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                                 " invalid queue number"
1995                                                 " for VMDQ RSS, allowed"
1996                                                 " value are 1, 2 or 4.");
1997                                         return -EINVAL;
1998                                 }
1999                         break;
2000                 case ETH_MQ_RX_VMDQ_ONLY:
2001                 case ETH_MQ_RX_NONE:
2002                         /* if nothing mq mode configure, use default scheme */
2003                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2006                         break;
2007                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008                         /* SRIOV only works in VMDq enable mode */
2009                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2010                                         " wrong mq_mode rx %d.",
2011                                         dev_conf->rxmode.mq_mode);
2012                         return -EINVAL;
2013                 }
2014
2015                 switch (dev_conf->txmode.mq_mode) {
2016                 case ETH_MQ_TX_VMDQ_DCB:
2017                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2019                         break;
2020                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2022                         break;
2023                 }
2024
2025                 /* check valid queue number */
2026                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2029                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2030                                         " must be less than or equal to %d.",
2031                                         nb_rx_q, nb_tx_q,
2032                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2033                         return -EINVAL;
2034                 }
2035         } else {
2036                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2038                                           " not supported.");
2039                         return -EINVAL;
2040                 }
2041                 /* check configuration for vmdb+dcb mode */
2042                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043                         const struct rte_eth_vmdq_dcb_conf *conf;
2044
2045                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2048                                 return -EINVAL;
2049                         }
2050                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052                                conf->nb_queue_pools == ETH_32_POOLS)) {
2053                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054                                                 " nb_queue_pools must be %d or %d.",
2055                                                 ETH_16_POOLS, ETH_32_POOLS);
2056                                 return -EINVAL;
2057                         }
2058                 }
2059                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2061
2062                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2065                                 return -EINVAL;
2066                         }
2067                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069                                conf->nb_queue_pools == ETH_32_POOLS)) {
2070                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071                                                 " nb_queue_pools != %d and"
2072                                                 " nb_queue_pools != %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077
2078                 /* For DCB mode check our configuration before we go further */
2079                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080                         const struct rte_eth_dcb_rx_conf *conf;
2081
2082                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084                                                  IXGBE_DCB_NB_QUEUES);
2085                                 return -EINVAL;
2086                         }
2087                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088                         if (!(conf->nb_tcs == ETH_4_TCS ||
2089                                conf->nb_tcs == ETH_8_TCS)) {
2090                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091                                                 " and nb_tcs != %d.",
2092                                                 ETH_4_TCS, ETH_8_TCS);
2093                                 return -EINVAL;
2094                         }
2095                 }
2096
2097                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098                         const struct rte_eth_dcb_tx_conf *conf;
2099
2100                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102                                                  IXGBE_DCB_NB_QUEUES);
2103                                 return -EINVAL;
2104                         }
2105                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106                         if (!(conf->nb_tcs == ETH_4_TCS ||
2107                                conf->nb_tcs == ETH_8_TCS)) {
2108                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109                                                 " and nb_tcs != %d.",
2110                                                 ETH_4_TCS, ETH_8_TCS);
2111                                 return -EINVAL;
2112                         }
2113                 }
2114
2115                 /*
2116                  * When DCB/VT is off, maximum number of queues changes,
2117                  * except for 82598EB, which remains constant.
2118                  */
2119                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120                                 hw->mac.type != ixgbe_mac_82598EB) {
2121                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2122                                 PMD_INIT_LOG(ERR,
2123                                              "Neither VT nor DCB are enabled, "
2124                                              "nb_tx_q > %d.",
2125                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2126                                 return -EINVAL;
2127                         }
2128                 }
2129         }
2130         return 0;
2131 }
2132
2133 static int
2134 ixgbe_dev_configure(struct rte_eth_dev *dev)
2135 {
2136         struct ixgbe_interrupt *intr =
2137                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138         struct ixgbe_adapter *adapter =
2139                 (struct ixgbe_adapter *)dev->data->dev_private;
2140         int ret;
2141
2142         PMD_INIT_FUNC_TRACE();
2143         /* multipe queue mode checking */
2144         ret  = ixgbe_check_mq_mode(dev);
2145         if (ret != 0) {
2146                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147                             ret);
2148                 return ret;
2149         }
2150
2151         /* set flag to update link status after init */
2152         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2153
2154         /*
2155          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156          * allocation or vector Rx preconditions we will reset it.
2157          */
2158         adapter->rx_bulk_alloc_allowed = true;
2159         adapter->rx_vec_allowed = true;
2160
2161         return 0;
2162 }
2163
2164 static void
2165 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct ixgbe_interrupt *intr =
2170                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2171         uint32_t gpie;
2172
2173         /* only set up it on X550EM_X */
2174         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180         }
2181 }
2182
2183 /*
2184  * Configure device link speed and setup link.
2185  * It returns 0 on success.
2186  */
2187 static int
2188 ixgbe_dev_start(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw =
2191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct ixgbe_vf_info *vfinfo =
2193                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2195         uint32_t intr_vector = 0;
2196         int err, link_up = 0, negotiate = 0;
2197         uint32_t speed = 0;
2198         int mask = 0;
2199         int status;
2200         uint16_t vf, idx;
2201         uint32_t *link_speeds;
2202
2203         PMD_INIT_FUNC_TRACE();
2204
2205         /* IXGBE devices don't support:
2206         *    - half duplex (checked afterwards for valid speeds)
2207         *    - fixed speed: TODO implement
2208         */
2209         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2210                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2211                              dev->data->port_id);
2212                 return -EINVAL;
2213         }
2214
2215         /* disable uio/vfio intr/eventfd mapping */
2216         rte_intr_disable(intr_handle);
2217
2218         /* stop adapter */
2219         hw->adapter_stopped = 0;
2220         ixgbe_stop_adapter(hw);
2221
2222         /* reinitialize adapter
2223          * this calls reset and start
2224          */
2225         status = ixgbe_pf_reset_hw(hw);
2226         if (status != 0)
2227                 return -1;
2228         hw->mac.ops.start_hw(hw);
2229         hw->mac.get_link_status = true;
2230
2231         /* configure PF module if SRIOV enabled */
2232         ixgbe_pf_host_configure(dev);
2233
2234         ixgbe_dev_phy_intr_setup(dev);
2235
2236         /* check and configure queue intr-vector mapping */
2237         if ((rte_intr_cap_multiple(intr_handle) ||
2238              !RTE_ETH_DEV_SRIOV(dev).active) &&
2239             dev->data->dev_conf.intr_conf.rxq != 0) {
2240                 intr_vector = dev->data->nb_rx_queues;
2241                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2242                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2243                                         IXGBE_MAX_INTR_QUEUE_NUM);
2244                         return -ENOTSUP;
2245                 }
2246                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2247                         return -1;
2248         }
2249
2250         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2251                 intr_handle->intr_vec =
2252                         rte_zmalloc("intr_vec",
2253                                     dev->data->nb_rx_queues * sizeof(int), 0);
2254                 if (intr_handle->intr_vec == NULL) {
2255                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2256                                      " intr_vec\n", dev->data->nb_rx_queues);
2257                         return -ENOMEM;
2258                 }
2259         }
2260
2261         /* confiugre msix for sleep until rx interrupt */
2262         ixgbe_configure_msix(dev);
2263
2264         /* initialize transmission unit */
2265         ixgbe_dev_tx_init(dev);
2266
2267         /* This can fail when allocating mbufs for descriptor rings */
2268         err = ixgbe_dev_rx_init(dev);
2269         if (err) {
2270                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2271                 goto error;
2272         }
2273
2274     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2275                 ETH_VLAN_EXTEND_MASK;
2276         ixgbe_vlan_offload_set(dev, mask);
2277
2278         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2279                 /* Enable vlan filtering for VMDq */
2280                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2281         }
2282
2283         /* Configure DCB hw */
2284         ixgbe_configure_dcb(dev);
2285
2286         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2287                 err = ixgbe_fdir_configure(dev);
2288                 if (err)
2289                         goto error;
2290         }
2291
2292         /* Restore vf rate limit */
2293         if (vfinfo != NULL) {
2294                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2295                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2296                                 if (vfinfo[vf].tx_rate[idx] != 0)
2297                                         ixgbe_set_vf_rate_limit(dev, vf,
2298                                                 vfinfo[vf].tx_rate[idx],
2299                                                 1 << idx);
2300         }
2301
2302         ixgbe_restore_statistics_mapping(dev);
2303
2304         err = ixgbe_dev_rxtx_start(dev);
2305         if (err < 0) {
2306                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2307                 goto error;
2308         }
2309
2310         /* Skip link setup if loopback mode is enabled for 82599. */
2311         if (hw->mac.type == ixgbe_mac_82599EB &&
2312                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2313                 goto skip_link_setup;
2314
2315         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2316                 err = hw->mac.ops.setup_sfp(hw);
2317                 if (err)
2318                         goto error;
2319         }
2320
2321         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2322                 /* Turn on the copper */
2323                 ixgbe_set_phy_power(hw, true);
2324         } else {
2325                 /* Turn on the laser */
2326                 ixgbe_enable_tx_laser(hw);
2327         }
2328
2329         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2330         if (err)
2331                 goto error;
2332         dev->data->dev_link.link_status = link_up;
2333
2334         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2335         if (err)
2336                 goto error;
2337
2338         link_speeds = &dev->data->dev_conf.link_speeds;
2339         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2340                         ETH_LINK_SPEED_10G)) {
2341                 PMD_INIT_LOG(ERR, "Invalid link setting");
2342                 goto error;
2343         }
2344
2345         speed = 0x0;
2346         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2347                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2348                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2349                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2350         } else {
2351                 if (*link_speeds & ETH_LINK_SPEED_10G)
2352                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2353                 if (*link_speeds & ETH_LINK_SPEED_1G)
2354                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2355                 if (*link_speeds & ETH_LINK_SPEED_100M)
2356                         speed |= IXGBE_LINK_SPEED_100_FULL;
2357         }
2358
2359         err = ixgbe_setup_link(hw, speed, link_up);
2360         if (err)
2361                 goto error;
2362
2363 skip_link_setup:
2364
2365         if (rte_intr_allow_others(intr_handle)) {
2366                 /* check if lsc interrupt is enabled */
2367                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2368                         ixgbe_dev_lsc_interrupt_setup(dev);
2369         } else {
2370                 rte_intr_callback_unregister(intr_handle,
2371                                              ixgbe_dev_interrupt_handler,
2372                                              (void *)dev);
2373                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375                                      " no intr multiplex\n");
2376         }
2377
2378         /* check if rxq interrupt is enabled */
2379         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380             rte_intr_dp_is_en(intr_handle))
2381                 ixgbe_dev_rxq_interrupt_setup(dev);
2382
2383         /* enable uio/vfio intr/eventfd mapping */
2384         rte_intr_enable(intr_handle);
2385
2386         /* resume enabled intr since hw reset */
2387         ixgbe_enable_intr(dev);
2388
2389         return 0;
2390
2391 error:
2392         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393         ixgbe_dev_clear_queues(dev);
2394         return -EIO;
2395 }
2396
2397 /*
2398  * Stop device: disable rx and tx functions to allow for reconfiguring.
2399  */
2400 static void
2401 ixgbe_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct rte_eth_link link;
2404         struct ixgbe_hw *hw =
2405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         struct ixgbe_vf_info *vfinfo =
2407                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408         struct ixgbe_filter_info *filter_info =
2409                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2412         int vf;
2413
2414         PMD_INIT_FUNC_TRACE();
2415
2416         /* disable interrupts */
2417         ixgbe_disable_intr(hw);
2418
2419         /* reset the NIC */
2420         ixgbe_pf_reset_hw(hw);
2421         hw->adapter_stopped = 0;
2422
2423         /* stop adapter */
2424         ixgbe_stop_adapter(hw);
2425
2426         for (vf = 0; vfinfo != NULL &&
2427                      vf < dev->pci_dev->max_vfs; vf++)
2428                 vfinfo[vf].clear_to_send = false;
2429
2430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431                 /* Turn off the copper */
2432                 ixgbe_set_phy_power(hw, false);
2433         } else {
2434                 /* Turn off the laser */
2435                 ixgbe_disable_tx_laser(hw);
2436         }
2437
2438         ixgbe_dev_clear_queues(dev);
2439
2440         /* Clear stored conf */
2441         dev->data->scattered_rx = 0;
2442         dev->data->lro = 0;
2443
2444         /* Clear recorded link status */
2445         memset(&link, 0, sizeof(link));
2446         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2447
2448         /* Remove all ntuple filters of the device */
2449         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2453                              p_5tuple, entries);
2454                 rte_free(p_5tuple);
2455         }
2456         memset(filter_info->fivetuple_mask, 0,
2457                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2458
2459         if (!rte_intr_allow_others(intr_handle))
2460                 /* resume to the default handler */
2461                 rte_intr_callback_register(intr_handle,
2462                                            ixgbe_dev_interrupt_handler,
2463                                            (void *)dev);
2464
2465         /* Clean datapath event and queue/vec mapping */
2466         rte_intr_efd_disable(intr_handle);
2467         if (intr_handle->intr_vec != NULL) {
2468                 rte_free(intr_handle->intr_vec);
2469                 intr_handle->intr_vec = NULL;
2470         }
2471 }
2472
2473 /*
2474  * Set device link up: enable tx.
2475  */
2476 static int
2477 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw =
2480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         if (hw->mac.type == ixgbe_mac_82599EB) {
2482 #ifdef RTE_NIC_BYPASS
2483                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484                         /* Not suported in bypass mode */
2485                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2486                                      "by device id 0x%x", hw->device_id);
2487                         return -ENOTSUP;
2488                 }
2489 #endif
2490         }
2491
2492         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493                 /* Turn on the copper */
2494                 ixgbe_set_phy_power(hw, true);
2495         } else {
2496                 /* Turn on the laser */
2497                 ixgbe_enable_tx_laser(hw);
2498         }
2499
2500         return 0;
2501 }
2502
2503 /*
2504  * Set device link down: disable tx.
2505  */
2506 static int
2507 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2508 {
2509         struct ixgbe_hw *hw =
2510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         if (hw->mac.type == ixgbe_mac_82599EB) {
2512 #ifdef RTE_NIC_BYPASS
2513                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514                         /* Not suported in bypass mode */
2515                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2516                                      "by device id 0x%x", hw->device_id);
2517                         return -ENOTSUP;
2518                 }
2519 #endif
2520         }
2521
2522         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523                 /* Turn off the copper */
2524                 ixgbe_set_phy_power(hw, false);
2525         } else {
2526                 /* Turn off the laser */
2527                 ixgbe_disable_tx_laser(hw);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * Reest and stop device.
2535  */
2536 static void
2537 ixgbe_dev_close(struct rte_eth_dev *dev)
2538 {
2539         struct ixgbe_hw *hw =
2540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542         PMD_INIT_FUNC_TRACE();
2543
2544         ixgbe_pf_reset_hw(hw);
2545
2546         ixgbe_dev_stop(dev);
2547         hw->adapter_stopped = 1;
2548
2549         ixgbe_dev_free_queues(dev);
2550
2551         ixgbe_disable_pcie_master(hw);
2552
2553         /* reprogram the RAR[0] in case user changed it. */
2554         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2555 }
2556
2557 static void
2558 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559                            struct ixgbe_hw_stats *hw_stats,
2560                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561                            uint64_t *total_qprc, uint64_t *total_qprdc)
2562 {
2563         uint32_t bprc, lxon, lxoff, total;
2564         uint32_t delta_gprc = 0;
2565         unsigned i;
2566         /* Workaround for RX byte count not including CRC bytes when CRC
2567 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2568          * is disabled.
2569 +        */
2570         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571                         IXGBE_HLREG0_RXCRCSTRP);
2572
2573         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2577
2578         for (i = 0; i < 8; i++) {
2579                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2580
2581                 /* global total per queue */
2582                 hw_stats->mpc[i] += mp;
2583                 /* Running comprehensive total for stats display */
2584                 *total_missed_rx += hw_stats->mpc[i];
2585                 if (hw->mac.type == ixgbe_mac_82598EB) {
2586                         hw_stats->rnbc[i] +=
2587                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588                         hw_stats->pxonrxc[i] +=
2589                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590                         hw_stats->pxoffrxc[i] +=
2591                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2592                 } else {
2593                         hw_stats->pxonrxc[i] +=
2594                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595                         hw_stats->pxoffrxc[i] +=
2596                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597                         hw_stats->pxon2offc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2599                 }
2600                 hw_stats->pxontxc[i] +=
2601                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602                 hw_stats->pxofftxc[i] +=
2603                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2604         }
2605         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2609
2610                 delta_gprc += delta_qprc;
2611
2612                 hw_stats->qprc[i] += delta_qprc;
2613                 hw_stats->qptc[i] += delta_qptc;
2614
2615                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616                 hw_stats->qbrc[i] +=
2617                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2618                 if (crc_strip == 0)
2619                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2620
2621                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622                 hw_stats->qbtc[i] +=
2623                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2624
2625                 hw_stats->qprdc[i] += delta_qprdc;
2626                 *total_qprdc += hw_stats->qprdc[i];
2627
2628                 *total_qprc += hw_stats->qprc[i];
2629                 *total_qbrc += hw_stats->qbrc[i];
2630         }
2631         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2634
2635         /*
2636          * An errata states that gprc actually counts good + missed packets:
2637          * Workaround to set gprc to summated queue packet receives
2638          */
2639         hw_stats->gprc = *total_qprc;
2640
2641         if (hw->mac.type != ixgbe_mac_82598EB) {
2642                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2650         } else {
2651                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653                 /* 82598 only has a counter in the high register */
2654                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2657         }
2658         uint64_t old_tpr = hw_stats->tpr;
2659
2660         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2662
2663         if (crc_strip == 0)
2664                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2665
2666         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667         hw_stats->gptc += delta_gptc;
2668         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2670
2671         /*
2672          * Workaround: mprc hardware is incorrectly counting
2673          * broadcasts, so for now we subtract those.
2674          */
2675         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676         hw_stats->bprc += bprc;
2677         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678         if (hw->mac.type == ixgbe_mac_82598EB)
2679                 hw_stats->mprc -= bprc;
2680
2681         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2687
2688         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689         hw_stats->lxontxc += lxon;
2690         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691         hw_stats->lxofftxc += lxoff;
2692         total = lxon + lxoff;
2693
2694         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696         hw_stats->gptc -= total;
2697         hw_stats->mptc -= total;
2698         hw_stats->ptc64 -= total;
2699         hw_stats->gotc -= total * ETHER_MIN_LEN;
2700
2701         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717         /* Only read FCOE on 82599 */
2718         if (hw->mac.type != ixgbe_mac_82598EB) {
2719                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2724         }
2725
2726         /* Flow Director Stats registers */
2727         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2729 }
2730
2731 /*
2732  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2733  */
2734 static void
2735 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736 {
2737         struct ixgbe_hw *hw =
2738                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         struct ixgbe_hw_stats *hw_stats =
2740                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2742         unsigned i;
2743
2744         total_missed_rx = 0;
2745         total_qbrc = 0;
2746         total_qprc = 0;
2747         total_qprdc = 0;
2748
2749         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750                         &total_qprc, &total_qprdc);
2751
2752         if (stats == NULL)
2753                 return;
2754
2755         /* Fill out the rte_eth_stats statistics structure */
2756         stats->ipackets = total_qprc;
2757         stats->ibytes = total_qbrc;
2758         stats->opackets = hw_stats->gptc;
2759         stats->obytes = hw_stats->gotc;
2760
2761         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762                 stats->q_ipackets[i] = hw_stats->qprc[i];
2763                 stats->q_opackets[i] = hw_stats->qptc[i];
2764                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765                 stats->q_obytes[i] = hw_stats->qbtc[i];
2766                 stats->q_errors[i] = hw_stats->qprdc[i];
2767         }
2768
2769         /* Rx Errors */
2770         stats->imissed  = total_missed_rx;
2771         stats->ierrors  = hw_stats->crcerrs +
2772                           hw_stats->mspdc +
2773                           hw_stats->rlec +
2774                           hw_stats->ruc +
2775                           hw_stats->roc +
2776                           hw_stats->illerrc +
2777                           hw_stats->errbc +
2778                           hw_stats->rfc +
2779                           hw_stats->fccrc +
2780                           hw_stats->fclast;
2781
2782         /* Tx Errors */
2783         stats->oerrors  = 0;
2784 }
2785
2786 static void
2787 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw_stats *stats =
2790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792         /* HW registers are cleared on read */
2793         ixgbe_dev_stats_get(dev, NULL);
2794
2795         /* Reset software totals */
2796         memset(stats, 0, sizeof(*stats));
2797 }
2798
2799 /* This function calculates the number of xstats based on the current config */
2800 static unsigned
2801 ixgbe_xstats_calc_num(void) {
2802         return IXGBE_NB_HW_STATS +
2803                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2805 }
2806
2807 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2809 {
2810         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811         unsigned stat, i, count;
2812
2813         if (xstats_names != NULL) {
2814                 count = 0;
2815
2816                 /* Note: limit >= cnt_stats checked upstream
2817                  * in rte_eth_xstats_names()
2818                  */
2819
2820                 /* Extended stats from ixgbe_hw_stats */
2821                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822                         snprintf(xstats_names[count].name,
2823                                 sizeof(xstats_names[count].name),
2824                                 "%s",
2825                                 rte_ixgbe_stats_strings[i].name);
2826                         count++;
2827                 }
2828
2829                 /* RX Priority Stats */
2830                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832                                 snprintf(xstats_names[count].name,
2833                                         sizeof(xstats_names[count].name),
2834                                         "rx_priority%u_%s", i,
2835                                         rte_ixgbe_rxq_strings[stat].name);
2836                                 count++;
2837                         }
2838                 }
2839
2840                 /* TX Priority Stats */
2841                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843                                 snprintf(xstats_names[count].name,
2844                                         sizeof(xstats_names[count].name),
2845                                         "tx_priority%u_%s", i,
2846                                         rte_ixgbe_txq_strings[stat].name);
2847                                 count++;
2848                         }
2849                 }
2850         }
2851         return cnt_stats;
2852 }
2853
2854 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2856 {
2857         unsigned i;
2858
2859         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2860                 return -ENOMEM;
2861
2862         if (xstats_names != NULL)
2863                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864                         snprintf(xstats_names[i].name,
2865                                 sizeof(xstats_names[i].name),
2866                                 "%s", rte_ixgbevf_stats_strings[i].name);
2867         return IXGBEVF_NB_XSTATS;
2868 }
2869
2870 static int
2871 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2872                                          unsigned n)
2873 {
2874         struct ixgbe_hw *hw =
2875                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_hw_stats *hw_stats =
2877                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879         unsigned i, stat, count = 0;
2880
2881         count = ixgbe_xstats_calc_num();
2882
2883         if (n < count)
2884                 return count;
2885
2886         total_missed_rx = 0;
2887         total_qbrc = 0;
2888         total_qprc = 0;
2889         total_qprdc = 0;
2890
2891         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892                                    &total_qprc, &total_qprdc);
2893
2894         /* If this is a reset xstats is NULL, and we have cleared the
2895          * registers by reading them.
2896          */
2897         if (!xstats)
2898                 return 0;
2899
2900         /* Extended stats from ixgbe_hw_stats */
2901         count = 0;
2902         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904                                 rte_ixgbe_stats_strings[i].offset);
2905                 xstats[count].id = count;
2906                 count++;
2907         }
2908
2909         /* RX Priority Stats */
2910         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2911                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2912                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2913                                         rte_ixgbe_rxq_strings[stat].offset +
2914                                         (sizeof(uint64_t) * i));
2915                         xstats[count].id = count;
2916                         count++;
2917                 }
2918         }
2919
2920         /* TX Priority Stats */
2921         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2922                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2923                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2924                                         rte_ixgbe_txq_strings[stat].offset +
2925                                         (sizeof(uint64_t) * i));
2926                         xstats[count].id = count;
2927                         count++;
2928                 }
2929         }
2930         return count;
2931 }
2932
2933 static void
2934 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2935 {
2936         struct ixgbe_hw_stats *stats =
2937                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2938
2939         unsigned count = ixgbe_xstats_calc_num();
2940
2941         /* HW registers are cleared on read */
2942         ixgbe_dev_xstats_get(dev, NULL, count);
2943
2944         /* Reset software totals */
2945         memset(stats, 0, sizeof(*stats));
2946 }
2947
2948 static void
2949 ixgbevf_update_stats(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2953                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2954
2955         /* Good Rx packet, include VF loopback */
2956         UPDATE_VF_STAT(IXGBE_VFGPRC,
2957             hw_stats->last_vfgprc, hw_stats->vfgprc);
2958
2959         /* Good Rx octets, include VF loopback */
2960         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2961             hw_stats->last_vfgorc, hw_stats->vfgorc);
2962
2963         /* Good Tx packet, include VF loopback */
2964         UPDATE_VF_STAT(IXGBE_VFGPTC,
2965             hw_stats->last_vfgptc, hw_stats->vfgptc);
2966
2967         /* Good Tx octets, include VF loopback */
2968         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2969             hw_stats->last_vfgotc, hw_stats->vfgotc);
2970
2971         /* Rx Multicst Packet */
2972         UPDATE_VF_STAT(IXGBE_VFMPRC,
2973             hw_stats->last_vfmprc, hw_stats->vfmprc);
2974 }
2975
2976 static int
2977 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2978                        unsigned n)
2979 {
2980         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2981                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2982         unsigned i;
2983
2984         if (n < IXGBEVF_NB_XSTATS)
2985                 return IXGBEVF_NB_XSTATS;
2986
2987         ixgbevf_update_stats(dev);
2988
2989         if (!xstats)
2990                 return 0;
2991
2992         /* Extended stats */
2993         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2994                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2995                         rte_ixgbevf_stats_strings[i].offset);
2996         }
2997
2998         return IXGBEVF_NB_XSTATS;
2999 }
3000
3001 static void
3002 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3003 {
3004         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3005                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3006
3007         ixgbevf_update_stats(dev);
3008
3009         if (stats == NULL)
3010                 return;
3011
3012         stats->ipackets = hw_stats->vfgprc;
3013         stats->ibytes = hw_stats->vfgorc;
3014         stats->opackets = hw_stats->vfgptc;
3015         stats->obytes = hw_stats->vfgotc;
3016 }
3017
3018 static void
3019 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3022                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3023
3024         /* Sync HW register to the last stats */
3025         ixgbevf_dev_stats_get(dev, NULL);
3026
3027         /* reset HW current stats*/
3028         hw_stats->vfgprc = 0;
3029         hw_stats->vfgorc = 0;
3030         hw_stats->vfgptc = 0;
3031         hw_stats->vfgotc = 0;
3032 }
3033
3034 static void
3035 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3036 {
3037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3039
3040         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3041         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3042         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3043                 /*
3044                  * When DCB/VT is off, maximum number of queues changes,
3045                  * except for 82598EB, which remains constant.
3046                  */
3047                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3048                                 hw->mac.type != ixgbe_mac_82598EB)
3049                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3050         }
3051         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3052         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3053         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3054         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3055         dev_info->max_vfs = dev->pci_dev->max_vfs;
3056         if (hw->mac.type == ixgbe_mac_82598EB)
3057                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3058         else
3059                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3060         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3061         dev_info->rx_offload_capa =
3062                 DEV_RX_OFFLOAD_VLAN_STRIP |
3063                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3064                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3065                 DEV_RX_OFFLOAD_TCP_CKSUM;
3066
3067         /*
3068          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3069          * mode.
3070          */
3071         if ((hw->mac.type == ixgbe_mac_82599EB ||
3072              hw->mac.type == ixgbe_mac_X540) &&
3073             !RTE_ETH_DEV_SRIOV(dev).active)
3074                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3075
3076         if (hw->mac.type == ixgbe_mac_X550 ||
3077             hw->mac.type == ixgbe_mac_X550EM_x ||
3078             hw->mac.type == ixgbe_mac_X550EM_a)
3079                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3080
3081         dev_info->tx_offload_capa =
3082                 DEV_TX_OFFLOAD_VLAN_INSERT |
3083                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3084                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3085                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3086                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3087                 DEV_TX_OFFLOAD_TCP_TSO;
3088
3089         if (hw->mac.type == ixgbe_mac_X550 ||
3090             hw->mac.type == ixgbe_mac_X550EM_x ||
3091             hw->mac.type == ixgbe_mac_X550EM_a)
3092                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3093
3094         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3095                 .rx_thresh = {
3096                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3097                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3098                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3099                 },
3100                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3101                 .rx_drop_en = 0,
3102         };
3103
3104         dev_info->default_txconf = (struct rte_eth_txconf) {
3105                 .tx_thresh = {
3106                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3107                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3108                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3109                 },
3110                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3111                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3112                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3113                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3114         };
3115
3116         dev_info->rx_desc_lim = rx_desc_lim;
3117         dev_info->tx_desc_lim = tx_desc_lim;
3118
3119         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3120         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3121         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3122
3123         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3124         if (hw->mac.type == ixgbe_mac_X540 ||
3125             hw->mac.type == ixgbe_mac_X540_vf ||
3126             hw->mac.type == ixgbe_mac_X550 ||
3127             hw->mac.type == ixgbe_mac_X550_vf) {
3128                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3129         }
3130 }
3131
3132 static const uint32_t *
3133 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3134 {
3135         static const uint32_t ptypes[] = {
3136                 /* For non-vec functions,
3137                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3138                  * for vec functions,
3139                  * refers to _recv_raw_pkts_vec().
3140                  */
3141                 RTE_PTYPE_L2_ETHER,
3142                 RTE_PTYPE_L3_IPV4,
3143                 RTE_PTYPE_L3_IPV4_EXT,
3144                 RTE_PTYPE_L3_IPV6,
3145                 RTE_PTYPE_L3_IPV6_EXT,
3146                 RTE_PTYPE_L4_SCTP,
3147                 RTE_PTYPE_L4_TCP,
3148                 RTE_PTYPE_L4_UDP,
3149                 RTE_PTYPE_TUNNEL_IP,
3150                 RTE_PTYPE_INNER_L3_IPV6,
3151                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3152                 RTE_PTYPE_INNER_L4_TCP,
3153                 RTE_PTYPE_INNER_L4_UDP,
3154                 RTE_PTYPE_UNKNOWN
3155         };
3156
3157         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3158             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3159             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3160             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3161                 return ptypes;
3162         return NULL;
3163 }
3164
3165 static void
3166 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3167                      struct rte_eth_dev_info *dev_info)
3168 {
3169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3170
3171         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3172         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3173         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3174         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3175         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3176         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3177         dev_info->max_vfs = dev->pci_dev->max_vfs;
3178         if (hw->mac.type == ixgbe_mac_82598EB)
3179                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3180         else
3181                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3182         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3183                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3184                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3185                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3186         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3187                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3188                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3189                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3190                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3191                                 DEV_TX_OFFLOAD_TCP_TSO;
3192
3193         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3194                 .rx_thresh = {
3195                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3196                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3197                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3198                 },
3199                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3200                 .rx_drop_en = 0,
3201         };
3202
3203         dev_info->default_txconf = (struct rte_eth_txconf) {
3204                 .tx_thresh = {
3205                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3206                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3207                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3208                 },
3209                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3210                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3211                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3212                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3213         };
3214
3215         dev_info->rx_desc_lim = rx_desc_lim;
3216         dev_info->tx_desc_lim = tx_desc_lim;
3217 }
3218
3219 /* return 0 means link status changed, -1 means not changed */
3220 static int
3221 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3222 {
3223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224         struct rte_eth_link link, old;
3225         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3226         int link_up;
3227         int diag;
3228
3229         link.link_status = ETH_LINK_DOWN;
3230         link.link_speed = 0;
3231         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3232         memset(&old, 0, sizeof(old));
3233         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3234
3235         hw->mac.get_link_status = true;
3236
3237         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3238         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3239                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3240         else
3241                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3242
3243         if (diag != 0) {
3244                 link.link_speed = ETH_SPEED_NUM_100M;
3245                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3246                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3247                 if (link.link_status == old.link_status)
3248                         return -1;
3249                 return 0;
3250         }
3251
3252         if (link_up == 0) {
3253                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3254                 if (link.link_status == old.link_status)
3255                         return -1;
3256                 return 0;
3257         }
3258         link.link_status = ETH_LINK_UP;
3259         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3260
3261         switch (link_speed) {
3262         default:
3263         case IXGBE_LINK_SPEED_UNKNOWN:
3264                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3265                 link.link_speed = ETH_SPEED_NUM_100M;
3266                 break;
3267
3268         case IXGBE_LINK_SPEED_100_FULL:
3269                 link.link_speed = ETH_SPEED_NUM_100M;
3270                 break;
3271
3272         case IXGBE_LINK_SPEED_1GB_FULL:
3273                 link.link_speed = ETH_SPEED_NUM_1G;
3274                 break;
3275
3276         case IXGBE_LINK_SPEED_10GB_FULL:
3277                 link.link_speed = ETH_SPEED_NUM_10G;
3278                 break;
3279         }
3280         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3281
3282         if (link.link_status == old.link_status)
3283                 return -1;
3284
3285         return 0;
3286 }
3287
3288 static void
3289 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3290 {
3291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         uint32_t fctrl;
3293
3294         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3295         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3296         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3297 }
3298
3299 static void
3300 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3301 {
3302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         uint32_t fctrl;
3304
3305         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3306         fctrl &= (~IXGBE_FCTRL_UPE);
3307         if (dev->data->all_multicast == 1)
3308                 fctrl |= IXGBE_FCTRL_MPE;
3309         else
3310                 fctrl &= (~IXGBE_FCTRL_MPE);
3311         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3312 }
3313
3314 static void
3315 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3316 {
3317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         uint32_t fctrl;
3319
3320         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3321         fctrl |= IXGBE_FCTRL_MPE;
3322         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3323 }
3324
3325 static void
3326 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3327 {
3328         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3329         uint32_t fctrl;
3330
3331         if (dev->data->promiscuous == 1)
3332                 return; /* must remain in all_multicast mode */
3333
3334         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3335         fctrl &= (~IXGBE_FCTRL_MPE);
3336         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3337 }
3338
3339 /**
3340  * It clears the interrupt causes and enables the interrupt.
3341  * It will be called once only during nic initialized.
3342  *
3343  * @param dev
3344  *  Pointer to struct rte_eth_dev.
3345  *
3346  * @return
3347  *  - On success, zero.
3348  *  - On failure, a negative value.
3349  */
3350 static int
3351 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3352 {
3353         struct ixgbe_interrupt *intr =
3354                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3355
3356         ixgbe_dev_link_status_print(dev);
3357         intr->mask |= IXGBE_EICR_LSC;
3358
3359         return 0;
3360 }
3361
3362 /**
3363  * It clears the interrupt causes and enables the interrupt.
3364  * It will be called once only during nic initialized.
3365  *
3366  * @param dev
3367  *  Pointer to struct rte_eth_dev.
3368  *
3369  * @return
3370  *  - On success, zero.
3371  *  - On failure, a negative value.
3372  */
3373 static int
3374 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3375 {
3376         struct ixgbe_interrupt *intr =
3377                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3378
3379         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3380
3381         return 0;
3382 }
3383
3384 /*
3385  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3386  *
3387  * @param dev
3388  *  Pointer to struct rte_eth_dev.
3389  *
3390  * @return
3391  *  - On success, zero.
3392  *  - On failure, a negative value.
3393  */
3394 static int
3395 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3396 {
3397         uint32_t eicr;
3398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399         struct ixgbe_interrupt *intr =
3400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3401
3402         /* clear all cause mask */
3403         ixgbe_disable_intr(hw);
3404
3405         /* read-on-clear nic registers here */
3406         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3407         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3408
3409         intr->flags = 0;
3410
3411         /* set flag for async link update */
3412         if (eicr & IXGBE_EICR_LSC)
3413                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3414
3415         if (eicr & IXGBE_EICR_MAILBOX)
3416                 intr->flags |= IXGBE_FLAG_MAILBOX;
3417
3418         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3419             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3420             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3421                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3422
3423         return 0;
3424 }
3425
3426 /**
3427  * It gets and then prints the link status.
3428  *
3429  * @param dev
3430  *  Pointer to struct rte_eth_dev.
3431  *
3432  * @return
3433  *  - On success, zero.
3434  *  - On failure, a negative value.
3435  */
3436 static void
3437 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3438 {
3439         struct rte_eth_link link;
3440
3441         memset(&link, 0, sizeof(link));
3442         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3443         if (link.link_status) {
3444                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3445                                         (int)(dev->data->port_id),
3446                                         (unsigned)link.link_speed,
3447                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3448                                         "full-duplex" : "half-duplex");
3449         } else {
3450                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3451                                 (int)(dev->data->port_id));
3452         }
3453         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3454                                 dev->pci_dev->addr.domain,
3455                                 dev->pci_dev->addr.bus,
3456                                 dev->pci_dev->addr.devid,
3457                                 dev->pci_dev->addr.function);
3458 }
3459
3460 /*
3461  * It executes link_update after knowing an interrupt occurred.
3462  *
3463  * @param dev
3464  *  Pointer to struct rte_eth_dev.
3465  *
3466  * @return
3467  *  - On success, zero.
3468  *  - On failure, a negative value.
3469  */
3470 static int
3471 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3472 {
3473         struct ixgbe_interrupt *intr =
3474                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3475         int64_t timeout;
3476         struct rte_eth_link link;
3477         struct ixgbe_hw *hw =
3478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3479
3480         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3481
3482         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3483                 ixgbe_pf_mbx_process(dev);
3484                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3485         }
3486
3487         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3488                 ixgbe_handle_lasi(hw);
3489                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3490         }
3491
3492         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3493                 /* get the link status before link update, for predicting later */
3494                 memset(&link, 0, sizeof(link));
3495                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3496
3497                 ixgbe_dev_link_update(dev, 0);
3498
3499                 /* likely to up */
3500                 if (!link.link_status)
3501                         /* handle it 1 sec later, wait it being stable */
3502                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3503                 /* likely to down */
3504                 else
3505                         /* handle it 4 sec later, wait it being stable */
3506                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3507
3508                 ixgbe_dev_link_status_print(dev);
3509                 intr->mask_original = intr->mask;
3510                 /* only disable lsc interrupt */
3511                 intr->mask &= ~IXGBE_EIMS_LSC;
3512                 if (rte_eal_alarm_set(timeout * 1000,
3513                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3514                         PMD_DRV_LOG(ERR, "Error setting alarm");
3515                 else
3516                         intr->mask = intr->mask_original;
3517         }
3518
3519         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3520         ixgbe_enable_intr(dev);
3521         rte_intr_enable(&dev->pci_dev->intr_handle);
3522
3523         return 0;
3524 }
3525
3526 /**
3527  * Interrupt handler which shall be registered for alarm callback for delayed
3528  * handling specific interrupt to wait for the stable nic state. As the
3529  * NIC interrupt state is not stable for ixgbe after link is just down,
3530  * it needs to wait 4 seconds to get the stable status.
3531  *
3532  * @param handle
3533  *  Pointer to interrupt handle.
3534  * @param param
3535  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3536  *
3537  * @return
3538  *  void
3539  */
3540 static void
3541 ixgbe_dev_interrupt_delayed_handler(void *param)
3542 {
3543         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3544         struct ixgbe_interrupt *intr =
3545                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3546         struct ixgbe_hw *hw =
3547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         uint32_t eicr;
3549
3550         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3551         if (eicr & IXGBE_EICR_MAILBOX)
3552                 ixgbe_pf_mbx_process(dev);
3553
3554         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3555                 ixgbe_handle_lasi(hw);
3556                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3557         }
3558
3559         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3560                 ixgbe_dev_link_update(dev, 0);
3561                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3562                 ixgbe_dev_link_status_print(dev);
3563                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3564         }
3565
3566         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3567         ixgbe_enable_intr(dev);
3568         rte_intr_enable(&(dev->pci_dev->intr_handle));
3569 }
3570
3571 /**
3572  * Interrupt handler triggered by NIC  for handling
3573  * specific interrupt.
3574  *
3575  * @param handle
3576  *  Pointer to interrupt handle.
3577  * @param param
3578  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3579  *
3580  * @return
3581  *  void
3582  */
3583 static void
3584 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3585                             void *param)
3586 {
3587         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3588
3589         ixgbe_dev_interrupt_get_status(dev);
3590         ixgbe_dev_interrupt_action(dev);
3591 }
3592
3593 static int
3594 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3595 {
3596         struct ixgbe_hw *hw;
3597
3598         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3600 }
3601
3602 static int
3603 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3604 {
3605         struct ixgbe_hw *hw;
3606
3607         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3609 }
3610
3611 static int
3612 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3613 {
3614         struct ixgbe_hw *hw;
3615         uint32_t mflcn_reg;
3616         uint32_t fccfg_reg;
3617         int rx_pause;
3618         int tx_pause;
3619
3620         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621
3622         fc_conf->pause_time = hw->fc.pause_time;
3623         fc_conf->high_water = hw->fc.high_water[0];
3624         fc_conf->low_water = hw->fc.low_water[0];
3625         fc_conf->send_xon = hw->fc.send_xon;
3626         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3627
3628         /*
3629          * Return rx_pause status according to actual setting of
3630          * MFLCN register.
3631          */
3632         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3633         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3634                 rx_pause = 1;
3635         else
3636                 rx_pause = 0;
3637
3638         /*
3639          * Return tx_pause status according to actual setting of
3640          * FCCFG register.
3641          */
3642         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3643         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3644                 tx_pause = 1;
3645         else
3646                 tx_pause = 0;
3647
3648         if (rx_pause && tx_pause)
3649                 fc_conf->mode = RTE_FC_FULL;
3650         else if (rx_pause)
3651                 fc_conf->mode = RTE_FC_RX_PAUSE;
3652         else if (tx_pause)
3653                 fc_conf->mode = RTE_FC_TX_PAUSE;
3654         else
3655                 fc_conf->mode = RTE_FC_NONE;
3656
3657         return 0;
3658 }
3659
3660 static int
3661 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3662 {
3663         struct ixgbe_hw *hw;
3664         int err;
3665         uint32_t rx_buf_size;
3666         uint32_t max_high_water;
3667         uint32_t mflcn;
3668         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3669                 ixgbe_fc_none,
3670                 ixgbe_fc_rx_pause,
3671                 ixgbe_fc_tx_pause,
3672                 ixgbe_fc_full
3673         };
3674
3675         PMD_INIT_FUNC_TRACE();
3676
3677         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3679         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3680
3681         /*
3682          * At least reserve one Ethernet frame for watermark
3683          * high_water/low_water in kilo bytes for ixgbe
3684          */
3685         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3686         if ((fc_conf->high_water > max_high_water) ||
3687                 (fc_conf->high_water < fc_conf->low_water)) {
3688                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3689                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3690                 return -EINVAL;
3691         }
3692
3693         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3694         hw->fc.pause_time     = fc_conf->pause_time;
3695         hw->fc.high_water[0]  = fc_conf->high_water;
3696         hw->fc.low_water[0]   = fc_conf->low_water;
3697         hw->fc.send_xon       = fc_conf->send_xon;
3698         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3699
3700         err = ixgbe_fc_enable(hw);
3701
3702         /* Not negotiated is not an error case */
3703         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3704
3705                 /* check if we want to forward MAC frames - driver doesn't have native
3706                  * capability to do that, so we'll write the registers ourselves */
3707
3708                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3709
3710                 /* set or clear MFLCN.PMCF bit depending on configuration */
3711                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3712                         mflcn |= IXGBE_MFLCN_PMCF;
3713                 else
3714                         mflcn &= ~IXGBE_MFLCN_PMCF;
3715
3716                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3717                 IXGBE_WRITE_FLUSH(hw);
3718
3719                 return 0;
3720         }
3721
3722         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3723         return -EIO;
3724 }
3725
3726 /**
3727  *  ixgbe_pfc_enable_generic - Enable flow control
3728  *  @hw: pointer to hardware structure
3729  *  @tc_num: traffic class number
3730  *  Enable flow control according to the current settings.
3731  */
3732 static int
3733 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3734 {
3735         int ret_val = 0;
3736         uint32_t mflcn_reg, fccfg_reg;
3737         uint32_t reg;
3738         uint32_t fcrtl, fcrth;
3739         uint8_t i;
3740         uint8_t nb_rx_en;
3741
3742         /* Validate the water mark configuration */
3743         if (!hw->fc.pause_time) {
3744                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3745                 goto out;
3746         }
3747
3748         /* Low water mark of zero causes XOFF floods */
3749         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3750                  /* High/Low water can not be 0 */
3751                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3752                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3753                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3754                         goto out;
3755                 }
3756
3757                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3758                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3759                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3760                         goto out;
3761                 }
3762         }
3763         /* Negotiate the fc mode to use */
3764         ixgbe_fc_autoneg(hw);
3765
3766         /* Disable any previous flow control settings */
3767         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3768         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3769
3770         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3771         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3772
3773         switch (hw->fc.current_mode) {
3774         case ixgbe_fc_none:
3775                 /*
3776                  * If the count of enabled RX Priority Flow control >1,
3777                  * and the TX pause can not be disabled
3778                  */
3779                 nb_rx_en = 0;
3780                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3781                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3782                         if (reg & IXGBE_FCRTH_FCEN)
3783                                 nb_rx_en++;
3784                 }
3785                 if (nb_rx_en > 1)
3786                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3787                 break;
3788         case ixgbe_fc_rx_pause:
3789                 /*
3790                  * Rx Flow control is enabled and Tx Flow control is
3791                  * disabled by software override. Since there really
3792                  * isn't a way to advertise that we are capable of RX
3793                  * Pause ONLY, we will advertise that we support both
3794                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3795                  * disable the adapter's ability to send PAUSE frames.
3796                  */
3797                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3798                 /*
3799                  * If the count of enabled RX Priority Flow control >1,
3800                  * and the TX pause can not be disabled
3801                  */
3802                 nb_rx_en = 0;
3803                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3804                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3805                         if (reg & IXGBE_FCRTH_FCEN)
3806                                 nb_rx_en++;
3807                 }
3808                 if (nb_rx_en > 1)
3809                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3810                 break;
3811         case ixgbe_fc_tx_pause:
3812                 /*
3813                  * Tx Flow control is enabled, and Rx Flow control is
3814                  * disabled by software override.
3815                  */
3816                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3817                 break;
3818         case ixgbe_fc_full:
3819                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3820                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3821                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3822                 break;
3823         default:
3824                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3825                 ret_val = IXGBE_ERR_CONFIG;
3826                 goto out;
3827         }
3828
3829         /* Set 802.3x based flow control settings. */
3830         mflcn_reg |= IXGBE_MFLCN_DPF;
3831         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3832         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3833
3834         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3835         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3836                 hw->fc.high_water[tc_num]) {
3837                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3838                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3839                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3840         } else {
3841                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3842                 /*
3843                  * In order to prevent Tx hangs when the internal Tx
3844                  * switch is enabled we must set the high water mark
3845                  * to the maximum FCRTH value.  This allows the Tx
3846                  * switch to function even under heavy Rx workloads.
3847                  */
3848                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3849         }
3850         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3851
3852         /* Configure pause time (2 TCs per register) */
3853         reg = hw->fc.pause_time * 0x00010001;
3854         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3855                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3856
3857         /* Configure flow control refresh threshold value */
3858         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3859
3860 out:
3861         return ret_val;
3862 }
3863
3864 static int
3865 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3866 {
3867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3869
3870         if (hw->mac.type != ixgbe_mac_82598EB) {
3871                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3872         }
3873         return ret_val;
3874 }
3875
3876 static int
3877 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3878 {
3879         int err;
3880         uint32_t rx_buf_size;
3881         uint32_t max_high_water;
3882         uint8_t tc_num;
3883         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3884         struct ixgbe_hw *hw =
3885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886         struct ixgbe_dcb_config *dcb_config =
3887                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3888
3889         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3890                 ixgbe_fc_none,
3891                 ixgbe_fc_rx_pause,
3892                 ixgbe_fc_tx_pause,
3893                 ixgbe_fc_full
3894         };
3895
3896         PMD_INIT_FUNC_TRACE();
3897
3898         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3899         tc_num = map[pfc_conf->priority];
3900         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3901         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3902         /*
3903          * At least reserve one Ethernet frame for watermark
3904          * high_water/low_water in kilo bytes for ixgbe
3905          */
3906         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3907         if ((pfc_conf->fc.high_water > max_high_water) ||
3908             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3909                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3910                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3911                 return -EINVAL;
3912         }
3913
3914         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3915         hw->fc.pause_time = pfc_conf->fc.pause_time;
3916         hw->fc.send_xon = pfc_conf->fc.send_xon;
3917         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3918         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3919
3920         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3921
3922         /* Not negotiated is not an error case */
3923         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3924                 return 0;
3925
3926         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3927         return -EIO;
3928 }
3929
3930 static int
3931 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3932                           struct rte_eth_rss_reta_entry64 *reta_conf,
3933                           uint16_t reta_size)
3934 {
3935         uint16_t i, sp_reta_size;
3936         uint8_t j, mask;
3937         uint32_t reta, r;
3938         uint16_t idx, shift;
3939         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940         uint32_t reta_reg;
3941
3942         PMD_INIT_FUNC_TRACE();
3943
3944         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3945                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3946                         "NIC.");
3947                 return -ENOTSUP;
3948         }
3949
3950         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3951         if (reta_size != sp_reta_size) {
3952                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3953                         "(%d) doesn't match the number hardware can supported "
3954                         "(%d)\n", reta_size, sp_reta_size);
3955                 return -EINVAL;
3956         }
3957
3958         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3959                 idx = i / RTE_RETA_GROUP_SIZE;
3960                 shift = i % RTE_RETA_GROUP_SIZE;
3961                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3962                                                 IXGBE_4_BIT_MASK);
3963                 if (!mask)
3964                         continue;
3965                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3966                 if (mask == IXGBE_4_BIT_MASK)
3967                         r = 0;
3968                 else
3969                         r = IXGBE_READ_REG(hw, reta_reg);
3970                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3971                         if (mask & (0x1 << j))
3972                                 reta |= reta_conf[idx].reta[shift + j] <<
3973                                                         (CHAR_BIT * j);
3974                         else
3975                                 reta |= r & (IXGBE_8_BIT_MASK <<
3976                                                 (CHAR_BIT * j));
3977                 }
3978                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3979         }
3980
3981         return 0;
3982 }
3983
3984 static int
3985 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3986                          struct rte_eth_rss_reta_entry64 *reta_conf,
3987                          uint16_t reta_size)
3988 {
3989         uint16_t i, sp_reta_size;
3990         uint8_t j, mask;
3991         uint32_t reta;
3992         uint16_t idx, shift;
3993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994         uint32_t reta_reg;
3995
3996         PMD_INIT_FUNC_TRACE();
3997         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3998         if (reta_size != sp_reta_size) {
3999                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4000                         "(%d) doesn't match the number hardware can supported "
4001                         "(%d)\n", reta_size, sp_reta_size);
4002                 return -EINVAL;
4003         }
4004
4005         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4006                 idx = i / RTE_RETA_GROUP_SIZE;
4007                 shift = i % RTE_RETA_GROUP_SIZE;
4008                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4009                                                 IXGBE_4_BIT_MASK);
4010                 if (!mask)
4011                         continue;
4012
4013                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4014                 reta = IXGBE_READ_REG(hw, reta_reg);
4015                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4016                         if (mask & (0x1 << j))
4017                                 reta_conf[idx].reta[shift + j] =
4018                                         ((reta >> (CHAR_BIT * j)) &
4019                                                 IXGBE_8_BIT_MASK);
4020                 }
4021         }
4022
4023         return 0;
4024 }
4025
4026 static void
4027 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4028                                 uint32_t index, uint32_t pool)
4029 {
4030         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031         uint32_t enable_addr = 1;
4032
4033         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4034 }
4035
4036 static void
4037 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4038 {
4039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040
4041         ixgbe_clear_rar(hw, index);
4042 }
4043
4044 static void
4045 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4046 {
4047         ixgbe_remove_rar(dev, 0);
4048
4049         ixgbe_add_rar(dev, addr, 0, 0);
4050 }
4051
4052 int
4053 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4054                 struct ether_addr *mac_addr)
4055 {
4056         struct ixgbe_hw *hw;
4057         struct ixgbe_vf_info *vfinfo;
4058         int rar_entry;
4059         uint8_t *new_mac = (uint8_t *)(mac_addr);
4060         struct rte_eth_dev *dev;
4061         struct rte_eth_dev_info dev_info;
4062
4063         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4064
4065         dev = &rte_eth_devices[port];
4066         rte_eth_dev_info_get(port, &dev_info);
4067
4068         if (vf >= dev_info.max_vfs)
4069                 return -EINVAL;
4070
4071         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4073         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4074
4075         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4076                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4077                                 ETHER_ADDR_LEN);
4078                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4079                                 IXGBE_RAH_AV);
4080         }
4081         return -EINVAL;
4082 }
4083
4084 static int
4085 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4086 {
4087         uint32_t hlreg0;
4088         uint32_t maxfrs;
4089         struct ixgbe_hw *hw;
4090         struct rte_eth_dev_info dev_info;
4091         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4092
4093         ixgbe_dev_info_get(dev, &dev_info);
4094
4095         /* check that mtu is within the allowed range */
4096         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4097                 return -EINVAL;
4098
4099         /* refuse mtu that requires the support of scattered packets when this
4100          * feature has not been enabled before.
4101          */
4102         if (!dev->data->scattered_rx &&
4103             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4104              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4105                 return -EINVAL;
4106
4107         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4109
4110         /* switch to jumbo mode if needed */
4111         if (frame_size > ETHER_MAX_LEN) {
4112                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4113                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4114         } else {
4115                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4116                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4117         }
4118         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4119
4120         /* update max frame size */
4121         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4122
4123         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4124         maxfrs &= 0x0000FFFF;
4125         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4126         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4127
4128         return 0;
4129 }
4130
4131 /*
4132  * Virtual Function operations
4133  */
4134 static void
4135 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4136 {
4137         PMD_INIT_FUNC_TRACE();
4138
4139         /* Clear interrupt mask to stop from interrupts being generated */
4140         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4141
4142         IXGBE_WRITE_FLUSH(hw);
4143 }
4144
4145 static void
4146 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4147 {
4148         PMD_INIT_FUNC_TRACE();
4149
4150         /* VF enable interrupt autoclean */
4151         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4152         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4153         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4154
4155         IXGBE_WRITE_FLUSH(hw);
4156 }
4157
4158 static int
4159 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4160 {
4161         struct rte_eth_conf *conf = &dev->data->dev_conf;
4162         struct ixgbe_adapter *adapter =
4163                         (struct ixgbe_adapter *)dev->data->dev_private;
4164
4165         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4166                      dev->data->port_id);
4167
4168         /*
4169          * VF has no ability to enable/disable HW CRC
4170          * Keep the persistent behavior the same as Host PF
4171          */
4172 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4173         if (!conf->rxmode.hw_strip_crc) {
4174                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4175                 conf->rxmode.hw_strip_crc = 1;
4176         }
4177 #else
4178         if (conf->rxmode.hw_strip_crc) {
4179                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4180                 conf->rxmode.hw_strip_crc = 0;
4181         }
4182 #endif
4183
4184         /*
4185          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4186          * allocation or vector Rx preconditions we will reset it.
4187          */
4188         adapter->rx_bulk_alloc_allowed = true;
4189         adapter->rx_vec_allowed = true;
4190
4191         return 0;
4192 }
4193
4194 static int
4195 ixgbevf_dev_start(struct rte_eth_dev *dev)
4196 {
4197         struct ixgbe_hw *hw =
4198                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         uint32_t intr_vector = 0;
4200         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4201
4202         int err, mask = 0;
4203
4204         PMD_INIT_FUNC_TRACE();
4205
4206         hw->mac.ops.reset_hw(hw);
4207         hw->mac.get_link_status = true;
4208
4209         /* negotiate mailbox API version to use with the PF. */
4210         ixgbevf_negotiate_api(hw);
4211
4212         ixgbevf_dev_tx_init(dev);
4213
4214         /* This can fail when allocating mbufs for descriptor rings */
4215         err = ixgbevf_dev_rx_init(dev);
4216         if (err) {
4217                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4218                 ixgbe_dev_clear_queues(dev);
4219                 return err;
4220         }
4221
4222         /* Set vfta */
4223         ixgbevf_set_vfta_all(dev, 1);
4224
4225         /* Set HW strip */
4226         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4227                 ETH_VLAN_EXTEND_MASK;
4228         ixgbevf_vlan_offload_set(dev, mask);
4229
4230         ixgbevf_dev_rxtx_start(dev);
4231
4232         /* check and configure queue intr-vector mapping */
4233         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4234                 intr_vector = dev->data->nb_rx_queues;
4235                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4236                         return -1;
4237         }
4238
4239         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4240                 intr_handle->intr_vec =
4241                         rte_zmalloc("intr_vec",
4242                                     dev->data->nb_rx_queues * sizeof(int), 0);
4243                 if (intr_handle->intr_vec == NULL) {
4244                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4245                                      " intr_vec\n", dev->data->nb_rx_queues);
4246                         return -ENOMEM;
4247                 }
4248         }
4249         ixgbevf_configure_msix(dev);
4250
4251         rte_intr_enable(intr_handle);
4252
4253         /* Re-enable interrupt for VF */
4254         ixgbevf_intr_enable(hw);
4255
4256         return 0;
4257 }
4258
4259 static void
4260 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4261 {
4262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4263         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4264
4265         PMD_INIT_FUNC_TRACE();
4266
4267         ixgbevf_intr_disable(hw);
4268
4269         hw->adapter_stopped = 1;
4270         ixgbe_stop_adapter(hw);
4271
4272         /*
4273           * Clear what we set, but we still keep shadow_vfta to
4274           * restore after device starts
4275           */
4276         ixgbevf_set_vfta_all(dev, 0);
4277
4278         /* Clear stored conf */
4279         dev->data->scattered_rx = 0;
4280
4281         ixgbe_dev_clear_queues(dev);
4282
4283         /* Clean datapath event and queue/vec mapping */
4284         rte_intr_efd_disable(intr_handle);
4285         if (intr_handle->intr_vec != NULL) {
4286                 rte_free(intr_handle->intr_vec);
4287                 intr_handle->intr_vec = NULL;
4288         }
4289 }
4290
4291 static void
4292 ixgbevf_dev_close(struct rte_eth_dev *dev)
4293 {
4294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295
4296         PMD_INIT_FUNC_TRACE();
4297
4298         ixgbe_reset_hw(hw);
4299
4300         ixgbevf_dev_stop(dev);
4301
4302         ixgbe_dev_free_queues(dev);
4303
4304         /**
4305          * Remove the VF MAC address ro ensure
4306          * that the VF traffic goes to the PF
4307          * after stop, close and detach of the VF
4308          **/
4309         ixgbevf_remove_mac_addr(dev, 0);
4310 }
4311
4312 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4313 {
4314         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4315         struct ixgbe_vfta *shadow_vfta =
4316                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4317         int i = 0, j = 0, vfta = 0, mask = 1;
4318
4319         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4320                 vfta = shadow_vfta->vfta[i];
4321                 if (vfta) {
4322                         mask = 1;
4323                         for (j = 0; j < 32; j++) {
4324                                 if (vfta & mask)
4325                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4326                                                        on, false);
4327                                 mask <<= 1;
4328                         }
4329                 }
4330         }
4331
4332 }
4333
4334 static int
4335 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4336 {
4337         struct ixgbe_hw *hw =
4338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4339         struct ixgbe_vfta *shadow_vfta =
4340                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4341         uint32_t vid_idx = 0;
4342         uint32_t vid_bit = 0;
4343         int ret = 0;
4344
4345         PMD_INIT_FUNC_TRACE();
4346
4347         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4348         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4349         if (ret) {
4350                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4351                 return ret;
4352         }
4353         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4354         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4355
4356         /* Save what we set and retore it after device reset */
4357         if (on)
4358                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4359         else
4360                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4361
4362         return 0;
4363 }
4364
4365 static void
4366 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4367 {
4368         struct ixgbe_hw *hw =
4369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         uint32_t ctrl;
4371
4372         PMD_INIT_FUNC_TRACE();
4373
4374         if (queue >= hw->mac.max_rx_queues)
4375                 return;
4376
4377         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4378         if (on)
4379                 ctrl |= IXGBE_RXDCTL_VME;
4380         else
4381                 ctrl &= ~IXGBE_RXDCTL_VME;
4382         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4383
4384         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4385 }
4386
4387 static void
4388 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4389 {
4390         struct ixgbe_hw *hw =
4391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         uint16_t i;
4393         int on = 0;
4394
4395         /* VF function only support hw strip feature, others are not support */
4396         if (mask & ETH_VLAN_STRIP_MASK) {
4397                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4398
4399                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4400                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4401         }
4402 }
4403
4404 static int
4405 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4406 {
4407         uint32_t reg_val;
4408
4409         /* we only need to do this if VMDq is enabled */
4410         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4411         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4412                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4413                 return -1;
4414         }
4415
4416         return 0;
4417 }
4418
4419 static uint32_t
4420 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4421 {
4422         uint32_t vector = 0;
4423
4424         switch (hw->mac.mc_filter_type) {
4425         case 0:   /* use bits [47:36] of the address */
4426                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4427                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4428                 break;
4429         case 1:   /* use bits [46:35] of the address */
4430                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4431                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4432                 break;
4433         case 2:   /* use bits [45:34] of the address */
4434                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4435                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4436                 break;
4437         case 3:   /* use bits [43:32] of the address */
4438                 vector = ((uc_addr->addr_bytes[4]) |
4439                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4440                 break;
4441         default:  /* Invalid mc_filter_type */
4442                 break;
4443         }
4444
4445         /* vector can only be 12-bits or boundary will be exceeded */
4446         vector &= 0xFFF;
4447         return vector;
4448 }
4449
4450 static int
4451 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4452                         uint8_t on)
4453 {
4454         uint32_t vector;
4455         uint32_t uta_idx;
4456         uint32_t reg_val;
4457         uint32_t uta_shift;
4458         uint32_t rc;
4459         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4460         const uint32_t ixgbe_uta_bit_shift = 5;
4461         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4462         const uint32_t bit1 = 0x1;
4463
4464         struct ixgbe_hw *hw =
4465                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466         struct ixgbe_uta_info *uta_info =
4467                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4468
4469         /* The UTA table only exists on 82599 hardware and newer */
4470         if (hw->mac.type < ixgbe_mac_82599EB)
4471                 return -ENOTSUP;
4472
4473         vector = ixgbe_uta_vector(hw, mac_addr);
4474         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4475         uta_shift = vector & ixgbe_uta_bit_mask;
4476
4477         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4478         if (rc == on)
4479                 return 0;
4480
4481         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4482         if (on) {
4483                 uta_info->uta_in_use++;
4484                 reg_val |= (bit1 << uta_shift);
4485                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4486         } else {
4487                 uta_info->uta_in_use--;
4488                 reg_val &= ~(bit1 << uta_shift);
4489                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4490         }
4491
4492         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4493
4494         if (uta_info->uta_in_use > 0)
4495                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4496                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4497         else
4498                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4499
4500         return 0;
4501 }
4502
4503 static int
4504 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4505 {
4506         int i;
4507         struct ixgbe_hw *hw =
4508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4509         struct ixgbe_uta_info *uta_info =
4510                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4511
4512         /* The UTA table only exists on 82599 hardware and newer */
4513         if (hw->mac.type < ixgbe_mac_82599EB)
4514                 return -ENOTSUP;
4515
4516         if (on) {
4517                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4518                         uta_info->uta_shadow[i] = ~0;
4519                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4520                 }
4521         } else {
4522                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4523                         uta_info->uta_shadow[i] = 0;
4524                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4525                 }
4526         }
4527         return 0;
4528
4529 }
4530
4531 uint32_t
4532 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4533 {
4534         uint32_t new_val = orig_val;
4535
4536         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4537                 new_val |= IXGBE_VMOLR_AUPE;
4538         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4539                 new_val |= IXGBE_VMOLR_ROMPE;
4540         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4541                 new_val |= IXGBE_VMOLR_ROPE;
4542         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4543                 new_val |= IXGBE_VMOLR_BAM;
4544         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4545                 new_val |= IXGBE_VMOLR_MPE;
4546
4547         return new_val;
4548 }
4549
4550 static int
4551 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4552                                uint16_t rx_mask, uint8_t on)
4553 {
4554         int val = 0;
4555
4556         struct ixgbe_hw *hw =
4557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4558         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4559
4560         if (hw->mac.type == ixgbe_mac_82598EB) {
4561                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4562                              " on 82599 hardware and newer");
4563                 return -ENOTSUP;
4564         }
4565         if (ixgbe_vmdq_mode_check(hw) < 0)
4566                 return -ENOTSUP;
4567
4568         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4569
4570         if (on)
4571                 vmolr |= val;
4572         else
4573                 vmolr &= ~val;
4574
4575         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4576
4577         return 0;
4578 }
4579
4580 static int
4581 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4582 {
4583         uint32_t reg, addr;
4584         uint32_t val;
4585         const uint8_t bit1 = 0x1;
4586
4587         struct ixgbe_hw *hw =
4588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589
4590         if (ixgbe_vmdq_mode_check(hw) < 0)
4591                 return -ENOTSUP;
4592
4593         if (pool >= ETH_64_POOLS)
4594                 return -EINVAL;
4595
4596         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4597         if (pool >= 32) {
4598                 addr = IXGBE_VFRE(1);
4599                 val = bit1 << (pool - 32);
4600         } else {
4601                 addr = IXGBE_VFRE(0);
4602                 val = bit1 << pool;
4603         }
4604
4605         reg = IXGBE_READ_REG(hw, addr);
4606
4607         if (on)
4608                 reg |= val;
4609         else
4610                 reg &= ~val;
4611
4612         IXGBE_WRITE_REG(hw, addr, reg);
4613
4614         return 0;
4615 }
4616
4617 static int
4618 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4619 {
4620         uint32_t reg, addr;
4621         uint32_t val;
4622         const uint8_t bit1 = 0x1;
4623
4624         struct ixgbe_hw *hw =
4625                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626
4627         if (ixgbe_vmdq_mode_check(hw) < 0)
4628                 return -ENOTSUP;
4629
4630         if (pool >= ETH_64_POOLS)
4631                 return -EINVAL;
4632
4633         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4634         if (pool >= 32) {
4635                 addr = IXGBE_VFTE(1);
4636                 val = bit1 << (pool - 32);
4637         } else {
4638                 addr = IXGBE_VFTE(0);
4639                 val = bit1 << pool;
4640         }
4641
4642         reg = IXGBE_READ_REG(hw, addr);
4643
4644         if (on)
4645                 reg |= val;
4646         else
4647                 reg &= ~val;
4648
4649         IXGBE_WRITE_REG(hw, addr, reg);
4650
4651         return 0;
4652 }
4653
4654 static int
4655 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4656                         uint64_t pool_mask, uint8_t vlan_on)
4657 {
4658         int ret = 0;
4659         uint16_t pool_idx;
4660         struct ixgbe_hw *hw =
4661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4662
4663         if (ixgbe_vmdq_mode_check(hw) < 0)
4664                 return -ENOTSUP;
4665         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4666                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4667                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4668                                                    vlan_on, false);
4669                         if (ret < 0)
4670                                 return ret;
4671                 }
4672         }
4673
4674         return ret;
4675 }
4676
4677 int
4678 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4679 {
4680         struct ixgbe_hw *hw;
4681         struct ixgbe_mac_info *mac;
4682         struct rte_eth_dev *dev;
4683         struct rte_eth_dev_info dev_info;
4684
4685         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4686
4687         dev = &rte_eth_devices[port];
4688         rte_eth_dev_info_get(port, &dev_info);
4689
4690         if (vf >= dev_info.max_vfs)
4691                 return -EINVAL;
4692
4693         if (on > 1)
4694                 return -EINVAL;
4695
4696         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         mac = &hw->mac;
4698
4699         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4700
4701         return 0;
4702 }
4703
4704 int
4705 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4706 {
4707         struct ixgbe_hw *hw;
4708         struct ixgbe_mac_info *mac;
4709         struct rte_eth_dev *dev;
4710         struct rte_eth_dev_info dev_info;
4711
4712         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4713
4714         dev = &rte_eth_devices[port];
4715         rte_eth_dev_info_get(port, &dev_info);
4716
4717         if (vf >= dev_info.max_vfs)
4718                 return -EINVAL;
4719
4720         if (on > 1)
4721                 return -EINVAL;
4722
4723         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         mac = &hw->mac;
4725         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4726
4727         return 0;
4728 }
4729
4730 int
4731 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4732 {
4733         struct ixgbe_hw *hw;
4734         uint32_t ctrl;
4735         struct rte_eth_dev *dev;
4736         struct rte_eth_dev_info dev_info;
4737
4738         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4739
4740         dev = &rte_eth_devices[port];
4741         rte_eth_dev_info_get(port, &dev_info);
4742
4743         if (vf >= dev_info.max_vfs)
4744                 return -EINVAL;
4745
4746         if (vlan_id > 4095)
4747                 return -EINVAL;
4748
4749         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4751         if (vlan_id) {
4752                 ctrl = vlan_id;
4753                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4754         } else {
4755                 ctrl = 0;
4756         }
4757
4758         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4759
4760         return 0;
4761 }
4762
4763 int
4764 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4765 {
4766         struct ixgbe_hw *hw;
4767         uint32_t ctrl;
4768         struct rte_eth_dev *dev;
4769
4770         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4771
4772         dev = &rte_eth_devices[port];
4773
4774         if (on > 1)
4775                 return -EINVAL;
4776
4777         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4779         /* enable or disable VMDQ loopback */
4780         if (on)
4781                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4782         else
4783                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4784
4785         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4786
4787         return 0;
4788 }
4789
4790 int
4791 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4792 {
4793         struct ixgbe_hw *hw;
4794         uint32_t reg_value;
4795         int i;
4796         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4797         struct rte_eth_dev *dev;
4798
4799         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4800
4801         dev = &rte_eth_devices[port];
4802
4803         if (on > 1)
4804                 return -EINVAL;
4805
4806         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807         for (i = 0; i <= num_queues; i++) {
4808                 reg_value = IXGBE_QDE_WRITE |
4809                                 (i << IXGBE_QDE_IDX_SHIFT) |
4810                                 (on & IXGBE_QDE_ENABLE);
4811                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4812         }
4813
4814         return 0;
4815 }
4816
4817 int
4818 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4819 {
4820         struct ixgbe_hw *hw;
4821         uint32_t reg_value;
4822         struct rte_eth_dev *dev;
4823         struct rte_eth_dev_info dev_info;
4824
4825         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4826
4827         dev = &rte_eth_devices[port];
4828         rte_eth_dev_info_get(port, &dev_info);
4829
4830         /* only support VF's 0 to 63 */
4831         if ((vf >= dev_info.max_vfs) || (vf > 63))
4832                 return -EINVAL;
4833
4834         if (on > 1)
4835                 return -EINVAL;
4836
4837         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4839         if (on)
4840                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4841         else
4842                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4843
4844         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4845
4846         return 0;
4847 }
4848
4849 int
4850 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4851 {
4852         struct rte_eth_dev *dev;
4853         struct rte_eth_dev_info dev_info;
4854         uint16_t queues_per_pool;
4855         uint32_t q;
4856
4857         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4858
4859         dev = &rte_eth_devices[port];
4860         rte_eth_dev_info_get(port, &dev_info);
4861
4862         if (vf >= dev_info.max_vfs)
4863                 return -EINVAL;
4864
4865         if (on > 1)
4866                 return -EINVAL;
4867
4868         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4869
4870         /* The PF has 128 queue pairs and in SRIOV configuration
4871          * those queues will be assigned to VF's, so RXDCTL
4872          * registers will be dealing with queues which will be
4873          * assigned to VF's.
4874          * Let's say we have SRIOV configured with 31 VF's then the
4875          * first 124 queues 0-123 will be allocated to VF's and only
4876          * the last 4 queues 123-127 will be assigned to the PF.
4877          */
4878
4879         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4880
4881         for (q = 0; q < queues_per_pool; q++)
4882                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4883                                 q + vf * queues_per_pool, on);
4884         return 0;
4885 }
4886
4887 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4888 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4889 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4890 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4891 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4892         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4893         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4894
4895 static int
4896 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4897                         struct rte_eth_mirror_conf *mirror_conf,
4898                         uint8_t rule_id, uint8_t on)
4899 {
4900         uint32_t mr_ctl, vlvf;
4901         uint32_t mp_lsb = 0;
4902         uint32_t mv_msb = 0;
4903         uint32_t mv_lsb = 0;
4904         uint32_t mp_msb = 0;
4905         uint8_t i = 0;
4906         int reg_index = 0;
4907         uint64_t vlan_mask = 0;
4908
4909         const uint8_t pool_mask_offset = 32;
4910         const uint8_t vlan_mask_offset = 32;
4911         const uint8_t dst_pool_offset = 8;
4912         const uint8_t rule_mr_offset  = 4;
4913         const uint8_t mirror_rule_mask = 0x0F;
4914
4915         struct ixgbe_mirror_info *mr_info =
4916                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4917         struct ixgbe_hw *hw =
4918                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         uint8_t mirror_type = 0;
4920
4921         if (ixgbe_vmdq_mode_check(hw) < 0)
4922                 return -ENOTSUP;
4923
4924         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4925                 return -EINVAL;
4926
4927         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4928                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4929                         mirror_conf->rule_type);
4930                 return -EINVAL;
4931         }
4932
4933         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4934                 mirror_type |= IXGBE_MRCTL_VLME;
4935                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4936                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4937                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4938                                 /* search vlan id related pool vlan filter index */
4939                                 reg_index = ixgbe_find_vlvf_slot(hw,
4940                                                  mirror_conf->vlan.vlan_id[i],
4941                                                  false);
4942                                 if (reg_index < 0)
4943                                         return -EINVAL;
4944                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4945                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4946                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4947                                       mirror_conf->vlan.vlan_id[i]))
4948                                         vlan_mask |= (1ULL << reg_index);
4949                                 else
4950                                         return -EINVAL;
4951                         }
4952                 }
4953
4954                 if (on) {
4955                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4956                         mv_msb = vlan_mask >> vlan_mask_offset;
4957
4958                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4959                                                 mirror_conf->vlan.vlan_mask;
4960                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4961                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4962                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4963                                                 mirror_conf->vlan.vlan_id[i];
4964                         }
4965                 } else {
4966                         mv_lsb = 0;
4967                         mv_msb = 0;
4968                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4969                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4970                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4971                 }
4972         }
4973
4974         /*
4975          * if enable pool mirror, write related pool mask register,if disable
4976          * pool mirror, clear PFMRVM register
4977          */
4978         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4979                 mirror_type |= IXGBE_MRCTL_VPME;
4980                 if (on) {
4981                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4982                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4983                         mr_info->mr_conf[rule_id].pool_mask =
4984                                         mirror_conf->pool_mask;
4985
4986                 } else {
4987                         mp_lsb = 0;
4988                         mp_msb = 0;
4989                         mr_info->mr_conf[rule_id].pool_mask = 0;
4990                 }
4991         }
4992         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4993                 mirror_type |= IXGBE_MRCTL_UPME;
4994         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4995                 mirror_type |= IXGBE_MRCTL_DPME;
4996
4997         /* read  mirror control register and recalculate it */
4998         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4999
5000         if (on) {
5001                 mr_ctl |= mirror_type;
5002                 mr_ctl &= mirror_rule_mask;
5003                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5004         } else
5005                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5006
5007         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5008         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5009
5010         /* write mirrror control  register */
5011         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5012
5013         /* write pool mirrror control  register */
5014         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5015                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5016                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5017                                 mp_msb);
5018         }
5019         /* write VLAN mirrror control  register */
5020         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5021                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5022                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5023                                 mv_msb);
5024         }
5025
5026         return 0;
5027 }
5028
5029 static int
5030 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5031 {
5032         int mr_ctl = 0;
5033         uint32_t lsb_val = 0;
5034         uint32_t msb_val = 0;
5035         const uint8_t rule_mr_offset = 4;
5036
5037         struct ixgbe_hw *hw =
5038                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         struct ixgbe_mirror_info *mr_info =
5040                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5041
5042         if (ixgbe_vmdq_mode_check(hw) < 0)
5043                 return -ENOTSUP;
5044
5045         memset(&mr_info->mr_conf[rule_id], 0,
5046                 sizeof(struct rte_eth_mirror_conf));
5047
5048         /* clear PFVMCTL register */
5049         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5050
5051         /* clear pool mask register */
5052         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5053         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5054
5055         /* clear vlan mask register */
5056         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5057         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5058
5059         return 0;
5060 }
5061
5062 static int
5063 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5064 {
5065         uint32_t mask;
5066         struct ixgbe_hw *hw =
5067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068
5069         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5070         mask |= (1 << IXGBE_MISC_VEC_ID);
5071         RTE_SET_USED(queue_id);
5072         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5073
5074         rte_intr_enable(&dev->pci_dev->intr_handle);
5075
5076         return 0;
5077 }
5078
5079 static int
5080 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5081 {
5082         uint32_t mask;
5083         struct ixgbe_hw *hw =
5084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085
5086         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5087         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5088         RTE_SET_USED(queue_id);
5089         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5090
5091         return 0;
5092 }
5093
5094 static int
5095 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5096 {
5097         uint32_t mask;
5098         struct ixgbe_hw *hw =
5099                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100         struct ixgbe_interrupt *intr =
5101                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5102
5103         if (queue_id < 16) {
5104                 ixgbe_disable_intr(hw);
5105                 intr->mask |= (1 << queue_id);
5106                 ixgbe_enable_intr(dev);
5107         } else if (queue_id < 32) {
5108                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5109                 mask &= (1 << queue_id);
5110                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5111         } else if (queue_id < 64) {
5112                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5113                 mask &= (1 << (queue_id - 32));
5114                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5115         }
5116         rte_intr_enable(&dev->pci_dev->intr_handle);
5117
5118         return 0;
5119 }
5120
5121 static int
5122 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5123 {
5124         uint32_t mask;
5125         struct ixgbe_hw *hw =
5126                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127         struct ixgbe_interrupt *intr =
5128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5129
5130         if (queue_id < 16) {
5131                 ixgbe_disable_intr(hw);
5132                 intr->mask &= ~(1 << queue_id);
5133                 ixgbe_enable_intr(dev);
5134         } else if (queue_id < 32) {
5135                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5136                 mask &= ~(1 << queue_id);
5137                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5138         } else if (queue_id < 64) {
5139                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5140                 mask &= ~(1 << (queue_id - 32));
5141                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5142         }
5143
5144         return 0;
5145 }
5146
5147 static void
5148 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5149                      uint8_t queue, uint8_t msix_vector)
5150 {
5151         uint32_t tmp, idx;
5152
5153         if (direction == -1) {
5154                 /* other causes */
5155                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5156                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5157                 tmp &= ~0xFF;
5158                 tmp |= msix_vector;
5159                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5160         } else {
5161                 /* rx or tx cause */
5162                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5163                 idx = ((16 * (queue & 1)) + (8 * direction));
5164                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5165                 tmp &= ~(0xFF << idx);
5166                 tmp |= (msix_vector << idx);
5167                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5168         }
5169 }
5170
5171 /**
5172  * set the IVAR registers, mapping interrupt causes to vectors
5173  * @param hw
5174  *  pointer to ixgbe_hw struct
5175  * @direction
5176  *  0 for Rx, 1 for Tx, -1 for other causes
5177  * @queue
5178  *  queue to map the corresponding interrupt to
5179  * @msix_vector
5180  *  the vector to map to the corresponding queue
5181  */
5182 static void
5183 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5184                    uint8_t queue, uint8_t msix_vector)
5185 {
5186         uint32_t tmp, idx;
5187
5188         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5189         if (hw->mac.type == ixgbe_mac_82598EB) {
5190                 if (direction == -1)
5191                         direction = 0;
5192                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5193                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5194                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5195                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5196                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5197         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5198                         (hw->mac.type == ixgbe_mac_X540)) {
5199                 if (direction == -1) {
5200                         /* other causes */
5201                         idx = ((queue & 1) * 8);
5202                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5203                         tmp &= ~(0xFF << idx);
5204                         tmp |= (msix_vector << idx);
5205                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5206                 } else {
5207                         /* rx or tx causes */
5208                         idx = ((16 * (queue & 1)) + (8 * direction));
5209                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5210                         tmp &= ~(0xFF << idx);
5211                         tmp |= (msix_vector << idx);
5212                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5213                 }
5214         }
5215 }
5216
5217 static void
5218 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5219 {
5220         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5221         struct ixgbe_hw *hw =
5222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223         uint32_t q_idx;
5224         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5225
5226         /* Configure VF other cause ivar */
5227         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5228
5229         /* won't configure msix register if no mapping is done
5230          * between intr vector and event fd.
5231          */
5232         if (!rte_intr_dp_is_en(intr_handle))
5233                 return;
5234
5235         /* Configure all RX queues of VF */
5236         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5237                 /* Force all queue use vector 0,
5238                  * as IXGBE_VF_MAXMSIVECOTR = 1
5239                  */
5240                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5241                 intr_handle->intr_vec[q_idx] = vector_idx;
5242         }
5243 }
5244
5245 /**
5246  * Sets up the hardware to properly generate MSI-X interrupts
5247  * @hw
5248  *  board private structure
5249  */
5250 static void
5251 ixgbe_configure_msix(struct rte_eth_dev *dev)
5252 {
5253         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5254         struct ixgbe_hw *hw =
5255                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5257         uint32_t vec = IXGBE_MISC_VEC_ID;
5258         uint32_t mask;
5259         uint32_t gpie;
5260
5261         /* won't configure msix register if no mapping is done
5262          * between intr vector and event fd
5263          */
5264         if (!rte_intr_dp_is_en(intr_handle))
5265                 return;
5266
5267         if (rte_intr_allow_others(intr_handle))
5268                 vec = base = IXGBE_RX_VEC_START;
5269
5270         /* setup GPIE for MSI-x mode */
5271         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5272         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5273                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5274         /* auto clearing and auto setting corresponding bits in EIMS
5275          * when MSI-X interrupt is triggered
5276          */
5277         if (hw->mac.type == ixgbe_mac_82598EB) {
5278                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5279         } else {
5280                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5281                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5282         }
5283         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5284
5285         /* Populate the IVAR table and set the ITR values to the
5286          * corresponding register.
5287          */
5288         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5289              queue_id++) {
5290                 /* by default, 1:1 mapping */
5291                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5292                 intr_handle->intr_vec[queue_id] = vec;
5293                 if (vec < base + intr_handle->nb_efd - 1)
5294                         vec++;
5295         }
5296
5297         switch (hw->mac.type) {
5298         case ixgbe_mac_82598EB:
5299                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5300                                    IXGBE_MISC_VEC_ID);
5301                 break;
5302         case ixgbe_mac_82599EB:
5303         case ixgbe_mac_X540:
5304                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5305                 break;
5306         default:
5307                 break;
5308         }
5309         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5310                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5311
5312         /* set up to autoclear timer, and the vectors */
5313         mask = IXGBE_EIMS_ENABLE_MASK;
5314         mask &= ~(IXGBE_EIMS_OTHER |
5315                   IXGBE_EIMS_MAILBOX |
5316                   IXGBE_EIMS_LSC);
5317
5318         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5319 }
5320
5321 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5322         uint16_t queue_idx, uint16_t tx_rate)
5323 {
5324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325         uint32_t rf_dec, rf_int;
5326         uint32_t bcnrc_val;
5327         uint16_t link_speed = dev->data->dev_link.link_speed;
5328
5329         if (queue_idx >= hw->mac.max_tx_queues)
5330                 return -EINVAL;
5331
5332         if (tx_rate != 0) {
5333                 /* Calculate the rate factor values to set */
5334                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5335                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5336                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5337
5338                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5339                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5340                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5341                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5342         } else {
5343                 bcnrc_val = 0;
5344         }
5345
5346         /*
5347          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5348          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5349          * set as 0x4.
5350          */
5351         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5352                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5353                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5354                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5355                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5356         else
5357                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5358                         IXGBE_MMW_SIZE_DEFAULT);
5359
5360         /* Set RTTBCNRC of queue X */
5361         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5362         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5363         IXGBE_WRITE_FLUSH(hw);
5364
5365         return 0;
5366 }
5367
5368 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5369         uint16_t tx_rate, uint64_t q_msk)
5370 {
5371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372         struct ixgbe_vf_info *vfinfo =
5373                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5374         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5375         uint32_t queue_stride =
5376                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5377         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5378         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5379         uint16_t total_rate = 0;
5380
5381         if (queue_end >= hw->mac.max_tx_queues)
5382                 return -EINVAL;
5383
5384         if (vfinfo != NULL) {
5385                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5386                         if (vf_idx == vf)
5387                                 continue;
5388                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5389                                 idx++)
5390                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5391                 }
5392         } else
5393                 return -EINVAL;
5394
5395         /* Store tx_rate for this vf. */
5396         for (idx = 0; idx < nb_q_per_pool; idx++) {
5397                 if (((uint64_t)0x1 << idx) & q_msk) {
5398                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5399                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5400                         total_rate += tx_rate;
5401                 }
5402         }
5403
5404         if (total_rate > dev->data->dev_link.link_speed) {
5405                 /*
5406                  * Reset stored TX rate of the VF if it causes exceed
5407                  * link speed.
5408                  */
5409                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5410                 return -EINVAL;
5411         }
5412
5413         /* Set RTTBCNRC of each queue/pool for vf X  */
5414         for (; queue_idx <= queue_end; queue_idx++) {
5415                 if (0x1 & q_msk)
5416                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5417                 q_msk = q_msk >> 1;
5418         }
5419
5420         return 0;
5421 }
5422
5423 static void
5424 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5425                      __attribute__((unused)) uint32_t index,
5426                      __attribute__((unused)) uint32_t pool)
5427 {
5428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5429         int diag;
5430
5431         /*
5432          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5433          * operation. Trap this case to avoid exhausting the [very limited]
5434          * set of PF resources used to store VF MAC addresses.
5435          */
5436         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5437                 return;
5438         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5439         if (diag == 0)
5440                 return;
5441         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5442 }
5443
5444 static void
5445 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5446 {
5447         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5449         struct ether_addr *mac_addr;
5450         uint32_t i;
5451         int diag;
5452
5453         /*
5454          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5455          * not support the deletion of a given MAC address.
5456          * Instead, it imposes to delete all MAC addresses, then to add again
5457          * all MAC addresses with the exception of the one to be deleted.
5458          */
5459         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5460
5461         /*
5462          * Add again all MAC addresses, with the exception of the deleted one
5463          * and of the permanent MAC address.
5464          */
5465         for (i = 0, mac_addr = dev->data->mac_addrs;
5466              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5467                 /* Skip the deleted MAC address */
5468                 if (i == index)
5469                         continue;
5470                 /* Skip NULL MAC addresses */
5471                 if (is_zero_ether_addr(mac_addr))
5472                         continue;
5473                 /* Skip the permanent MAC address */
5474                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5475                         continue;
5476                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5477                 if (diag != 0)
5478                         PMD_DRV_LOG(ERR,
5479                                     "Adding again MAC address "
5480                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5481                                     "diag=%d",
5482                                     mac_addr->addr_bytes[0],
5483                                     mac_addr->addr_bytes[1],
5484                                     mac_addr->addr_bytes[2],
5485                                     mac_addr->addr_bytes[3],
5486                                     mac_addr->addr_bytes[4],
5487                                     mac_addr->addr_bytes[5],
5488                                     diag);
5489         }
5490 }
5491
5492 static void
5493 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5494 {
5495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5496
5497         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5498 }
5499
5500 #define MAC_TYPE_FILTER_SUP(type)    do {\
5501         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5502                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5503                 (type) != ixgbe_mac_X550EM_a)\
5504                 return -ENOTSUP;\
5505 } while (0)
5506
5507 static int
5508 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5509                         struct rte_eth_syn_filter *filter,
5510                         bool add)
5511 {
5512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         uint32_t synqf;
5514
5515         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5516                 return -EINVAL;
5517
5518         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5519
5520         if (add) {
5521                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5522                         return -EINVAL;
5523                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5524                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5525
5526                 if (filter->hig_pri)
5527                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5528                 else
5529                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5530         } else {
5531                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5532                         return -ENOENT;
5533                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5534         }
5535         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5536         IXGBE_WRITE_FLUSH(hw);
5537         return 0;
5538 }
5539
5540 static int
5541 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5542                         struct rte_eth_syn_filter *filter)
5543 {
5544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5546
5547         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5548                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5549                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5550                 return 0;
5551         }
5552         return -ENOENT;
5553 }
5554
5555 static int
5556 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5557                         enum rte_filter_op filter_op,
5558                         void *arg)
5559 {
5560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5561         int ret;
5562
5563         MAC_TYPE_FILTER_SUP(hw->mac.type);
5564
5565         if (filter_op == RTE_ETH_FILTER_NOP)
5566                 return 0;
5567
5568         if (arg == NULL) {
5569                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5570                             filter_op);
5571                 return -EINVAL;
5572         }
5573
5574         switch (filter_op) {
5575         case RTE_ETH_FILTER_ADD:
5576                 ret = ixgbe_syn_filter_set(dev,
5577                                 (struct rte_eth_syn_filter *)arg,
5578                                 TRUE);
5579                 break;
5580         case RTE_ETH_FILTER_DELETE:
5581                 ret = ixgbe_syn_filter_set(dev,
5582                                 (struct rte_eth_syn_filter *)arg,
5583                                 FALSE);
5584                 break;
5585         case RTE_ETH_FILTER_GET:
5586                 ret = ixgbe_syn_filter_get(dev,
5587                                 (struct rte_eth_syn_filter *)arg);
5588                 break;
5589         default:
5590                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5591                 ret = -EINVAL;
5592                 break;
5593         }
5594
5595         return ret;
5596 }
5597
5598
5599 static inline enum ixgbe_5tuple_protocol
5600 convert_protocol_type(uint8_t protocol_value)
5601 {
5602         if (protocol_value == IPPROTO_TCP)
5603                 return IXGBE_FILTER_PROTOCOL_TCP;
5604         else if (protocol_value == IPPROTO_UDP)
5605                 return IXGBE_FILTER_PROTOCOL_UDP;
5606         else if (protocol_value == IPPROTO_SCTP)
5607                 return IXGBE_FILTER_PROTOCOL_SCTP;
5608         else
5609                 return IXGBE_FILTER_PROTOCOL_NONE;
5610 }
5611
5612 /*
5613  * add a 5tuple filter
5614  *
5615  * @param
5616  * dev: Pointer to struct rte_eth_dev.
5617  * index: the index the filter allocates.
5618  * filter: ponter to the filter that will be added.
5619  * rx_queue: the queue id the filter assigned to.
5620  *
5621  * @return
5622  *    - On success, zero.
5623  *    - On failure, a negative value.
5624  */
5625 static int
5626 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5627                         struct ixgbe_5tuple_filter *filter)
5628 {
5629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5630         struct ixgbe_filter_info *filter_info =
5631                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5632         int i, idx, shift;
5633         uint32_t ftqf, sdpqf;
5634         uint32_t l34timir = 0;
5635         uint8_t mask = 0xff;
5636
5637         /*
5638          * look for an unused 5tuple filter index,
5639          * and insert the filter to list.
5640          */
5641         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5642                 idx = i / (sizeof(uint32_t) * NBBY);
5643                 shift = i % (sizeof(uint32_t) * NBBY);
5644                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5645                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5646                         filter->index = i;
5647                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5648                                           filter,
5649                                           entries);
5650                         break;
5651                 }
5652         }
5653         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5654                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5655                 return -ENOSYS;
5656         }
5657
5658         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5659                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5660         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5661
5662         ftqf = (uint32_t)(filter->filter_info.proto &
5663                 IXGBE_FTQF_PROTOCOL_MASK);
5664         ftqf |= (uint32_t)((filter->filter_info.priority &
5665                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5666         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5667                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5668         if (filter->filter_info.dst_ip_mask == 0)
5669                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5670         if (filter->filter_info.src_port_mask == 0)
5671                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5672         if (filter->filter_info.dst_port_mask == 0)
5673                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5674         if (filter->filter_info.proto_mask == 0)
5675                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5676         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5677         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5678         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5679
5680         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5681         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5682         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5683         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5684
5685         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5686         l34timir |= (uint32_t)(filter->queue <<
5687                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5688         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5689         return 0;
5690 }
5691
5692 /*
5693  * remove a 5tuple filter
5694  *
5695  * @param
5696  * dev: Pointer to struct rte_eth_dev.
5697  * filter: the pointer of the filter will be removed.
5698  */
5699 static void
5700 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5701                         struct ixgbe_5tuple_filter *filter)
5702 {
5703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704         struct ixgbe_filter_info *filter_info =
5705                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5706         uint16_t index = filter->index;
5707
5708         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5709                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5710         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5711         rte_free(filter);
5712
5713         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5714         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5715         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5716         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5717         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5718 }
5719
5720 static int
5721 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5722 {
5723         struct ixgbe_hw *hw;
5724         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5725
5726         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727
5728         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5729                 return -EINVAL;
5730
5731         /* refuse mtu that requires the support of scattered packets when this
5732          * feature has not been enabled before.
5733          */
5734         if (!dev->data->scattered_rx &&
5735             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5736              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5737                 return -EINVAL;
5738
5739         /*
5740          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5741          * request of the version 2.0 of the mailbox API.
5742          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5743          * of the mailbox API.
5744          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5745          * prior to 3.11.33 which contains the following change:
5746          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5747          */
5748         ixgbevf_rlpml_set_vf(hw, max_frame);
5749
5750         /* update max frame size */
5751         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5752         return 0;
5753 }
5754
5755 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5756         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5757                 return -ENOTSUP;\
5758 } while (0)
5759
5760 static inline struct ixgbe_5tuple_filter *
5761 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5762                         struct ixgbe_5tuple_filter_info *key)
5763 {
5764         struct ixgbe_5tuple_filter *it;
5765
5766         TAILQ_FOREACH(it, filter_list, entries) {
5767                 if (memcmp(key, &it->filter_info,
5768                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5769                         return it;
5770                 }
5771         }
5772         return NULL;
5773 }
5774
5775 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5776 static inline int
5777 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5778                         struct ixgbe_5tuple_filter_info *filter_info)
5779 {
5780         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5781                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5782                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5783                 return -EINVAL;
5784
5785         switch (filter->dst_ip_mask) {
5786         case UINT32_MAX:
5787                 filter_info->dst_ip_mask = 0;
5788                 filter_info->dst_ip = filter->dst_ip;
5789                 break;
5790         case 0:
5791                 filter_info->dst_ip_mask = 1;
5792                 break;
5793         default:
5794                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5795                 return -EINVAL;
5796         }
5797
5798         switch (filter->src_ip_mask) {
5799         case UINT32_MAX:
5800                 filter_info->src_ip_mask = 0;
5801                 filter_info->src_ip = filter->src_ip;
5802                 break;
5803         case 0:
5804                 filter_info->src_ip_mask = 1;
5805                 break;
5806         default:
5807                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5808                 return -EINVAL;
5809         }
5810
5811         switch (filter->dst_port_mask) {
5812         case UINT16_MAX:
5813                 filter_info->dst_port_mask = 0;
5814                 filter_info->dst_port = filter->dst_port;
5815                 break;
5816         case 0:
5817                 filter_info->dst_port_mask = 1;
5818                 break;
5819         default:
5820                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5821                 return -EINVAL;
5822         }
5823
5824         switch (filter->src_port_mask) {
5825         case UINT16_MAX:
5826                 filter_info->src_port_mask = 0;
5827                 filter_info->src_port = filter->src_port;
5828                 break;
5829         case 0:
5830                 filter_info->src_port_mask = 1;
5831                 break;
5832         default:
5833                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5834                 return -EINVAL;
5835         }
5836
5837         switch (filter->proto_mask) {
5838         case UINT8_MAX:
5839                 filter_info->proto_mask = 0;
5840                 filter_info->proto =
5841                         convert_protocol_type(filter->proto);
5842                 break;
5843         case 0:
5844                 filter_info->proto_mask = 1;
5845                 break;
5846         default:
5847                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5848                 return -EINVAL;
5849         }
5850
5851         filter_info->priority = (uint8_t)filter->priority;
5852         return 0;
5853 }
5854
5855 /*
5856  * add or delete a ntuple filter
5857  *
5858  * @param
5859  * dev: Pointer to struct rte_eth_dev.
5860  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5861  * add: if true, add filter, if false, remove filter
5862  *
5863  * @return
5864  *    - On success, zero.
5865  *    - On failure, a negative value.
5866  */
5867 static int
5868 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5869                         struct rte_eth_ntuple_filter *ntuple_filter,
5870                         bool add)
5871 {
5872         struct ixgbe_filter_info *filter_info =
5873                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5874         struct ixgbe_5tuple_filter_info filter_5tuple;
5875         struct ixgbe_5tuple_filter *filter;
5876         int ret;
5877
5878         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5879                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5880                 return -EINVAL;
5881         }
5882
5883         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5884         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5885         if (ret < 0)
5886                 return ret;
5887
5888         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5889                                          &filter_5tuple);
5890         if (filter != NULL && add) {
5891                 PMD_DRV_LOG(ERR, "filter exists.");
5892                 return -EEXIST;
5893         }
5894         if (filter == NULL && !add) {
5895                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5896                 return -ENOENT;
5897         }
5898
5899         if (add) {
5900                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5901                                 sizeof(struct ixgbe_5tuple_filter), 0);
5902                 if (filter == NULL)
5903                         return -ENOMEM;
5904                 (void)rte_memcpy(&filter->filter_info,
5905                                  &filter_5tuple,
5906                                  sizeof(struct ixgbe_5tuple_filter_info));
5907                 filter->queue = ntuple_filter->queue;
5908                 ret = ixgbe_add_5tuple_filter(dev, filter);
5909                 if (ret < 0) {
5910                         rte_free(filter);
5911                         return ret;
5912                 }
5913         } else
5914                 ixgbe_remove_5tuple_filter(dev, filter);
5915
5916         return 0;
5917 }
5918
5919 /*
5920  * get a ntuple filter
5921  *
5922  * @param
5923  * dev: Pointer to struct rte_eth_dev.
5924  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5925  *
5926  * @return
5927  *    - On success, zero.
5928  *    - On failure, a negative value.
5929  */
5930 static int
5931 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5932                         struct rte_eth_ntuple_filter *ntuple_filter)
5933 {
5934         struct ixgbe_filter_info *filter_info =
5935                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5936         struct ixgbe_5tuple_filter_info filter_5tuple;
5937         struct ixgbe_5tuple_filter *filter;
5938         int ret;
5939
5940         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5941                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5942                 return -EINVAL;
5943         }
5944
5945         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5946         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5947         if (ret < 0)
5948                 return ret;
5949
5950         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5951                                          &filter_5tuple);
5952         if (filter == NULL) {
5953                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5954                 return -ENOENT;
5955         }
5956         ntuple_filter->queue = filter->queue;
5957         return 0;
5958 }
5959
5960 /*
5961  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5962  * @dev: pointer to rte_eth_dev structure
5963  * @filter_op:operation will be taken.
5964  * @arg: a pointer to specific structure corresponding to the filter_op
5965  *
5966  * @return
5967  *    - On success, zero.
5968  *    - On failure, a negative value.
5969  */
5970 static int
5971 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5972                                 enum rte_filter_op filter_op,
5973                                 void *arg)
5974 {
5975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976         int ret;
5977
5978         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5979
5980         if (filter_op == RTE_ETH_FILTER_NOP)
5981                 return 0;
5982
5983         if (arg == NULL) {
5984                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5985                             filter_op);
5986                 return -EINVAL;
5987         }
5988
5989         switch (filter_op) {
5990         case RTE_ETH_FILTER_ADD:
5991                 ret = ixgbe_add_del_ntuple_filter(dev,
5992                         (struct rte_eth_ntuple_filter *)arg,
5993                         TRUE);
5994                 break;
5995         case RTE_ETH_FILTER_DELETE:
5996                 ret = ixgbe_add_del_ntuple_filter(dev,
5997                         (struct rte_eth_ntuple_filter *)arg,
5998                         FALSE);
5999                 break;
6000         case RTE_ETH_FILTER_GET:
6001                 ret = ixgbe_get_ntuple_filter(dev,
6002                         (struct rte_eth_ntuple_filter *)arg);
6003                 break;
6004         default:
6005                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6006                 ret = -EINVAL;
6007                 break;
6008         }
6009         return ret;
6010 }
6011
6012 static inline int
6013 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6014                         uint16_t ethertype)
6015 {
6016         int i;
6017
6018         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6019                 if (filter_info->ethertype_filters[i] == ethertype &&
6020                     (filter_info->ethertype_mask & (1 << i)))
6021                         return i;
6022         }
6023         return -1;
6024 }
6025
6026 static inline int
6027 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6028                         uint16_t ethertype)
6029 {
6030         int i;
6031
6032         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6033                 if (!(filter_info->ethertype_mask & (1 << i))) {
6034                         filter_info->ethertype_mask |= 1 << i;
6035                         filter_info->ethertype_filters[i] = ethertype;
6036                         return i;
6037                 }
6038         }
6039         return -1;
6040 }
6041
6042 static inline int
6043 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6044                         uint8_t idx)
6045 {
6046         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6047                 return -1;
6048         filter_info->ethertype_mask &= ~(1 << idx);
6049         filter_info->ethertype_filters[idx] = 0;
6050         return idx;
6051 }
6052
6053 static int
6054 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6055                         struct rte_eth_ethertype_filter *filter,
6056                         bool add)
6057 {
6058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6059         struct ixgbe_filter_info *filter_info =
6060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6061         uint32_t etqf = 0;
6062         uint32_t etqs = 0;
6063         int ret;
6064
6065         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6066                 return -EINVAL;
6067
6068         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6069                 filter->ether_type == ETHER_TYPE_IPv6) {
6070                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6071                         " ethertype filter.", filter->ether_type);
6072                 return -EINVAL;
6073         }
6074
6075         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6076                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6077                 return -EINVAL;
6078         }
6079         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6080                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6081                 return -EINVAL;
6082         }
6083
6084         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6085         if (ret >= 0 && add) {
6086                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6087                             filter->ether_type);
6088                 return -EEXIST;
6089         }
6090         if (ret < 0 && !add) {
6091                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6092                             filter->ether_type);
6093                 return -ENOENT;
6094         }
6095
6096         if (add) {
6097                 ret = ixgbe_ethertype_filter_insert(filter_info,
6098                         filter->ether_type);
6099                 if (ret < 0) {
6100                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6101                         return -ENOSYS;
6102                 }
6103                 etqf = IXGBE_ETQF_FILTER_EN;
6104                 etqf |= (uint32_t)filter->ether_type;
6105                 etqs |= (uint32_t)((filter->queue <<
6106                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6107                                     IXGBE_ETQS_RX_QUEUE);
6108                 etqs |= IXGBE_ETQS_QUEUE_EN;
6109         } else {
6110                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6111                 if (ret < 0)
6112                         return -ENOSYS;
6113         }
6114         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6115         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6116         IXGBE_WRITE_FLUSH(hw);
6117
6118         return 0;
6119 }
6120
6121 static int
6122 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6123                         struct rte_eth_ethertype_filter *filter)
6124 {
6125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126         struct ixgbe_filter_info *filter_info =
6127                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6128         uint32_t etqf, etqs;
6129         int ret;
6130
6131         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6132         if (ret < 0) {
6133                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6134                             filter->ether_type);
6135                 return -ENOENT;
6136         }
6137
6138         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6139         if (etqf & IXGBE_ETQF_FILTER_EN) {
6140                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6141                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6142                 filter->flags = 0;
6143                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6144                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6145                 return 0;
6146         }
6147         return -ENOENT;
6148 }
6149
6150 /*
6151  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6152  * @dev: pointer to rte_eth_dev structure
6153  * @filter_op:operation will be taken.
6154  * @arg: a pointer to specific structure corresponding to the filter_op
6155  */
6156 static int
6157 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6158                                 enum rte_filter_op filter_op,
6159                                 void *arg)
6160 {
6161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         int ret;
6163
6164         MAC_TYPE_FILTER_SUP(hw->mac.type);
6165
6166         if (filter_op == RTE_ETH_FILTER_NOP)
6167                 return 0;
6168
6169         if (arg == NULL) {
6170                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6171                             filter_op);
6172                 return -EINVAL;
6173         }
6174
6175         switch (filter_op) {
6176         case RTE_ETH_FILTER_ADD:
6177                 ret = ixgbe_add_del_ethertype_filter(dev,
6178                         (struct rte_eth_ethertype_filter *)arg,
6179                         TRUE);
6180                 break;
6181         case RTE_ETH_FILTER_DELETE:
6182                 ret = ixgbe_add_del_ethertype_filter(dev,
6183                         (struct rte_eth_ethertype_filter *)arg,
6184                         FALSE);
6185                 break;
6186         case RTE_ETH_FILTER_GET:
6187                 ret = ixgbe_get_ethertype_filter(dev,
6188                         (struct rte_eth_ethertype_filter *)arg);
6189                 break;
6190         default:
6191                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6192                 ret = -EINVAL;
6193                 break;
6194         }
6195         return ret;
6196 }
6197
6198 static int
6199 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6200                      enum rte_filter_type filter_type,
6201                      enum rte_filter_op filter_op,
6202                      void *arg)
6203 {
6204         int ret = -EINVAL;
6205
6206         switch (filter_type) {
6207         case RTE_ETH_FILTER_NTUPLE:
6208                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6209                 break;
6210         case RTE_ETH_FILTER_ETHERTYPE:
6211                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6212                 break;
6213         case RTE_ETH_FILTER_SYN:
6214                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6215                 break;
6216         case RTE_ETH_FILTER_FDIR:
6217                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6218                 break;
6219         case RTE_ETH_FILTER_L2_TUNNEL:
6220                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6221                 break;
6222         default:
6223                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6224                                                         filter_type);
6225                 break;
6226         }
6227
6228         return ret;
6229 }
6230
6231 static u8 *
6232 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6233                         u8 **mc_addr_ptr, u32 *vmdq)
6234 {
6235         u8 *mc_addr;
6236
6237         *vmdq = 0;
6238         mc_addr = *mc_addr_ptr;
6239         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6240         return mc_addr;
6241 }
6242
6243 static int
6244 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6245                           struct ether_addr *mc_addr_set,
6246                           uint32_t nb_mc_addr)
6247 {
6248         struct ixgbe_hw *hw;
6249         u8 *mc_addr_list;
6250
6251         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6252         mc_addr_list = (u8 *)mc_addr_set;
6253         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6254                                          ixgbe_dev_addr_list_itr, TRUE);
6255 }
6256
6257 static uint64_t
6258 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6259 {
6260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6261         uint64_t systime_cycles;
6262
6263         switch (hw->mac.type) {
6264         case ixgbe_mac_X550:
6265         case ixgbe_mac_X550EM_x:
6266         case ixgbe_mac_X550EM_a:
6267                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6268                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6269                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6270                                 * NSEC_PER_SEC;
6271                 break;
6272         default:
6273                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6274                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6275                                 << 32;
6276         }
6277
6278         return systime_cycles;
6279 }
6280
6281 static uint64_t
6282 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6283 {
6284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285         uint64_t rx_tstamp_cycles;
6286
6287         switch (hw->mac.type) {
6288         case ixgbe_mac_X550:
6289         case ixgbe_mac_X550EM_x:
6290         case ixgbe_mac_X550EM_a:
6291                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6292                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6293                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6294                                 * NSEC_PER_SEC;
6295                 break;
6296         default:
6297                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6298                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6299                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6300                                 << 32;
6301         }
6302
6303         return rx_tstamp_cycles;
6304 }
6305
6306 static uint64_t
6307 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6308 {
6309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6310         uint64_t tx_tstamp_cycles;
6311
6312         switch (hw->mac.type) {
6313         case ixgbe_mac_X550:
6314         case ixgbe_mac_X550EM_x:
6315         case ixgbe_mac_X550EM_a:
6316                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6317                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6318                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6319                                 * NSEC_PER_SEC;
6320                 break;
6321         default:
6322                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6323                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6324                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6325                                 << 32;
6326         }
6327
6328         return tx_tstamp_cycles;
6329 }
6330
6331 static void
6332 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6333 {
6334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6335         struct ixgbe_adapter *adapter =
6336                 (struct ixgbe_adapter *)dev->data->dev_private;
6337         struct rte_eth_link link;
6338         uint32_t incval = 0;
6339         uint32_t shift = 0;
6340
6341         /* Get current link speed. */
6342         memset(&link, 0, sizeof(link));
6343         ixgbe_dev_link_update(dev, 1);
6344         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6345
6346         switch (link.link_speed) {
6347         case ETH_SPEED_NUM_100M:
6348                 incval = IXGBE_INCVAL_100;
6349                 shift = IXGBE_INCVAL_SHIFT_100;
6350                 break;
6351         case ETH_SPEED_NUM_1G:
6352                 incval = IXGBE_INCVAL_1GB;
6353                 shift = IXGBE_INCVAL_SHIFT_1GB;
6354                 break;
6355         case ETH_SPEED_NUM_10G:
6356         default:
6357                 incval = IXGBE_INCVAL_10GB;
6358                 shift = IXGBE_INCVAL_SHIFT_10GB;
6359                 break;
6360         }
6361
6362         switch (hw->mac.type) {
6363         case ixgbe_mac_X550:
6364         case ixgbe_mac_X550EM_x:
6365         case ixgbe_mac_X550EM_a:
6366                 /* Independent of link speed. */
6367                 incval = 1;
6368                 /* Cycles read will be interpreted as ns. */
6369                 shift = 0;
6370                 /* Fall-through */
6371         case ixgbe_mac_X540:
6372                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6373                 break;
6374         case ixgbe_mac_82599EB:
6375                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6376                 shift -= IXGBE_INCVAL_SHIFT_82599;
6377                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6378                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6379                 break;
6380         default:
6381                 /* Not supported. */
6382                 return;
6383         }
6384
6385         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6386         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6387         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6388
6389         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6390         adapter->systime_tc.cc_shift = shift;
6391         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6392
6393         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6394         adapter->rx_tstamp_tc.cc_shift = shift;
6395         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6396
6397         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6398         adapter->tx_tstamp_tc.cc_shift = shift;
6399         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6400 }
6401
6402 static int
6403 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6404 {
6405         struct ixgbe_adapter *adapter =
6406                         (struct ixgbe_adapter *)dev->data->dev_private;
6407
6408         adapter->systime_tc.nsec += delta;
6409         adapter->rx_tstamp_tc.nsec += delta;
6410         adapter->tx_tstamp_tc.nsec += delta;
6411
6412         return 0;
6413 }
6414
6415 static int
6416 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6417 {
6418         uint64_t ns;
6419         struct ixgbe_adapter *adapter =
6420                         (struct ixgbe_adapter *)dev->data->dev_private;
6421
6422         ns = rte_timespec_to_ns(ts);
6423         /* Set the timecounters to a new value. */
6424         adapter->systime_tc.nsec = ns;
6425         adapter->rx_tstamp_tc.nsec = ns;
6426         adapter->tx_tstamp_tc.nsec = ns;
6427
6428         return 0;
6429 }
6430
6431 static int
6432 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6433 {
6434         uint64_t ns, systime_cycles;
6435         struct ixgbe_adapter *adapter =
6436                         (struct ixgbe_adapter *)dev->data->dev_private;
6437
6438         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6439         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6440         *ts = rte_ns_to_timespec(ns);
6441
6442         return 0;
6443 }
6444
6445 static int
6446 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6447 {
6448         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6449         uint32_t tsync_ctl;
6450         uint32_t tsauxc;
6451
6452         /* Stop the timesync system time. */
6453         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6454         /* Reset the timesync system time value. */
6455         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6456         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6457
6458         /* Enable system time for platforms where it isn't on by default. */
6459         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6460         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6461         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6462
6463         ixgbe_start_timecounters(dev);
6464
6465         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6466         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6467                         (ETHER_TYPE_1588 |
6468                          IXGBE_ETQF_FILTER_EN |
6469                          IXGBE_ETQF_1588));
6470
6471         /* Enable timestamping of received PTP packets. */
6472         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6473         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6474         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6475
6476         /* Enable timestamping of transmitted PTP packets. */
6477         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6478         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6479         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6480
6481         IXGBE_WRITE_FLUSH(hw);
6482
6483         return 0;
6484 }
6485
6486 static int
6487 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6488 {
6489         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6490         uint32_t tsync_ctl;
6491
6492         /* Disable timestamping of transmitted PTP packets. */
6493         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6494         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6495         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6496
6497         /* Disable timestamping of received PTP packets. */
6498         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6499         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6500         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6501
6502         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6503         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6504
6505         /* Stop incrementating the System Time registers. */
6506         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6507
6508         return 0;
6509 }
6510
6511 static int
6512 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6513                                  struct timespec *timestamp,
6514                                  uint32_t flags __rte_unused)
6515 {
6516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517         struct ixgbe_adapter *adapter =
6518                 (struct ixgbe_adapter *)dev->data->dev_private;
6519         uint32_t tsync_rxctl;
6520         uint64_t rx_tstamp_cycles;
6521         uint64_t ns;
6522
6523         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6524         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6525                 return -EINVAL;
6526
6527         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6528         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6529         *timestamp = rte_ns_to_timespec(ns);
6530
6531         return  0;
6532 }
6533
6534 static int
6535 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6536                                  struct timespec *timestamp)
6537 {
6538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6539         struct ixgbe_adapter *adapter =
6540                 (struct ixgbe_adapter *)dev->data->dev_private;
6541         uint32_t tsync_txctl;
6542         uint64_t tx_tstamp_cycles;
6543         uint64_t ns;
6544
6545         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6546         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6547                 return -EINVAL;
6548
6549         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6550         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6551         *timestamp = rte_ns_to_timespec(ns);
6552
6553         return 0;
6554 }
6555
6556 static int
6557 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6558 {
6559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560         int count = 0;
6561         int g_ind = 0;
6562         const struct reg_info *reg_group;
6563         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6564                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6565
6566         while ((reg_group = reg_set[g_ind++]))
6567                 count += ixgbe_regs_group_count(reg_group);
6568
6569         return count;
6570 }
6571
6572 static int
6573 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6574 {
6575         int count = 0;
6576         int g_ind = 0;
6577         const struct reg_info *reg_group;
6578
6579         while ((reg_group = ixgbevf_regs[g_ind++]))
6580                 count += ixgbe_regs_group_count(reg_group);
6581
6582         return count;
6583 }
6584
6585 static int
6586 ixgbe_get_regs(struct rte_eth_dev *dev,
6587               struct rte_dev_reg_info *regs)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         uint32_t *data = regs->data;
6591         int g_ind = 0;
6592         int count = 0;
6593         const struct reg_info *reg_group;
6594         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6595                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6596
6597         if (data == NULL) {
6598                 regs->length = ixgbe_get_reg_length(dev);
6599                 regs->width = sizeof(uint32_t);
6600                 return 0;
6601         }
6602
6603         /* Support only full register dump */
6604         if ((regs->length == 0) ||
6605             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6606                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6607                         hw->device_id;
6608                 while ((reg_group = reg_set[g_ind++]))
6609                         count += ixgbe_read_regs_group(dev, &data[count],
6610                                 reg_group);
6611                 return 0;
6612         }
6613
6614         return -ENOTSUP;
6615 }
6616
6617 static int
6618 ixgbevf_get_regs(struct rte_eth_dev *dev,
6619                 struct rte_dev_reg_info *regs)
6620 {
6621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6622         uint32_t *data = regs->data;
6623         int g_ind = 0;
6624         int count = 0;
6625         const struct reg_info *reg_group;
6626
6627         if (data == NULL) {
6628                 regs->length = ixgbevf_get_reg_length(dev);
6629                 regs->width = sizeof(uint32_t);
6630                 return 0;
6631         }
6632
6633         /* Support only full register dump */
6634         if ((regs->length == 0) ||
6635             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6636                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6637                         hw->device_id;
6638                 while ((reg_group = ixgbevf_regs[g_ind++]))
6639                         count += ixgbe_read_regs_group(dev, &data[count],
6640                                                       reg_group);
6641                 return 0;
6642         }
6643
6644         return -ENOTSUP;
6645 }
6646
6647 static int
6648 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6649 {
6650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6651
6652         /* Return unit is byte count */
6653         return hw->eeprom.word_size * 2;
6654 }
6655
6656 static int
6657 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6658                 struct rte_dev_eeprom_info *in_eeprom)
6659 {
6660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6662         uint16_t *data = in_eeprom->data;
6663         int first, length;
6664
6665         first = in_eeprom->offset >> 1;
6666         length = in_eeprom->length >> 1;
6667         if ((first > hw->eeprom.word_size) ||
6668             ((first + length) > hw->eeprom.word_size))
6669                 return -EINVAL;
6670
6671         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6672
6673         return eeprom->ops.read_buffer(hw, first, length, data);
6674 }
6675
6676 static int
6677 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6678                 struct rte_dev_eeprom_info *in_eeprom)
6679 {
6680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6681         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6682         uint16_t *data = in_eeprom->data;
6683         int first, length;
6684
6685         first = in_eeprom->offset >> 1;
6686         length = in_eeprom->length >> 1;
6687         if ((first > hw->eeprom.word_size) ||
6688             ((first + length) > hw->eeprom.word_size))
6689                 return -EINVAL;
6690
6691         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6692
6693         return eeprom->ops.write_buffer(hw,  first, length, data);
6694 }
6695
6696 uint16_t
6697 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6698         switch (mac_type) {
6699         case ixgbe_mac_X550:
6700         case ixgbe_mac_X550EM_x:
6701         case ixgbe_mac_X550EM_a:
6702                 return ETH_RSS_RETA_SIZE_512;
6703         case ixgbe_mac_X550_vf:
6704         case ixgbe_mac_X550EM_x_vf:
6705         case ixgbe_mac_X550EM_a_vf:
6706                 return ETH_RSS_RETA_SIZE_64;
6707         default:
6708                 return ETH_RSS_RETA_SIZE_128;
6709         }
6710 }
6711
6712 uint32_t
6713 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6714         switch (mac_type) {
6715         case ixgbe_mac_X550:
6716         case ixgbe_mac_X550EM_x:
6717         case ixgbe_mac_X550EM_a:
6718                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6719                         return IXGBE_RETA(reta_idx >> 2);
6720                 else
6721                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6722         case ixgbe_mac_X550_vf:
6723         case ixgbe_mac_X550EM_x_vf:
6724         case ixgbe_mac_X550EM_a_vf:
6725                 return IXGBE_VFRETA(reta_idx >> 2);
6726         default:
6727                 return IXGBE_RETA(reta_idx >> 2);
6728         }
6729 }
6730
6731 uint32_t
6732 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6733         switch (mac_type) {
6734         case ixgbe_mac_X550_vf:
6735         case ixgbe_mac_X550EM_x_vf:
6736         case ixgbe_mac_X550EM_a_vf:
6737                 return IXGBE_VFMRQC;
6738         default:
6739                 return IXGBE_MRQC;
6740         }
6741 }
6742
6743 uint32_t
6744 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6745         switch (mac_type) {
6746         case ixgbe_mac_X550_vf:
6747         case ixgbe_mac_X550EM_x_vf:
6748         case ixgbe_mac_X550EM_a_vf:
6749                 return IXGBE_VFRSSRK(i);
6750         default:
6751                 return IXGBE_RSSRK(i);
6752         }
6753 }
6754
6755 bool
6756 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6757         switch (mac_type) {
6758         case ixgbe_mac_82599_vf:
6759         case ixgbe_mac_X540_vf:
6760                 return 0;
6761         default:
6762                 return 1;
6763         }
6764 }
6765
6766 static int
6767 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6768                         struct rte_eth_dcb_info *dcb_info)
6769 {
6770         struct ixgbe_dcb_config *dcb_config =
6771                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6772         struct ixgbe_dcb_tc_config *tc;
6773         uint8_t i, j;
6774
6775         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6776                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6777         else
6778                 dcb_info->nb_tcs = 1;
6779
6780         if (dcb_config->vt_mode) { /* vt is enabled*/
6781                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6782                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6783                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6784                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6785                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6786                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6787                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6788                                                 i * dcb_info->nb_tcs + j;
6789                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6790                                 dcb_info->tc_queue.tc_txq[i][j].base =
6791                                                 i * dcb_info->nb_tcs + j;
6792                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6793                         }
6794                 }
6795         } else { /* vt is disabled*/
6796                 struct rte_eth_dcb_rx_conf *rx_conf =
6797                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6798                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6799                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6800                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6801                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6802                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6803                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6804                         }
6805                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6806                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6807                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6808                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6809                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6810                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6811                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6812                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6813                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6814                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6815                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6816                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6817                         }
6818                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6819                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6820                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6821                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6822                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6823                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6824                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6825                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6826                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6827                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6828                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6829                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6830                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6831                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6832                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6833                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6834                 }
6835         }
6836         for (i = 0; i < dcb_info->nb_tcs; i++) {
6837                 tc = &dcb_config->tc_config[i];
6838                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6839         }
6840         return 0;
6841 }
6842
6843 /* Update e-tag ether type */
6844 static int
6845 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6846                             uint16_t ether_type)
6847 {
6848         uint32_t etag_etype;
6849
6850         if (hw->mac.type != ixgbe_mac_X550 &&
6851             hw->mac.type != ixgbe_mac_X550EM_x &&
6852             hw->mac.type != ixgbe_mac_X550EM_a) {
6853                 return -ENOTSUP;
6854         }
6855
6856         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6857         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6858         etag_etype |= ether_type;
6859         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6860         IXGBE_WRITE_FLUSH(hw);
6861
6862         return 0;
6863 }
6864
6865 /* Config l2 tunnel ether type */
6866 static int
6867 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6868                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6869 {
6870         int ret = 0;
6871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872
6873         if (l2_tunnel == NULL)
6874                 return -EINVAL;
6875
6876         switch (l2_tunnel->l2_tunnel_type) {
6877         case RTE_L2_TUNNEL_TYPE_E_TAG:
6878                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6879                 break;
6880         default:
6881                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6882                 ret = -EINVAL;
6883                 break;
6884         }
6885
6886         return ret;
6887 }
6888
6889 /* Enable e-tag tunnel */
6890 static int
6891 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6892 {
6893         uint32_t etag_etype;
6894
6895         if (hw->mac.type != ixgbe_mac_X550 &&
6896             hw->mac.type != ixgbe_mac_X550EM_x &&
6897             hw->mac.type != ixgbe_mac_X550EM_a) {
6898                 return -ENOTSUP;
6899         }
6900
6901         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6902         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6903         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6904         IXGBE_WRITE_FLUSH(hw);
6905
6906         return 0;
6907 }
6908
6909 /* Enable l2 tunnel */
6910 static int
6911 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6912                            enum rte_eth_tunnel_type l2_tunnel_type)
6913 {
6914         int ret = 0;
6915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6916
6917         switch (l2_tunnel_type) {
6918         case RTE_L2_TUNNEL_TYPE_E_TAG:
6919                 ret = ixgbe_e_tag_enable(hw);
6920                 break;
6921         default:
6922                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6923                 ret = -EINVAL;
6924                 break;
6925         }
6926
6927         return ret;
6928 }
6929
6930 /* Disable e-tag tunnel */
6931 static int
6932 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6933 {
6934         uint32_t etag_etype;
6935
6936         if (hw->mac.type != ixgbe_mac_X550 &&
6937             hw->mac.type != ixgbe_mac_X550EM_x &&
6938             hw->mac.type != ixgbe_mac_X550EM_a) {
6939                 return -ENOTSUP;
6940         }
6941
6942         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6943         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6944         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6945         IXGBE_WRITE_FLUSH(hw);
6946
6947         return 0;
6948 }
6949
6950 /* Disable l2 tunnel */
6951 static int
6952 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6953                             enum rte_eth_tunnel_type l2_tunnel_type)
6954 {
6955         int ret = 0;
6956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957
6958         switch (l2_tunnel_type) {
6959         case RTE_L2_TUNNEL_TYPE_E_TAG:
6960                 ret = ixgbe_e_tag_disable(hw);
6961                 break;
6962         default:
6963                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6964                 ret = -EINVAL;
6965                 break;
6966         }
6967
6968         return ret;
6969 }
6970
6971 static int
6972 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6973                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6974 {
6975         int ret = 0;
6976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977         uint32_t i, rar_entries;
6978         uint32_t rar_low, rar_high;
6979
6980         if (hw->mac.type != ixgbe_mac_X550 &&
6981             hw->mac.type != ixgbe_mac_X550EM_x &&
6982             hw->mac.type != ixgbe_mac_X550EM_a) {
6983                 return -ENOTSUP;
6984         }
6985
6986         rar_entries = ixgbe_get_num_rx_addrs(hw);
6987
6988         for (i = 1; i < rar_entries; i++) {
6989                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6990                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6991                 if ((rar_high & IXGBE_RAH_AV) &&
6992                     (rar_high & IXGBE_RAH_ADTYPE) &&
6993                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6994                      l2_tunnel->tunnel_id)) {
6995                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6996                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6997
6998                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6999
7000                         return ret;
7001                 }
7002         }
7003
7004         return ret;
7005 }
7006
7007 static int
7008 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7009                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7010 {
7011         int ret = 0;
7012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         uint32_t i, rar_entries;
7014         uint32_t rar_low, rar_high;
7015
7016         if (hw->mac.type != ixgbe_mac_X550 &&
7017             hw->mac.type != ixgbe_mac_X550EM_x &&
7018             hw->mac.type != ixgbe_mac_X550EM_a) {
7019                 return -ENOTSUP;
7020         }
7021
7022         /* One entry for one tunnel. Try to remove potential existing entry. */
7023         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7024
7025         rar_entries = ixgbe_get_num_rx_addrs(hw);
7026
7027         for (i = 1; i < rar_entries; i++) {
7028                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7029                 if (rar_high & IXGBE_RAH_AV) {
7030                         continue;
7031                 } else {
7032                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7033                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7034                         rar_low = l2_tunnel->tunnel_id;
7035
7036                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7037                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7038
7039                         return ret;
7040                 }
7041         }
7042
7043         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7044                      " Please remove a rule before adding a new one.");
7045         return -EINVAL;
7046 }
7047
7048 /* Add l2 tunnel filter */
7049 static int
7050 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7051                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7052 {
7053         int ret = 0;
7054
7055         switch (l2_tunnel->l2_tunnel_type) {
7056         case RTE_L2_TUNNEL_TYPE_E_TAG:
7057                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7058                 break;
7059         default:
7060                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7061                 ret = -EINVAL;
7062                 break;
7063         }
7064
7065         return ret;
7066 }
7067
7068 /* Delete l2 tunnel filter */
7069 static int
7070 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7071                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7072 {
7073         int ret = 0;
7074
7075         switch (l2_tunnel->l2_tunnel_type) {
7076         case RTE_L2_TUNNEL_TYPE_E_TAG:
7077                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7078                 break;
7079         default:
7080                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7081                 ret = -EINVAL;
7082                 break;
7083         }
7084
7085         return ret;
7086 }
7087
7088 /**
7089  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7090  * @dev: pointer to rte_eth_dev structure
7091  * @filter_op:operation will be taken.
7092  * @arg: a pointer to specific structure corresponding to the filter_op
7093  */
7094 static int
7095 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7096                                   enum rte_filter_op filter_op,
7097                                   void *arg)
7098 {
7099         int ret = 0;
7100
7101         if (filter_op == RTE_ETH_FILTER_NOP)
7102                 return 0;
7103
7104         if (arg == NULL) {
7105                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7106                             filter_op);
7107                 return -EINVAL;
7108         }
7109
7110         switch (filter_op) {
7111         case RTE_ETH_FILTER_ADD:
7112                 ret = ixgbe_dev_l2_tunnel_filter_add
7113                         (dev,
7114                          (struct rte_eth_l2_tunnel_conf *)arg);
7115                 break;
7116         case RTE_ETH_FILTER_DELETE:
7117                 ret = ixgbe_dev_l2_tunnel_filter_del
7118                         (dev,
7119                          (struct rte_eth_l2_tunnel_conf *)arg);
7120                 break;
7121         default:
7122                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7123                 ret = -EINVAL;
7124                 break;
7125         }
7126         return ret;
7127 }
7128
7129 static int
7130 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7131 {
7132         int ret = 0;
7133         uint32_t ctrl;
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135
7136         if (hw->mac.type != ixgbe_mac_X550 &&
7137             hw->mac.type != ixgbe_mac_X550EM_x &&
7138             hw->mac.type != ixgbe_mac_X550EM_a) {
7139                 return -ENOTSUP;
7140         }
7141
7142         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7143         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7144         if (en)
7145                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7146         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7147
7148         return ret;
7149 }
7150
7151 /* Enable l2 tunnel forwarding */
7152 static int
7153 ixgbe_dev_l2_tunnel_forwarding_enable
7154         (struct rte_eth_dev *dev,
7155          enum rte_eth_tunnel_type l2_tunnel_type)
7156 {
7157         int ret = 0;
7158
7159         switch (l2_tunnel_type) {
7160         case RTE_L2_TUNNEL_TYPE_E_TAG:
7161                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7162                 break;
7163         default:
7164                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7165                 ret = -EINVAL;
7166                 break;
7167         }
7168
7169         return ret;
7170 }
7171
7172 /* Disable l2 tunnel forwarding */
7173 static int
7174 ixgbe_dev_l2_tunnel_forwarding_disable
7175         (struct rte_eth_dev *dev,
7176          enum rte_eth_tunnel_type l2_tunnel_type)
7177 {
7178         int ret = 0;
7179
7180         switch (l2_tunnel_type) {
7181         case RTE_L2_TUNNEL_TYPE_E_TAG:
7182                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7183                 break;
7184         default:
7185                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7186                 ret = -EINVAL;
7187                 break;
7188         }
7189
7190         return ret;
7191 }
7192
7193 static int
7194 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7195                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7196                              bool en)
7197 {
7198         int ret = 0;
7199         uint32_t vmtir, vmvir;
7200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201
7202         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
7203                 PMD_DRV_LOG(ERR,
7204                             "VF id %u should be less than %u",
7205                             l2_tunnel->vf_id,
7206                             dev->pci_dev->max_vfs);
7207                 return -EINVAL;
7208         }
7209
7210         if (hw->mac.type != ixgbe_mac_X550 &&
7211             hw->mac.type != ixgbe_mac_X550EM_x &&
7212             hw->mac.type != ixgbe_mac_X550EM_a) {
7213                 return -ENOTSUP;
7214         }
7215
7216         if (en)
7217                 vmtir = l2_tunnel->tunnel_id;
7218         else
7219                 vmtir = 0;
7220
7221         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7222
7223         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7224         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7225         if (en)
7226                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7227         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7228
7229         return ret;
7230 }
7231
7232 /* Enable l2 tunnel tag insertion */
7233 static int
7234 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7235                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7236 {
7237         int ret = 0;
7238
7239         switch (l2_tunnel->l2_tunnel_type) {
7240         case RTE_L2_TUNNEL_TYPE_E_TAG:
7241                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7242                 break;
7243         default:
7244                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7245                 ret = -EINVAL;
7246                 break;
7247         }
7248
7249         return ret;
7250 }
7251
7252 /* Disable l2 tunnel tag insertion */
7253 static int
7254 ixgbe_dev_l2_tunnel_insertion_disable
7255         (struct rte_eth_dev *dev,
7256          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7257 {
7258         int ret = 0;
7259
7260         switch (l2_tunnel->l2_tunnel_type) {
7261         case RTE_L2_TUNNEL_TYPE_E_TAG:
7262                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7263                 break;
7264         default:
7265                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7266                 ret = -EINVAL;
7267                 break;
7268         }
7269
7270         return ret;
7271 }
7272
7273 static int
7274 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7275                              bool en)
7276 {
7277         int ret = 0;
7278         uint32_t qde;
7279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7280
7281         if (hw->mac.type != ixgbe_mac_X550 &&
7282             hw->mac.type != ixgbe_mac_X550EM_x &&
7283             hw->mac.type != ixgbe_mac_X550EM_a) {
7284                 return -ENOTSUP;
7285         }
7286
7287         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7288         if (en)
7289                 qde |= IXGBE_QDE_STRIP_TAG;
7290         else
7291                 qde &= ~IXGBE_QDE_STRIP_TAG;
7292         qde &= ~IXGBE_QDE_READ;
7293         qde |= IXGBE_QDE_WRITE;
7294         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7295
7296         return ret;
7297 }
7298
7299 /* Enable l2 tunnel tag stripping */
7300 static int
7301 ixgbe_dev_l2_tunnel_stripping_enable
7302         (struct rte_eth_dev *dev,
7303          enum rte_eth_tunnel_type l2_tunnel_type)
7304 {
7305         int ret = 0;
7306
7307         switch (l2_tunnel_type) {
7308         case RTE_L2_TUNNEL_TYPE_E_TAG:
7309                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7310                 break;
7311         default:
7312                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7313                 ret = -EINVAL;
7314                 break;
7315         }
7316
7317         return ret;
7318 }
7319
7320 /* Disable l2 tunnel tag stripping */
7321 static int
7322 ixgbe_dev_l2_tunnel_stripping_disable
7323         (struct rte_eth_dev *dev,
7324          enum rte_eth_tunnel_type l2_tunnel_type)
7325 {
7326         int ret = 0;
7327
7328         switch (l2_tunnel_type) {
7329         case RTE_L2_TUNNEL_TYPE_E_TAG:
7330                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7331                 break;
7332         default:
7333                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7334                 ret = -EINVAL;
7335                 break;
7336         }
7337
7338         return ret;
7339 }
7340
7341 /* Enable/disable l2 tunnel offload functions */
7342 static int
7343 ixgbe_dev_l2_tunnel_offload_set
7344         (struct rte_eth_dev *dev,
7345          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7346          uint32_t mask,
7347          uint8_t en)
7348 {
7349         int ret = 0;
7350
7351         if (l2_tunnel == NULL)
7352                 return -EINVAL;
7353
7354         ret = -EINVAL;
7355         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7356                 if (en)
7357                         ret = ixgbe_dev_l2_tunnel_enable(
7358                                 dev,
7359                                 l2_tunnel->l2_tunnel_type);
7360                 else
7361                         ret = ixgbe_dev_l2_tunnel_disable(
7362                                 dev,
7363                                 l2_tunnel->l2_tunnel_type);
7364         }
7365
7366         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7367                 if (en)
7368                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7369                                 dev,
7370                                 l2_tunnel);
7371                 else
7372                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7373                                 dev,
7374                                 l2_tunnel);
7375         }
7376
7377         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7378                 if (en)
7379                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7380                                 dev,
7381                                 l2_tunnel->l2_tunnel_type);
7382                 else
7383                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7384                                 dev,
7385                                 l2_tunnel->l2_tunnel_type);
7386         }
7387
7388         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7389                 if (en)
7390                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7391                                 dev,
7392                                 l2_tunnel->l2_tunnel_type);
7393                 else
7394                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7395                                 dev,
7396                                 l2_tunnel->l2_tunnel_type);
7397         }
7398
7399         return ret;
7400 }
7401
7402 static int
7403 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7404                         uint16_t port)
7405 {
7406         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7407         IXGBE_WRITE_FLUSH(hw);
7408
7409         return 0;
7410 }
7411
7412 /* There's only one register for VxLAN UDP port.
7413  * So, we cannot add several ports. Will update it.
7414  */
7415 static int
7416 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7417                      uint16_t port)
7418 {
7419         if (port == 0) {
7420                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7421                 return -EINVAL;
7422         }
7423
7424         return ixgbe_update_vxlan_port(hw, port);
7425 }
7426
7427 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7428  * UDP port, it must have a value.
7429  * So, will reset it to the original value 0.
7430  */
7431 static int
7432 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7433                      uint16_t port)
7434 {
7435         uint16_t cur_port;
7436
7437         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7438
7439         if (cur_port != port) {
7440                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7441                 return -EINVAL;
7442         }
7443
7444         return ixgbe_update_vxlan_port(hw, 0);
7445 }
7446
7447 /* Add UDP tunneling port */
7448 static int
7449 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7450                               struct rte_eth_udp_tunnel *udp_tunnel)
7451 {
7452         int ret = 0;
7453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7454
7455         if (hw->mac.type != ixgbe_mac_X550 &&
7456             hw->mac.type != ixgbe_mac_X550EM_x &&
7457             hw->mac.type != ixgbe_mac_X550EM_a) {
7458                 return -ENOTSUP;
7459         }
7460
7461         if (udp_tunnel == NULL)
7462                 return -EINVAL;
7463
7464         switch (udp_tunnel->prot_type) {
7465         case RTE_TUNNEL_TYPE_VXLAN:
7466                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7467                 break;
7468
7469         case RTE_TUNNEL_TYPE_GENEVE:
7470         case RTE_TUNNEL_TYPE_TEREDO:
7471                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7472                 ret = -EINVAL;
7473                 break;
7474
7475         default:
7476                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7477                 ret = -EINVAL;
7478                 break;
7479         }
7480
7481         return ret;
7482 }
7483
7484 /* Remove UDP tunneling port */
7485 static int
7486 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7487                               struct rte_eth_udp_tunnel *udp_tunnel)
7488 {
7489         int ret = 0;
7490         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7491
7492         if (hw->mac.type != ixgbe_mac_X550 &&
7493             hw->mac.type != ixgbe_mac_X550EM_x &&
7494             hw->mac.type != ixgbe_mac_X550EM_a) {
7495                 return -ENOTSUP;
7496         }
7497
7498         if (udp_tunnel == NULL)
7499                 return -EINVAL;
7500
7501         switch (udp_tunnel->prot_type) {
7502         case RTE_TUNNEL_TYPE_VXLAN:
7503                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7504                 break;
7505         case RTE_TUNNEL_TYPE_GENEVE:
7506         case RTE_TUNNEL_TYPE_TEREDO:
7507                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7508                 ret = -EINVAL;
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512                 ret = -EINVAL;
7513                 break;
7514         }
7515
7516         return ret;
7517 }
7518
7519 static void
7520 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7521 {
7522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7523
7524         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7525 }
7526
7527 static void
7528 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7529 {
7530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7531
7532         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7533 }
7534
7535 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7536 {
7537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7538         u32 in_msg = 0;
7539
7540         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7541                 return;
7542
7543         /* PF reset VF event */
7544         if (in_msg == IXGBE_PF_CONTROL_MSG)
7545                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7546 }
7547
7548 static int
7549 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7550 {
7551         uint32_t eicr;
7552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7553         struct ixgbe_interrupt *intr =
7554                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7555         ixgbevf_intr_disable(hw);
7556
7557         /* read-on-clear nic registers here */
7558         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7559         intr->flags = 0;
7560
7561         /* only one misc vector supported - mailbox */
7562         eicr &= IXGBE_VTEICR_MASK;
7563         if (eicr == IXGBE_MISC_VEC_ID)
7564                 intr->flags |= IXGBE_FLAG_MAILBOX;
7565
7566         return 0;
7567 }
7568
7569 static int
7570 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7571 {
7572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7573         struct ixgbe_interrupt *intr =
7574                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7575
7576         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7577                 ixgbevf_mbx_process(dev);
7578                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7579         }
7580
7581         ixgbevf_intr_enable(hw);
7582
7583         return 0;
7584 }
7585
7586 static void
7587 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7588                               void *param)
7589 {
7590         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7591
7592         ixgbevf_dev_interrupt_get_status(dev);
7593         ixgbevf_dev_interrupt_action(dev);
7594 }
7595
7596 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7597 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7598 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7599 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);