drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 265
 266 /* For Eth VMDQ APIs support */
 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 268                 ether_addr * mac_addr, uint8_t on);
 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 271                 struct rte_eth_mirror_conf *mirror_conf,
 272                 uint8_t rule_id, uint8_t on);
 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 274                 uint8_t rule_id);
 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                           uint16_t queue_id);
 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                            uint16_t queue_id);
 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 280                                uint8_t queue, uint8_t msix_vector);
 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 282
 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 284                                 struct ether_addr *mac_addr,
 285                                 uint32_t index, uint32_t pool);
 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 288                                              struct ether_addr *mac_addr);
 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 290                         struct rte_eth_syn_filter *filter);
 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 292                         enum rte_filter_op filter_op,
 293                         void *arg);
 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ntuple_filter *filter);
 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 304                                 enum rte_filter_op filter_op,
 305                                 void *arg);
 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 307                         struct rte_eth_ethertype_filter *filter);
 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 309                      enum rte_filter_type filter_type,
 310                      enum rte_filter_op filter_op,
 311                      void *arg);
 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 313
 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 315                                       struct ether_addr *mc_addr_set,
 316                                       uint32_t nb_mc_addr);
 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 318                                    struct rte_eth_dcb_info *dcb_info);
 319
 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 322                             struct rte_dev_reg_info *regs);
 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328
 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 330                                  struct rte_eth_dev_module_info *modinfo);
 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 332                                    struct rte_dev_eeprom_info *info);
 333
 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 336                                 struct rte_dev_reg_info *regs);
 337
 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp,
 342                                             uint32_t flags);
 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp);
 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 347                                    struct timespec *timestamp);
 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 349                                    const struct timespec *timestamp);
 350 static void ixgbevf_dev_interrupt_handler(void *param);
 351
 352 static int ixgbe_dev_l2_tunnel_eth_type_conf
 353         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 354 static int ixgbe_dev_l2_tunnel_offload_set
 355         (struct rte_eth_dev *dev,
 356          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 357          uint32_t mask,
 358          uint8_t en);
 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 360                                              enum rte_filter_op filter_op,
 361                                              void *arg);
 362
 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 369
 370 /*
 371  * Define VF Stats MACRO for Non "cleared on read" register
 372  */
 373 #define UPDATE_VF_STAT(reg, last, cur)                          \
 374 {                                                               \
 375         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 376         cur += (latest - last) & UINT_MAX;                      \
 377         last = latest;                                          \
 378 }
 379
 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 381 {                                                                \
 382         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 383         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 384         u64 latest = ((new_msb << 32) | new_lsb);                \
 385         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 386         last = latest;                                           \
 387 }
 388
 389 #define IXGBE_SET_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] |= 1 << bit;\
 393         } while (0)
 394
 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (h)->bitmap[idx] &= ~(1 << bit);\
 399         } while (0)
 400
 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (r) = (h)->bitmap[idx] >> bit & 1;\
 405         } while (0)
 406
 407 int ixgbe_logtype_init;
 408 int ixgbe_logtype_driver;
 409
 410 /*
 411  * The set of PCI devices this driver supports
 412  */
 413 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1123                 PMD_INIT_LOG(ERR, "\nERROR: "
1124                         "Firmware recovery mode detected. Limiting functionality.\n"
1125                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1126                         "User Guide for details on firmware recovery mode.");
1127                 return -EIO;
1128         }
1129
1130         /* pick up the PCI bus settings for reporting later */
1131         ixgbe_get_bus_info(hw);
1132
1133         /* Unlock any pending hardware semaphore */
1134         ixgbe_swfw_lock_reset(hw);
1135
1136 #ifdef RTE_LIBRTE_SECURITY
1137         /* Initialize security_ctx only for primary process*/
1138         if (ixgbe_ipsec_ctx_create(eth_dev))
1139                 return -ENOMEM;
1140 #endif
1141
1142         /* Initialize DCB configuration*/
1143         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1144         ixgbe_dcb_init(hw, dcb_config);
1145         /* Get Hardware Flow Control setting */
1146         hw->fc.requested_mode = ixgbe_fc_full;
1147         hw->fc.current_mode = ixgbe_fc_full;
1148         hw->fc.pause_time = IXGBE_FC_PAUSE;
1149         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1150                 hw->fc.low_water[i] = IXGBE_FC_LO;
1151                 hw->fc.high_water[i] = IXGBE_FC_HI;
1152         }
1153         hw->fc.send_xon = 1;
1154
1155         /* Make sure we have a good EEPROM before we read from it */
1156         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1157         if (diag != IXGBE_SUCCESS) {
1158                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1159                 return -EIO;
1160         }
1161
1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1163         diag = ixgbe_bypass_init_hw(hw);
1164 #else
1165         diag = ixgbe_init_hw(hw);
1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1167
1168         /*
1169          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1170          * is called too soon after the kernel driver unbinding/binding occurs.
1171          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1172          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1173          * also called. See ixgbe_identify_phy_82599(). The reason for the
1174          * failure is not known, and only occuts when virtualisation features
1175          * are disabled in the bios. A delay of 100ms  was found to be enough by
1176          * trial-and-error, and is doubled to be safe.
1177          */
1178         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1179                 rte_delay_ms(200);
1180                 diag = ixgbe_init_hw(hw);
1181         }
1182
1183         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1184                 diag = IXGBE_SUCCESS;
1185
1186         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1187                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1188                              "LOM.  Please be aware there may be issues associated "
1189                              "with your hardware.");
1190                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1191                              "please contact your Intel or hardware representative "
1192                              "who provided you with this hardware.");
1193         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1194                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1195         if (diag) {
1196                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1197                 return -EIO;
1198         }
1199
1200         /* Reset the hw statistics */
1201         ixgbe_dev_stats_reset(eth_dev);
1202
1203         /* disable interrupt */
1204         ixgbe_disable_intr(hw);
1205
1206         /* reset mappings for queue statistics hw counters*/
1207         ixgbe_reset_qstat_mappings(hw);
1208
1209         /* Allocate memory for storing MAC addresses */
1210         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1211                                                hw->mac.num_rar_entries, 0);
1212         if (eth_dev->data->mac_addrs == NULL) {
1213                 PMD_INIT_LOG(ERR,
1214                              "Failed to allocate %u bytes needed to store "
1215                              "MAC addresses",
1216                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1217                 return -ENOMEM;
1218         }
1219         /* Copy the permanent MAC address */
1220         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1221                         &eth_dev->data->mac_addrs[0]);
1222
1223         /* Allocate memory for storing hash filter MAC addresses */
1224         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1226         if (eth_dev->data->hash_mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %d bytes needed to store MAC addresses",
1229                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1230                 return -ENOMEM;
1231         }
1232
1233         /* initialize the vfta */
1234         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1235
1236         /* initialize the hw strip bitmap*/
1237         memset(hwstrip, 0, sizeof(*hwstrip));
1238
1239         /* initialize PF if max_vfs not zero */
1240         ixgbe_pf_host_init(eth_dev);
1241
1242         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1243         /* let hardware know driver is loaded */
1244         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1245         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1247         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1248         IXGBE_WRITE_FLUSH(hw);
1249
1250         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1251                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1252                              (int) hw->mac.type, (int) hw->phy.type,
1253                              (int) hw->phy.sfp_type);
1254         else
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type);
1257
1258         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1259                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1260                      pci_dev->id.device_id);
1261
1262         rte_intr_callback_register(intr_handle,
1263                                    ixgbe_dev_interrupt_handler, eth_dev);
1264
1265         /* enable uio/vfio intr/eventfd mapping */
1266         rte_intr_enable(intr_handle);
1267
1268         /* enable support intr */
1269         ixgbe_enable_intr(eth_dev);
1270
1271         /* initialize filter info */
1272         memset(filter_info, 0,
1273                sizeof(struct ixgbe_filter_info));
1274
1275         /* initialize 5tuple filter list */
1276         TAILQ_INIT(&filter_info->fivetuple_list);
1277
1278         /* initialize flow director filter list & hash */
1279         ixgbe_fdir_filter_init(eth_dev);
1280
1281         /* initialize l2 tunnel filter list & hash */
1282         ixgbe_l2_tn_filter_init(eth_dev);
1283
1284         /* initialize flow filter lists */
1285         ixgbe_filterlist_init();
1286
1287         /* initialize bandwidth configuration info */
1288         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1289
1290         /* initialize Traffic Manager configuration */
1291         ixgbe_tm_conf_init(eth_dev);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1298 {
1299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301         struct ixgbe_hw *hw;
1302         int retries = 0;
1303         int ret;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308                 return 0;
1309
1310         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1311
1312         if (hw->adapter_stopped == 0)
1313                 ixgbe_dev_close(eth_dev);
1314
1315         eth_dev->dev_ops = NULL;
1316         eth_dev->rx_pkt_burst = NULL;
1317         eth_dev->tx_pkt_burst = NULL;
1318
1319         /* Unlock any pending hardware semaphore */
1320         ixgbe_swfw_lock_reset(hw);
1321
1322         /* disable uio intr before callback unregister */
1323         rte_intr_disable(intr_handle);
1324
1325         do {
1326                 ret = rte_intr_callback_unregister(intr_handle,
1327                                 ixgbe_dev_interrupt_handler, eth_dev);
1328                 if (ret >= 0) {
1329                         break;
1330                 } else if (ret != -EAGAIN) {
1331                         PMD_INIT_LOG(ERR,
1332                                 "intr callback unregister failed: %d",
1333                                 ret);
1334                         return ret;
1335                 }
1336                 rte_delay_ms(100);
1337         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1338
1339         /* uninitialize PF if max_vfs not zero */
1340         ixgbe_pf_host_uninit(eth_dev);
1341
1342         /* remove all the fdir filters & hash */
1343         ixgbe_fdir_filter_uninit(eth_dev);
1344
1345         /* remove all the L2 tunnel filters & hash */
1346         ixgbe_l2_tn_filter_uninit(eth_dev);
1347
1348         /* Remove all ntuple filters of the device */
1349         ixgbe_ntuple_filter_uninit(eth_dev);
1350
1351         /* clear all the filters list */
1352         ixgbe_filterlist_flush();
1353
1354         /* Remove all Traffic Manager configuration */
1355         ixgbe_tm_conf_uninit(eth_dev);
1356
1357 #ifdef RTE_LIBRTE_SECURITY
1358         rte_free(eth_dev->security_ctx);
1359 #endif
1360
1361         return 0;
1362 }
1363
1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1365 {
1366         struct ixgbe_filter_info *filter_info =
1367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1368         struct ixgbe_5tuple_filter *p_5tuple;
1369
1370         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1371                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1372                              p_5tuple,
1373                              entries);
1374                 rte_free(p_5tuple);
1375         }
1376         memset(filter_info->fivetuple_mask, 0,
1377                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1378
1379         return 0;
1380 }
1381
1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1383 {
1384         struct ixgbe_hw_fdir_info *fdir_info =
1385                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1386         struct ixgbe_fdir_filter *fdir_filter;
1387
1388                 if (fdir_info->hash_map)
1389                 rte_free(fdir_info->hash_map);
1390         if (fdir_info->hash_handle)
1391                 rte_hash_free(fdir_info->hash_handle);
1392
1393         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1394                 TAILQ_REMOVE(&fdir_info->fdir_list,
1395                              fdir_filter,
1396                              entries);
1397                 rte_free(fdir_filter);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_l2_tn_filter *l2_tn_filter;
1408
1409         if (l2_tn_info->hash_map)
1410                 rte_free(l2_tn_info->hash_map);
1411         if (l2_tn_info->hash_handle)
1412                 rte_hash_free(l2_tn_info->hash_handle);
1413
1414         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1415                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1416                              l2_tn_filter,
1417                              entries);
1418                 rte_free(l2_tn_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_hw_fdir_info *fdir_info =
1427                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1428         char fdir_hash_name[RTE_HASH_NAMESIZE];
1429         struct rte_hash_parameters fdir_hash_params = {
1430                 .name = fdir_hash_name,
1431                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1432                 .key_len = sizeof(union ixgbe_atr_input),
1433                 .hash_func = rte_hash_crc,
1434                 .hash_func_init_val = 0,
1435                 .socket_id = rte_socket_id(),
1436         };
1437
1438         TAILQ_INIT(&fdir_info->fdir_list);
1439         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1440                  "fdir_%s", eth_dev->device->name);
1441         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1442         if (!fdir_info->hash_handle) {
1443                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1444                 return -EINVAL;
1445         }
1446         fdir_info->hash_map = rte_zmalloc("ixgbe",
1447                                           sizeof(struct ixgbe_fdir_filter *) *
1448                                           IXGBE_MAX_FDIR_FILTER_NUM,
1449                                           0);
1450         if (!fdir_info->hash_map) {
1451                 PMD_INIT_LOG(ERR,
1452                              "Failed to allocate memory for fdir hash map!");
1453                 return -ENOMEM;
1454         }
1455         fdir_info->mask_added = FALSE;
1456
1457         return 0;
1458 }
1459
1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1461 {
1462         struct ixgbe_l2_tn_info *l2_tn_info =
1463                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1464         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1465         struct rte_hash_parameters l2_tn_hash_params = {
1466                 .name = l2_tn_hash_name,
1467                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1468                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1469                 .hash_func = rte_hash_crc,
1470                 .hash_func_init_val = 0,
1471                 .socket_id = rte_socket_id(),
1472         };
1473
1474         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1475         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1476                  "l2_tn_%s", eth_dev->device->name);
1477         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1478         if (!l2_tn_info->hash_handle) {
1479                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1480                 return -EINVAL;
1481         }
1482         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1483                                    sizeof(struct ixgbe_l2_tn_filter *) *
1484                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1485                                    0);
1486         if (!l2_tn_info->hash_map) {
1487                 PMD_INIT_LOG(ERR,
1488                         "Failed to allocate memory for L2 TN hash map!");
1489                 return -ENOMEM;
1490         }
1491         l2_tn_info->e_tag_en = FALSE;
1492         l2_tn_info->e_tag_fwd_en = FALSE;
1493         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1494
1495         return 0;
1496 }
1497 /*
1498  * Negotiate mailbox API version with the PF.
1499  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1500  * Then we try to negotiate starting with the most recent one.
1501  * If all negotiation attempts fail, then we will proceed with
1502  * the default one (ixgbe_mbox_api_10).
1503  */
1504 static void
1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1506 {
1507         int32_t i;
1508
1509         /* start with highest supported, proceed down */
1510         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1511                 ixgbe_mbox_api_12,
1512                 ixgbe_mbox_api_11,
1513                 ixgbe_mbox_api_10,
1514         };
1515
1516         for (i = 0;
1517                         i != RTE_DIM(sup_ver) &&
1518                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1519                         i++)
1520                 ;
1521 }
1522
1523 static void
1524 generate_random_mac_addr(struct ether_addr *mac_addr)
1525 {
1526         uint64_t random;
1527
1528         /* Set Organizationally Unique Identifier (OUI) prefix. */
1529         mac_addr->addr_bytes[0] = 0x00;
1530         mac_addr->addr_bytes[1] = 0x09;
1531         mac_addr->addr_bytes[2] = 0xC0;
1532         /* Force indication of locally assigned MAC address. */
1533         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1534         /* Generate the last 3 bytes of the MAC address with a random number. */
1535         random = rte_rand();
1536         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1537 }
1538
1539 /*
1540  * Virtual Function device init
1541  */
1542 static int
1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1544 {
1545         int diag;
1546         uint32_t tc, tcs;
1547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1549         struct ixgbe_hw *hw =
1550                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1551         struct ixgbe_vfta *shadow_vfta =
1552                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1553         struct ixgbe_hwstrip *hwstrip =
1554                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1555         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1556
1557         PMD_INIT_FUNC_TRACE();
1558
1559         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1560         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1561         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1562
1563         /* for secondary processes, we don't initialise any further as primary
1564          * has already done this work. Only check we don't need a different
1565          * RX function
1566          */
1567         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1568                 struct ixgbe_tx_queue *txq;
1569                 /* TX queue function in primary, set by last queue initialized
1570                  * Tx queue may not initialized by primary process
1571                  */
1572                 if (eth_dev->data->tx_queues) {
1573                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1574                         ixgbe_set_tx_function(eth_dev, txq);
1575                 } else {
1576                         /* Use default TX function if we get here */
1577                         PMD_INIT_LOG(NOTICE,
1578                                      "No TX queues configured yet. Using default TX function.");
1579                 }
1580
1581                 ixgbe_set_rx_function(eth_dev);
1582
1583                 return 0;
1584         }
1585
1586         rte_eth_copy_pci_info(eth_dev, pci_dev);
1587
1588         hw->device_id = pci_dev->id.device_id;
1589         hw->vendor_id = pci_dev->id.vendor_id;
1590         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1591
1592         /* initialize the vfta */
1593         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1594
1595         /* initialize the hw strip bitmap*/
1596         memset(hwstrip, 0, sizeof(*hwstrip));
1597
1598         /* Initialize the shared code (base driver) */
1599         diag = ixgbe_init_shared_code(hw);
1600         if (diag != IXGBE_SUCCESS) {
1601                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602                 return -EIO;
1603         }
1604
1605         /* init_mailbox_params */
1606         hw->mbx.ops.init_params(hw);
1607
1608         /* Reset the hw statistics */
1609         ixgbevf_dev_stats_reset(eth_dev);
1610
1611         /* Disable the interrupts for VF */
1612         ixgbevf_intr_disable(eth_dev);
1613
1614         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1615         diag = hw->mac.ops.reset_hw(hw);
1616
1617         /*
1618          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1619          * the underlying PF driver has not assigned a MAC address to the VF.
1620          * In this case, assign a random MAC address.
1621          */
1622         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1623                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624                 /*
1625                  * This error code will be propagated to the app by
1626                  * rte_eth_dev_reset, so use a public error code rather than
1627                  * the internal-only IXGBE_ERR_RESET_FAILED
1628                  */
1629                 return -EAGAIN;
1630         }
1631
1632         /* negotiate mailbox API version to use with the PF. */
1633         ixgbevf_negotiate_api(hw);
1634
1635         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1636         ixgbevf_get_queues(hw, &tcs, &tc);
1637
1638         /* Allocate memory for storing MAC addresses */
1639         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1640                                                hw->mac.num_rar_entries, 0);
1641         if (eth_dev->data->mac_addrs == NULL) {
1642                 PMD_INIT_LOG(ERR,
1643                              "Failed to allocate %u bytes needed to store "
1644                              "MAC addresses",
1645                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1646                 return -ENOMEM;
1647         }
1648
1649         /* Generate a random MAC address, if none was assigned by PF. */
1650         if (is_zero_ether_addr(perm_addr)) {
1651                 generate_random_mac_addr(perm_addr);
1652                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1653                 if (diag) {
1654                         rte_free(eth_dev->data->mac_addrs);
1655                         eth_dev->data->mac_addrs = NULL;
1656                         return diag;
1657                 }
1658                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1659                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1660                              "%02x:%02x:%02x:%02x:%02x:%02x",
1661                              perm_addr->addr_bytes[0],
1662                              perm_addr->addr_bytes[1],
1663                              perm_addr->addr_bytes[2],
1664                              perm_addr->addr_bytes[3],
1665                              perm_addr->addr_bytes[4],
1666                              perm_addr->addr_bytes[5]);
1667         }
1668
1669         /* Copy the permanent MAC address */
1670         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1671
1672         /* reset the hardware with the new settings */
1673         diag = hw->mac.ops.start_hw(hw);
1674         switch (diag) {
1675         case  0:
1676                 break;
1677
1678         default:
1679                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1680                 return -EIO;
1681         }
1682
1683         rte_intr_callback_register(intr_handle,
1684                                    ixgbevf_dev_interrupt_handler, eth_dev);
1685         rte_intr_enable(intr_handle);
1686         ixgbevf_intr_enable(eth_dev);
1687
1688         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1689                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1690                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1691
1692         return 0;
1693 }
1694
1695 /* Virtual Function device uninit */
1696
1697 static int
1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1699 {
1700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1701         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1702         struct ixgbe_hw *hw;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707                 return 0;
1708
1709         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1710
1711         if (hw->adapter_stopped == 0)
1712                 ixgbevf_dev_close(eth_dev);
1713
1714         eth_dev->dev_ops = NULL;
1715         eth_dev->rx_pkt_burst = NULL;
1716         eth_dev->tx_pkt_burst = NULL;
1717
1718         /* Disable the interrupts for VF */
1719         ixgbevf_intr_disable(eth_dev);
1720
1721         rte_intr_disable(intr_handle);
1722         rte_intr_callback_unregister(intr_handle,
1723                                      ixgbevf_dev_interrupt_handler, eth_dev);
1724
1725         return 0;
1726 }
1727
1728 static int
1729 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1730                 struct rte_pci_device *pci_dev)
1731 {
1732         char name[RTE_ETH_NAME_MAX_LEN];
1733         struct rte_eth_dev *pf_ethdev;
1734         struct rte_eth_devargs eth_da;
1735         int i, retval;
1736
1737         if (pci_dev->device.devargs) {
1738                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1739                                 &eth_da);
1740                 if (retval)
1741                         return retval;
1742         } else
1743                 memset(&eth_da, 0, sizeof(eth_da));
1744
1745         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1746                 sizeof(struct ixgbe_adapter),
1747                 eth_dev_pci_specific_init, pci_dev,
1748                 eth_ixgbe_dev_init, NULL);
1749
1750         if (retval || eth_da.nb_representor_ports < 1)
1751                 return retval;
1752
1753         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1754         if (pf_ethdev == NULL)
1755                 return -ENODEV;
1756
1757         /* probe VF representor ports */
1758         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1759                 struct ixgbe_vf_info *vfinfo;
1760                 struct ixgbe_vf_representor representor;
1761
1762                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1763                         pf_ethdev->data->dev_private);
1764                 if (vfinfo == NULL) {
1765                         PMD_DRV_LOG(ERR,
1766                                 "no virtual functions supported by PF");
1767                         break;
1768                 }
1769
1770                 representor.vf_id = eth_da.representor_ports[i];
1771                 representor.switch_domain_id = vfinfo->switch_domain_id;
1772                 representor.pf_ethdev = pf_ethdev;
1773
1774                 /* representor port net_bdf_port */
1775                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1776                         pci_dev->device.name,
1777                         eth_da.representor_ports[i]);
1778
1779                 retval = rte_eth_dev_create(&pci_dev->device, name,
1780                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1781                         ixgbe_vf_representor_init, &representor);
1782
1783                 if (retval)
1784                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1785                                 "representor %s.", name);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1792 {
1793         struct rte_eth_dev *ethdev;
1794
1795         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1796         if (!ethdev)
1797                 return -ENODEV;
1798
1799         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1800                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1801         else
1802                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1803 }
1804
1805 static struct rte_pci_driver rte_ixgbe_pmd = {
1806         .id_table = pci_id_ixgbe_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1808                      RTE_PCI_DRV_IOVA_AS_VA,
1809         .probe = eth_ixgbe_pci_probe,
1810         .remove = eth_ixgbe_pci_remove,
1811 };
1812
1813 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1814         struct rte_pci_device *pci_dev)
1815 {
1816         return rte_eth_dev_pci_generic_probe(pci_dev,
1817                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1818 }
1819
1820 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1821 {
1822         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1823 }
1824
1825 /*
1826  * virtual function driver struct
1827  */
1828 static struct rte_pci_driver rte_ixgbevf_pmd = {
1829         .id_table = pci_id_ixgbevf_map,
1830         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1831         .probe = eth_ixgbevf_pci_probe,
1832         .remove = eth_ixgbevf_pci_remove,
1833 };
1834
1835 static int
1836 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct ixgbe_vfta *shadow_vfta =
1841                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1842         uint32_t vfta;
1843         uint32_t vid_idx;
1844         uint32_t vid_bit;
1845
1846         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1847         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1848         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1849         if (on)
1850                 vfta |= vid_bit;
1851         else
1852                 vfta &= ~vid_bit;
1853         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1854
1855         /* update local VFTA copy */
1856         shadow_vfta->vfta[vid_idx] = vfta;
1857
1858         return 0;
1859 }
1860
1861 static void
1862 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1863 {
1864         if (on)
1865                 ixgbe_vlan_hw_strip_enable(dev, queue);
1866         else
1867                 ixgbe_vlan_hw_strip_disable(dev, queue);
1868 }
1869
1870 static int
1871 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1872                     enum rte_vlan_type vlan_type,
1873                     uint16_t tpid)
1874 {
1875         struct ixgbe_hw *hw =
1876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         int ret = 0;
1878         uint32_t reg;
1879         uint32_t qinq;
1880
1881         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1882         qinq &= IXGBE_DMATXCTL_GDV;
1883
1884         switch (vlan_type) {
1885         case ETH_VLAN_TYPE_INNER:
1886                 if (qinq) {
1887                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1889                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1890                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1892                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1893                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894                 } else {
1895                         ret = -ENOTSUP;
1896                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1897                                     " by single VLAN");
1898                 }
1899                 break;
1900         case ETH_VLAN_TYPE_OUTER:
1901                 if (qinq) {
1902                         /* Only the high 16-bits is valid */
1903                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1904                                         IXGBE_EXVET_VET_EXT_SHIFT);
1905                 } else {
1906                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1908                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1909                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1910                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1911                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1912                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1913                 }
1914
1915                 break;
1916         default:
1917                 ret = -EINVAL;
1918                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1919                 break;
1920         }
1921
1922         return ret;
1923 }
1924
1925 void
1926 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1927 {
1928         struct ixgbe_hw *hw =
1929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         uint32_t vlnctrl;
1931
1932         PMD_INIT_FUNC_TRACE();
1933
1934         /* Filter Table Disable */
1935         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1937
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1939 }
1940
1941 void
1942 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         struct ixgbe_vfta *shadow_vfta =
1947                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1948         uint32_t vlnctrl;
1949         uint16_t i;
1950
1951         PMD_INIT_FUNC_TRACE();
1952
1953         /* Filter Table Enable */
1954         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1955         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1956         vlnctrl |= IXGBE_VLNCTRL_VFE;
1957
1958         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1959
1960         /* write whatever is in local vfta copy */
1961         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1962                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1967 {
1968         struct ixgbe_hwstrip *hwstrip =
1969                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1970         struct ixgbe_rx_queue *rxq;
1971
1972         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1973                 return;
1974
1975         if (on)
1976                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1977         else
1978                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1979
1980         if (queue >= dev->data->nb_rx_queues)
1981                 return;
1982
1983         rxq = dev->data->rx_queues[queue];
1984
1985         if (on) {
1986                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1987                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1988         } else {
1989                 rxq->vlan_flags = PKT_RX_VLAN;
1990                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1991         }
1992 }
1993
1994 static void
1995 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1996 {
1997         struct ixgbe_hw *hw =
1998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999         uint32_t ctrl;
2000
2001         PMD_INIT_FUNC_TRACE();
2002
2003         if (hw->mac.type == ixgbe_mac_82598EB) {
2004                 /* No queue level support */
2005                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006                 return;
2007         }
2008
2009         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2010         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2011         ctrl &= ~IXGBE_RXDCTL_VME;
2012         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2013
2014         /* record those setting for HW strip per queue */
2015         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2016 }
2017
2018 static void
2019 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2020 {
2021         struct ixgbe_hw *hw =
2022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint32_t ctrl;
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         if (hw->mac.type == ixgbe_mac_82598EB) {
2028                 /* No queue level supported */
2029                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2030                 return;
2031         }
2032
2033         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2035         ctrl |= IXGBE_RXDCTL_VME;
2036         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2037
2038         /* record those setting for HW strip per queue */
2039         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2040 }
2041
2042 static void
2043 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2044 {
2045         struct ixgbe_hw *hw =
2046                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047         uint32_t ctrl;
2048
2049         PMD_INIT_FUNC_TRACE();
2050
2051         /* DMATXCTRL: Geric Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2053         ctrl &= ~IXGBE_DMATXCTL_GDV;
2054         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2055
2056         /* CTRL_EXT: Global Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2058         ctrl &= ~IXGBE_EXTENDED_VLAN;
2059         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2060
2061 }
2062
2063 static void
2064 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         uint32_t ctrl;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         /* DMATXCTRL: Geric Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074         ctrl |= IXGBE_DMATXCTL_GDV;
2075         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076
2077         /* CTRL_EXT: Global Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079         ctrl |= IXGBE_EXTENDED_VLAN;
2080         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2081
2082         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2083         if (hw->mac.type == ixgbe_mac_X550 ||
2084             hw->mac.type == ixgbe_mac_X550EM_x ||
2085             hw->mac.type == ixgbe_mac_X550EM_a) {
2086                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2087                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2088                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2089         }
2090
2091         /*
2092          * VET EXT field in the EXVET register = 0x8100 by default
2093          * So no need to change. Same to VT field of DMATXCTL register
2094          */
2095 }
2096
2097 void
2098 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2099 {
2100         struct ixgbe_hw *hw =
2101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2103         uint32_t ctrl;
2104         uint16_t i;
2105         struct ixgbe_rx_queue *rxq;
2106         bool on;
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         if (hw->mac.type == ixgbe_mac_82598EB) {
2111                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2112                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113                         ctrl |= IXGBE_VLNCTRL_VME;
2114                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2115                 } else {
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2117                         ctrl &= ~IXGBE_VLNCTRL_VME;
2118                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2119                 }
2120         } else {
2121                 /*
2122                  * Other 10G NIC, the VLAN strip can be setup
2123                  * per queue in RXDCTL
2124                  */
2125                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2126                         rxq = dev->data->rx_queues[i];
2127                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2128                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2129                                 ctrl |= IXGBE_RXDCTL_VME;
2130                                 on = TRUE;
2131                         } else {
2132                                 ctrl &= ~IXGBE_RXDCTL_VME;
2133                                 on = FALSE;
2134                         }
2135                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2136
2137                         /* record those setting for HW strip per queue */
2138                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2139                 }
2140         }
2141 }
2142
2143 static void
2144 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2145 {
2146         uint16_t i;
2147         struct rte_eth_rxmode *rxmode;
2148         struct ixgbe_rx_queue *rxq;
2149
2150         if (mask & ETH_VLAN_STRIP_MASK) {
2151                 rxmode = &dev->data->dev_conf.rxmode;
2152                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157                 else
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162         }
2163 }
2164
2165 static int
2166 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2167 {
2168         struct rte_eth_rxmode *rxmode;
2169         rxmode = &dev->data->dev_conf.rxmode;
2170
2171         if (mask & ETH_VLAN_STRIP_MASK) {
2172                 ixgbe_vlan_hw_strip_config(dev);
2173         }
2174
2175         if (mask & ETH_VLAN_FILTER_MASK) {
2176                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2177                         ixgbe_vlan_hw_filter_enable(dev);
2178                 else
2179                         ixgbe_vlan_hw_filter_disable(dev);
2180         }
2181
2182         if (mask & ETH_VLAN_EXTEND_MASK) {
2183                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2184                         ixgbe_vlan_hw_extend_enable(dev);
2185                 else
2186                         ixgbe_vlan_hw_extend_disable(dev);
2187         }
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2194 {
2195         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2196
2197         ixgbe_vlan_offload_config(dev, mask);
2198
2199         return 0;
2200 }
2201
2202 static void
2203 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2204 {
2205         struct ixgbe_hw *hw =
2206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2208         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2209
2210         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2211         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2212 }
2213
2214 static int
2215 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2216 {
2217         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2218
2219         switch (nb_rx_q) {
2220         case 1:
2221         case 2:
2222                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2223                 break;
2224         case 4:
2225                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2226                 break;
2227         default:
2228                 return -EINVAL;
2229         }
2230
2231         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2232                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2233         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2234                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2235         return 0;
2236 }
2237
2238 static int
2239 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2240 {
2241         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2244         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2245
2246         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2247                 /* check multi-queue mode */
2248                 switch (dev_conf->rxmode.mq_mode) {
2249                 case ETH_MQ_RX_VMDQ_DCB:
2250                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2251                         break;
2252                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2253                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2254                         PMD_INIT_LOG(ERR, "SRIOV active,"
2255                                         " unsupported mq_mode rx %d.",
2256                                         dev_conf->rxmode.mq_mode);
2257                         return -EINVAL;
2258                 case ETH_MQ_RX_RSS:
2259                 case ETH_MQ_RX_VMDQ_RSS:
2260                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2261                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2262                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2263                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2264                                                 " invalid queue number"
2265                                                 " for VMDQ RSS, allowed"
2266                                                 " value are 1, 2 or 4.");
2267                                         return -EINVAL;
2268                                 }
2269                         break;
2270                 case ETH_MQ_RX_VMDQ_ONLY:
2271                 case ETH_MQ_RX_NONE:
2272                         /* if nothing mq mode configure, use default scheme */
2273                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2274                         break;
2275                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2276                         /* SRIOV only works in VMDq enable mode */
2277                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2278                                         " wrong mq_mode rx %d.",
2279                                         dev_conf->rxmode.mq_mode);
2280                         return -EINVAL;
2281                 }
2282
2283                 switch (dev_conf->txmode.mq_mode) {
2284                 case ETH_MQ_TX_VMDQ_DCB:
2285                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2286                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2287                         break;
2288                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2289                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2290                         break;
2291                 }
2292
2293                 /* check valid queue number */
2294                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2295                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2296                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2297                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2298                                         " must be less than or equal to %d.",
2299                                         nb_rx_q, nb_tx_q,
2300                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2301                         return -EINVAL;
2302                 }
2303         } else {
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2305                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2306                                           " not supported.");
2307                         return -EINVAL;
2308                 }
2309                 /* check configuration for vmdb+dcb mode */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2311                         const struct rte_eth_vmdq_dcb_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2315                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2319                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2320                                conf->nb_queue_pools == ETH_32_POOLS)) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2322                                                 " nb_queue_pools must be %d or %d.",
2323                                                 ETH_16_POOLS, ETH_32_POOLS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2328                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2329
2330                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2332                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2333                                 return -EINVAL;
2334                         }
2335                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2336                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2337                                conf->nb_queue_pools == ETH_32_POOLS)) {
2338                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2339                                                 " nb_queue_pools != %d and"
2340                                                 " nb_queue_pools != %d.",
2341                                                 ETH_16_POOLS, ETH_32_POOLS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /* For DCB mode check our configuration before we go further */
2347                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2348                         const struct rte_eth_dcb_rx_conf *conf;
2349
2350                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2351                         if (!(conf->nb_tcs == ETH_4_TCS ||
2352                                conf->nb_tcs == ETH_8_TCS)) {
2353                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2354                                                 " and nb_tcs != %d.",
2355                                                 ETH_4_TCS, ETH_8_TCS);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359
2360                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2361                         const struct rte_eth_dcb_tx_conf *conf;
2362
2363                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2364                         if (!(conf->nb_tcs == ETH_4_TCS ||
2365                                conf->nb_tcs == ETH_8_TCS)) {
2366                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2367                                                 " and nb_tcs != %d.",
2368                                                 ETH_4_TCS, ETH_8_TCS);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372
2373                 /*
2374                  * When DCB/VT is off, maximum number of queues changes,
2375                  * except for 82598EB, which remains constant.
2376                  */
2377                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2378                                 hw->mac.type != ixgbe_mac_82598EB) {
2379                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2380                                 PMD_INIT_LOG(ERR,
2381                                              "Neither VT nor DCB are enabled, "
2382                                              "nb_tx_q > %d.",
2383                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2384                                 return -EINVAL;
2385                         }
2386                 }
2387         }
2388         return 0;
2389 }
2390
2391 static int
2392 ixgbe_dev_configure(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         struct ixgbe_adapter *adapter =
2397                 (struct ixgbe_adapter *)dev->data->dev_private;
2398         int ret;
2399
2400         PMD_INIT_FUNC_TRACE();
2401         /* multipe queue mode checking */
2402         ret  = ixgbe_check_mq_mode(dev);
2403         if (ret != 0) {
2404                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2405                             ret);
2406                 return ret;
2407         }
2408
2409         /* set flag to update link status after init */
2410         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2411
2412         /*
2413          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2414          * allocation or vector Rx preconditions we will reset it.
2415          */
2416         adapter->rx_bulk_alloc_allowed = true;
2417         adapter->rx_vec_allowed = true;
2418
2419         return 0;
2420 }
2421
2422 static void
2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2424 {
2425         struct ixgbe_hw *hw =
2426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427         struct ixgbe_interrupt *intr =
2428                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2429         uint32_t gpie;
2430
2431         /* only set up it on X550EM_X */
2432         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2433                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2434                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2435                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2436                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2437                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2438         }
2439 }
2440
2441 int
2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2443                         uint16_t tx_rate, uint64_t q_msk)
2444 {
2445         struct ixgbe_hw *hw;
2446         struct ixgbe_vf_info *vfinfo;
2447         struct rte_eth_link link;
2448         uint8_t  nb_q_per_pool;
2449         uint32_t queue_stride;
2450         uint32_t queue_idx, idx = 0, vf_idx;
2451         uint32_t queue_end;
2452         uint16_t total_rate = 0;
2453         struct rte_pci_device *pci_dev;
2454
2455         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2456         rte_eth_link_get_nowait(dev->data->port_id, &link);
2457
2458         if (vf >= pci_dev->max_vfs)
2459                 return -EINVAL;
2460
2461         if (tx_rate > link.link_speed)
2462                 return -EINVAL;
2463
2464         if (q_msk == 0)
2465                 return 0;
2466
2467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2469         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2470         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2471         queue_idx = vf * queue_stride;
2472         queue_end = queue_idx + nb_q_per_pool - 1;
2473         if (queue_end >= hw->mac.max_tx_queues)
2474                 return -EINVAL;
2475
2476         if (vfinfo) {
2477                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2478                         if (vf_idx == vf)
2479                                 continue;
2480                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2481                                 idx++)
2482                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2483                 }
2484         } else {
2485                 return -EINVAL;
2486         }
2487
2488         /* Store tx_rate for this vf. */
2489         for (idx = 0; idx < nb_q_per_pool; idx++) {
2490                 if (((uint64_t)0x1 << idx) & q_msk) {
2491                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2492                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2493                         total_rate += tx_rate;
2494                 }
2495         }
2496
2497         if (total_rate > dev->data->dev_link.link_speed) {
2498                 /* Reset stored TX rate of the VF if it causes exceed
2499                  * link speed.
2500                  */
2501                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2502                 return -EINVAL;
2503         }
2504
2505         /* Set RTTBCNRC of each queue/pool for vf X  */
2506         for (; queue_idx <= queue_end; queue_idx++) {
2507                 if (0x1 & q_msk)
2508                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2509                 q_msk = q_msk >> 1;
2510         }
2511
2512         return 0;
2513 }
2514
2515 /*
2516  * Configure device link speed and setup link.
2517  * It returns 0 on success.
2518  */
2519 static int
2520 ixgbe_dev_start(struct rte_eth_dev *dev)
2521 {
2522         struct ixgbe_hw *hw =
2523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         struct ixgbe_vf_info *vfinfo =
2525                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2528         uint32_t intr_vector = 0;
2529         int err, link_up = 0, negotiate = 0;
2530         uint32_t speed = 0;
2531         uint32_t allowed_speeds = 0;
2532         int mask = 0;
2533         int status;
2534         uint16_t vf, idx;
2535         uint32_t *link_speeds;
2536         struct ixgbe_tm_conf *tm_conf =
2537                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2538
2539         PMD_INIT_FUNC_TRACE();
2540
2541         /* IXGBE devices don't support:
2542         *    - half duplex (checked afterwards for valid speeds)
2543         *    - fixed speed: TODO implement
2544         */
2545         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2546                 PMD_INIT_LOG(ERR,
2547                 "Invalid link_speeds for port %u, fix speed not supported",
2548                                 dev->data->port_id);
2549                 return -EINVAL;
2550         }
2551
2552         /* disable uio/vfio intr/eventfd mapping */
2553         rte_intr_disable(intr_handle);
2554
2555         /* stop adapter */
2556         hw->adapter_stopped = 0;
2557         ixgbe_stop_adapter(hw);
2558
2559         /* reinitialize adapter
2560          * this calls reset and start
2561          */
2562         status = ixgbe_pf_reset_hw(hw);
2563         if (status != 0)
2564                 return -1;
2565         hw->mac.ops.start_hw(hw);
2566         hw->mac.get_link_status = true;
2567
2568         /* configure PF module if SRIOV enabled */
2569         ixgbe_pf_host_configure(dev);
2570
2571         ixgbe_dev_phy_intr_setup(dev);
2572
2573         /* check and configure queue intr-vector mapping */
2574         if ((rte_intr_cap_multiple(intr_handle) ||
2575              !RTE_ETH_DEV_SRIOV(dev).active) &&
2576             dev->data->dev_conf.intr_conf.rxq != 0) {
2577                 intr_vector = dev->data->nb_rx_queues;
2578                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2579                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2580                                         IXGBE_MAX_INTR_QUEUE_NUM);
2581                         return -ENOTSUP;
2582                 }
2583                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2584                         return -1;
2585         }
2586
2587         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2588                 intr_handle->intr_vec =
2589                         rte_zmalloc("intr_vec",
2590                                     dev->data->nb_rx_queues * sizeof(int), 0);
2591                 if (intr_handle->intr_vec == NULL) {
2592                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2593                                      " intr_vec", dev->data->nb_rx_queues);
2594                         return -ENOMEM;
2595                 }
2596         }
2597
2598         /* confiugre msix for sleep until rx interrupt */
2599         ixgbe_configure_msix(dev);
2600
2601         /* initialize transmission unit */
2602         ixgbe_dev_tx_init(dev);
2603
2604         /* This can fail when allocating mbufs for descriptor rings */
2605         err = ixgbe_dev_rx_init(dev);
2606         if (err) {
2607                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2608                 goto error;
2609         }
2610
2611         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2612                 ETH_VLAN_EXTEND_MASK;
2613         err = ixgbe_vlan_offload_config(dev, mask);
2614         if (err) {
2615                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2616                 goto error;
2617         }
2618
2619         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2620                 /* Enable vlan filtering for VMDq */
2621                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2622         }
2623
2624         /* Configure DCB hw */
2625         ixgbe_configure_dcb(dev);
2626
2627         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2628                 err = ixgbe_fdir_configure(dev);
2629                 if (err)
2630                         goto error;
2631         }
2632
2633         /* Restore vf rate limit */
2634         if (vfinfo != NULL) {
2635                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2636                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2637                                 if (vfinfo[vf].tx_rate[idx] != 0)
2638                                         ixgbe_set_vf_rate_limit(
2639                                                 dev, vf,
2640                                                 vfinfo[vf].tx_rate[idx],
2641                                                 1 << idx);
2642         }
2643
2644         ixgbe_restore_statistics_mapping(dev);
2645
2646         err = ixgbe_dev_rxtx_start(dev);
2647         if (err < 0) {
2648                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2649                 goto error;
2650         }
2651
2652         /* Skip link setup if loopback mode is enabled for 82599. */
2653         if (hw->mac.type == ixgbe_mac_82599EB &&
2654                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2655                 goto skip_link_setup;
2656
2657         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2658                 err = hw->mac.ops.setup_sfp(hw);
2659                 if (err)
2660                         goto error;
2661         }
2662
2663         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2664                 /* Turn on the copper */
2665                 ixgbe_set_phy_power(hw, true);
2666         } else {
2667                 /* Turn on the laser */
2668                 ixgbe_enable_tx_laser(hw);
2669         }
2670
2671         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2672         if (err)
2673                 goto error;
2674         dev->data->dev_link.link_status = link_up;
2675
2676         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2677         if (err)
2678                 goto error;
2679
2680         switch (hw->mac.type) {
2681         case ixgbe_mac_X550:
2682         case ixgbe_mac_X550EM_x:
2683         case ixgbe_mac_X550EM_a:
2684                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2685                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2686                         ETH_LINK_SPEED_10G;
2687                 break;
2688         default:
2689                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2690                         ETH_LINK_SPEED_10G;
2691         }
2692
2693         link_speeds = &dev->data->dev_conf.link_speeds;
2694         if (*link_speeds & ~allowed_speeds) {
2695                 PMD_INIT_LOG(ERR, "Invalid link setting");
2696                 goto error;
2697         }
2698
2699         speed = 0x0;
2700         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2701                 switch (hw->mac.type) {
2702                 case ixgbe_mac_82598EB:
2703                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2704                         break;
2705                 case ixgbe_mac_82599EB:
2706                 case ixgbe_mac_X540:
2707                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2708                         break;
2709                 case ixgbe_mac_X550:
2710                 case ixgbe_mac_X550EM_x:
2711                 case ixgbe_mac_X550EM_a:
2712                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2713                         break;
2714                 default:
2715                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2716                 }
2717         } else {
2718                 if (*link_speeds & ETH_LINK_SPEED_10G)
2719                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2720                 if (*link_speeds & ETH_LINK_SPEED_5G)
2721                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2722                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2723                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2724                 if (*link_speeds & ETH_LINK_SPEED_1G)
2725                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2726                 if (*link_speeds & ETH_LINK_SPEED_100M)
2727                         speed |= IXGBE_LINK_SPEED_100_FULL;
2728         }
2729
2730         err = ixgbe_setup_link(hw, speed, link_up);
2731         if (err)
2732                 goto error;
2733
2734         ixgbe_dev_link_update(dev, 0);
2735
2736 skip_link_setup:
2737
2738         if (rte_intr_allow_others(intr_handle)) {
2739                 /* check if lsc interrupt is enabled */
2740                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2741                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2742                 else
2743                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2744                 ixgbe_dev_macsec_interrupt_setup(dev);
2745         } else {
2746                 rte_intr_callback_unregister(intr_handle,
2747                                              ixgbe_dev_interrupt_handler, dev);
2748                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2749                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2750                                      " no intr multiplex");
2751         }
2752
2753         /* check if rxq interrupt is enabled */
2754         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2755             rte_intr_dp_is_en(intr_handle))
2756                 ixgbe_dev_rxq_interrupt_setup(dev);
2757
2758         /* enable uio/vfio intr/eventfd mapping */
2759         rte_intr_enable(intr_handle);
2760
2761         /* resume enabled intr since hw reset */
2762         ixgbe_enable_intr(dev);
2763         ixgbe_l2_tunnel_conf(dev);
2764         ixgbe_filter_restore(dev);
2765
2766         if (tm_conf->root && !tm_conf->committed)
2767                 PMD_DRV_LOG(WARNING,
2768                             "please call hierarchy_commit() "
2769                             "before starting the port");
2770
2771         return 0;
2772
2773 error:
2774         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2775         ixgbe_dev_clear_queues(dev);
2776         return -EIO;
2777 }
2778
2779 /*
2780  * Stop device: disable rx and tx functions to allow for reconfiguring.
2781  */
2782 static void
2783 ixgbe_dev_stop(struct rte_eth_dev *dev)
2784 {
2785         struct rte_eth_link link;
2786         struct ixgbe_hw *hw =
2787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788         struct ixgbe_vf_info *vfinfo =
2789                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2790         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2791         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2792         int vf;
2793         struct ixgbe_tm_conf *tm_conf =
2794                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2795
2796         PMD_INIT_FUNC_TRACE();
2797
2798         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2799
2800         /* disable interrupts */
2801         ixgbe_disable_intr(hw);
2802
2803         /* reset the NIC */
2804         ixgbe_pf_reset_hw(hw);
2805         hw->adapter_stopped = 0;
2806
2807         /* stop adapter */
2808         ixgbe_stop_adapter(hw);
2809
2810         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2811                 vfinfo[vf].clear_to_send = false;
2812
2813         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2814                 /* Turn off the copper */
2815                 ixgbe_set_phy_power(hw, false);
2816         } else {
2817                 /* Turn off the laser */
2818                 ixgbe_disable_tx_laser(hw);
2819         }
2820
2821         ixgbe_dev_clear_queues(dev);
2822
2823         /* Clear stored conf */
2824         dev->data->scattered_rx = 0;
2825         dev->data->lro = 0;
2826
2827         /* Clear recorded link status */
2828         memset(&link, 0, sizeof(link));
2829         rte_eth_linkstatus_set(dev, &link);
2830
2831         if (!rte_intr_allow_others(intr_handle))
2832                 /* resume to the default handler */
2833                 rte_intr_callback_register(intr_handle,
2834                                            ixgbe_dev_interrupt_handler,
2835                                            (void *)dev);
2836
2837         /* Clean datapath event and queue/vec mapping */
2838         rte_intr_efd_disable(intr_handle);
2839         if (intr_handle->intr_vec != NULL) {
2840                 rte_free(intr_handle->intr_vec);
2841                 intr_handle->intr_vec = NULL;
2842         }
2843
2844         /* reset hierarchy commit */
2845         tm_conf->committed = false;
2846 }
2847
2848 /*
2849  * Set device link up: enable tx.
2850  */
2851 static int
2852 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2853 {
2854         struct ixgbe_hw *hw =
2855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856         if (hw->mac.type == ixgbe_mac_82599EB) {
2857 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2858                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2859                         /* Not suported in bypass mode */
2860                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2861                                      "by device id 0x%x", hw->device_id);
2862                         return -ENOTSUP;
2863                 }
2864 #endif
2865         }
2866
2867         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2868                 /* Turn on the copper */
2869                 ixgbe_set_phy_power(hw, true);
2870         } else {
2871                 /* Turn on the laser */
2872                 ixgbe_enable_tx_laser(hw);
2873         }
2874
2875         return 0;
2876 }
2877
2878 /*
2879  * Set device link down: disable tx.
2880  */
2881 static int
2882 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2883 {
2884         struct ixgbe_hw *hw =
2885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886         if (hw->mac.type == ixgbe_mac_82599EB) {
2887 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2888                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2889                         /* Not suported in bypass mode */
2890                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2891                                      "by device id 0x%x", hw->device_id);
2892                         return -ENOTSUP;
2893                 }
2894 #endif
2895         }
2896
2897         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2898                 /* Turn off the copper */
2899                 ixgbe_set_phy_power(hw, false);
2900         } else {
2901                 /* Turn off the laser */
2902                 ixgbe_disable_tx_laser(hw);
2903         }
2904
2905         return 0;
2906 }
2907
2908 /*
2909  * Reset and stop device.
2910  */
2911 static void
2912 ixgbe_dev_close(struct rte_eth_dev *dev)
2913 {
2914         struct ixgbe_hw *hw =
2915                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916
2917         PMD_INIT_FUNC_TRACE();
2918
2919         ixgbe_pf_reset_hw(hw);
2920
2921         ixgbe_dev_stop(dev);
2922         hw->adapter_stopped = 1;
2923
2924         ixgbe_dev_free_queues(dev);
2925
2926         ixgbe_disable_pcie_master(hw);
2927
2928         /* reprogram the RAR[0] in case user changed it. */
2929         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2930 }
2931
2932 /*
2933  * Reset PF device.
2934  */
2935 static int
2936 ixgbe_dev_reset(struct rte_eth_dev *dev)
2937 {
2938         int ret;
2939
2940         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2941          * its VF to make them align with it. The detailed notification
2942          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2943          * To avoid unexpected behavior in VF, currently reset of PF with
2944          * SR-IOV activation is not supported. It might be supported later.
2945          */
2946         if (dev->data->sriov.active)
2947                 return -ENOTSUP;
2948
2949         ret = eth_ixgbe_dev_uninit(dev);
2950         if (ret)
2951                 return ret;
2952
2953         ret = eth_ixgbe_dev_init(dev, NULL);
2954
2955         return ret;
2956 }
2957
2958 static void
2959 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2960                            struct ixgbe_hw_stats *hw_stats,
2961                            struct ixgbe_macsec_stats *macsec_stats,
2962                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2963                            uint64_t *total_qprc, uint64_t *total_qprdc)
2964 {
2965         uint32_t bprc, lxon, lxoff, total;
2966         uint32_t delta_gprc = 0;
2967         unsigned i;
2968         /* Workaround for RX byte count not including CRC bytes when CRC
2969          * strip is enabled. CRC bytes are removed from counters when crc_strip
2970          * is disabled.
2971          */
2972         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2973                         IXGBE_HLREG0_RXCRCSTRP);
2974
2975         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2976         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2977         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2978         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2979
2980         for (i = 0; i < 8; i++) {
2981                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2982
2983                 /* global total per queue */
2984                 hw_stats->mpc[i] += mp;
2985                 /* Running comprehensive total for stats display */
2986                 *total_missed_rx += hw_stats->mpc[i];
2987                 if (hw->mac.type == ixgbe_mac_82598EB) {
2988                         hw_stats->rnbc[i] +=
2989                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2990                         hw_stats->pxonrxc[i] +=
2991                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2992                         hw_stats->pxoffrxc[i] +=
2993                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2994                 } else {
2995                         hw_stats->pxonrxc[i] +=
2996                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2997                         hw_stats->pxoffrxc[i] +=
2998                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2999                         hw_stats->pxon2offc[i] +=
3000                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3001                 }
3002                 hw_stats->pxontxc[i] +=
3003                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3004                 hw_stats->pxofftxc[i] +=
3005                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3006         }
3007         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3008                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3009                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3010                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3011
3012                 delta_gprc += delta_qprc;
3013
3014                 hw_stats->qprc[i] += delta_qprc;
3015                 hw_stats->qptc[i] += delta_qptc;
3016
3017                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3018                 hw_stats->qbrc[i] +=
3019                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3020                 if (crc_strip == 0)
3021                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3022
3023                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3024                 hw_stats->qbtc[i] +=
3025                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3026
3027                 hw_stats->qprdc[i] += delta_qprdc;
3028                 *total_qprdc += hw_stats->qprdc[i];
3029
3030                 *total_qprc += hw_stats->qprc[i];
3031                 *total_qbrc += hw_stats->qbrc[i];
3032         }
3033         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3034         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3035         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3036
3037         /*
3038          * An errata states that gprc actually counts good + missed packets:
3039          * Workaround to set gprc to summated queue packet receives
3040          */
3041         hw_stats->gprc = *total_qprc;
3042
3043         if (hw->mac.type != ixgbe_mac_82598EB) {
3044                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3045                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3046                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3047                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3048                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3049                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3050                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3051                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3052         } else {
3053                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3054                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3055                 /* 82598 only has a counter in the high register */
3056                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3057                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3058                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3059         }
3060         uint64_t old_tpr = hw_stats->tpr;
3061
3062         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3063         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3064
3065         if (crc_strip == 0)
3066                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3067
3068         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3069         hw_stats->gptc += delta_gptc;
3070         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3071         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3072
3073         /*
3074          * Workaround: mprc hardware is incorrectly counting
3075          * broadcasts, so for now we subtract those.
3076          */
3077         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3078         hw_stats->bprc += bprc;
3079         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3080         if (hw->mac.type == ixgbe_mac_82598EB)
3081                 hw_stats->mprc -= bprc;
3082
3083         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3084         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3085         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3086         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3087         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3088         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3089
3090         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3091         hw_stats->lxontxc += lxon;
3092         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3093         hw_stats->lxofftxc += lxoff;
3094         total = lxon + lxoff;
3095
3096         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3097         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3098         hw_stats->gptc -= total;
3099         hw_stats->mptc -= total;
3100         hw_stats->ptc64 -= total;
3101         hw_stats->gotc -= total * ETHER_MIN_LEN;
3102
3103         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3104         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3105         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3106         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3107         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3108         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3109         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3110         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3111         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3112         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3113         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3114         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3115         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3116         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3117         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3118         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3119         /* Only read FCOE on 82599 */
3120         if (hw->mac.type != ixgbe_mac_82598EB) {
3121                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3122                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3123                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3124                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3125                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3126         }
3127
3128         /* Flow Director Stats registers */
3129         if (hw->mac.type != ixgbe_mac_82598EB) {
3130                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3131                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3132                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3133                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3134                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3135                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3136                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3137                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3138                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3139                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3140         }
3141         /* MACsec Stats registers */
3142         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3143         macsec_stats->out_pkts_encrypted +=
3144                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3145         macsec_stats->out_pkts_protected +=
3146                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3147         macsec_stats->out_octets_encrypted +=
3148                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3149         macsec_stats->out_octets_protected +=
3150                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3151         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3152         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3153         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3154         macsec_stats->in_pkts_unknownsci +=
3155                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3156         macsec_stats->in_octets_decrypted +=
3157                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3158         macsec_stats->in_octets_validated +=
3159                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3160         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3161         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3162         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3163         for (i = 0; i < 2; i++) {
3164                 macsec_stats->in_pkts_ok +=
3165                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3166                 macsec_stats->in_pkts_invalid +=
3167                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3168                 macsec_stats->in_pkts_notvalid +=
3169                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3170         }
3171         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3172         macsec_stats->in_pkts_notusingsa +=
3173                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3174 }
3175
3176 /*
3177  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3178  */
3179 static int
3180 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3181 {
3182         struct ixgbe_hw *hw =
3183                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184         struct ixgbe_hw_stats *hw_stats =
3185                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3186         struct ixgbe_macsec_stats *macsec_stats =
3187                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3188                                 dev->data->dev_private);
3189         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3190         unsigned i;
3191
3192         total_missed_rx = 0;
3193         total_qbrc = 0;
3194         total_qprc = 0;
3195         total_qprdc = 0;
3196
3197         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3198                         &total_qbrc, &total_qprc, &total_qprdc);
3199
3200         if (stats == NULL)
3201                 return -EINVAL;
3202
3203         /* Fill out the rte_eth_stats statistics structure */
3204         stats->ipackets = total_qprc;
3205         stats->ibytes = total_qbrc;
3206         stats->opackets = hw_stats->gptc;
3207         stats->obytes = hw_stats->gotc;
3208
3209         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3210                 stats->q_ipackets[i] = hw_stats->qprc[i];
3211                 stats->q_opackets[i] = hw_stats->qptc[i];
3212                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3213                 stats->q_obytes[i] = hw_stats->qbtc[i];
3214                 stats->q_errors[i] = hw_stats->qprdc[i];
3215         }
3216
3217         /* Rx Errors */
3218         stats->imissed  = total_missed_rx;
3219         stats->ierrors  = hw_stats->crcerrs +
3220                           hw_stats->mspdc +
3221                           hw_stats->rlec +
3222                           hw_stats->ruc +
3223                           hw_stats->roc +
3224                           hw_stats->illerrc +
3225                           hw_stats->errbc +
3226                           hw_stats->rfc +
3227                           hw_stats->fccrc +
3228                           hw_stats->fclast;
3229
3230         /* Tx Errors */
3231         stats->oerrors  = 0;
3232         return 0;
3233 }
3234
3235 static void
3236 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3237 {
3238         struct ixgbe_hw_stats *stats =
3239                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3240
3241         /* HW registers are cleared on read */
3242         ixgbe_dev_stats_get(dev, NULL);
3243
3244         /* Reset software totals */
3245         memset(stats, 0, sizeof(*stats));
3246 }
3247
3248 /* This function calculates the number of xstats based on the current config */
3249 static unsigned
3250 ixgbe_xstats_calc_num(void) {
3251         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3252                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3253                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3254 }
3255
3256 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3257         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3258 {
3259         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3260         unsigned stat, i, count;
3261
3262         if (xstats_names != NULL) {
3263                 count = 0;
3264
3265                 /* Note: limit >= cnt_stats checked upstream
3266                  * in rte_eth_xstats_names()
3267                  */
3268
3269                 /* Extended stats from ixgbe_hw_stats */
3270                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3271                         snprintf(xstats_names[count].name,
3272                                 sizeof(xstats_names[count].name),
3273                                 "%s",
3274                                 rte_ixgbe_stats_strings[i].name);
3275                         count++;
3276                 }
3277
3278                 /* MACsec Stats */
3279                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3280                         snprintf(xstats_names[count].name,
3281                                 sizeof(xstats_names[count].name),
3282                                 "%s",
3283                                 rte_ixgbe_macsec_strings[i].name);
3284                         count++;
3285                 }
3286
3287                 /* RX Priority Stats */
3288                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3289                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3290                                 snprintf(xstats_names[count].name,
3291                                         sizeof(xstats_names[count].name),
3292                                         "rx_priority%u_%s", i,
3293                                         rte_ixgbe_rxq_strings[stat].name);
3294                                 count++;
3295                         }
3296                 }
3297
3298                 /* TX Priority Stats */
3299                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3300                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3301                                 snprintf(xstats_names[count].name,
3302                                         sizeof(xstats_names[count].name),
3303                                         "tx_priority%u_%s", i,
3304                                         rte_ixgbe_txq_strings[stat].name);
3305                                 count++;
3306                         }
3307                 }
3308         }
3309         return cnt_stats;
3310 }
3311
3312 static int ixgbe_dev_xstats_get_names_by_id(
3313         struct rte_eth_dev *dev,
3314         struct rte_eth_xstat_name *xstats_names,
3315         const uint64_t *ids,
3316         unsigned int limit)
3317 {
3318         if (!ids) {
3319                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3320                 unsigned int stat, i, count;
3321
3322                 if (xstats_names != NULL) {
3323                         count = 0;
3324
3325                         /* Note: limit >= cnt_stats checked upstream
3326                          * in rte_eth_xstats_names()
3327                          */
3328
3329                         /* Extended stats from ixgbe_hw_stats */
3330                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3331                                 snprintf(xstats_names[count].name,
3332                                         sizeof(xstats_names[count].name),
3333                                         "%s",
3334                                         rte_ixgbe_stats_strings[i].name);
3335                                 count++;
3336                         }
3337
3338                         /* MACsec Stats */
3339                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3340                                 snprintf(xstats_names[count].name,
3341                                         sizeof(xstats_names[count].name),
3342                                         "%s",
3343                                         rte_ixgbe_macsec_strings[i].name);
3344                                 count++;
3345                         }
3346
3347                         /* RX Priority Stats */
3348                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3349                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3350                                         snprintf(xstats_names[count].name,
3351                                             sizeof(xstats_names[count].name),
3352                                             "rx_priority%u_%s", i,
3353                                             rte_ixgbe_rxq_strings[stat].name);
3354                                         count++;
3355                                 }
3356                         }
3357
3358                         /* TX Priority Stats */
3359                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3360                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3361                                         snprintf(xstats_names[count].name,
3362                                             sizeof(xstats_names[count].name),
3363                                             "tx_priority%u_%s", i,
3364                                             rte_ixgbe_txq_strings[stat].name);
3365                                         count++;
3366                                 }
3367                         }
3368                 }
3369                 return cnt_stats;
3370         }
3371
3372         uint16_t i;
3373         uint16_t size = ixgbe_xstats_calc_num();
3374         struct rte_eth_xstat_name xstats_names_copy[size];
3375
3376         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3377                         size);
3378
3379         for (i = 0; i < limit; i++) {
3380                 if (ids[i] >= size) {
3381                         PMD_INIT_LOG(ERR, "id value isn't valid");
3382                         return -1;
3383                 }
3384                 strcpy(xstats_names[i].name,
3385                                 xstats_names_copy[ids[i]].name);
3386         }
3387         return limit;
3388 }
3389
3390 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3391         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3392 {
3393         unsigned i;
3394
3395         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3396                 return -ENOMEM;
3397
3398         if (xstats_names != NULL)
3399                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3400                         snprintf(xstats_names[i].name,
3401                                 sizeof(xstats_names[i].name),
3402                                 "%s", rte_ixgbevf_stats_strings[i].name);
3403         return IXGBEVF_NB_XSTATS;
3404 }
3405
3406 static int
3407 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3408                                          unsigned n)
3409 {
3410         struct ixgbe_hw *hw =
3411                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412         struct ixgbe_hw_stats *hw_stats =
3413                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3414         struct ixgbe_macsec_stats *macsec_stats =
3415                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3416                                 dev->data->dev_private);
3417         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3418         unsigned i, stat, count = 0;
3419
3420         count = ixgbe_xstats_calc_num();
3421
3422         if (n < count)
3423                 return count;
3424
3425         total_missed_rx = 0;
3426         total_qbrc = 0;
3427         total_qprc = 0;
3428         total_qprdc = 0;
3429
3430         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3431                         &total_qbrc, &total_qprc, &total_qprdc);
3432
3433         /* If this is a reset xstats is NULL, and we have cleared the
3434          * registers by reading them.
3435          */
3436         if (!xstats)
3437                 return 0;
3438
3439         /* Extended stats from ixgbe_hw_stats */
3440         count = 0;
3441         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3442                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3443                                 rte_ixgbe_stats_strings[i].offset);
3444                 xstats[count].id = count;
3445                 count++;
3446         }
3447
3448         /* MACsec Stats */
3449         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3450                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3451                                 rte_ixgbe_macsec_strings[i].offset);
3452                 xstats[count].id = count;
3453                 count++;
3454         }
3455
3456         /* RX Priority Stats */
3457         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3458                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3459                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3460                                         rte_ixgbe_rxq_strings[stat].offset +
3461                                         (sizeof(uint64_t) * i));
3462                         xstats[count].id = count;
3463                         count++;
3464                 }
3465         }
3466
3467         /* TX Priority Stats */
3468         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3469                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3470                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3471                                         rte_ixgbe_txq_strings[stat].offset +
3472                                         (sizeof(uint64_t) * i));
3473                         xstats[count].id = count;
3474                         count++;
3475                 }
3476         }
3477         return count;
3478 }
3479
3480 static int
3481 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3482                 uint64_t *values, unsigned int n)
3483 {
3484         if (!ids) {
3485                 struct ixgbe_hw *hw =
3486                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3487                 struct ixgbe_hw_stats *hw_stats =
3488                                 IXGBE_DEV_PRIVATE_TO_STATS(
3489                                                 dev->data->dev_private);
3490                 struct ixgbe_macsec_stats *macsec_stats =
3491                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3492                                         dev->data->dev_private);
3493                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3494                 unsigned int i, stat, count = 0;
3495
3496                 count = ixgbe_xstats_calc_num();
3497
3498                 if (!ids && n < count)
3499                         return count;
3500
3501                 total_missed_rx = 0;
3502                 total_qbrc = 0;
3503                 total_qprc = 0;
3504                 total_qprdc = 0;
3505
3506                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3507                                 &total_missed_rx, &total_qbrc, &total_qprc,
3508                                 &total_qprdc);
3509
3510                 /* If this is a reset xstats is NULL, and we have cleared the
3511                  * registers by reading them.
3512                  */
3513                 if (!ids && !values)
3514                         return 0;
3515
3516                 /* Extended stats from ixgbe_hw_stats */
3517                 count = 0;
3518                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3519                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3520                                         rte_ixgbe_stats_strings[i].offset);
3521                         count++;
3522                 }
3523
3524                 /* MACsec Stats */
3525                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3526                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3527                                         rte_ixgbe_macsec_strings[i].offset);
3528                         count++;
3529                 }
3530
3531                 /* RX Priority Stats */
3532                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3533                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3534                                 values[count] =
3535                                         *(uint64_t *)(((char *)hw_stats) +
3536                                         rte_ixgbe_rxq_strings[stat].offset +
3537                                         (sizeof(uint64_t) * i));
3538                                 count++;
3539                         }
3540                 }
3541
3542                 /* TX Priority Stats */
3543                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3544                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3545                                 values[count] =
3546                                         *(uint64_t *)(((char *)hw_stats) +
3547                                         rte_ixgbe_txq_strings[stat].offset +
3548                                         (sizeof(uint64_t) * i));
3549                                 count++;
3550                         }
3551                 }
3552                 return count;
3553         }
3554
3555         uint16_t i;
3556         uint16_t size = ixgbe_xstats_calc_num();
3557         uint64_t values_copy[size];
3558
3559         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3560
3561         for (i = 0; i < n; i++) {
3562                 if (ids[i] >= size) {
3563                         PMD_INIT_LOG(ERR, "id value isn't valid");
3564                         return -1;
3565                 }
3566                 values[i] = values_copy[ids[i]];
3567         }
3568         return n;
3569 }
3570
3571 static void
3572 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3573 {
3574         struct ixgbe_hw_stats *stats =
3575                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3576         struct ixgbe_macsec_stats *macsec_stats =
3577                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3578                                 dev->data->dev_private);
3579
3580         unsigned count = ixgbe_xstats_calc_num();
3581
3582         /* HW registers are cleared on read */
3583         ixgbe_dev_xstats_get(dev, NULL, count);
3584
3585         /* Reset software totals */
3586         memset(stats, 0, sizeof(*stats));
3587         memset(macsec_stats, 0, sizeof(*macsec_stats));
3588 }
3589
3590 static void
3591 ixgbevf_update_stats(struct rte_eth_dev *dev)
3592 {
3593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3595                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3596
3597         /* Good Rx packet, include VF loopback */
3598         UPDATE_VF_STAT(IXGBE_VFGPRC,
3599             hw_stats->last_vfgprc, hw_stats->vfgprc);
3600
3601         /* Good Rx octets, include VF loopback */
3602         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3603             hw_stats->last_vfgorc, hw_stats->vfgorc);
3604
3605         /* Good Tx packet, include VF loopback */
3606         UPDATE_VF_STAT(IXGBE_VFGPTC,
3607             hw_stats->last_vfgptc, hw_stats->vfgptc);
3608
3609         /* Good Tx octets, include VF loopback */
3610         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3611             hw_stats->last_vfgotc, hw_stats->vfgotc);
3612
3613         /* Rx Multicst Packet */
3614         UPDATE_VF_STAT(IXGBE_VFMPRC,
3615             hw_stats->last_vfmprc, hw_stats->vfmprc);
3616 }
3617
3618 static int
3619 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3620                        unsigned n)
3621 {
3622         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3623                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3624         unsigned i;
3625
3626         if (n < IXGBEVF_NB_XSTATS)
3627                 return IXGBEVF_NB_XSTATS;
3628
3629         ixgbevf_update_stats(dev);
3630
3631         if (!xstats)
3632                 return 0;
3633
3634         /* Extended stats */
3635         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3636                 xstats[i].id = i;
3637                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3638                         rte_ixgbevf_stats_strings[i].offset);
3639         }
3640
3641         return IXGBEVF_NB_XSTATS;
3642 }
3643
3644 static int
3645 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3646 {
3647         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3648                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3649
3650         ixgbevf_update_stats(dev);
3651
3652         if (stats == NULL)
3653                 return -EINVAL;
3654
3655         stats->ipackets = hw_stats->vfgprc;
3656         stats->ibytes = hw_stats->vfgorc;
3657         stats->opackets = hw_stats->vfgptc;
3658         stats->obytes = hw_stats->vfgotc;
3659         return 0;
3660 }
3661
3662 static void
3663 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3664 {
3665         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3666                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3667
3668         /* Sync HW register to the last stats */
3669         ixgbevf_dev_stats_get(dev, NULL);
3670
3671         /* reset HW current stats*/
3672         hw_stats->vfgprc = 0;
3673         hw_stats->vfgorc = 0;
3674         hw_stats->vfgptc = 0;
3675         hw_stats->vfgotc = 0;
3676 }
3677
3678 static int
3679 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3680 {
3681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         u16 eeprom_verh, eeprom_verl;
3683         u32 etrack_id;
3684         int ret;
3685
3686         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3687         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3688
3689         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3690         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3691
3692         ret += 1; /* add the size of '\0' */
3693         if (fw_size < (u32)ret)
3694                 return ret;
3695         else
3696                 return 0;
3697 }
3698
3699 static void
3700 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3701 {
3702         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3705
3706         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3707         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3708         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3709                 /*
3710                  * When DCB/VT is off, maximum number of queues changes,
3711                  * except for 82598EB, which remains constant.
3712                  */
3713                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3714                                 hw->mac.type != ixgbe_mac_82598EB)
3715                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3716         }
3717         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3718         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3719         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3720         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3721         dev_info->max_vfs = pci_dev->max_vfs;
3722         if (hw->mac.type == ixgbe_mac_82598EB)
3723                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3724         else
3725                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3726         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3727         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3728         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3729                                      dev_info->rx_queue_offload_capa);
3730         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3731         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3732
3733         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3734                 .rx_thresh = {
3735                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3736                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3737                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3738                 },
3739                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3740                 .rx_drop_en = 0,
3741                 .offloads = 0,
3742         };
3743
3744         dev_info->default_txconf = (struct rte_eth_txconf) {
3745                 .tx_thresh = {
3746                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3747                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3748                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3749                 },
3750                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3751                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3752                 .offloads = 0,
3753         };
3754
3755         dev_info->rx_desc_lim = rx_desc_lim;
3756         dev_info->tx_desc_lim = tx_desc_lim;
3757
3758         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3759         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3760         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3761
3762         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3763         if (hw->mac.type == ixgbe_mac_X540 ||
3764             hw->mac.type == ixgbe_mac_X540_vf ||
3765             hw->mac.type == ixgbe_mac_X550 ||
3766             hw->mac.type == ixgbe_mac_X550_vf) {
3767                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3768         }
3769         if (hw->mac.type == ixgbe_mac_X550) {
3770                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3771                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3772         }
3773
3774         /* Driver-preferred Rx/Tx parameters */
3775         dev_info->default_rxportconf.burst_size = 32;
3776         dev_info->default_txportconf.burst_size = 32;
3777         dev_info->default_rxportconf.nb_queues = 1;
3778         dev_info->default_txportconf.nb_queues = 1;
3779         dev_info->default_rxportconf.ring_size = 256;
3780         dev_info->default_txportconf.ring_size = 256;
3781 }
3782
3783 static const uint32_t *
3784 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3785 {
3786         static const uint32_t ptypes[] = {
3787                 /* For non-vec functions,
3788                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3789                  * for vec functions,
3790                  * refers to _recv_raw_pkts_vec().
3791                  */
3792                 RTE_PTYPE_L2_ETHER,
3793                 RTE_PTYPE_L3_IPV4,
3794                 RTE_PTYPE_L3_IPV4_EXT,
3795                 RTE_PTYPE_L3_IPV6,
3796                 RTE_PTYPE_L3_IPV6_EXT,
3797                 RTE_PTYPE_L4_SCTP,
3798                 RTE_PTYPE_L4_TCP,
3799                 RTE_PTYPE_L4_UDP,
3800                 RTE_PTYPE_TUNNEL_IP,
3801                 RTE_PTYPE_INNER_L3_IPV6,
3802                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3803                 RTE_PTYPE_INNER_L4_TCP,
3804                 RTE_PTYPE_INNER_L4_UDP,
3805                 RTE_PTYPE_UNKNOWN
3806         };
3807
3808         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3809             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3810             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3811             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3812                 return ptypes;
3813
3814 #if defined(RTE_ARCH_X86)
3815         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3816             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3817                 return ptypes;
3818 #endif
3819         return NULL;
3820 }
3821
3822 static void
3823 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3824                      struct rte_eth_dev_info *dev_info)
3825 {
3826         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3828
3829         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3830         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3831         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3832         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3833         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3834         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3835         dev_info->max_vfs = pci_dev->max_vfs;
3836         if (hw->mac.type == ixgbe_mac_82598EB)
3837                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3838         else
3839                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3840         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3841         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3842                                      dev_info->rx_queue_offload_capa);
3843         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3844         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3845
3846         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3847                 .rx_thresh = {
3848                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3849                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3850                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3851                 },
3852                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3853                 .rx_drop_en = 0,
3854                 .offloads = 0,
3855         };
3856
3857         dev_info->default_txconf = (struct rte_eth_txconf) {
3858                 .tx_thresh = {
3859                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3860                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3861                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3862                 },
3863                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3864                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3865                 .offloads = 0,
3866         };
3867
3868         dev_info->rx_desc_lim = rx_desc_lim;
3869         dev_info->tx_desc_lim = tx_desc_lim;
3870 }
3871
3872 static int
3873 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3874                    int *link_up, int wait_to_complete)
3875 {
3876         /**
3877          * for a quick link status checking, wait_to_compelet == 0,
3878          * skip PF link status checking
3879          */
3880         bool no_pflink_check = wait_to_complete == 0;
3881         struct ixgbe_mbx_info *mbx = &hw->mbx;
3882         struct ixgbe_mac_info *mac = &hw->mac;
3883         uint32_t links_reg, in_msg;
3884         int ret_val = 0;
3885
3886         /* If we were hit with a reset drop the link */
3887         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3888                 mac->get_link_status = true;
3889
3890         if (!mac->get_link_status)
3891                 goto out;
3892
3893         /* if link status is down no point in checking to see if pf is up */
3894         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3895         if (!(links_reg & IXGBE_LINKS_UP))
3896                 goto out;
3897
3898         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3899          * before the link status is correct
3900          */
3901         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3902                 int i;
3903
3904                 for (i = 0; i < 5; i++) {
3905                         rte_delay_us(100);
3906                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3907
3908                         if (!(links_reg & IXGBE_LINKS_UP))
3909                                 goto out;
3910                 }
3911         }
3912
3913         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3914         case IXGBE_LINKS_SPEED_10G_82599:
3915                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3916                 if (hw->mac.type >= ixgbe_mac_X550) {
3917                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3918                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3919                 }
3920                 break;
3921         case IXGBE_LINKS_SPEED_1G_82599:
3922                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3923                 break;
3924         case IXGBE_LINKS_SPEED_100_82599:
3925                 *speed = IXGBE_LINK_SPEED_100_FULL;
3926                 if (hw->mac.type == ixgbe_mac_X550) {
3927                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3928                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3929                 }
3930                 break;
3931         case IXGBE_LINKS_SPEED_10_X550EM_A:
3932                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3933                 /* Since Reserved in older MAC's */
3934                 if (hw->mac.type >= ixgbe_mac_X550)
3935                         *speed = IXGBE_LINK_SPEED_10_FULL;
3936                 break;
3937         default:
3938                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3939         }
3940
3941         if (no_pflink_check) {
3942                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3943                         mac->get_link_status = true;
3944                 else
3945                         mac->get_link_status = false;
3946
3947                 goto out;
3948         }
3949         /* if the read failed it could just be a mailbox collision, best wait
3950          * until we are called again and don't report an error
3951          */
3952         if (mbx->ops.read(hw, &in_msg, 1, 0))
3953                 goto out;
3954
3955         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3956                 /* msg is not CTS and is NACK we must have lost CTS status */
3957                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3958                         ret_val = -1;
3959                 goto out;
3960         }
3961
3962         /* the pf is talking, if we timed out in the past we reinit */
3963         if (!mbx->timeout) {
3964                 ret_val = -1;
3965                 goto out;
3966         }
3967
3968         /* if we passed all the tests above then the link is up and we no
3969          * longer need to check for link
3970          */
3971         mac->get_link_status = false;
3972
3973 out:
3974         *link_up = !mac->get_link_status;
3975         return ret_val;
3976 }
3977
3978 static void
3979 ixgbe_dev_setup_link_alarm_handler(void *param)
3980 {
3981         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983         struct ixgbe_interrupt *intr =
3984                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3985         u32 speed;
3986         bool autoneg = false;
3987
3988         speed = hw->phy.autoneg_advertised;
3989         if (!speed)
3990                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3991
3992         ixgbe_setup_link(hw, speed, true);
3993
3994         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3995 }
3996
3997 /* return 0 means link status changed, -1 means not changed */
3998 int
3999 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4000                             int wait_to_complete, int vf)
4001 {
4002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4003         struct rte_eth_link link;
4004         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4005         struct ixgbe_interrupt *intr =
4006                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4007         int link_up;
4008         int diag;
4009         int wait = 1;
4010
4011         memset(&link, 0, sizeof(link));
4012         link.link_status = ETH_LINK_DOWN;
4013         link.link_speed = ETH_SPEED_NUM_NONE;
4014         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4015         link.link_autoneg = ETH_LINK_AUTONEG;
4016
4017         hw->mac.get_link_status = true;
4018
4019         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4020                 return rte_eth_linkstatus_set(dev, &link);
4021
4022         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4023         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4024                 wait = 0;
4025
4026         if (vf)
4027                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4028         else
4029                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4030
4031         if (diag != 0) {
4032                 link.link_speed = ETH_SPEED_NUM_100M;
4033                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4034                 return rte_eth_linkstatus_set(dev, &link);
4035         }
4036
4037         if (link_up == 0) {
4038                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4039                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4040                         rte_eal_alarm_set(10,
4041                                 ixgbe_dev_setup_link_alarm_handler, dev);
4042                 }
4043                 return rte_eth_linkstatus_set(dev, &link);
4044         }
4045
4046         link.link_status = ETH_LINK_UP;
4047         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4048
4049         switch (link_speed) {
4050         default:
4051         case IXGBE_LINK_SPEED_UNKNOWN:
4052                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4053                 link.link_speed = ETH_SPEED_NUM_100M;
4054                 break;
4055
4056         case IXGBE_LINK_SPEED_100_FULL:
4057                 link.link_speed = ETH_SPEED_NUM_100M;
4058                 break;
4059
4060         case IXGBE_LINK_SPEED_1GB_FULL:
4061                 link.link_speed = ETH_SPEED_NUM_1G;
4062                 break;
4063
4064         case IXGBE_LINK_SPEED_2_5GB_FULL:
4065                 link.link_speed = ETH_SPEED_NUM_2_5G;
4066                 break;
4067
4068         case IXGBE_LINK_SPEED_5GB_FULL:
4069                 link.link_speed = ETH_SPEED_NUM_5G;
4070                 break;
4071
4072         case IXGBE_LINK_SPEED_10GB_FULL:
4073                 link.link_speed = ETH_SPEED_NUM_10G;
4074                 break;
4075         }
4076
4077         return rte_eth_linkstatus_set(dev, &link);
4078 }
4079
4080 static int
4081 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4082 {
4083         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4084 }
4085
4086 static int
4087 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4088 {
4089         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4090 }
4091
4092 static void
4093 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4094 {
4095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4096         uint32_t fctrl;
4097
4098         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4099         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4100         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4101 }
4102
4103 static void
4104 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4105 {
4106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107         uint32_t fctrl;
4108
4109         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4110         fctrl &= (~IXGBE_FCTRL_UPE);
4111         if (dev->data->all_multicast == 1)
4112                 fctrl |= IXGBE_FCTRL_MPE;
4113         else
4114                 fctrl &= (~IXGBE_FCTRL_MPE);
4115         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4116 }
4117
4118 static void
4119 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4120 {
4121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         uint32_t fctrl;
4123
4124         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4125         fctrl |= IXGBE_FCTRL_MPE;
4126         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4127 }
4128
4129 static void
4130 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4131 {
4132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4133         uint32_t fctrl;
4134
4135         if (dev->data->promiscuous == 1)
4136                 return; /* must remain in all_multicast mode */
4137
4138         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4139         fctrl &= (~IXGBE_FCTRL_MPE);
4140         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4141 }
4142
4143 /**
4144  * It clears the interrupt causes and enables the interrupt.
4145  * It will be called once only during nic initialized.
4146  *
4147  * @param dev
4148  *  Pointer to struct rte_eth_dev.
4149  * @param on
4150  *  Enable or Disable.
4151  *
4152  * @return
4153  *  - On success, zero.
4154  *  - On failure, a negative value.
4155  */
4156 static int
4157 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4158 {
4159         struct ixgbe_interrupt *intr =
4160                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4161
4162         ixgbe_dev_link_status_print(dev);
4163         if (on)
4164                 intr->mask |= IXGBE_EICR_LSC;
4165         else
4166                 intr->mask &= ~IXGBE_EICR_LSC;
4167
4168         return 0;
4169 }
4170
4171 /**
4172  * It clears the interrupt causes and enables the interrupt.
4173  * It will be called once only during nic initialized.
4174  *
4175  * @param dev
4176  *  Pointer to struct rte_eth_dev.
4177  *
4178  * @return
4179  *  - On success, zero.
4180  *  - On failure, a negative value.
4181  */
4182 static int
4183 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4184 {
4185         struct ixgbe_interrupt *intr =
4186                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4187
4188         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4189
4190         return 0;
4191 }
4192
4193 /**
4194  * It clears the interrupt causes and enables the interrupt.
4195  * It will be called once only during nic initialized.
4196  *
4197  * @param dev
4198  *  Pointer to struct rte_eth_dev.
4199  *
4200  * @return
4201  *  - On success, zero.
4202  *  - On failure, a negative value.
4203  */
4204 static int
4205 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4206 {
4207         struct ixgbe_interrupt *intr =
4208                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4209
4210         intr->mask |= IXGBE_EICR_LINKSEC;
4211
4212         return 0;
4213 }
4214
4215 /*
4216  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4217  *
4218  * @param dev
4219  *  Pointer to struct rte_eth_dev.
4220  *
4221  * @return
4222  *  - On success, zero.
4223  *  - On failure, a negative value.
4224  */
4225 static int
4226 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4227 {
4228         uint32_t eicr;
4229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4230         struct ixgbe_interrupt *intr =
4231                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4232
4233         /* clear all cause mask */
4234         ixgbe_disable_intr(hw);
4235
4236         /* read-on-clear nic registers here */
4237         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4238         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4239
4240         intr->flags = 0;
4241
4242         /* set flag for async link update */
4243         if (eicr & IXGBE_EICR_LSC)
4244                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4245
4246         if (eicr & IXGBE_EICR_MAILBOX)
4247                 intr->flags |= IXGBE_FLAG_MAILBOX;
4248
4249         if (eicr & IXGBE_EICR_LINKSEC)
4250                 intr->flags |= IXGBE_FLAG_MACSEC;
4251
4252         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4253             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4254             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4255                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4256
4257         return 0;
4258 }
4259
4260 /**
4261  * It gets and then prints the link status.
4262  *
4263  * @param dev
4264  *  Pointer to struct rte_eth_dev.
4265  *
4266  * @return
4267  *  - On success, zero.
4268  *  - On failure, a negative value.
4269  */
4270 static void
4271 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4272 {
4273         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4274         struct rte_eth_link link;
4275
4276         rte_eth_linkstatus_get(dev, &link);
4277
4278         if (link.link_status) {
4279                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4280                                         (int)(dev->data->port_id),
4281                                         (unsigned)link.link_speed,
4282                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4283                                         "full-duplex" : "half-duplex");
4284         } else {
4285                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4286                                 (int)(dev->data->port_id));
4287         }
4288         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4289                                 pci_dev->addr.domain,
4290                                 pci_dev->addr.bus,
4291                                 pci_dev->addr.devid,
4292                                 pci_dev->addr.function);
4293 }
4294
4295 /*
4296  * It executes link_update after knowing an interrupt occurred.
4297  *
4298  * @param dev
4299  *  Pointer to struct rte_eth_dev.
4300  *
4301  * @return
4302  *  - On success, zero.
4303  *  - On failure, a negative value.
4304  */
4305 static int
4306 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4307 {
4308         struct ixgbe_interrupt *intr =
4309                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4310         int64_t timeout;
4311         struct ixgbe_hw *hw =
4312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313
4314         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4315
4316         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4317                 ixgbe_pf_mbx_process(dev);
4318                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4319         }
4320
4321         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4322                 ixgbe_handle_lasi(hw);
4323                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4324         }
4325
4326         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4327                 struct rte_eth_link link;
4328
4329                 /* get the link status before link update, for predicting later */
4330                 rte_eth_linkstatus_get(dev, &link);
4331
4332                 ixgbe_dev_link_update(dev, 0);
4333
4334                 /* likely to up */
4335                 if (!link.link_status)
4336                         /* handle it 1 sec later, wait it being stable */
4337                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4338                 /* likely to down */
4339                 else
4340                         /* handle it 4 sec later, wait it being stable */
4341                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4342
4343                 ixgbe_dev_link_status_print(dev);
4344                 if (rte_eal_alarm_set(timeout * 1000,
4345                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4346                         PMD_DRV_LOG(ERR, "Error setting alarm");
4347                 else {
4348                         /* remember original mask */
4349                         intr->mask_original = intr->mask;
4350                         /* only disable lsc interrupt */
4351                         intr->mask &= ~IXGBE_EIMS_LSC;
4352                 }
4353         }
4354
4355         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4356         ixgbe_enable_intr(dev);
4357
4358         return 0;
4359 }
4360
4361 /**
4362  * Interrupt handler which shall be registered for alarm callback for delayed
4363  * handling specific interrupt to wait for the stable nic state. As the
4364  * NIC interrupt state is not stable for ixgbe after link is just down,
4365  * it needs to wait 4 seconds to get the stable status.
4366  *
4367  * @param handle
4368  *  Pointer to interrupt handle.
4369  * @param param
4370  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4371  *
4372  * @return
4373  *  void
4374  */
4375 static void
4376 ixgbe_dev_interrupt_delayed_handler(void *param)
4377 {
4378         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4379         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4380         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4381         struct ixgbe_interrupt *intr =
4382                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4383         struct ixgbe_hw *hw =
4384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4385         uint32_t eicr;
4386
4387         ixgbe_disable_intr(hw);
4388
4389         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4390         if (eicr & IXGBE_EICR_MAILBOX)
4391                 ixgbe_pf_mbx_process(dev);
4392
4393         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4394                 ixgbe_handle_lasi(hw);
4395                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4396         }
4397
4398         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4399                 ixgbe_dev_link_update(dev, 0);
4400                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4401                 ixgbe_dev_link_status_print(dev);
4402                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4403                                               NULL);
4404         }
4405
4406         if (intr->flags & IXGBE_FLAG_MACSEC) {
4407                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4408                                               NULL);
4409                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4410         }
4411
4412         /* restore original mask */
4413         intr->mask = intr->mask_original;
4414         intr->mask_original = 0;
4415
4416         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4417         ixgbe_enable_intr(dev);
4418         rte_intr_enable(intr_handle);
4419 }
4420
4421 /**
4422  * Interrupt handler triggered by NIC  for handling
4423  * specific interrupt.
4424  *
4425  * @param handle
4426  *  Pointer to interrupt handle.
4427  * @param param
4428  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4429  *
4430  * @return
4431  *  void
4432  */
4433 static void
4434 ixgbe_dev_interrupt_handler(void *param)
4435 {
4436         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4437
4438         ixgbe_dev_interrupt_get_status(dev);
4439         ixgbe_dev_interrupt_action(dev);
4440 }
4441
4442 static int
4443 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4444 {
4445         struct ixgbe_hw *hw;
4446
4447         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4449 }
4450
4451 static int
4452 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4453 {
4454         struct ixgbe_hw *hw;
4455
4456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4458 }
4459
4460 static int
4461 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4462 {
4463         struct ixgbe_hw *hw;
4464         uint32_t mflcn_reg;
4465         uint32_t fccfg_reg;
4466         int rx_pause;
4467         int tx_pause;
4468
4469         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470
4471         fc_conf->pause_time = hw->fc.pause_time;
4472         fc_conf->high_water = hw->fc.high_water[0];
4473         fc_conf->low_water = hw->fc.low_water[0];
4474         fc_conf->send_xon = hw->fc.send_xon;
4475         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4476
4477         /*
4478          * Return rx_pause status according to actual setting of
4479          * MFLCN register.
4480          */
4481         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4482         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4483                 rx_pause = 1;
4484         else
4485                 rx_pause = 0;
4486
4487         /*
4488          * Return tx_pause status according to actual setting of
4489          * FCCFG register.
4490          */
4491         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4492         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4493                 tx_pause = 1;
4494         else
4495                 tx_pause = 0;
4496
4497         if (rx_pause && tx_pause)
4498                 fc_conf->mode = RTE_FC_FULL;
4499         else if (rx_pause)
4500                 fc_conf->mode = RTE_FC_RX_PAUSE;
4501         else if (tx_pause)
4502                 fc_conf->mode = RTE_FC_TX_PAUSE;
4503         else
4504                 fc_conf->mode = RTE_FC_NONE;
4505
4506         return 0;
4507 }
4508
4509 static int
4510 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4511 {
4512         struct ixgbe_hw *hw;
4513         int err;
4514         uint32_t rx_buf_size;
4515         uint32_t max_high_water;
4516         uint32_t mflcn;
4517         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4518                 ixgbe_fc_none,
4519                 ixgbe_fc_rx_pause,
4520                 ixgbe_fc_tx_pause,
4521                 ixgbe_fc_full
4522         };
4523
4524         PMD_INIT_FUNC_TRACE();
4525
4526         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4528         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4529
4530         /*
4531          * At least reserve one Ethernet frame for watermark
4532          * high_water/low_water in kilo bytes for ixgbe
4533          */
4534         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4535         if ((fc_conf->high_water > max_high_water) ||
4536                 (fc_conf->high_water < fc_conf->low_water)) {
4537                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4538                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4539                 return -EINVAL;
4540         }
4541
4542         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4543         hw->fc.pause_time     = fc_conf->pause_time;
4544         hw->fc.high_water[0]  = fc_conf->high_water;
4545         hw->fc.low_water[0]   = fc_conf->low_water;
4546         hw->fc.send_xon       = fc_conf->send_xon;
4547         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4548
4549         err = ixgbe_fc_enable(hw);
4550
4551         /* Not negotiated is not an error case */
4552         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4553
4554                 /* check if we want to forward MAC frames - driver doesn't have native
4555                  * capability to do that, so we'll write the registers ourselves */
4556
4557                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4558
4559                 /* set or clear MFLCN.PMCF bit depending on configuration */
4560                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4561                         mflcn |= IXGBE_MFLCN_PMCF;
4562                 else
4563                         mflcn &= ~IXGBE_MFLCN_PMCF;
4564
4565                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4566                 IXGBE_WRITE_FLUSH(hw);
4567
4568                 return 0;
4569         }
4570
4571         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4572         return -EIO;
4573 }
4574
4575 /**
4576  *  ixgbe_pfc_enable_generic - Enable flow control
4577  *  @hw: pointer to hardware structure
4578  *  @tc_num: traffic class number
4579  *  Enable flow control according to the current settings.
4580  */
4581 static int
4582 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4583 {
4584         int ret_val = 0;
4585         uint32_t mflcn_reg, fccfg_reg;
4586         uint32_t reg;
4587         uint32_t fcrtl, fcrth;
4588         uint8_t i;
4589         uint8_t nb_rx_en;
4590
4591         /* Validate the water mark configuration */
4592         if (!hw->fc.pause_time) {
4593                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4594                 goto out;
4595         }
4596
4597         /* Low water mark of zero causes XOFF floods */
4598         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4599                  /* High/Low water can not be 0 */
4600                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4601                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4602                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4603                         goto out;
4604                 }
4605
4606                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4607                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4608                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4609                         goto out;
4610                 }
4611         }
4612         /* Negotiate the fc mode to use */
4613         ixgbe_fc_autoneg(hw);
4614
4615         /* Disable any previous flow control settings */
4616         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4617         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4618
4619         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4620         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4621
4622         switch (hw->fc.current_mode) {
4623         case ixgbe_fc_none:
4624                 /*
4625                  * If the count of enabled RX Priority Flow control >1,
4626                  * and the TX pause can not be disabled
4627                  */
4628                 nb_rx_en = 0;
4629                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4630                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4631                         if (reg & IXGBE_FCRTH_FCEN)
4632                                 nb_rx_en++;
4633                 }
4634                 if (nb_rx_en > 1)
4635                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4636                 break;
4637         case ixgbe_fc_rx_pause:
4638                 /*
4639                  * Rx Flow control is enabled and Tx Flow control is
4640                  * disabled by software override. Since there really
4641                  * isn't a way to advertise that we are capable of RX
4642                  * Pause ONLY, we will advertise that we support both
4643                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4644                  * disable the adapter's ability to send PAUSE frames.
4645                  */
4646                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4647                 /*
4648                  * If the count of enabled RX Priority Flow control >1,
4649                  * and the TX pause can not be disabled
4650                  */
4651                 nb_rx_en = 0;
4652                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4653                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4654                         if (reg & IXGBE_FCRTH_FCEN)
4655                                 nb_rx_en++;
4656                 }
4657                 if (nb_rx_en > 1)
4658                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4659                 break;
4660         case ixgbe_fc_tx_pause:
4661                 /*
4662                  * Tx Flow control is enabled, and Rx Flow control is
4663                  * disabled by software override.
4664                  */
4665                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4666                 break;
4667         case ixgbe_fc_full:
4668                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4669                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4670                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4671                 break;
4672         default:
4673                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4674                 ret_val = IXGBE_ERR_CONFIG;
4675                 goto out;
4676         }
4677
4678         /* Set 802.3x based flow control settings. */
4679         mflcn_reg |= IXGBE_MFLCN_DPF;
4680         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4681         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4682
4683         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4684         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4685                 hw->fc.high_water[tc_num]) {
4686                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4687                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4688                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4689         } else {
4690                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4691                 /*
4692                  * In order to prevent Tx hangs when the internal Tx
4693                  * switch is enabled we must set the high water mark
4694                  * to the maximum FCRTH value.  This allows the Tx
4695                  * switch to function even under heavy Rx workloads.
4696                  */
4697                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4698         }
4699         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4700
4701         /* Configure pause time (2 TCs per register) */
4702         reg = hw->fc.pause_time * 0x00010001;
4703         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4704                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4705
4706         /* Configure flow control refresh threshold value */
4707         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4708
4709 out:
4710         return ret_val;
4711 }
4712
4713 static int
4714 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4715 {
4716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4718
4719         if (hw->mac.type != ixgbe_mac_82598EB) {
4720                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4721         }
4722         return ret_val;
4723 }
4724
4725 static int
4726 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4727 {
4728         int err;
4729         uint32_t rx_buf_size;
4730         uint32_t max_high_water;
4731         uint8_t tc_num;
4732         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4733         struct ixgbe_hw *hw =
4734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         struct ixgbe_dcb_config *dcb_config =
4736                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4737
4738         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4739                 ixgbe_fc_none,
4740                 ixgbe_fc_rx_pause,
4741                 ixgbe_fc_tx_pause,
4742                 ixgbe_fc_full
4743         };
4744
4745         PMD_INIT_FUNC_TRACE();
4746
4747         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4748         tc_num = map[pfc_conf->priority];
4749         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4750         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4751         /*
4752          * At least reserve one Ethernet frame for watermark
4753          * high_water/low_water in kilo bytes for ixgbe
4754          */
4755         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4756         if ((pfc_conf->fc.high_water > max_high_water) ||
4757             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4758                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4759                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4760                 return -EINVAL;
4761         }
4762
4763         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4764         hw->fc.pause_time = pfc_conf->fc.pause_time;
4765         hw->fc.send_xon = pfc_conf->fc.send_xon;
4766         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4767         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4768
4769         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4770
4771         /* Not negotiated is not an error case */
4772         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4773                 return 0;
4774
4775         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4776         return -EIO;
4777 }
4778
4779 static int
4780 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4781                           struct rte_eth_rss_reta_entry64 *reta_conf,
4782                           uint16_t reta_size)
4783 {
4784         uint16_t i, sp_reta_size;
4785         uint8_t j, mask;
4786         uint32_t reta, r;
4787         uint16_t idx, shift;
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         uint32_t reta_reg;
4790
4791         PMD_INIT_FUNC_TRACE();
4792
4793         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4794                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4795                         "NIC.");
4796                 return -ENOTSUP;
4797         }
4798
4799         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4800         if (reta_size != sp_reta_size) {
4801                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4802                         "(%d) doesn't match the number hardware can supported "
4803                         "(%d)", reta_size, sp_reta_size);
4804                 return -EINVAL;
4805         }
4806
4807         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4808                 idx = i / RTE_RETA_GROUP_SIZE;
4809                 shift = i % RTE_RETA_GROUP_SIZE;
4810                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4811                                                 IXGBE_4_BIT_MASK);
4812                 if (!mask)
4813                         continue;
4814                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4815                 if (mask == IXGBE_4_BIT_MASK)
4816                         r = 0;
4817                 else
4818                         r = IXGBE_READ_REG(hw, reta_reg);
4819                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4820                         if (mask & (0x1 << j))
4821                                 reta |= reta_conf[idx].reta[shift + j] <<
4822                                                         (CHAR_BIT * j);
4823                         else
4824                                 reta |= r & (IXGBE_8_BIT_MASK <<
4825                                                 (CHAR_BIT * j));
4826                 }
4827                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4828         }
4829
4830         return 0;
4831 }
4832
4833 static int
4834 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4835                          struct rte_eth_rss_reta_entry64 *reta_conf,
4836                          uint16_t reta_size)
4837 {
4838         uint16_t i, sp_reta_size;
4839         uint8_t j, mask;
4840         uint32_t reta;
4841         uint16_t idx, shift;
4842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4843         uint32_t reta_reg;
4844
4845         PMD_INIT_FUNC_TRACE();
4846         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4847         if (reta_size != sp_reta_size) {
4848                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4849                         "(%d) doesn't match the number hardware can supported "
4850                         "(%d)", reta_size, sp_reta_size);
4851                 return -EINVAL;
4852         }
4853
4854         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4855                 idx = i / RTE_RETA_GROUP_SIZE;
4856                 shift = i % RTE_RETA_GROUP_SIZE;
4857                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4858                                                 IXGBE_4_BIT_MASK);
4859                 if (!mask)
4860                         continue;
4861
4862                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4863                 reta = IXGBE_READ_REG(hw, reta_reg);
4864                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4865                         if (mask & (0x1 << j))
4866                                 reta_conf[idx].reta[shift + j] =
4867                                         ((reta >> (CHAR_BIT * j)) &
4868                                                 IXGBE_8_BIT_MASK);
4869                 }
4870         }
4871
4872         return 0;
4873 }
4874
4875 static int
4876 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4877                                 uint32_t index, uint32_t pool)
4878 {
4879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880         uint32_t enable_addr = 1;
4881
4882         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4883                              pool, enable_addr);
4884 }
4885
4886 static void
4887 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4888 {
4889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890
4891         ixgbe_clear_rar(hw, index);
4892 }
4893
4894 static int
4895 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4896 {
4897         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4898
4899         ixgbe_remove_rar(dev, 0);
4900         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4901
4902         return 0;
4903 }
4904
4905 static bool
4906 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4907 {
4908         if (strcmp(dev->device->driver->name, drv->driver.name))
4909                 return false;
4910
4911         return true;
4912 }
4913
4914 bool
4915 is_ixgbe_supported(struct rte_eth_dev *dev)
4916 {
4917         return is_device_supported(dev, &rte_ixgbe_pmd);
4918 }
4919
4920 static int
4921 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4922 {
4923         uint32_t hlreg0;
4924         uint32_t maxfrs;
4925         struct ixgbe_hw *hw;
4926         struct rte_eth_dev_info dev_info;
4927         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4928         struct rte_eth_dev_data *dev_data = dev->data;
4929
4930         ixgbe_dev_info_get(dev, &dev_info);
4931
4932         /* check that mtu is within the allowed range */
4933         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4934                 return -EINVAL;
4935
4936         /* If device is started, refuse mtu that requires the support of
4937          * scattered packets when this feature has not been enabled before.
4938          */
4939         if (dev_data->dev_started && !dev_data->scattered_rx &&
4940             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4941              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4942                 PMD_INIT_LOG(ERR, "Stop port first.");
4943                 return -EINVAL;
4944         }
4945
4946         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4947         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4948
4949         /* switch to jumbo mode if needed */
4950         if (frame_size > ETHER_MAX_LEN) {
4951                 dev->data->dev_conf.rxmode.offloads |=
4952                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4953                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4954         } else {
4955                 dev->data->dev_conf.rxmode.offloads &=
4956                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4957                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4958         }
4959         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4960
4961         /* update max frame size */
4962         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4963
4964         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4965         maxfrs &= 0x0000FFFF;
4966         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4967         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4968
4969         return 0;
4970 }
4971
4972 /*
4973  * Virtual Function operations
4974  */
4975 static void
4976 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4977 {
4978         struct ixgbe_interrupt *intr =
4979                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4980         struct ixgbe_hw *hw =
4981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982
4983         PMD_INIT_FUNC_TRACE();
4984
4985         /* Clear interrupt mask to stop from interrupts being generated */
4986         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4987
4988         IXGBE_WRITE_FLUSH(hw);
4989
4990         /* Clear mask value. */
4991         intr->mask = 0;
4992 }
4993
4994 static void
4995 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4996 {
4997         struct ixgbe_interrupt *intr =
4998                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4999         struct ixgbe_hw *hw =
5000                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001
5002         PMD_INIT_FUNC_TRACE();
5003
5004         /* VF enable interrupt autoclean */
5005         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5006         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5007         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5008
5009         IXGBE_WRITE_FLUSH(hw);
5010
5011         /* Save IXGBE_VTEIMS value to mask. */
5012         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5013 }
5014
5015 static int
5016 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5017 {
5018         struct rte_eth_conf *conf = &dev->data->dev_conf;
5019         struct ixgbe_adapter *adapter =
5020                         (struct ixgbe_adapter *)dev->data->dev_private;
5021
5022         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5023                      dev->data->port_id);
5024
5025         /*
5026          * VF has no ability to enable/disable HW CRC
5027          * Keep the persistent behavior the same as Host PF
5028          */
5029 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5030         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5031                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5032                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5033         }
5034 #else
5035         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5036                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5037                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5038         }
5039 #endif
5040
5041         /*
5042          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5043          * allocation or vector Rx preconditions we will reset it.
5044          */
5045         adapter->rx_bulk_alloc_allowed = true;
5046         adapter->rx_vec_allowed = true;
5047
5048         return 0;
5049 }
5050
5051 static int
5052 ixgbevf_dev_start(struct rte_eth_dev *dev)
5053 {
5054         struct ixgbe_hw *hw =
5055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056         uint32_t intr_vector = 0;
5057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5059
5060         int err, mask = 0;
5061
5062         PMD_INIT_FUNC_TRACE();
5063
5064         err = hw->mac.ops.reset_hw(hw);
5065         if (err) {
5066                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5067                 return err;
5068         }
5069         hw->mac.get_link_status = true;
5070
5071         /* negotiate mailbox API version to use with the PF. */
5072         ixgbevf_negotiate_api(hw);
5073
5074         ixgbevf_dev_tx_init(dev);
5075
5076         /* This can fail when allocating mbufs for descriptor rings */
5077         err = ixgbevf_dev_rx_init(dev);
5078         if (err) {
5079                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5080                 ixgbe_dev_clear_queues(dev);
5081                 return err;
5082         }
5083
5084         /* Set vfta */
5085         ixgbevf_set_vfta_all(dev, 1);
5086
5087         /* Set HW strip */
5088         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5089                 ETH_VLAN_EXTEND_MASK;
5090         err = ixgbevf_vlan_offload_config(dev, mask);
5091         if (err) {
5092                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5093                 ixgbe_dev_clear_queues(dev);
5094                 return err;
5095         }
5096
5097         ixgbevf_dev_rxtx_start(dev);
5098
5099         ixgbevf_dev_link_update(dev, 0);
5100
5101         /* check and configure queue intr-vector mapping */
5102         if (rte_intr_cap_multiple(intr_handle) &&
5103             dev->data->dev_conf.intr_conf.rxq) {
5104                 /* According to datasheet, only vector 0/1/2 can be used,
5105                  * now only one vector is used for Rx queue
5106                  */
5107                 intr_vector = 1;
5108                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5109                         return -1;
5110         }
5111
5112         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5113                 intr_handle->intr_vec =
5114                         rte_zmalloc("intr_vec",
5115                                     dev->data->nb_rx_queues * sizeof(int), 0);
5116                 if (intr_handle->intr_vec == NULL) {
5117                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5118                                      " intr_vec", dev->data->nb_rx_queues);
5119                         return -ENOMEM;
5120                 }
5121         }
5122         ixgbevf_configure_msix(dev);
5123
5124         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5125          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5126          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5127          * is not cleared, it will fail when following rte_intr_enable( ) tries
5128          * to map Rx queue interrupt to other VFIO vectors.
5129          * So clear uio/vfio intr/evevnfd first to avoid failure.
5130          */
5131         rte_intr_disable(intr_handle);
5132
5133         rte_intr_enable(intr_handle);
5134
5135         /* Re-enable interrupt for VF */
5136         ixgbevf_intr_enable(dev);
5137
5138         return 0;
5139 }
5140
5141 static void
5142 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5143 {
5144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5146         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5147
5148         PMD_INIT_FUNC_TRACE();
5149
5150         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5151
5152         ixgbevf_intr_disable(dev);
5153
5154         hw->adapter_stopped = 1;
5155         ixgbe_stop_adapter(hw);
5156
5157         /*
5158           * Clear what we set, but we still keep shadow_vfta to
5159           * restore after device starts
5160           */
5161         ixgbevf_set_vfta_all(dev, 0);
5162
5163         /* Clear stored conf */
5164         dev->data->scattered_rx = 0;
5165
5166         ixgbe_dev_clear_queues(dev);
5167
5168         /* Clean datapath event and queue/vec mapping */
5169         rte_intr_efd_disable(intr_handle);
5170         if (intr_handle->intr_vec != NULL) {
5171                 rte_free(intr_handle->intr_vec);
5172                 intr_handle->intr_vec = NULL;
5173         }
5174 }
5175
5176 static void
5177 ixgbevf_dev_close(struct rte_eth_dev *dev)
5178 {
5179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180
5181         PMD_INIT_FUNC_TRACE();
5182
5183         ixgbe_reset_hw(hw);
5184
5185         ixgbevf_dev_stop(dev);
5186
5187         ixgbe_dev_free_queues(dev);
5188
5189         /**
5190          * Remove the VF MAC address ro ensure
5191          * that the VF traffic goes to the PF
5192          * after stop, close and detach of the VF
5193          **/
5194         ixgbevf_remove_mac_addr(dev, 0);
5195 }
5196
5197 /*
5198  * Reset VF device
5199  */
5200 static int
5201 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5202 {
5203         int ret;
5204
5205         ret = eth_ixgbevf_dev_uninit(dev);
5206         if (ret)
5207                 return ret;
5208
5209         ret = eth_ixgbevf_dev_init(dev);
5210
5211         return ret;
5212 }
5213
5214 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5215 {
5216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5217         struct ixgbe_vfta *shadow_vfta =
5218                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5219         int i = 0, j = 0, vfta = 0, mask = 1;
5220
5221         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5222                 vfta = shadow_vfta->vfta[i];
5223                 if (vfta) {
5224                         mask = 1;
5225                         for (j = 0; j < 32; j++) {
5226                                 if (vfta & mask)
5227                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5228                                                        on, false);
5229                                 mask <<= 1;
5230                         }
5231                 }
5232         }
5233
5234 }
5235
5236 static int
5237 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5238 {
5239         struct ixgbe_hw *hw =
5240                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5241         struct ixgbe_vfta *shadow_vfta =
5242                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5243         uint32_t vid_idx = 0;
5244         uint32_t vid_bit = 0;
5245         int ret = 0;
5246
5247         PMD_INIT_FUNC_TRACE();
5248
5249         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5250         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5251         if (ret) {
5252                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5253                 return ret;
5254         }
5255         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5256         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5257
5258         /* Save what we set and retore it after device reset */
5259         if (on)
5260                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5261         else
5262                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5263
5264         return 0;
5265 }
5266
5267 static void
5268 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5269 {
5270         struct ixgbe_hw *hw =
5271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272         uint32_t ctrl;
5273
5274         PMD_INIT_FUNC_TRACE();
5275
5276         if (queue >= hw->mac.max_rx_queues)
5277                 return;
5278
5279         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5280         if (on)
5281                 ctrl |= IXGBE_RXDCTL_VME;
5282         else
5283                 ctrl &= ~IXGBE_RXDCTL_VME;
5284         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5285
5286         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5287 }
5288
5289 static int
5290 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5291 {
5292         struct ixgbe_rx_queue *rxq;
5293         uint16_t i;
5294         int on = 0;
5295
5296         /* VF function only support hw strip feature, others are not support */
5297         if (mask & ETH_VLAN_STRIP_MASK) {
5298                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5299                         rxq = dev->data->rx_queues[i];
5300                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5301                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5302                 }
5303         }
5304
5305         return 0;
5306 }
5307
5308 static int
5309 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5310 {
5311         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5312
5313         ixgbevf_vlan_offload_config(dev, mask);
5314
5315         return 0;
5316 }
5317
5318 int
5319 ixgbe_vt_check(struct ixgbe_hw *hw)
5320 {
5321         uint32_t reg_val;
5322
5323         /* if Virtualization Technology is enabled */
5324         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5325         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5326                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5327                 return -1;
5328         }
5329
5330         return 0;
5331 }
5332
5333 static uint32_t
5334 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5335 {
5336         uint32_t vector = 0;
5337
5338         switch (hw->mac.mc_filter_type) {
5339         case 0:   /* use bits [47:36] of the address */
5340                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5341                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5342                 break;
5343         case 1:   /* use bits [46:35] of the address */
5344                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5345                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5346                 break;
5347         case 2:   /* use bits [45:34] of the address */
5348                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5349                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5350                 break;
5351         case 3:   /* use bits [43:32] of the address */
5352                 vector = ((uc_addr->addr_bytes[4]) |
5353                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5354                 break;
5355         default:  /* Invalid mc_filter_type */
5356                 break;
5357         }
5358
5359         /* vector can only be 12-bits or boundary will be exceeded */
5360         vector &= 0xFFF;
5361         return vector;
5362 }
5363
5364 static int
5365 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5366                         uint8_t on)
5367 {
5368         uint32_t vector;
5369         uint32_t uta_idx;
5370         uint32_t reg_val;
5371         uint32_t uta_shift;
5372         uint32_t rc;
5373         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5374         const uint32_t ixgbe_uta_bit_shift = 5;
5375         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5376         const uint32_t bit1 = 0x1;
5377
5378         struct ixgbe_hw *hw =
5379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5380         struct ixgbe_uta_info *uta_info =
5381                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5382
5383         /* The UTA table only exists on 82599 hardware and newer */
5384         if (hw->mac.type < ixgbe_mac_82599EB)
5385                 return -ENOTSUP;
5386
5387         vector = ixgbe_uta_vector(hw, mac_addr);
5388         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5389         uta_shift = vector & ixgbe_uta_bit_mask;
5390
5391         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5392         if (rc == on)
5393                 return 0;
5394
5395         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5396         if (on) {
5397                 uta_info->uta_in_use++;
5398                 reg_val |= (bit1 << uta_shift);
5399                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5400         } else {
5401                 uta_info->uta_in_use--;
5402                 reg_val &= ~(bit1 << uta_shift);
5403                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5404         }
5405
5406         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5407
5408         if (uta_info->uta_in_use > 0)
5409                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5410                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5411         else
5412                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5413
5414         return 0;
5415 }
5416
5417 static int
5418 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5419 {
5420         int i;
5421         struct ixgbe_hw *hw =
5422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5423         struct ixgbe_uta_info *uta_info =
5424                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5425
5426         /* The UTA table only exists on 82599 hardware and newer */
5427         if (hw->mac.type < ixgbe_mac_82599EB)
5428                 return -ENOTSUP;
5429
5430         if (on) {
5431                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5432                         uta_info->uta_shadow[i] = ~0;
5433                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5434                 }
5435         } else {
5436                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5437                         uta_info->uta_shadow[i] = 0;
5438                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5439                 }
5440         }
5441         return 0;
5442
5443 }
5444
5445 uint32_t
5446 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5447 {
5448         uint32_t new_val = orig_val;
5449
5450         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5451                 new_val |= IXGBE_VMOLR_AUPE;
5452         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5453                 new_val |= IXGBE_VMOLR_ROMPE;
5454         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5455                 new_val |= IXGBE_VMOLR_ROPE;
5456         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5457                 new_val |= IXGBE_VMOLR_BAM;
5458         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5459                 new_val |= IXGBE_VMOLR_MPE;
5460
5461         return new_val;
5462 }
5463
5464 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5465 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5466 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5467 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5468 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5469         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5470         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5471
5472 static int
5473 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5474                       struct rte_eth_mirror_conf *mirror_conf,
5475                       uint8_t rule_id, uint8_t on)
5476 {
5477         uint32_t mr_ctl, vlvf;
5478         uint32_t mp_lsb = 0;
5479         uint32_t mv_msb = 0;
5480         uint32_t mv_lsb = 0;
5481         uint32_t mp_msb = 0;
5482         uint8_t i = 0;
5483         int reg_index = 0;
5484         uint64_t vlan_mask = 0;
5485
5486         const uint8_t pool_mask_offset = 32;
5487         const uint8_t vlan_mask_offset = 32;
5488         const uint8_t dst_pool_offset = 8;
5489         const uint8_t rule_mr_offset  = 4;
5490         const uint8_t mirror_rule_mask = 0x0F;
5491
5492         struct ixgbe_mirror_info *mr_info =
5493                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5494         struct ixgbe_hw *hw =
5495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5496         uint8_t mirror_type = 0;
5497
5498         if (ixgbe_vt_check(hw) < 0)
5499                 return -ENOTSUP;
5500
5501         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5502                 return -EINVAL;
5503
5504         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5505                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5506                             mirror_conf->rule_type);
5507                 return -EINVAL;
5508         }
5509
5510         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5511                 mirror_type |= IXGBE_MRCTL_VLME;
5512                 /* Check if vlan id is valid and find conresponding VLAN ID
5513                  * index in VLVF
5514                  */
5515                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5516                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5517                                 /* search vlan id related pool vlan filter
5518                                  * index
5519                                  */
5520                                 reg_index = ixgbe_find_vlvf_slot(
5521                                                 hw,
5522                                                 mirror_conf->vlan.vlan_id[i],
5523                                                 false);
5524                                 if (reg_index < 0)
5525                                         return -EINVAL;
5526                                 vlvf = IXGBE_READ_REG(hw,
5527                                                       IXGBE_VLVF(reg_index));
5528                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5529                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5530                                       mirror_conf->vlan.vlan_id[i]))
5531                                         vlan_mask |= (1ULL << reg_index);
5532                                 else
5533                                         return -EINVAL;
5534                         }
5535                 }
5536
5537                 if (on) {
5538                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5539                         mv_msb = vlan_mask >> vlan_mask_offset;
5540
5541                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5542                                                 mirror_conf->vlan.vlan_mask;
5543                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5544                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5545                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5546                                                 mirror_conf->vlan.vlan_id[i];
5547                         }
5548                 } else {
5549                         mv_lsb = 0;
5550                         mv_msb = 0;
5551                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5552                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5553                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5554                 }
5555         }
5556
5557         /**
5558          * if enable pool mirror, write related pool mask register,if disable
5559          * pool mirror, clear PFMRVM register
5560          */
5561         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5562                 mirror_type |= IXGBE_MRCTL_VPME;
5563                 if (on) {
5564                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5565                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5566                         mr_info->mr_conf[rule_id].pool_mask =
5567                                         mirror_conf->pool_mask;
5568
5569                 } else {
5570                         mp_lsb = 0;
5571                         mp_msb = 0;
5572                         mr_info->mr_conf[rule_id].pool_mask = 0;
5573                 }
5574         }
5575         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5576                 mirror_type |= IXGBE_MRCTL_UPME;
5577         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5578                 mirror_type |= IXGBE_MRCTL_DPME;
5579
5580         /* read  mirror control register and recalculate it */
5581         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5582
5583         if (on) {
5584                 mr_ctl |= mirror_type;
5585                 mr_ctl &= mirror_rule_mask;
5586                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5587         } else {
5588                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5589         }
5590
5591         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5592         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5593
5594         /* write mirrror control  register */
5595         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5596
5597         /* write pool mirrror control  register */
5598         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5599                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5600                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5601                                 mp_msb);
5602         }
5603         /* write VLAN mirrror control  register */
5604         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5605                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5606                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5607                                 mv_msb);
5608         }
5609
5610         return 0;
5611 }
5612
5613 static int
5614 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5615 {
5616         int mr_ctl = 0;
5617         uint32_t lsb_val = 0;
5618         uint32_t msb_val = 0;
5619         const uint8_t rule_mr_offset = 4;
5620
5621         struct ixgbe_hw *hw =
5622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5623         struct ixgbe_mirror_info *mr_info =
5624                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5625
5626         if (ixgbe_vt_check(hw) < 0)
5627                 return -ENOTSUP;
5628
5629         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5630                 return -EINVAL;
5631
5632         memset(&mr_info->mr_conf[rule_id], 0,
5633                sizeof(struct rte_eth_mirror_conf));
5634
5635         /* clear PFVMCTL register */
5636         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5637
5638         /* clear pool mask register */
5639         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5640         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5641
5642         /* clear vlan mask register */
5643         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5644         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5645
5646         return 0;
5647 }
5648
5649 static int
5650 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5651 {
5652         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5653         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5654         struct ixgbe_interrupt *intr =
5655                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5656         struct ixgbe_hw *hw =
5657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5658         uint32_t vec = IXGBE_MISC_VEC_ID;
5659
5660         if (rte_intr_allow_others(intr_handle))
5661                 vec = IXGBE_RX_VEC_START;
5662         intr->mask |= (1 << vec);
5663         RTE_SET_USED(queue_id);
5664         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5665
5666         rte_intr_enable(intr_handle);
5667
5668         return 0;
5669 }
5670
5671 static int
5672 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5673 {
5674         struct ixgbe_interrupt *intr =
5675                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5676         struct ixgbe_hw *hw =
5677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5680         uint32_t vec = IXGBE_MISC_VEC_ID;
5681
5682         if (rte_intr_allow_others(intr_handle))
5683                 vec = IXGBE_RX_VEC_START;
5684         intr->mask &= ~(1 << vec);
5685         RTE_SET_USED(queue_id);
5686         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5687
5688         return 0;
5689 }
5690
5691 static int
5692 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5693 {
5694         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5695         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5696         uint32_t mask;
5697         struct ixgbe_hw *hw =
5698                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         struct ixgbe_interrupt *intr =
5700                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5701
5702         if (queue_id < 16) {
5703                 ixgbe_disable_intr(hw);
5704                 intr->mask |= (1 << queue_id);
5705                 ixgbe_enable_intr(dev);
5706         } else if (queue_id < 32) {
5707                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5708                 mask &= (1 << queue_id);
5709                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5710         } else if (queue_id < 64) {
5711                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5712                 mask &= (1 << (queue_id - 32));
5713                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5714         }
5715         rte_intr_enable(intr_handle);
5716
5717         return 0;
5718 }
5719
5720 static int
5721 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5722 {
5723         uint32_t mask;
5724         struct ixgbe_hw *hw =
5725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726         struct ixgbe_interrupt *intr =
5727                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5728
5729         if (queue_id < 16) {
5730                 ixgbe_disable_intr(hw);
5731                 intr->mask &= ~(1 << queue_id);
5732                 ixgbe_enable_intr(dev);
5733         } else if (queue_id < 32) {
5734                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5735                 mask &= ~(1 << queue_id);
5736                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5737         } else if (queue_id < 64) {
5738                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5739                 mask &= ~(1 << (queue_id - 32));
5740                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5741         }
5742
5743         return 0;
5744 }
5745
5746 static void
5747 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5748                      uint8_t queue, uint8_t msix_vector)
5749 {
5750         uint32_t tmp, idx;
5751
5752         if (direction == -1) {
5753                 /* other causes */
5754                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5755                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5756                 tmp &= ~0xFF;
5757                 tmp |= msix_vector;
5758                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5759         } else {
5760                 /* rx or tx cause */
5761                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5762                 idx = ((16 * (queue & 1)) + (8 * direction));
5763                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5764                 tmp &= ~(0xFF << idx);
5765                 tmp |= (msix_vector << idx);
5766                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5767         }
5768 }
5769
5770 /**
5771  * set the IVAR registers, mapping interrupt causes to vectors
5772  * @param hw
5773  *  pointer to ixgbe_hw struct
5774  * @direction
5775  *  0 for Rx, 1 for Tx, -1 for other causes
5776  * @queue
5777  *  queue to map the corresponding interrupt to
5778  * @msix_vector
5779  *  the vector to map to the corresponding queue
5780  */
5781 static void
5782 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5783                    uint8_t queue, uint8_t msix_vector)
5784 {
5785         uint32_t tmp, idx;
5786
5787         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5788         if (hw->mac.type == ixgbe_mac_82598EB) {
5789                 if (direction == -1)
5790                         direction = 0;
5791                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5792                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5793                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5794                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5795                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5796         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5797                         (hw->mac.type == ixgbe_mac_X540) ||
5798                         (hw->mac.type == ixgbe_mac_X550)) {
5799                 if (direction == -1) {
5800                         /* other causes */
5801                         idx = ((queue & 1) * 8);
5802                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5803                         tmp &= ~(0xFF << idx);
5804                         tmp |= (msix_vector << idx);
5805                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5806                 } else {
5807                         /* rx or tx causes */
5808                         idx = ((16 * (queue & 1)) + (8 * direction));
5809                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5810                         tmp &= ~(0xFF << idx);
5811                         tmp |= (msix_vector << idx);
5812                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5813                 }
5814         }
5815 }
5816
5817 static void
5818 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5819 {
5820         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5821         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5822         struct ixgbe_hw *hw =
5823                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824         uint32_t q_idx;
5825         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5826         uint32_t base = IXGBE_MISC_VEC_ID;
5827
5828         /* Configure VF other cause ivar */
5829         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5830
5831         /* won't configure msix register if no mapping is done
5832          * between intr vector and event fd.
5833          */
5834         if (!rte_intr_dp_is_en(intr_handle))
5835                 return;
5836
5837         if (rte_intr_allow_others(intr_handle)) {
5838                 base = IXGBE_RX_VEC_START;
5839                 vector_idx = IXGBE_RX_VEC_START;
5840         }
5841
5842         /* Configure all RX queues of VF */
5843         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5844                 /* Force all queue use vector 0,
5845                  * as IXGBE_VF_MAXMSIVECOTR = 1
5846                  */
5847                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5848                 intr_handle->intr_vec[q_idx] = vector_idx;
5849                 if (vector_idx < base + intr_handle->nb_efd - 1)
5850                         vector_idx++;
5851         }
5852
5853         /* As RX queue setting above show, all queues use the vector 0.
5854          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5855          */
5856         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5857                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5858                         | IXGBE_EITR_CNT_WDIS);
5859 }
5860
5861 /**
5862  * Sets up the hardware to properly generate MSI-X interrupts
5863  * @hw
5864  *  board private structure
5865  */
5866 static void
5867 ixgbe_configure_msix(struct rte_eth_dev *dev)
5868 {
5869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5871         struct ixgbe_hw *hw =
5872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5873         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5874         uint32_t vec = IXGBE_MISC_VEC_ID;
5875         uint32_t mask;
5876         uint32_t gpie;
5877
5878         /* won't configure msix register if no mapping is done
5879          * between intr vector and event fd
5880          * but if misx has been enabled already, need to configure
5881          * auto clean, auto mask and throttling.
5882          */
5883         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5884         if (!rte_intr_dp_is_en(intr_handle) &&
5885             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5886                 return;
5887
5888         if (rte_intr_allow_others(intr_handle))
5889                 vec = base = IXGBE_RX_VEC_START;
5890
5891         /* setup GPIE for MSI-x mode */
5892         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5893         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5894                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5895         /* auto clearing and auto setting corresponding bits in EIMS
5896          * when MSI-X interrupt is triggered
5897          */
5898         if (hw->mac.type == ixgbe_mac_82598EB) {
5899                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5900         } else {
5901                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5902                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5903         }
5904         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5905
5906         /* Populate the IVAR table and set the ITR values to the
5907          * corresponding register.
5908          */
5909         if (rte_intr_dp_is_en(intr_handle)) {
5910                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5911                         queue_id++) {
5912                         /* by default, 1:1 mapping */
5913                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5914                         intr_handle->intr_vec[queue_id] = vec;
5915                         if (vec < base + intr_handle->nb_efd - 1)
5916                                 vec++;
5917                 }
5918
5919                 switch (hw->mac.type) {
5920                 case ixgbe_mac_82598EB:
5921                         ixgbe_set_ivar_map(hw, -1,
5922                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5923                                            IXGBE_MISC_VEC_ID);
5924                         break;
5925                 case ixgbe_mac_82599EB:
5926                 case ixgbe_mac_X540:
5927                 case ixgbe_mac_X550:
5928                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5929                         break;
5930                 default:
5931                         break;
5932                 }
5933         }
5934         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5935                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5936                         | IXGBE_EITR_CNT_WDIS);
5937
5938         /* set up to autoclear timer, and the vectors */
5939         mask = IXGBE_EIMS_ENABLE_MASK;
5940         mask &= ~(IXGBE_EIMS_OTHER |
5941                   IXGBE_EIMS_MAILBOX |
5942                   IXGBE_EIMS_LSC);
5943
5944         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5945 }
5946
5947 int
5948 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5949                            uint16_t queue_idx, uint16_t tx_rate)
5950 {
5951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5952         struct rte_eth_rxmode *rxmode;
5953         uint32_t rf_dec, rf_int;
5954         uint32_t bcnrc_val;
5955         uint16_t link_speed = dev->data->dev_link.link_speed;
5956
5957         if (queue_idx >= hw->mac.max_tx_queues)
5958                 return -EINVAL;
5959
5960         if (tx_rate != 0) {
5961                 /* Calculate the rate factor values to set */
5962                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5963                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5964                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5965
5966                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5967                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5968                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5969                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5970         } else {
5971                 bcnrc_val = 0;
5972         }
5973
5974         rxmode = &dev->data->dev_conf.rxmode;
5975         /*
5976          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5977          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5978          * set as 0x4.
5979          */
5980         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5981             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5982                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5983                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5984         else
5985                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5986                         IXGBE_MMW_SIZE_DEFAULT);
5987
5988         /* Set RTTBCNRC of queue X */
5989         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5990         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5991         IXGBE_WRITE_FLUSH(hw);
5992
5993         return 0;
5994 }
5995
5996 static int
5997 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5998                      __attribute__((unused)) uint32_t index,
5999                      __attribute__((unused)) uint32_t pool)
6000 {
6001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002         int diag;
6003
6004         /*
6005          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6006          * operation. Trap this case to avoid exhausting the [very limited]
6007          * set of PF resources used to store VF MAC addresses.
6008          */
6009         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6010                 return -1;
6011         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6012         if (diag != 0)
6013                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6014                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6015                             mac_addr->addr_bytes[0],
6016                             mac_addr->addr_bytes[1],
6017                             mac_addr->addr_bytes[2],
6018                             mac_addr->addr_bytes[3],
6019                             mac_addr->addr_bytes[4],
6020                             mac_addr->addr_bytes[5],
6021                             diag);
6022         return diag;
6023 }
6024
6025 static void
6026 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6027 {
6028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6029         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6030         struct ether_addr *mac_addr;
6031         uint32_t i;
6032         int diag;
6033
6034         /*
6035          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6036          * not support the deletion of a given MAC address.
6037          * Instead, it imposes to delete all MAC addresses, then to add again
6038          * all MAC addresses with the exception of the one to be deleted.
6039          */
6040         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6041
6042         /*
6043          * Add again all MAC addresses, with the exception of the deleted one
6044          * and of the permanent MAC address.
6045          */
6046         for (i = 0, mac_addr = dev->data->mac_addrs;
6047              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6048                 /* Skip the deleted MAC address */
6049                 if (i == index)
6050                         continue;
6051                 /* Skip NULL MAC addresses */
6052                 if (is_zero_ether_addr(mac_addr))
6053                         continue;
6054                 /* Skip the permanent MAC address */
6055                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6056                         continue;
6057                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6058                 if (diag != 0)
6059                         PMD_DRV_LOG(ERR,
6060                                     "Adding again MAC address "
6061                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6062                                     "diag=%d",
6063                                     mac_addr->addr_bytes[0],
6064                                     mac_addr->addr_bytes[1],
6065                                     mac_addr->addr_bytes[2],
6066                                     mac_addr->addr_bytes[3],
6067                                     mac_addr->addr_bytes[4],
6068                                     mac_addr->addr_bytes[5],
6069                                     diag);
6070         }
6071 }
6072
6073 static int
6074 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6075 {
6076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077
6078         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6079
6080         return 0;
6081 }
6082
6083 int
6084 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6085                         struct rte_eth_syn_filter *filter,
6086                         bool add)
6087 {
6088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6089         struct ixgbe_filter_info *filter_info =
6090                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6091         uint32_t syn_info;
6092         uint32_t synqf;
6093
6094         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6095                 return -EINVAL;
6096
6097         syn_info = filter_info->syn_info;
6098
6099         if (add) {
6100                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6101                         return -EINVAL;
6102                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6103                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6104
6105                 if (filter->hig_pri)
6106                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6107                 else
6108                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6109         } else {
6110                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6111                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6112                         return -ENOENT;
6113                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6114         }
6115
6116         filter_info->syn_info = synqf;
6117         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6118         IXGBE_WRITE_FLUSH(hw);
6119         return 0;
6120 }
6121
6122 static int
6123 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6124                         struct rte_eth_syn_filter *filter)
6125 {
6126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6127         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6128
6129         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6130                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6131                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6132                 return 0;
6133         }
6134         return -ENOENT;
6135 }
6136
6137 static int
6138 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6139                         enum rte_filter_op filter_op,
6140                         void *arg)
6141 {
6142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143         int ret;
6144
6145         MAC_TYPE_FILTER_SUP(hw->mac.type);
6146
6147         if (filter_op == RTE_ETH_FILTER_NOP)
6148                 return 0;
6149
6150         if (arg == NULL) {
6151                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6152                             filter_op);
6153                 return -EINVAL;
6154         }
6155
6156         switch (filter_op) {
6157         case RTE_ETH_FILTER_ADD:
6158                 ret = ixgbe_syn_filter_set(dev,
6159                                 (struct rte_eth_syn_filter *)arg,
6160                                 TRUE);
6161                 break;
6162         case RTE_ETH_FILTER_DELETE:
6163                 ret = ixgbe_syn_filter_set(dev,
6164                                 (struct rte_eth_syn_filter *)arg,
6165                                 FALSE);
6166                 break;
6167         case RTE_ETH_FILTER_GET:
6168                 ret = ixgbe_syn_filter_get(dev,
6169                                 (struct rte_eth_syn_filter *)arg);
6170                 break;
6171         default:
6172                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6173                 ret = -EINVAL;
6174                 break;
6175         }
6176
6177         return ret;
6178 }
6179
6180
6181 static inline enum ixgbe_5tuple_protocol
6182 convert_protocol_type(uint8_t protocol_value)
6183 {
6184         if (protocol_value == IPPROTO_TCP)
6185                 return IXGBE_FILTER_PROTOCOL_TCP;
6186         else if (protocol_value == IPPROTO_UDP)
6187                 return IXGBE_FILTER_PROTOCOL_UDP;
6188         else if (protocol_value == IPPROTO_SCTP)
6189                 return IXGBE_FILTER_PROTOCOL_SCTP;
6190         else
6191                 return IXGBE_FILTER_PROTOCOL_NONE;
6192 }
6193
6194 /* inject a 5-tuple filter to HW */
6195 static inline void
6196 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6197                            struct ixgbe_5tuple_filter *filter)
6198 {
6199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6200         int i;
6201         uint32_t ftqf, sdpqf;
6202         uint32_t l34timir = 0;
6203         uint8_t mask = 0xff;
6204
6205         i = filter->index;
6206
6207         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6208                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6209         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6210
6211         ftqf = (uint32_t)(filter->filter_info.proto &
6212                 IXGBE_FTQF_PROTOCOL_MASK);
6213         ftqf |= (uint32_t)((filter->filter_info.priority &
6214                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6215         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6216                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6217         if (filter->filter_info.dst_ip_mask == 0)
6218                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6219         if (filter->filter_info.src_port_mask == 0)
6220                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6221         if (filter->filter_info.dst_port_mask == 0)
6222                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6223         if (filter->filter_info.proto_mask == 0)
6224                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6225         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6226         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6227         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6228
6229         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6230         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6231         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6232         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6233
6234         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6235         l34timir |= (uint32_t)(filter->queue <<
6236                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6237         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6238 }
6239
6240 /*
6241  * add a 5tuple filter
6242  *
6243  * @param
6244  * dev: Pointer to struct rte_eth_dev.
6245  * index: the index the filter allocates.
6246  * filter: ponter to the filter that will be added.
6247  * rx_queue: the queue id the filter assigned to.
6248  *
6249  * @return
6250  *    - On success, zero.
6251  *    - On failure, a negative value.
6252  */
6253 static int
6254 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6255                         struct ixgbe_5tuple_filter *filter)
6256 {
6257         struct ixgbe_filter_info *filter_info =
6258                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6259         int i, idx, shift;
6260
6261         /*
6262          * look for an unused 5tuple filter index,
6263          * and insert the filter to list.
6264          */
6265         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6266                 idx = i / (sizeof(uint32_t) * NBBY);
6267                 shift = i % (sizeof(uint32_t) * NBBY);
6268                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6269                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6270                         filter->index = i;
6271                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6272                                           filter,
6273                                           entries);
6274                         break;
6275                 }
6276         }
6277         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6278                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6279                 return -ENOSYS;
6280         }
6281
6282         ixgbe_inject_5tuple_filter(dev, filter);
6283
6284         return 0;
6285 }
6286
6287 /*
6288  * remove a 5tuple filter
6289  *
6290  * @param
6291  * dev: Pointer to struct rte_eth_dev.
6292  * filter: the pointer of the filter will be removed.
6293  */
6294 static void
6295 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6296                         struct ixgbe_5tuple_filter *filter)
6297 {
6298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6299         struct ixgbe_filter_info *filter_info =
6300                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6301         uint16_t index = filter->index;
6302
6303         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6304                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6305         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6306         rte_free(filter);
6307
6308         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6309         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6310         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6311         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6312         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6313 }
6314
6315 static int
6316 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6317 {
6318         struct ixgbe_hw *hw;
6319         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6320         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6321
6322         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6323
6324         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6325                 return -EINVAL;
6326
6327         /* refuse mtu that requires the support of scattered packets when this
6328          * feature has not been enabled before.
6329          */
6330         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6331             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6332              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6333                 return -EINVAL;
6334
6335         /*
6336          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6337          * request of the version 2.0 of the mailbox API.
6338          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6339          * of the mailbox API.
6340          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6341          * prior to 3.11.33 which contains the following change:
6342          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6343          */
6344         ixgbevf_rlpml_set_vf(hw, max_frame);
6345
6346         /* update max frame size */
6347         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6348         return 0;
6349 }
6350
6351 static inline struct ixgbe_5tuple_filter *
6352 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6353                         struct ixgbe_5tuple_filter_info *key)
6354 {
6355         struct ixgbe_5tuple_filter *it;
6356
6357         TAILQ_FOREACH(it, filter_list, entries) {
6358                 if (memcmp(key, &it->filter_info,
6359                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6360                         return it;
6361                 }
6362         }
6363         return NULL;
6364 }
6365
6366 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6367 static inline int
6368 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6369                         struct ixgbe_5tuple_filter_info *filter_info)
6370 {
6371         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6372                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6373                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6374                 return -EINVAL;
6375
6376         switch (filter->dst_ip_mask) {
6377         case UINT32_MAX:
6378                 filter_info->dst_ip_mask = 0;
6379                 filter_info->dst_ip = filter->dst_ip;
6380                 break;
6381         case 0:
6382                 filter_info->dst_ip_mask = 1;
6383                 break;
6384         default:
6385                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6386                 return -EINVAL;
6387         }
6388
6389         switch (filter->src_ip_mask) {
6390         case UINT32_MAX:
6391                 filter_info->src_ip_mask = 0;
6392                 filter_info->src_ip = filter->src_ip;
6393                 break;
6394         case 0:
6395                 filter_info->src_ip_mask = 1;
6396                 break;
6397         default:
6398                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6399                 return -EINVAL;
6400         }
6401
6402         switch (filter->dst_port_mask) {
6403         case UINT16_MAX:
6404                 filter_info->dst_port_mask = 0;
6405                 filter_info->dst_port = filter->dst_port;
6406                 break;
6407         case 0:
6408                 filter_info->dst_port_mask = 1;
6409                 break;
6410         default:
6411                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6412                 return -EINVAL;
6413         }
6414
6415         switch (filter->src_port_mask) {
6416         case UINT16_MAX:
6417                 filter_info->src_port_mask = 0;
6418                 filter_info->src_port = filter->src_port;
6419                 break;
6420         case 0:
6421                 filter_info->src_port_mask = 1;
6422                 break;
6423         default:
6424                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6425                 return -EINVAL;
6426         }
6427
6428         switch (filter->proto_mask) {
6429         case UINT8_MAX:
6430                 filter_info->proto_mask = 0;
6431                 filter_info->proto =
6432                         convert_protocol_type(filter->proto);
6433                 break;
6434         case 0:
6435                 filter_info->proto_mask = 1;
6436                 break;
6437         default:
6438                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6439                 return -EINVAL;
6440         }
6441
6442         filter_info->priority = (uint8_t)filter->priority;
6443         return 0;
6444 }
6445
6446 /*
6447  * add or delete a ntuple filter
6448  *
6449  * @param
6450  * dev: Pointer to struct rte_eth_dev.
6451  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6452  * add: if true, add filter, if false, remove filter
6453  *
6454  * @return
6455  *    - On success, zero.
6456  *    - On failure, a negative value.
6457  */
6458 int
6459 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6460                         struct rte_eth_ntuple_filter *ntuple_filter,
6461                         bool add)
6462 {
6463         struct ixgbe_filter_info *filter_info =
6464                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6465         struct ixgbe_5tuple_filter_info filter_5tuple;
6466         struct ixgbe_5tuple_filter *filter;
6467         int ret;
6468
6469         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6470                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6471                 return -EINVAL;
6472         }
6473
6474         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6475         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6476         if (ret < 0)
6477                 return ret;
6478
6479         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6480                                          &filter_5tuple);
6481         if (filter != NULL && add) {
6482                 PMD_DRV_LOG(ERR, "filter exists.");
6483                 return -EEXIST;
6484         }
6485         if (filter == NULL && !add) {
6486                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6487                 return -ENOENT;
6488         }
6489
6490         if (add) {
6491                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6492                                 sizeof(struct ixgbe_5tuple_filter), 0);
6493                 if (filter == NULL)
6494                         return -ENOMEM;
6495                 rte_memcpy(&filter->filter_info,
6496                                  &filter_5tuple,
6497                                  sizeof(struct ixgbe_5tuple_filter_info));
6498                 filter->queue = ntuple_filter->queue;
6499                 ret = ixgbe_add_5tuple_filter(dev, filter);
6500                 if (ret < 0) {
6501                         rte_free(filter);
6502                         return ret;
6503                 }
6504         } else
6505                 ixgbe_remove_5tuple_filter(dev, filter);
6506
6507         return 0;
6508 }
6509
6510 /*
6511  * get a ntuple filter
6512  *
6513  * @param
6514  * dev: Pointer to struct rte_eth_dev.
6515  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6516  *
6517  * @return
6518  *    - On success, zero.
6519  *    - On failure, a negative value.
6520  */
6521 static int
6522 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6523                         struct rte_eth_ntuple_filter *ntuple_filter)
6524 {
6525         struct ixgbe_filter_info *filter_info =
6526                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6527         struct ixgbe_5tuple_filter_info filter_5tuple;
6528         struct ixgbe_5tuple_filter *filter;
6529         int ret;
6530
6531         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6532                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6533                 return -EINVAL;
6534         }
6535
6536         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6537         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6538         if (ret < 0)
6539                 return ret;
6540
6541         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6542                                          &filter_5tuple);
6543         if (filter == NULL) {
6544                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6545                 return -ENOENT;
6546         }
6547         ntuple_filter->queue = filter->queue;
6548         return 0;
6549 }
6550
6551 /*
6552  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6553  * @dev: pointer to rte_eth_dev structure
6554  * @filter_op:operation will be taken.
6555  * @arg: a pointer to specific structure corresponding to the filter_op
6556  *
6557  * @return
6558  *    - On success, zero.
6559  *    - On failure, a negative value.
6560  */
6561 static int
6562 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6563                                 enum rte_filter_op filter_op,
6564                                 void *arg)
6565 {
6566         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6567         int ret;
6568
6569         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6570
6571         if (filter_op == RTE_ETH_FILTER_NOP)
6572                 return 0;
6573
6574         if (arg == NULL) {
6575                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6576                             filter_op);
6577                 return -EINVAL;
6578         }
6579
6580         switch (filter_op) {
6581         case RTE_ETH_FILTER_ADD:
6582                 ret = ixgbe_add_del_ntuple_filter(dev,
6583                         (struct rte_eth_ntuple_filter *)arg,
6584                         TRUE);
6585                 break;
6586         case RTE_ETH_FILTER_DELETE:
6587                 ret = ixgbe_add_del_ntuple_filter(dev,
6588                         (struct rte_eth_ntuple_filter *)arg,
6589                         FALSE);
6590                 break;
6591         case RTE_ETH_FILTER_GET:
6592                 ret = ixgbe_get_ntuple_filter(dev,
6593                         (struct rte_eth_ntuple_filter *)arg);
6594                 break;
6595         default:
6596                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6597                 ret = -EINVAL;
6598                 break;
6599         }
6600         return ret;
6601 }
6602
6603 int
6604 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6605                         struct rte_eth_ethertype_filter *filter,
6606                         bool add)
6607 {
6608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609         struct ixgbe_filter_info *filter_info =
6610                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6611         uint32_t etqf = 0;
6612         uint32_t etqs = 0;
6613         int ret;
6614         struct ixgbe_ethertype_filter ethertype_filter;
6615
6616         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6617                 return -EINVAL;
6618
6619         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6620                 filter->ether_type == ETHER_TYPE_IPv6) {
6621                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6622                         " ethertype filter.", filter->ether_type);
6623                 return -EINVAL;
6624         }
6625
6626         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6627                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6628                 return -EINVAL;
6629         }
6630         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6631                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6632                 return -EINVAL;
6633         }
6634
6635         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6636         if (ret >= 0 && add) {
6637                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6638                             filter->ether_type);
6639                 return -EEXIST;
6640         }
6641         if (ret < 0 && !add) {
6642                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6643                             filter->ether_type);
6644                 return -ENOENT;
6645         }
6646
6647         if (add) {
6648                 etqf = IXGBE_ETQF_FILTER_EN;
6649                 etqf |= (uint32_t)filter->ether_type;
6650                 etqs |= (uint32_t)((filter->queue <<
6651                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6652                                     IXGBE_ETQS_RX_QUEUE);
6653                 etqs |= IXGBE_ETQS_QUEUE_EN;
6654
6655                 ethertype_filter.ethertype = filter->ether_type;
6656                 ethertype_filter.etqf = etqf;
6657                 ethertype_filter.etqs = etqs;
6658                 ethertype_filter.conf = FALSE;
6659                 ret = ixgbe_ethertype_filter_insert(filter_info,
6660                                                     &ethertype_filter);
6661                 if (ret < 0) {
6662                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6663                         return -ENOSPC;
6664                 }
6665         } else {
6666                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6667                 if (ret < 0)
6668                         return -ENOSYS;
6669         }
6670         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6671         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6672         IXGBE_WRITE_FLUSH(hw);
6673
6674         return 0;
6675 }
6676
6677 static int
6678 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6679                         struct rte_eth_ethertype_filter *filter)
6680 {
6681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         struct ixgbe_filter_info *filter_info =
6683                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6684         uint32_t etqf, etqs;
6685         int ret;
6686
6687         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6688         if (ret < 0) {
6689                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6690                             filter->ether_type);
6691                 return -ENOENT;
6692         }
6693
6694         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6695         if (etqf & IXGBE_ETQF_FILTER_EN) {
6696                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6697                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6698                 filter->flags = 0;
6699                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6700                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6701                 return 0;
6702         }
6703         return -ENOENT;
6704 }
6705
6706 /*
6707  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6708  * @dev: pointer to rte_eth_dev structure
6709  * @filter_op:operation will be taken.
6710  * @arg: a pointer to specific structure corresponding to the filter_op
6711  */
6712 static int
6713 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6714                                 enum rte_filter_op filter_op,
6715                                 void *arg)
6716 {
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         int ret;
6719
6720         MAC_TYPE_FILTER_SUP(hw->mac.type);
6721
6722         if (filter_op == RTE_ETH_FILTER_NOP)
6723                 return 0;
6724
6725         if (arg == NULL) {
6726                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6727                             filter_op);
6728                 return -EINVAL;
6729         }
6730
6731         switch (filter_op) {
6732         case RTE_ETH_FILTER_ADD:
6733                 ret = ixgbe_add_del_ethertype_filter(dev,
6734                         (struct rte_eth_ethertype_filter *)arg,
6735                         TRUE);
6736                 break;
6737         case RTE_ETH_FILTER_DELETE:
6738                 ret = ixgbe_add_del_ethertype_filter(dev,
6739                         (struct rte_eth_ethertype_filter *)arg,
6740                         FALSE);
6741                 break;
6742         case RTE_ETH_FILTER_GET:
6743                 ret = ixgbe_get_ethertype_filter(dev,
6744                         (struct rte_eth_ethertype_filter *)arg);
6745                 break;
6746         default:
6747                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6748                 ret = -EINVAL;
6749                 break;
6750         }
6751         return ret;
6752 }
6753
6754 static int
6755 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6756                      enum rte_filter_type filter_type,
6757                      enum rte_filter_op filter_op,
6758                      void *arg)
6759 {
6760         int ret = 0;
6761
6762         switch (filter_type) {
6763         case RTE_ETH_FILTER_NTUPLE:
6764                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6765                 break;
6766         case RTE_ETH_FILTER_ETHERTYPE:
6767                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6768                 break;
6769         case RTE_ETH_FILTER_SYN:
6770                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6771                 break;
6772         case RTE_ETH_FILTER_FDIR:
6773                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6774                 break;
6775         case RTE_ETH_FILTER_L2_TUNNEL:
6776                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6777                 break;
6778         case RTE_ETH_FILTER_GENERIC:
6779                 if (filter_op != RTE_ETH_FILTER_GET)
6780                         return -EINVAL;
6781                 *(const void **)arg = &ixgbe_flow_ops;
6782                 break;
6783         default:
6784                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6785                                                         filter_type);
6786                 ret = -EINVAL;
6787                 break;
6788         }
6789
6790         return ret;
6791 }
6792
6793 static u8 *
6794 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6795                         u8 **mc_addr_ptr, u32 *vmdq)
6796 {
6797         u8 *mc_addr;
6798
6799         *vmdq = 0;
6800         mc_addr = *mc_addr_ptr;
6801         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6802         return mc_addr;
6803 }
6804
6805 static int
6806 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6807                           struct ether_addr *mc_addr_set,
6808                           uint32_t nb_mc_addr)
6809 {
6810         struct ixgbe_hw *hw;
6811         u8 *mc_addr_list;
6812
6813         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6814         mc_addr_list = (u8 *)mc_addr_set;
6815         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6816                                          ixgbe_dev_addr_list_itr, TRUE);
6817 }
6818
6819 static uint64_t
6820 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6821 {
6822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6823         uint64_t systime_cycles;
6824
6825         switch (hw->mac.type) {
6826         case ixgbe_mac_X550:
6827         case ixgbe_mac_X550EM_x:
6828         case ixgbe_mac_X550EM_a:
6829                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6830                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6831                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6832                                 * NSEC_PER_SEC;
6833                 break;
6834         default:
6835                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6836                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6837                                 << 32;
6838         }
6839
6840         return systime_cycles;
6841 }
6842
6843 static uint64_t
6844 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6845 {
6846         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6847         uint64_t rx_tstamp_cycles;
6848
6849         switch (hw->mac.type) {
6850         case ixgbe_mac_X550:
6851         case ixgbe_mac_X550EM_x:
6852         case ixgbe_mac_X550EM_a:
6853                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6854                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6855                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6856                                 * NSEC_PER_SEC;
6857                 break;
6858         default:
6859                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6860                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6861                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6862                                 << 32;
6863         }
6864
6865         return rx_tstamp_cycles;
6866 }
6867
6868 static uint64_t
6869 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6870 {
6871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872         uint64_t tx_tstamp_cycles;
6873
6874         switch (hw->mac.type) {
6875         case ixgbe_mac_X550:
6876         case ixgbe_mac_X550EM_x:
6877         case ixgbe_mac_X550EM_a:
6878                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6879                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6880                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6881                                 * NSEC_PER_SEC;
6882                 break;
6883         default:
6884                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6885                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6886                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6887                                 << 32;
6888         }
6889
6890         return tx_tstamp_cycles;
6891 }
6892
6893 static void
6894 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         struct ixgbe_adapter *adapter =
6898                 (struct ixgbe_adapter *)dev->data->dev_private;
6899         struct rte_eth_link link;
6900         uint32_t incval = 0;
6901         uint32_t shift = 0;
6902
6903         /* Get current link speed. */
6904         ixgbe_dev_link_update(dev, 1);
6905         rte_eth_linkstatus_get(dev, &link);
6906
6907         switch (link.link_speed) {
6908         case ETH_SPEED_NUM_100M:
6909                 incval = IXGBE_INCVAL_100;
6910                 shift = IXGBE_INCVAL_SHIFT_100;
6911                 break;
6912         case ETH_SPEED_NUM_1G:
6913                 incval = IXGBE_INCVAL_1GB;
6914                 shift = IXGBE_INCVAL_SHIFT_1GB;
6915                 break;
6916         case ETH_SPEED_NUM_10G:
6917         default:
6918                 incval = IXGBE_INCVAL_10GB;
6919                 shift = IXGBE_INCVAL_SHIFT_10GB;
6920                 break;
6921         }
6922
6923         switch (hw->mac.type) {
6924         case ixgbe_mac_X550:
6925         case ixgbe_mac_X550EM_x:
6926         case ixgbe_mac_X550EM_a:
6927                 /* Independent of link speed. */
6928                 incval = 1;
6929                 /* Cycles read will be interpreted as ns. */
6930                 shift = 0;
6931                 /* Fall-through */
6932         case ixgbe_mac_X540:
6933                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6934                 break;
6935         case ixgbe_mac_82599EB:
6936                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6937                 shift -= IXGBE_INCVAL_SHIFT_82599;
6938                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6939                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6940                 break;
6941         default:
6942                 /* Not supported. */
6943                 return;
6944         }
6945
6946         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6947         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6948         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6949
6950         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6951         adapter->systime_tc.cc_shift = shift;
6952         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6953
6954         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6955         adapter->rx_tstamp_tc.cc_shift = shift;
6956         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6957
6958         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6959         adapter->tx_tstamp_tc.cc_shift = shift;
6960         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6961 }
6962
6963 static int
6964 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6965 {
6966         struct ixgbe_adapter *adapter =
6967                         (struct ixgbe_adapter *)dev->data->dev_private;
6968
6969         adapter->systime_tc.nsec += delta;
6970         adapter->rx_tstamp_tc.nsec += delta;
6971         adapter->tx_tstamp_tc.nsec += delta;
6972
6973         return 0;
6974 }
6975
6976 static int
6977 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6978 {
6979         uint64_t ns;
6980         struct ixgbe_adapter *adapter =
6981                         (struct ixgbe_adapter *)dev->data->dev_private;
6982
6983         ns = rte_timespec_to_ns(ts);
6984         /* Set the timecounters to a new value. */
6985         adapter->systime_tc.nsec = ns;
6986         adapter->rx_tstamp_tc.nsec = ns;
6987         adapter->tx_tstamp_tc.nsec = ns;
6988
6989         return 0;
6990 }
6991
6992 static int
6993 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6994 {
6995         uint64_t ns, systime_cycles;
6996         struct ixgbe_adapter *adapter =
6997                         (struct ixgbe_adapter *)dev->data->dev_private;
6998
6999         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7000         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7001         *ts = rte_ns_to_timespec(ns);
7002
7003         return 0;
7004 }
7005
7006 static int
7007 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7008 {
7009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7010         uint32_t tsync_ctl;
7011         uint32_t tsauxc;
7012
7013         /* Stop the timesync system time. */
7014         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7015         /* Reset the timesync system time value. */
7016         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7017         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7018
7019         /* Enable system time for platforms where it isn't on by default. */
7020         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7021         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7022         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7023
7024         ixgbe_start_timecounters(dev);
7025
7026         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7027         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7028                         (ETHER_TYPE_1588 |
7029                          IXGBE_ETQF_FILTER_EN |
7030                          IXGBE_ETQF_1588));
7031
7032         /* Enable timestamping of received PTP packets. */
7033         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7034         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7035         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7036
7037         /* Enable timestamping of transmitted PTP packets. */
7038         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7039         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7040         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7041
7042         IXGBE_WRITE_FLUSH(hw);
7043
7044         return 0;
7045 }
7046
7047 static int
7048 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7049 {
7050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051         uint32_t tsync_ctl;
7052
7053         /* Disable timestamping of transmitted PTP packets. */
7054         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7055         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7056         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7057
7058         /* Disable timestamping of received PTP packets. */
7059         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7060         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7061         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7062
7063         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7064         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7065
7066         /* Stop incrementating the System Time registers. */
7067         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7068
7069         return 0;
7070 }
7071
7072 static int
7073 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7074                                  struct timespec *timestamp,
7075                                  uint32_t flags __rte_unused)
7076 {
7077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7078         struct ixgbe_adapter *adapter =
7079                 (struct ixgbe_adapter *)dev->data->dev_private;
7080         uint32_t tsync_rxctl;
7081         uint64_t rx_tstamp_cycles;
7082         uint64_t ns;
7083
7084         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7085         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7086                 return -EINVAL;
7087
7088         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7089         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7090         *timestamp = rte_ns_to_timespec(ns);
7091
7092         return  0;
7093 }
7094
7095 static int
7096 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7097                                  struct timespec *timestamp)
7098 {
7099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7100         struct ixgbe_adapter *adapter =
7101                 (struct ixgbe_adapter *)dev->data->dev_private;
7102         uint32_t tsync_txctl;
7103         uint64_t tx_tstamp_cycles;
7104         uint64_t ns;
7105
7106         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7107         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7108                 return -EINVAL;
7109
7110         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7111         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7112         *timestamp = rte_ns_to_timespec(ns);
7113
7114         return 0;
7115 }
7116
7117 static int
7118 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7119 {
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121         int count = 0;
7122         int g_ind = 0;
7123         const struct reg_info *reg_group;
7124         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7125                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7126
7127         while ((reg_group = reg_set[g_ind++]))
7128                 count += ixgbe_regs_group_count(reg_group);
7129
7130         return count;
7131 }
7132
7133 static int
7134 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7135 {
7136         int count = 0;
7137         int g_ind = 0;
7138         const struct reg_info *reg_group;
7139
7140         while ((reg_group = ixgbevf_regs[g_ind++]))
7141                 count += ixgbe_regs_group_count(reg_group);
7142
7143         return count;
7144 }
7145
7146 static int
7147 ixgbe_get_regs(struct rte_eth_dev *dev,
7148               struct rte_dev_reg_info *regs)
7149 {
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151         uint32_t *data = regs->data;
7152         int g_ind = 0;
7153         int count = 0;
7154         const struct reg_info *reg_group;
7155         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7156                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7157
7158         if (data == NULL) {
7159                 regs->length = ixgbe_get_reg_length(dev);
7160                 regs->width = sizeof(uint32_t);
7161                 return 0;
7162         }
7163
7164         /* Support only full register dump */
7165         if ((regs->length == 0) ||
7166             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7167                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7168                         hw->device_id;
7169                 while ((reg_group = reg_set[g_ind++]))
7170                         count += ixgbe_read_regs_group(dev, &data[count],
7171                                 reg_group);
7172                 return 0;
7173         }
7174
7175         return -ENOTSUP;
7176 }
7177
7178 static int
7179 ixgbevf_get_regs(struct rte_eth_dev *dev,
7180                 struct rte_dev_reg_info *regs)
7181 {
7182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183         uint32_t *data = regs->data;
7184         int g_ind = 0;
7185         int count = 0;
7186         const struct reg_info *reg_group;
7187
7188         if (data == NULL) {
7189                 regs->length = ixgbevf_get_reg_length(dev);
7190                 regs->width = sizeof(uint32_t);
7191                 return 0;
7192         }
7193
7194         /* Support only full register dump */
7195         if ((regs->length == 0) ||
7196             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7197                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7198                         hw->device_id;
7199                 while ((reg_group = ixgbevf_regs[g_ind++]))
7200                         count += ixgbe_read_regs_group(dev, &data[count],
7201                                                       reg_group);
7202                 return 0;
7203         }
7204
7205         return -ENOTSUP;
7206 }
7207
7208 static int
7209 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7210 {
7211         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7212
7213         /* Return unit is byte count */
7214         return hw->eeprom.word_size * 2;
7215 }
7216
7217 static int
7218 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7219                 struct rte_dev_eeprom_info *in_eeprom)
7220 {
7221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7223         uint16_t *data = in_eeprom->data;
7224         int first, length;
7225
7226         first = in_eeprom->offset >> 1;
7227         length = in_eeprom->length >> 1;
7228         if ((first > hw->eeprom.word_size) ||
7229             ((first + length) > hw->eeprom.word_size))
7230                 return -EINVAL;
7231
7232         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7233
7234         return eeprom->ops.read_buffer(hw, first, length, data);
7235 }
7236
7237 static int
7238 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7239                 struct rte_dev_eeprom_info *in_eeprom)
7240 {
7241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7242         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7243         uint16_t *data = in_eeprom->data;
7244         int first, length;
7245
7246         first = in_eeprom->offset >> 1;
7247         length = in_eeprom->length >> 1;
7248         if ((first > hw->eeprom.word_size) ||
7249             ((first + length) > hw->eeprom.word_size))
7250                 return -EINVAL;
7251
7252         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7253
7254         return eeprom->ops.write_buffer(hw,  first, length, data);
7255 }
7256
7257 static int
7258 ixgbe_get_module_info(struct rte_eth_dev *dev,
7259                       struct rte_eth_dev_module_info *modinfo)
7260 {
7261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         uint32_t status;
7263         uint8_t sff8472_rev, addr_mode;
7264         bool page_swap = false;
7265
7266         /* Check whether we support SFF-8472 or not */
7267         status = hw->phy.ops.read_i2c_eeprom(hw,
7268                                              IXGBE_SFF_SFF_8472_COMP,
7269                                              &sff8472_rev);
7270         if (status != 0)
7271                 return -EIO;
7272
7273         /* addressing mode is not supported */
7274         status = hw->phy.ops.read_i2c_eeprom(hw,
7275                                              IXGBE_SFF_SFF_8472_SWAP,
7276                                              &addr_mode);
7277         if (status != 0)
7278                 return -EIO;
7279
7280         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7281                 PMD_DRV_LOG(ERR,
7282                             "Address change required to access page 0xA2, "
7283                             "but not supported. Please report the module "
7284                             "type to the driver maintainers.");
7285                 page_swap = true;
7286         }
7287
7288         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7289                 /* We have a SFP, but it does not support SFF-8472 */
7290                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7291                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7292         } else {
7293                 /* We have a SFP which supports a revision of SFF-8472. */
7294                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7295                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7296         }
7297
7298         return 0;
7299 }
7300
7301 static int
7302 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7303                         struct rte_dev_eeprom_info *info)
7304 {
7305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7306         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7307         uint8_t databyte = 0xFF;
7308         uint8_t *data = info->data;
7309         uint32_t i = 0;
7310
7311         if (info->length == 0)
7312                 return -EINVAL;
7313
7314         for (i = info->offset; i < info->offset + info->length; i++) {
7315                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7316                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7317                 else
7318                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7319
7320                 if (status != 0)
7321                         return -EIO;
7322
7323                 data[i - info->offset] = databyte;
7324         }
7325
7326         return 0;
7327 }
7328
7329 uint16_t
7330 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7331         switch (mac_type) {
7332         case ixgbe_mac_X550:
7333         case ixgbe_mac_X550EM_x:
7334         case ixgbe_mac_X550EM_a:
7335                 return ETH_RSS_RETA_SIZE_512;
7336         case ixgbe_mac_X550_vf:
7337         case ixgbe_mac_X550EM_x_vf:
7338         case ixgbe_mac_X550EM_a_vf:
7339                 return ETH_RSS_RETA_SIZE_64;
7340         default:
7341                 return ETH_RSS_RETA_SIZE_128;
7342         }
7343 }
7344
7345 uint32_t
7346 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7347         switch (mac_type) {
7348         case ixgbe_mac_X550:
7349         case ixgbe_mac_X550EM_x:
7350         case ixgbe_mac_X550EM_a:
7351                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7352                         return IXGBE_RETA(reta_idx >> 2);
7353                 else
7354                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7355         case ixgbe_mac_X550_vf:
7356         case ixgbe_mac_X550EM_x_vf:
7357         case ixgbe_mac_X550EM_a_vf:
7358                 return IXGBE_VFRETA(reta_idx >> 2);
7359         default:
7360                 return IXGBE_RETA(reta_idx >> 2);
7361         }
7362 }
7363
7364 uint32_t
7365 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7366         switch (mac_type) {
7367         case ixgbe_mac_X550_vf:
7368         case ixgbe_mac_X550EM_x_vf:
7369         case ixgbe_mac_X550EM_a_vf:
7370                 return IXGBE_VFMRQC;
7371         default:
7372                 return IXGBE_MRQC;
7373         }
7374 }
7375
7376 uint32_t
7377 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7378         switch (mac_type) {
7379         case ixgbe_mac_X550_vf:
7380         case ixgbe_mac_X550EM_x_vf:
7381         case ixgbe_mac_X550EM_a_vf:
7382                 return IXGBE_VFRSSRK(i);
7383         default:
7384                 return IXGBE_RSSRK(i);
7385         }
7386 }
7387
7388 bool
7389 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7390         switch (mac_type) {
7391         case ixgbe_mac_82599_vf:
7392         case ixgbe_mac_X540_vf:
7393                 return 0;
7394         default:
7395                 return 1;
7396         }
7397 }
7398
7399 static int
7400 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7401                         struct rte_eth_dcb_info *dcb_info)
7402 {
7403         struct ixgbe_dcb_config *dcb_config =
7404                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7405         struct ixgbe_dcb_tc_config *tc;
7406         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7407         uint8_t nb_tcs;
7408         uint8_t i, j;
7409
7410         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7411                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7412         else
7413                 dcb_info->nb_tcs = 1;
7414
7415         tc_queue = &dcb_info->tc_queue;
7416         nb_tcs = dcb_info->nb_tcs;
7417
7418         if (dcb_config->vt_mode) { /* vt is enabled*/
7419                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7420                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7421                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7422                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7423                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7424                         for (j = 0; j < nb_tcs; j++) {
7425                                 tc_queue->tc_rxq[0][j].base = j;
7426                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7427                                 tc_queue->tc_txq[0][j].base = j;
7428                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7429                         }
7430                 } else {
7431                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7432                                 for (j = 0; j < nb_tcs; j++) {
7433                                         tc_queue->tc_rxq[i][j].base =
7434                                                 i * nb_tcs + j;
7435                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7436                                         tc_queue->tc_txq[i][j].base =
7437                                                 i * nb_tcs + j;
7438                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7439                                 }
7440                         }
7441                 }
7442         } else { /* vt is disabled*/
7443                 struct rte_eth_dcb_rx_conf *rx_conf =
7444                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7445                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7446                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7447                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7448                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7449                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7450                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7451                         }
7452                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7453                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7454                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7455                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7456                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7457                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7458                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7459                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7460                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7461                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7462                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7463                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7464                         }
7465                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7466                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7467                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7468                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7469                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7470                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7471                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7472                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7473                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7474                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7475                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7476                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7477                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7478                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7479                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7480                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7481                 }
7482         }
7483         for (i = 0; i < dcb_info->nb_tcs; i++) {
7484                 tc = &dcb_config->tc_config[i];
7485                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7486         }
7487         return 0;
7488 }
7489
7490 /* Update e-tag ether type */
7491 static int
7492 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7493                             uint16_t ether_type)
7494 {
7495         uint32_t etag_etype;
7496
7497         if (hw->mac.type != ixgbe_mac_X550 &&
7498             hw->mac.type != ixgbe_mac_X550EM_x &&
7499             hw->mac.type != ixgbe_mac_X550EM_a) {
7500                 return -ENOTSUP;
7501         }
7502
7503         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7504         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7505         etag_etype |= ether_type;
7506         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7507         IXGBE_WRITE_FLUSH(hw);
7508
7509         return 0;
7510 }
7511
7512 /* Config l2 tunnel ether type */
7513 static int
7514 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7515                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7516 {
7517         int ret = 0;
7518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7519         struct ixgbe_l2_tn_info *l2_tn_info =
7520                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7521
7522         if (l2_tunnel == NULL)
7523                 return -EINVAL;
7524
7525         switch (l2_tunnel->l2_tunnel_type) {
7526         case RTE_L2_TUNNEL_TYPE_E_TAG:
7527                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7528                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7529                 break;
7530         default:
7531                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7532                 ret = -EINVAL;
7533                 break;
7534         }
7535
7536         return ret;
7537 }
7538
7539 /* Enable e-tag tunnel */
7540 static int
7541 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7542 {
7543         uint32_t etag_etype;
7544
7545         if (hw->mac.type != ixgbe_mac_X550 &&
7546             hw->mac.type != ixgbe_mac_X550EM_x &&
7547             hw->mac.type != ixgbe_mac_X550EM_a) {
7548                 return -ENOTSUP;
7549         }
7550
7551         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7552         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7553         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7554         IXGBE_WRITE_FLUSH(hw);
7555
7556         return 0;
7557 }
7558
7559 /* Enable l2 tunnel */
7560 static int
7561 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7562                            enum rte_eth_tunnel_type l2_tunnel_type)
7563 {
7564         int ret = 0;
7565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7566         struct ixgbe_l2_tn_info *l2_tn_info =
7567                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7568
7569         switch (l2_tunnel_type) {
7570         case RTE_L2_TUNNEL_TYPE_E_TAG:
7571                 l2_tn_info->e_tag_en = TRUE;
7572                 ret = ixgbe_e_tag_enable(hw);
7573                 break;
7574         default:
7575                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7576                 ret = -EINVAL;
7577                 break;
7578         }
7579
7580         return ret;
7581 }
7582
7583 /* Disable e-tag tunnel */
7584 static int
7585 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7586 {
7587         uint32_t etag_etype;
7588
7589         if (hw->mac.type != ixgbe_mac_X550 &&
7590             hw->mac.type != ixgbe_mac_X550EM_x &&
7591             hw->mac.type != ixgbe_mac_X550EM_a) {
7592                 return -ENOTSUP;
7593         }
7594
7595         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7596         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7597         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7598         IXGBE_WRITE_FLUSH(hw);
7599
7600         return 0;
7601 }
7602
7603 /* Disable l2 tunnel */
7604 static int
7605 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7606                             enum rte_eth_tunnel_type l2_tunnel_type)
7607 {
7608         int ret = 0;
7609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7610         struct ixgbe_l2_tn_info *l2_tn_info =
7611                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7612
7613         switch (l2_tunnel_type) {
7614         case RTE_L2_TUNNEL_TYPE_E_TAG:
7615                 l2_tn_info->e_tag_en = FALSE;
7616                 ret = ixgbe_e_tag_disable(hw);
7617                 break;
7618         default:
7619                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7620                 ret = -EINVAL;
7621                 break;
7622         }
7623
7624         return ret;
7625 }
7626
7627 static int
7628 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7629                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7630 {
7631         int ret = 0;
7632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7633         uint32_t i, rar_entries;
7634         uint32_t rar_low, rar_high;
7635
7636         if (hw->mac.type != ixgbe_mac_X550 &&
7637             hw->mac.type != ixgbe_mac_X550EM_x &&
7638             hw->mac.type != ixgbe_mac_X550EM_a) {
7639                 return -ENOTSUP;
7640         }
7641
7642         rar_entries = ixgbe_get_num_rx_addrs(hw);
7643
7644         for (i = 1; i < rar_entries; i++) {
7645                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7646                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7647                 if ((rar_high & IXGBE_RAH_AV) &&
7648                     (rar_high & IXGBE_RAH_ADTYPE) &&
7649                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7650                      l2_tunnel->tunnel_id)) {
7651                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7652                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7653
7654                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7655
7656                         return ret;
7657                 }
7658         }
7659
7660         return ret;
7661 }
7662
7663 static int
7664 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7665                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7666 {
7667         int ret = 0;
7668         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7669         uint32_t i, rar_entries;
7670         uint32_t rar_low, rar_high;
7671
7672         if (hw->mac.type != ixgbe_mac_X550 &&
7673             hw->mac.type != ixgbe_mac_X550EM_x &&
7674             hw->mac.type != ixgbe_mac_X550EM_a) {
7675                 return -ENOTSUP;
7676         }
7677
7678         /* One entry for one tunnel. Try to remove potential existing entry. */
7679         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7680
7681         rar_entries = ixgbe_get_num_rx_addrs(hw);
7682
7683         for (i = 1; i < rar_entries; i++) {
7684                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7685                 if (rar_high & IXGBE_RAH_AV) {
7686                         continue;
7687                 } else {
7688                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7689                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7690                         rar_low = l2_tunnel->tunnel_id;
7691
7692                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7693                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7694
7695                         return ret;
7696                 }
7697         }
7698
7699         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7700                      " Please remove a rule before adding a new one.");
7701         return -EINVAL;
7702 }
7703
7704 static inline struct ixgbe_l2_tn_filter *
7705 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7706                           struct ixgbe_l2_tn_key *key)
7707 {
7708         int ret;
7709
7710         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7711         if (ret < 0)
7712                 return NULL;
7713
7714         return l2_tn_info->hash_map[ret];
7715 }
7716
7717 static inline int
7718 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7719                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7720 {
7721         int ret;
7722
7723         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7724                                &l2_tn_filter->key);
7725
7726         if (ret < 0) {
7727                 PMD_DRV_LOG(ERR,
7728                             "Failed to insert L2 tunnel filter"
7729                             " to hash table %d!",
7730                             ret);
7731                 return ret;
7732         }
7733
7734         l2_tn_info->hash_map[ret] = l2_tn_filter;
7735
7736         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7737
7738         return 0;
7739 }
7740
7741 static inline int
7742 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7743                           struct ixgbe_l2_tn_key *key)
7744 {
7745         int ret;
7746         struct ixgbe_l2_tn_filter *l2_tn_filter;
7747
7748         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7749
7750         if (ret < 0) {
7751                 PMD_DRV_LOG(ERR,
7752                             "No such L2 tunnel filter to delete %d!",
7753                             ret);
7754                 return ret;
7755         }
7756
7757         l2_tn_filter = l2_tn_info->hash_map[ret];
7758         l2_tn_info->hash_map[ret] = NULL;
7759
7760         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7761         rte_free(l2_tn_filter);
7762
7763         return 0;
7764 }
7765
7766 /* Add l2 tunnel filter */
7767 int
7768 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7769                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7770                                bool restore)
7771 {
7772         int ret;
7773         struct ixgbe_l2_tn_info *l2_tn_info =
7774                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7775         struct ixgbe_l2_tn_key key;
7776         struct ixgbe_l2_tn_filter *node;
7777
7778         if (!restore) {
7779                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7780                 key.tn_id = l2_tunnel->tunnel_id;
7781
7782                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7783
7784                 if (node) {
7785                         PMD_DRV_LOG(ERR,
7786                                     "The L2 tunnel filter already exists!");
7787                         return -EINVAL;
7788                 }
7789
7790                 node = rte_zmalloc("ixgbe_l2_tn",
7791                                    sizeof(struct ixgbe_l2_tn_filter),
7792                                    0);
7793                 if (!node)
7794                         return -ENOMEM;
7795
7796                 rte_memcpy(&node->key,
7797                                  &key,
7798                                  sizeof(struct ixgbe_l2_tn_key));
7799                 node->pool = l2_tunnel->pool;
7800                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7801                 if (ret < 0) {
7802                         rte_free(node);
7803                         return ret;
7804                 }
7805         }
7806
7807         switch (l2_tunnel->l2_tunnel_type) {
7808         case RTE_L2_TUNNEL_TYPE_E_TAG:
7809                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7810                 break;
7811         default:
7812                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7813                 ret = -EINVAL;
7814                 break;
7815         }
7816
7817         if ((!restore) && (ret < 0))
7818                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7819
7820         return ret;
7821 }
7822
7823 /* Delete l2 tunnel filter */
7824 int
7825 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7826                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7827 {
7828         int ret;
7829         struct ixgbe_l2_tn_info *l2_tn_info =
7830                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7831         struct ixgbe_l2_tn_key key;
7832
7833         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7834         key.tn_id = l2_tunnel->tunnel_id;
7835         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7836         if (ret < 0)
7837                 return ret;
7838
7839         switch (l2_tunnel->l2_tunnel_type) {
7840         case RTE_L2_TUNNEL_TYPE_E_TAG:
7841                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7842                 break;
7843         default:
7844                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7845                 ret = -EINVAL;
7846                 break;
7847         }
7848
7849         return ret;
7850 }
7851
7852 /**
7853  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7854  * @dev: pointer to rte_eth_dev structure
7855  * @filter_op:operation will be taken.
7856  * @arg: a pointer to specific structure corresponding to the filter_op
7857  */
7858 static int
7859 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7860                                   enum rte_filter_op filter_op,
7861                                   void *arg)
7862 {
7863         int ret;
7864
7865         if (filter_op == RTE_ETH_FILTER_NOP)
7866                 return 0;
7867
7868         if (arg == NULL) {
7869                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7870                             filter_op);
7871                 return -EINVAL;
7872         }
7873
7874         switch (filter_op) {
7875         case RTE_ETH_FILTER_ADD:
7876                 ret = ixgbe_dev_l2_tunnel_filter_add
7877                         (dev,
7878                          (struct rte_eth_l2_tunnel_conf *)arg,
7879                          FALSE);
7880                 break;
7881         case RTE_ETH_FILTER_DELETE:
7882                 ret = ixgbe_dev_l2_tunnel_filter_del
7883                         (dev,
7884                          (struct rte_eth_l2_tunnel_conf *)arg);
7885                 break;
7886         default:
7887                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7888                 ret = -EINVAL;
7889                 break;
7890         }
7891         return ret;
7892 }
7893
7894 static int
7895 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7896 {
7897         int ret = 0;
7898         uint32_t ctrl;
7899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7900
7901         if (hw->mac.type != ixgbe_mac_X550 &&
7902             hw->mac.type != ixgbe_mac_X550EM_x &&
7903             hw->mac.type != ixgbe_mac_X550EM_a) {
7904                 return -ENOTSUP;
7905         }
7906
7907         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7908         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7909         if (en)
7910                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7911         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7912
7913         return ret;
7914 }
7915
7916 /* Enable l2 tunnel forwarding */
7917 static int
7918 ixgbe_dev_l2_tunnel_forwarding_enable
7919         (struct rte_eth_dev *dev,
7920          enum rte_eth_tunnel_type l2_tunnel_type)
7921 {
7922         struct ixgbe_l2_tn_info *l2_tn_info =
7923                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7924         int ret = 0;
7925
7926         switch (l2_tunnel_type) {
7927         case RTE_L2_TUNNEL_TYPE_E_TAG:
7928                 l2_tn_info->e_tag_fwd_en = TRUE;
7929                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7933                 ret = -EINVAL;
7934                 break;
7935         }
7936
7937         return ret;
7938 }
7939
7940 /* Disable l2 tunnel forwarding */
7941 static int
7942 ixgbe_dev_l2_tunnel_forwarding_disable
7943         (struct rte_eth_dev *dev,
7944          enum rte_eth_tunnel_type l2_tunnel_type)
7945 {
7946         struct ixgbe_l2_tn_info *l2_tn_info =
7947                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7948         int ret = 0;
7949
7950         switch (l2_tunnel_type) {
7951         case RTE_L2_TUNNEL_TYPE_E_TAG:
7952                 l2_tn_info->e_tag_fwd_en = FALSE;
7953                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7954                 break;
7955         default:
7956                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7957                 ret = -EINVAL;
7958                 break;
7959         }
7960
7961         return ret;
7962 }
7963
7964 static int
7965 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7966                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7967                              bool en)
7968 {
7969         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7970         int ret = 0;
7971         uint32_t vmtir, vmvir;
7972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7973
7974         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7975                 PMD_DRV_LOG(ERR,
7976                             "VF id %u should be less than %u",
7977                             l2_tunnel->vf_id,
7978                             pci_dev->max_vfs);
7979                 return -EINVAL;
7980         }
7981
7982         if (hw->mac.type != ixgbe_mac_X550 &&
7983             hw->mac.type != ixgbe_mac_X550EM_x &&
7984             hw->mac.type != ixgbe_mac_X550EM_a) {
7985                 return -ENOTSUP;
7986         }
7987
7988         if (en)
7989                 vmtir = l2_tunnel->tunnel_id;
7990         else
7991                 vmtir = 0;
7992
7993         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7994
7995         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7996         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7997         if (en)
7998                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7999         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8000
8001         return ret;
8002 }
8003
8004 /* Enable l2 tunnel tag insertion */
8005 static int
8006 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8007                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8008 {
8009         int ret = 0;
8010
8011         switch (l2_tunnel->l2_tunnel_type) {
8012         case RTE_L2_TUNNEL_TYPE_E_TAG:
8013                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8014                 break;
8015         default:
8016                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8017                 ret = -EINVAL;
8018                 break;
8019         }
8020
8021         return ret;
8022 }
8023
8024 /* Disable l2 tunnel tag insertion */
8025 static int
8026 ixgbe_dev_l2_tunnel_insertion_disable
8027         (struct rte_eth_dev *dev,
8028          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8029 {
8030         int ret = 0;
8031
8032         switch (l2_tunnel->l2_tunnel_type) {
8033         case RTE_L2_TUNNEL_TYPE_E_TAG:
8034                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8035                 break;
8036         default:
8037                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8038                 ret = -EINVAL;
8039                 break;
8040         }
8041
8042         return ret;
8043 }
8044
8045 static int
8046 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8047                              bool en)
8048 {
8049         int ret = 0;
8050         uint32_t qde;
8051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8052
8053         if (hw->mac.type != ixgbe_mac_X550 &&
8054             hw->mac.type != ixgbe_mac_X550EM_x &&
8055             hw->mac.type != ixgbe_mac_X550EM_a) {
8056                 return -ENOTSUP;
8057         }
8058
8059         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8060         if (en)
8061                 qde |= IXGBE_QDE_STRIP_TAG;
8062         else
8063                 qde &= ~IXGBE_QDE_STRIP_TAG;
8064         qde &= ~IXGBE_QDE_READ;
8065         qde |= IXGBE_QDE_WRITE;
8066         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8067
8068         return ret;
8069 }
8070
8071 /* Enable l2 tunnel tag stripping */
8072 static int
8073 ixgbe_dev_l2_tunnel_stripping_enable
8074         (struct rte_eth_dev *dev,
8075          enum rte_eth_tunnel_type l2_tunnel_type)
8076 {
8077         int ret = 0;
8078
8079         switch (l2_tunnel_type) {
8080         case RTE_L2_TUNNEL_TYPE_E_TAG:
8081                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8082                 break;
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -EINVAL;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 /* Disable l2 tunnel tag stripping */
8093 static int
8094 ixgbe_dev_l2_tunnel_stripping_disable
8095         (struct rte_eth_dev *dev,
8096          enum rte_eth_tunnel_type l2_tunnel_type)
8097 {
8098         int ret = 0;
8099
8100         switch (l2_tunnel_type) {
8101         case RTE_L2_TUNNEL_TYPE_E_TAG:
8102                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8103                 break;
8104         default:
8105                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8106                 ret = -EINVAL;
8107                 break;
8108         }
8109
8110         return ret;
8111 }
8112
8113 /* Enable/disable l2 tunnel offload functions */
8114 static int
8115 ixgbe_dev_l2_tunnel_offload_set
8116         (struct rte_eth_dev *dev,
8117          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8118          uint32_t mask,
8119          uint8_t en)
8120 {
8121         int ret = 0;
8122
8123         if (l2_tunnel == NULL)
8124                 return -EINVAL;
8125
8126         ret = -EINVAL;
8127         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8128                 if (en)
8129                         ret = ixgbe_dev_l2_tunnel_enable(
8130                                 dev,
8131                                 l2_tunnel->l2_tunnel_type);
8132                 else
8133                         ret = ixgbe_dev_l2_tunnel_disable(
8134                                 dev,
8135                                 l2_tunnel->l2_tunnel_type);
8136         }
8137
8138         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8139                 if (en)
8140                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8141                                 dev,
8142                                 l2_tunnel);
8143                 else
8144                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8145                                 dev,
8146                                 l2_tunnel);
8147         }
8148
8149         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8150                 if (en)
8151                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8152                                 dev,
8153                                 l2_tunnel->l2_tunnel_type);
8154                 else
8155                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8156                                 dev,
8157                                 l2_tunnel->l2_tunnel_type);
8158         }
8159
8160         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8161                 if (en)
8162                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8163                                 dev,
8164                                 l2_tunnel->l2_tunnel_type);
8165                 else
8166                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8167                                 dev,
8168                                 l2_tunnel->l2_tunnel_type);
8169         }
8170
8171         return ret;
8172 }
8173
8174 static int
8175 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8176                         uint16_t port)
8177 {
8178         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8179         IXGBE_WRITE_FLUSH(hw);
8180
8181         return 0;
8182 }
8183
8184 /* There's only one register for VxLAN UDP port.
8185  * So, we cannot add several ports. Will update it.
8186  */
8187 static int
8188 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8189                      uint16_t port)
8190 {
8191         if (port == 0) {
8192                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8193                 return -EINVAL;
8194         }
8195
8196         return ixgbe_update_vxlan_port(hw, port);
8197 }
8198
8199 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8200  * UDP port, it must have a value.
8201  * So, will reset it to the original value 0.
8202  */
8203 static int
8204 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8205                      uint16_t port)
8206 {
8207         uint16_t cur_port;
8208
8209         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8210
8211         if (cur_port != port) {
8212                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8213                 return -EINVAL;
8214         }
8215
8216         return ixgbe_update_vxlan_port(hw, 0);
8217 }
8218
8219 /* Add UDP tunneling port */
8220 static int
8221 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8222                               struct rte_eth_udp_tunnel *udp_tunnel)
8223 {
8224         int ret = 0;
8225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8226
8227         if (hw->mac.type != ixgbe_mac_X550 &&
8228             hw->mac.type != ixgbe_mac_X550EM_x &&
8229             hw->mac.type != ixgbe_mac_X550EM_a) {
8230                 return -ENOTSUP;
8231         }
8232
8233         if (udp_tunnel == NULL)
8234                 return -EINVAL;
8235
8236         switch (udp_tunnel->prot_type) {
8237         case RTE_TUNNEL_TYPE_VXLAN:
8238                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8239                 break;
8240
8241         case RTE_TUNNEL_TYPE_GENEVE:
8242         case RTE_TUNNEL_TYPE_TEREDO:
8243                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8244                 ret = -EINVAL;
8245                 break;
8246
8247         default:
8248                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8249                 ret = -EINVAL;
8250                 break;
8251         }
8252
8253         return ret;
8254 }
8255
8256 /* Remove UDP tunneling port */
8257 static int
8258 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8259                               struct rte_eth_udp_tunnel *udp_tunnel)
8260 {
8261         int ret = 0;
8262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8263
8264         if (hw->mac.type != ixgbe_mac_X550 &&
8265             hw->mac.type != ixgbe_mac_X550EM_x &&
8266             hw->mac.type != ixgbe_mac_X550EM_a) {
8267                 return -ENOTSUP;
8268         }
8269
8270         if (udp_tunnel == NULL)
8271                 return -EINVAL;
8272
8273         switch (udp_tunnel->prot_type) {
8274         case RTE_TUNNEL_TYPE_VXLAN:
8275                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8276                 break;
8277         case RTE_TUNNEL_TYPE_GENEVE:
8278         case RTE_TUNNEL_TYPE_TEREDO:
8279                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8280                 ret = -EINVAL;
8281                 break;
8282         default:
8283                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8284                 ret = -EINVAL;
8285                 break;
8286         }
8287
8288         return ret;
8289 }
8290
8291 static void
8292 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8293 {
8294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8295
8296         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8297 }
8298
8299 static void
8300 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8301 {
8302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8303
8304         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8305 }
8306
8307 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8308 {
8309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8310         u32 in_msg = 0;
8311
8312         /* peek the message first */
8313         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8314
8315         /* PF reset VF event */
8316         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8317                 /* dummy mbx read to ack pf */
8318                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8319                         return;
8320                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8321                                               NULL);
8322         }
8323 }
8324
8325 static int
8326 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8327 {
8328         uint32_t eicr;
8329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8330         struct ixgbe_interrupt *intr =
8331                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8332         ixgbevf_intr_disable(dev);
8333
8334         /* read-on-clear nic registers here */
8335         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8336         intr->flags = 0;
8337
8338         /* only one misc vector supported - mailbox */
8339         eicr &= IXGBE_VTEICR_MASK;
8340         if (eicr == IXGBE_MISC_VEC_ID)
8341                 intr->flags |= IXGBE_FLAG_MAILBOX;
8342
8343         return 0;
8344 }
8345
8346 static int
8347 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8348 {
8349         struct ixgbe_interrupt *intr =
8350                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8351
8352         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8353                 ixgbevf_mbx_process(dev);
8354                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8355         }
8356
8357         ixgbevf_intr_enable(dev);
8358
8359         return 0;
8360 }
8361
8362 static void
8363 ixgbevf_dev_interrupt_handler(void *param)
8364 {
8365         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8366
8367         ixgbevf_dev_interrupt_get_status(dev);
8368         ixgbevf_dev_interrupt_action(dev);
8369 }
8370
8371 /**
8372  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8373  *  @hw: pointer to hardware structure
8374  *
8375  *  Stops the transmit data path and waits for the HW to internally empty
8376  *  the Tx security block
8377  **/
8378 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8379 {
8380 #define IXGBE_MAX_SECTX_POLL 40
8381
8382         int i;
8383         int sectxreg;
8384
8385         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8386         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8387         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8388         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8389                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8390                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8391                         break;
8392                 /* Use interrupt-safe sleep just in case */
8393                 usec_delay(1000);
8394         }
8395
8396         /* For informational purposes only */
8397         if (i >= IXGBE_MAX_SECTX_POLL)
8398                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8399                          "path fully disabled.  Continuing with init.");
8400
8401         return IXGBE_SUCCESS;
8402 }
8403
8404 /**
8405  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8406  *  @hw: pointer to hardware structure
8407  *
8408  *  Enables the transmit data path.
8409  **/
8410 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8411 {
8412         uint32_t sectxreg;
8413
8414         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8415         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8416         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8417         IXGBE_WRITE_FLUSH(hw);
8418
8419         return IXGBE_SUCCESS;
8420 }
8421
8422 /* restore n-tuple filter */
8423 static inline void
8424 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8425 {
8426         struct ixgbe_filter_info *filter_info =
8427                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8428         struct ixgbe_5tuple_filter *node;
8429
8430         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8431                 ixgbe_inject_5tuple_filter(dev, node);
8432         }
8433 }
8434
8435 /* restore ethernet type filter */
8436 static inline void
8437 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8438 {
8439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8440         struct ixgbe_filter_info *filter_info =
8441                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8442         int i;
8443
8444         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8445                 if (filter_info->ethertype_mask & (1 << i)) {
8446                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8447                                         filter_info->ethertype_filters[i].etqf);
8448                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8449                                         filter_info->ethertype_filters[i].etqs);
8450                         IXGBE_WRITE_FLUSH(hw);
8451                 }
8452         }
8453 }
8454
8455 /* restore SYN filter */
8456 static inline void
8457 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8458 {
8459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8460         struct ixgbe_filter_info *filter_info =
8461                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8462         uint32_t synqf;
8463
8464         synqf = filter_info->syn_info;
8465
8466         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8467                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8468                 IXGBE_WRITE_FLUSH(hw);
8469         }
8470 }
8471
8472 /* restore L2 tunnel filter */
8473 static inline void
8474 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8475 {
8476         struct ixgbe_l2_tn_info *l2_tn_info =
8477                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8478         struct ixgbe_l2_tn_filter *node;
8479         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8480
8481         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8482                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8483                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8484                 l2_tn_conf.pool           = node->pool;
8485                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8486         }
8487 }
8488
8489 /* restore rss filter */
8490 static inline void
8491 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8492 {
8493         struct ixgbe_filter_info *filter_info =
8494                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8495
8496         if (filter_info->rss_info.conf.queue_num)
8497                 ixgbe_config_rss_filter(dev,
8498                         &filter_info->rss_info, TRUE);
8499 }
8500
8501 static int
8502 ixgbe_filter_restore(struct rte_eth_dev *dev)
8503 {
8504         ixgbe_ntuple_filter_restore(dev);
8505         ixgbe_ethertype_filter_restore(dev);
8506         ixgbe_syn_filter_restore(dev);
8507         ixgbe_fdir_filter_restore(dev);
8508         ixgbe_l2_tn_filter_restore(dev);
8509         ixgbe_rss_filter_restore(dev);
8510
8511         return 0;
8512 }
8513
8514 static void
8515 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8516 {
8517         struct ixgbe_l2_tn_info *l2_tn_info =
8518                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8520
8521         if (l2_tn_info->e_tag_en)
8522                 (void)ixgbe_e_tag_enable(hw);
8523
8524         if (l2_tn_info->e_tag_fwd_en)
8525                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8526
8527         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8528 }
8529
8530 /* remove all the n-tuple filters */
8531 void
8532 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8533 {
8534         struct ixgbe_filter_info *filter_info =
8535                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8536         struct ixgbe_5tuple_filter *p_5tuple;
8537
8538         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8539                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8540 }
8541
8542 /* remove all the ether type filters */
8543 void
8544 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8545 {
8546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8547         struct ixgbe_filter_info *filter_info =
8548                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8549         int i;
8550
8551         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8552                 if (filter_info->ethertype_mask & (1 << i) &&
8553                     !filter_info->ethertype_filters[i].conf) {
8554                         (void)ixgbe_ethertype_filter_remove(filter_info,
8555                                                             (uint8_t)i);
8556                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8557                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8558                         IXGBE_WRITE_FLUSH(hw);
8559                 }
8560         }
8561 }
8562
8563 /* remove the SYN filter */
8564 void
8565 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8566 {
8567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8568         struct ixgbe_filter_info *filter_info =
8569                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8570
8571         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8572                 filter_info->syn_info = 0;
8573
8574                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8575                 IXGBE_WRITE_FLUSH(hw);
8576         }
8577 }
8578
8579 /* remove all the L2 tunnel filters */
8580 int
8581 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8582 {
8583         struct ixgbe_l2_tn_info *l2_tn_info =
8584                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8585         struct ixgbe_l2_tn_filter *l2_tn_filter;
8586         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8587         int ret = 0;
8588
8589         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8590                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8591                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8592                 l2_tn_conf.pool           = l2_tn_filter->pool;
8593                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8594                 if (ret < 0)
8595                         return ret;
8596         }
8597
8598         return 0;
8599 }
8600
8601 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8602 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8603 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8604 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8605 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8606 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8607
8608 RTE_INIT(ixgbe_init_log)
8609 {
8610         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8611         if (ixgbe_logtype_init >= 0)
8612                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8613         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8614         if (ixgbe_logtype_driver >= 0)
8615                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8616 }