drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153 #define IXGBE_VTEICR_MASK                      0x07
 154
 155 enum ixgbevf_xcast_modes {
 156         IXGBEVF_XCAST_MODE_NONE = 0,
 157         IXGBEVF_XCAST_MODE_MULTI,
 158         IXGBEVF_XCAST_MODE_ALLMULTI,
 159 };
 160
 161 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 162 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 163
 164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 191                                              uint16_t queue_id,
 192                                              uint8_t stat_idx,
 193                                              uint8_t is_rx);
 194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 195                                struct rte_eth_dev_info *dev_info);
 196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 198                                  struct rte_eth_dev_info *dev_info);
 199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200
 201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 202                 uint16_t vlan_id, int on);
 203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 204                                enum rte_vlan_type vlan_type,
 205                                uint16_t tpid_id);
 206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, bool on);
 208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 209                 int on);
 210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 215
 216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 219                                struct rte_eth_fc_conf *fc_conf);
 220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 223                 struct rte_eth_pfc_conf *pfc_conf);
 224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 225                         struct rte_eth_rss_reta_entry64 *reta_conf,
 226                         uint16_t reta_size);
 227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 236                 void *param);
 237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 239                 uint32_t index, uint32_t pool);
 240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 242                                            struct ether_addr *mac_addr);
 243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 255                 struct rte_eth_stats *stats);
 256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 258                 uint16_t vlan_id, int on);
 259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 260                 uint16_t queue, int on);
 261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 264                                             uint16_t queue_id);
 265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 266                                              uint16_t queue_id);
 267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 268                                  uint8_t queue, uint8_t msix_vector);
 269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 272
 273 /* For Eth VMDQ APIs support */
 274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 275                 ether_addr * mac_addr, uint8_t on);
 276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 277 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 278                 uint16_t rx_mask, uint8_t on);
 279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 282                 uint64_t pool_mask, uint8_t vlan_on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 299                 uint16_t tx_rate, uint64_t q_msk);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter,
 309                         bool add);
 310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter);
 312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 313                         enum rte_filter_op filter_op,
 314                         void *arg);
 315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter,
 321                         bool add);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ethertype_filter *filter,
 329                         bool add);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 373                                           void *param);
 374
 375 static int ixgbe_dev_l2_tunnel_eth_type_conf
 376         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 377 static int ixgbe_dev_l2_tunnel_offload_set
 378         (struct rte_eth_dev *dev,
 379          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 380          uint32_t mask,
 381          uint8_t en);
 382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 383                                              enum rte_filter_op filter_op,
 384                                              void *arg);
 385
 386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432
 433 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 434 #include "rte_pci_dev_ids.h"
 435
 436 { .vendor_id = 0, /* sentinel */ },
 437 };
 438
 439
 440 /*
 441  * The set of PCI devices this driver supports (for 82599 VF)
 442  */
 443 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 444
 445 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 446 #include "rte_pci_dev_ids.h"
 447 { .vendor_id = 0, /* sentinel */ },
 448
 449 };
 450
 451 static const struct rte_eth_desc_lim rx_desc_lim = {
 452         .nb_max = IXGBE_MAX_RING_DESC,
 453         .nb_min = IXGBE_MIN_RING_DESC,
 454         .nb_align = IXGBE_RXD_ALIGN,
 455 };
 456
 457 static const struct rte_eth_desc_lim tx_desc_lim = {
 458         .nb_max = IXGBE_MAX_RING_DESC,
 459         .nb_min = IXGBE_MIN_RING_DESC,
 460         .nb_align = IXGBE_TXD_ALIGN,
 461 };
 462
 463 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 464         .dev_configure        = ixgbe_dev_configure,
 465         .dev_start            = ixgbe_dev_start,
 466         .dev_stop             = ixgbe_dev_stop,
 467         .dev_set_link_up    = ixgbe_dev_set_link_up,
 468         .dev_set_link_down  = ixgbe_dev_set_link_down,
 469         .dev_close            = ixgbe_dev_close,
 470         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 471         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 472         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 473         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 474         .link_update          = ixgbe_dev_link_update,
 475         .stats_get            = ixgbe_dev_stats_get,
 476         .xstats_get           = ixgbe_dev_xstats_get,
 477         .stats_reset          = ixgbe_dev_stats_reset,
 478         .xstats_reset         = ixgbe_dev_xstats_reset,
 479         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 480         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 481         .dev_infos_get        = ixgbe_dev_info_get,
 482         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 483         .mtu_set              = ixgbe_dev_mtu_set,
 484         .vlan_filter_set      = ixgbe_vlan_filter_set,
 485         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 486         .vlan_offload_set     = ixgbe_vlan_offload_set,
 487         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 488         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 489         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 490         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 491         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 492         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 493         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 494         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 495         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 496         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 497         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 498         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 499         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 500         .dev_led_on           = ixgbe_dev_led_on,
 501         .dev_led_off          = ixgbe_dev_led_off,
 502         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 503         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 504         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 505         .mac_addr_add         = ixgbe_add_rar,
 506         .mac_addr_remove      = ixgbe_remove_rar,
 507         .mac_addr_set         = ixgbe_set_default_mac_addr,
 508         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 509         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 510         .mirror_rule_set      = ixgbe_mirror_rule_set,
 511         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 512         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 513         .set_vf_rx            = ixgbe_set_pool_rx,
 514         .set_vf_tx            = ixgbe_set_pool_tx,
 515         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 516         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 517         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 518         .reta_update          = ixgbe_dev_rss_reta_update,
 519         .reta_query           = ixgbe_dev_rss_reta_query,
 520 #ifdef RTE_NIC_BYPASS
 521         .bypass_init          = ixgbe_bypass_init,
 522         .bypass_state_set     = ixgbe_bypass_state_store,
 523         .bypass_state_show    = ixgbe_bypass_state_show,
 524         .bypass_event_set     = ixgbe_bypass_event_store,
 525         .bypass_event_show    = ixgbe_bypass_event_show,
 526         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 527         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 528         .bypass_ver_show      = ixgbe_bypass_ver_show,
 529         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 530 #endif /* RTE_NIC_BYPASS */
 531         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 532         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 533         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 534         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 535         .rxq_info_get         = ixgbe_rxq_info_get,
 536         .txq_info_get         = ixgbe_txq_info_get,
 537         .timesync_enable      = ixgbe_timesync_enable,
 538         .timesync_disable     = ixgbe_timesync_disable,
 539         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 540         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 541         .get_reg              = ixgbe_get_regs,
 542         .get_eeprom_length    = ixgbe_get_eeprom_length,
 543         .get_eeprom           = ixgbe_get_eeprom,
 544         .set_eeprom           = ixgbe_set_eeprom,
 545         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 546         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 547         .timesync_read_time   = ixgbe_timesync_read_time,
 548         .timesync_write_time  = ixgbe_timesync_write_time,
 549         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 550         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 551         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 552         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 553 };
 554
 555 /*
 556  * dev_ops for virtual function, bare necessities for basic vf
 557  * operation have been implemented
 558  */
 559 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 560         .dev_configure        = ixgbevf_dev_configure,
 561         .dev_start            = ixgbevf_dev_start,
 562         .dev_stop             = ixgbevf_dev_stop,
 563         .link_update          = ixgbe_dev_link_update,
 564         .stats_get            = ixgbevf_dev_stats_get,
 565         .xstats_get           = ixgbevf_dev_xstats_get,
 566         .stats_reset          = ixgbevf_dev_stats_reset,
 567         .xstats_reset         = ixgbevf_dev_stats_reset,
 568         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 569         .dev_close            = ixgbevf_dev_close,
 570         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 571         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 572         .dev_infos_get        = ixgbevf_dev_info_get,
 573         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 574         .mtu_set              = ixgbevf_dev_set_mtu,
 575         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 576         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 577         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 578         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 579         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 580         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 581         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 582         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 583         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 584         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 585         .mac_addr_add         = ixgbevf_add_mac_addr,
 586         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 587         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 588         .rxq_info_get         = ixgbe_rxq_info_get,
 589         .txq_info_get         = ixgbe_txq_info_get,
 590         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 591         .get_reg              = ixgbevf_get_regs,
 592         .reta_update          = ixgbe_dev_rss_reta_update,
 593         .reta_query           = ixgbe_dev_rss_reta_query,
 594         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 595         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 596 };
 597
 598 /* store statistics names and its offset in stats structure */
 599 struct rte_ixgbe_xstats_name_off {
 600         char name[RTE_ETH_XSTATS_NAME_SIZE];
 601         unsigned offset;
 602 };
 603
 604 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 605         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 606         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 607         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 608         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 609         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 610         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 611         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 612         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 613         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 614         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 615         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 616         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 617         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 618         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 619         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 620                 prc1023)},
 621         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 622                 prc1522)},
 623         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 624         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 625         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 626         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 627         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 628         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 629         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 630         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 631         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 632         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 633         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 634         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 635         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 636         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 637         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 638         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 639         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 640                 ptc1023)},
 641         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 642                 ptc1522)},
 643         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 644         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 645         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 646         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 647
 648         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirustat_add)},
 650         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 651                 fdirustat_remove)},
 652         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 653                 fdirfstat_fadd)},
 654         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 655                 fdirfstat_fremove)},
 656         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 657                 fdirmatch)},
 658         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 659                 fdirmiss)},
 660
 661         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 662         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 663         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 664                 fclast)},
 665         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 666         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 667         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 668         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 669         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 670                 fcoe_noddp)},
 671         {"rx_fcoe_no_direct_data_placement_ext_buff",
 672                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 673
 674         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 675                 lxontxc)},
 676         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 677                 lxonrxc)},
 678         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 679                 lxofftxc)},
 680         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 681                 lxoffrxc)},
 682         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 683 };
 684
 685 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 686                            sizeof(rte_ixgbe_stats_strings[0]))
 687
 688 /* Per-queue statistics */
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 690         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 691         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 692         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 693         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 694 };
 695
 696 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 697                            sizeof(rte_ixgbe_rxq_strings[0]))
 698 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 699
 700 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 701         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 702         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 703         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 704                 pxon2offc)},
 705 };
 706
 707 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 708                            sizeof(rte_ixgbe_txq_strings[0]))
 709 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 710
 711 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 712         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 713 };
 714
 715 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 716                 sizeof(rte_ixgbevf_stats_strings[0]))
 717
 718 /**
 719  * Atomically reads the link status information from global
 720  * structure rte_eth_dev.
 721  *
 722  * @param dev
 723  *   - Pointer to the structure rte_eth_dev to read from.
 724  *   - Pointer to the buffer to be saved with the link status.
 725  *
 726  * @return
 727  *   - On success, zero.
 728  *   - On failure, negative value.
 729  */
 730 static inline int
 731 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 732                                 struct rte_eth_link *link)
 733 {
 734         struct rte_eth_link *dst = link;
 735         struct rte_eth_link *src = &(dev->data->dev_link);
 736
 737         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 738                                         *(uint64_t *)src) == 0)
 739                 return -1;
 740
 741         return 0;
 742 }
 743
 744 /**
 745  * Atomically writes the link status information into global
 746  * structure rte_eth_dev.
 747  *
 748  * @param dev
 749  *   - Pointer to the structure rte_eth_dev to read from.
 750  *   - Pointer to the buffer to be saved with the link status.
 751  *
 752  * @return
 753  *   - On success, zero.
 754  *   - On failure, negative value.
 755  */
 756 static inline int
 757 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 758                                 struct rte_eth_link *link)
 759 {
 760         struct rte_eth_link *dst = &(dev->data->dev_link);
 761         struct rte_eth_link *src = link;
 762
 763         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 764                                         *(uint64_t *)src) == 0)
 765                 return -1;
 766
 767         return 0;
 768 }
 769
 770 /*
 771  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 772  */
 773 static inline int
 774 ixgbe_is_sfp(struct ixgbe_hw *hw)
 775 {
 776         switch (hw->phy.type) {
 777         case ixgbe_phy_sfp_avago:
 778         case ixgbe_phy_sfp_ftl:
 779         case ixgbe_phy_sfp_intel:
 780         case ixgbe_phy_sfp_unknown:
 781         case ixgbe_phy_sfp_passive_tyco:
 782         case ixgbe_phy_sfp_passive_unknown:
 783                 return 1;
 784         default:
 785                 return 0;
 786         }
 787 }
 788
 789 static inline int32_t
 790 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 791 {
 792         uint32_t ctrl_ext;
 793         int32_t status;
 794
 795         status = ixgbe_reset_hw(hw);
 796
 797         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 798         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 799         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 800         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 801         IXGBE_WRITE_FLUSH(hw);
 802
 803         return status;
 804 }
 805
 806 static inline void
 807 ixgbe_enable_intr(struct rte_eth_dev *dev)
 808 {
 809         struct ixgbe_interrupt *intr =
 810                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 811         struct ixgbe_hw *hw =
 812                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 813
 814         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 815         IXGBE_WRITE_FLUSH(hw);
 816 }
 817
 818 /*
 819  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 820  */
 821 static void
 822 ixgbe_disable_intr(struct ixgbe_hw *hw)
 823 {
 824         PMD_INIT_FUNC_TRACE();
 825
 826         if (hw->mac.type == ixgbe_mac_82598EB) {
 827                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 828         } else {
 829                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 830                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 831                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 832         }
 833         IXGBE_WRITE_FLUSH(hw);
 834 }
 835
 836 /*
 837  * This function resets queue statistics mapping registers.
 838  * From Niantic datasheet, Initialization of Statistics section:
 839  * "...if software requires the queue counters, the RQSMR and TQSM registers
 840  * must be re-programmed following a device reset.
 841  */
 842 static void
 843 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 844 {
 845         uint32_t i;
 846
 847         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 848                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 849                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 850         }
 851 }
 852
 853
 854 static int
 855 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 856                                   uint16_t queue_id,
 857                                   uint8_t stat_idx,
 858                                   uint8_t is_rx)
 859 {
 860 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 861 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 862 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 863
 864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 865         struct ixgbe_stat_mapping_registers *stat_mappings =
 866                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 867         uint32_t qsmr_mask = 0;
 868         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 869         uint32_t q_map;
 870         uint8_t n, offset;
 871
 872         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 873                 (hw->mac.type != ixgbe_mac_X540) &&
 874                 (hw->mac.type != ixgbe_mac_X550) &&
 875                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 876                 (hw->mac.type != ixgbe_mac_X550EM_a))
 877                 return -ENOSYS;
 878
 879         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 880                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 881                      queue_id, stat_idx);
 882
 883         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 884         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 885                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 886                 return -EIO;
 887         }
 888         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 889
 890         /* Now clear any previous stat_idx set */
 891         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 892         if (!is_rx)
 893                 stat_mappings->tqsm[n] &= ~clearing_mask;
 894         else
 895                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 896
 897         q_map = (uint32_t)stat_idx;
 898         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 899         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 900         if (!is_rx)
 901                 stat_mappings->tqsm[n] |= qsmr_mask;
 902         else
 903                 stat_mappings->rqsmr[n] |= qsmr_mask;
 904
 905         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 909                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 910
 911         /* Now write the mapping in the appropriate register */
 912         if (is_rx) {
 913                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 914                              stat_mappings->rqsmr[n], n);
 915                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 916         } else {
 917                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 918                              stat_mappings->tqsm[n], n);
 919                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 920         }
 921         return 0;
 922 }
 923
 924 static void
 925 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 926 {
 927         struct ixgbe_stat_mapping_registers *stat_mappings =
 928                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 930         int i;
 931
 932         /* write whatever was in stat mapping table to the NIC */
 933         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 934                 /* rx */
 935                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 936
 937                 /* tx */
 938                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 939         }
 940 }
 941
 942 static void
 943 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 944 {
 945         uint8_t i;
 946         struct ixgbe_dcb_tc_config *tc;
 947         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 948
 949         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 950         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 951         for (i = 0; i < dcb_max_tc; i++) {
 952                 tc = &dcb_config->tc_config[i];
 953                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 954                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 955                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 956                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 957                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 958                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 959                 tc->pfc = ixgbe_dcb_pfc_disabled;
 960         }
 961
 962         /* Initialize default user to priority mapping, UPx->TC0 */
 963         tc = &dcb_config->tc_config[0];
 964         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 965         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 966         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 967                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 968                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 969         }
 970         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 971         dcb_config->pfc_mode_enable = false;
 972         dcb_config->vt_mode = true;
 973         dcb_config->round_robin_enable = false;
 974         /* support all DCB capabilities in 82599 */
 975         dcb_config->support.capabilities = 0xFF;
 976
 977         /*we only support 4 Tcs for X540, X550 */
 978         if (hw->mac.type == ixgbe_mac_X540 ||
 979                 hw->mac.type == ixgbe_mac_X550 ||
 980                 hw->mac.type == ixgbe_mac_X550EM_x ||
 981                 hw->mac.type == ixgbe_mac_X550EM_a) {
 982                 dcb_config->num_tcs.pg_tcs = 4;
 983                 dcb_config->num_tcs.pfc_tcs = 4;
 984         }
 985 }
 986
 987 /*
 988  * Ensure that all locks are released before first NVM or PHY access
 989  */
 990 static void
 991 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 992 {
 993         uint16_t mask;
 994
 995         /*
 996          * Phy lock should not fail in this early stage. If this is the case,
 997          * it is due to an improper exit of the application.
 998          * So force the release of the faulty lock. Release of common lock
 999          * is done automatically by swfw_sync function.
1000          */
1001         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1002         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1003                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1004         }
1005         ixgbe_release_swfw_semaphore(hw, mask);
1006
1007         /*
1008          * These ones are more tricky since they are common to all ports; but
1009          * swfw_sync retries last long enough (1s) to be almost sure that if
1010          * lock can not be taken it is due to an improper lock of the
1011          * semaphore.
1012          */
1013         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1014         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1015                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1016         }
1017         ixgbe_release_swfw_semaphore(hw, mask);
1018 }
1019
1020 /*
1021  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1022  * It returns 0 on success.
1023  */
1024 static int
1025 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1026 {
1027         struct rte_pci_device *pci_dev;
1028         struct ixgbe_hw *hw =
1029                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1030         struct ixgbe_vfta *shadow_vfta =
1031                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1032         struct ixgbe_hwstrip *hwstrip =
1033                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1034         struct ixgbe_dcb_config *dcb_config =
1035                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1036         struct ixgbe_filter_info *filter_info =
1037                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1038         uint32_t ctrl_ext;
1039         uint16_t csum;
1040         int diag, i;
1041
1042         PMD_INIT_FUNC_TRACE();
1043
1044         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1045         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1046         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1047
1048         /*
1049          * For secondary processes, we don't initialise any further as primary
1050          * has already done this work. Only check we don't need a different
1051          * RX and TX function.
1052          */
1053         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1054                 struct ixgbe_tx_queue *txq;
1055                 /* TX queue function in primary, set by last queue initialized
1056                  * Tx queue may not initialized by primary process
1057                  */
1058                 if (eth_dev->data->tx_queues) {
1059                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1060                         ixgbe_set_tx_function(eth_dev, txq);
1061                 } else {
1062                         /* Use default TX function if we get here */
1063                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1064                                      "Using default TX function.");
1065                 }
1066
1067                 ixgbe_set_rx_function(eth_dev);
1068
1069                 return 0;
1070         }
1071         pci_dev = eth_dev->pci_dev;
1072
1073         rte_eth_copy_pci_info(eth_dev, pci_dev);
1074
1075         /* Vendor and Device ID need to be set before init of shared code */
1076         hw->device_id = pci_dev->id.device_id;
1077         hw->vendor_id = pci_dev->id.vendor_id;
1078         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1079         hw->allow_unsupported_sfp = 1;
1080
1081         /* Initialize the shared code (base driver) */
1082 #ifdef RTE_NIC_BYPASS
1083         diag = ixgbe_bypass_init_shared_code(hw);
1084 #else
1085         diag = ixgbe_init_shared_code(hw);
1086 #endif /* RTE_NIC_BYPASS */
1087
1088         if (diag != IXGBE_SUCCESS) {
1089                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1090                 return -EIO;
1091         }
1092
1093         /* pick up the PCI bus settings for reporting later */
1094         ixgbe_get_bus_info(hw);
1095
1096         /* Unlock any pending hardware semaphore */
1097         ixgbe_swfw_lock_reset(hw);
1098
1099         /* Initialize DCB configuration*/
1100         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1101         ixgbe_dcb_init(hw, dcb_config);
1102         /* Get Hardware Flow Control setting */
1103         hw->fc.requested_mode = ixgbe_fc_full;
1104         hw->fc.current_mode = ixgbe_fc_full;
1105         hw->fc.pause_time = IXGBE_FC_PAUSE;
1106         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1107                 hw->fc.low_water[i] = IXGBE_FC_LO;
1108                 hw->fc.high_water[i] = IXGBE_FC_HI;
1109         }
1110         hw->fc.send_xon = 1;
1111
1112         /* Make sure we have a good EEPROM before we read from it */
1113         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1114         if (diag != IXGBE_SUCCESS) {
1115                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1116                 return -EIO;
1117         }
1118
1119 #ifdef RTE_NIC_BYPASS
1120         diag = ixgbe_bypass_init_hw(hw);
1121 #else
1122         diag = ixgbe_init_hw(hw);
1123 #endif /* RTE_NIC_BYPASS */
1124
1125         /*
1126          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1127          * is called too soon after the kernel driver unbinding/binding occurs.
1128          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1129          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1130          * also called. See ixgbe_identify_phy_82599(). The reason for the
1131          * failure is not known, and only occuts when virtualisation features
1132          * are disabled in the bios. A delay of 100ms  was found to be enough by
1133          * trial-and-error, and is doubled to be safe.
1134          */
1135         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1136                 rte_delay_ms(200);
1137                 diag = ixgbe_init_hw(hw);
1138         }
1139
1140         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1141                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1142                              "LOM.  Please be aware there may be issues associated "
1143                              "with your hardware.");
1144                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1145                              "please contact your Intel or hardware representative "
1146                              "who provided you with this hardware.");
1147         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1148                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1149         if (diag) {
1150                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1151                 return -EIO;
1152         }
1153
1154         /* Reset the hw statistics */
1155         ixgbe_dev_stats_reset(eth_dev);
1156
1157         /* disable interrupt */
1158         ixgbe_disable_intr(hw);
1159
1160         /* reset mappings for queue statistics hw counters*/
1161         ixgbe_reset_qstat_mappings(hw);
1162
1163         /* Allocate memory for storing MAC addresses */
1164         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1165                                                hw->mac.num_rar_entries, 0);
1166         if (eth_dev->data->mac_addrs == NULL) {
1167                 PMD_INIT_LOG(ERR,
1168                              "Failed to allocate %u bytes needed to store "
1169                              "MAC addresses",
1170                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1171                 return -ENOMEM;
1172         }
1173         /* Copy the permanent MAC address */
1174         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1175                         &eth_dev->data->mac_addrs[0]);
1176
1177         /* Allocate memory for storing hash filter MAC addresses */
1178         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1179                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1180         if (eth_dev->data->hash_mac_addrs == NULL) {
1181                 PMD_INIT_LOG(ERR,
1182                              "Failed to allocate %d bytes needed to store MAC addresses",
1183                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1184                 return -ENOMEM;
1185         }
1186
1187         /* initialize the vfta */
1188         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1189
1190         /* initialize the hw strip bitmap*/
1191         memset(hwstrip, 0, sizeof(*hwstrip));
1192
1193         /* initialize PF if max_vfs not zero */
1194         ixgbe_pf_host_init(eth_dev);
1195
1196         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1197         /* let hardware know driver is loaded */
1198         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1199         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1200         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1201         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1202         IXGBE_WRITE_FLUSH(hw);
1203
1204         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1205                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1206                              (int) hw->mac.type, (int) hw->phy.type,
1207                              (int) hw->phy.sfp_type);
1208         else
1209                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1210                              (int) hw->mac.type, (int) hw->phy.type);
1211
1212         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1213                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1214                      pci_dev->id.device_id);
1215
1216         rte_intr_callback_register(&pci_dev->intr_handle,
1217                                    ixgbe_dev_interrupt_handler,
1218                                    (void *)eth_dev);
1219
1220         /* enable uio/vfio intr/eventfd mapping */
1221         rte_intr_enable(&pci_dev->intr_handle);
1222
1223         /* enable support intr */
1224         ixgbe_enable_intr(eth_dev);
1225
1226         /* initialize 5tuple filter list */
1227         TAILQ_INIT(&filter_info->fivetuple_list);
1228         memset(filter_info->fivetuple_mask, 0,
1229                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1230
1231         return 0;
1232 }
1233
1234 static int
1235 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1236 {
1237         struct rte_pci_device *pci_dev;
1238         struct ixgbe_hw *hw;
1239
1240         PMD_INIT_FUNC_TRACE();
1241
1242         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1243                 return -EPERM;
1244
1245         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1246         pci_dev = eth_dev->pci_dev;
1247
1248         if (hw->adapter_stopped == 0)
1249                 ixgbe_dev_close(eth_dev);
1250
1251         eth_dev->dev_ops = NULL;
1252         eth_dev->rx_pkt_burst = NULL;
1253         eth_dev->tx_pkt_burst = NULL;
1254
1255         /* Unlock any pending hardware semaphore */
1256         ixgbe_swfw_lock_reset(hw);
1257
1258         /* disable uio intr before callback unregister */
1259         rte_intr_disable(&(pci_dev->intr_handle));
1260         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1261                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1262
1263         /* uninitialize PF if max_vfs not zero */
1264         ixgbe_pf_host_uninit(eth_dev);
1265
1266         rte_free(eth_dev->data->mac_addrs);
1267         eth_dev->data->mac_addrs = NULL;
1268
1269         rte_free(eth_dev->data->hash_mac_addrs);
1270         eth_dev->data->hash_mac_addrs = NULL;
1271
1272         return 0;
1273 }
1274
1275 /*
1276  * Negotiate mailbox API version with the PF.
1277  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1278  * Then we try to negotiate starting with the most recent one.
1279  * If all negotiation attempts fail, then we will proceed with
1280  * the default one (ixgbe_mbox_api_10).
1281  */
1282 static void
1283 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1284 {
1285         int32_t i;
1286
1287         /* start with highest supported, proceed down */
1288         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1289                 ixgbe_mbox_api_12,
1290                 ixgbe_mbox_api_11,
1291                 ixgbe_mbox_api_10,
1292         };
1293
1294         for (i = 0;
1295                         i != RTE_DIM(sup_ver) &&
1296                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1297                         i++)
1298                 ;
1299 }
1300
1301 static void
1302 generate_random_mac_addr(struct ether_addr *mac_addr)
1303 {
1304         uint64_t random;
1305
1306         /* Set Organizationally Unique Identifier (OUI) prefix. */
1307         mac_addr->addr_bytes[0] = 0x00;
1308         mac_addr->addr_bytes[1] = 0x09;
1309         mac_addr->addr_bytes[2] = 0xC0;
1310         /* Force indication of locally assigned MAC address. */
1311         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1312         /* Generate the last 3 bytes of the MAC address with a random number. */
1313         random = rte_rand();
1314         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1315 }
1316
1317 /*
1318  * Virtual Function device init
1319  */
1320 static int
1321 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1322 {
1323         int diag;
1324         uint32_t tc, tcs;
1325         struct rte_pci_device *pci_dev;
1326         struct ixgbe_hw *hw =
1327                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1328         struct ixgbe_vfta *shadow_vfta =
1329                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1330         struct ixgbe_hwstrip *hwstrip =
1331                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1332         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1333
1334         PMD_INIT_FUNC_TRACE();
1335
1336         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1337         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1338         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1339
1340         /* for secondary processes, we don't initialise any further as primary
1341          * has already done this work. Only check we don't need a different
1342          * RX function
1343          */
1344         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1345                 struct ixgbe_tx_queue *txq;
1346                 /* TX queue function in primary, set by last queue initialized
1347                  * Tx queue may not initialized by primary process
1348                  */
1349                 if (eth_dev->data->tx_queues) {
1350                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1351                         ixgbe_set_tx_function(eth_dev, txq);
1352                 } else {
1353                         /* Use default TX function if we get here */
1354                         PMD_INIT_LOG(NOTICE,
1355                                      "No TX queues configured yet. Using default TX function.");
1356                 }
1357
1358                 ixgbe_set_rx_function(eth_dev);
1359
1360                 return 0;
1361         }
1362
1363         pci_dev = eth_dev->pci_dev;
1364
1365         rte_eth_copy_pci_info(eth_dev, pci_dev);
1366
1367         hw->device_id = pci_dev->id.device_id;
1368         hw->vendor_id = pci_dev->id.vendor_id;
1369         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1370
1371         /* initialize the vfta */
1372         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1373
1374         /* initialize the hw strip bitmap*/
1375         memset(hwstrip, 0, sizeof(*hwstrip));
1376
1377         /* Initialize the shared code (base driver) */
1378         diag = ixgbe_init_shared_code(hw);
1379         if (diag != IXGBE_SUCCESS) {
1380                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1381                 return -EIO;
1382         }
1383
1384         /* init_mailbox_params */
1385         hw->mbx.ops.init_params(hw);
1386
1387         /* Reset the hw statistics */
1388         ixgbevf_dev_stats_reset(eth_dev);
1389
1390         /* Disable the interrupts for VF */
1391         ixgbevf_intr_disable(hw);
1392
1393         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1394         diag = hw->mac.ops.reset_hw(hw);
1395
1396         /*
1397          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1398          * the underlying PF driver has not assigned a MAC address to the VF.
1399          * In this case, assign a random MAC address.
1400          */
1401         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1402                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1403                 return diag;
1404         }
1405
1406         /* negotiate mailbox API version to use with the PF. */
1407         ixgbevf_negotiate_api(hw);
1408
1409         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1410         ixgbevf_get_queues(hw, &tcs, &tc);
1411
1412         /* Allocate memory for storing MAC addresses */
1413         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1414                                                hw->mac.num_rar_entries, 0);
1415         if (eth_dev->data->mac_addrs == NULL) {
1416                 PMD_INIT_LOG(ERR,
1417                              "Failed to allocate %u bytes needed to store "
1418                              "MAC addresses",
1419                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1420                 return -ENOMEM;
1421         }
1422
1423         /* Generate a random MAC address, if none was assigned by PF. */
1424         if (is_zero_ether_addr(perm_addr)) {
1425                 generate_random_mac_addr(perm_addr);
1426                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1427                 if (diag) {
1428                         rte_free(eth_dev->data->mac_addrs);
1429                         eth_dev->data->mac_addrs = NULL;
1430                         return diag;
1431                 }
1432                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1433                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1434                              "%02x:%02x:%02x:%02x:%02x:%02x",
1435                              perm_addr->addr_bytes[0],
1436                              perm_addr->addr_bytes[1],
1437                              perm_addr->addr_bytes[2],
1438                              perm_addr->addr_bytes[3],
1439                              perm_addr->addr_bytes[4],
1440                              perm_addr->addr_bytes[5]);
1441         }
1442
1443         /* Copy the permanent MAC address */
1444         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1445
1446         /* reset the hardware with the new settings */
1447         diag = hw->mac.ops.start_hw(hw);
1448         switch (diag) {
1449         case  0:
1450                 break;
1451
1452         default:
1453                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1454                 return -EIO;
1455         }
1456
1457         rte_intr_callback_register(&pci_dev->intr_handle,
1458                                    ixgbevf_dev_interrupt_handler,
1459                                    (void *)eth_dev);
1460         rte_intr_enable(&pci_dev->intr_handle);
1461         ixgbevf_intr_enable(hw);
1462
1463         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1464                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1465                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1466
1467         return 0;
1468 }
1469
1470 /* Virtual Function device uninit */
1471
1472 static int
1473 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1474 {
1475         struct ixgbe_hw *hw;
1476         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1477
1478         PMD_INIT_FUNC_TRACE();
1479
1480         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1481                 return -EPERM;
1482
1483         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1484
1485         if (hw->adapter_stopped == 0)
1486                 ixgbevf_dev_close(eth_dev);
1487
1488         eth_dev->dev_ops = NULL;
1489         eth_dev->rx_pkt_burst = NULL;
1490         eth_dev->tx_pkt_burst = NULL;
1491
1492         /* Disable the interrupts for VF */
1493         ixgbevf_intr_disable(hw);
1494
1495         rte_free(eth_dev->data->mac_addrs);
1496         eth_dev->data->mac_addrs = NULL;
1497
1498         rte_intr_disable(&pci_dev->intr_handle);
1499         rte_intr_callback_unregister(&pci_dev->intr_handle,
1500                                      ixgbevf_dev_interrupt_handler,
1501                                      (void *)eth_dev);
1502
1503         return 0;
1504 }
1505
1506 static struct eth_driver rte_ixgbe_pmd = {
1507         .pci_drv = {
1508                 .name = "rte_ixgbe_pmd",
1509                 .id_table = pci_id_ixgbe_map,
1510                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1511                         RTE_PCI_DRV_DETACHABLE,
1512         },
1513         .eth_dev_init = eth_ixgbe_dev_init,
1514         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1515         .dev_private_size = sizeof(struct ixgbe_adapter),
1516 };
1517
1518 /*
1519  * virtual function driver struct
1520  */
1521 static struct eth_driver rte_ixgbevf_pmd = {
1522         .pci_drv = {
1523                 .name = "rte_ixgbevf_pmd",
1524                 .id_table = pci_id_ixgbevf_map,
1525                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1526         },
1527         .eth_dev_init = eth_ixgbevf_dev_init,
1528         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1529         .dev_private_size = sizeof(struct ixgbe_adapter),
1530 };
1531
1532 /*
1533  * Driver initialization routine.
1534  * Invoked once at EAL init time.
1535  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1536  */
1537 static int
1538 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1539 {
1540         PMD_INIT_FUNC_TRACE();
1541
1542         rte_eth_driver_register(&rte_ixgbe_pmd);
1543         return 0;
1544 }
1545
1546 /*
1547  * VF Driver initialization routine.
1548  * Invoked one at EAL init time.
1549  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1550  */
1551 static int
1552 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1553 {
1554         PMD_INIT_FUNC_TRACE();
1555
1556         rte_eth_driver_register(&rte_ixgbevf_pmd);
1557         return 0;
1558 }
1559
1560 static int
1561 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1562 {
1563         struct ixgbe_hw *hw =
1564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         struct ixgbe_vfta *shadow_vfta =
1566                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1567         uint32_t vfta;
1568         uint32_t vid_idx;
1569         uint32_t vid_bit;
1570
1571         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1572         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1573         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1574         if (on)
1575                 vfta |= vid_bit;
1576         else
1577                 vfta &= ~vid_bit;
1578         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1579
1580         /* update local VFTA copy */
1581         shadow_vfta->vfta[vid_idx] = vfta;
1582
1583         return 0;
1584 }
1585
1586 static void
1587 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1588 {
1589         if (on)
1590                 ixgbe_vlan_hw_strip_enable(dev, queue);
1591         else
1592                 ixgbe_vlan_hw_strip_disable(dev, queue);
1593 }
1594
1595 static int
1596 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1597                     enum rte_vlan_type vlan_type,
1598                     uint16_t tpid)
1599 {
1600         struct ixgbe_hw *hw =
1601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602         int ret = 0;
1603         uint32_t reg;
1604         uint32_t qinq;
1605
1606         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1607         qinq &= IXGBE_DMATXCTL_GDV;
1608
1609         switch (vlan_type) {
1610         case ETH_VLAN_TYPE_INNER:
1611                 if (qinq) {
1612                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1613                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1614                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1615                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1616                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1617                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1618                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1619                 } else {
1620                         ret = -ENOTSUP;
1621                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1622                                     " by single VLAN");
1623                 }
1624                 break;
1625         case ETH_VLAN_TYPE_OUTER:
1626                 if (qinq) {
1627                         /* Only the high 16-bits is valid */
1628                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1629                                         IXGBE_EXVET_VET_EXT_SHIFT);
1630                 } else {
1631                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1632                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1633                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1634                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1635                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1636                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1637                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1638                 }
1639
1640                 break;
1641         default:
1642                 ret = -EINVAL;
1643                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1644                 break;
1645         }
1646
1647         return ret;
1648 }
1649
1650 void
1651 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1652 {
1653         struct ixgbe_hw *hw =
1654                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         uint32_t vlnctrl;
1656
1657         PMD_INIT_FUNC_TRACE();
1658
1659         /* Filter Table Disable */
1660         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1661         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1662
1663         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1664 }
1665
1666 void
1667 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1668 {
1669         struct ixgbe_hw *hw =
1670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671         struct ixgbe_vfta *shadow_vfta =
1672                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1673         uint32_t vlnctrl;
1674         uint16_t i;
1675
1676         PMD_INIT_FUNC_TRACE();
1677
1678         /* Filter Table Enable */
1679         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1680         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1681         vlnctrl |= IXGBE_VLNCTRL_VFE;
1682
1683         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1684
1685         /* write whatever is in local vfta copy */
1686         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1687                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1688 }
1689
1690 static void
1691 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1692 {
1693         struct ixgbe_hwstrip *hwstrip =
1694                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1695         struct ixgbe_rx_queue *rxq;
1696
1697         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1698                 return;
1699
1700         if (on)
1701                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1702         else
1703                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1704
1705         if (queue >= dev->data->nb_rx_queues)
1706                 return;
1707
1708         rxq = dev->data->rx_queues[queue];
1709
1710         if (on)
1711                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1712         else
1713                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1714 }
1715
1716 static void
1717 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1718 {
1719         struct ixgbe_hw *hw =
1720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721         uint32_t ctrl;
1722
1723         PMD_INIT_FUNC_TRACE();
1724
1725         if (hw->mac.type == ixgbe_mac_82598EB) {
1726                 /* No queue level support */
1727                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1728                 return;
1729         }
1730
1731         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1732         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1733         ctrl &= ~IXGBE_RXDCTL_VME;
1734         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1735
1736         /* record those setting for HW strip per queue */
1737         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1738 }
1739
1740 static void
1741 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1742 {
1743         struct ixgbe_hw *hw =
1744                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745         uint32_t ctrl;
1746
1747         PMD_INIT_FUNC_TRACE();
1748
1749         if (hw->mac.type == ixgbe_mac_82598EB) {
1750                 /* No queue level supported */
1751                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1752                 return;
1753         }
1754
1755         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1756         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1757         ctrl |= IXGBE_RXDCTL_VME;
1758         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1759
1760         /* record those setting for HW strip per queue */
1761         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1762 }
1763
1764 void
1765 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1766 {
1767         struct ixgbe_hw *hw =
1768                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1769         uint32_t ctrl;
1770         uint16_t i;
1771
1772         PMD_INIT_FUNC_TRACE();
1773
1774         if (hw->mac.type == ixgbe_mac_82598EB) {
1775                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1776                 ctrl &= ~IXGBE_VLNCTRL_VME;
1777                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1778         } else {
1779                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1780                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1781                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1782                         ctrl &= ~IXGBE_RXDCTL_VME;
1783                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1784
1785                         /* record those setting for HW strip per queue */
1786                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1787                 }
1788         }
1789 }
1790
1791 void
1792 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1793 {
1794         struct ixgbe_hw *hw =
1795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         uint32_t ctrl;
1797         uint16_t i;
1798
1799         PMD_INIT_FUNC_TRACE();
1800
1801         if (hw->mac.type == ixgbe_mac_82598EB) {
1802                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1803                 ctrl |= IXGBE_VLNCTRL_VME;
1804                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1805         } else {
1806                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1807                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1808                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1809                         ctrl |= IXGBE_RXDCTL_VME;
1810                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1811
1812                         /* record those setting for HW strip per queue */
1813                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1814                 }
1815         }
1816 }
1817
1818 static void
1819 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1820 {
1821         struct ixgbe_hw *hw =
1822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         uint32_t ctrl;
1824
1825         PMD_INIT_FUNC_TRACE();
1826
1827         /* DMATXCTRL: Geric Double VLAN Disable */
1828         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1829         ctrl &= ~IXGBE_DMATXCTL_GDV;
1830         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1831
1832         /* CTRL_EXT: Global Double VLAN Disable */
1833         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1834         ctrl &= ~IXGBE_EXTENDED_VLAN;
1835         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1836
1837 }
1838
1839 static void
1840 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1841 {
1842         struct ixgbe_hw *hw =
1843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844         uint32_t ctrl;
1845
1846         PMD_INIT_FUNC_TRACE();
1847
1848         /* DMATXCTRL: Geric Double VLAN Enable */
1849         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1850         ctrl |= IXGBE_DMATXCTL_GDV;
1851         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1852
1853         /* CTRL_EXT: Global Double VLAN Enable */
1854         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1855         ctrl |= IXGBE_EXTENDED_VLAN;
1856         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1857
1858         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1859         if (hw->mac.type == ixgbe_mac_X550 ||
1860             hw->mac.type == ixgbe_mac_X550EM_x ||
1861             hw->mac.type == ixgbe_mac_X550EM_a) {
1862                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1863                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1864                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1865         }
1866
1867         /*
1868          * VET EXT field in the EXVET register = 0x8100 by default
1869          * So no need to change. Same to VT field of DMATXCTL register
1870          */
1871 }
1872
1873 static void
1874 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1875 {
1876         if (mask & ETH_VLAN_STRIP_MASK) {
1877                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1878                         ixgbe_vlan_hw_strip_enable_all(dev);
1879                 else
1880                         ixgbe_vlan_hw_strip_disable_all(dev);
1881         }
1882
1883         if (mask & ETH_VLAN_FILTER_MASK) {
1884                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1885                         ixgbe_vlan_hw_filter_enable(dev);
1886                 else
1887                         ixgbe_vlan_hw_filter_disable(dev);
1888         }
1889
1890         if (mask & ETH_VLAN_EXTEND_MASK) {
1891                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1892                         ixgbe_vlan_hw_extend_enable(dev);
1893                 else
1894                         ixgbe_vlan_hw_extend_disable(dev);
1895         }
1896 }
1897
1898 static void
1899 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1900 {
1901         struct ixgbe_hw *hw =
1902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1904         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1905
1906         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1907         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1908 }
1909
1910 static int
1911 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1912 {
1913         switch (nb_rx_q) {
1914         case 1:
1915         case 2:
1916                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1917                 break;
1918         case 4:
1919                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1920                 break;
1921         default:
1922                 return -EINVAL;
1923         }
1924
1925         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1926         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1927
1928         return 0;
1929 }
1930
1931 static int
1932 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1933 {
1934         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1937         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1938
1939         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1940                 /* check multi-queue mode */
1941                 switch (dev_conf->rxmode.mq_mode) {
1942                 case ETH_MQ_RX_VMDQ_DCB:
1943                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1944                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1945                         PMD_INIT_LOG(ERR, "SRIOV active,"
1946                                         " unsupported mq_mode rx %d.",
1947                                         dev_conf->rxmode.mq_mode);
1948                         return -EINVAL;
1949                 case ETH_MQ_RX_RSS:
1950                 case ETH_MQ_RX_VMDQ_RSS:
1951                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1952                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1953                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1954                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1955                                                 " invalid queue number"
1956                                                 " for VMDQ RSS, allowed"
1957                                                 " value are 1, 2 or 4.");
1958                                         return -EINVAL;
1959                                 }
1960                         break;
1961                 case ETH_MQ_RX_VMDQ_ONLY:
1962                 case ETH_MQ_RX_NONE:
1963                         /* if nothing mq mode configure, use default scheme */
1964                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1965                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1966                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1967                         break;
1968                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1969                         /* SRIOV only works in VMDq enable mode */
1970                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1971                                         " wrong mq_mode rx %d.",
1972                                         dev_conf->rxmode.mq_mode);
1973                         return -EINVAL;
1974                 }
1975
1976                 switch (dev_conf->txmode.mq_mode) {
1977                 case ETH_MQ_TX_VMDQ_DCB:
1978                         /* DCB VMDQ in SRIOV mode, not implement yet */
1979                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1980                                         " unsupported VMDQ mq_mode tx %d.",
1981                                         dev_conf->txmode.mq_mode);
1982                         return -EINVAL;
1983                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1984                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1985                         break;
1986                 }
1987
1988                 /* check valid queue number */
1989                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1990                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1991                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1992                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1993                                         " must be less than or equal to %d.",
1994                                         nb_rx_q, nb_tx_q,
1995                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1996                         return -EINVAL;
1997                 }
1998         } else {
1999                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2000                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2001                                           " not supported.");
2002                         return -EINVAL;
2003                 }
2004                 /* check configuration for vmdb+dcb mode */
2005                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2006                         const struct rte_eth_vmdq_dcb_conf *conf;
2007
2008                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2009                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2010                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2011                                 return -EINVAL;
2012                         }
2013                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2014                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2015                                conf->nb_queue_pools == ETH_32_POOLS)) {
2016                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2017                                                 " nb_queue_pools must be %d or %d.",
2018                                                 ETH_16_POOLS, ETH_32_POOLS);
2019                                 return -EINVAL;
2020                         }
2021                 }
2022                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2023                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2024
2025                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2026                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2027                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2028                                 return -EINVAL;
2029                         }
2030                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2031                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2032                                conf->nb_queue_pools == ETH_32_POOLS)) {
2033                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2034                                                 " nb_queue_pools != %d and"
2035                                                 " nb_queue_pools != %d.",
2036                                                 ETH_16_POOLS, ETH_32_POOLS);
2037                                 return -EINVAL;
2038                         }
2039                 }
2040
2041                 /* For DCB mode check our configuration before we go further */
2042                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2043                         const struct rte_eth_dcb_rx_conf *conf;
2044
2045                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2046                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2047                                                  IXGBE_DCB_NB_QUEUES);
2048                                 return -EINVAL;
2049                         }
2050                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2051                         if (!(conf->nb_tcs == ETH_4_TCS ||
2052                                conf->nb_tcs == ETH_8_TCS)) {
2053                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2054                                                 " and nb_tcs != %d.",
2055                                                 ETH_4_TCS, ETH_8_TCS);
2056                                 return -EINVAL;
2057                         }
2058                 }
2059
2060                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2061                         const struct rte_eth_dcb_tx_conf *conf;
2062
2063                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2064                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2065                                                  IXGBE_DCB_NB_QUEUES);
2066                                 return -EINVAL;
2067                         }
2068                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2069                         if (!(conf->nb_tcs == ETH_4_TCS ||
2070                                conf->nb_tcs == ETH_8_TCS)) {
2071                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2072                                                 " and nb_tcs != %d.",
2073                                                 ETH_4_TCS, ETH_8_TCS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077
2078                 /*
2079                  * When DCB/VT is off, maximum number of queues changes,
2080                  * except for 82598EB, which remains constant.
2081                  */
2082                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2083                                 hw->mac.type != ixgbe_mac_82598EB) {
2084                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2085                                 PMD_INIT_LOG(ERR,
2086                                              "Neither VT nor DCB are enabled, "
2087                                              "nb_tx_q > %d.",
2088                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2089                                 return -EINVAL;
2090                         }
2091                 }
2092         }
2093         return 0;
2094 }
2095
2096 static int
2097 ixgbe_dev_configure(struct rte_eth_dev *dev)
2098 {
2099         struct ixgbe_interrupt *intr =
2100                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2101         struct ixgbe_adapter *adapter =
2102                 (struct ixgbe_adapter *)dev->data->dev_private;
2103         int ret;
2104
2105         PMD_INIT_FUNC_TRACE();
2106         /* multipe queue mode checking */
2107         ret  = ixgbe_check_mq_mode(dev);
2108         if (ret != 0) {
2109                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2110                             ret);
2111                 return ret;
2112         }
2113
2114         /* set flag to update link status after init */
2115         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2116
2117         /*
2118          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2119          * allocation or vector Rx preconditions we will reset it.
2120          */
2121         adapter->rx_bulk_alloc_allowed = true;
2122         adapter->rx_vec_allowed = true;
2123
2124         return 0;
2125 }
2126
2127 static void
2128 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_hw *hw =
2131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         struct ixgbe_interrupt *intr =
2133                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2134         uint32_t gpie;
2135
2136         /* only set up it on X550EM_X */
2137         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2138                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2139                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2140                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2141                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2142                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2143         }
2144 }
2145
2146 /*
2147  * Configure device link speed and setup link.
2148  * It returns 0 on success.
2149  */
2150 static int
2151 ixgbe_dev_start(struct rte_eth_dev *dev)
2152 {
2153         struct ixgbe_hw *hw =
2154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct ixgbe_vf_info *vfinfo =
2156                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2157         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2158         uint32_t intr_vector = 0;
2159         int err, link_up = 0, negotiate = 0;
2160         uint32_t speed = 0;
2161         int mask = 0;
2162         int status;
2163         uint16_t vf, idx;
2164         uint32_t *link_speeds;
2165
2166         PMD_INIT_FUNC_TRACE();
2167
2168         /* IXGBE devices don't support:
2169         *    - half duplex (checked afterwards for valid speeds)
2170         *    - fixed speed: TODO implement
2171         */
2172         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2173                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2174                              dev->data->port_id);
2175                 return -EINVAL;
2176         }
2177
2178         /* disable uio/vfio intr/eventfd mapping */
2179         rte_intr_disable(intr_handle);
2180
2181         /* stop adapter */
2182         hw->adapter_stopped = 0;
2183         ixgbe_stop_adapter(hw);
2184
2185         /* reinitialize adapter
2186          * this calls reset and start
2187          */
2188         status = ixgbe_pf_reset_hw(hw);
2189         if (status != 0)
2190                 return -1;
2191         hw->mac.ops.start_hw(hw);
2192         hw->mac.get_link_status = true;
2193
2194         /* configure PF module if SRIOV enabled */
2195         ixgbe_pf_host_configure(dev);
2196
2197         ixgbe_dev_phy_intr_setup(dev);
2198
2199         /* check and configure queue intr-vector mapping */
2200         if ((rte_intr_cap_multiple(intr_handle) ||
2201              !RTE_ETH_DEV_SRIOV(dev).active) &&
2202             dev->data->dev_conf.intr_conf.rxq != 0) {
2203                 intr_vector = dev->data->nb_rx_queues;
2204                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2205                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2206                                         IXGBE_MAX_INTR_QUEUE_NUM);
2207                         return -ENOTSUP;
2208                 }
2209                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2210                         return -1;
2211         }
2212
2213         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2214                 intr_handle->intr_vec =
2215                         rte_zmalloc("intr_vec",
2216                                     dev->data->nb_rx_queues * sizeof(int), 0);
2217                 if (intr_handle->intr_vec == NULL) {
2218                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2219                                      " intr_vec\n", dev->data->nb_rx_queues);
2220                         return -ENOMEM;
2221                 }
2222         }
2223
2224         /* confiugre msix for sleep until rx interrupt */
2225         ixgbe_configure_msix(dev);
2226
2227         /* initialize transmission unit */
2228         ixgbe_dev_tx_init(dev);
2229
2230         /* This can fail when allocating mbufs for descriptor rings */
2231         err = ixgbe_dev_rx_init(dev);
2232         if (err) {
2233                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2234                 goto error;
2235         }
2236
2237         err = ixgbe_dev_rxtx_start(dev);
2238         if (err < 0) {
2239                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2240                 goto error;
2241         }
2242
2243         /* Skip link setup if loopback mode is enabled for 82599. */
2244         if (hw->mac.type == ixgbe_mac_82599EB &&
2245                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2246                 goto skip_link_setup;
2247
2248         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2249                 err = hw->mac.ops.setup_sfp(hw);
2250                 if (err)
2251                         goto error;
2252         }
2253
2254         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2255                 /* Turn on the copper */
2256                 ixgbe_set_phy_power(hw, true);
2257         } else {
2258                 /* Turn on the laser */
2259                 ixgbe_enable_tx_laser(hw);
2260         }
2261
2262         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2263         if (err)
2264                 goto error;
2265         dev->data->dev_link.link_status = link_up;
2266
2267         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2268         if (err)
2269                 goto error;
2270
2271         link_speeds = &dev->data->dev_conf.link_speeds;
2272         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2273                         ETH_LINK_SPEED_10G)) {
2274                 PMD_INIT_LOG(ERR, "Invalid link setting");
2275                 goto error;
2276         }
2277
2278         speed = 0x0;
2279         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2280                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2281                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2282                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2283         } else {
2284                 if (*link_speeds & ETH_LINK_SPEED_10G)
2285                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2286                 if (*link_speeds & ETH_LINK_SPEED_1G)
2287                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2288                 if (*link_speeds & ETH_LINK_SPEED_100M)
2289                         speed |= IXGBE_LINK_SPEED_100_FULL;
2290         }
2291
2292         err = ixgbe_setup_link(hw, speed, link_up);
2293         if (err)
2294                 goto error;
2295
2296 skip_link_setup:
2297
2298         if (rte_intr_allow_others(intr_handle)) {
2299                 /* check if lsc interrupt is enabled */
2300                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2301                         ixgbe_dev_lsc_interrupt_setup(dev);
2302         } else {
2303                 rte_intr_callback_unregister(intr_handle,
2304                                              ixgbe_dev_interrupt_handler,
2305                                              (void *)dev);
2306                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2307                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2308                                      " no intr multiplex\n");
2309         }
2310
2311         /* check if rxq interrupt is enabled */
2312         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2313             rte_intr_dp_is_en(intr_handle))
2314                 ixgbe_dev_rxq_interrupt_setup(dev);
2315
2316         /* enable uio/vfio intr/eventfd mapping */
2317         rte_intr_enable(intr_handle);
2318
2319         /* resume enabled intr since hw reset */
2320         ixgbe_enable_intr(dev);
2321
2322         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2323                 ETH_VLAN_EXTEND_MASK;
2324         ixgbe_vlan_offload_set(dev, mask);
2325
2326         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2327                 /* Enable vlan filtering for VMDq */
2328                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2329         }
2330
2331         /* Configure DCB hw */
2332         ixgbe_configure_dcb(dev);
2333
2334         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2335                 err = ixgbe_fdir_configure(dev);
2336                 if (err)
2337                         goto error;
2338         }
2339
2340         /* Restore vf rate limit */
2341         if (vfinfo != NULL) {
2342                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2343                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2344                                 if (vfinfo[vf].tx_rate[idx] != 0)
2345                                         ixgbe_set_vf_rate_limit(dev, vf,
2346                                                 vfinfo[vf].tx_rate[idx],
2347                                                 1 << idx);
2348         }
2349
2350         ixgbe_restore_statistics_mapping(dev);
2351
2352         return 0;
2353
2354 error:
2355         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2356         ixgbe_dev_clear_queues(dev);
2357         return -EIO;
2358 }
2359
2360 /*
2361  * Stop device: disable rx and tx functions to allow for reconfiguring.
2362  */
2363 static void
2364 ixgbe_dev_stop(struct rte_eth_dev *dev)
2365 {
2366         struct rte_eth_link link;
2367         struct ixgbe_hw *hw =
2368                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369         struct ixgbe_vf_info *vfinfo =
2370                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2371         struct ixgbe_filter_info *filter_info =
2372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2373         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2374         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2375         int vf;
2376
2377         PMD_INIT_FUNC_TRACE();
2378
2379         /* disable interrupts */
2380         ixgbe_disable_intr(hw);
2381
2382         /* reset the NIC */
2383         ixgbe_pf_reset_hw(hw);
2384         hw->adapter_stopped = 0;
2385
2386         /* stop adapter */
2387         ixgbe_stop_adapter(hw);
2388
2389         for (vf = 0; vfinfo != NULL &&
2390                      vf < dev->pci_dev->max_vfs; vf++)
2391                 vfinfo[vf].clear_to_send = false;
2392
2393         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2394                 /* Turn off the copper */
2395                 ixgbe_set_phy_power(hw, false);
2396         } else {
2397                 /* Turn off the laser */
2398                 ixgbe_disable_tx_laser(hw);
2399         }
2400
2401         ixgbe_dev_clear_queues(dev);
2402
2403         /* Clear stored conf */
2404         dev->data->scattered_rx = 0;
2405         dev->data->lro = 0;
2406
2407         /* Clear recorded link status */
2408         memset(&link, 0, sizeof(link));
2409         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2410
2411         /* Remove all ntuple filters of the device */
2412         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2413              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2414                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2415                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2416                              p_5tuple, entries);
2417                 rte_free(p_5tuple);
2418         }
2419         memset(filter_info->fivetuple_mask, 0,
2420                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2421
2422         if (!rte_intr_allow_others(intr_handle))
2423                 /* resume to the default handler */
2424                 rte_intr_callback_register(intr_handle,
2425                                            ixgbe_dev_interrupt_handler,
2426                                            (void *)dev);
2427
2428         /* Clean datapath event and queue/vec mapping */
2429         rte_intr_efd_disable(intr_handle);
2430         if (intr_handle->intr_vec != NULL) {
2431                 rte_free(intr_handle->intr_vec);
2432                 intr_handle->intr_vec = NULL;
2433         }
2434 }
2435
2436 /*
2437  * Set device link up: enable tx.
2438  */
2439 static int
2440 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2441 {
2442         struct ixgbe_hw *hw =
2443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444         if (hw->mac.type == ixgbe_mac_82599EB) {
2445 #ifdef RTE_NIC_BYPASS
2446                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2447                         /* Not suported in bypass mode */
2448                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2449                                      "by device id 0x%x", hw->device_id);
2450                         return -ENOTSUP;
2451                 }
2452 #endif
2453         }
2454
2455         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2456                 /* Turn on the copper */
2457                 ixgbe_set_phy_power(hw, true);
2458         } else {
2459                 /* Turn on the laser */
2460                 ixgbe_enable_tx_laser(hw);
2461         }
2462
2463         return 0;
2464 }
2465
2466 /*
2467  * Set device link down: disable tx.
2468  */
2469 static int
2470 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2471 {
2472         struct ixgbe_hw *hw =
2473                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474         if (hw->mac.type == ixgbe_mac_82599EB) {
2475 #ifdef RTE_NIC_BYPASS
2476                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2477                         /* Not suported in bypass mode */
2478                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2479                                      "by device id 0x%x", hw->device_id);
2480                         return -ENOTSUP;
2481                 }
2482 #endif
2483         }
2484
2485         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2486                 /* Turn off the copper */
2487                 ixgbe_set_phy_power(hw, false);
2488         } else {
2489                 /* Turn off the laser */
2490                 ixgbe_disable_tx_laser(hw);
2491         }
2492
2493         return 0;
2494 }
2495
2496 /*
2497  * Reest and stop device.
2498  */
2499 static void
2500 ixgbe_dev_close(struct rte_eth_dev *dev)
2501 {
2502         struct ixgbe_hw *hw =
2503                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504
2505         PMD_INIT_FUNC_TRACE();
2506
2507         ixgbe_pf_reset_hw(hw);
2508
2509         ixgbe_dev_stop(dev);
2510         hw->adapter_stopped = 1;
2511
2512         ixgbe_dev_free_queues(dev);
2513
2514         ixgbe_disable_pcie_master(hw);
2515
2516         /* reprogram the RAR[0] in case user changed it. */
2517         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2518 }
2519
2520 static void
2521 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2522                            struct ixgbe_hw_stats *hw_stats,
2523                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2524                            uint64_t *total_qprc, uint64_t *total_qprdc)
2525 {
2526         uint32_t bprc, lxon, lxoff, total;
2527         uint32_t delta_gprc = 0;
2528         unsigned i;
2529         /* Workaround for RX byte count not including CRC bytes when CRC
2530 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2531          * is disabled.
2532 +        */
2533         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2534                         IXGBE_HLREG0_RXCRCSTRP);
2535
2536         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2537         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2538         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2539         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2540
2541         for (i = 0; i < 8; i++) {
2542                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2543
2544                 /* global total per queue */
2545                 hw_stats->mpc[i] += mp;
2546                 /* Running comprehensive total for stats display */
2547                 *total_missed_rx += hw_stats->mpc[i];
2548                 if (hw->mac.type == ixgbe_mac_82598EB) {
2549                         hw_stats->rnbc[i] +=
2550                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2551                         hw_stats->pxonrxc[i] +=
2552                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2553                         hw_stats->pxoffrxc[i] +=
2554                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2555                 } else {
2556                         hw_stats->pxonrxc[i] +=
2557                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2558                         hw_stats->pxoffrxc[i] +=
2559                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2560                         hw_stats->pxon2offc[i] +=
2561                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2562                 }
2563                 hw_stats->pxontxc[i] +=
2564                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2565                 hw_stats->pxofftxc[i] +=
2566                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2567         }
2568         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2569                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2570                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2571                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2572
2573                 delta_gprc += delta_qprc;
2574
2575                 hw_stats->qprc[i] += delta_qprc;
2576                 hw_stats->qptc[i] += delta_qptc;
2577
2578                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2579                 hw_stats->qbrc[i] +=
2580                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2581                 if (crc_strip == 0)
2582                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2583
2584                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2585                 hw_stats->qbtc[i] +=
2586                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2587
2588                 hw_stats->qprdc[i] += delta_qprdc;
2589                 *total_qprdc += hw_stats->qprdc[i];
2590
2591                 *total_qprc += hw_stats->qprc[i];
2592                 *total_qbrc += hw_stats->qbrc[i];
2593         }
2594         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2595         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2596         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2597
2598         /*
2599          * An errata states that gprc actually counts good + missed packets:
2600          * Workaround to set gprc to summated queue packet receives
2601          */
2602         hw_stats->gprc = *total_qprc;
2603
2604         if (hw->mac.type != ixgbe_mac_82598EB) {
2605                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2606                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2607                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2608                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2609                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2610                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2611                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2612                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2613         } else {
2614                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2615                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2616                 /* 82598 only has a counter in the high register */
2617                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2618                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2619                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2620         }
2621         uint64_t old_tpr = hw_stats->tpr;
2622
2623         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2624         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2625
2626         if (crc_strip == 0)
2627                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2628
2629         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2630         hw_stats->gptc += delta_gptc;
2631         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2632         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2633
2634         /*
2635          * Workaround: mprc hardware is incorrectly counting
2636          * broadcasts, so for now we subtract those.
2637          */
2638         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2639         hw_stats->bprc += bprc;
2640         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2641         if (hw->mac.type == ixgbe_mac_82598EB)
2642                 hw_stats->mprc -= bprc;
2643
2644         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2645         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2646         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2647         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2648         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2649         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2650
2651         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2652         hw_stats->lxontxc += lxon;
2653         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2654         hw_stats->lxofftxc += lxoff;
2655         total = lxon + lxoff;
2656
2657         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2658         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2659         hw_stats->gptc -= total;
2660         hw_stats->mptc -= total;
2661         hw_stats->ptc64 -= total;
2662         hw_stats->gotc -= total * ETHER_MIN_LEN;
2663
2664         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2665         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2666         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2667         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2668         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2669         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2670         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2671         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2672         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2673         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2674         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2675         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2676         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2677         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2678         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2679         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2680         /* Only read FCOE on 82599 */
2681         if (hw->mac.type != ixgbe_mac_82598EB) {
2682                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2683                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2684                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2685                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2686                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2687         }
2688
2689         /* Flow Director Stats registers */
2690         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2691         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2692 }
2693
2694 /*
2695  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2696  */
2697 static void
2698 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2699 {
2700         struct ixgbe_hw *hw =
2701                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         struct ixgbe_hw_stats *hw_stats =
2703                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2704         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2705         unsigned i;
2706
2707         total_missed_rx = 0;
2708         total_qbrc = 0;
2709         total_qprc = 0;
2710         total_qprdc = 0;
2711
2712         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2713                         &total_qprc, &total_qprdc);
2714
2715         if (stats == NULL)
2716                 return;
2717
2718         /* Fill out the rte_eth_stats statistics structure */
2719         stats->ipackets = total_qprc;
2720         stats->ibytes = total_qbrc;
2721         stats->opackets = hw_stats->gptc;
2722         stats->obytes = hw_stats->gotc;
2723
2724         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2725                 stats->q_ipackets[i] = hw_stats->qprc[i];
2726                 stats->q_opackets[i] = hw_stats->qptc[i];
2727                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2728                 stats->q_obytes[i] = hw_stats->qbtc[i];
2729                 stats->q_errors[i] = hw_stats->qprdc[i];
2730         }
2731
2732         /* Rx Errors */
2733         stats->imissed  = total_missed_rx;
2734         stats->ierrors  = hw_stats->crcerrs +
2735                           hw_stats->mspdc +
2736                           hw_stats->rlec +
2737                           hw_stats->ruc +
2738                           hw_stats->roc +
2739                           hw_stats->illerrc +
2740                           hw_stats->errbc +
2741                           hw_stats->rfc +
2742                           hw_stats->fccrc +
2743                           hw_stats->fclast;
2744
2745         /* Tx Errors */
2746         stats->oerrors  = 0;
2747 }
2748
2749 static void
2750 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2751 {
2752         struct ixgbe_hw_stats *stats =
2753                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2754
2755         /* HW registers are cleared on read */
2756         ixgbe_dev_stats_get(dev, NULL);
2757
2758         /* Reset software totals */
2759         memset(stats, 0, sizeof(*stats));
2760 }
2761
2762 /* This function calculates the number of xstats based on the current config */
2763 static unsigned
2764 ixgbe_xstats_calc_num(void) {
2765         return IXGBE_NB_HW_STATS +
2766                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2767                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2768 }
2769
2770 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2771         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2772 {
2773         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2774         unsigned stat, i, count;
2775
2776         if (xstats_names != NULL) {
2777                 count = 0;
2778
2779                 /* Note: limit >= cnt_stats checked upstream
2780                  * in rte_eth_xstats_names()
2781                  */
2782
2783                 /* Extended stats from ixgbe_hw_stats */
2784                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2785                         snprintf(xstats_names[count].name,
2786                                 sizeof(xstats_names[count].name),
2787                                 "%s",
2788                                 rte_ixgbe_stats_strings[i].name);
2789                         count++;
2790                 }
2791
2792                 /* RX Priority Stats */
2793                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2794                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2795                                 snprintf(xstats_names[count].name,
2796                                         sizeof(xstats_names[count].name),
2797                                         "rx_priority%u_%s", i,
2798                                         rte_ixgbe_rxq_strings[stat].name);
2799                                 count++;
2800                         }
2801                 }
2802
2803                 /* TX Priority Stats */
2804                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2805                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2806                                 snprintf(xstats_names[count].name,
2807                                         sizeof(xstats_names[count].name),
2808                                         "tx_priority%u_%s", i,
2809                                         rte_ixgbe_txq_strings[stat].name);
2810                                 count++;
2811                         }
2812                 }
2813         }
2814         return cnt_stats;
2815 }
2816
2817 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2818         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2819 {
2820         unsigned i;
2821
2822         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2823                 return -ENOMEM;
2824
2825         if (xstats_names != NULL)
2826                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2827                         snprintf(xstats_names[i].name,
2828                                 sizeof(xstats_names[i].name),
2829                                 "%s", rte_ixgbevf_stats_strings[i].name);
2830         return IXGBEVF_NB_XSTATS;
2831 }
2832
2833 static int
2834 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2835                                          unsigned n)
2836 {
2837         struct ixgbe_hw *hw =
2838                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct ixgbe_hw_stats *hw_stats =
2840                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2841         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2842         unsigned i, stat, count = 0;
2843
2844         count = ixgbe_xstats_calc_num();
2845
2846         if (n < count)
2847                 return count;
2848
2849         total_missed_rx = 0;
2850         total_qbrc = 0;
2851         total_qprc = 0;
2852         total_qprdc = 0;
2853
2854         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2855                                    &total_qprc, &total_qprdc);
2856
2857         /* If this is a reset xstats is NULL, and we have cleared the
2858          * registers by reading them.
2859          */
2860         if (!xstats)
2861                 return 0;
2862
2863         /* Extended stats from ixgbe_hw_stats */
2864         count = 0;
2865         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2866                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2867                                 rte_ixgbe_stats_strings[i].offset);
2868                 count++;
2869         }
2870
2871         /* RX Priority Stats */
2872         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2873                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2874                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2875                                         rte_ixgbe_rxq_strings[stat].offset +
2876                                         (sizeof(uint64_t) * i));
2877                         count++;
2878                 }
2879         }
2880
2881         /* TX Priority Stats */
2882         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2883                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2884                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2885                                         rte_ixgbe_txq_strings[stat].offset +
2886                                         (sizeof(uint64_t) * i));
2887                         count++;
2888                 }
2889         }
2890         return count;
2891 }
2892
2893 static void
2894 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2895 {
2896         struct ixgbe_hw_stats *stats =
2897                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2898
2899         unsigned count = ixgbe_xstats_calc_num();
2900
2901         /* HW registers are cleared on read */
2902         ixgbe_dev_xstats_get(dev, NULL, count);
2903
2904         /* Reset software totals */
2905         memset(stats, 0, sizeof(*stats));
2906 }
2907
2908 static void
2909 ixgbevf_update_stats(struct rte_eth_dev *dev)
2910 {
2911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2913                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2914
2915         /* Good Rx packet, include VF loopback */
2916         UPDATE_VF_STAT(IXGBE_VFGPRC,
2917             hw_stats->last_vfgprc, hw_stats->vfgprc);
2918
2919         /* Good Rx octets, include VF loopback */
2920         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2921             hw_stats->last_vfgorc, hw_stats->vfgorc);
2922
2923         /* Good Tx packet, include VF loopback */
2924         UPDATE_VF_STAT(IXGBE_VFGPTC,
2925             hw_stats->last_vfgptc, hw_stats->vfgptc);
2926
2927         /* Good Tx octets, include VF loopback */
2928         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2929             hw_stats->last_vfgotc, hw_stats->vfgotc);
2930
2931         /* Rx Multicst Packet */
2932         UPDATE_VF_STAT(IXGBE_VFMPRC,
2933             hw_stats->last_vfmprc, hw_stats->vfmprc);
2934 }
2935
2936 static int
2937 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2938                        unsigned n)
2939 {
2940         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2941                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2942         unsigned i;
2943
2944         if (n < IXGBEVF_NB_XSTATS)
2945                 return IXGBEVF_NB_XSTATS;
2946
2947         ixgbevf_update_stats(dev);
2948
2949         if (!xstats)
2950                 return 0;
2951
2952         /* Extended stats */
2953         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2954                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2955                         rte_ixgbevf_stats_strings[i].offset);
2956         }
2957
2958         return IXGBEVF_NB_XSTATS;
2959 }
2960
2961 static void
2962 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2963 {
2964         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2965                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2966
2967         ixgbevf_update_stats(dev);
2968
2969         if (stats == NULL)
2970                 return;
2971
2972         stats->ipackets = hw_stats->vfgprc;
2973         stats->ibytes = hw_stats->vfgorc;
2974         stats->opackets = hw_stats->vfgptc;
2975         stats->obytes = hw_stats->vfgotc;
2976 }
2977
2978 static void
2979 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2980 {
2981         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2982                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2983
2984         /* Sync HW register to the last stats */
2985         ixgbevf_dev_stats_get(dev, NULL);
2986
2987         /* reset HW current stats*/
2988         hw_stats->vfgprc = 0;
2989         hw_stats->vfgorc = 0;
2990         hw_stats->vfgptc = 0;
2991         hw_stats->vfgotc = 0;
2992 }
2993
2994 static void
2995 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2996 {
2997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2999
3000         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3001         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3002         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3003                 /*
3004                  * When DCB/VT is off, maximum number of queues changes,
3005                  * except for 82598EB, which remains constant.
3006                  */
3007                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3008                                 hw->mac.type != ixgbe_mac_82598EB)
3009                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3010         }
3011         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3012         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3013         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3014         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3015         dev_info->max_vfs = dev->pci_dev->max_vfs;
3016         if (hw->mac.type == ixgbe_mac_82598EB)
3017                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3018         else
3019                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3020         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3021         dev_info->rx_offload_capa =
3022                 DEV_RX_OFFLOAD_VLAN_STRIP |
3023                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3024                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3025                 DEV_RX_OFFLOAD_TCP_CKSUM;
3026
3027         /*
3028          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3029          * mode.
3030          */
3031         if ((hw->mac.type == ixgbe_mac_82599EB ||
3032              hw->mac.type == ixgbe_mac_X540) &&
3033             !RTE_ETH_DEV_SRIOV(dev).active)
3034                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3035
3036         if (hw->mac.type == ixgbe_mac_X550 ||
3037             hw->mac.type == ixgbe_mac_X550EM_x ||
3038             hw->mac.type == ixgbe_mac_X550EM_a)
3039                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3040
3041         dev_info->tx_offload_capa =
3042                 DEV_TX_OFFLOAD_VLAN_INSERT |
3043                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3044                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3045                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3046                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3047                 DEV_TX_OFFLOAD_TCP_TSO;
3048
3049         if (hw->mac.type == ixgbe_mac_X550 ||
3050             hw->mac.type == ixgbe_mac_X550EM_x ||
3051             hw->mac.type == ixgbe_mac_X550EM_a)
3052                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3053
3054         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3055                 .rx_thresh = {
3056                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3057                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3058                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3059                 },
3060                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3061                 .rx_drop_en = 0,
3062         };
3063
3064         dev_info->default_txconf = (struct rte_eth_txconf) {
3065                 .tx_thresh = {
3066                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3067                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3068                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3069                 },
3070                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3071                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3072                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3073                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3074         };
3075
3076         dev_info->rx_desc_lim = rx_desc_lim;
3077         dev_info->tx_desc_lim = tx_desc_lim;
3078
3079         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3080         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3081         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3082
3083         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3084         if (hw->mac.type == ixgbe_mac_X540 ||
3085             hw->mac.type == ixgbe_mac_X540_vf ||
3086             hw->mac.type == ixgbe_mac_X550 ||
3087             hw->mac.type == ixgbe_mac_X550_vf) {
3088                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3089         }
3090 }
3091
3092 static const uint32_t *
3093 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3094 {
3095         static const uint32_t ptypes[] = {
3096                 /* For non-vec functions,
3097                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3098                  * for vec functions,
3099                  * refers to _recv_raw_pkts_vec().
3100                  */
3101                 RTE_PTYPE_L2_ETHER,
3102                 RTE_PTYPE_L3_IPV4,
3103                 RTE_PTYPE_L3_IPV4_EXT,
3104                 RTE_PTYPE_L3_IPV6,
3105                 RTE_PTYPE_L3_IPV6_EXT,
3106                 RTE_PTYPE_L4_SCTP,
3107                 RTE_PTYPE_L4_TCP,
3108                 RTE_PTYPE_L4_UDP,
3109                 RTE_PTYPE_TUNNEL_IP,
3110                 RTE_PTYPE_INNER_L3_IPV6,
3111                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3112                 RTE_PTYPE_INNER_L4_TCP,
3113                 RTE_PTYPE_INNER_L4_UDP,
3114                 RTE_PTYPE_UNKNOWN
3115         };
3116
3117         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3118             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3119             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3120             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3121                 return ptypes;
3122         return NULL;
3123 }
3124
3125 static void
3126 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3127                      struct rte_eth_dev_info *dev_info)
3128 {
3129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130
3131         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3132         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3133         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3134         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3135         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3136         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3137         dev_info->max_vfs = dev->pci_dev->max_vfs;
3138         if (hw->mac.type == ixgbe_mac_82598EB)
3139                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3140         else
3141                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3142         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3143                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3144                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3145                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3146         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3147                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3148                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3149                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3150                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3151                                 DEV_TX_OFFLOAD_TCP_TSO;
3152
3153         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3154                 .rx_thresh = {
3155                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3156                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3157                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3158                 },
3159                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3160                 .rx_drop_en = 0,
3161         };
3162
3163         dev_info->default_txconf = (struct rte_eth_txconf) {
3164                 .tx_thresh = {
3165                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3166                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3167                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3168                 },
3169                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3170                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3171                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3172                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3173         };
3174
3175         dev_info->rx_desc_lim = rx_desc_lim;
3176         dev_info->tx_desc_lim = tx_desc_lim;
3177 }
3178
3179 /* return 0 means link status changed, -1 means not changed */
3180 static int
3181 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3182 {
3183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184         struct rte_eth_link link, old;
3185         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3186         int link_up;
3187         int diag;
3188
3189         link.link_status = ETH_LINK_DOWN;
3190         link.link_speed = 0;
3191         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3192         memset(&old, 0, sizeof(old));
3193         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3194
3195         hw->mac.get_link_status = true;
3196
3197         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3198         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3199                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3200         else
3201                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3202
3203         if (diag != 0) {
3204                 link.link_speed = ETH_SPEED_NUM_100M;
3205                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3206                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3207                 if (link.link_status == old.link_status)
3208                         return -1;
3209                 return 0;
3210         }
3211
3212         if (link_up == 0) {
3213                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3214                 if (link.link_status == old.link_status)
3215                         return -1;
3216                 return 0;
3217         }
3218         link.link_status = ETH_LINK_UP;
3219         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3220
3221         switch (link_speed) {
3222         default:
3223         case IXGBE_LINK_SPEED_UNKNOWN:
3224                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3225                 link.link_speed = ETH_SPEED_NUM_100M;
3226                 break;
3227
3228         case IXGBE_LINK_SPEED_100_FULL:
3229                 link.link_speed = ETH_SPEED_NUM_100M;
3230                 break;
3231
3232         case IXGBE_LINK_SPEED_1GB_FULL:
3233                 link.link_speed = ETH_SPEED_NUM_1G;
3234                 break;
3235
3236         case IXGBE_LINK_SPEED_10GB_FULL:
3237                 link.link_speed = ETH_SPEED_NUM_10G;
3238                 break;
3239         }
3240         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3241
3242         if (link.link_status == old.link_status)
3243                 return -1;
3244
3245         return 0;
3246 }
3247
3248 static void
3249 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3250 {
3251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252         uint32_t fctrl;
3253
3254         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3255         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3256         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3257 }
3258
3259 static void
3260 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3261 {
3262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263         uint32_t fctrl;
3264
3265         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3266         fctrl &= (~IXGBE_FCTRL_UPE);
3267         if (dev->data->all_multicast == 1)
3268                 fctrl |= IXGBE_FCTRL_MPE;
3269         else
3270                 fctrl &= (~IXGBE_FCTRL_MPE);
3271         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3272 }
3273
3274 static void
3275 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3276 {
3277         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         uint32_t fctrl;
3279
3280         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3281         fctrl |= IXGBE_FCTRL_MPE;
3282         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3283 }
3284
3285 static void
3286 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3287 {
3288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289         uint32_t fctrl;
3290
3291         if (dev->data->promiscuous == 1)
3292                 return; /* must remain in all_multicast mode */
3293
3294         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3295         fctrl &= (~IXGBE_FCTRL_MPE);
3296         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3297 }
3298
3299 /**
3300  * It clears the interrupt causes and enables the interrupt.
3301  * It will be called once only during nic initialized.
3302  *
3303  * @param dev
3304  *  Pointer to struct rte_eth_dev.
3305  *
3306  * @return
3307  *  - On success, zero.
3308  *  - On failure, a negative value.
3309  */
3310 static int
3311 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3312 {
3313         struct ixgbe_interrupt *intr =
3314                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3315
3316         ixgbe_dev_link_status_print(dev);
3317         intr->mask |= IXGBE_EICR_LSC;
3318
3319         return 0;
3320 }
3321
3322 /**
3323  * It clears the interrupt causes and enables the interrupt.
3324  * It will be called once only during nic initialized.
3325  *
3326  * @param dev
3327  *  Pointer to struct rte_eth_dev.
3328  *
3329  * @return
3330  *  - On success, zero.
3331  *  - On failure, a negative value.
3332  */
3333 static int
3334 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3335 {
3336         struct ixgbe_interrupt *intr =
3337                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3338
3339         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3340
3341         return 0;
3342 }
3343
3344 /*
3345  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3346  *
3347  * @param dev
3348  *  Pointer to struct rte_eth_dev.
3349  *
3350  * @return
3351  *  - On success, zero.
3352  *  - On failure, a negative value.
3353  */
3354 static int
3355 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3356 {
3357         uint32_t eicr;
3358         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359         struct ixgbe_interrupt *intr =
3360                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3361
3362         /* clear all cause mask */
3363         ixgbe_disable_intr(hw);
3364
3365         /* read-on-clear nic registers here */
3366         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3367         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3368
3369         intr->flags = 0;
3370
3371         /* set flag for async link update */
3372         if (eicr & IXGBE_EICR_LSC)
3373                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3374
3375         if (eicr & IXGBE_EICR_MAILBOX)
3376                 intr->flags |= IXGBE_FLAG_MAILBOX;
3377
3378         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3379             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3380             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3381                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3382
3383         return 0;
3384 }
3385
3386 /**
3387  * It gets and then prints the link status.
3388  *
3389  * @param dev
3390  *  Pointer to struct rte_eth_dev.
3391  *
3392  * @return
3393  *  - On success, zero.
3394  *  - On failure, a negative value.
3395  */
3396 static void
3397 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3398 {
3399         struct rte_eth_link link;
3400
3401         memset(&link, 0, sizeof(link));
3402         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3403         if (link.link_status) {
3404                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3405                                         (int)(dev->data->port_id),
3406                                         (unsigned)link.link_speed,
3407                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3408                                         "full-duplex" : "half-duplex");
3409         } else {
3410                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3411                                 (int)(dev->data->port_id));
3412         }
3413         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3414                                 dev->pci_dev->addr.domain,
3415                                 dev->pci_dev->addr.bus,
3416                                 dev->pci_dev->addr.devid,
3417                                 dev->pci_dev->addr.function);
3418 }
3419
3420 /*
3421  * It executes link_update after knowing an interrupt occurred.
3422  *
3423  * @param dev
3424  *  Pointer to struct rte_eth_dev.
3425  *
3426  * @return
3427  *  - On success, zero.
3428  *  - On failure, a negative value.
3429  */
3430 static int
3431 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3432 {
3433         struct ixgbe_interrupt *intr =
3434                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3435         int64_t timeout;
3436         struct rte_eth_link link;
3437         int intr_enable_delay = false;
3438         struct ixgbe_hw *hw =
3439                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440
3441         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3442
3443         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3444                 ixgbe_pf_mbx_process(dev);
3445                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3446         }
3447
3448         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3449                 ixgbe_handle_lasi(hw);
3450                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3451         }
3452
3453         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3454                 /* get the link status before link update, for predicting later */
3455                 memset(&link, 0, sizeof(link));
3456                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3457
3458                 ixgbe_dev_link_update(dev, 0);
3459
3460                 /* likely to up */
3461                 if (!link.link_status)
3462                         /* handle it 1 sec later, wait it being stable */
3463                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3464                 /* likely to down */
3465                 else
3466                         /* handle it 4 sec later, wait it being stable */
3467                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3468
3469                 ixgbe_dev_link_status_print(dev);
3470
3471                 intr_enable_delay = true;
3472         }
3473
3474         if (intr_enable_delay) {
3475                 if (rte_eal_alarm_set(timeout * 1000,
3476                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3477                         PMD_DRV_LOG(ERR, "Error setting alarm");
3478         } else {
3479                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3480                 ixgbe_enable_intr(dev);
3481                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3482         }
3483
3484
3485         return 0;
3486 }
3487
3488 /**
3489  * Interrupt handler which shall be registered for alarm callback for delayed
3490  * handling specific interrupt to wait for the stable nic state. As the
3491  * NIC interrupt state is not stable for ixgbe after link is just down,
3492  * it needs to wait 4 seconds to get the stable status.
3493  *
3494  * @param handle
3495  *  Pointer to interrupt handle.
3496  * @param param
3497  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3498  *
3499  * @return
3500  *  void
3501  */
3502 static void
3503 ixgbe_dev_interrupt_delayed_handler(void *param)
3504 {
3505         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3506         struct ixgbe_interrupt *intr =
3507                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3508         struct ixgbe_hw *hw =
3509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         uint32_t eicr;
3511
3512         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3513         if (eicr & IXGBE_EICR_MAILBOX)
3514                 ixgbe_pf_mbx_process(dev);
3515
3516         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3517                 ixgbe_handle_lasi(hw);
3518                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3519         }
3520
3521         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3522                 ixgbe_dev_link_update(dev, 0);
3523                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3524                 ixgbe_dev_link_status_print(dev);
3525                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3526         }
3527
3528         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3529         ixgbe_enable_intr(dev);
3530         rte_intr_enable(&(dev->pci_dev->intr_handle));
3531 }
3532
3533 /**
3534  * Interrupt handler triggered by NIC  for handling
3535  * specific interrupt.
3536  *
3537  * @param handle
3538  *  Pointer to interrupt handle.
3539  * @param param
3540  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3541  *
3542  * @return
3543  *  void
3544  */
3545 static void
3546 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3547                             void *param)
3548 {
3549         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3550
3551         ixgbe_dev_interrupt_get_status(dev);
3552         ixgbe_dev_interrupt_action(dev);
3553 }
3554
3555 static int
3556 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3557 {
3558         struct ixgbe_hw *hw;
3559
3560         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3562 }
3563
3564 static int
3565 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3566 {
3567         struct ixgbe_hw *hw;
3568
3569         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3571 }
3572
3573 static int
3574 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3575 {
3576         struct ixgbe_hw *hw;
3577         uint32_t mflcn_reg;
3578         uint32_t fccfg_reg;
3579         int rx_pause;
3580         int tx_pause;
3581
3582         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3583
3584         fc_conf->pause_time = hw->fc.pause_time;
3585         fc_conf->high_water = hw->fc.high_water[0];
3586         fc_conf->low_water = hw->fc.low_water[0];
3587         fc_conf->send_xon = hw->fc.send_xon;
3588         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3589
3590         /*
3591          * Return rx_pause status according to actual setting of
3592          * MFLCN register.
3593          */
3594         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3595         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3596                 rx_pause = 1;
3597         else
3598                 rx_pause = 0;
3599
3600         /*
3601          * Return tx_pause status according to actual setting of
3602          * FCCFG register.
3603          */
3604         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3605         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3606                 tx_pause = 1;
3607         else
3608                 tx_pause = 0;
3609
3610         if (rx_pause && tx_pause)
3611                 fc_conf->mode = RTE_FC_FULL;
3612         else if (rx_pause)
3613                 fc_conf->mode = RTE_FC_RX_PAUSE;
3614         else if (tx_pause)
3615                 fc_conf->mode = RTE_FC_TX_PAUSE;
3616         else
3617                 fc_conf->mode = RTE_FC_NONE;
3618
3619         return 0;
3620 }
3621
3622 static int
3623 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3624 {
3625         struct ixgbe_hw *hw;
3626         int err;
3627         uint32_t rx_buf_size;
3628         uint32_t max_high_water;
3629         uint32_t mflcn;
3630         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3631                 ixgbe_fc_none,
3632                 ixgbe_fc_rx_pause,
3633                 ixgbe_fc_tx_pause,
3634                 ixgbe_fc_full
3635         };
3636
3637         PMD_INIT_FUNC_TRACE();
3638
3639         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3641         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3642
3643         /*
3644          * At least reserve one Ethernet frame for watermark
3645          * high_water/low_water in kilo bytes for ixgbe
3646          */
3647         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3648         if ((fc_conf->high_water > max_high_water) ||
3649                 (fc_conf->high_water < fc_conf->low_water)) {
3650                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3651                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3652                 return -EINVAL;
3653         }
3654
3655         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3656         hw->fc.pause_time     = fc_conf->pause_time;
3657         hw->fc.high_water[0]  = fc_conf->high_water;
3658         hw->fc.low_water[0]   = fc_conf->low_water;
3659         hw->fc.send_xon       = fc_conf->send_xon;
3660         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3661
3662         err = ixgbe_fc_enable(hw);
3663
3664         /* Not negotiated is not an error case */
3665         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3666
3667                 /* check if we want to forward MAC frames - driver doesn't have native
3668                  * capability to do that, so we'll write the registers ourselves */
3669
3670                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3671
3672                 /* set or clear MFLCN.PMCF bit depending on configuration */
3673                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3674                         mflcn |= IXGBE_MFLCN_PMCF;
3675                 else
3676                         mflcn &= ~IXGBE_MFLCN_PMCF;
3677
3678                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3679                 IXGBE_WRITE_FLUSH(hw);
3680
3681                 return 0;
3682         }
3683
3684         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3685         return -EIO;
3686 }
3687
3688 /**
3689  *  ixgbe_pfc_enable_generic - Enable flow control
3690  *  @hw: pointer to hardware structure
3691  *  @tc_num: traffic class number
3692  *  Enable flow control according to the current settings.
3693  */
3694 static int
3695 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3696 {
3697         int ret_val = 0;
3698         uint32_t mflcn_reg, fccfg_reg;
3699         uint32_t reg;
3700         uint32_t fcrtl, fcrth;
3701         uint8_t i;
3702         uint8_t nb_rx_en;
3703
3704         /* Validate the water mark configuration */
3705         if (!hw->fc.pause_time) {
3706                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3707                 goto out;
3708         }
3709
3710         /* Low water mark of zero causes XOFF floods */
3711         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3712                  /* High/Low water can not be 0 */
3713                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3714                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3715                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3716                         goto out;
3717                 }
3718
3719                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3720                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3721                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3722                         goto out;
3723                 }
3724         }
3725         /* Negotiate the fc mode to use */
3726         ixgbe_fc_autoneg(hw);
3727
3728         /* Disable any previous flow control settings */
3729         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3730         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3731
3732         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3733         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3734
3735         switch (hw->fc.current_mode) {
3736         case ixgbe_fc_none:
3737                 /*
3738                  * If the count of enabled RX Priority Flow control >1,
3739                  * and the TX pause can not be disabled
3740                  */
3741                 nb_rx_en = 0;
3742                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3743                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3744                         if (reg & IXGBE_FCRTH_FCEN)
3745                                 nb_rx_en++;
3746                 }
3747                 if (nb_rx_en > 1)
3748                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3749                 break;
3750         case ixgbe_fc_rx_pause:
3751                 /*
3752                  * Rx Flow control is enabled and Tx Flow control is
3753                  * disabled by software override. Since there really
3754                  * isn't a way to advertise that we are capable of RX
3755                  * Pause ONLY, we will advertise that we support both
3756                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3757                  * disable the adapter's ability to send PAUSE frames.
3758                  */
3759                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3760                 /*
3761                  * If the count of enabled RX Priority Flow control >1,
3762                  * and the TX pause can not be disabled
3763                  */
3764                 nb_rx_en = 0;
3765                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3766                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3767                         if (reg & IXGBE_FCRTH_FCEN)
3768                                 nb_rx_en++;
3769                 }
3770                 if (nb_rx_en > 1)
3771                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3772                 break;
3773         case ixgbe_fc_tx_pause:
3774                 /*
3775                  * Tx Flow control is enabled, and Rx Flow control is
3776                  * disabled by software override.
3777                  */
3778                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3779                 break;
3780         case ixgbe_fc_full:
3781                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3782                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3783                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3784                 break;
3785         default:
3786                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3787                 ret_val = IXGBE_ERR_CONFIG;
3788                 goto out;
3789         }
3790
3791         /* Set 802.3x based flow control settings. */
3792         mflcn_reg |= IXGBE_MFLCN_DPF;
3793         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3794         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3795
3796         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3797         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3798                 hw->fc.high_water[tc_num]) {
3799                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3800                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3801                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3802         } else {
3803                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3804                 /*
3805                  * In order to prevent Tx hangs when the internal Tx
3806                  * switch is enabled we must set the high water mark
3807                  * to the maximum FCRTH value.  This allows the Tx
3808                  * switch to function even under heavy Rx workloads.
3809                  */
3810                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3811         }
3812         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3813
3814         /* Configure pause time (2 TCs per register) */
3815         reg = hw->fc.pause_time * 0x00010001;
3816         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3817                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3818
3819         /* Configure flow control refresh threshold value */
3820         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3821
3822 out:
3823         return ret_val;
3824 }
3825
3826 static int
3827 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3828 {
3829         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3830         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3831
3832         if (hw->mac.type != ixgbe_mac_82598EB) {
3833                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3834         }
3835         return ret_val;
3836 }
3837
3838 static int
3839 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3840 {
3841         int err;
3842         uint32_t rx_buf_size;
3843         uint32_t max_high_water;
3844         uint8_t tc_num;
3845         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3846         struct ixgbe_hw *hw =
3847                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848         struct ixgbe_dcb_config *dcb_config =
3849                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3850
3851         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3852                 ixgbe_fc_none,
3853                 ixgbe_fc_rx_pause,
3854                 ixgbe_fc_tx_pause,
3855                 ixgbe_fc_full
3856         };
3857
3858         PMD_INIT_FUNC_TRACE();
3859
3860         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3861         tc_num = map[pfc_conf->priority];
3862         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3863         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3864         /*
3865          * At least reserve one Ethernet frame for watermark
3866          * high_water/low_water in kilo bytes for ixgbe
3867          */
3868         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3869         if ((pfc_conf->fc.high_water > max_high_water) ||
3870             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3871                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3872                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3873                 return -EINVAL;
3874         }
3875
3876         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3877         hw->fc.pause_time = pfc_conf->fc.pause_time;
3878         hw->fc.send_xon = pfc_conf->fc.send_xon;
3879         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3880         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3881
3882         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3883
3884         /* Not negotiated is not an error case */
3885         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3886                 return 0;
3887
3888         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3889         return -EIO;
3890 }
3891
3892 static int
3893 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3894                           struct rte_eth_rss_reta_entry64 *reta_conf,
3895                           uint16_t reta_size)
3896 {
3897         uint16_t i, sp_reta_size;
3898         uint8_t j, mask;
3899         uint32_t reta, r;
3900         uint16_t idx, shift;
3901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3902         uint32_t reta_reg;
3903
3904         PMD_INIT_FUNC_TRACE();
3905
3906         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3907                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3908                         "NIC.");
3909                 return -ENOTSUP;
3910         }
3911
3912         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3913         if (reta_size != sp_reta_size) {
3914                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3915                         "(%d) doesn't match the number hardware can supported "
3916                         "(%d)\n", reta_size, sp_reta_size);
3917                 return -EINVAL;
3918         }
3919
3920         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3921                 idx = i / RTE_RETA_GROUP_SIZE;
3922                 shift = i % RTE_RETA_GROUP_SIZE;
3923                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3924                                                 IXGBE_4_BIT_MASK);
3925                 if (!mask)
3926                         continue;
3927                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3928                 if (mask == IXGBE_4_BIT_MASK)
3929                         r = 0;
3930                 else
3931                         r = IXGBE_READ_REG(hw, reta_reg);
3932                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3933                         if (mask & (0x1 << j))
3934                                 reta |= reta_conf[idx].reta[shift + j] <<
3935                                                         (CHAR_BIT * j);
3936                         else
3937                                 reta |= r & (IXGBE_8_BIT_MASK <<
3938                                                 (CHAR_BIT * j));
3939                 }
3940                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3941         }
3942
3943         return 0;
3944 }
3945
3946 static int
3947 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3948                          struct rte_eth_rss_reta_entry64 *reta_conf,
3949                          uint16_t reta_size)
3950 {
3951         uint16_t i, sp_reta_size;
3952         uint8_t j, mask;
3953         uint32_t reta;
3954         uint16_t idx, shift;
3955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956         uint32_t reta_reg;
3957
3958         PMD_INIT_FUNC_TRACE();
3959         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3960         if (reta_size != sp_reta_size) {
3961                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3962                         "(%d) doesn't match the number hardware can supported "
3963                         "(%d)\n", reta_size, sp_reta_size);
3964                 return -EINVAL;
3965         }
3966
3967         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3968                 idx = i / RTE_RETA_GROUP_SIZE;
3969                 shift = i % RTE_RETA_GROUP_SIZE;
3970                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3971                                                 IXGBE_4_BIT_MASK);
3972                 if (!mask)
3973                         continue;
3974
3975                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3976                 reta = IXGBE_READ_REG(hw, reta_reg);
3977                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3978                         if (mask & (0x1 << j))
3979                                 reta_conf[idx].reta[shift + j] =
3980                                         ((reta >> (CHAR_BIT * j)) &
3981                                                 IXGBE_8_BIT_MASK);
3982                 }
3983         }
3984
3985         return 0;
3986 }
3987
3988 static void
3989 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3990                                 uint32_t index, uint32_t pool)
3991 {
3992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993         uint32_t enable_addr = 1;
3994
3995         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3996 }
3997
3998 static void
3999 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4000 {
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002
4003         ixgbe_clear_rar(hw, index);
4004 }
4005
4006 static void
4007 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4008 {
4009         ixgbe_remove_rar(dev, 0);
4010
4011         ixgbe_add_rar(dev, addr, 0, 0);
4012 }
4013
4014 static int
4015 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4016 {
4017         uint32_t hlreg0;
4018         uint32_t maxfrs;
4019         struct ixgbe_hw *hw;
4020         struct rte_eth_dev_info dev_info;
4021         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4022
4023         ixgbe_dev_info_get(dev, &dev_info);
4024
4025         /* check that mtu is within the allowed range */
4026         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4027                 return -EINVAL;
4028
4029         /* refuse mtu that requires the support of scattered packets when this
4030          * feature has not been enabled before.
4031          */
4032         if (!dev->data->scattered_rx &&
4033             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4034              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4035                 return -EINVAL;
4036
4037         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4039
4040         /* switch to jumbo mode if needed */
4041         if (frame_size > ETHER_MAX_LEN) {
4042                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4043                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4044         } else {
4045                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4046                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4047         }
4048         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4049
4050         /* update max frame size */
4051         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4052
4053         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4054         maxfrs &= 0x0000FFFF;
4055         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4056         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4057
4058         return 0;
4059 }
4060
4061 /*
4062  * Virtual Function operations
4063  */
4064 static void
4065 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4066 {
4067         PMD_INIT_FUNC_TRACE();
4068
4069         /* Clear interrupt mask to stop from interrupts being generated */
4070         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4071
4072         IXGBE_WRITE_FLUSH(hw);
4073 }
4074
4075 static void
4076 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4077 {
4078         PMD_INIT_FUNC_TRACE();
4079
4080         /* VF enable interrupt autoclean */
4081         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4082         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4083         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4084
4085         IXGBE_WRITE_FLUSH(hw);
4086 }
4087
4088 static int
4089 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4090 {
4091         struct rte_eth_conf *conf = &dev->data->dev_conf;
4092         struct ixgbe_adapter *adapter =
4093                         (struct ixgbe_adapter *)dev->data->dev_private;
4094
4095         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4096                      dev->data->port_id);
4097
4098         /*
4099          * VF has no ability to enable/disable HW CRC
4100          * Keep the persistent behavior the same as Host PF
4101          */
4102 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4103         if (!conf->rxmode.hw_strip_crc) {
4104                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4105                 conf->rxmode.hw_strip_crc = 1;
4106         }
4107 #else
4108         if (conf->rxmode.hw_strip_crc) {
4109                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4110                 conf->rxmode.hw_strip_crc = 0;
4111         }
4112 #endif
4113
4114         /*
4115          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4116          * allocation or vector Rx preconditions we will reset it.
4117          */
4118         adapter->rx_bulk_alloc_allowed = true;
4119         adapter->rx_vec_allowed = true;
4120
4121         return 0;
4122 }
4123
4124 static int
4125 ixgbevf_dev_start(struct rte_eth_dev *dev)
4126 {
4127         struct ixgbe_hw *hw =
4128                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t intr_vector = 0;
4130         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4131
4132         int err, mask = 0;
4133
4134         PMD_INIT_FUNC_TRACE();
4135
4136         hw->mac.ops.reset_hw(hw);
4137         hw->mac.get_link_status = true;
4138
4139         /* negotiate mailbox API version to use with the PF. */
4140         ixgbevf_negotiate_api(hw);
4141
4142         ixgbevf_dev_tx_init(dev);
4143
4144         /* This can fail when allocating mbufs for descriptor rings */
4145         err = ixgbevf_dev_rx_init(dev);
4146         if (err) {
4147                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4148                 ixgbe_dev_clear_queues(dev);
4149                 return err;
4150         }
4151
4152         /* Set vfta */
4153         ixgbevf_set_vfta_all(dev, 1);
4154
4155         /* Set HW strip */
4156         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4157                 ETH_VLAN_EXTEND_MASK;
4158         ixgbevf_vlan_offload_set(dev, mask);
4159
4160         ixgbevf_dev_rxtx_start(dev);
4161
4162         /* check and configure queue intr-vector mapping */
4163         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4164                 intr_vector = dev->data->nb_rx_queues;
4165                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4166                         return -1;
4167         }
4168
4169         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4170                 intr_handle->intr_vec =
4171                         rte_zmalloc("intr_vec",
4172                                     dev->data->nb_rx_queues * sizeof(int), 0);
4173                 if (intr_handle->intr_vec == NULL) {
4174                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4175                                      " intr_vec\n", dev->data->nb_rx_queues);
4176                         return -ENOMEM;
4177                 }
4178         }
4179         ixgbevf_configure_msix(dev);
4180
4181         rte_intr_enable(intr_handle);
4182
4183         /* Re-enable interrupt for VF */
4184         ixgbevf_intr_enable(hw);
4185
4186         return 0;
4187 }
4188
4189 static void
4190 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4191 {
4192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4193         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4194
4195         PMD_INIT_FUNC_TRACE();
4196
4197         ixgbevf_intr_disable(hw);
4198
4199         hw->adapter_stopped = 1;
4200         ixgbe_stop_adapter(hw);
4201
4202         /*
4203           * Clear what we set, but we still keep shadow_vfta to
4204           * restore after device starts
4205           */
4206         ixgbevf_set_vfta_all(dev, 0);
4207
4208         /* Clear stored conf */
4209         dev->data->scattered_rx = 0;
4210
4211         ixgbe_dev_clear_queues(dev);
4212
4213         /* Clean datapath event and queue/vec mapping */
4214         rte_intr_efd_disable(intr_handle);
4215         if (intr_handle->intr_vec != NULL) {
4216                 rte_free(intr_handle->intr_vec);
4217                 intr_handle->intr_vec = NULL;
4218         }
4219 }
4220
4221 static void
4222 ixgbevf_dev_close(struct rte_eth_dev *dev)
4223 {
4224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225
4226         PMD_INIT_FUNC_TRACE();
4227
4228         ixgbe_reset_hw(hw);
4229
4230         ixgbevf_dev_stop(dev);
4231
4232         ixgbe_dev_free_queues(dev);
4233
4234         /**
4235          * Remove the VF MAC address ro ensure
4236          * that the VF traffic goes to the PF
4237          * after stop, close and detach of the VF
4238          **/
4239         ixgbevf_remove_mac_addr(dev, 0);
4240 }
4241
4242 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4243 {
4244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4245         struct ixgbe_vfta *shadow_vfta =
4246                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4247         int i = 0, j = 0, vfta = 0, mask = 1;
4248
4249         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4250                 vfta = shadow_vfta->vfta[i];
4251                 if (vfta) {
4252                         mask = 1;
4253                         for (j = 0; j < 32; j++) {
4254                                 if (vfta & mask)
4255                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4256                                                        on, false);
4257                                 mask <<= 1;
4258                         }
4259                 }
4260         }
4261
4262 }
4263
4264 static int
4265 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4266 {
4267         struct ixgbe_hw *hw =
4268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269         struct ixgbe_vfta *shadow_vfta =
4270                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4271         uint32_t vid_idx = 0;
4272         uint32_t vid_bit = 0;
4273         int ret = 0;
4274
4275         PMD_INIT_FUNC_TRACE();
4276
4277         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4278         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4279         if (ret) {
4280                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4281                 return ret;
4282         }
4283         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4284         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4285
4286         /* Save what we set and retore it after device reset */
4287         if (on)
4288                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4289         else
4290                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4291
4292         return 0;
4293 }
4294
4295 static void
4296 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4297 {
4298         struct ixgbe_hw *hw =
4299                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4300         uint32_t ctrl;
4301
4302         PMD_INIT_FUNC_TRACE();
4303
4304         if (queue >= hw->mac.max_rx_queues)
4305                 return;
4306
4307         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4308         if (on)
4309                 ctrl |= IXGBE_RXDCTL_VME;
4310         else
4311                 ctrl &= ~IXGBE_RXDCTL_VME;
4312         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4313
4314         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4315 }
4316
4317 static void
4318 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4319 {
4320         struct ixgbe_hw *hw =
4321                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322         uint16_t i;
4323         int on = 0;
4324
4325         /* VF function only support hw strip feature, others are not support */
4326         if (mask & ETH_VLAN_STRIP_MASK) {
4327                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4328
4329                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4330                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4331         }
4332 }
4333
4334 static int
4335 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4336 {
4337         uint32_t reg_val;
4338
4339         /* we only need to do this if VMDq is enabled */
4340         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4341         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4342                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4343                 return -1;
4344         }
4345
4346         return 0;
4347 }
4348
4349 static uint32_t
4350 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4351 {
4352         uint32_t vector = 0;
4353
4354         switch (hw->mac.mc_filter_type) {
4355         case 0:   /* use bits [47:36] of the address */
4356                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4357                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4358                 break;
4359         case 1:   /* use bits [46:35] of the address */
4360                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4361                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4362                 break;
4363         case 2:   /* use bits [45:34] of the address */
4364                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4365                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4366                 break;
4367         case 3:   /* use bits [43:32] of the address */
4368                 vector = ((uc_addr->addr_bytes[4]) |
4369                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4370                 break;
4371         default:  /* Invalid mc_filter_type */
4372                 break;
4373         }
4374
4375         /* vector can only be 12-bits or boundary will be exceeded */
4376         vector &= 0xFFF;
4377         return vector;
4378 }
4379
4380 static int
4381 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4382                         uint8_t on)
4383 {
4384         uint32_t vector;
4385         uint32_t uta_idx;
4386         uint32_t reg_val;
4387         uint32_t uta_shift;
4388         uint32_t rc;
4389         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4390         const uint32_t ixgbe_uta_bit_shift = 5;
4391         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4392         const uint32_t bit1 = 0x1;
4393
4394         struct ixgbe_hw *hw =
4395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396         struct ixgbe_uta_info *uta_info =
4397                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4398
4399         /* The UTA table only exists on 82599 hardware and newer */
4400         if (hw->mac.type < ixgbe_mac_82599EB)
4401                 return -ENOTSUP;
4402
4403         vector = ixgbe_uta_vector(hw, mac_addr);
4404         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4405         uta_shift = vector & ixgbe_uta_bit_mask;
4406
4407         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4408         if (rc == on)
4409                 return 0;
4410
4411         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4412         if (on) {
4413                 uta_info->uta_in_use++;
4414                 reg_val |= (bit1 << uta_shift);
4415                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4416         } else {
4417                 uta_info->uta_in_use--;
4418                 reg_val &= ~(bit1 << uta_shift);
4419                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4420         }
4421
4422         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4423
4424         if (uta_info->uta_in_use > 0)
4425                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4426                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4427         else
4428                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4429
4430         return 0;
4431 }
4432
4433 static int
4434 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4435 {
4436         int i;
4437         struct ixgbe_hw *hw =
4438                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439         struct ixgbe_uta_info *uta_info =
4440                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4441
4442         /* The UTA table only exists on 82599 hardware and newer */
4443         if (hw->mac.type < ixgbe_mac_82599EB)
4444                 return -ENOTSUP;
4445
4446         if (on) {
4447                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4448                         uta_info->uta_shadow[i] = ~0;
4449                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4450                 }
4451         } else {
4452                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4453                         uta_info->uta_shadow[i] = 0;
4454                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4455                 }
4456         }
4457         return 0;
4458
4459 }
4460
4461 uint32_t
4462 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4463 {
4464         uint32_t new_val = orig_val;
4465
4466         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4467                 new_val |= IXGBE_VMOLR_AUPE;
4468         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4469                 new_val |= IXGBE_VMOLR_ROMPE;
4470         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4471                 new_val |= IXGBE_VMOLR_ROPE;
4472         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4473                 new_val |= IXGBE_VMOLR_BAM;
4474         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4475                 new_val |= IXGBE_VMOLR_MPE;
4476
4477         return new_val;
4478 }
4479
4480 static int
4481 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4482                                uint16_t rx_mask, uint8_t on)
4483 {
4484         int val = 0;
4485
4486         struct ixgbe_hw *hw =
4487                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4489
4490         if (hw->mac.type == ixgbe_mac_82598EB) {
4491                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4492                              " on 82599 hardware and newer");
4493                 return -ENOTSUP;
4494         }
4495         if (ixgbe_vmdq_mode_check(hw) < 0)
4496                 return -ENOTSUP;
4497
4498         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4499
4500         if (on)
4501                 vmolr |= val;
4502         else
4503                 vmolr &= ~val;
4504
4505         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4506
4507         return 0;
4508 }
4509
4510 static int
4511 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4512 {
4513         uint32_t reg, addr;
4514         uint32_t val;
4515         const uint8_t bit1 = 0x1;
4516
4517         struct ixgbe_hw *hw =
4518                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519
4520         if (ixgbe_vmdq_mode_check(hw) < 0)
4521                 return -ENOTSUP;
4522
4523         if (pool >= ETH_64_POOLS)
4524                 return -EINVAL;
4525
4526         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4527         if (pool >= 32) {
4528                 addr = IXGBE_VFRE(1);
4529                 val = bit1 << (pool - 32);
4530         } else {
4531                 addr = IXGBE_VFRE(0);
4532                 val = bit1 << pool;
4533         }
4534
4535         reg = IXGBE_READ_REG(hw, addr);
4536
4537         if (on)
4538                 reg |= val;
4539         else
4540                 reg &= ~val;
4541
4542         IXGBE_WRITE_REG(hw, addr, reg);
4543
4544         return 0;
4545 }
4546
4547 static int
4548 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4549 {
4550         uint32_t reg, addr;
4551         uint32_t val;
4552         const uint8_t bit1 = 0x1;
4553
4554         struct ixgbe_hw *hw =
4555                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4556
4557         if (ixgbe_vmdq_mode_check(hw) < 0)
4558                 return -ENOTSUP;
4559
4560         if (pool >= ETH_64_POOLS)
4561                 return -EINVAL;
4562
4563         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4564         if (pool >= 32) {
4565                 addr = IXGBE_VFTE(1);
4566                 val = bit1 << (pool - 32);
4567         } else {
4568                 addr = IXGBE_VFTE(0);
4569                 val = bit1 << pool;
4570         }
4571
4572         reg = IXGBE_READ_REG(hw, addr);
4573
4574         if (on)
4575                 reg |= val;
4576         else
4577                 reg &= ~val;
4578
4579         IXGBE_WRITE_REG(hw, addr, reg);
4580
4581         return 0;
4582 }
4583
4584 static int
4585 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4586                         uint64_t pool_mask, uint8_t vlan_on)
4587 {
4588         int ret = 0;
4589         uint16_t pool_idx;
4590         struct ixgbe_hw *hw =
4591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592
4593         if (ixgbe_vmdq_mode_check(hw) < 0)
4594                 return -ENOTSUP;
4595         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4596                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4597                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4598                                                    vlan_on, false);
4599                         if (ret < 0)
4600                                 return ret;
4601                 }
4602         }
4603
4604         return ret;
4605 }
4606
4607 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4608 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4609 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4610 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4611 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4612         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4613         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4614
4615 static int
4616 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4617                         struct rte_eth_mirror_conf *mirror_conf,
4618                         uint8_t rule_id, uint8_t on)
4619 {
4620         uint32_t mr_ctl, vlvf;
4621         uint32_t mp_lsb = 0;
4622         uint32_t mv_msb = 0;
4623         uint32_t mv_lsb = 0;
4624         uint32_t mp_msb = 0;
4625         uint8_t i = 0;
4626         int reg_index = 0;
4627         uint64_t vlan_mask = 0;
4628
4629         const uint8_t pool_mask_offset = 32;
4630         const uint8_t vlan_mask_offset = 32;
4631         const uint8_t dst_pool_offset = 8;
4632         const uint8_t rule_mr_offset  = 4;
4633         const uint8_t mirror_rule_mask = 0x0F;
4634
4635         struct ixgbe_mirror_info *mr_info =
4636                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4637         struct ixgbe_hw *hw =
4638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639         uint8_t mirror_type = 0;
4640
4641         if (ixgbe_vmdq_mode_check(hw) < 0)
4642                 return -ENOTSUP;
4643
4644         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4645                 return -EINVAL;
4646
4647         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4648                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4649                         mirror_conf->rule_type);
4650                 return -EINVAL;
4651         }
4652
4653         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4654                 mirror_type |= IXGBE_MRCTL_VLME;
4655                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4656                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4657                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4658                                 /* search vlan id related pool vlan filter index */
4659                                 reg_index = ixgbe_find_vlvf_slot(hw,
4660                                                  mirror_conf->vlan.vlan_id[i],
4661                                                  false);
4662                                 if (reg_index < 0)
4663                                         return -EINVAL;
4664                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4665                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4666                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4667                                       mirror_conf->vlan.vlan_id[i]))
4668                                         vlan_mask |= (1ULL << reg_index);
4669                                 else
4670                                         return -EINVAL;
4671                         }
4672                 }
4673
4674                 if (on) {
4675                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4676                         mv_msb = vlan_mask >> vlan_mask_offset;
4677
4678                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4679                                                 mirror_conf->vlan.vlan_mask;
4680                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4681                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4682                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4683                                                 mirror_conf->vlan.vlan_id[i];
4684                         }
4685                 } else {
4686                         mv_lsb = 0;
4687                         mv_msb = 0;
4688                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4689                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4690                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4691                 }
4692         }
4693
4694         /*
4695          * if enable pool mirror, write related pool mask register,if disable
4696          * pool mirror, clear PFMRVM register
4697          */
4698         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4699                 mirror_type |= IXGBE_MRCTL_VPME;
4700                 if (on) {
4701                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4702                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4703                         mr_info->mr_conf[rule_id].pool_mask =
4704                                         mirror_conf->pool_mask;
4705
4706                 } else {
4707                         mp_lsb = 0;
4708                         mp_msb = 0;
4709                         mr_info->mr_conf[rule_id].pool_mask = 0;
4710                 }
4711         }
4712         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4713                 mirror_type |= IXGBE_MRCTL_UPME;
4714         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4715                 mirror_type |= IXGBE_MRCTL_DPME;
4716
4717         /* read  mirror control register and recalculate it */
4718         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4719
4720         if (on) {
4721                 mr_ctl |= mirror_type;
4722                 mr_ctl &= mirror_rule_mask;
4723                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4724         } else
4725                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4726
4727         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4728         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4729
4730         /* write mirrror control  register */
4731         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4732
4733         /* write pool mirrror control  register */
4734         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4735                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4736                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4737                                 mp_msb);
4738         }
4739         /* write VLAN mirrror control  register */
4740         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4741                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4742                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4743                                 mv_msb);
4744         }
4745
4746         return 0;
4747 }
4748
4749 static int
4750 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4751 {
4752         int mr_ctl = 0;
4753         uint32_t lsb_val = 0;
4754         uint32_t msb_val = 0;
4755         const uint8_t rule_mr_offset = 4;
4756
4757         struct ixgbe_hw *hw =
4758                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759         struct ixgbe_mirror_info *mr_info =
4760                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4761
4762         if (ixgbe_vmdq_mode_check(hw) < 0)
4763                 return -ENOTSUP;
4764
4765         memset(&mr_info->mr_conf[rule_id], 0,
4766                 sizeof(struct rte_eth_mirror_conf));
4767
4768         /* clear PFVMCTL register */
4769         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4770
4771         /* clear pool mask register */
4772         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4773         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4774
4775         /* clear vlan mask register */
4776         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4777         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4778
4779         return 0;
4780 }
4781
4782 static int
4783 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4784 {
4785         uint32_t mask;
4786         struct ixgbe_hw *hw =
4787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4788
4789         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4790         mask |= (1 << IXGBE_MISC_VEC_ID);
4791         RTE_SET_USED(queue_id);
4792         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4793
4794         rte_intr_enable(&dev->pci_dev->intr_handle);
4795
4796         return 0;
4797 }
4798
4799 static int
4800 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4801 {
4802         uint32_t mask;
4803         struct ixgbe_hw *hw =
4804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805
4806         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4807         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4808         RTE_SET_USED(queue_id);
4809         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4810
4811         return 0;
4812 }
4813
4814 static int
4815 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4816 {
4817         uint32_t mask;
4818         struct ixgbe_hw *hw =
4819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820         struct ixgbe_interrupt *intr =
4821                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4822
4823         if (queue_id < 16) {
4824                 ixgbe_disable_intr(hw);
4825                 intr->mask |= (1 << queue_id);
4826                 ixgbe_enable_intr(dev);
4827         } else if (queue_id < 32) {
4828                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4829                 mask &= (1 << queue_id);
4830                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4831         } else if (queue_id < 64) {
4832                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4833                 mask &= (1 << (queue_id - 32));
4834                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4835         }
4836         rte_intr_enable(&dev->pci_dev->intr_handle);
4837
4838         return 0;
4839 }
4840
4841 static int
4842 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4843 {
4844         uint32_t mask;
4845         struct ixgbe_hw *hw =
4846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847         struct ixgbe_interrupt *intr =
4848                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4849
4850         if (queue_id < 16) {
4851                 ixgbe_disable_intr(hw);
4852                 intr->mask &= ~(1 << queue_id);
4853                 ixgbe_enable_intr(dev);
4854         } else if (queue_id < 32) {
4855                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4856                 mask &= ~(1 << queue_id);
4857                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4858         } else if (queue_id < 64) {
4859                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4860                 mask &= ~(1 << (queue_id - 32));
4861                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4862         }
4863
4864         return 0;
4865 }
4866
4867 static void
4868 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4869                      uint8_t queue, uint8_t msix_vector)
4870 {
4871         uint32_t tmp, idx;
4872
4873         if (direction == -1) {
4874                 /* other causes */
4875                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4876                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4877                 tmp &= ~0xFF;
4878                 tmp |= msix_vector;
4879                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4880         } else {
4881                 /* rx or tx cause */
4882                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4883                 idx = ((16 * (queue & 1)) + (8 * direction));
4884                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4885                 tmp &= ~(0xFF << idx);
4886                 tmp |= (msix_vector << idx);
4887                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4888         }
4889 }
4890
4891 /**
4892  * set the IVAR registers, mapping interrupt causes to vectors
4893  * @param hw
4894  *  pointer to ixgbe_hw struct
4895  * @direction
4896  *  0 for Rx, 1 for Tx, -1 for other causes
4897  * @queue
4898  *  queue to map the corresponding interrupt to
4899  * @msix_vector
4900  *  the vector to map to the corresponding queue
4901  */
4902 static void
4903 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4904                    uint8_t queue, uint8_t msix_vector)
4905 {
4906         uint32_t tmp, idx;
4907
4908         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4909         if (hw->mac.type == ixgbe_mac_82598EB) {
4910                 if (direction == -1)
4911                         direction = 0;
4912                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4913                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4914                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4915                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4916                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4917         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4918                         (hw->mac.type == ixgbe_mac_X540)) {
4919                 if (direction == -1) {
4920                         /* other causes */
4921                         idx = ((queue & 1) * 8);
4922                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4923                         tmp &= ~(0xFF << idx);
4924                         tmp |= (msix_vector << idx);
4925                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4926                 } else {
4927                         /* rx or tx causes */
4928                         idx = ((16 * (queue & 1)) + (8 * direction));
4929                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4930                         tmp &= ~(0xFF << idx);
4931                         tmp |= (msix_vector << idx);
4932                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4933                 }
4934         }
4935 }
4936
4937 static void
4938 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4939 {
4940         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4941         struct ixgbe_hw *hw =
4942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         uint32_t q_idx;
4944         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4945
4946         /* Configure VF other cause ivar */
4947         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4948
4949         /* won't configure msix register if no mapping is done
4950          * between intr vector and event fd.
4951          */
4952         if (!rte_intr_dp_is_en(intr_handle))
4953                 return;
4954
4955         /* Configure all RX queues of VF */
4956         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4957                 /* Force all queue use vector 0,
4958                  * as IXGBE_VF_MAXMSIVECOTR = 1
4959                  */
4960                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4961                 intr_handle->intr_vec[q_idx] = vector_idx;
4962         }
4963 }
4964
4965 /**
4966  * Sets up the hardware to properly generate MSI-X interrupts
4967  * @hw
4968  *  board private structure
4969  */
4970 static void
4971 ixgbe_configure_msix(struct rte_eth_dev *dev)
4972 {
4973         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4974         struct ixgbe_hw *hw =
4975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4977         uint32_t vec = IXGBE_MISC_VEC_ID;
4978         uint32_t mask;
4979         uint32_t gpie;
4980
4981         /* won't configure msix register if no mapping is done
4982          * between intr vector and event fd
4983          */
4984         if (!rte_intr_dp_is_en(intr_handle))
4985                 return;
4986
4987         if (rte_intr_allow_others(intr_handle))
4988                 vec = base = IXGBE_RX_VEC_START;
4989
4990         /* setup GPIE for MSI-x mode */
4991         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4992         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4993                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4994         /* auto clearing and auto setting corresponding bits in EIMS
4995          * when MSI-X interrupt is triggered
4996          */
4997         if (hw->mac.type == ixgbe_mac_82598EB) {
4998                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4999         } else {
5000                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5001                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5002         }
5003         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5004
5005         /* Populate the IVAR table and set the ITR values to the
5006          * corresponding register.
5007          */
5008         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5009              queue_id++) {
5010                 /* by default, 1:1 mapping */
5011                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5012                 intr_handle->intr_vec[queue_id] = vec;
5013                 if (vec < base + intr_handle->nb_efd - 1)
5014                         vec++;
5015         }
5016
5017         switch (hw->mac.type) {
5018         case ixgbe_mac_82598EB:
5019                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5020                                    IXGBE_MISC_VEC_ID);
5021                 break;
5022         case ixgbe_mac_82599EB:
5023         case ixgbe_mac_X540:
5024                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5025                 break;
5026         default:
5027                 break;
5028         }
5029         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5030                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5031
5032         /* set up to autoclear timer, and the vectors */
5033         mask = IXGBE_EIMS_ENABLE_MASK;
5034         mask &= ~(IXGBE_EIMS_OTHER |
5035                   IXGBE_EIMS_MAILBOX |
5036                   IXGBE_EIMS_LSC);
5037
5038         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5039 }
5040
5041 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5042         uint16_t queue_idx, uint16_t tx_rate)
5043 {
5044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         uint32_t rf_dec, rf_int;
5046         uint32_t bcnrc_val;
5047         uint16_t link_speed = dev->data->dev_link.link_speed;
5048
5049         if (queue_idx >= hw->mac.max_tx_queues)
5050                 return -EINVAL;
5051
5052         if (tx_rate != 0) {
5053                 /* Calculate the rate factor values to set */
5054                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5055                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5056                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5057
5058                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5059                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5060                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5061                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5062         } else {
5063                 bcnrc_val = 0;
5064         }
5065
5066         /*
5067          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5068          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5069          * set as 0x4.
5070          */
5071         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5072                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5073                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5074                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5075                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5076         else
5077                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5078                         IXGBE_MMW_SIZE_DEFAULT);
5079
5080         /* Set RTTBCNRC of queue X */
5081         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5082         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5083         IXGBE_WRITE_FLUSH(hw);
5084
5085         return 0;
5086 }
5087
5088 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5089         uint16_t tx_rate, uint64_t q_msk)
5090 {
5091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         struct ixgbe_vf_info *vfinfo =
5093                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5094         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5095         uint32_t queue_stride =
5096                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5097         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5098         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5099         uint16_t total_rate = 0;
5100
5101         if (queue_end >= hw->mac.max_tx_queues)
5102                 return -EINVAL;
5103
5104         if (vfinfo != NULL) {
5105                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5106                         if (vf_idx == vf)
5107                                 continue;
5108                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5109                                 idx++)
5110                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5111                 }
5112         } else
5113                 return -EINVAL;
5114
5115         /* Store tx_rate for this vf. */
5116         for (idx = 0; idx < nb_q_per_pool; idx++) {
5117                 if (((uint64_t)0x1 << idx) & q_msk) {
5118                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5119                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5120                         total_rate += tx_rate;
5121                 }
5122         }
5123
5124         if (total_rate > dev->data->dev_link.link_speed) {
5125                 /*
5126                  * Reset stored TX rate of the VF if it causes exceed
5127                  * link speed.
5128                  */
5129                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5130                 return -EINVAL;
5131         }
5132
5133         /* Set RTTBCNRC of each queue/pool for vf X  */
5134         for (; queue_idx <= queue_end; queue_idx++) {
5135                 if (0x1 & q_msk)
5136                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5137                 q_msk = q_msk >> 1;
5138         }
5139
5140         return 0;
5141 }
5142
5143 static void
5144 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5145                      __attribute__((unused)) uint32_t index,
5146                      __attribute__((unused)) uint32_t pool)
5147 {
5148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149         int diag;
5150
5151         /*
5152          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5153          * operation. Trap this case to avoid exhausting the [very limited]
5154          * set of PF resources used to store VF MAC addresses.
5155          */
5156         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5157                 return;
5158         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5159         if (diag == 0)
5160                 return;
5161         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5162 }
5163
5164 static void
5165 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5166 {
5167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5169         struct ether_addr *mac_addr;
5170         uint32_t i;
5171         int diag;
5172
5173         /*
5174          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5175          * not support the deletion of a given MAC address.
5176          * Instead, it imposes to delete all MAC addresses, then to add again
5177          * all MAC addresses with the exception of the one to be deleted.
5178          */
5179         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5180
5181         /*
5182          * Add again all MAC addresses, with the exception of the deleted one
5183          * and of the permanent MAC address.
5184          */
5185         for (i = 0, mac_addr = dev->data->mac_addrs;
5186              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5187                 /* Skip the deleted MAC address */
5188                 if (i == index)
5189                         continue;
5190                 /* Skip NULL MAC addresses */
5191                 if (is_zero_ether_addr(mac_addr))
5192                         continue;
5193                 /* Skip the permanent MAC address */
5194                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5195                         continue;
5196                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5197                 if (diag != 0)
5198                         PMD_DRV_LOG(ERR,
5199                                     "Adding again MAC address "
5200                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5201                                     "diag=%d",
5202                                     mac_addr->addr_bytes[0],
5203                                     mac_addr->addr_bytes[1],
5204                                     mac_addr->addr_bytes[2],
5205                                     mac_addr->addr_bytes[3],
5206                                     mac_addr->addr_bytes[4],
5207                                     mac_addr->addr_bytes[5],
5208                                     diag);
5209         }
5210 }
5211
5212 static void
5213 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5214 {
5215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216
5217         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5218 }
5219
5220 #define MAC_TYPE_FILTER_SUP(type)    do {\
5221         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5222                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5223                 (type) != ixgbe_mac_X550EM_a)\
5224                 return -ENOTSUP;\
5225 } while (0)
5226
5227 static int
5228 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5229                         struct rte_eth_syn_filter *filter,
5230                         bool add)
5231 {
5232         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233         uint32_t synqf;
5234
5235         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5236                 return -EINVAL;
5237
5238         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5239
5240         if (add) {
5241                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5242                         return -EINVAL;
5243                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5244                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5245
5246                 if (filter->hig_pri)
5247                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5248                 else
5249                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5250         } else {
5251                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5252                         return -ENOENT;
5253                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5254         }
5255         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5256         IXGBE_WRITE_FLUSH(hw);
5257         return 0;
5258 }
5259
5260 static int
5261 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5262                         struct rte_eth_syn_filter *filter)
5263 {
5264         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5266
5267         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5268                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5269                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5270                 return 0;
5271         }
5272         return -ENOENT;
5273 }
5274
5275 static int
5276 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5277                         enum rte_filter_op filter_op,
5278                         void *arg)
5279 {
5280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5281         int ret;
5282
5283         MAC_TYPE_FILTER_SUP(hw->mac.type);
5284
5285         if (filter_op == RTE_ETH_FILTER_NOP)
5286                 return 0;
5287
5288         if (arg == NULL) {
5289                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5290                             filter_op);
5291                 return -EINVAL;
5292         }
5293
5294         switch (filter_op) {
5295         case RTE_ETH_FILTER_ADD:
5296                 ret = ixgbe_syn_filter_set(dev,
5297                                 (struct rte_eth_syn_filter *)arg,
5298                                 TRUE);
5299                 break;
5300         case RTE_ETH_FILTER_DELETE:
5301                 ret = ixgbe_syn_filter_set(dev,
5302                                 (struct rte_eth_syn_filter *)arg,
5303                                 FALSE);
5304                 break;
5305         case RTE_ETH_FILTER_GET:
5306                 ret = ixgbe_syn_filter_get(dev,
5307                                 (struct rte_eth_syn_filter *)arg);
5308                 break;
5309         default:
5310                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5311                 ret = -EINVAL;
5312                 break;
5313         }
5314
5315         return ret;
5316 }
5317
5318
5319 static inline enum ixgbe_5tuple_protocol
5320 convert_protocol_type(uint8_t protocol_value)
5321 {
5322         if (protocol_value == IPPROTO_TCP)
5323                 return IXGBE_FILTER_PROTOCOL_TCP;
5324         else if (protocol_value == IPPROTO_UDP)
5325                 return IXGBE_FILTER_PROTOCOL_UDP;
5326         else if (protocol_value == IPPROTO_SCTP)
5327                 return IXGBE_FILTER_PROTOCOL_SCTP;
5328         else
5329                 return IXGBE_FILTER_PROTOCOL_NONE;
5330 }
5331
5332 /*
5333  * add a 5tuple filter
5334  *
5335  * @param
5336  * dev: Pointer to struct rte_eth_dev.
5337  * index: the index the filter allocates.
5338  * filter: ponter to the filter that will be added.
5339  * rx_queue: the queue id the filter assigned to.
5340  *
5341  * @return
5342  *    - On success, zero.
5343  *    - On failure, a negative value.
5344  */
5345 static int
5346 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5347                         struct ixgbe_5tuple_filter *filter)
5348 {
5349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5350         struct ixgbe_filter_info *filter_info =
5351                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5352         int i, idx, shift;
5353         uint32_t ftqf, sdpqf;
5354         uint32_t l34timir = 0;
5355         uint8_t mask = 0xff;
5356
5357         /*
5358          * look for an unused 5tuple filter index,
5359          * and insert the filter to list.
5360          */
5361         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5362                 idx = i / (sizeof(uint32_t) * NBBY);
5363                 shift = i % (sizeof(uint32_t) * NBBY);
5364                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5365                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5366                         filter->index = i;
5367                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5368                                           filter,
5369                                           entries);
5370                         break;
5371                 }
5372         }
5373         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5374                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5375                 return -ENOSYS;
5376         }
5377
5378         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5379                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5380         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5381
5382         ftqf = (uint32_t)(filter->filter_info.proto &
5383                 IXGBE_FTQF_PROTOCOL_MASK);
5384         ftqf |= (uint32_t)((filter->filter_info.priority &
5385                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5386         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5387                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5388         if (filter->filter_info.dst_ip_mask == 0)
5389                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5390         if (filter->filter_info.src_port_mask == 0)
5391                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5392         if (filter->filter_info.dst_port_mask == 0)
5393                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5394         if (filter->filter_info.proto_mask == 0)
5395                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5396         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5397         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5398         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5399
5400         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5401         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5402         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5403         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5404
5405         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5406         l34timir |= (uint32_t)(filter->queue <<
5407                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5408         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5409         return 0;
5410 }
5411
5412 /*
5413  * remove a 5tuple filter
5414  *
5415  * @param
5416  * dev: Pointer to struct rte_eth_dev.
5417  * filter: the pointer of the filter will be removed.
5418  */
5419 static void
5420 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5421                         struct ixgbe_5tuple_filter *filter)
5422 {
5423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5424         struct ixgbe_filter_info *filter_info =
5425                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5426         uint16_t index = filter->index;
5427
5428         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5429                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5430         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5431         rte_free(filter);
5432
5433         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5434         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5435         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5436         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5437         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5438 }
5439
5440 static int
5441 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5442 {
5443         struct ixgbe_hw *hw;
5444         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5445
5446         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447
5448         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5449                 return -EINVAL;
5450
5451         /* refuse mtu that requires the support of scattered packets when this
5452          * feature has not been enabled before.
5453          */
5454         if (!dev->data->scattered_rx &&
5455             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5456              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5457                 return -EINVAL;
5458
5459         /*
5460          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5461          * request of the version 2.0 of the mailbox API.
5462          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5463          * of the mailbox API.
5464          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5465          * prior to 3.11.33 which contains the following change:
5466          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5467          */
5468         ixgbevf_rlpml_set_vf(hw, max_frame);
5469
5470         /* update max frame size */
5471         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5472         return 0;
5473 }
5474
5475 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5476         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5477                 return -ENOTSUP;\
5478 } while (0)
5479
5480 static inline struct ixgbe_5tuple_filter *
5481 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5482                         struct ixgbe_5tuple_filter_info *key)
5483 {
5484         struct ixgbe_5tuple_filter *it;
5485
5486         TAILQ_FOREACH(it, filter_list, entries) {
5487                 if (memcmp(key, &it->filter_info,
5488                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5489                         return it;
5490                 }
5491         }
5492         return NULL;
5493 }
5494
5495 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5496 static inline int
5497 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5498                         struct ixgbe_5tuple_filter_info *filter_info)
5499 {
5500         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5501                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5502                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5503                 return -EINVAL;
5504
5505         switch (filter->dst_ip_mask) {
5506         case UINT32_MAX:
5507                 filter_info->dst_ip_mask = 0;
5508                 filter_info->dst_ip = filter->dst_ip;
5509                 break;
5510         case 0:
5511                 filter_info->dst_ip_mask = 1;
5512                 break;
5513         default:
5514                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5515                 return -EINVAL;
5516         }
5517
5518         switch (filter->src_ip_mask) {
5519         case UINT32_MAX:
5520                 filter_info->src_ip_mask = 0;
5521                 filter_info->src_ip = filter->src_ip;
5522                 break;
5523         case 0:
5524                 filter_info->src_ip_mask = 1;
5525                 break;
5526         default:
5527                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5528                 return -EINVAL;
5529         }
5530
5531         switch (filter->dst_port_mask) {
5532         case UINT16_MAX:
5533                 filter_info->dst_port_mask = 0;
5534                 filter_info->dst_port = filter->dst_port;
5535                 break;
5536         case 0:
5537                 filter_info->dst_port_mask = 1;
5538                 break;
5539         default:
5540                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5541                 return -EINVAL;
5542         }
5543
5544         switch (filter->src_port_mask) {
5545         case UINT16_MAX:
5546                 filter_info->src_port_mask = 0;
5547                 filter_info->src_port = filter->src_port;
5548                 break;
5549         case 0:
5550                 filter_info->src_port_mask = 1;
5551                 break;
5552         default:
5553                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5554                 return -EINVAL;
5555         }
5556
5557         switch (filter->proto_mask) {
5558         case UINT8_MAX:
5559                 filter_info->proto_mask = 0;
5560                 filter_info->proto =
5561                         convert_protocol_type(filter->proto);
5562                 break;
5563         case 0:
5564                 filter_info->proto_mask = 1;
5565                 break;
5566         default:
5567                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5568                 return -EINVAL;
5569         }
5570
5571         filter_info->priority = (uint8_t)filter->priority;
5572         return 0;
5573 }
5574
5575 /*
5576  * add or delete a ntuple filter
5577  *
5578  * @param
5579  * dev: Pointer to struct rte_eth_dev.
5580  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5581  * add: if true, add filter, if false, remove filter
5582  *
5583  * @return
5584  *    - On success, zero.
5585  *    - On failure, a negative value.
5586  */
5587 static int
5588 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5589                         struct rte_eth_ntuple_filter *ntuple_filter,
5590                         bool add)
5591 {
5592         struct ixgbe_filter_info *filter_info =
5593                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5594         struct ixgbe_5tuple_filter_info filter_5tuple;
5595         struct ixgbe_5tuple_filter *filter;
5596         int ret;
5597
5598         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5599                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5600                 return -EINVAL;
5601         }
5602
5603         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5604         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5605         if (ret < 0)
5606                 return ret;
5607
5608         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5609                                          &filter_5tuple);
5610         if (filter != NULL && add) {
5611                 PMD_DRV_LOG(ERR, "filter exists.");
5612                 return -EEXIST;
5613         }
5614         if (filter == NULL && !add) {
5615                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5616                 return -ENOENT;
5617         }
5618
5619         if (add) {
5620                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5621                                 sizeof(struct ixgbe_5tuple_filter), 0);
5622                 if (filter == NULL)
5623                         return -ENOMEM;
5624                 (void)rte_memcpy(&filter->filter_info,
5625                                  &filter_5tuple,
5626                                  sizeof(struct ixgbe_5tuple_filter_info));
5627                 filter->queue = ntuple_filter->queue;
5628                 ret = ixgbe_add_5tuple_filter(dev, filter);
5629                 if (ret < 0) {
5630                         rte_free(filter);
5631                         return ret;
5632                 }
5633         } else
5634                 ixgbe_remove_5tuple_filter(dev, filter);
5635
5636         return 0;
5637 }
5638
5639 /*
5640  * get a ntuple filter
5641  *
5642  * @param
5643  * dev: Pointer to struct rte_eth_dev.
5644  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5645  *
5646  * @return
5647  *    - On success, zero.
5648  *    - On failure, a negative value.
5649  */
5650 static int
5651 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5652                         struct rte_eth_ntuple_filter *ntuple_filter)
5653 {
5654         struct ixgbe_filter_info *filter_info =
5655                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5656         struct ixgbe_5tuple_filter_info filter_5tuple;
5657         struct ixgbe_5tuple_filter *filter;
5658         int ret;
5659
5660         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5661                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5662                 return -EINVAL;
5663         }
5664
5665         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5666         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5667         if (ret < 0)
5668                 return ret;
5669
5670         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5671                                          &filter_5tuple);
5672         if (filter == NULL) {
5673                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5674                 return -ENOENT;
5675         }
5676         ntuple_filter->queue = filter->queue;
5677         return 0;
5678 }
5679
5680 /*
5681  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5682  * @dev: pointer to rte_eth_dev structure
5683  * @filter_op:operation will be taken.
5684  * @arg: a pointer to specific structure corresponding to the filter_op
5685  *
5686  * @return
5687  *    - On success, zero.
5688  *    - On failure, a negative value.
5689  */
5690 static int
5691 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5692                                 enum rte_filter_op filter_op,
5693                                 void *arg)
5694 {
5695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696         int ret;
5697
5698         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5699
5700         if (filter_op == RTE_ETH_FILTER_NOP)
5701                 return 0;
5702
5703         if (arg == NULL) {
5704                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5705                             filter_op);
5706                 return -EINVAL;
5707         }
5708
5709         switch (filter_op) {
5710         case RTE_ETH_FILTER_ADD:
5711                 ret = ixgbe_add_del_ntuple_filter(dev,
5712                         (struct rte_eth_ntuple_filter *)arg,
5713                         TRUE);
5714                 break;
5715         case RTE_ETH_FILTER_DELETE:
5716                 ret = ixgbe_add_del_ntuple_filter(dev,
5717                         (struct rte_eth_ntuple_filter *)arg,
5718                         FALSE);
5719                 break;
5720         case RTE_ETH_FILTER_GET:
5721                 ret = ixgbe_get_ntuple_filter(dev,
5722                         (struct rte_eth_ntuple_filter *)arg);
5723                 break;
5724         default:
5725                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5726                 ret = -EINVAL;
5727                 break;
5728         }
5729         return ret;
5730 }
5731
5732 static inline int
5733 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5734                         uint16_t ethertype)
5735 {
5736         int i;
5737
5738         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5739                 if (filter_info->ethertype_filters[i] == ethertype &&
5740                     (filter_info->ethertype_mask & (1 << i)))
5741                         return i;
5742         }
5743         return -1;
5744 }
5745
5746 static inline int
5747 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5748                         uint16_t ethertype)
5749 {
5750         int i;
5751
5752         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5753                 if (!(filter_info->ethertype_mask & (1 << i))) {
5754                         filter_info->ethertype_mask |= 1 << i;
5755                         filter_info->ethertype_filters[i] = ethertype;
5756                         return i;
5757                 }
5758         }
5759         return -1;
5760 }
5761
5762 static inline int
5763 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5764                         uint8_t idx)
5765 {
5766         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5767                 return -1;
5768         filter_info->ethertype_mask &= ~(1 << idx);
5769         filter_info->ethertype_filters[idx] = 0;
5770         return idx;
5771 }
5772
5773 static int
5774 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5775                         struct rte_eth_ethertype_filter *filter,
5776                         bool add)
5777 {
5778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         struct ixgbe_filter_info *filter_info =
5780                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5781         uint32_t etqf = 0;
5782         uint32_t etqs = 0;
5783         int ret;
5784
5785         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5786                 return -EINVAL;
5787
5788         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5789                 filter->ether_type == ETHER_TYPE_IPv6) {
5790                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5791                         " ethertype filter.", filter->ether_type);
5792                 return -EINVAL;
5793         }
5794
5795         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5796                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5797                 return -EINVAL;
5798         }
5799         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5800                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5801                 return -EINVAL;
5802         }
5803
5804         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5805         if (ret >= 0 && add) {
5806                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5807                             filter->ether_type);
5808                 return -EEXIST;
5809         }
5810         if (ret < 0 && !add) {
5811                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5812                             filter->ether_type);
5813                 return -ENOENT;
5814         }
5815
5816         if (add) {
5817                 ret = ixgbe_ethertype_filter_insert(filter_info,
5818                         filter->ether_type);
5819                 if (ret < 0) {
5820                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5821                         return -ENOSYS;
5822                 }
5823                 etqf = IXGBE_ETQF_FILTER_EN;
5824                 etqf |= (uint32_t)filter->ether_type;
5825                 etqs |= (uint32_t)((filter->queue <<
5826                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5827                                     IXGBE_ETQS_RX_QUEUE);
5828                 etqs |= IXGBE_ETQS_QUEUE_EN;
5829         } else {
5830                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5831                 if (ret < 0)
5832                         return -ENOSYS;
5833         }
5834         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5835         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5836         IXGBE_WRITE_FLUSH(hw);
5837
5838         return 0;
5839 }
5840
5841 static int
5842 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5843                         struct rte_eth_ethertype_filter *filter)
5844 {
5845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5846         struct ixgbe_filter_info *filter_info =
5847                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5848         uint32_t etqf, etqs;
5849         int ret;
5850
5851         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5852         if (ret < 0) {
5853                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5854                             filter->ether_type);
5855                 return -ENOENT;
5856         }
5857
5858         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5859         if (etqf & IXGBE_ETQF_FILTER_EN) {
5860                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5861                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5862                 filter->flags = 0;
5863                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5864                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5865                 return 0;
5866         }
5867         return -ENOENT;
5868 }
5869
5870 /*
5871  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5872  * @dev: pointer to rte_eth_dev structure
5873  * @filter_op:operation will be taken.
5874  * @arg: a pointer to specific structure corresponding to the filter_op
5875  */
5876 static int
5877 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5878                                 enum rte_filter_op filter_op,
5879                                 void *arg)
5880 {
5881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5882         int ret;
5883
5884         MAC_TYPE_FILTER_SUP(hw->mac.type);
5885
5886         if (filter_op == RTE_ETH_FILTER_NOP)
5887                 return 0;
5888
5889         if (arg == NULL) {
5890                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5891                             filter_op);
5892                 return -EINVAL;
5893         }
5894
5895         switch (filter_op) {
5896         case RTE_ETH_FILTER_ADD:
5897                 ret = ixgbe_add_del_ethertype_filter(dev,
5898                         (struct rte_eth_ethertype_filter *)arg,
5899                         TRUE);
5900                 break;
5901         case RTE_ETH_FILTER_DELETE:
5902                 ret = ixgbe_add_del_ethertype_filter(dev,
5903                         (struct rte_eth_ethertype_filter *)arg,
5904                         FALSE);
5905                 break;
5906         case RTE_ETH_FILTER_GET:
5907                 ret = ixgbe_get_ethertype_filter(dev,
5908                         (struct rte_eth_ethertype_filter *)arg);
5909                 break;
5910         default:
5911                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5912                 ret = -EINVAL;
5913                 break;
5914         }
5915         return ret;
5916 }
5917
5918 static int
5919 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5920                      enum rte_filter_type filter_type,
5921                      enum rte_filter_op filter_op,
5922                      void *arg)
5923 {
5924         int ret = -EINVAL;
5925
5926         switch (filter_type) {
5927         case RTE_ETH_FILTER_NTUPLE:
5928                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5929                 break;
5930         case RTE_ETH_FILTER_ETHERTYPE:
5931                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5932                 break;
5933         case RTE_ETH_FILTER_SYN:
5934                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5935                 break;
5936         case RTE_ETH_FILTER_FDIR:
5937                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5938                 break;
5939         case RTE_ETH_FILTER_L2_TUNNEL:
5940                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5941                 break;
5942         default:
5943                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5944                                                         filter_type);
5945                 break;
5946         }
5947
5948         return ret;
5949 }
5950
5951 static u8 *
5952 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5953                         u8 **mc_addr_ptr, u32 *vmdq)
5954 {
5955         u8 *mc_addr;
5956
5957         *vmdq = 0;
5958         mc_addr = *mc_addr_ptr;
5959         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5960         return mc_addr;
5961 }
5962
5963 static int
5964 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5965                           struct ether_addr *mc_addr_set,
5966                           uint32_t nb_mc_addr)
5967 {
5968         struct ixgbe_hw *hw;
5969         u8 *mc_addr_list;
5970
5971         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5972         mc_addr_list = (u8 *)mc_addr_set;
5973         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5974                                          ixgbe_dev_addr_list_itr, TRUE);
5975 }
5976
5977 static uint64_t
5978 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5979 {
5980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981         uint64_t systime_cycles;
5982
5983         switch (hw->mac.type) {
5984         case ixgbe_mac_X550:
5985         case ixgbe_mac_X550EM_x:
5986         case ixgbe_mac_X550EM_a:
5987                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5988                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5989                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5990                                 * NSEC_PER_SEC;
5991                 break;
5992         default:
5993                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5994                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5995                                 << 32;
5996         }
5997
5998         return systime_cycles;
5999 }
6000
6001 static uint64_t
6002 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6003 {
6004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         uint64_t rx_tstamp_cycles;
6006
6007         switch (hw->mac.type) {
6008         case ixgbe_mac_X550:
6009         case ixgbe_mac_X550EM_x:
6010         case ixgbe_mac_X550EM_a:
6011                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6012                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6013                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6014                                 * NSEC_PER_SEC;
6015                 break;
6016         default:
6017                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6018                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6019                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6020                                 << 32;
6021         }
6022
6023         return rx_tstamp_cycles;
6024 }
6025
6026 static uint64_t
6027 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6028 {
6029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         uint64_t tx_tstamp_cycles;
6031
6032         switch (hw->mac.type) {
6033         case ixgbe_mac_X550:
6034         case ixgbe_mac_X550EM_x:
6035         case ixgbe_mac_X550EM_a:
6036                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6037                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6038                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6039                                 * NSEC_PER_SEC;
6040                 break;
6041         default:
6042                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6043                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6044                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6045                                 << 32;
6046         }
6047
6048         return tx_tstamp_cycles;
6049 }
6050
6051 static void
6052 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6053 {
6054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055         struct ixgbe_adapter *adapter =
6056                 (struct ixgbe_adapter *)dev->data->dev_private;
6057         struct rte_eth_link link;
6058         uint32_t incval = 0;
6059         uint32_t shift = 0;
6060
6061         /* Get current link speed. */
6062         memset(&link, 0, sizeof(link));
6063         ixgbe_dev_link_update(dev, 1);
6064         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6065
6066         switch (link.link_speed) {
6067         case ETH_SPEED_NUM_100M:
6068                 incval = IXGBE_INCVAL_100;
6069                 shift = IXGBE_INCVAL_SHIFT_100;
6070                 break;
6071         case ETH_SPEED_NUM_1G:
6072                 incval = IXGBE_INCVAL_1GB;
6073                 shift = IXGBE_INCVAL_SHIFT_1GB;
6074                 break;
6075         case ETH_SPEED_NUM_10G:
6076         default:
6077                 incval = IXGBE_INCVAL_10GB;
6078                 shift = IXGBE_INCVAL_SHIFT_10GB;
6079                 break;
6080         }
6081
6082         switch (hw->mac.type) {
6083         case ixgbe_mac_X550:
6084         case ixgbe_mac_X550EM_x:
6085         case ixgbe_mac_X550EM_a:
6086                 /* Independent of link speed. */
6087                 incval = 1;
6088                 /* Cycles read will be interpreted as ns. */
6089                 shift = 0;
6090                 /* Fall-through */
6091         case ixgbe_mac_X540:
6092                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6093                 break;
6094         case ixgbe_mac_82599EB:
6095                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6096                 shift -= IXGBE_INCVAL_SHIFT_82599;
6097                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6098                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6099                 break;
6100         default:
6101                 /* Not supported. */
6102                 return;
6103         }
6104
6105         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6106         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6107         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6108
6109         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6110         adapter->systime_tc.cc_shift = shift;
6111         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6112
6113         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6114         adapter->rx_tstamp_tc.cc_shift = shift;
6115         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6116
6117         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6118         adapter->tx_tstamp_tc.cc_shift = shift;
6119         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6120 }
6121
6122 static int
6123 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6124 {
6125         struct ixgbe_adapter *adapter =
6126                         (struct ixgbe_adapter *)dev->data->dev_private;
6127
6128         adapter->systime_tc.nsec += delta;
6129         adapter->rx_tstamp_tc.nsec += delta;
6130         adapter->tx_tstamp_tc.nsec += delta;
6131
6132         return 0;
6133 }
6134
6135 static int
6136 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6137 {
6138         uint64_t ns;
6139         struct ixgbe_adapter *adapter =
6140                         (struct ixgbe_adapter *)dev->data->dev_private;
6141
6142         ns = rte_timespec_to_ns(ts);
6143         /* Set the timecounters to a new value. */
6144         adapter->systime_tc.nsec = ns;
6145         adapter->rx_tstamp_tc.nsec = ns;
6146         adapter->tx_tstamp_tc.nsec = ns;
6147
6148         return 0;
6149 }
6150
6151 static int
6152 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6153 {
6154         uint64_t ns, systime_cycles;
6155         struct ixgbe_adapter *adapter =
6156                         (struct ixgbe_adapter *)dev->data->dev_private;
6157
6158         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6159         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6160         *ts = rte_ns_to_timespec(ns);
6161
6162         return 0;
6163 }
6164
6165 static int
6166 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6167 {
6168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6169         uint32_t tsync_ctl;
6170         uint32_t tsauxc;
6171
6172         /* Stop the timesync system time. */
6173         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6174         /* Reset the timesync system time value. */
6175         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6176         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6177
6178         /* Enable system time for platforms where it isn't on by default. */
6179         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6180         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6181         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6182
6183         ixgbe_start_timecounters(dev);
6184
6185         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6186         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6187                         (ETHER_TYPE_1588 |
6188                          IXGBE_ETQF_FILTER_EN |
6189                          IXGBE_ETQF_1588));
6190
6191         /* Enable timestamping of received PTP packets. */
6192         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6193         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6194         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6195
6196         /* Enable timestamping of transmitted PTP packets. */
6197         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6198         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6199         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6200
6201         IXGBE_WRITE_FLUSH(hw);
6202
6203         return 0;
6204 }
6205
6206 static int
6207 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6208 {
6209         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6210         uint32_t tsync_ctl;
6211
6212         /* Disable timestamping of transmitted PTP packets. */
6213         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6214         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6215         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6216
6217         /* Disable timestamping of received PTP packets. */
6218         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6219         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6220         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6221
6222         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6223         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6224
6225         /* Stop incrementating the System Time registers. */
6226         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6227
6228         return 0;
6229 }
6230
6231 static int
6232 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6233                                  struct timespec *timestamp,
6234                                  uint32_t flags __rte_unused)
6235 {
6236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6237         struct ixgbe_adapter *adapter =
6238                 (struct ixgbe_adapter *)dev->data->dev_private;
6239         uint32_t tsync_rxctl;
6240         uint64_t rx_tstamp_cycles;
6241         uint64_t ns;
6242
6243         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6244         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6245                 return -EINVAL;
6246
6247         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6248         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6249         *timestamp = rte_ns_to_timespec(ns);
6250
6251         return  0;
6252 }
6253
6254 static int
6255 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6256                                  struct timespec *timestamp)
6257 {
6258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6259         struct ixgbe_adapter *adapter =
6260                 (struct ixgbe_adapter *)dev->data->dev_private;
6261         uint32_t tsync_txctl;
6262         uint64_t tx_tstamp_cycles;
6263         uint64_t ns;
6264
6265         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6266         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6267                 return -EINVAL;
6268
6269         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6270         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6271         *timestamp = rte_ns_to_timespec(ns);
6272
6273         return 0;
6274 }
6275
6276 static int
6277 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6278 {
6279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6280         int count = 0;
6281         int g_ind = 0;
6282         const struct reg_info *reg_group;
6283         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6284                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6285
6286         while ((reg_group = reg_set[g_ind++]))
6287                 count += ixgbe_regs_group_count(reg_group);
6288
6289         return count;
6290 }
6291
6292 static int
6293 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6294 {
6295         int count = 0;
6296         int g_ind = 0;
6297         const struct reg_info *reg_group;
6298
6299         while ((reg_group = ixgbevf_regs[g_ind++]))
6300                 count += ixgbe_regs_group_count(reg_group);
6301
6302         return count;
6303 }
6304
6305 static int
6306 ixgbe_get_regs(struct rte_eth_dev *dev,
6307               struct rte_dev_reg_info *regs)
6308 {
6309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6310         uint32_t *data = regs->data;
6311         int g_ind = 0;
6312         int count = 0;
6313         const struct reg_info *reg_group;
6314         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6315                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6316
6317         if (data == NULL) {
6318                 regs->length = ixgbe_get_reg_length(dev);
6319                 regs->width = sizeof(uint32_t);
6320                 return 0;
6321         }
6322
6323         /* Support only full register dump */
6324         if ((regs->length == 0) ||
6325             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6326                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6327                         hw->device_id;
6328                 while ((reg_group = reg_set[g_ind++]))
6329                         count += ixgbe_read_regs_group(dev, &data[count],
6330                                 reg_group);
6331                 return 0;
6332         }
6333
6334         return -ENOTSUP;
6335 }
6336
6337 static int
6338 ixgbevf_get_regs(struct rte_eth_dev *dev,
6339                 struct rte_dev_reg_info *regs)
6340 {
6341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6342         uint32_t *data = regs->data;
6343         int g_ind = 0;
6344         int count = 0;
6345         const struct reg_info *reg_group;
6346
6347         if (data == NULL) {
6348                 regs->length = ixgbevf_get_reg_length(dev);
6349                 regs->width = sizeof(uint32_t);
6350                 return 0;
6351         }
6352
6353         /* Support only full register dump */
6354         if ((regs->length == 0) ||
6355             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6356                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6357                         hw->device_id;
6358                 while ((reg_group = ixgbevf_regs[g_ind++]))
6359                         count += ixgbe_read_regs_group(dev, &data[count],
6360                                                       reg_group);
6361                 return 0;
6362         }
6363
6364         return -ENOTSUP;
6365 }
6366
6367 static int
6368 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6369 {
6370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6371
6372         /* Return unit is byte count */
6373         return hw->eeprom.word_size * 2;
6374 }
6375
6376 static int
6377 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6378                 struct rte_dev_eeprom_info *in_eeprom)
6379 {
6380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6381         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6382         uint16_t *data = in_eeprom->data;
6383         int first, length;
6384
6385         first = in_eeprom->offset >> 1;
6386         length = in_eeprom->length >> 1;
6387         if ((first > hw->eeprom.word_size) ||
6388             ((first + length) > hw->eeprom.word_size))
6389                 return -EINVAL;
6390
6391         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6392
6393         return eeprom->ops.read_buffer(hw, first, length, data);
6394 }
6395
6396 static int
6397 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6398                 struct rte_dev_eeprom_info *in_eeprom)
6399 {
6400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6401         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6402         uint16_t *data = in_eeprom->data;
6403         int first, length;
6404
6405         first = in_eeprom->offset >> 1;
6406         length = in_eeprom->length >> 1;
6407         if ((first > hw->eeprom.word_size) ||
6408             ((first + length) > hw->eeprom.word_size))
6409                 return -EINVAL;
6410
6411         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6412
6413         return eeprom->ops.write_buffer(hw,  first, length, data);
6414 }
6415
6416 uint16_t
6417 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6418         switch (mac_type) {
6419         case ixgbe_mac_X550:
6420         case ixgbe_mac_X550EM_x:
6421         case ixgbe_mac_X550EM_a:
6422                 return ETH_RSS_RETA_SIZE_512;
6423         case ixgbe_mac_X550_vf:
6424         case ixgbe_mac_X550EM_x_vf:
6425         case ixgbe_mac_X550EM_a_vf:
6426                 return ETH_RSS_RETA_SIZE_64;
6427         default:
6428                 return ETH_RSS_RETA_SIZE_128;
6429         }
6430 }
6431
6432 uint32_t
6433 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6434         switch (mac_type) {
6435         case ixgbe_mac_X550:
6436         case ixgbe_mac_X550EM_x:
6437         case ixgbe_mac_X550EM_a:
6438                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6439                         return IXGBE_RETA(reta_idx >> 2);
6440                 else
6441                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6442         case ixgbe_mac_X550_vf:
6443         case ixgbe_mac_X550EM_x_vf:
6444         case ixgbe_mac_X550EM_a_vf:
6445                 return IXGBE_VFRETA(reta_idx >> 2);
6446         default:
6447                 return IXGBE_RETA(reta_idx >> 2);
6448         }
6449 }
6450
6451 uint32_t
6452 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6453         switch (mac_type) {
6454         case ixgbe_mac_X550_vf:
6455         case ixgbe_mac_X550EM_x_vf:
6456         case ixgbe_mac_X550EM_a_vf:
6457                 return IXGBE_VFMRQC;
6458         default:
6459                 return IXGBE_MRQC;
6460         }
6461 }
6462
6463 uint32_t
6464 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6465         switch (mac_type) {
6466         case ixgbe_mac_X550_vf:
6467         case ixgbe_mac_X550EM_x_vf:
6468         case ixgbe_mac_X550EM_a_vf:
6469                 return IXGBE_VFRSSRK(i);
6470         default:
6471                 return IXGBE_RSSRK(i);
6472         }
6473 }
6474
6475 bool
6476 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6477         switch (mac_type) {
6478         case ixgbe_mac_82599_vf:
6479         case ixgbe_mac_X540_vf:
6480                 return 0;
6481         default:
6482                 return 1;
6483         }
6484 }
6485
6486 static int
6487 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6488                         struct rte_eth_dcb_info *dcb_info)
6489 {
6490         struct ixgbe_dcb_config *dcb_config =
6491                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6492         struct ixgbe_dcb_tc_config *tc;
6493         uint8_t i, j;
6494
6495         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6496                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6497         else
6498                 dcb_info->nb_tcs = 1;
6499
6500         if (dcb_config->vt_mode) { /* vt is enabled*/
6501                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6502                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6503                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6504                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6505                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6506                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6507                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6508                                                 i * dcb_info->nb_tcs + j;
6509                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6510                                 dcb_info->tc_queue.tc_txq[i][j].base =
6511                                                 i * dcb_info->nb_tcs + j;
6512                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6513                         }
6514                 }
6515         } else { /* vt is disabled*/
6516                 struct rte_eth_dcb_rx_conf *rx_conf =
6517                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6518                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6519                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6520                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6521                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6522                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6523                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6524                         }
6525                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6526                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6527                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6528                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6529                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6530                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6531                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6532                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6533                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6534                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6535                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6536                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6537                         }
6538                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6539                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6540                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6541                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6542                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6543                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6544                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6545                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6546                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6547                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6548                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6549                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6550                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6551                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6552                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6553                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6554                 }
6555         }
6556         for (i = 0; i < dcb_info->nb_tcs; i++) {
6557                 tc = &dcb_config->tc_config[i];
6558                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6559         }
6560         return 0;
6561 }
6562
6563 /* Update e-tag ether type */
6564 static int
6565 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6566                             uint16_t ether_type)
6567 {
6568         uint32_t etag_etype;
6569
6570         if (hw->mac.type != ixgbe_mac_X550 &&
6571             hw->mac.type != ixgbe_mac_X550EM_x &&
6572             hw->mac.type != ixgbe_mac_X550EM_a) {
6573                 return -ENOTSUP;
6574         }
6575
6576         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6577         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6578         etag_etype |= ether_type;
6579         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6580         IXGBE_WRITE_FLUSH(hw);
6581
6582         return 0;
6583 }
6584
6585 /* Config l2 tunnel ether type */
6586 static int
6587 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6588                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6589 {
6590         int ret = 0;
6591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592
6593         if (l2_tunnel == NULL)
6594                 return -EINVAL;
6595
6596         switch (l2_tunnel->l2_tunnel_type) {
6597         case RTE_L2_TUNNEL_TYPE_E_TAG:
6598                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6599                 break;
6600         default:
6601                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6602                 ret = -EINVAL;
6603                 break;
6604         }
6605
6606         return ret;
6607 }
6608
6609 /* Enable e-tag tunnel */
6610 static int
6611 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6612 {
6613         uint32_t etag_etype;
6614
6615         if (hw->mac.type != ixgbe_mac_X550 &&
6616             hw->mac.type != ixgbe_mac_X550EM_x &&
6617             hw->mac.type != ixgbe_mac_X550EM_a) {
6618                 return -ENOTSUP;
6619         }
6620
6621         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6622         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6623         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6624         IXGBE_WRITE_FLUSH(hw);
6625
6626         return 0;
6627 }
6628
6629 /* Enable l2 tunnel */
6630 static int
6631 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6632                            enum rte_eth_tunnel_type l2_tunnel_type)
6633 {
6634         int ret = 0;
6635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636
6637         switch (l2_tunnel_type) {
6638         case RTE_L2_TUNNEL_TYPE_E_TAG:
6639                 ret = ixgbe_e_tag_enable(hw);
6640                 break;
6641         default:
6642                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6643                 ret = -EINVAL;
6644                 break;
6645         }
6646
6647         return ret;
6648 }
6649
6650 /* Disable e-tag tunnel */
6651 static int
6652 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6653 {
6654         uint32_t etag_etype;
6655
6656         if (hw->mac.type != ixgbe_mac_X550 &&
6657             hw->mac.type != ixgbe_mac_X550EM_x &&
6658             hw->mac.type != ixgbe_mac_X550EM_a) {
6659                 return -ENOTSUP;
6660         }
6661
6662         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6663         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6664         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6665         IXGBE_WRITE_FLUSH(hw);
6666
6667         return 0;
6668 }
6669
6670 /* Disable l2 tunnel */
6671 static int
6672 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6673                             enum rte_eth_tunnel_type l2_tunnel_type)
6674 {
6675         int ret = 0;
6676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677
6678         switch (l2_tunnel_type) {
6679         case RTE_L2_TUNNEL_TYPE_E_TAG:
6680                 ret = ixgbe_e_tag_disable(hw);
6681                 break;
6682         default:
6683                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6684                 ret = -EINVAL;
6685                 break;
6686         }
6687
6688         return ret;
6689 }
6690
6691 static int
6692 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6693                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6694 {
6695         int ret = 0;
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         uint32_t i, rar_entries;
6698         uint32_t rar_low, rar_high;
6699
6700         if (hw->mac.type != ixgbe_mac_X550 &&
6701             hw->mac.type != ixgbe_mac_X550EM_x &&
6702             hw->mac.type != ixgbe_mac_X550EM_a) {
6703                 return -ENOTSUP;
6704         }
6705
6706         rar_entries = ixgbe_get_num_rx_addrs(hw);
6707
6708         for (i = 1; i < rar_entries; i++) {
6709                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6710                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6711                 if ((rar_high & IXGBE_RAH_AV) &&
6712                     (rar_high & IXGBE_RAH_ADTYPE) &&
6713                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6714                      l2_tunnel->tunnel_id)) {
6715                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6716                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6717
6718                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6719
6720                         return ret;
6721                 }
6722         }
6723
6724         return ret;
6725 }
6726
6727 static int
6728 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6729                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6730 {
6731         int ret = 0;
6732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733         uint32_t i, rar_entries;
6734         uint32_t rar_low, rar_high;
6735
6736         if (hw->mac.type != ixgbe_mac_X550 &&
6737             hw->mac.type != ixgbe_mac_X550EM_x &&
6738             hw->mac.type != ixgbe_mac_X550EM_a) {
6739                 return -ENOTSUP;
6740         }
6741
6742         /* One entry for one tunnel. Try to remove potential existing entry. */
6743         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6744
6745         rar_entries = ixgbe_get_num_rx_addrs(hw);
6746
6747         for (i = 1; i < rar_entries; i++) {
6748                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6749                 if (rar_high & IXGBE_RAH_AV) {
6750                         continue;
6751                 } else {
6752                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6753                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6754                         rar_low = l2_tunnel->tunnel_id;
6755
6756                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6757                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6758
6759                         return ret;
6760                 }
6761         }
6762
6763         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6764                      " Please remove a rule before adding a new one.");
6765         return -EINVAL;
6766 }
6767
6768 /* Add l2 tunnel filter */
6769 static int
6770 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6771                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6772 {
6773         int ret = 0;
6774
6775         switch (l2_tunnel->l2_tunnel_type) {
6776         case RTE_L2_TUNNEL_TYPE_E_TAG:
6777                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6778                 break;
6779         default:
6780                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6781                 ret = -EINVAL;
6782                 break;
6783         }
6784
6785         return ret;
6786 }
6787
6788 /* Delete l2 tunnel filter */
6789 static int
6790 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6791                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6792 {
6793         int ret = 0;
6794
6795         switch (l2_tunnel->l2_tunnel_type) {
6796         case RTE_L2_TUNNEL_TYPE_E_TAG:
6797                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6798                 break;
6799         default:
6800                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6801                 ret = -EINVAL;
6802                 break;
6803         }
6804
6805         return ret;
6806 }
6807
6808 /**
6809  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6810  * @dev: pointer to rte_eth_dev structure
6811  * @filter_op:operation will be taken.
6812  * @arg: a pointer to specific structure corresponding to the filter_op
6813  */
6814 static int
6815 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6816                                   enum rte_filter_op filter_op,
6817                                   void *arg)
6818 {
6819         int ret = 0;
6820
6821         if (filter_op == RTE_ETH_FILTER_NOP)
6822                 return 0;
6823
6824         if (arg == NULL) {
6825                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6826                             filter_op);
6827                 return -EINVAL;
6828         }
6829
6830         switch (filter_op) {
6831         case RTE_ETH_FILTER_ADD:
6832                 ret = ixgbe_dev_l2_tunnel_filter_add
6833                         (dev,
6834                          (struct rte_eth_l2_tunnel_conf *)arg);
6835                 break;
6836         case RTE_ETH_FILTER_DELETE:
6837                 ret = ixgbe_dev_l2_tunnel_filter_del
6838                         (dev,
6839                          (struct rte_eth_l2_tunnel_conf *)arg);
6840                 break;
6841         default:
6842                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6843                 ret = -EINVAL;
6844                 break;
6845         }
6846         return ret;
6847 }
6848
6849 static int
6850 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6851 {
6852         int ret = 0;
6853         uint32_t ctrl;
6854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6855
6856         if (hw->mac.type != ixgbe_mac_X550 &&
6857             hw->mac.type != ixgbe_mac_X550EM_x &&
6858             hw->mac.type != ixgbe_mac_X550EM_a) {
6859                 return -ENOTSUP;
6860         }
6861
6862         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6863         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6864         if (en)
6865                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6866         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6867
6868         return ret;
6869 }
6870
6871 /* Enable l2 tunnel forwarding */
6872 static int
6873 ixgbe_dev_l2_tunnel_forwarding_enable
6874         (struct rte_eth_dev *dev,
6875          enum rte_eth_tunnel_type l2_tunnel_type)
6876 {
6877         int ret = 0;
6878
6879         switch (l2_tunnel_type) {
6880         case RTE_L2_TUNNEL_TYPE_E_TAG:
6881                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6882                 break;
6883         default:
6884                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6885                 ret = -EINVAL;
6886                 break;
6887         }
6888
6889         return ret;
6890 }
6891
6892 /* Disable l2 tunnel forwarding */
6893 static int
6894 ixgbe_dev_l2_tunnel_forwarding_disable
6895         (struct rte_eth_dev *dev,
6896          enum rte_eth_tunnel_type l2_tunnel_type)
6897 {
6898         int ret = 0;
6899
6900         switch (l2_tunnel_type) {
6901         case RTE_L2_TUNNEL_TYPE_E_TAG:
6902                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6903                 break;
6904         default:
6905                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6906                 ret = -EINVAL;
6907                 break;
6908         }
6909
6910         return ret;
6911 }
6912
6913 static int
6914 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6915                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6916                              bool en)
6917 {
6918         int ret = 0;
6919         uint32_t vmtir, vmvir;
6920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6921
6922         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6923                 PMD_DRV_LOG(ERR,
6924                             "VF id %u should be less than %u",
6925                             l2_tunnel->vf_id,
6926                             dev->pci_dev->max_vfs);
6927                 return -EINVAL;
6928         }
6929
6930         if (hw->mac.type != ixgbe_mac_X550 &&
6931             hw->mac.type != ixgbe_mac_X550EM_x &&
6932             hw->mac.type != ixgbe_mac_X550EM_a) {
6933                 return -ENOTSUP;
6934         }
6935
6936         if (en)
6937                 vmtir = l2_tunnel->tunnel_id;
6938         else
6939                 vmtir = 0;
6940
6941         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6942
6943         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6944         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6945         if (en)
6946                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6947         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6948
6949         return ret;
6950 }
6951
6952 /* Enable l2 tunnel tag insertion */
6953 static int
6954 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6955                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6956 {
6957         int ret = 0;
6958
6959         switch (l2_tunnel->l2_tunnel_type) {
6960         case RTE_L2_TUNNEL_TYPE_E_TAG:
6961                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6962                 break;
6963         default:
6964                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6965                 ret = -EINVAL;
6966                 break;
6967         }
6968
6969         return ret;
6970 }
6971
6972 /* Disable l2 tunnel tag insertion */
6973 static int
6974 ixgbe_dev_l2_tunnel_insertion_disable
6975         (struct rte_eth_dev *dev,
6976          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6977 {
6978         int ret = 0;
6979
6980         switch (l2_tunnel->l2_tunnel_type) {
6981         case RTE_L2_TUNNEL_TYPE_E_TAG:
6982                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6983                 break;
6984         default:
6985                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6986                 ret = -EINVAL;
6987                 break;
6988         }
6989
6990         return ret;
6991 }
6992
6993 static int
6994 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6995                              bool en)
6996 {
6997         int ret = 0;
6998         uint32_t qde;
6999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7000
7001         if (hw->mac.type != ixgbe_mac_X550 &&
7002             hw->mac.type != ixgbe_mac_X550EM_x &&
7003             hw->mac.type != ixgbe_mac_X550EM_a) {
7004                 return -ENOTSUP;
7005         }
7006
7007         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7008         if (en)
7009                 qde |= IXGBE_QDE_STRIP_TAG;
7010         else
7011                 qde &= ~IXGBE_QDE_STRIP_TAG;
7012         qde &= ~IXGBE_QDE_READ;
7013         qde |= IXGBE_QDE_WRITE;
7014         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7015
7016         return ret;
7017 }
7018
7019 /* Enable l2 tunnel tag stripping */
7020 static int
7021 ixgbe_dev_l2_tunnel_stripping_enable
7022         (struct rte_eth_dev *dev,
7023          enum rte_eth_tunnel_type l2_tunnel_type)
7024 {
7025         int ret = 0;
7026
7027         switch (l2_tunnel_type) {
7028         case RTE_L2_TUNNEL_TYPE_E_TAG:
7029                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7030                 break;
7031         default:
7032                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7033                 ret = -EINVAL;
7034                 break;
7035         }
7036
7037         return ret;
7038 }
7039
7040 /* Disable l2 tunnel tag stripping */
7041 static int
7042 ixgbe_dev_l2_tunnel_stripping_disable
7043         (struct rte_eth_dev *dev,
7044          enum rte_eth_tunnel_type l2_tunnel_type)
7045 {
7046         int ret = 0;
7047
7048         switch (l2_tunnel_type) {
7049         case RTE_L2_TUNNEL_TYPE_E_TAG:
7050                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7051                 break;
7052         default:
7053                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7054                 ret = -EINVAL;
7055                 break;
7056         }
7057
7058         return ret;
7059 }
7060
7061 /* Enable/disable l2 tunnel offload functions */
7062 static int
7063 ixgbe_dev_l2_tunnel_offload_set
7064         (struct rte_eth_dev *dev,
7065          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7066          uint32_t mask,
7067          uint8_t en)
7068 {
7069         int ret = 0;
7070
7071         if (l2_tunnel == NULL)
7072                 return -EINVAL;
7073
7074         ret = -EINVAL;
7075         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7076                 if (en)
7077                         ret = ixgbe_dev_l2_tunnel_enable(
7078                                 dev,
7079                                 l2_tunnel->l2_tunnel_type);
7080                 else
7081                         ret = ixgbe_dev_l2_tunnel_disable(
7082                                 dev,
7083                                 l2_tunnel->l2_tunnel_type);
7084         }
7085
7086         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7087                 if (en)
7088                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7089                                 dev,
7090                                 l2_tunnel);
7091                 else
7092                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7093                                 dev,
7094                                 l2_tunnel);
7095         }
7096
7097         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7098                 if (en)
7099                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7100                                 dev,
7101                                 l2_tunnel->l2_tunnel_type);
7102                 else
7103                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7104                                 dev,
7105                                 l2_tunnel->l2_tunnel_type);
7106         }
7107
7108         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7109                 if (en)
7110                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7111                                 dev,
7112                                 l2_tunnel->l2_tunnel_type);
7113                 else
7114                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7115                                 dev,
7116                                 l2_tunnel->l2_tunnel_type);
7117         }
7118
7119         return ret;
7120 }
7121
7122 static int
7123 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7124                         uint16_t port)
7125 {
7126         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7127         IXGBE_WRITE_FLUSH(hw);
7128
7129         return 0;
7130 }
7131
7132 /* There's only one register for VxLAN UDP port.
7133  * So, we cannot add several ports. Will update it.
7134  */
7135 static int
7136 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7137                      uint16_t port)
7138 {
7139         if (port == 0) {
7140                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7141                 return -EINVAL;
7142         }
7143
7144         return ixgbe_update_vxlan_port(hw, port);
7145 }
7146
7147 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7148  * UDP port, it must have a value.
7149  * So, will reset it to the original value 0.
7150  */
7151 static int
7152 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7153                      uint16_t port)
7154 {
7155         uint16_t cur_port;
7156
7157         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7158
7159         if (cur_port != port) {
7160                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7161                 return -EINVAL;
7162         }
7163
7164         return ixgbe_update_vxlan_port(hw, 0);
7165 }
7166
7167 /* Add UDP tunneling port */
7168 static int
7169 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7170                               struct rte_eth_udp_tunnel *udp_tunnel)
7171 {
7172         int ret = 0;
7173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7174
7175         if (hw->mac.type != ixgbe_mac_X550 &&
7176             hw->mac.type != ixgbe_mac_X550EM_x &&
7177             hw->mac.type != ixgbe_mac_X550EM_a) {
7178                 return -ENOTSUP;
7179         }
7180
7181         if (udp_tunnel == NULL)
7182                 return -EINVAL;
7183
7184         switch (udp_tunnel->prot_type) {
7185         case RTE_TUNNEL_TYPE_VXLAN:
7186                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7187                 break;
7188
7189         case RTE_TUNNEL_TYPE_GENEVE:
7190         case RTE_TUNNEL_TYPE_TEREDO:
7191                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7192                 ret = -EINVAL;
7193                 break;
7194
7195         default:
7196                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7197                 ret = -EINVAL;
7198                 break;
7199         }
7200
7201         return ret;
7202 }
7203
7204 /* Remove UDP tunneling port */
7205 static int
7206 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7207                               struct rte_eth_udp_tunnel *udp_tunnel)
7208 {
7209         int ret = 0;
7210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7211
7212         if (hw->mac.type != ixgbe_mac_X550 &&
7213             hw->mac.type != ixgbe_mac_X550EM_x &&
7214             hw->mac.type != ixgbe_mac_X550EM_a) {
7215                 return -ENOTSUP;
7216         }
7217
7218         if (udp_tunnel == NULL)
7219                 return -EINVAL;
7220
7221         switch (udp_tunnel->prot_type) {
7222         case RTE_TUNNEL_TYPE_VXLAN:
7223                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7224                 break;
7225         case RTE_TUNNEL_TYPE_GENEVE:
7226         case RTE_TUNNEL_TYPE_TEREDO:
7227                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7228                 ret = -EINVAL;
7229                 break;
7230         default:
7231                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7232                 ret = -EINVAL;
7233                 break;
7234         }
7235
7236         return ret;
7237 }
7238
7239 /* ixgbevf_update_xcast_mode - Update Multicast mode
7240  * @hw: pointer to the HW structure
7241  * @netdev: pointer to net device structure
7242  * @xcast_mode: new multicast mode
7243  *
7244  * Updates the Multicast Mode of VF.
7245  */
7246 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7247                                      int xcast_mode)
7248 {
7249         struct ixgbe_mbx_info *mbx = &hw->mbx;
7250         u32 msgbuf[2];
7251         s32 err;
7252
7253         switch (hw->api_version) {
7254         case ixgbe_mbox_api_12:
7255                 break;
7256         default:
7257                 return -EOPNOTSUPP;
7258         }
7259
7260         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7261         msgbuf[1] = xcast_mode;
7262
7263         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7264         if (err)
7265                 return err;
7266
7267         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7268         if (err)
7269                 return err;
7270
7271         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7272         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7273                 return -EPERM;
7274
7275         return 0;
7276 }
7277
7278 static void
7279 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7280 {
7281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7282
7283         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7284 }
7285
7286 static void
7287 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7288 {
7289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7290
7291         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7292 }
7293
7294 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7295 {
7296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7297         u32 in_msg = 0;
7298
7299         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7300                 return;
7301
7302         /* PF reset VF event */
7303         if (in_msg == IXGBE_PF_CONTROL_MSG)
7304                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7305 }
7306
7307 static int
7308 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7309 {
7310         uint32_t eicr;
7311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7312         struct ixgbe_interrupt *intr =
7313                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7314         ixgbevf_intr_disable(hw);
7315
7316         /* read-on-clear nic registers here */
7317         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7318         intr->flags = 0;
7319
7320         /* only one misc vector supported - mailbox */
7321         eicr &= IXGBE_VTEICR_MASK;
7322         if (eicr == IXGBE_MISC_VEC_ID)
7323                 intr->flags |= IXGBE_FLAG_MAILBOX;
7324
7325         return 0;
7326 }
7327
7328 static int
7329 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7330 {
7331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7332         struct ixgbe_interrupt *intr =
7333                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7334
7335         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7336                 ixgbevf_mbx_process(dev);
7337                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7338         }
7339
7340         ixgbevf_intr_enable(hw);
7341
7342         return 0;
7343 }
7344
7345 static void
7346 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7347                               void *param)
7348 {
7349         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7350
7351         ixgbevf_dev_interrupt_get_status(dev);
7352         ixgbevf_dev_interrupt_action(dev);
7353 }
7354
7355 static struct rte_driver rte_ixgbe_driver = {
7356         .type = PMD_PDEV,
7357         .init = rte_ixgbe_pmd_init,
7358 };
7359
7360 static struct rte_driver rte_ixgbevf_driver = {
7361         .type = PMD_PDEV,
7362         .init = rte_ixgbevf_pmd_init,
7363 };
7364
7365 PMD_REGISTER_DRIVER(rte_ixgbe_driver, ixgbe);
7366 DRIVER_REGISTER_PCI_TABLE(ixgbe, pci_id_ixgbe_map);
7367 PMD_REGISTER_DRIVER(rte_ixgbevf_driver, ixgbevf);
7368 DRIVER_REGISTER_PCI_TABLE(ixgbevf, pci_id_ixgbevf_map);