drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_bus_pci.h>
  52 #include <rte_atomic.h>
  53 #include <rte_branch_prediction.h>
  54 #include <rte_memory.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64 #ifdef RTE_LIBRTE_SECURITY
  65 #include <rte_security_driver.h>
  66 #endif
  67
  68 #include "ixgbe_logs.h"
  69 #include "base/ixgbe_api.h"
  70 #include "base/ixgbe_vf.h"
  71 #include "base/ixgbe_common.h"
  72 #include "ixgbe_ethdev.h"
  73 #include "ixgbe_bypass.h"
  74 #include "ixgbe_rxtx.h"
  75 #include "base/ixgbe_type.h"
  76 #include "base/ixgbe_phy.h"
  77 #include "ixgbe_regs.h"
  78
  79 /*
  80  * High threshold controlling when to start sending XOFF frames. Must be at
  81  * least 8 bytes less than receive packet buffer size. This value is in units
  82  * of 1024 bytes.
  83  */
  84 #define IXGBE_FC_HI    0x80
  85
  86 /*
  87  * Low threshold controlling when to start sending XON frames. This value is
  88  * in units of 1024 bytes.
  89  */
  90 #define IXGBE_FC_LO    0x40
  91
  92 /* Default minimum inter-interrupt interval for EITR configuration */
  93 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  94
  95 /* Timer value included in XOFF frames. */
  96 #define IXGBE_FC_PAUSE 0x680
  97
  98 /*Default value of Max Rx Queue*/
  99 #define IXGBE_MAX_RX_QUEUE_NUM 128
 100
 101 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
 102 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
 103 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 104
 105 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 106 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 107 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 108
 109 /*
 110  *  Default values for RX/TX configuration
 111  */
 112 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_RX_PTHRESH      8
 114 #define IXGBE_DEFAULT_RX_HTHRESH      8
 115 #define IXGBE_DEFAULT_RX_WTHRESH      0
 116
 117 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 118 #define IXGBE_DEFAULT_TX_PTHRESH      32
 119 #define IXGBE_DEFAULT_TX_HTHRESH      0
 120 #define IXGBE_DEFAULT_TX_WTHRESH      0
 121 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 122
 123 /* Bit shift and mask */
 124 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 125 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 126 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 127 #define IXGBE_8_BIT_MASK   UINT8_MAX
 128
 129 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 130
 131 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 132
 133 #define IXGBE_HKEY_MAX_INDEX 10
 134
 135 /* Additional timesync values. */
 136 #define NSEC_PER_SEC             1000000000L
 137 #define IXGBE_INCVAL_10GB        0x66666666
 138 #define IXGBE_INCVAL_1GB         0x40000000
 139 #define IXGBE_INCVAL_100         0x50000000
 140 #define IXGBE_INCVAL_SHIFT_10GB  28
 141 #define IXGBE_INCVAL_SHIFT_1GB   24
 142 #define IXGBE_INCVAL_SHIFT_100   21
 143 #define IXGBE_INCVAL_SHIFT_82599 7
 144 #define IXGBE_INCPER_SHIFT_82599 24
 145
 146 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 147
 148 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 149 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 150 #define DEFAULT_ETAG_ETYPE                     0x893f
 151 #define IXGBE_ETAG_ETYPE                       0x00005084
 152 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 153 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 154 #define IXGBE_RAH_ADTYPE                       0x40000000
 155 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 156 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 157 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 158 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 159 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 160 #define IXGBE_VTEICR_MASK                      0x07
 161
 162 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 163 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 164
 165 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 166 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 168 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 172 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 173 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 176 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 183 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 184                                 int wait_to_complete);
 185 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_stats *stats);
 187 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 188                                 struct rte_eth_xstat *xstats, unsigned n);
 189 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 190                                   struct rte_eth_xstat *xstats, unsigned n);
 191 static int
 192 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 193                 uint64_t *values, unsigned int n);
 194 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 195 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 196 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         unsigned int size);
 199 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 200         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 201 static int ixgbe_dev_xstats_get_names_by_id(
 202         struct rte_eth_dev *dev,
 203         struct rte_eth_xstat_name *xstats_names,
 204         const uint64_t *ids,
 205         unsigned int limit);
 206 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 207                                              uint16_t queue_id,
 208                                              uint8_t stat_idx,
 209                                              uint8_t is_rx);
 210 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 211                                  size_t fw_size);
 212 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_dev_info *dev_info);
 214 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 215 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 216                                  struct rte_eth_dev_info *dev_info);
 217 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 218
 219 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 220                 uint16_t vlan_id, int on);
 221 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 222                                enum rte_vlan_type vlan_type,
 223                                uint16_t tpid_id);
 224 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 225                 uint16_t queue, bool on);
 226 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 227                 int on);
 228 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 229 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 230 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 231 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 232 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 233
 234 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 236 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_fc_conf *fc_conf);
 238 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 239                                struct rte_eth_fc_conf *fc_conf);
 240 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 241                 struct rte_eth_pfc_conf *pfc_conf);
 242 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 243                         struct rte_eth_rss_reta_entry64 *reta_conf,
 244                         uint16_t reta_size);
 245 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 246                         struct rte_eth_rss_reta_entry64 *reta_conf,
 247                         uint16_t reta_size);
 248 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 249 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 250 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 251 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 252 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 253 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 254                                       struct rte_intr_handle *handle);
 255 static void ixgbe_dev_interrupt_handler(void *param);
 256 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 257 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 258
 259 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 260                          uint32_t index, uint32_t pool);
 261 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 262 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 263                                            struct ether_addr *mac_addr);
 264 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 265 static bool is_device_supported(struct rte_eth_dev *dev,
 266                                 struct rte_pci_driver *drv);
 267
 268 /* For Virtual Function support */
 269 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 270 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 271 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 272 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 274                                    int wait_to_complete);
 275 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 277 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 278 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 279 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 280 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 281                 struct rte_eth_stats *stats);
 282 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 283 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 284                 uint16_t vlan_id, int on);
 285 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 286                 uint16_t queue, int on);
 287 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 288 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 289 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                             uint16_t queue_id);
 291 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                              uint16_t queue_id);
 293 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                  uint8_t queue, uint8_t msix_vector);
 295 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 296 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 297 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 298
 299 /* For Eth VMDQ APIs support */
 300 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 301                 ether_addr * mac_addr, uint8_t on);
 302 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 303 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 304                 struct rte_eth_mirror_conf *mirror_conf,
 305                 uint8_t rule_id, uint8_t on);
 306 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 307                 uint8_t rule_id);
 308 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 309                                           uint16_t queue_id);
 310 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 311                                            uint16_t queue_id);
 312 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 313                                uint8_t queue, uint8_t msix_vector);
 314 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 315
 316 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 317                                 struct ether_addr *mac_addr,
 318                                 uint32_t index, uint32_t pool);
 319 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 320 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 321                                              struct ether_addr *mac_addr);
 322 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 323                         struct rte_eth_syn_filter *filter);
 324 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 325                         enum rte_filter_op filter_op,
 326                         void *arg);
 327 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 328                         struct ixgbe_5tuple_filter *filter);
 329 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 330                         struct ixgbe_5tuple_filter *filter);
 331 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 332                                 enum rte_filter_op filter_op,
 333                                 void *arg);
 334 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 335                         struct rte_eth_ntuple_filter *filter);
 336 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 337                                 enum rte_filter_op filter_op,
 338                                 void *arg);
 339 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 340                         struct rte_eth_ethertype_filter *filter);
 341 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 342                      enum rte_filter_type filter_type,
 343                      enum rte_filter_op filter_op,
 344                      void *arg);
 345 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 346
 347 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 348                                       struct ether_addr *mc_addr_set,
 349                                       uint32_t nb_mc_addr);
 350 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 351                                    struct rte_eth_dcb_info *dcb_info);
 352
 353 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 355                             struct rte_dev_reg_info *regs);
 356 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 357 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 358                                 struct rte_dev_eeprom_info *eeprom);
 359 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 360                                 struct rte_dev_eeprom_info *eeprom);
 361
 362 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 363 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 364                                 struct rte_dev_reg_info *regs);
 365
 366 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 367 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 368 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp,
 370                                             uint32_t flags);
 371 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 372                                             struct timespec *timestamp);
 373 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 374 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 375                                    struct timespec *timestamp);
 376 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 377                                    const struct timespec *timestamp);
 378 static void ixgbevf_dev_interrupt_handler(void *param);
 379
 380 static int ixgbe_dev_l2_tunnel_eth_type_conf
 381         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 382 static int ixgbe_dev_l2_tunnel_offload_set
 383         (struct rte_eth_dev *dev,
 384          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 385          uint32_t mask,
 386          uint8_t en);
 387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 388                                              enum rte_filter_op filter_op,
 389                                              void *arg);
 390
 391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                          struct rte_eth_udp_tunnel *udp_tunnel);
 395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 396 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 397
 398 /*
 399  * Define VF Stats MACRO for Non "cleared on read" register
 400  */
 401 #define UPDATE_VF_STAT(reg, last, cur)                          \
 402 {                                                               \
 403         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 404         cur += (latest - last) & UINT_MAX;                      \
 405         last = latest;                                          \
 406 }
 407
 408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 409 {                                                                \
 410         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 411         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 412         u64 latest = ((new_msb << 32) | new_lsb);                \
 413         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 414         last = latest;                                           \
 415 }
 416
 417 #define IXGBE_SET_HWSTRIP(h, q) do {\
 418                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 419                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 420                 (h)->bitmap[idx] |= 1 << bit;\
 421         } while (0)
 422
 423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 424                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 425                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 426                 (h)->bitmap[idx] &= ~(1 << bit);\
 427         } while (0)
 428
 429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 430                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 431                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 432                 (r) = (h)->bitmap[idx] >> bit & 1;\
 433         } while (0)
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 487 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 489 #endif
 490         { .vendor_id = 0, /* sentinel */ },
 491 };
 492
 493 /*
 494  * The set of PCI devices this driver supports (for 82599 VF)
 495  */
 496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 507         { .vendor_id = 0, /* sentinel */ },
 508 };
 509
 510 static const struct rte_eth_desc_lim rx_desc_lim = {
 511         .nb_max = IXGBE_MAX_RING_DESC,
 512         .nb_min = IXGBE_MIN_RING_DESC,
 513         .nb_align = IXGBE_RXD_ALIGN,
 514 };
 515
 516 static const struct rte_eth_desc_lim tx_desc_lim = {
 517         .nb_max = IXGBE_MAX_RING_DESC,
 518         .nb_min = IXGBE_MIN_RING_DESC,
 519         .nb_align = IXGBE_TXD_ALIGN,
 520         .nb_seg_max = IXGBE_TX_MAX_SEG,
 521         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 522 };
 523
 524 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 525         .dev_configure        = ixgbe_dev_configure,
 526         .dev_start            = ixgbe_dev_start,
 527         .dev_stop             = ixgbe_dev_stop,
 528         .dev_set_link_up    = ixgbe_dev_set_link_up,
 529         .dev_set_link_down  = ixgbe_dev_set_link_down,
 530         .dev_close            = ixgbe_dev_close,
 531         .dev_reset            = ixgbe_dev_reset,
 532         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 533         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 534         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 535         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 536         .link_update          = ixgbe_dev_link_update,
 537         .stats_get            = ixgbe_dev_stats_get,
 538         .xstats_get           = ixgbe_dev_xstats_get,
 539         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 540         .stats_reset          = ixgbe_dev_stats_reset,
 541         .xstats_reset         = ixgbe_dev_xstats_reset,
 542         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 543         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .fw_version_get       = ixgbe_fw_version_get,
 546         .dev_infos_get        = ixgbe_dev_info_get,
 547         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 548         .mtu_set              = ixgbe_dev_mtu_set,
 549         .vlan_filter_set      = ixgbe_vlan_filter_set,
 550         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 551         .vlan_offload_set     = ixgbe_vlan_offload_set,
 552         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 553         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 554         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 555         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 556         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 557         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 558         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 559         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 560         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 561         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 562         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 563         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 564         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 565         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 566         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 567         .dev_led_on           = ixgbe_dev_led_on,
 568         .dev_led_off          = ixgbe_dev_led_off,
 569         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 570         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 571         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 572         .mac_addr_add         = ixgbe_add_rar,
 573         .mac_addr_remove      = ixgbe_remove_rar,
 574         .mac_addr_set         = ixgbe_set_default_mac_addr,
 575         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 576         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 577         .mirror_rule_set      = ixgbe_mirror_rule_set,
 578         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 583         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 584         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 585         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 586         .rxq_info_get         = ixgbe_rxq_info_get,
 587         .txq_info_get         = ixgbe_txq_info_get,
 588         .timesync_enable      = ixgbe_timesync_enable,
 589         .timesync_disable     = ixgbe_timesync_disable,
 590         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 591         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 592         .get_reg              = ixgbe_get_regs,
 593         .get_eeprom_length    = ixgbe_get_eeprom_length,
 594         .get_eeprom           = ixgbe_get_eeprom,
 595         .set_eeprom           = ixgbe_set_eeprom,
 596         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 597         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 598         .timesync_read_time   = ixgbe_timesync_read_time,
 599         .timesync_write_time  = ixgbe_timesync_write_time,
 600         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 601         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 602         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 603         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 604         .tm_ops_get           = ixgbe_tm_ops_get,
 605 };
 606
 607 /*
 608  * dev_ops for virtual function, bare necessities for basic vf
 609  * operation have been implemented
 610  */
 611 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 612         .dev_configure        = ixgbevf_dev_configure,
 613         .dev_start            = ixgbevf_dev_start,
 614         .dev_stop             = ixgbevf_dev_stop,
 615         .link_update          = ixgbevf_dev_link_update,
 616         .stats_get            = ixgbevf_dev_stats_get,
 617         .xstats_get           = ixgbevf_dev_xstats_get,
 618         .stats_reset          = ixgbevf_dev_stats_reset,
 619         .xstats_reset         = ixgbevf_dev_stats_reset,
 620         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 621         .dev_close            = ixgbevf_dev_close,
 622         .dev_reset            = ixgbevf_dev_reset,
 623         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 624         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 625         .dev_infos_get        = ixgbevf_dev_info_get,
 626         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 627         .mtu_set              = ixgbevf_dev_set_mtu,
 628         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 629         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 630         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 631         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 632         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 633         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 634         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 635         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 636         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 637         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 638         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 639         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 640         .mac_addr_add         = ixgbevf_add_mac_addr,
 641         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 642         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 643         .rxq_info_get         = ixgbe_rxq_info_get,
 644         .txq_info_get         = ixgbe_txq_info_get,
 645         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 646         .get_reg              = ixgbevf_get_regs,
 647         .reta_update          = ixgbe_dev_rss_reta_update,
 648         .reta_query           = ixgbe_dev_rss_reta_query,
 649         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 650         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 651 };
 652
 653 /* store statistics names and its offset in stats structure */
 654 struct rte_ixgbe_xstats_name_off {
 655         char name[RTE_ETH_XSTATS_NAME_SIZE];
 656         unsigned offset;
 657 };
 658
 659 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 660         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 661         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 662         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 663         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 664         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 665         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 666         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 667         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 668         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 669         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 670         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 671         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 672         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 673         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 674         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 675                 prc1023)},
 676         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1522)},
 678         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 679         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 680         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 681         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 682         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 683         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 684         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 685         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 686         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 687         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 688         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 689         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 690         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 691         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 692         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 693         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 694         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 695                 ptc1023)},
 696         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1522)},
 698         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 699         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 700         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 701         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 702
 703         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirustat_add)},
 705         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_remove)},
 707         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 708                 fdirfstat_fadd)},
 709         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fremove)},
 711         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirmatch)},
 713         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmiss)},
 715
 716         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 717         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 718         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 719                 fclast)},
 720         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 721         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 722         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 723         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 724         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 725                 fcoe_noddp)},
 726         {"rx_fcoe_no_direct_data_placement_ext_buff",
 727                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 728
 729         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxontxc)},
 731         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxonrxc)},
 733         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxofftxc)},
 735         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxoffrxc)},
 737         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 738 };
 739
 740 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 741                            sizeof(rte_ixgbe_stats_strings[0]))
 742
 743 /* MACsec statistics */
 744 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 745         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 746                 out_pkts_untagged)},
 747         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_encrypted)},
 749         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 750                 out_pkts_protected)},
 751         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 752                 out_octets_encrypted)},
 753         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 754                 out_octets_protected)},
 755         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_untagged)},
 757         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_badtag)},
 759         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_nosci)},
 761         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unknownsci)},
 763         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 764                 in_octets_decrypted)},
 765         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 766                 in_octets_validated)},
 767         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_unchecked)},
 769         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_delayed)},
 771         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_late)},
 773         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_ok)},
 775         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_invalid)},
 777         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_notvalid)},
 779         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_unusedsa)},
 781         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_notusingsa)},
 783 };
 784
 785 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 786                            sizeof(rte_ixgbe_macsec_strings[0]))
 787
 788 /* Per-queue statistics */
 789 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 790         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 791         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 792         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 793         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 794 };
 795
 796 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 797                            sizeof(rte_ixgbe_rxq_strings[0]))
 798 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 799
 800 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 801         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 802         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 803         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 804                 pxon2offc)},
 805 };
 806
 807 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 808                            sizeof(rte_ixgbe_txq_strings[0]))
 809 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 810
 811 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 812         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 813 };
 814
 815 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 816                 sizeof(rte_ixgbevf_stats_strings[0]))
 817
 818 /**
 819  * Atomically reads the link status information from global
 820  * structure rte_eth_dev.
 821  *
 822  * @param dev
 823  *   - Pointer to the structure rte_eth_dev to read from.
 824  *   - Pointer to the buffer to be saved with the link status.
 825  *
 826  * @return
 827  *   - On success, zero.
 828  *   - On failure, negative value.
 829  */
 830 static inline int
 831 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 832                                 struct rte_eth_link *link)
 833 {
 834         struct rte_eth_link *dst = link;
 835         struct rte_eth_link *src = &(dev->data->dev_link);
 836
 837         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 838                                         *(uint64_t *)src) == 0)
 839                 return -1;
 840
 841         return 0;
 842 }
 843
 844 /**
 845  * Atomically writes the link status information into global
 846  * structure rte_eth_dev.
 847  *
 848  * @param dev
 849  *   - Pointer to the structure rte_eth_dev to read from.
 850  *   - Pointer to the buffer to be saved with the link status.
 851  *
 852  * @return
 853  *   - On success, zero.
 854  *   - On failure, negative value.
 855  */
 856 static inline int
 857 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 858                                 struct rte_eth_link *link)
 859 {
 860         struct rte_eth_link *dst = &(dev->data->dev_link);
 861         struct rte_eth_link *src = link;
 862
 863         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 864                                         *(uint64_t *)src) == 0)
 865                 return -1;
 866
 867         return 0;
 868 }
 869
 870 /*
 871  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 872  */
 873 static inline int
 874 ixgbe_is_sfp(struct ixgbe_hw *hw)
 875 {
 876         switch (hw->phy.type) {
 877         case ixgbe_phy_sfp_avago:
 878         case ixgbe_phy_sfp_ftl:
 879         case ixgbe_phy_sfp_intel:
 880         case ixgbe_phy_sfp_unknown:
 881         case ixgbe_phy_sfp_passive_tyco:
 882         case ixgbe_phy_sfp_passive_unknown:
 883                 return 1;
 884         default:
 885                 return 0;
 886         }
 887 }
 888
 889 static inline int32_t
 890 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 891 {
 892         uint32_t ctrl_ext;
 893         int32_t status;
 894
 895         status = ixgbe_reset_hw(hw);
 896
 897         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 898         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 899         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 900         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 901         IXGBE_WRITE_FLUSH(hw);
 902
 903         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 904                 status = IXGBE_SUCCESS;
 905         return status;
 906 }
 907
 908 static inline void
 909 ixgbe_enable_intr(struct rte_eth_dev *dev)
 910 {
 911         struct ixgbe_interrupt *intr =
 912                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 913         struct ixgbe_hw *hw =
 914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 915
 916         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 917         IXGBE_WRITE_FLUSH(hw);
 918 }
 919
 920 /*
 921  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 922  */
 923 static void
 924 ixgbe_disable_intr(struct ixgbe_hw *hw)
 925 {
 926         PMD_INIT_FUNC_TRACE();
 927
 928         if (hw->mac.type == ixgbe_mac_82598EB) {
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 930         } else {
 931                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 932                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 933                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 934         }
 935         IXGBE_WRITE_FLUSH(hw);
 936 }
 937
 938 /*
 939  * This function resets queue statistics mapping registers.
 940  * From Niantic datasheet, Initialization of Statistics section:
 941  * "...if software requires the queue counters, the RQSMR and TQSM registers
 942  * must be re-programmed following a device reset.
 943  */
 944 static void
 945 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 946 {
 947         uint32_t i;
 948
 949         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 950                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 951                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 952         }
 953 }
 954
 955
 956 static int
 957 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 958                                   uint16_t queue_id,
 959                                   uint8_t stat_idx,
 960                                   uint8_t is_rx)
 961 {
 962 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 963 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 964 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 965
 966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 967         struct ixgbe_stat_mapping_registers *stat_mappings =
 968                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 969         uint32_t qsmr_mask = 0;
 970         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 971         uint32_t q_map;
 972         uint8_t n, offset;
 973
 974         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 975                 (hw->mac.type != ixgbe_mac_X540) &&
 976                 (hw->mac.type != ixgbe_mac_X550) &&
 977                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 978                 (hw->mac.type != ixgbe_mac_X550EM_a))
 979                 return -ENOSYS;
 980
 981         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 982                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 983                      queue_id, stat_idx);
 984
 985         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 986         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 987                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 988                 return -EIO;
 989         }
 990         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 991
 992         /* Now clear any previous stat_idx set */
 993         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 994         if (!is_rx)
 995                 stat_mappings->tqsm[n] &= ~clearing_mask;
 996         else
 997                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 998
 999         q_map = (uint32_t)stat_idx;
1000         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1001         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1002         if (!is_rx)
1003                 stat_mappings->tqsm[n] |= qsmr_mask;
1004         else
1005                 stat_mappings->rqsmr[n] |= qsmr_mask;
1006
1007         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1008                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1009                      queue_id, stat_idx);
1010         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1011                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1012
1013         /* Now write the mapping in the appropriate register */
1014         if (is_rx) {
1015                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1016                              stat_mappings->rqsmr[n], n);
1017                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1018         } else {
1019                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1020                              stat_mappings->tqsm[n], n);
1021                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1022         }
1023         return 0;
1024 }
1025
1026 static void
1027 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1028 {
1029         struct ixgbe_stat_mapping_registers *stat_mappings =
1030                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         int i;
1033
1034         /* write whatever was in stat mapping table to the NIC */
1035         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1036                 /* rx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1038
1039                 /* tx */
1040                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1041         }
1042 }
1043
1044 static void
1045 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1046 {
1047         uint8_t i;
1048         struct ixgbe_dcb_tc_config *tc;
1049         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1050
1051         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1052         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1053         for (i = 0; i < dcb_max_tc; i++) {
1054                 tc = &dcb_config->tc_config[i];
1055                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1059                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1060                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1061                 tc->pfc = ixgbe_dcb_pfc_disabled;
1062         }
1063
1064         /* Initialize default user to priority mapping, UPx->TC0 */
1065         tc = &dcb_config->tc_config[0];
1066         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1067         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1068         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1069                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1070                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1071         }
1072         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1073         dcb_config->pfc_mode_enable = false;
1074         dcb_config->vt_mode = true;
1075         dcb_config->round_robin_enable = false;
1076         /* support all DCB capabilities in 82599 */
1077         dcb_config->support.capabilities = 0xFF;
1078
1079         /*we only support 4 Tcs for X540, X550 */
1080         if (hw->mac.type == ixgbe_mac_X540 ||
1081                 hw->mac.type == ixgbe_mac_X550 ||
1082                 hw->mac.type == ixgbe_mac_X550EM_x ||
1083                 hw->mac.type == ixgbe_mac_X550EM_a) {
1084                 dcb_config->num_tcs.pg_tcs = 4;
1085                 dcb_config->num_tcs.pfc_tcs = 4;
1086         }
1087 }
1088
1089 /*
1090  * Ensure that all locks are released before first NVM or PHY access
1091  */
1092 static void
1093 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1094 {
1095         uint16_t mask;
1096
1097         /*
1098          * Phy lock should not fail in this early stage. If this is the case,
1099          * it is due to an improper exit of the application.
1100          * So force the release of the faulty lock. Release of common lock
1101          * is done automatically by swfw_sync function.
1102          */
1103         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1104         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1105                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1106         }
1107         ixgbe_release_swfw_semaphore(hw, mask);
1108
1109         /*
1110          * These ones are more tricky since they are common to all ports; but
1111          * swfw_sync retries last long enough (1s) to be almost sure that if
1112          * lock can not be taken it is due to an improper lock of the
1113          * semaphore.
1114          */
1115         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1116         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1117                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1118         }
1119         ixgbe_release_swfw_semaphore(hw, mask);
1120 }
1121
1122 /*
1123  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1124  * It returns 0 on success.
1125  */
1126 static int
1127 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1128 {
1129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1131         struct ixgbe_hw *hw =
1132                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1133         struct ixgbe_vfta *shadow_vfta =
1134                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1135         struct ixgbe_hwstrip *hwstrip =
1136                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1137         struct ixgbe_dcb_config *dcb_config =
1138                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1139         struct ixgbe_filter_info *filter_info =
1140                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1141         struct ixgbe_bw_conf *bw_conf =
1142                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1143         uint32_t ctrl_ext;
1144         uint16_t csum;
1145         int diag, i;
1146
1147         PMD_INIT_FUNC_TRACE();
1148
1149         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1150         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1151         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1152         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1153
1154         /*
1155          * For secondary processes, we don't initialise any further as primary
1156          * has already done this work. Only check we don't need a different
1157          * RX and TX function.
1158          */
1159         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1160                 struct ixgbe_tx_queue *txq;
1161                 /* TX queue function in primary, set by last queue initialized
1162                  * Tx queue may not initialized by primary process
1163                  */
1164                 if (eth_dev->data->tx_queues) {
1165                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1166                         ixgbe_set_tx_function(eth_dev, txq);
1167                 } else {
1168                         /* Use default TX function if we get here */
1169                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1170                                      "Using default TX function.");
1171                 }
1172
1173                 ixgbe_set_rx_function(eth_dev);
1174
1175                 return 0;
1176         }
1177
1178 #ifdef RTE_LIBRTE_SECURITY
1179         /* Initialize security_ctx only for primary process*/
1180         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1181         if (eth_dev->security_ctx == NULL)
1182                 return -ENOMEM;
1183 #endif
1184
1185         rte_eth_copy_pci_info(eth_dev, pci_dev);
1186
1187         /* Vendor and Device ID need to be set before init of shared code */
1188         hw->device_id = pci_dev->id.device_id;
1189         hw->vendor_id = pci_dev->id.vendor_id;
1190         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1191         hw->allow_unsupported_sfp = 1;
1192
1193         /* Initialize the shared code (base driver) */
1194 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1195         diag = ixgbe_bypass_init_shared_code(hw);
1196 #else
1197         diag = ixgbe_init_shared_code(hw);
1198 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1199
1200         if (diag != IXGBE_SUCCESS) {
1201                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1202                 return -EIO;
1203         }
1204
1205         /* pick up the PCI bus settings for reporting later */
1206         ixgbe_get_bus_info(hw);
1207
1208         /* Unlock any pending hardware semaphore */
1209         ixgbe_swfw_lock_reset(hw);
1210
1211         /* Initialize DCB configuration*/
1212         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1213         ixgbe_dcb_init(hw, dcb_config);
1214         /* Get Hardware Flow Control setting */
1215         hw->fc.requested_mode = ixgbe_fc_full;
1216         hw->fc.current_mode = ixgbe_fc_full;
1217         hw->fc.pause_time = IXGBE_FC_PAUSE;
1218         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1219                 hw->fc.low_water[i] = IXGBE_FC_LO;
1220                 hw->fc.high_water[i] = IXGBE_FC_HI;
1221         }
1222         hw->fc.send_xon = 1;
1223
1224         /* Make sure we have a good EEPROM before we read from it */
1225         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1226         if (diag != IXGBE_SUCCESS) {
1227                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1228                 return -EIO;
1229         }
1230
1231 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1232         diag = ixgbe_bypass_init_hw(hw);
1233 #else
1234         diag = ixgbe_init_hw(hw);
1235 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1236
1237         /*
1238          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1239          * is called too soon after the kernel driver unbinding/binding occurs.
1240          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1241          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1242          * also called. See ixgbe_identify_phy_82599(). The reason for the
1243          * failure is not known, and only occuts when virtualisation features
1244          * are disabled in the bios. A delay of 100ms  was found to be enough by
1245          * trial-and-error, and is doubled to be safe.
1246          */
1247         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1248                 rte_delay_ms(200);
1249                 diag = ixgbe_init_hw(hw);
1250         }
1251
1252         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1253                 diag = IXGBE_SUCCESS;
1254
1255         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1256                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1257                              "LOM.  Please be aware there may be issues associated "
1258                              "with your hardware.");
1259                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1260                              "please contact your Intel or hardware representative "
1261                              "who provided you with this hardware.");
1262         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1263                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1264         if (diag) {
1265                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1266                 return -EIO;
1267         }
1268
1269         /* Reset the hw statistics */
1270         ixgbe_dev_stats_reset(eth_dev);
1271
1272         /* disable interrupt */
1273         ixgbe_disable_intr(hw);
1274
1275         /* reset mappings for queue statistics hw counters*/
1276         ixgbe_reset_qstat_mappings(hw);
1277
1278         /* Allocate memory for storing MAC addresses */
1279         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1280                                                hw->mac.num_rar_entries, 0);
1281         if (eth_dev->data->mac_addrs == NULL) {
1282                 PMD_INIT_LOG(ERR,
1283                              "Failed to allocate %u bytes needed to store "
1284                              "MAC addresses",
1285                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1286                 return -ENOMEM;
1287         }
1288         /* Copy the permanent MAC address */
1289         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1290                         &eth_dev->data->mac_addrs[0]);
1291
1292         /* Allocate memory for storing hash filter MAC addresses */
1293         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1294                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1295         if (eth_dev->data->hash_mac_addrs == NULL) {
1296                 PMD_INIT_LOG(ERR,
1297                              "Failed to allocate %d bytes needed to store MAC addresses",
1298                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1299                 return -ENOMEM;
1300         }
1301
1302         /* initialize the vfta */
1303         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1304
1305         /* initialize the hw strip bitmap*/
1306         memset(hwstrip, 0, sizeof(*hwstrip));
1307
1308         /* initialize PF if max_vfs not zero */
1309         ixgbe_pf_host_init(eth_dev);
1310
1311         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1312         /* let hardware know driver is loaded */
1313         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1314         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1315         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1316         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1317         IXGBE_WRITE_FLUSH(hw);
1318
1319         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1320                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1321                              (int) hw->mac.type, (int) hw->phy.type,
1322                              (int) hw->phy.sfp_type);
1323         else
1324                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1325                              (int) hw->mac.type, (int) hw->phy.type);
1326
1327         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1328                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1329                      pci_dev->id.device_id);
1330
1331         rte_intr_callback_register(intr_handle,
1332                                    ixgbe_dev_interrupt_handler, eth_dev);
1333
1334         /* enable uio/vfio intr/eventfd mapping */
1335         rte_intr_enable(intr_handle);
1336
1337         /* enable support intr */
1338         ixgbe_enable_intr(eth_dev);
1339
1340         /* initialize filter info */
1341         memset(filter_info, 0,
1342                sizeof(struct ixgbe_filter_info));
1343
1344         /* initialize 5tuple filter list */
1345         TAILQ_INIT(&filter_info->fivetuple_list);
1346
1347         /* initialize flow director filter list & hash */
1348         ixgbe_fdir_filter_init(eth_dev);
1349
1350         /* initialize l2 tunnel filter list & hash */
1351         ixgbe_l2_tn_filter_init(eth_dev);
1352
1353         /* initialize flow filter lists */
1354         ixgbe_filterlist_init();
1355
1356         /* initialize bandwidth configuration info */
1357         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1358
1359         /* initialize Traffic Manager configuration */
1360         ixgbe_tm_conf_init(eth_dev);
1361
1362         return 0;
1363 }
1364
1365 static int
1366 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1370         struct ixgbe_hw *hw;
1371         int retries = 0;
1372         int ret;
1373
1374         PMD_INIT_FUNC_TRACE();
1375
1376         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1377                 return -EPERM;
1378
1379         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1380
1381         if (hw->adapter_stopped == 0)
1382                 ixgbe_dev_close(eth_dev);
1383
1384         eth_dev->dev_ops = NULL;
1385         eth_dev->rx_pkt_burst = NULL;
1386         eth_dev->tx_pkt_burst = NULL;
1387
1388         /* Unlock any pending hardware semaphore */
1389         ixgbe_swfw_lock_reset(hw);
1390
1391         /* disable uio intr before callback unregister */
1392         rte_intr_disable(intr_handle);
1393
1394         do {
1395                 ret = rte_intr_callback_unregister(intr_handle,
1396                                 ixgbe_dev_interrupt_handler, eth_dev);
1397                 if (ret >= 0) {
1398                         break;
1399                 } else if (ret != -EAGAIN) {
1400                         PMD_INIT_LOG(ERR,
1401                                 "intr callback unregister failed: %d",
1402                                 ret);
1403                         return ret;
1404                 }
1405                 rte_delay_ms(100);
1406         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1407
1408         /* uninitialize PF if max_vfs not zero */
1409         ixgbe_pf_host_uninit(eth_dev);
1410
1411         rte_free(eth_dev->data->mac_addrs);
1412         eth_dev->data->mac_addrs = NULL;
1413
1414         rte_free(eth_dev->data->hash_mac_addrs);
1415         eth_dev->data->hash_mac_addrs = NULL;
1416
1417         /* remove all the fdir filters & hash */
1418         ixgbe_fdir_filter_uninit(eth_dev);
1419
1420         /* remove all the L2 tunnel filters & hash */
1421         ixgbe_l2_tn_filter_uninit(eth_dev);
1422
1423         /* Remove all ntuple filters of the device */
1424         ixgbe_ntuple_filter_uninit(eth_dev);
1425
1426         /* clear all the filters list */
1427         ixgbe_filterlist_flush();
1428
1429         /* Remove all Traffic Manager configuration */
1430         ixgbe_tm_conf_uninit(eth_dev);
1431
1432 #ifdef RTE_LIBRTE_SECURITY
1433         rte_free(eth_dev->security_ctx);
1434 #endif
1435
1436         return 0;
1437 }
1438
1439 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1440 {
1441         struct ixgbe_filter_info *filter_info =
1442                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1443         struct ixgbe_5tuple_filter *p_5tuple;
1444
1445         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1446                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1447                              p_5tuple,
1448                              entries);
1449                 rte_free(p_5tuple);
1450         }
1451         memset(filter_info->fivetuple_mask, 0,
1452                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_hw_fdir_info *fdir_info =
1460                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1461         struct ixgbe_fdir_filter *fdir_filter;
1462
1463                 if (fdir_info->hash_map)
1464                 rte_free(fdir_info->hash_map);
1465         if (fdir_info->hash_handle)
1466                 rte_hash_free(fdir_info->hash_handle);
1467
1468         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1469                 TAILQ_REMOVE(&fdir_info->fdir_list,
1470                              fdir_filter,
1471                              entries);
1472                 rte_free(fdir_filter);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1479 {
1480         struct ixgbe_l2_tn_info *l2_tn_info =
1481                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1482         struct ixgbe_l2_tn_filter *l2_tn_filter;
1483
1484         if (l2_tn_info->hash_map)
1485                 rte_free(l2_tn_info->hash_map);
1486         if (l2_tn_info->hash_handle)
1487                 rte_hash_free(l2_tn_info->hash_handle);
1488
1489         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1490                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1491                              l2_tn_filter,
1492                              entries);
1493                 rte_free(l2_tn_filter);
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1500 {
1501         struct ixgbe_hw_fdir_info *fdir_info =
1502                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1503         char fdir_hash_name[RTE_HASH_NAMESIZE];
1504         struct rte_hash_parameters fdir_hash_params = {
1505                 .name = fdir_hash_name,
1506                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1507                 .key_len = sizeof(union ixgbe_atr_input),
1508                 .hash_func = rte_hash_crc,
1509                 .hash_func_init_val = 0,
1510                 .socket_id = rte_socket_id(),
1511         };
1512
1513         TAILQ_INIT(&fdir_info->fdir_list);
1514         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1515                  "fdir_%s", eth_dev->device->name);
1516         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1517         if (!fdir_info->hash_handle) {
1518                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1519                 return -EINVAL;
1520         }
1521         fdir_info->hash_map = rte_zmalloc("ixgbe",
1522                                           sizeof(struct ixgbe_fdir_filter *) *
1523                                           IXGBE_MAX_FDIR_FILTER_NUM,
1524                                           0);
1525         if (!fdir_info->hash_map) {
1526                 PMD_INIT_LOG(ERR,
1527                              "Failed to allocate memory for fdir hash map!");
1528                 return -ENOMEM;
1529         }
1530         fdir_info->mask_added = FALSE;
1531
1532         return 0;
1533 }
1534
1535 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1536 {
1537         struct ixgbe_l2_tn_info *l2_tn_info =
1538                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1539         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1540         struct rte_hash_parameters l2_tn_hash_params = {
1541                 .name = l2_tn_hash_name,
1542                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1543                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1544                 .hash_func = rte_hash_crc,
1545                 .hash_func_init_val = 0,
1546                 .socket_id = rte_socket_id(),
1547         };
1548
1549         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1550         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1551                  "l2_tn_%s", eth_dev->device->name);
1552         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1553         if (!l2_tn_info->hash_handle) {
1554                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1555                 return -EINVAL;
1556         }
1557         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1558                                    sizeof(struct ixgbe_l2_tn_filter *) *
1559                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1560                                    0);
1561         if (!l2_tn_info->hash_map) {
1562                 PMD_INIT_LOG(ERR,
1563                         "Failed to allocate memory for L2 TN hash map!");
1564                 return -ENOMEM;
1565         }
1566         l2_tn_info->e_tag_en = FALSE;
1567         l2_tn_info->e_tag_fwd_en = FALSE;
1568         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1569
1570         return 0;
1571 }
1572 /*
1573  * Negotiate mailbox API version with the PF.
1574  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1575  * Then we try to negotiate starting with the most recent one.
1576  * If all negotiation attempts fail, then we will proceed with
1577  * the default one (ixgbe_mbox_api_10).
1578  */
1579 static void
1580 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1581 {
1582         int32_t i;
1583
1584         /* start with highest supported, proceed down */
1585         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1586                 ixgbe_mbox_api_12,
1587                 ixgbe_mbox_api_11,
1588                 ixgbe_mbox_api_10,
1589         };
1590
1591         for (i = 0;
1592                         i != RTE_DIM(sup_ver) &&
1593                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1594                         i++)
1595                 ;
1596 }
1597
1598 static void
1599 generate_random_mac_addr(struct ether_addr *mac_addr)
1600 {
1601         uint64_t random;
1602
1603         /* Set Organizationally Unique Identifier (OUI) prefix. */
1604         mac_addr->addr_bytes[0] = 0x00;
1605         mac_addr->addr_bytes[1] = 0x09;
1606         mac_addr->addr_bytes[2] = 0xC0;
1607         /* Force indication of locally assigned MAC address. */
1608         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1609         /* Generate the last 3 bytes of the MAC address with a random number. */
1610         random = rte_rand();
1611         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1612 }
1613
1614 /*
1615  * Virtual Function device init
1616  */
1617 static int
1618 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1619 {
1620         int diag;
1621         uint32_t tc, tcs;
1622         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1623         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1624         struct ixgbe_hw *hw =
1625                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1626         struct ixgbe_vfta *shadow_vfta =
1627                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1628         struct ixgbe_hwstrip *hwstrip =
1629                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1630         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1631
1632         PMD_INIT_FUNC_TRACE();
1633
1634         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1635         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1636         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1637
1638         /* for secondary processes, we don't initialise any further as primary
1639          * has already done this work. Only check we don't need a different
1640          * RX function
1641          */
1642         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1643                 struct ixgbe_tx_queue *txq;
1644                 /* TX queue function in primary, set by last queue initialized
1645                  * Tx queue may not initialized by primary process
1646                  */
1647                 if (eth_dev->data->tx_queues) {
1648                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1649                         ixgbe_set_tx_function(eth_dev, txq);
1650                 } else {
1651                         /* Use default TX function if we get here */
1652                         PMD_INIT_LOG(NOTICE,
1653                                      "No TX queues configured yet. Using default TX function.");
1654                 }
1655
1656                 ixgbe_set_rx_function(eth_dev);
1657
1658                 return 0;
1659         }
1660
1661         rte_eth_copy_pci_info(eth_dev, pci_dev);
1662
1663         hw->device_id = pci_dev->id.device_id;
1664         hw->vendor_id = pci_dev->id.vendor_id;
1665         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1666
1667         /* initialize the vfta */
1668         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1669
1670         /* initialize the hw strip bitmap*/
1671         memset(hwstrip, 0, sizeof(*hwstrip));
1672
1673         /* Initialize the shared code (base driver) */
1674         diag = ixgbe_init_shared_code(hw);
1675         if (diag != IXGBE_SUCCESS) {
1676                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1677                 return -EIO;
1678         }
1679
1680         /* init_mailbox_params */
1681         hw->mbx.ops.init_params(hw);
1682
1683         /* Reset the hw statistics */
1684         ixgbevf_dev_stats_reset(eth_dev);
1685
1686         /* Disable the interrupts for VF */
1687         ixgbevf_intr_disable(hw);
1688
1689         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1690         diag = hw->mac.ops.reset_hw(hw);
1691
1692         /*
1693          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1694          * the underlying PF driver has not assigned a MAC address to the VF.
1695          * In this case, assign a random MAC address.
1696          */
1697         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1698                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1699                 return diag;
1700         }
1701
1702         /* negotiate mailbox API version to use with the PF. */
1703         ixgbevf_negotiate_api(hw);
1704
1705         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1706         ixgbevf_get_queues(hw, &tcs, &tc);
1707
1708         /* Allocate memory for storing MAC addresses */
1709         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1710                                                hw->mac.num_rar_entries, 0);
1711         if (eth_dev->data->mac_addrs == NULL) {
1712                 PMD_INIT_LOG(ERR,
1713                              "Failed to allocate %u bytes needed to store "
1714                              "MAC addresses",
1715                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1716                 return -ENOMEM;
1717         }
1718
1719         /* Generate a random MAC address, if none was assigned by PF. */
1720         if (is_zero_ether_addr(perm_addr)) {
1721                 generate_random_mac_addr(perm_addr);
1722                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1723                 if (diag) {
1724                         rte_free(eth_dev->data->mac_addrs);
1725                         eth_dev->data->mac_addrs = NULL;
1726                         return diag;
1727                 }
1728                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1729                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1730                              "%02x:%02x:%02x:%02x:%02x:%02x",
1731                              perm_addr->addr_bytes[0],
1732                              perm_addr->addr_bytes[1],
1733                              perm_addr->addr_bytes[2],
1734                              perm_addr->addr_bytes[3],
1735                              perm_addr->addr_bytes[4],
1736                              perm_addr->addr_bytes[5]);
1737         }
1738
1739         /* Copy the permanent MAC address */
1740         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1741
1742         /* reset the hardware with the new settings */
1743         diag = hw->mac.ops.start_hw(hw);
1744         switch (diag) {
1745         case  0:
1746                 break;
1747
1748         default:
1749                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1750                 return -EIO;
1751         }
1752
1753         rte_intr_callback_register(intr_handle,
1754                                    ixgbevf_dev_interrupt_handler, eth_dev);
1755         rte_intr_enable(intr_handle);
1756         ixgbevf_intr_enable(hw);
1757
1758         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1759                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1760                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1761
1762         return 0;
1763 }
1764
1765 /* Virtual Function device uninit */
1766
1767 static int
1768 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1769 {
1770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1771         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1772         struct ixgbe_hw *hw;
1773
1774         PMD_INIT_FUNC_TRACE();
1775
1776         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1777                 return -EPERM;
1778
1779         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1780
1781         if (hw->adapter_stopped == 0)
1782                 ixgbevf_dev_close(eth_dev);
1783
1784         eth_dev->dev_ops = NULL;
1785         eth_dev->rx_pkt_burst = NULL;
1786         eth_dev->tx_pkt_burst = NULL;
1787
1788         /* Disable the interrupts for VF */
1789         ixgbevf_intr_disable(hw);
1790
1791         rte_free(eth_dev->data->mac_addrs);
1792         eth_dev->data->mac_addrs = NULL;
1793
1794         rte_intr_disable(intr_handle);
1795         rte_intr_callback_unregister(intr_handle,
1796                                      ixgbevf_dev_interrupt_handler, eth_dev);
1797
1798         return 0;
1799 }
1800
1801 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1802         struct rte_pci_device *pci_dev)
1803 {
1804         return rte_eth_dev_pci_generic_probe(pci_dev,
1805                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1806 }
1807
1808 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1809 {
1810         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1811 }
1812
1813 static struct rte_pci_driver rte_ixgbe_pmd = {
1814         .id_table = pci_id_ixgbe_map,
1815         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1816                      RTE_PCI_DRV_IOVA_AS_VA,
1817         .probe = eth_ixgbe_pci_probe,
1818         .remove = eth_ixgbe_pci_remove,
1819 };
1820
1821 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1822         struct rte_pci_device *pci_dev)
1823 {
1824         return rte_eth_dev_pci_generic_probe(pci_dev,
1825                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1826 }
1827
1828 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1829 {
1830         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1831 }
1832
1833 /*
1834  * virtual function driver struct
1835  */
1836 static struct rte_pci_driver rte_ixgbevf_pmd = {
1837         .id_table = pci_id_ixgbevf_map,
1838         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1839         .probe = eth_ixgbevf_pci_probe,
1840         .remove = eth_ixgbevf_pci_remove,
1841 };
1842
1843 static int
1844 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 {
1846         struct ixgbe_hw *hw =
1847                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct ixgbe_vfta *shadow_vfta =
1849                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1850         uint32_t vfta;
1851         uint32_t vid_idx;
1852         uint32_t vid_bit;
1853
1854         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1855         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1856         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1857         if (on)
1858                 vfta |= vid_bit;
1859         else
1860                 vfta &= ~vid_bit;
1861         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1862
1863         /* update local VFTA copy */
1864         shadow_vfta->vfta[vid_idx] = vfta;
1865
1866         return 0;
1867 }
1868
1869 static void
1870 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1871 {
1872         if (on)
1873                 ixgbe_vlan_hw_strip_enable(dev, queue);
1874         else
1875                 ixgbe_vlan_hw_strip_disable(dev, queue);
1876 }
1877
1878 static int
1879 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1880                     enum rte_vlan_type vlan_type,
1881                     uint16_t tpid)
1882 {
1883         struct ixgbe_hw *hw =
1884                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         int ret = 0;
1886         uint32_t reg;
1887         uint32_t qinq;
1888
1889         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890         qinq &= IXGBE_DMATXCTL_GDV;
1891
1892         switch (vlan_type) {
1893         case ETH_VLAN_TYPE_INNER:
1894                 if (qinq) {
1895                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1897                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1898                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1899                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1900                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1901                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1902                 } else {
1903                         ret = -ENOTSUP;
1904                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1905                                     " by single VLAN");
1906                 }
1907                 break;
1908         case ETH_VLAN_TYPE_OUTER:
1909                 if (qinq) {
1910                         /* Only the high 16-bits is valid */
1911                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1912                                         IXGBE_EXVET_VET_EXT_SHIFT);
1913                 } else {
1914                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1916                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1917                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1918                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1919                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1920                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1921                 }
1922
1923                 break;
1924         default:
1925                 ret = -EINVAL;
1926                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1927                 break;
1928         }
1929
1930         return ret;
1931 }
1932
1933 void
1934 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         uint32_t vlnctrl;
1939
1940         PMD_INIT_FUNC_TRACE();
1941
1942         /* Filter Table Disable */
1943         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1945
1946         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1947 }
1948
1949 void
1950 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1951 {
1952         struct ixgbe_hw *hw =
1953                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct ixgbe_vfta *shadow_vfta =
1955                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1956         uint32_t vlnctrl;
1957         uint16_t i;
1958
1959         PMD_INIT_FUNC_TRACE();
1960
1961         /* Filter Table Enable */
1962         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1963         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1964         vlnctrl |= IXGBE_VLNCTRL_VFE;
1965
1966         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1967
1968         /* write whatever is in local vfta copy */
1969         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1970                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1971 }
1972
1973 static void
1974 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1975 {
1976         struct ixgbe_hwstrip *hwstrip =
1977                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1978         struct ixgbe_rx_queue *rxq;
1979
1980         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1981                 return;
1982
1983         if (on)
1984                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1985         else
1986                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1987
1988         if (queue >= dev->data->nb_rx_queues)
1989                 return;
1990
1991         rxq = dev->data->rx_queues[queue];
1992
1993         if (on)
1994                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1995         else
1996                 rxq->vlan_flags = PKT_RX_VLAN;
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 void
2048 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053         uint16_t i;
2054         struct ixgbe_rx_queue *rxq;
2055
2056         PMD_INIT_FUNC_TRACE();
2057
2058         if (hw->mac.type == ixgbe_mac_82598EB) {
2059                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2060                 ctrl &= ~IXGBE_VLNCTRL_VME;
2061                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2062         } else {
2063                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2064                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2065                         rxq = dev->data->rx_queues[i];
2066                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2067                         ctrl &= ~IXGBE_RXDCTL_VME;
2068                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2069
2070                         /* record those setting for HW strip per queue */
2071                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2072                 }
2073         }
2074 }
2075
2076 void
2077 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2078 {
2079         struct ixgbe_hw *hw =
2080                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081         uint32_t ctrl;
2082         uint16_t i;
2083         struct ixgbe_rx_queue *rxq;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         if (hw->mac.type == ixgbe_mac_82598EB) {
2088                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2089                 ctrl |= IXGBE_VLNCTRL_VME;
2090                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2091         } else {
2092                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2093                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2094                         rxq = dev->data->rx_queues[i];
2095                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2096                         ctrl |= IXGBE_RXDCTL_VME;
2097                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2098
2099                         /* record those setting for HW strip per queue */
2100                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2101                 }
2102         }
2103 }
2104
2105 static void
2106 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         uint32_t ctrl;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         /* DMATXCTRL: Geric Double VLAN Disable */
2115         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2116         ctrl &= ~IXGBE_DMATXCTL_GDV;
2117         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2118
2119         /* CTRL_EXT: Global Double VLAN Disable */
2120         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2121         ctrl &= ~IXGBE_EXTENDED_VLAN;
2122         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2123
2124 }
2125
2126 static void
2127 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2128 {
2129         struct ixgbe_hw *hw =
2130                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131         uint32_t ctrl;
2132
2133         PMD_INIT_FUNC_TRACE();
2134
2135         /* DMATXCTRL: Geric Double VLAN Enable */
2136         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2137         ctrl |= IXGBE_DMATXCTL_GDV;
2138         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2139
2140         /* CTRL_EXT: Global Double VLAN Enable */
2141         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2142         ctrl |= IXGBE_EXTENDED_VLAN;
2143         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2144
2145         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2146         if (hw->mac.type == ixgbe_mac_X550 ||
2147             hw->mac.type == ixgbe_mac_X550EM_x ||
2148             hw->mac.type == ixgbe_mac_X550EM_a) {
2149                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2150                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2151                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2152         }
2153
2154         /*
2155          * VET EXT field in the EXVET register = 0x8100 by default
2156          * So no need to change. Same to VT field of DMATXCTL register
2157          */
2158 }
2159
2160 static int
2161 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2162 {
2163         if (mask & ETH_VLAN_STRIP_MASK) {
2164                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2165                         ixgbe_vlan_hw_strip_enable_all(dev);
2166                 else
2167                         ixgbe_vlan_hw_strip_disable_all(dev);
2168         }
2169
2170         if (mask & ETH_VLAN_FILTER_MASK) {
2171                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2172                         ixgbe_vlan_hw_filter_enable(dev);
2173                 else
2174                         ixgbe_vlan_hw_filter_disable(dev);
2175         }
2176
2177         if (mask & ETH_VLAN_EXTEND_MASK) {
2178                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2179                         ixgbe_vlan_hw_extend_enable(dev);
2180                 else
2181                         ixgbe_vlan_hw_extend_disable(dev);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static void
2188 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw =
2191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2193         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2194
2195         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2196         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2197 }
2198
2199 static int
2200 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2201 {
2202         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2203
2204         switch (nb_rx_q) {
2205         case 1:
2206         case 2:
2207                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2208                 break;
2209         case 4:
2210                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2211                 break;
2212         default:
2213                 return -EINVAL;
2214         }
2215
2216         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2217                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2218         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2219                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2220         return 0;
2221 }
2222
2223 static int
2224 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2225 {
2226         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2229         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2230
2231         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2232                 /* check multi-queue mode */
2233                 switch (dev_conf->rxmode.mq_mode) {
2234                 case ETH_MQ_RX_VMDQ_DCB:
2235                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2236                         break;
2237                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2238                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2239                         PMD_INIT_LOG(ERR, "SRIOV active,"
2240                                         " unsupported mq_mode rx %d.",
2241                                         dev_conf->rxmode.mq_mode);
2242                         return -EINVAL;
2243                 case ETH_MQ_RX_RSS:
2244                 case ETH_MQ_RX_VMDQ_RSS:
2245                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2246                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2247                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2248                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                                 " invalid queue number"
2250                                                 " for VMDQ RSS, allowed"
2251                                                 " value are 1, 2 or 4.");
2252                                         return -EINVAL;
2253                                 }
2254                         break;
2255                 case ETH_MQ_RX_VMDQ_ONLY:
2256                 case ETH_MQ_RX_NONE:
2257                         /* if nothing mq mode configure, use default scheme */
2258                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2259                         break;
2260                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2261                         /* SRIOV only works in VMDq enable mode */
2262                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2263                                         " wrong mq_mode rx %d.",
2264                                         dev_conf->rxmode.mq_mode);
2265                         return -EINVAL;
2266                 }
2267
2268                 switch (dev_conf->txmode.mq_mode) {
2269                 case ETH_MQ_TX_VMDQ_DCB:
2270                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2271                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2272                         break;
2273                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2274                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2275                         break;
2276                 }
2277
2278                 /* check valid queue number */
2279                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2280                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2281                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2282                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2283                                         " must be less than or equal to %d.",
2284                                         nb_rx_q, nb_tx_q,
2285                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2286                         return -EINVAL;
2287                 }
2288         } else {
2289                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2290                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2291                                           " not supported.");
2292                         return -EINVAL;
2293                 }
2294                 /* check configuration for vmdb+dcb mode */
2295                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2296                         const struct rte_eth_vmdq_dcb_conf *conf;
2297
2298                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2299                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2300                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2301                                 return -EINVAL;
2302                         }
2303                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2304                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2305                                conf->nb_queue_pools == ETH_32_POOLS)) {
2306                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2307                                                 " nb_queue_pools must be %d or %d.",
2308                                                 ETH_16_POOLS, ETH_32_POOLS);
2309                                 return -EINVAL;
2310                         }
2311                 }
2312                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2313                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2314
2315                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2317                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2318                                 return -EINVAL;
2319                         }
2320                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2321                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2322                                conf->nb_queue_pools == ETH_32_POOLS)) {
2323                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2324                                                 " nb_queue_pools != %d and"
2325                                                 " nb_queue_pools != %d.",
2326                                                 ETH_16_POOLS, ETH_32_POOLS);
2327                                 return -EINVAL;
2328                         }
2329                 }
2330
2331                 /* For DCB mode check our configuration before we go further */
2332                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2333                         const struct rte_eth_dcb_rx_conf *conf;
2334
2335                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2336                         if (!(conf->nb_tcs == ETH_4_TCS ||
2337                                conf->nb_tcs == ETH_8_TCS)) {
2338                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2339                                                 " and nb_tcs != %d.",
2340                                                 ETH_4_TCS, ETH_8_TCS);
2341                                 return -EINVAL;
2342                         }
2343                 }
2344
2345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2346                         const struct rte_eth_dcb_tx_conf *conf;
2347
2348                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2349                         if (!(conf->nb_tcs == ETH_4_TCS ||
2350                                conf->nb_tcs == ETH_8_TCS)) {
2351                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2352                                                 " and nb_tcs != %d.",
2353                                                 ETH_4_TCS, ETH_8_TCS);
2354                                 return -EINVAL;
2355                         }
2356                 }
2357
2358                 /*
2359                  * When DCB/VT is off, maximum number of queues changes,
2360                  * except for 82598EB, which remains constant.
2361                  */
2362                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2363                                 hw->mac.type != ixgbe_mac_82598EB) {
2364                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2365                                 PMD_INIT_LOG(ERR,
2366                                              "Neither VT nor DCB are enabled, "
2367                                              "nb_tx_q > %d.",
2368                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372         }
2373         return 0;
2374 }
2375
2376 static int
2377 ixgbe_dev_configure(struct rte_eth_dev *dev)
2378 {
2379         struct ixgbe_interrupt *intr =
2380                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2381         struct ixgbe_adapter *adapter =
2382                 (struct ixgbe_adapter *)dev->data->dev_private;
2383         int ret;
2384
2385         PMD_INIT_FUNC_TRACE();
2386         /* multipe queue mode checking */
2387         ret  = ixgbe_check_mq_mode(dev);
2388         if (ret != 0) {
2389                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2390                             ret);
2391                 return ret;
2392         }
2393
2394         /* set flag to update link status after init */
2395         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2396
2397         /*
2398          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2399          * allocation or vector Rx preconditions we will reset it.
2400          */
2401         adapter->rx_bulk_alloc_allowed = true;
2402         adapter->rx_vec_allowed = true;
2403
2404         return 0;
2405 }
2406
2407 static void
2408 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2409 {
2410         struct ixgbe_hw *hw =
2411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct ixgbe_interrupt *intr =
2413                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414         uint32_t gpie;
2415
2416         /* only set up it on X550EM_X */
2417         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2418                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2419                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2420                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2421                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2422                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2423         }
2424 }
2425
2426 int
2427 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2428                         uint16_t tx_rate, uint64_t q_msk)
2429 {
2430         struct ixgbe_hw *hw;
2431         struct ixgbe_vf_info *vfinfo;
2432         struct rte_eth_link link;
2433         uint8_t  nb_q_per_pool;
2434         uint32_t queue_stride;
2435         uint32_t queue_idx, idx = 0, vf_idx;
2436         uint32_t queue_end;
2437         uint16_t total_rate = 0;
2438         struct rte_pci_device *pci_dev;
2439
2440         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2441         rte_eth_link_get_nowait(dev->data->port_id, &link);
2442
2443         if (vf >= pci_dev->max_vfs)
2444                 return -EINVAL;
2445
2446         if (tx_rate > link.link_speed)
2447                 return -EINVAL;
2448
2449         if (q_msk == 0)
2450                 return 0;
2451
2452         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2453         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2454         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2455         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2456         queue_idx = vf * queue_stride;
2457         queue_end = queue_idx + nb_q_per_pool - 1;
2458         if (queue_end >= hw->mac.max_tx_queues)
2459                 return -EINVAL;
2460
2461         if (vfinfo) {
2462                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2463                         if (vf_idx == vf)
2464                                 continue;
2465                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2466                                 idx++)
2467                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2468                 }
2469         } else {
2470                 return -EINVAL;
2471         }
2472
2473         /* Store tx_rate for this vf. */
2474         for (idx = 0; idx < nb_q_per_pool; idx++) {
2475                 if (((uint64_t)0x1 << idx) & q_msk) {
2476                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2477                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2478                         total_rate += tx_rate;
2479                 }
2480         }
2481
2482         if (total_rate > dev->data->dev_link.link_speed) {
2483                 /* Reset stored TX rate of the VF if it causes exceed
2484                  * link speed.
2485                  */
2486                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2487                 return -EINVAL;
2488         }
2489
2490         /* Set RTTBCNRC of each queue/pool for vf X  */
2491         for (; queue_idx <= queue_end; queue_idx++) {
2492                 if (0x1 & q_msk)
2493                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2494                 q_msk = q_msk >> 1;
2495         }
2496
2497         return 0;
2498 }
2499
2500 /*
2501  * Configure device link speed and setup link.
2502  * It returns 0 on success.
2503  */
2504 static int
2505 ixgbe_dev_start(struct rte_eth_dev *dev)
2506 {
2507         struct ixgbe_hw *hw =
2508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509         struct ixgbe_vf_info *vfinfo =
2510                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2511         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2512         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2513         uint32_t intr_vector = 0;
2514         int err, link_up = 0, negotiate = 0;
2515         uint32_t speed = 0;
2516         int mask = 0;
2517         int status;
2518         uint16_t vf, idx;
2519         uint32_t *link_speeds;
2520         struct ixgbe_tm_conf *tm_conf =
2521                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2522
2523         PMD_INIT_FUNC_TRACE();
2524
2525         /* IXGBE devices don't support:
2526         *    - half duplex (checked afterwards for valid speeds)
2527         *    - fixed speed: TODO implement
2528         */
2529         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2530                 PMD_INIT_LOG(ERR,
2531                 "Invalid link_speeds for port %u, fix speed not supported",
2532                                 dev->data->port_id);
2533                 return -EINVAL;
2534         }
2535
2536         /* Stop the link setup handler before resetting the HW. */
2537         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2538
2539         /* disable uio/vfio intr/eventfd mapping */
2540         rte_intr_disable(intr_handle);
2541
2542         /* stop adapter */
2543         hw->adapter_stopped = 0;
2544         ixgbe_stop_adapter(hw);
2545
2546         /* reinitialize adapter
2547          * this calls reset and start
2548          */
2549         status = ixgbe_pf_reset_hw(hw);
2550         if (status != 0)
2551                 return -1;
2552         hw->mac.ops.start_hw(hw);
2553         hw->mac.get_link_status = true;
2554
2555         /* configure PF module if SRIOV enabled */
2556         ixgbe_pf_host_configure(dev);
2557
2558         ixgbe_dev_phy_intr_setup(dev);
2559
2560         /* check and configure queue intr-vector mapping */
2561         if ((rte_intr_cap_multiple(intr_handle) ||
2562              !RTE_ETH_DEV_SRIOV(dev).active) &&
2563             dev->data->dev_conf.intr_conf.rxq != 0) {
2564                 intr_vector = dev->data->nb_rx_queues;
2565                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2566                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2567                                         IXGBE_MAX_INTR_QUEUE_NUM);
2568                         return -ENOTSUP;
2569                 }
2570                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2571                         return -1;
2572         }
2573
2574         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2575                 intr_handle->intr_vec =
2576                         rte_zmalloc("intr_vec",
2577                                     dev->data->nb_rx_queues * sizeof(int), 0);
2578                 if (intr_handle->intr_vec == NULL) {
2579                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2580                                      " intr_vec", dev->data->nb_rx_queues);
2581                         return -ENOMEM;
2582                 }
2583         }
2584
2585         /* confiugre msix for sleep until rx interrupt */
2586         ixgbe_configure_msix(dev);
2587
2588         /* initialize transmission unit */
2589         ixgbe_dev_tx_init(dev);
2590
2591         /* This can fail when allocating mbufs for descriptor rings */
2592         err = ixgbe_dev_rx_init(dev);
2593         if (err) {
2594                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2595                 goto error;
2596         }
2597
2598         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2599                 ETH_VLAN_EXTEND_MASK;
2600         err = ixgbe_vlan_offload_set(dev, mask);
2601         if (err) {
2602                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2603                 goto error;
2604         }
2605
2606         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2607                 /* Enable vlan filtering for VMDq */
2608                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2609         }
2610
2611         /* Configure DCB hw */
2612         ixgbe_configure_dcb(dev);
2613
2614         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2615                 err = ixgbe_fdir_configure(dev);
2616                 if (err)
2617                         goto error;
2618         }
2619
2620         /* Restore vf rate limit */
2621         if (vfinfo != NULL) {
2622                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2623                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2624                                 if (vfinfo[vf].tx_rate[idx] != 0)
2625                                         ixgbe_set_vf_rate_limit(
2626                                                 dev, vf,
2627                                                 vfinfo[vf].tx_rate[idx],
2628                                                 1 << idx);
2629         }
2630
2631         ixgbe_restore_statistics_mapping(dev);
2632
2633         err = ixgbe_dev_rxtx_start(dev);
2634         if (err < 0) {
2635                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2636                 goto error;
2637         }
2638
2639         /* Skip link setup if loopback mode is enabled for 82599. */
2640         if (hw->mac.type == ixgbe_mac_82599EB &&
2641                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2642                 goto skip_link_setup;
2643
2644         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2645                 err = hw->mac.ops.setup_sfp(hw);
2646                 if (err)
2647                         goto error;
2648         }
2649
2650         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2651                 /* Turn on the copper */
2652                 ixgbe_set_phy_power(hw, true);
2653         } else {
2654                 /* Turn on the laser */
2655                 ixgbe_enable_tx_laser(hw);
2656         }
2657
2658         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2659         if (err)
2660                 goto error;
2661         dev->data->dev_link.link_status = link_up;
2662
2663         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2664         if (err)
2665                 goto error;
2666
2667         link_speeds = &dev->data->dev_conf.link_speeds;
2668         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2669                         ETH_LINK_SPEED_10G)) {
2670                 PMD_INIT_LOG(ERR, "Invalid link setting");
2671                 goto error;
2672         }
2673
2674         speed = 0x0;
2675         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2676                 switch (hw->mac.type) {
2677                 case ixgbe_mac_82598EB:
2678                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2679                         break;
2680                 case ixgbe_mac_82599EB:
2681                 case ixgbe_mac_X540:
2682                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2683                         break;
2684                 case ixgbe_mac_X550:
2685                 case ixgbe_mac_X550EM_x:
2686                 case ixgbe_mac_X550EM_a:
2687                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2688                         break;
2689                 default:
2690                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2691                 }
2692         } else {
2693                 if (*link_speeds & ETH_LINK_SPEED_10G)
2694                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2695                 if (*link_speeds & ETH_LINK_SPEED_1G)
2696                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2697                 if (*link_speeds & ETH_LINK_SPEED_100M)
2698                         speed |= IXGBE_LINK_SPEED_100_FULL;
2699         }
2700
2701         err = ixgbe_setup_link(hw, speed, link_up);
2702         if (err)
2703                 goto error;
2704
2705 skip_link_setup:
2706
2707         if (rte_intr_allow_others(intr_handle)) {
2708                 /* check if lsc interrupt is enabled */
2709                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2710                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2711                 else
2712                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2713                 ixgbe_dev_macsec_interrupt_setup(dev);
2714         } else {
2715                 rte_intr_callback_unregister(intr_handle,
2716                                              ixgbe_dev_interrupt_handler, dev);
2717                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2718                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2719                                      " no intr multiplex");
2720         }
2721
2722         /* check if rxq interrupt is enabled */
2723         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2724             rte_intr_dp_is_en(intr_handle))
2725                 ixgbe_dev_rxq_interrupt_setup(dev);
2726
2727         /* enable uio/vfio intr/eventfd mapping */
2728         rte_intr_enable(intr_handle);
2729
2730         /* resume enabled intr since hw reset */
2731         ixgbe_enable_intr(dev);
2732         ixgbe_l2_tunnel_conf(dev);
2733         ixgbe_filter_restore(dev);
2734
2735         if (tm_conf->root && !tm_conf->committed)
2736                 PMD_DRV_LOG(WARNING,
2737                             "please call hierarchy_commit() "
2738                             "before starting the port");
2739
2740         /*
2741          * Update link status right before return, because it may
2742          * start link configuration process in a separate thread.
2743          */
2744         ixgbe_dev_link_update(dev, 0);
2745
2746         return 0;
2747
2748 error:
2749         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2750         ixgbe_dev_clear_queues(dev);
2751         return -EIO;
2752 }
2753
2754 /*
2755  * Stop device: disable rx and tx functions to allow for reconfiguring.
2756  */
2757 static void
2758 ixgbe_dev_stop(struct rte_eth_dev *dev)
2759 {
2760         struct rte_eth_link link;
2761         struct ixgbe_hw *hw =
2762                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763         struct ixgbe_vf_info *vfinfo =
2764                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2767         int vf;
2768         struct ixgbe_tm_conf *tm_conf =
2769                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2770
2771         PMD_INIT_FUNC_TRACE();
2772
2773         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2774
2775         /* disable interrupts */
2776         ixgbe_disable_intr(hw);
2777
2778         /* reset the NIC */
2779         ixgbe_pf_reset_hw(hw);
2780         hw->adapter_stopped = 0;
2781
2782         /* stop adapter */
2783         ixgbe_stop_adapter(hw);
2784
2785         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2786                 vfinfo[vf].clear_to_send = false;
2787
2788         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2789                 /* Turn off the copper */
2790                 ixgbe_set_phy_power(hw, false);
2791         } else {
2792                 /* Turn off the laser */
2793                 ixgbe_disable_tx_laser(hw);
2794         }
2795
2796         ixgbe_dev_clear_queues(dev);
2797
2798         /* Clear stored conf */
2799         dev->data->scattered_rx = 0;
2800         dev->data->lro = 0;
2801
2802         /* Clear recorded link status */
2803         memset(&link, 0, sizeof(link));
2804         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2805
2806         if (!rte_intr_allow_others(intr_handle))
2807                 /* resume to the default handler */
2808                 rte_intr_callback_register(intr_handle,
2809                                            ixgbe_dev_interrupt_handler,
2810                                            (void *)dev);
2811
2812         /* Clean datapath event and queue/vec mapping */
2813         rte_intr_efd_disable(intr_handle);
2814         if (intr_handle->intr_vec != NULL) {
2815                 rte_free(intr_handle->intr_vec);
2816                 intr_handle->intr_vec = NULL;
2817         }
2818
2819         /* reset hierarchy commit */
2820         tm_conf->committed = false;
2821 }
2822
2823 /*
2824  * Set device link up: enable tx.
2825  */
2826 static int
2827 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2828 {
2829         struct ixgbe_hw *hw =
2830                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831         if (hw->mac.type == ixgbe_mac_82599EB) {
2832 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2833                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2834                         /* Not suported in bypass mode */
2835                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2836                                      "by device id 0x%x", hw->device_id);
2837                         return -ENOTSUP;
2838                 }
2839 #endif
2840         }
2841
2842         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2843                 /* Turn on the copper */
2844                 ixgbe_set_phy_power(hw, true);
2845         } else {
2846                 /* Turn on the laser */
2847                 ixgbe_enable_tx_laser(hw);
2848         }
2849
2850         return 0;
2851 }
2852
2853 /*
2854  * Set device link down: disable tx.
2855  */
2856 static int
2857 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2858 {
2859         struct ixgbe_hw *hw =
2860                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         if (hw->mac.type == ixgbe_mac_82599EB) {
2862 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2863                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2864                         /* Not suported in bypass mode */
2865                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2866                                      "by device id 0x%x", hw->device_id);
2867                         return -ENOTSUP;
2868                 }
2869 #endif
2870         }
2871
2872         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2873                 /* Turn off the copper */
2874                 ixgbe_set_phy_power(hw, false);
2875         } else {
2876                 /* Turn off the laser */
2877                 ixgbe_disable_tx_laser(hw);
2878         }
2879
2880         return 0;
2881 }
2882
2883 /*
2884  * Reset and stop device.
2885  */
2886 static void
2887 ixgbe_dev_close(struct rte_eth_dev *dev)
2888 {
2889         struct ixgbe_hw *hw =
2890                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891
2892         PMD_INIT_FUNC_TRACE();
2893
2894         ixgbe_pf_reset_hw(hw);
2895
2896         ixgbe_dev_stop(dev);
2897         hw->adapter_stopped = 1;
2898
2899         ixgbe_dev_free_queues(dev);
2900
2901         ixgbe_disable_pcie_master(hw);
2902
2903         /* reprogram the RAR[0] in case user changed it. */
2904         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2905 }
2906
2907 /*
2908  * Reset PF device.
2909  */
2910 static int
2911 ixgbe_dev_reset(struct rte_eth_dev *dev)
2912 {
2913         int ret;
2914
2915         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2916          * its VF to make them align with it. The detailed notification
2917          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2918          * To avoid unexpected behavior in VF, currently reset of PF with
2919          * SR-IOV activation is not supported. It might be supported later.
2920          */
2921         if (dev->data->sriov.active)
2922                 return -ENOTSUP;
2923
2924         ret = eth_ixgbe_dev_uninit(dev);
2925         if (ret)
2926                 return ret;
2927
2928         ret = eth_ixgbe_dev_init(dev);
2929
2930         return ret;
2931 }
2932
2933 static void
2934 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2935                            struct ixgbe_hw_stats *hw_stats,
2936                            struct ixgbe_macsec_stats *macsec_stats,
2937                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2938                            uint64_t *total_qprc, uint64_t *total_qprdc)
2939 {
2940         uint32_t bprc, lxon, lxoff, total;
2941         uint32_t delta_gprc = 0;
2942         unsigned i;
2943         /* Workaround for RX byte count not including CRC bytes when CRC
2944          * strip is enabled. CRC bytes are removed from counters when crc_strip
2945          * is disabled.
2946          */
2947         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2948                         IXGBE_HLREG0_RXCRCSTRP);
2949
2950         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2951         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2952         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2953         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2954
2955         for (i = 0; i < 8; i++) {
2956                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2957
2958                 /* global total per queue */
2959                 hw_stats->mpc[i] += mp;
2960                 /* Running comprehensive total for stats display */
2961                 *total_missed_rx += hw_stats->mpc[i];
2962                 if (hw->mac.type == ixgbe_mac_82598EB) {
2963                         hw_stats->rnbc[i] +=
2964                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2965                         hw_stats->pxonrxc[i] +=
2966                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2967                         hw_stats->pxoffrxc[i] +=
2968                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2969                 } else {
2970                         hw_stats->pxonrxc[i] +=
2971                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2972                         hw_stats->pxoffrxc[i] +=
2973                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2974                         hw_stats->pxon2offc[i] +=
2975                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2976                 }
2977                 hw_stats->pxontxc[i] +=
2978                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2979                 hw_stats->pxofftxc[i] +=
2980                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2981         }
2982         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2983                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2984                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2985                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2986
2987                 delta_gprc += delta_qprc;
2988
2989                 hw_stats->qprc[i] += delta_qprc;
2990                 hw_stats->qptc[i] += delta_qptc;
2991
2992                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2993                 hw_stats->qbrc[i] +=
2994                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2995                 if (crc_strip == 0)
2996                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2997
2998                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2999                 hw_stats->qbtc[i] +=
3000                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3001
3002                 hw_stats->qprdc[i] += delta_qprdc;
3003                 *total_qprdc += hw_stats->qprdc[i];
3004
3005                 *total_qprc += hw_stats->qprc[i];
3006                 *total_qbrc += hw_stats->qbrc[i];
3007         }
3008         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3009         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3010         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3011
3012         /*
3013          * An errata states that gprc actually counts good + missed packets:
3014          * Workaround to set gprc to summated queue packet receives
3015          */
3016         hw_stats->gprc = *total_qprc;
3017
3018         if (hw->mac.type != ixgbe_mac_82598EB) {
3019                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3020                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3021                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3022                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3023                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3024                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3025                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3026                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3027         } else {
3028                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3029                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3030                 /* 82598 only has a counter in the high register */
3031                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3032                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3033                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3034         }
3035         uint64_t old_tpr = hw_stats->tpr;
3036
3037         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3038         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3039
3040         if (crc_strip == 0)
3041                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3042
3043         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3044         hw_stats->gptc += delta_gptc;
3045         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3046         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3047
3048         /*
3049          * Workaround: mprc hardware is incorrectly counting
3050          * broadcasts, so for now we subtract those.
3051          */
3052         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3053         hw_stats->bprc += bprc;
3054         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3055         if (hw->mac.type == ixgbe_mac_82598EB)
3056                 hw_stats->mprc -= bprc;
3057
3058         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3059         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3060         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3061         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3062         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3063         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3064
3065         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3066         hw_stats->lxontxc += lxon;
3067         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3068         hw_stats->lxofftxc += lxoff;
3069         total = lxon + lxoff;
3070
3071         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3072         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3073         hw_stats->gptc -= total;
3074         hw_stats->mptc -= total;
3075         hw_stats->ptc64 -= total;
3076         hw_stats->gotc -= total * ETHER_MIN_LEN;
3077
3078         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3079         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3080         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3081         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3082         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3083         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3084         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3085         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3086         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3087         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3088         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3089         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3090         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3091         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3092         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3093         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3094         /* Only read FCOE on 82599 */
3095         if (hw->mac.type != ixgbe_mac_82598EB) {
3096                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3097                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3098                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3099                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3100                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3101         }
3102
3103         /* Flow Director Stats registers */
3104         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3105         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3106
3107         /* MACsec Stats registers */
3108         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3109         macsec_stats->out_pkts_encrypted +=
3110                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3111         macsec_stats->out_pkts_protected +=
3112                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3113         macsec_stats->out_octets_encrypted +=
3114                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3115         macsec_stats->out_octets_protected +=
3116                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3117         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3118         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3119         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3120         macsec_stats->in_pkts_unknownsci +=
3121                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3122         macsec_stats->in_octets_decrypted +=
3123                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3124         macsec_stats->in_octets_validated +=
3125                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3126         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3127         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3128         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3129         for (i = 0; i < 2; i++) {
3130                 macsec_stats->in_pkts_ok +=
3131                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3132                 macsec_stats->in_pkts_invalid +=
3133                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3134                 macsec_stats->in_pkts_notvalid +=
3135                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3136         }
3137         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3138         macsec_stats->in_pkts_notusingsa +=
3139                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3140 }
3141
3142 /*
3143  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3144  */
3145 static int
3146 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3147 {
3148         struct ixgbe_hw *hw =
3149                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3150         struct ixgbe_hw_stats *hw_stats =
3151                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3152         struct ixgbe_macsec_stats *macsec_stats =
3153                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3154                                 dev->data->dev_private);
3155         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3156         unsigned i;
3157
3158         total_missed_rx = 0;
3159         total_qbrc = 0;
3160         total_qprc = 0;
3161         total_qprdc = 0;
3162
3163         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3164                         &total_qbrc, &total_qprc, &total_qprdc);
3165
3166         if (stats == NULL)
3167                 return -EINVAL;
3168
3169         /* Fill out the rte_eth_stats statistics structure */
3170         stats->ipackets = total_qprc;
3171         stats->ibytes = total_qbrc;
3172         stats->opackets = hw_stats->gptc;
3173         stats->obytes = hw_stats->gotc;
3174
3175         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3176                 stats->q_ipackets[i] = hw_stats->qprc[i];
3177                 stats->q_opackets[i] = hw_stats->qptc[i];
3178                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3179                 stats->q_obytes[i] = hw_stats->qbtc[i];
3180                 stats->q_errors[i] = hw_stats->qprdc[i];
3181         }
3182
3183         /* Rx Errors */
3184         stats->imissed  = total_missed_rx;
3185         stats->ierrors  = hw_stats->crcerrs +
3186                           hw_stats->mspdc +
3187                           hw_stats->rlec +
3188                           hw_stats->ruc +
3189                           hw_stats->roc +
3190                           hw_stats->illerrc +
3191                           hw_stats->errbc +
3192                           hw_stats->rfc +
3193                           hw_stats->fccrc +
3194                           hw_stats->fclast;
3195
3196         /* Tx Errors */
3197         stats->oerrors  = 0;
3198         return 0;
3199 }
3200
3201 static void
3202 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3203 {
3204         struct ixgbe_hw_stats *stats =
3205                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3206
3207         /* HW registers are cleared on read */
3208         ixgbe_dev_stats_get(dev, NULL);
3209
3210         /* Reset software totals */
3211         memset(stats, 0, sizeof(*stats));
3212 }
3213
3214 /* This function calculates the number of xstats based on the current config */
3215 static unsigned
3216 ixgbe_xstats_calc_num(void) {
3217         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3218                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3219                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3220 }
3221
3222 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3223         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3224 {
3225         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3226         unsigned stat, i, count;
3227
3228         if (xstats_names != NULL) {
3229                 count = 0;
3230
3231                 /* Note: limit >= cnt_stats checked upstream
3232                  * in rte_eth_xstats_names()
3233                  */
3234
3235                 /* Extended stats from ixgbe_hw_stats */
3236                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3237                         snprintf(xstats_names[count].name,
3238                                 sizeof(xstats_names[count].name),
3239                                 "%s",
3240                                 rte_ixgbe_stats_strings[i].name);
3241                         count++;
3242                 }
3243
3244                 /* MACsec Stats */
3245                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3246                         snprintf(xstats_names[count].name,
3247                                 sizeof(xstats_names[count].name),
3248                                 "%s",
3249                                 rte_ixgbe_macsec_strings[i].name);
3250                         count++;
3251                 }
3252
3253                 /* RX Priority Stats */
3254                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3255                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3256                                 snprintf(xstats_names[count].name,
3257                                         sizeof(xstats_names[count].name),
3258                                         "rx_priority%u_%s", i,
3259                                         rte_ixgbe_rxq_strings[stat].name);
3260                                 count++;
3261                         }
3262                 }
3263
3264                 /* TX Priority Stats */
3265                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3266                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3267                                 snprintf(xstats_names[count].name,
3268                                         sizeof(xstats_names[count].name),
3269                                         "tx_priority%u_%s", i,
3270                                         rte_ixgbe_txq_strings[stat].name);
3271                                 count++;
3272                         }
3273                 }
3274         }
3275         return cnt_stats;
3276 }
3277
3278 static int ixgbe_dev_xstats_get_names_by_id(
3279         struct rte_eth_dev *dev,
3280         struct rte_eth_xstat_name *xstats_names,
3281         const uint64_t *ids,
3282         unsigned int limit)
3283 {
3284         if (!ids) {
3285                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3286                 unsigned int stat, i, count;
3287
3288                 if (xstats_names != NULL) {
3289                         count = 0;
3290
3291                         /* Note: limit >= cnt_stats checked upstream
3292                          * in rte_eth_xstats_names()
3293                          */
3294
3295                         /* Extended stats from ixgbe_hw_stats */
3296                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3297                                 snprintf(xstats_names[count].name,
3298                                         sizeof(xstats_names[count].name),
3299                                         "%s",
3300                                         rte_ixgbe_stats_strings[i].name);
3301                                 count++;
3302                         }
3303
3304                         /* MACsec Stats */
3305                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3306                                 snprintf(xstats_names[count].name,
3307                                         sizeof(xstats_names[count].name),
3308                                         "%s",
3309                                         rte_ixgbe_macsec_strings[i].name);
3310                                 count++;
3311                         }
3312
3313                         /* RX Priority Stats */
3314                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3315                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3316                                         snprintf(xstats_names[count].name,
3317                                             sizeof(xstats_names[count].name),
3318                                             "rx_priority%u_%s", i,
3319                                             rte_ixgbe_rxq_strings[stat].name);
3320                                         count++;
3321                                 }
3322                         }
3323
3324                         /* TX Priority Stats */
3325                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3326                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3327                                         snprintf(xstats_names[count].name,
3328                                             sizeof(xstats_names[count].name),
3329                                             "tx_priority%u_%s", i,
3330                                             rte_ixgbe_txq_strings[stat].name);
3331                                         count++;
3332                                 }
3333                         }
3334                 }
3335                 return cnt_stats;
3336         }
3337
3338         uint16_t i;
3339         uint16_t size = ixgbe_xstats_calc_num();
3340         struct rte_eth_xstat_name xstats_names_copy[size];
3341
3342         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3343                         size);
3344
3345         for (i = 0; i < limit; i++) {
3346                 if (ids[i] >= size) {
3347                         PMD_INIT_LOG(ERR, "id value isn't valid");
3348                         return -1;
3349                 }
3350                 strcpy(xstats_names[i].name,
3351                                 xstats_names_copy[ids[i]].name);
3352         }
3353         return limit;
3354 }
3355
3356 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3357         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3358 {
3359         unsigned i;
3360
3361         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3362                 return -ENOMEM;
3363
3364         if (xstats_names != NULL)
3365                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3366                         snprintf(xstats_names[i].name,
3367                                 sizeof(xstats_names[i].name),
3368                                 "%s", rte_ixgbevf_stats_strings[i].name);
3369         return IXGBEVF_NB_XSTATS;
3370 }
3371
3372 static int
3373 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3374                                          unsigned n)
3375 {
3376         struct ixgbe_hw *hw =
3377                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         struct ixgbe_hw_stats *hw_stats =
3379                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3380         struct ixgbe_macsec_stats *macsec_stats =
3381                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3382                                 dev->data->dev_private);
3383         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3384         unsigned i, stat, count = 0;
3385
3386         count = ixgbe_xstats_calc_num();
3387
3388         if (n < count)
3389                 return count;
3390
3391         total_missed_rx = 0;
3392         total_qbrc = 0;
3393         total_qprc = 0;
3394         total_qprdc = 0;
3395
3396         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3397                         &total_qbrc, &total_qprc, &total_qprdc);
3398
3399         /* If this is a reset xstats is NULL, and we have cleared the
3400          * registers by reading them.
3401          */
3402         if (!xstats)
3403                 return 0;
3404
3405         /* Extended stats from ixgbe_hw_stats */
3406         count = 0;
3407         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3408                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3409                                 rte_ixgbe_stats_strings[i].offset);
3410                 xstats[count].id = count;
3411                 count++;
3412         }
3413
3414         /* MACsec Stats */
3415         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3416                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3417                                 rte_ixgbe_macsec_strings[i].offset);
3418                 xstats[count].id = count;
3419                 count++;
3420         }
3421
3422         /* RX Priority Stats */
3423         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3424                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3425                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3426                                         rte_ixgbe_rxq_strings[stat].offset +
3427                                         (sizeof(uint64_t) * i));
3428                         xstats[count].id = count;
3429                         count++;
3430                 }
3431         }
3432
3433         /* TX Priority Stats */
3434         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3435                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3436                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3437                                         rte_ixgbe_txq_strings[stat].offset +
3438                                         (sizeof(uint64_t) * i));
3439                         xstats[count].id = count;
3440                         count++;
3441                 }
3442         }
3443         return count;
3444 }
3445
3446 static int
3447 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3448                 uint64_t *values, unsigned int n)
3449 {
3450         if (!ids) {
3451                 struct ixgbe_hw *hw =
3452                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453                 struct ixgbe_hw_stats *hw_stats =
3454                                 IXGBE_DEV_PRIVATE_TO_STATS(
3455                                                 dev->data->dev_private);
3456                 struct ixgbe_macsec_stats *macsec_stats =
3457                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3458                                         dev->data->dev_private);
3459                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3460                 unsigned int i, stat, count = 0;
3461
3462                 count = ixgbe_xstats_calc_num();
3463
3464                 if (!ids && n < count)
3465                         return count;
3466
3467                 total_missed_rx = 0;
3468                 total_qbrc = 0;
3469                 total_qprc = 0;
3470                 total_qprdc = 0;
3471
3472                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3473                                 &total_missed_rx, &total_qbrc, &total_qprc,
3474                                 &total_qprdc);
3475
3476                 /* If this is a reset xstats is NULL, and we have cleared the
3477                  * registers by reading them.
3478                  */
3479                 if (!ids && !values)
3480                         return 0;
3481
3482                 /* Extended stats from ixgbe_hw_stats */
3483                 count = 0;
3484                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3485                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3486                                         rte_ixgbe_stats_strings[i].offset);
3487                         count++;
3488                 }
3489
3490                 /* MACsec Stats */
3491                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3492                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3493                                         rte_ixgbe_macsec_strings[i].offset);
3494                         count++;
3495                 }
3496
3497                 /* RX Priority Stats */
3498                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3499                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3500                                 values[count] =
3501                                         *(uint64_t *)(((char *)hw_stats) +
3502                                         rte_ixgbe_rxq_strings[stat].offset +
3503                                         (sizeof(uint64_t) * i));
3504                                 count++;
3505                         }
3506                 }
3507
3508                 /* TX Priority Stats */
3509                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3510                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3511                                 values[count] =
3512                                         *(uint64_t *)(((char *)hw_stats) +
3513                                         rte_ixgbe_txq_strings[stat].offset +
3514                                         (sizeof(uint64_t) * i));
3515                                 count++;
3516                         }
3517                 }
3518                 return count;
3519         }
3520
3521         uint16_t i;
3522         uint16_t size = ixgbe_xstats_calc_num();
3523         uint64_t values_copy[size];
3524
3525         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3526
3527         for (i = 0; i < n; i++) {
3528                 if (ids[i] >= size) {
3529                         PMD_INIT_LOG(ERR, "id value isn't valid");
3530                         return -1;
3531                 }
3532                 values[i] = values_copy[ids[i]];
3533         }
3534         return n;
3535 }
3536
3537 static void
3538 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3539 {
3540         struct ixgbe_hw_stats *stats =
3541                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542         struct ixgbe_macsec_stats *macsec_stats =
3543                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3544                                 dev->data->dev_private);
3545
3546         unsigned count = ixgbe_xstats_calc_num();
3547
3548         /* HW registers are cleared on read */
3549         ixgbe_dev_xstats_get(dev, NULL, count);
3550
3551         /* Reset software totals */
3552         memset(stats, 0, sizeof(*stats));
3553         memset(macsec_stats, 0, sizeof(*macsec_stats));
3554 }
3555
3556 static void
3557 ixgbevf_update_stats(struct rte_eth_dev *dev)
3558 {
3559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3561                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3562
3563         /* Good Rx packet, include VF loopback */
3564         UPDATE_VF_STAT(IXGBE_VFGPRC,
3565             hw_stats->last_vfgprc, hw_stats->vfgprc);
3566
3567         /* Good Rx octets, include VF loopback */
3568         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3569             hw_stats->last_vfgorc, hw_stats->vfgorc);
3570
3571         /* Good Tx packet, include VF loopback */
3572         UPDATE_VF_STAT(IXGBE_VFGPTC,
3573             hw_stats->last_vfgptc, hw_stats->vfgptc);
3574
3575         /* Good Tx octets, include VF loopback */
3576         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3577             hw_stats->last_vfgotc, hw_stats->vfgotc);
3578
3579         /* Rx Multicst Packet */
3580         UPDATE_VF_STAT(IXGBE_VFMPRC,
3581             hw_stats->last_vfmprc, hw_stats->vfmprc);
3582 }
3583
3584 static int
3585 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3586                        unsigned n)
3587 {
3588         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3589                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3590         unsigned i;
3591
3592         if (n < IXGBEVF_NB_XSTATS)
3593                 return IXGBEVF_NB_XSTATS;
3594
3595         ixgbevf_update_stats(dev);
3596
3597         if (!xstats)
3598                 return 0;
3599
3600         /* Extended stats */
3601         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3602                 xstats[i].id = i;
3603                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3604                         rte_ixgbevf_stats_strings[i].offset);
3605         }
3606
3607         return IXGBEVF_NB_XSTATS;
3608 }
3609
3610 static int
3611 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3612 {
3613         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3614                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3615
3616         ixgbevf_update_stats(dev);
3617
3618         if (stats == NULL)
3619                 return -EINVAL;
3620
3621         stats->ipackets = hw_stats->vfgprc;
3622         stats->ibytes = hw_stats->vfgorc;
3623         stats->opackets = hw_stats->vfgptc;
3624         stats->obytes = hw_stats->vfgotc;
3625         return 0;
3626 }
3627
3628 static void
3629 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3630 {
3631         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3632                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3633
3634         /* Sync HW register to the last stats */
3635         ixgbevf_dev_stats_get(dev, NULL);
3636
3637         /* reset HW current stats*/
3638         hw_stats->vfgprc = 0;
3639         hw_stats->vfgorc = 0;
3640         hw_stats->vfgptc = 0;
3641         hw_stats->vfgotc = 0;
3642 }
3643
3644 static int
3645 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3646 {
3647         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648         u16 eeprom_verh, eeprom_verl;
3649         u32 etrack_id;
3650         int ret;
3651
3652         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3653         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3654
3655         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3656         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3657
3658         ret += 1; /* add the size of '\0' */
3659         if (fw_size < (u32)ret)
3660                 return ret;
3661         else
3662                 return 0;
3663 }
3664
3665 static void
3666 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3667 {
3668         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3671
3672         dev_info->pci_dev = pci_dev;
3673         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3674         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3675         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3676                 /*
3677                  * When DCB/VT is off, maximum number of queues changes,
3678                  * except for 82598EB, which remains constant.
3679                  */
3680                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3681                                 hw->mac.type != ixgbe_mac_82598EB)
3682                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3683         }
3684         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3685         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3686         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3687         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3688         dev_info->max_vfs = pci_dev->max_vfs;
3689         if (hw->mac.type == ixgbe_mac_82598EB)
3690                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3691         else
3692                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3693         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3694         dev_info->rx_offload_capa =
3695                 DEV_RX_OFFLOAD_VLAN_STRIP |
3696                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3697                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3698                 DEV_RX_OFFLOAD_TCP_CKSUM;
3699
3700         /*
3701          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3702          * mode.
3703          */
3704         if ((hw->mac.type == ixgbe_mac_82599EB ||
3705              hw->mac.type == ixgbe_mac_X540) &&
3706             !RTE_ETH_DEV_SRIOV(dev).active)
3707                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3708
3709         if (hw->mac.type == ixgbe_mac_82599EB ||
3710             hw->mac.type == ixgbe_mac_X540)
3711                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3712
3713         if (hw->mac.type == ixgbe_mac_X550 ||
3714             hw->mac.type == ixgbe_mac_X550EM_x ||
3715             hw->mac.type == ixgbe_mac_X550EM_a)
3716                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3717
3718         dev_info->tx_offload_capa =
3719                 DEV_TX_OFFLOAD_VLAN_INSERT |
3720                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3721                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3722                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3723                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3724                 DEV_TX_OFFLOAD_TCP_TSO;
3725
3726         if (hw->mac.type == ixgbe_mac_82599EB ||
3727             hw->mac.type == ixgbe_mac_X540)
3728                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3729
3730         if (hw->mac.type == ixgbe_mac_X550 ||
3731             hw->mac.type == ixgbe_mac_X550EM_x ||
3732             hw->mac.type == ixgbe_mac_X550EM_a)
3733                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3734
3735 #ifdef RTE_LIBRTE_SECURITY
3736         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3737         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3738 #endif
3739
3740         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3741                 .rx_thresh = {
3742                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3743                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3744                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3745                 },
3746                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3747                 .rx_drop_en = 0,
3748         };
3749
3750         dev_info->default_txconf = (struct rte_eth_txconf) {
3751                 .tx_thresh = {
3752                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3753                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3754                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3755                 },
3756                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3757                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3758                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3759                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3760         };
3761
3762         dev_info->rx_desc_lim = rx_desc_lim;
3763         dev_info->tx_desc_lim = tx_desc_lim;
3764
3765         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3766         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3767         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3768
3769         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3770         if (hw->mac.type == ixgbe_mac_X540 ||
3771             hw->mac.type == ixgbe_mac_X540_vf ||
3772             hw->mac.type == ixgbe_mac_X550 ||
3773             hw->mac.type == ixgbe_mac_X550_vf) {
3774                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3775         }
3776         if (hw->mac.type == ixgbe_mac_X550) {
3777                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3778                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3779         }
3780 }
3781
3782 static const uint32_t *
3783 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3784 {
3785         static const uint32_t ptypes[] = {
3786                 /* For non-vec functions,
3787                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3788                  * for vec functions,
3789                  * refers to _recv_raw_pkts_vec().
3790                  */
3791                 RTE_PTYPE_L2_ETHER,
3792                 RTE_PTYPE_L3_IPV4,
3793                 RTE_PTYPE_L3_IPV4_EXT,
3794                 RTE_PTYPE_L3_IPV6,
3795                 RTE_PTYPE_L3_IPV6_EXT,
3796                 RTE_PTYPE_L4_SCTP,
3797                 RTE_PTYPE_L4_TCP,
3798                 RTE_PTYPE_L4_UDP,
3799                 RTE_PTYPE_TUNNEL_IP,
3800                 RTE_PTYPE_INNER_L3_IPV6,
3801                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3802                 RTE_PTYPE_INNER_L4_TCP,
3803                 RTE_PTYPE_INNER_L4_UDP,
3804                 RTE_PTYPE_UNKNOWN
3805         };
3806
3807         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3808             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3809             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3810             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3811                 return ptypes;
3812
3813 #if defined(RTE_ARCH_X86)
3814         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3815             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3816                 return ptypes;
3817 #endif
3818         return NULL;
3819 }
3820
3821 static void
3822 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3823                      struct rte_eth_dev_info *dev_info)
3824 {
3825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827
3828         dev_info->pci_dev = pci_dev;
3829         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3830         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3831         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3832         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3833         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3834         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3835         dev_info->max_vfs = pci_dev->max_vfs;
3836         if (hw->mac.type == ixgbe_mac_82598EB)
3837                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3838         else
3839                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3840         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3841                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3842                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3843                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3844         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3845                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3846                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3847                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3848                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3849                                 DEV_TX_OFFLOAD_TCP_TSO;
3850
3851         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3852                 .rx_thresh = {
3853                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3854                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3855                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3856                 },
3857                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3858                 .rx_drop_en = 0,
3859         };
3860
3861         dev_info->default_txconf = (struct rte_eth_txconf) {
3862                 .tx_thresh = {
3863                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3864                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3865                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3866                 },
3867                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3868                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3869                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3870                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3871         };
3872
3873         dev_info->rx_desc_lim = rx_desc_lim;
3874         dev_info->tx_desc_lim = tx_desc_lim;
3875 }
3876
3877 static int
3878 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3879                    int *link_up, int wait_to_complete)
3880 {
3881         struct ixgbe_mbx_info *mbx = &hw->mbx;
3882         struct ixgbe_mac_info *mac = &hw->mac;
3883         uint32_t links_reg, in_msg;
3884         int ret_val = 0;
3885
3886         /* If we were hit with a reset drop the link */
3887         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3888                 mac->get_link_status = true;
3889
3890         if (!mac->get_link_status)
3891                 goto out;
3892
3893         /* if link status is down no point in checking to see if pf is up */
3894         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3895         if (!(links_reg & IXGBE_LINKS_UP))
3896                 goto out;
3897
3898         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3899          * before the link status is correct
3900          */
3901         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3902                 int i;
3903
3904                 for (i = 0; i < 5; i++) {
3905                         rte_delay_us(100);
3906                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3907
3908                         if (!(links_reg & IXGBE_LINKS_UP))
3909                                 goto out;
3910                 }
3911         }
3912
3913         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3914         case IXGBE_LINKS_SPEED_10G_82599:
3915                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3916                 if (hw->mac.type >= ixgbe_mac_X550) {
3917                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3918                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3919                 }
3920                 break;
3921         case IXGBE_LINKS_SPEED_1G_82599:
3922                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3923                 break;
3924         case IXGBE_LINKS_SPEED_100_82599:
3925                 *speed = IXGBE_LINK_SPEED_100_FULL;
3926                 if (hw->mac.type == ixgbe_mac_X550) {
3927                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3928                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3929                 }
3930                 break;
3931         case IXGBE_LINKS_SPEED_10_X550EM_A:
3932                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3933                 /* Since Reserved in older MAC's */
3934                 if (hw->mac.type >= ixgbe_mac_X550)
3935                         *speed = IXGBE_LINK_SPEED_10_FULL;
3936                 break;
3937         default:
3938                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3939         }
3940
3941         /* if the read failed it could just be a mailbox collision, best wait
3942          * until we are called again and don't report an error
3943          */
3944         if (mbx->ops.read(hw, &in_msg, 1, 0))
3945                 goto out;
3946
3947         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3948                 /* msg is not CTS and is NACK we must have lost CTS status */
3949                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3950                         mac->get_link_status = false;
3951                 goto out;
3952         }
3953
3954         /* the pf is talking, if we timed out in the past we reinit */
3955         if (!mbx->timeout) {
3956                 ret_val = -1;
3957                 goto out;
3958         }
3959
3960         /* if we passed all the tests above then the link is up and we no
3961          * longer need to check for link
3962          */
3963         mac->get_link_status = false;
3964
3965 out:
3966         *link_up = !mac->get_link_status;
3967         return ret_val;
3968 }
3969
3970 static void
3971 ixgbe_dev_setup_link_alarm_handler(void *param)
3972 {
3973         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975         struct ixgbe_interrupt *intr =
3976                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3977         u32 speed;
3978         bool autoneg = false;
3979
3980         speed = hw->phy.autoneg_advertised;
3981         if (!speed)
3982                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3983
3984         ixgbe_setup_link(hw, speed, true);
3985
3986         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3987 }
3988
3989 /* return 0 means link status changed, -1 means not changed */
3990 static int
3991 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3992                             int wait_to_complete, int vf)
3993 {
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct rte_eth_link link, old;
3996         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3997         struct ixgbe_interrupt *intr =
3998                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3999         int link_up;
4000         int diag;
4001         int wait = 1;
4002
4003         link.link_status = ETH_LINK_DOWN;
4004         link.link_speed = 0;
4005         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4006         link.link_autoneg = ETH_LINK_AUTONEG;
4007         memset(&old, 0, sizeof(old));
4008         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
4009
4010         hw->mac.get_link_status = true;
4011
4012         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) {
4013                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4014                 if (link.link_status == old.link_status)
4015                         return -1;
4016                 return 0;
4017         }
4018
4019         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4020         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4021                 wait = 0;
4022
4023         if (vf)
4024                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4025         else
4026                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4027
4028         if (diag != 0) {
4029                 link.link_speed = ETH_SPEED_NUM_100M;
4030                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4031                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4032                 if (link.link_status == old.link_status)
4033                         return -1;
4034                 return 0;
4035         }
4036
4037         if (link_up == 0) {
4038                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4039                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4040                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4041                         rte_eal_alarm_set(10,
4042                                 ixgbe_dev_setup_link_alarm_handler, dev);
4043                 }
4044                 if (link.link_status == old.link_status)
4045                         return -1;
4046                 return 0;
4047         }
4048
4049         link.link_status = ETH_LINK_UP;
4050         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4051
4052         switch (link_speed) {
4053         default:
4054         case IXGBE_LINK_SPEED_UNKNOWN:
4055                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4056                 link.link_speed = ETH_SPEED_NUM_100M;
4057                 break;
4058
4059         case IXGBE_LINK_SPEED_100_FULL:
4060                 link.link_speed = ETH_SPEED_NUM_100M;
4061                 break;
4062
4063         case IXGBE_LINK_SPEED_1GB_FULL:
4064                 link.link_speed = ETH_SPEED_NUM_1G;
4065                 break;
4066
4067         case IXGBE_LINK_SPEED_2_5GB_FULL:
4068                 link.link_speed = ETH_SPEED_NUM_2_5G;
4069                 break;
4070
4071         case IXGBE_LINK_SPEED_5GB_FULL:
4072                 link.link_speed = ETH_SPEED_NUM_5G;
4073                 break;
4074
4075         case IXGBE_LINK_SPEED_10GB_FULL:
4076                 link.link_speed = ETH_SPEED_NUM_10G;
4077                 break;
4078         }
4079         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4080
4081         if (link.link_status == old.link_status)
4082                 return -1;
4083
4084         return 0;
4085 }
4086
4087 static int
4088 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4089 {
4090         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4091 }
4092
4093 static int
4094 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4095 {
4096         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4097 }
4098
4099 static void
4100 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4101 {
4102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103         uint32_t fctrl;
4104
4105         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4107         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4108 }
4109
4110 static void
4111 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4112 {
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t fctrl;
4115
4116         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4117         fctrl &= (~IXGBE_FCTRL_UPE);
4118         if (dev->data->all_multicast == 1)
4119                 fctrl |= IXGBE_FCTRL_MPE;
4120         else
4121                 fctrl &= (~IXGBE_FCTRL_MPE);
4122         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4123 }
4124
4125 static void
4126 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4127 {
4128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t fctrl;
4130
4131         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4132         fctrl |= IXGBE_FCTRL_MPE;
4133         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4134 }
4135
4136 static void
4137 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4138 {
4139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         uint32_t fctrl;
4141
4142         if (dev->data->promiscuous == 1)
4143                 return; /* must remain in all_multicast mode */
4144
4145         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4146         fctrl &= (~IXGBE_FCTRL_MPE);
4147         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  * @param on
4157  *  Enable or Disable.
4158  *
4159  * @return
4160  *  - On success, zero.
4161  *  - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4165 {
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168
4169         ixgbe_dev_link_status_print(dev);
4170         if (on)
4171                 intr->mask |= IXGBE_EICR_LSC;
4172         else
4173                 intr->mask &= ~IXGBE_EICR_LSC;
4174
4175         return 0;
4176 }
4177
4178 /**
4179  * It clears the interrupt causes and enables the interrupt.
4180  * It will be called once only during nic initialized.
4181  *
4182  * @param dev
4183  *  Pointer to struct rte_eth_dev.
4184  *
4185  * @return
4186  *  - On success, zero.
4187  *  - On failure, a negative value.
4188  */
4189 static int
4190 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4191 {
4192         struct ixgbe_interrupt *intr =
4193                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4194
4195         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4196
4197         return 0;
4198 }
4199
4200 /**
4201  * It clears the interrupt causes and enables the interrupt.
4202  * It will be called once only during nic initialized.
4203  *
4204  * @param dev
4205  *  Pointer to struct rte_eth_dev.
4206  *
4207  * @return
4208  *  - On success, zero.
4209  *  - On failure, a negative value.
4210  */
4211 static int
4212 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4213 {
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216
4217         intr->mask |= IXGBE_EICR_LINKSEC;
4218
4219         return 0;
4220 }
4221
4222 /*
4223  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4224  *
4225  * @param dev
4226  *  Pointer to struct rte_eth_dev.
4227  *
4228  * @return
4229  *  - On success, zero.
4230  *  - On failure, a negative value.
4231  */
4232 static int
4233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4234 {
4235         uint32_t eicr;
4236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237         struct ixgbe_interrupt *intr =
4238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4239
4240         /* clear all cause mask */
4241         ixgbe_disable_intr(hw);
4242
4243         /* read-on-clear nic registers here */
4244         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4245         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4246
4247         intr->flags = 0;
4248
4249         /* set flag for async link update */
4250         if (eicr & IXGBE_EICR_LSC)
4251                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4252
4253         if (eicr & IXGBE_EICR_MAILBOX)
4254                 intr->flags |= IXGBE_FLAG_MAILBOX;
4255
4256         if (eicr & IXGBE_EICR_LINKSEC)
4257                 intr->flags |= IXGBE_FLAG_MACSEC;
4258
4259         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4260             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4261             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4262                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4263
4264         return 0;
4265 }
4266
4267 /**
4268  * It gets and then prints the link status.
4269  *
4270  * @param dev
4271  *  Pointer to struct rte_eth_dev.
4272  *
4273  * @return
4274  *  - On success, zero.
4275  *  - On failure, a negative value.
4276  */
4277 static void
4278 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4279 {
4280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281         struct rte_eth_link link;
4282
4283         memset(&link, 0, sizeof(link));
4284         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4285         if (link.link_status) {
4286                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4287                                         (int)(dev->data->port_id),
4288                                         (unsigned)link.link_speed,
4289                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4290                                         "full-duplex" : "half-duplex");
4291         } else {
4292                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4293                                 (int)(dev->data->port_id));
4294         }
4295         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4296                                 pci_dev->addr.domain,
4297                                 pci_dev->addr.bus,
4298                                 pci_dev->addr.devid,
4299                                 pci_dev->addr.function);
4300 }
4301
4302 /*
4303  * It executes link_update after knowing an interrupt occurred.
4304  *
4305  * @param dev
4306  *  Pointer to struct rte_eth_dev.
4307  *
4308  * @return
4309  *  - On success, zero.
4310  *  - On failure, a negative value.
4311  */
4312 static int
4313 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4314                            struct rte_intr_handle *intr_handle)
4315 {
4316         struct ixgbe_interrupt *intr =
4317                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4318         int64_t timeout;
4319         struct rte_eth_link link;
4320         struct ixgbe_hw *hw =
4321                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322
4323         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4324
4325         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4326                 ixgbe_pf_mbx_process(dev);
4327                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4328         }
4329
4330         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4331                 ixgbe_handle_lasi(hw);
4332                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4333         }
4334
4335         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4336                 /* get the link status before link update, for predicting later */
4337                 memset(&link, 0, sizeof(link));
4338                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4339
4340                 ixgbe_dev_link_update(dev, 0);
4341
4342                 /* likely to up */
4343                 if (!link.link_status)
4344                         /* handle it 1 sec later, wait it being stable */
4345                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4346                 /* likely to down */
4347                 else
4348                         /* handle it 4 sec later, wait it being stable */
4349                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4350
4351                 ixgbe_dev_link_status_print(dev);
4352                 if (rte_eal_alarm_set(timeout * 1000,
4353                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4354                         PMD_DRV_LOG(ERR, "Error setting alarm");
4355                 else {
4356                         /* remember original mask */
4357                         intr->mask_original = intr->mask;
4358                         /* only disable lsc interrupt */
4359                         intr->mask &= ~IXGBE_EIMS_LSC;
4360                 }
4361         }
4362
4363         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4364         ixgbe_enable_intr(dev);
4365         rte_intr_enable(intr_handle);
4366
4367         return 0;
4368 }
4369
4370 /**
4371  * Interrupt handler which shall be registered for alarm callback for delayed
4372  * handling specific interrupt to wait for the stable nic state. As the
4373  * NIC interrupt state is not stable for ixgbe after link is just down,
4374  * it needs to wait 4 seconds to get the stable status.
4375  *
4376  * @param handle
4377  *  Pointer to interrupt handle.
4378  * @param param
4379  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4380  *
4381  * @return
4382  *  void
4383  */
4384 static void
4385 ixgbe_dev_interrupt_delayed_handler(void *param)
4386 {
4387         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4388         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4389         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4390         struct ixgbe_interrupt *intr =
4391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4392         struct ixgbe_hw *hw =
4393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394         uint32_t eicr;
4395
4396         ixgbe_disable_intr(hw);
4397
4398         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4399         if (eicr & IXGBE_EICR_MAILBOX)
4400                 ixgbe_pf_mbx_process(dev);
4401
4402         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4403                 ixgbe_handle_lasi(hw);
4404                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4405         }
4406
4407         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4408                 ixgbe_dev_link_update(dev, 0);
4409                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4410                 ixgbe_dev_link_status_print(dev);
4411                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4412                                               NULL, NULL);
4413         }
4414
4415         if (intr->flags & IXGBE_FLAG_MACSEC) {
4416                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4417                                               NULL, NULL);
4418                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4419         }
4420
4421         /* restore original mask */
4422         intr->mask = intr->mask_original;
4423         intr->mask_original = 0;
4424
4425         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4426         ixgbe_enable_intr(dev);
4427         rte_intr_enable(intr_handle);
4428 }
4429
4430 /**
4431  * Interrupt handler triggered by NIC  for handling
4432  * specific interrupt.
4433  *
4434  * @param handle
4435  *  Pointer to interrupt handle.
4436  * @param param
4437  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4438  *
4439  * @return
4440  *  void
4441  */
4442 static void
4443 ixgbe_dev_interrupt_handler(void *param)
4444 {
4445         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4446
4447         ixgbe_dev_interrupt_get_status(dev);
4448         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4449 }
4450
4451 static int
4452 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4453 {
4454         struct ixgbe_hw *hw;
4455
4456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4458 }
4459
4460 static int
4461 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4462 {
4463         struct ixgbe_hw *hw;
4464
4465         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4467 }
4468
4469 static int
4470 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4471 {
4472         struct ixgbe_hw *hw;
4473         uint32_t mflcn_reg;
4474         uint32_t fccfg_reg;
4475         int rx_pause;
4476         int tx_pause;
4477
4478         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479
4480         fc_conf->pause_time = hw->fc.pause_time;
4481         fc_conf->high_water = hw->fc.high_water[0];
4482         fc_conf->low_water = hw->fc.low_water[0];
4483         fc_conf->send_xon = hw->fc.send_xon;
4484         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4485
4486         /*
4487          * Return rx_pause status according to actual setting of
4488          * MFLCN register.
4489          */
4490         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4491         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4492                 rx_pause = 1;
4493         else
4494                 rx_pause = 0;
4495
4496         /*
4497          * Return tx_pause status according to actual setting of
4498          * FCCFG register.
4499          */
4500         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4501         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4502                 tx_pause = 1;
4503         else
4504                 tx_pause = 0;
4505
4506         if (rx_pause && tx_pause)
4507                 fc_conf->mode = RTE_FC_FULL;
4508         else if (rx_pause)
4509                 fc_conf->mode = RTE_FC_RX_PAUSE;
4510         else if (tx_pause)
4511                 fc_conf->mode = RTE_FC_TX_PAUSE;
4512         else
4513                 fc_conf->mode = RTE_FC_NONE;
4514
4515         return 0;
4516 }
4517
4518 static int
4519 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4520 {
4521         struct ixgbe_hw *hw;
4522         int err;
4523         uint32_t rx_buf_size;
4524         uint32_t max_high_water;
4525         uint32_t mflcn;
4526         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4527                 ixgbe_fc_none,
4528                 ixgbe_fc_rx_pause,
4529                 ixgbe_fc_tx_pause,
4530                 ixgbe_fc_full
4531         };
4532
4533         PMD_INIT_FUNC_TRACE();
4534
4535         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4536         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4537         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4538
4539         /*
4540          * At least reserve one Ethernet frame for watermark
4541          * high_water/low_water in kilo bytes for ixgbe
4542          */
4543         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4544         if ((fc_conf->high_water > max_high_water) ||
4545                 (fc_conf->high_water < fc_conf->low_water)) {
4546                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4547                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4548                 return -EINVAL;
4549         }
4550
4551         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4552         hw->fc.pause_time     = fc_conf->pause_time;
4553         hw->fc.high_water[0]  = fc_conf->high_water;
4554         hw->fc.low_water[0]   = fc_conf->low_water;
4555         hw->fc.send_xon       = fc_conf->send_xon;
4556         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4557
4558         err = ixgbe_fc_enable(hw);
4559
4560         /* Not negotiated is not an error case */
4561         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4562
4563                 /* check if we want to forward MAC frames - driver doesn't have native
4564                  * capability to do that, so we'll write the registers ourselves */
4565
4566                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4567
4568                 /* set or clear MFLCN.PMCF bit depending on configuration */
4569                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4570                         mflcn |= IXGBE_MFLCN_PMCF;
4571                 else
4572                         mflcn &= ~IXGBE_MFLCN_PMCF;
4573
4574                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4575                 IXGBE_WRITE_FLUSH(hw);
4576
4577                 return 0;
4578         }
4579
4580         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4581         return -EIO;
4582 }
4583
4584 /**
4585  *  ixgbe_pfc_enable_generic - Enable flow control
4586  *  @hw: pointer to hardware structure
4587  *  @tc_num: traffic class number
4588  *  Enable flow control according to the current settings.
4589  */
4590 static int
4591 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4592 {
4593         int ret_val = 0;
4594         uint32_t mflcn_reg, fccfg_reg;
4595         uint32_t reg;
4596         uint32_t fcrtl, fcrth;
4597         uint8_t i;
4598         uint8_t nb_rx_en;
4599
4600         /* Validate the water mark configuration */
4601         if (!hw->fc.pause_time) {
4602                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4603                 goto out;
4604         }
4605
4606         /* Low water mark of zero causes XOFF floods */
4607         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4608                  /* High/Low water can not be 0 */
4609                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4610                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4611                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4612                         goto out;
4613                 }
4614
4615                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4616                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4617                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4618                         goto out;
4619                 }
4620         }
4621         /* Negotiate the fc mode to use */
4622         ixgbe_fc_autoneg(hw);
4623
4624         /* Disable any previous flow control settings */
4625         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4626         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4627
4628         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4629         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4630
4631         switch (hw->fc.current_mode) {
4632         case ixgbe_fc_none:
4633                 /*
4634                  * If the count of enabled RX Priority Flow control >1,
4635                  * and the TX pause can not be disabled
4636                  */
4637                 nb_rx_en = 0;
4638                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4639                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4640                         if (reg & IXGBE_FCRTH_FCEN)
4641                                 nb_rx_en++;
4642                 }
4643                 if (nb_rx_en > 1)
4644                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4645                 break;
4646         case ixgbe_fc_rx_pause:
4647                 /*
4648                  * Rx Flow control is enabled and Tx Flow control is
4649                  * disabled by software override. Since there really
4650                  * isn't a way to advertise that we are capable of RX
4651                  * Pause ONLY, we will advertise that we support both
4652                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4653                  * disable the adapter's ability to send PAUSE frames.
4654                  */
4655                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4656                 /*
4657                  * If the count of enabled RX Priority Flow control >1,
4658                  * and the TX pause can not be disabled
4659                  */
4660                 nb_rx_en = 0;
4661                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4662                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4663                         if (reg & IXGBE_FCRTH_FCEN)
4664                                 nb_rx_en++;
4665                 }
4666                 if (nb_rx_en > 1)
4667                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4668                 break;
4669         case ixgbe_fc_tx_pause:
4670                 /*
4671                  * Tx Flow control is enabled, and Rx Flow control is
4672                  * disabled by software override.
4673                  */
4674                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4675                 break;
4676         case ixgbe_fc_full:
4677                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4678                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4679                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4680                 break;
4681         default:
4682                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4683                 ret_val = IXGBE_ERR_CONFIG;
4684                 goto out;
4685         }
4686
4687         /* Set 802.3x based flow control settings. */
4688         mflcn_reg |= IXGBE_MFLCN_DPF;
4689         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4690         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4691
4692         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4693         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4694                 hw->fc.high_water[tc_num]) {
4695                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4696                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4697                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4698         } else {
4699                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4700                 /*
4701                  * In order to prevent Tx hangs when the internal Tx
4702                  * switch is enabled we must set the high water mark
4703                  * to the maximum FCRTH value.  This allows the Tx
4704                  * switch to function even under heavy Rx workloads.
4705                  */
4706                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4707         }
4708         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4709
4710         /* Configure pause time (2 TCs per register) */
4711         reg = hw->fc.pause_time * 0x00010001;
4712         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4713                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4714
4715         /* Configure flow control refresh threshold value */
4716         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4717
4718 out:
4719         return ret_val;
4720 }
4721
4722 static int
4723 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4724 {
4725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4726         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4727
4728         if (hw->mac.type != ixgbe_mac_82598EB) {
4729                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4730         }
4731         return ret_val;
4732 }
4733
4734 static int
4735 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4736 {
4737         int err;
4738         uint32_t rx_buf_size;
4739         uint32_t max_high_water;
4740         uint8_t tc_num;
4741         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4742         struct ixgbe_hw *hw =
4743                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         struct ixgbe_dcb_config *dcb_config =
4745                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4746
4747         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4748                 ixgbe_fc_none,
4749                 ixgbe_fc_rx_pause,
4750                 ixgbe_fc_tx_pause,
4751                 ixgbe_fc_full
4752         };
4753
4754         PMD_INIT_FUNC_TRACE();
4755
4756         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4757         tc_num = map[pfc_conf->priority];
4758         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4759         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4760         /*
4761          * At least reserve one Ethernet frame for watermark
4762          * high_water/low_water in kilo bytes for ixgbe
4763          */
4764         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4765         if ((pfc_conf->fc.high_water > max_high_water) ||
4766             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4767                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4768                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4769                 return -EINVAL;
4770         }
4771
4772         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4773         hw->fc.pause_time = pfc_conf->fc.pause_time;
4774         hw->fc.send_xon = pfc_conf->fc.send_xon;
4775         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4776         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4777
4778         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4779
4780         /* Not negotiated is not an error case */
4781         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4782                 return 0;
4783
4784         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4785         return -EIO;
4786 }
4787
4788 static int
4789 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4790                           struct rte_eth_rss_reta_entry64 *reta_conf,
4791                           uint16_t reta_size)
4792 {
4793         uint16_t i, sp_reta_size;
4794         uint8_t j, mask;
4795         uint32_t reta, r;
4796         uint16_t idx, shift;
4797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         uint32_t reta_reg;
4799
4800         PMD_INIT_FUNC_TRACE();
4801
4802         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4803                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4804                         "NIC.");
4805                 return -ENOTSUP;
4806         }
4807
4808         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4809         if (reta_size != sp_reta_size) {
4810                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4811                         "(%d) doesn't match the number hardware can supported "
4812                         "(%d)", reta_size, sp_reta_size);
4813                 return -EINVAL;
4814         }
4815
4816         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4817                 idx = i / RTE_RETA_GROUP_SIZE;
4818                 shift = i % RTE_RETA_GROUP_SIZE;
4819                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4820                                                 IXGBE_4_BIT_MASK);
4821                 if (!mask)
4822                         continue;
4823                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4824                 if (mask == IXGBE_4_BIT_MASK)
4825                         r = 0;
4826                 else
4827                         r = IXGBE_READ_REG(hw, reta_reg);
4828                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4829                         if (mask & (0x1 << j))
4830                                 reta |= reta_conf[idx].reta[shift + j] <<
4831                                                         (CHAR_BIT * j);
4832                         else
4833                                 reta |= r & (IXGBE_8_BIT_MASK <<
4834                                                 (CHAR_BIT * j));
4835                 }
4836                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4837         }
4838
4839         return 0;
4840 }
4841
4842 static int
4843 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4844                          struct rte_eth_rss_reta_entry64 *reta_conf,
4845                          uint16_t reta_size)
4846 {
4847         uint16_t i, sp_reta_size;
4848         uint8_t j, mask;
4849         uint32_t reta;
4850         uint16_t idx, shift;
4851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852         uint32_t reta_reg;
4853
4854         PMD_INIT_FUNC_TRACE();
4855         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4856         if (reta_size != sp_reta_size) {
4857                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4858                         "(%d) doesn't match the number hardware can supported "
4859                         "(%d)", reta_size, sp_reta_size);
4860                 return -EINVAL;
4861         }
4862
4863         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4864                 idx = i / RTE_RETA_GROUP_SIZE;
4865                 shift = i % RTE_RETA_GROUP_SIZE;
4866                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4867                                                 IXGBE_4_BIT_MASK);
4868                 if (!mask)
4869                         continue;
4870
4871                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4872                 reta = IXGBE_READ_REG(hw, reta_reg);
4873                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4874                         if (mask & (0x1 << j))
4875                                 reta_conf[idx].reta[shift + j] =
4876                                         ((reta >> (CHAR_BIT * j)) &
4877                                                 IXGBE_8_BIT_MASK);
4878                 }
4879         }
4880
4881         return 0;
4882 }
4883
4884 static int
4885 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4886                                 uint32_t index, uint32_t pool)
4887 {
4888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889         uint32_t enable_addr = 1;
4890
4891         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4892                              pool, enable_addr);
4893 }
4894
4895 static void
4896 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4897 {
4898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4899
4900         ixgbe_clear_rar(hw, index);
4901 }
4902
4903 static void
4904 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4905 {
4906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4907
4908         ixgbe_remove_rar(dev, 0);
4909
4910         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4911 }
4912
4913 static bool
4914 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4915 {
4916         if (strcmp(dev->device->driver->name, drv->driver.name))
4917                 return false;
4918
4919         return true;
4920 }
4921
4922 bool
4923 is_ixgbe_supported(struct rte_eth_dev *dev)
4924 {
4925         return is_device_supported(dev, &rte_ixgbe_pmd);
4926 }
4927
4928 static int
4929 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4930 {
4931         uint32_t hlreg0;
4932         uint32_t maxfrs;
4933         struct ixgbe_hw *hw;
4934         struct rte_eth_dev_info dev_info;
4935         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4936         struct rte_eth_dev_data *dev_data = dev->data;
4937
4938         ixgbe_dev_info_get(dev, &dev_info);
4939
4940         /* check that mtu is within the allowed range */
4941         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4942                 return -EINVAL;
4943
4944         /* If device is started, refuse mtu that requires the support of
4945          * scattered packets when this feature has not been enabled before.
4946          */
4947         if (dev_data->dev_started && !dev_data->scattered_rx &&
4948             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4949              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4950                 PMD_INIT_LOG(ERR, "Stop port first.");
4951                 return -EINVAL;
4952         }
4953
4954         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4955         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4956
4957         /* switch to jumbo mode if needed */
4958         if (frame_size > ETHER_MAX_LEN) {
4959                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4960                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4961         } else {
4962                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4963                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4964         }
4965         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4966
4967         /* update max frame size */
4968         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4969
4970         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4971         maxfrs &= 0x0000FFFF;
4972         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4973         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4974
4975         return 0;
4976 }
4977
4978 /*
4979  * Virtual Function operations
4980  */
4981 static void
4982 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4983 {
4984         PMD_INIT_FUNC_TRACE();
4985
4986         /* Clear interrupt mask to stop from interrupts being generated */
4987         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4988
4989         IXGBE_WRITE_FLUSH(hw);
4990 }
4991
4992 static void
4993 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4994 {
4995         PMD_INIT_FUNC_TRACE();
4996
4997         /* VF enable interrupt autoclean */
4998         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4999         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5000         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5001
5002         IXGBE_WRITE_FLUSH(hw);
5003 }
5004
5005 static int
5006 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5007 {
5008         struct rte_eth_conf *conf = &dev->data->dev_conf;
5009         struct ixgbe_adapter *adapter =
5010                         (struct ixgbe_adapter *)dev->data->dev_private;
5011
5012         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5013                      dev->data->port_id);
5014
5015         /*
5016          * VF has no ability to enable/disable HW CRC
5017          * Keep the persistent behavior the same as Host PF
5018          */
5019 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5020         if (!conf->rxmode.hw_strip_crc) {
5021                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5022                 conf->rxmode.hw_strip_crc = 1;
5023         }
5024 #else
5025         if (conf->rxmode.hw_strip_crc) {
5026                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5027                 conf->rxmode.hw_strip_crc = 0;
5028         }
5029 #endif
5030
5031         /*
5032          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5033          * allocation or vector Rx preconditions we will reset it.
5034          */
5035         adapter->rx_bulk_alloc_allowed = true;
5036         adapter->rx_vec_allowed = true;
5037
5038         return 0;
5039 }
5040
5041 static int
5042 ixgbevf_dev_start(struct rte_eth_dev *dev)
5043 {
5044         struct ixgbe_hw *hw =
5045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         uint32_t intr_vector = 0;
5047         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5048         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5049
5050         int err, mask = 0;
5051
5052         PMD_INIT_FUNC_TRACE();
5053
5054         /* Stop the link setup handler before resetting the HW. */
5055         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5056
5057         err = hw->mac.ops.reset_hw(hw);
5058         if (err) {
5059                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5060                 return err;
5061         }
5062         hw->mac.get_link_status = true;
5063
5064         /* negotiate mailbox API version to use with the PF. */
5065         ixgbevf_negotiate_api(hw);
5066
5067         ixgbevf_dev_tx_init(dev);
5068
5069         /* This can fail when allocating mbufs for descriptor rings */
5070         err = ixgbevf_dev_rx_init(dev);
5071         if (err) {
5072                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5073                 ixgbe_dev_clear_queues(dev);
5074                 return err;
5075         }
5076
5077         /* Set vfta */
5078         ixgbevf_set_vfta_all(dev, 1);
5079
5080         /* Set HW strip */
5081         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5082                 ETH_VLAN_EXTEND_MASK;
5083         err = ixgbevf_vlan_offload_set(dev, mask);
5084         if (err) {
5085                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5086                 ixgbe_dev_clear_queues(dev);
5087                 return err;
5088         }
5089
5090         ixgbevf_dev_rxtx_start(dev);
5091
5092         /* check and configure queue intr-vector mapping */
5093         if (rte_intr_cap_multiple(intr_handle) &&
5094             dev->data->dev_conf.intr_conf.rxq) {
5095                 /* According to datasheet, only vector 0/1/2 can be used,
5096                  * now only one vector is used for Rx queue
5097                  */
5098                 intr_vector = 1;
5099                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5100                         return -1;
5101         }
5102
5103         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5104                 intr_handle->intr_vec =
5105                         rte_zmalloc("intr_vec",
5106                                     dev->data->nb_rx_queues * sizeof(int), 0);
5107                 if (intr_handle->intr_vec == NULL) {
5108                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5109                                      " intr_vec", dev->data->nb_rx_queues);
5110                         return -ENOMEM;
5111                 }
5112         }
5113         ixgbevf_configure_msix(dev);
5114
5115         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5116          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5117          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5118          * is not cleared, it will fail when following rte_intr_enable( ) tries
5119          * to map Rx queue interrupt to other VFIO vectors.
5120          * So clear uio/vfio intr/evevnfd first to avoid failure.
5121          */
5122         rte_intr_disable(intr_handle);
5123
5124         rte_intr_enable(intr_handle);
5125
5126         /* Re-enable interrupt for VF */
5127         ixgbevf_intr_enable(hw);
5128
5129         /*
5130          * Update link status right before return, because it may
5131          * start link configuration process in a separate thread.
5132          */
5133         ixgbevf_dev_link_update(dev, 0);
5134
5135         return 0;
5136 }
5137
5138 static void
5139 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5140 {
5141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5143         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5144
5145         PMD_INIT_FUNC_TRACE();
5146
5147         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5148
5149         ixgbevf_intr_disable(hw);
5150
5151         hw->adapter_stopped = 1;
5152         ixgbe_stop_adapter(hw);
5153
5154         /*
5155           * Clear what we set, but we still keep shadow_vfta to
5156           * restore after device starts
5157           */
5158         ixgbevf_set_vfta_all(dev, 0);
5159
5160         /* Clear stored conf */
5161         dev->data->scattered_rx = 0;
5162
5163         ixgbe_dev_clear_queues(dev);
5164
5165         /* Clean datapath event and queue/vec mapping */
5166         rte_intr_efd_disable(intr_handle);
5167         if (intr_handle->intr_vec != NULL) {
5168                 rte_free(intr_handle->intr_vec);
5169                 intr_handle->intr_vec = NULL;
5170         }
5171 }
5172
5173 static void
5174 ixgbevf_dev_close(struct rte_eth_dev *dev)
5175 {
5176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177
5178         PMD_INIT_FUNC_TRACE();
5179
5180         ixgbe_reset_hw(hw);
5181
5182         ixgbevf_dev_stop(dev);
5183
5184         ixgbe_dev_free_queues(dev);
5185
5186         /**
5187          * Remove the VF MAC address ro ensure
5188          * that the VF traffic goes to the PF
5189          * after stop, close and detach of the VF
5190          **/
5191         ixgbevf_remove_mac_addr(dev, 0);
5192 }
5193
5194 /*
5195  * Reset VF device
5196  */
5197 static int
5198 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5199 {
5200         int ret;
5201
5202         ret = eth_ixgbevf_dev_uninit(dev);
5203         if (ret)
5204                 return ret;
5205
5206         ret = eth_ixgbevf_dev_init(dev);
5207
5208         return ret;
5209 }
5210
5211 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5212 {
5213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214         struct ixgbe_vfta *shadow_vfta =
5215                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5216         int i = 0, j = 0, vfta = 0, mask = 1;
5217
5218         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5219                 vfta = shadow_vfta->vfta[i];
5220                 if (vfta) {
5221                         mask = 1;
5222                         for (j = 0; j < 32; j++) {
5223                                 if (vfta & mask)
5224                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5225                                                        on, false);
5226                                 mask <<= 1;
5227                         }
5228                 }
5229         }
5230
5231 }
5232
5233 static int
5234 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5235 {
5236         struct ixgbe_hw *hw =
5237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         struct ixgbe_vfta *shadow_vfta =
5239                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5240         uint32_t vid_idx = 0;
5241         uint32_t vid_bit = 0;
5242         int ret = 0;
5243
5244         PMD_INIT_FUNC_TRACE();
5245
5246         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5247         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5248         if (ret) {
5249                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5250                 return ret;
5251         }
5252         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5253         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5254
5255         /* Save what we set and retore it after device reset */
5256         if (on)
5257                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5258         else
5259                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5260
5261         return 0;
5262 }
5263
5264 static void
5265 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5266 {
5267         struct ixgbe_hw *hw =
5268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         uint32_t ctrl;
5270
5271         PMD_INIT_FUNC_TRACE();
5272
5273         if (queue >= hw->mac.max_rx_queues)
5274                 return;
5275
5276         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5277         if (on)
5278                 ctrl |= IXGBE_RXDCTL_VME;
5279         else
5280                 ctrl &= ~IXGBE_RXDCTL_VME;
5281         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5282
5283         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5284 }
5285
5286 static int
5287 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5288 {
5289         struct ixgbe_hw *hw =
5290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         uint16_t i;
5292         int on = 0;
5293
5294         /* VF function only support hw strip feature, others are not support */
5295         if (mask & ETH_VLAN_STRIP_MASK) {
5296                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5297
5298                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5299                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5300         }
5301
5302         return 0;
5303 }
5304
5305 int
5306 ixgbe_vt_check(struct ixgbe_hw *hw)
5307 {
5308         uint32_t reg_val;
5309
5310         /* if Virtualization Technology is enabled */
5311         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5312         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5313                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5314                 return -1;
5315         }
5316
5317         return 0;
5318 }
5319
5320 static uint32_t
5321 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5322 {
5323         uint32_t vector = 0;
5324
5325         switch (hw->mac.mc_filter_type) {
5326         case 0:   /* use bits [47:36] of the address */
5327                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5328                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5329                 break;
5330         case 1:   /* use bits [46:35] of the address */
5331                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5332                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5333                 break;
5334         case 2:   /* use bits [45:34] of the address */
5335                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5336                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5337                 break;
5338         case 3:   /* use bits [43:32] of the address */
5339                 vector = ((uc_addr->addr_bytes[4]) |
5340                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5341                 break;
5342         default:  /* Invalid mc_filter_type */
5343                 break;
5344         }
5345
5346         /* vector can only be 12-bits or boundary will be exceeded */
5347         vector &= 0xFFF;
5348         return vector;
5349 }
5350
5351 static int
5352 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5353                         uint8_t on)
5354 {
5355         uint32_t vector;
5356         uint32_t uta_idx;
5357         uint32_t reg_val;
5358         uint32_t uta_shift;
5359         uint32_t rc;
5360         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5361         const uint32_t ixgbe_uta_bit_shift = 5;
5362         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5363         const uint32_t bit1 = 0x1;
5364
5365         struct ixgbe_hw *hw =
5366                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         struct ixgbe_uta_info *uta_info =
5368                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5369
5370         /* The UTA table only exists on 82599 hardware and newer */
5371         if (hw->mac.type < ixgbe_mac_82599EB)
5372                 return -ENOTSUP;
5373
5374         vector = ixgbe_uta_vector(hw, mac_addr);
5375         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5376         uta_shift = vector & ixgbe_uta_bit_mask;
5377
5378         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5379         if (rc == on)
5380                 return 0;
5381
5382         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5383         if (on) {
5384                 uta_info->uta_in_use++;
5385                 reg_val |= (bit1 << uta_shift);
5386                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5387         } else {
5388                 uta_info->uta_in_use--;
5389                 reg_val &= ~(bit1 << uta_shift);
5390                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5391         }
5392
5393         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5394
5395         if (uta_info->uta_in_use > 0)
5396                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5397                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5398         else
5399                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5400
5401         return 0;
5402 }
5403
5404 static int
5405 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5406 {
5407         int i;
5408         struct ixgbe_hw *hw =
5409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410         struct ixgbe_uta_info *uta_info =
5411                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5412
5413         /* The UTA table only exists on 82599 hardware and newer */
5414         if (hw->mac.type < ixgbe_mac_82599EB)
5415                 return -ENOTSUP;
5416
5417         if (on) {
5418                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5419                         uta_info->uta_shadow[i] = ~0;
5420                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5421                 }
5422         } else {
5423                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5424                         uta_info->uta_shadow[i] = 0;
5425                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5426                 }
5427         }
5428         return 0;
5429
5430 }
5431
5432 uint32_t
5433 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5434 {
5435         uint32_t new_val = orig_val;
5436
5437         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5438                 new_val |= IXGBE_VMOLR_AUPE;
5439         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5440                 new_val |= IXGBE_VMOLR_ROMPE;
5441         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5442                 new_val |= IXGBE_VMOLR_ROPE;
5443         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5444                 new_val |= IXGBE_VMOLR_BAM;
5445         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5446                 new_val |= IXGBE_VMOLR_MPE;
5447
5448         return new_val;
5449 }
5450
5451 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5452 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5453 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5454 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5455 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5456         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5457         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5458
5459 static int
5460 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5461                       struct rte_eth_mirror_conf *mirror_conf,
5462                       uint8_t rule_id, uint8_t on)
5463 {
5464         uint32_t mr_ctl, vlvf;
5465         uint32_t mp_lsb = 0;
5466         uint32_t mv_msb = 0;
5467         uint32_t mv_lsb = 0;
5468         uint32_t mp_msb = 0;
5469         uint8_t i = 0;
5470         int reg_index = 0;
5471         uint64_t vlan_mask = 0;
5472
5473         const uint8_t pool_mask_offset = 32;
5474         const uint8_t vlan_mask_offset = 32;
5475         const uint8_t dst_pool_offset = 8;
5476         const uint8_t rule_mr_offset  = 4;
5477         const uint8_t mirror_rule_mask = 0x0F;
5478
5479         struct ixgbe_mirror_info *mr_info =
5480                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5481         struct ixgbe_hw *hw =
5482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483         uint8_t mirror_type = 0;
5484
5485         if (ixgbe_vt_check(hw) < 0)
5486                 return -ENOTSUP;
5487
5488         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5489                 return -EINVAL;
5490
5491         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5492                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5493                             mirror_conf->rule_type);
5494                 return -EINVAL;
5495         }
5496
5497         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5498                 mirror_type |= IXGBE_MRCTL_VLME;
5499                 /* Check if vlan id is valid and find conresponding VLAN ID
5500                  * index in VLVF
5501                  */
5502                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5503                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5504                                 /* search vlan id related pool vlan filter
5505                                  * index
5506                                  */
5507                                 reg_index = ixgbe_find_vlvf_slot(
5508                                                 hw,
5509                                                 mirror_conf->vlan.vlan_id[i],
5510                                                 false);
5511                                 if (reg_index < 0)
5512                                         return -EINVAL;
5513                                 vlvf = IXGBE_READ_REG(hw,
5514                                                       IXGBE_VLVF(reg_index));
5515                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5516                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5517                                       mirror_conf->vlan.vlan_id[i]))
5518                                         vlan_mask |= (1ULL << reg_index);
5519                                 else
5520                                         return -EINVAL;
5521                         }
5522                 }
5523
5524                 if (on) {
5525                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5526                         mv_msb = vlan_mask >> vlan_mask_offset;
5527
5528                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5529                                                 mirror_conf->vlan.vlan_mask;
5530                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5531                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5532                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5533                                                 mirror_conf->vlan.vlan_id[i];
5534                         }
5535                 } else {
5536                         mv_lsb = 0;
5537                         mv_msb = 0;
5538                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5539                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5540                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5541                 }
5542         }
5543
5544         /**
5545          * if enable pool mirror, write related pool mask register,if disable
5546          * pool mirror, clear PFMRVM register
5547          */
5548         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5549                 mirror_type |= IXGBE_MRCTL_VPME;
5550                 if (on) {
5551                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5552                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5553                         mr_info->mr_conf[rule_id].pool_mask =
5554                                         mirror_conf->pool_mask;
5555
5556                 } else {
5557                         mp_lsb = 0;
5558                         mp_msb = 0;
5559                         mr_info->mr_conf[rule_id].pool_mask = 0;
5560                 }
5561         }
5562         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5563                 mirror_type |= IXGBE_MRCTL_UPME;
5564         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5565                 mirror_type |= IXGBE_MRCTL_DPME;
5566
5567         /* read  mirror control register and recalculate it */
5568         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5569
5570         if (on) {
5571                 mr_ctl |= mirror_type;
5572                 mr_ctl &= mirror_rule_mask;
5573                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5574         } else {
5575                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5576         }
5577
5578         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5579         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5580
5581         /* write mirrror control  register */
5582         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5583
5584         /* write pool mirrror control  register */
5585         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5586                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5587                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5588                                 mp_msb);
5589         }
5590         /* write VLAN mirrror control  register */
5591         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5592                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5593                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5594                                 mv_msb);
5595         }
5596
5597         return 0;
5598 }
5599
5600 static int
5601 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5602 {
5603         int mr_ctl = 0;
5604         uint32_t lsb_val = 0;
5605         uint32_t msb_val = 0;
5606         const uint8_t rule_mr_offset = 4;
5607
5608         struct ixgbe_hw *hw =
5609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5610         struct ixgbe_mirror_info *mr_info =
5611                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5612
5613         if (ixgbe_vt_check(hw) < 0)
5614                 return -ENOTSUP;
5615
5616         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5617                 return -EINVAL;
5618
5619         memset(&mr_info->mr_conf[rule_id], 0,
5620                sizeof(struct rte_eth_mirror_conf));
5621
5622         /* clear PFVMCTL register */
5623         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5624
5625         /* clear pool mask register */
5626         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5627         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5628
5629         /* clear vlan mask register */
5630         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5631         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5632
5633         return 0;
5634 }
5635
5636 static int
5637 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5638 {
5639         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5640         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5641         uint32_t mask;
5642         struct ixgbe_hw *hw =
5643                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644         uint32_t vec = IXGBE_MISC_VEC_ID;
5645
5646         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5647         if (rte_intr_allow_others(intr_handle))
5648                 vec = IXGBE_RX_VEC_START;
5649         mask |= (1 << vec);
5650         RTE_SET_USED(queue_id);
5651         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5652
5653         rte_intr_enable(intr_handle);
5654
5655         return 0;
5656 }
5657
5658 static int
5659 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5660 {
5661         uint32_t mask;
5662         struct ixgbe_hw *hw =
5663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5664         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5665         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5666         uint32_t vec = IXGBE_MISC_VEC_ID;
5667
5668         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5669         if (rte_intr_allow_others(intr_handle))
5670                 vec = IXGBE_RX_VEC_START;
5671         mask &= ~(1 << vec);
5672         RTE_SET_USED(queue_id);
5673         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5674
5675         return 0;
5676 }
5677
5678 static int
5679 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5680 {
5681         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5682         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5683         uint32_t mask;
5684         struct ixgbe_hw *hw =
5685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686         struct ixgbe_interrupt *intr =
5687                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5688
5689         if (queue_id < 16) {
5690                 ixgbe_disable_intr(hw);
5691                 intr->mask |= (1 << queue_id);
5692                 ixgbe_enable_intr(dev);
5693         } else if (queue_id < 32) {
5694                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5695                 mask &= (1 << queue_id);
5696                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5697         } else if (queue_id < 64) {
5698                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5699                 mask &= (1 << (queue_id - 32));
5700                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5701         }
5702         rte_intr_enable(intr_handle);
5703
5704         return 0;
5705 }
5706
5707 static int
5708 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5709 {
5710         uint32_t mask;
5711         struct ixgbe_hw *hw =
5712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713         struct ixgbe_interrupt *intr =
5714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5715
5716         if (queue_id < 16) {
5717                 ixgbe_disable_intr(hw);
5718                 intr->mask &= ~(1 << queue_id);
5719                 ixgbe_enable_intr(dev);
5720         } else if (queue_id < 32) {
5721                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5722                 mask &= ~(1 << queue_id);
5723                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5724         } else if (queue_id < 64) {
5725                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5726                 mask &= ~(1 << (queue_id - 32));
5727                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5728         }
5729
5730         return 0;
5731 }
5732
5733 static void
5734 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5735                      uint8_t queue, uint8_t msix_vector)
5736 {
5737         uint32_t tmp, idx;
5738
5739         if (direction == -1) {
5740                 /* other causes */
5741                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5742                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5743                 tmp &= ~0xFF;
5744                 tmp |= msix_vector;
5745                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5746         } else {
5747                 /* rx or tx cause */
5748                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5749                 idx = ((16 * (queue & 1)) + (8 * direction));
5750                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5751                 tmp &= ~(0xFF << idx);
5752                 tmp |= (msix_vector << idx);
5753                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5754         }
5755 }
5756
5757 /**
5758  * set the IVAR registers, mapping interrupt causes to vectors
5759  * @param hw
5760  *  pointer to ixgbe_hw struct
5761  * @direction
5762  *  0 for Rx, 1 for Tx, -1 for other causes
5763  * @queue
5764  *  queue to map the corresponding interrupt to
5765  * @msix_vector
5766  *  the vector to map to the corresponding queue
5767  */
5768 static void
5769 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5770                    uint8_t queue, uint8_t msix_vector)
5771 {
5772         uint32_t tmp, idx;
5773
5774         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5775         if (hw->mac.type == ixgbe_mac_82598EB) {
5776                 if (direction == -1)
5777                         direction = 0;
5778                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5779                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5780                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5781                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5782                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5783         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5784                         (hw->mac.type == ixgbe_mac_X540) ||
5785                         (hw->mac.type == ixgbe_mac_X550)) {
5786                 if (direction == -1) {
5787                         /* other causes */
5788                         idx = ((queue & 1) * 8);
5789                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5790                         tmp &= ~(0xFF << idx);
5791                         tmp |= (msix_vector << idx);
5792                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5793                 } else {
5794                         /* rx or tx causes */
5795                         idx = ((16 * (queue & 1)) + (8 * direction));
5796                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5797                         tmp &= ~(0xFF << idx);
5798                         tmp |= (msix_vector << idx);
5799                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5800                 }
5801         }
5802 }
5803
5804 static void
5805 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5806 {
5807         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5808         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5809         struct ixgbe_hw *hw =
5810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811         uint32_t q_idx;
5812         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5813         uint32_t base = IXGBE_MISC_VEC_ID;
5814
5815         /* Configure VF other cause ivar */
5816         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5817
5818         /* won't configure msix register if no mapping is done
5819          * between intr vector and event fd.
5820          */
5821         if (!rte_intr_dp_is_en(intr_handle))
5822                 return;
5823
5824         if (rte_intr_allow_others(intr_handle)) {
5825                 base = IXGBE_RX_VEC_START;
5826                 vector_idx = IXGBE_RX_VEC_START;
5827         }
5828
5829         /* Configure all RX queues of VF */
5830         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5831                 /* Force all queue use vector 0,
5832                  * as IXGBE_VF_MAXMSIVECOTR = 1
5833                  */
5834                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5835                 intr_handle->intr_vec[q_idx] = vector_idx;
5836                 if (vector_idx < base + intr_handle->nb_efd - 1)
5837                         vector_idx++;
5838         }
5839 }
5840
5841 /**
5842  * Sets up the hardware to properly generate MSI-X interrupts
5843  * @hw
5844  *  board private structure
5845  */
5846 static void
5847 ixgbe_configure_msix(struct rte_eth_dev *dev)
5848 {
5849         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5850         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5851         struct ixgbe_hw *hw =
5852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5853         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5854         uint32_t vec = IXGBE_MISC_VEC_ID;
5855         uint32_t mask;
5856         uint32_t gpie;
5857
5858         /* won't configure msix register if no mapping is done
5859          * between intr vector and event fd
5860          * but if misx has been enabled already, need to configure
5861          * auto clean, auto mask and throttling.
5862          */
5863         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5864         if (!rte_intr_dp_is_en(intr_handle) &&
5865             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5866                 return;
5867
5868         if (rte_intr_allow_others(intr_handle))
5869                 vec = base = IXGBE_RX_VEC_START;
5870
5871         /* setup GPIE for MSI-x mode */
5872         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5873         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5874                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5875         /* auto clearing and auto setting corresponding bits in EIMS
5876          * when MSI-X interrupt is triggered
5877          */
5878         if (hw->mac.type == ixgbe_mac_82598EB) {
5879                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5880         } else {
5881                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5882                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5883         }
5884         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5885
5886         /* Populate the IVAR table and set the ITR values to the
5887          * corresponding register.
5888          */
5889         if (rte_intr_dp_is_en(intr_handle)) {
5890                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5891                         queue_id++) {
5892                         /* by default, 1:1 mapping */
5893                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5894                         intr_handle->intr_vec[queue_id] = vec;
5895                         if (vec < base + intr_handle->nb_efd - 1)
5896                                 vec++;
5897                 }
5898
5899                 switch (hw->mac.type) {
5900                 case ixgbe_mac_82598EB:
5901                         ixgbe_set_ivar_map(hw, -1,
5902                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5903                                            IXGBE_MISC_VEC_ID);
5904                         break;
5905                 case ixgbe_mac_82599EB:
5906                 case ixgbe_mac_X540:
5907                 case ixgbe_mac_X550:
5908                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5909                         break;
5910                 default:
5911                         break;
5912                 }
5913         }
5914         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5915                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5916
5917         /* set up to autoclear timer, and the vectors */
5918         mask = IXGBE_EIMS_ENABLE_MASK;
5919         mask &= ~(IXGBE_EIMS_OTHER |
5920                   IXGBE_EIMS_MAILBOX |
5921                   IXGBE_EIMS_LSC);
5922
5923         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5924 }
5925
5926 int
5927 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5928                            uint16_t queue_idx, uint16_t tx_rate)
5929 {
5930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5931         uint32_t rf_dec, rf_int;
5932         uint32_t bcnrc_val;
5933         uint16_t link_speed = dev->data->dev_link.link_speed;
5934
5935         if (queue_idx >= hw->mac.max_tx_queues)
5936                 return -EINVAL;
5937
5938         if (tx_rate != 0) {
5939                 /* Calculate the rate factor values to set */
5940                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5941                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5942                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5943
5944                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5945                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5946                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5947                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5948         } else {
5949                 bcnrc_val = 0;
5950         }
5951
5952         /*
5953          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5954          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5955          * set as 0x4.
5956          */
5957         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5958                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5959                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5960                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5961                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5962         else
5963                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5964                         IXGBE_MMW_SIZE_DEFAULT);
5965
5966         /* Set RTTBCNRC of queue X */
5967         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5968         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5969         IXGBE_WRITE_FLUSH(hw);
5970
5971         return 0;
5972 }
5973
5974 static int
5975 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5976                      __attribute__((unused)) uint32_t index,
5977                      __attribute__((unused)) uint32_t pool)
5978 {
5979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980         int diag;
5981
5982         /*
5983          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5984          * operation. Trap this case to avoid exhausting the [very limited]
5985          * set of PF resources used to store VF MAC addresses.
5986          */
5987         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5988                 return -1;
5989         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5990         if (diag != 0)
5991                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5992                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5993                             mac_addr->addr_bytes[0],
5994                             mac_addr->addr_bytes[1],
5995                             mac_addr->addr_bytes[2],
5996                             mac_addr->addr_bytes[3],
5997                             mac_addr->addr_bytes[4],
5998                             mac_addr->addr_bytes[5],
5999                             diag);
6000         return diag;
6001 }
6002
6003 static void
6004 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6005 {
6006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6008         struct ether_addr *mac_addr;
6009         uint32_t i;
6010         int diag;
6011
6012         /*
6013          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6014          * not support the deletion of a given MAC address.
6015          * Instead, it imposes to delete all MAC addresses, then to add again
6016          * all MAC addresses with the exception of the one to be deleted.
6017          */
6018         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6019
6020         /*
6021          * Add again all MAC addresses, with the exception of the deleted one
6022          * and of the permanent MAC address.
6023          */
6024         for (i = 0, mac_addr = dev->data->mac_addrs;
6025              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6026                 /* Skip the deleted MAC address */
6027                 if (i == index)
6028                         continue;
6029                 /* Skip NULL MAC addresses */
6030                 if (is_zero_ether_addr(mac_addr))
6031                         continue;
6032                 /* Skip the permanent MAC address */
6033                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6034                         continue;
6035                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6036                 if (diag != 0)
6037                         PMD_DRV_LOG(ERR,
6038                                     "Adding again MAC address "
6039                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6040                                     "diag=%d",
6041                                     mac_addr->addr_bytes[0],
6042                                     mac_addr->addr_bytes[1],
6043                                     mac_addr->addr_bytes[2],
6044                                     mac_addr->addr_bytes[3],
6045                                     mac_addr->addr_bytes[4],
6046                                     mac_addr->addr_bytes[5],
6047                                     diag);
6048         }
6049 }
6050
6051 static void
6052 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6053 {
6054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055
6056         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6057 }
6058
6059 int
6060 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6061                         struct rte_eth_syn_filter *filter,
6062                         bool add)
6063 {
6064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6065         struct ixgbe_filter_info *filter_info =
6066                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6067         uint32_t syn_info;
6068         uint32_t synqf;
6069
6070         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6071                 return -EINVAL;
6072
6073         syn_info = filter_info->syn_info;
6074
6075         if (add) {
6076                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6077                         return -EINVAL;
6078                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6079                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6080
6081                 if (filter->hig_pri)
6082                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6083                 else
6084                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6085         } else {
6086                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6087                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6088                         return -ENOENT;
6089                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6090         }
6091
6092         filter_info->syn_info = synqf;
6093         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6094         IXGBE_WRITE_FLUSH(hw);
6095         return 0;
6096 }
6097
6098 static int
6099 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6100                         struct rte_eth_syn_filter *filter)
6101 {
6102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6104
6105         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6106                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6107                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6108                 return 0;
6109         }
6110         return -ENOENT;
6111 }
6112
6113 static int
6114 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6115                         enum rte_filter_op filter_op,
6116                         void *arg)
6117 {
6118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6119         int ret;
6120
6121         MAC_TYPE_FILTER_SUP(hw->mac.type);
6122
6123         if (filter_op == RTE_ETH_FILTER_NOP)
6124                 return 0;
6125
6126         if (arg == NULL) {
6127                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6128                             filter_op);
6129                 return -EINVAL;
6130         }
6131
6132         switch (filter_op) {
6133         case RTE_ETH_FILTER_ADD:
6134                 ret = ixgbe_syn_filter_set(dev,
6135                                 (struct rte_eth_syn_filter *)arg,
6136                                 TRUE);
6137                 break;
6138         case RTE_ETH_FILTER_DELETE:
6139                 ret = ixgbe_syn_filter_set(dev,
6140                                 (struct rte_eth_syn_filter *)arg,
6141                                 FALSE);
6142                 break;
6143         case RTE_ETH_FILTER_GET:
6144                 ret = ixgbe_syn_filter_get(dev,
6145                                 (struct rte_eth_syn_filter *)arg);
6146                 break;
6147         default:
6148                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6149                 ret = -EINVAL;
6150                 break;
6151         }
6152
6153         return ret;
6154 }
6155
6156
6157 static inline enum ixgbe_5tuple_protocol
6158 convert_protocol_type(uint8_t protocol_value)
6159 {
6160         if (protocol_value == IPPROTO_TCP)
6161                 return IXGBE_FILTER_PROTOCOL_TCP;
6162         else if (protocol_value == IPPROTO_UDP)
6163                 return IXGBE_FILTER_PROTOCOL_UDP;
6164         else if (protocol_value == IPPROTO_SCTP)
6165                 return IXGBE_FILTER_PROTOCOL_SCTP;
6166         else
6167                 return IXGBE_FILTER_PROTOCOL_NONE;
6168 }
6169
6170 /* inject a 5-tuple filter to HW */
6171 static inline void
6172 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6173                            struct ixgbe_5tuple_filter *filter)
6174 {
6175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176         int i;
6177         uint32_t ftqf, sdpqf;
6178         uint32_t l34timir = 0;
6179         uint8_t mask = 0xff;
6180
6181         i = filter->index;
6182
6183         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6184                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6185         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6186
6187         ftqf = (uint32_t)(filter->filter_info.proto &
6188                 IXGBE_FTQF_PROTOCOL_MASK);
6189         ftqf |= (uint32_t)((filter->filter_info.priority &
6190                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6191         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6192                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6193         if (filter->filter_info.dst_ip_mask == 0)
6194                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6195         if (filter->filter_info.src_port_mask == 0)
6196                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6197         if (filter->filter_info.dst_port_mask == 0)
6198                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6199         if (filter->filter_info.proto_mask == 0)
6200                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6201         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6202         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6203         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6204
6205         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6206         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6207         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6208         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6209
6210         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6211         l34timir |= (uint32_t)(filter->queue <<
6212                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6213         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6214 }
6215
6216 /*
6217  * add a 5tuple filter
6218  *
6219  * @param
6220  * dev: Pointer to struct rte_eth_dev.
6221  * index: the index the filter allocates.
6222  * filter: ponter to the filter that will be added.
6223  * rx_queue: the queue id the filter assigned to.
6224  *
6225  * @return
6226  *    - On success, zero.
6227  *    - On failure, a negative value.
6228  */
6229 static int
6230 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6231                         struct ixgbe_5tuple_filter *filter)
6232 {
6233         struct ixgbe_filter_info *filter_info =
6234                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6235         int i, idx, shift;
6236
6237         /*
6238          * look for an unused 5tuple filter index,
6239          * and insert the filter to list.
6240          */
6241         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6242                 idx = i / (sizeof(uint32_t) * NBBY);
6243                 shift = i % (sizeof(uint32_t) * NBBY);
6244                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6245                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6246                         filter->index = i;
6247                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6248                                           filter,
6249                                           entries);
6250                         break;
6251                 }
6252         }
6253         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6254                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6255                 return -ENOSYS;
6256         }
6257
6258         ixgbe_inject_5tuple_filter(dev, filter);
6259
6260         return 0;
6261 }
6262
6263 /*
6264  * remove a 5tuple filter
6265  *
6266  * @param
6267  * dev: Pointer to struct rte_eth_dev.
6268  * filter: the pointer of the filter will be removed.
6269  */
6270 static void
6271 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6272                         struct ixgbe_5tuple_filter *filter)
6273 {
6274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6275         struct ixgbe_filter_info *filter_info =
6276                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6277         uint16_t index = filter->index;
6278
6279         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6280                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6281         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6282         rte_free(filter);
6283
6284         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6285         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6286         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6287         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6288         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6289 }
6290
6291 static int
6292 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6293 {
6294         struct ixgbe_hw *hw;
6295         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6296         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6297
6298         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6299
6300         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6301                 return -EINVAL;
6302
6303         /* refuse mtu that requires the support of scattered packets when this
6304          * feature has not been enabled before.
6305          */
6306         if (!rx_conf->enable_scatter &&
6307             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6308              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6309                 return -EINVAL;
6310
6311         /*
6312          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6313          * request of the version 2.0 of the mailbox API.
6314          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6315          * of the mailbox API.
6316          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6317          * prior to 3.11.33 which contains the following change:
6318          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6319          */
6320         ixgbevf_rlpml_set_vf(hw, max_frame);
6321
6322         /* update max frame size */
6323         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6324         return 0;
6325 }
6326
6327 static inline struct ixgbe_5tuple_filter *
6328 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6329                         struct ixgbe_5tuple_filter_info *key)
6330 {
6331         struct ixgbe_5tuple_filter *it;
6332
6333         TAILQ_FOREACH(it, filter_list, entries) {
6334                 if (memcmp(key, &it->filter_info,
6335                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6336                         return it;
6337                 }
6338         }
6339         return NULL;
6340 }
6341
6342 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6343 static inline int
6344 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6345                         struct ixgbe_5tuple_filter_info *filter_info)
6346 {
6347         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6348                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6349                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6350                 return -EINVAL;
6351
6352         switch (filter->dst_ip_mask) {
6353         case UINT32_MAX:
6354                 filter_info->dst_ip_mask = 0;
6355                 filter_info->dst_ip = filter->dst_ip;
6356                 break;
6357         case 0:
6358                 filter_info->dst_ip_mask = 1;
6359                 break;
6360         default:
6361                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6362                 return -EINVAL;
6363         }
6364
6365         switch (filter->src_ip_mask) {
6366         case UINT32_MAX:
6367                 filter_info->src_ip_mask = 0;
6368                 filter_info->src_ip = filter->src_ip;
6369                 break;
6370         case 0:
6371                 filter_info->src_ip_mask = 1;
6372                 break;
6373         default:
6374                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6375                 return -EINVAL;
6376         }
6377
6378         switch (filter->dst_port_mask) {
6379         case UINT16_MAX:
6380                 filter_info->dst_port_mask = 0;
6381                 filter_info->dst_port = filter->dst_port;
6382                 break;
6383         case 0:
6384                 filter_info->dst_port_mask = 1;
6385                 break;
6386         default:
6387                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6388                 return -EINVAL;
6389         }
6390
6391         switch (filter->src_port_mask) {
6392         case UINT16_MAX:
6393                 filter_info->src_port_mask = 0;
6394                 filter_info->src_port = filter->src_port;
6395                 break;
6396         case 0:
6397                 filter_info->src_port_mask = 1;
6398                 break;
6399         default:
6400                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6401                 return -EINVAL;
6402         }
6403
6404         switch (filter->proto_mask) {
6405         case UINT8_MAX:
6406                 filter_info->proto_mask = 0;
6407                 filter_info->proto =
6408                         convert_protocol_type(filter->proto);
6409                 break;
6410         case 0:
6411                 filter_info->proto_mask = 1;
6412                 break;
6413         default:
6414                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6415                 return -EINVAL;
6416         }
6417
6418         filter_info->priority = (uint8_t)filter->priority;
6419         return 0;
6420 }
6421
6422 /*
6423  * add or delete a ntuple filter
6424  *
6425  * @param
6426  * dev: Pointer to struct rte_eth_dev.
6427  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6428  * add: if true, add filter, if false, remove filter
6429  *
6430  * @return
6431  *    - On success, zero.
6432  *    - On failure, a negative value.
6433  */
6434 int
6435 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6436                         struct rte_eth_ntuple_filter *ntuple_filter,
6437                         bool add)
6438 {
6439         struct ixgbe_filter_info *filter_info =
6440                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6441         struct ixgbe_5tuple_filter_info filter_5tuple;
6442         struct ixgbe_5tuple_filter *filter;
6443         int ret;
6444
6445         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6446                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6447                 return -EINVAL;
6448         }
6449
6450         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6451         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6452         if (ret < 0)
6453                 return ret;
6454
6455         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6456                                          &filter_5tuple);
6457         if (filter != NULL && add) {
6458                 PMD_DRV_LOG(ERR, "filter exists.");
6459                 return -EEXIST;
6460         }
6461         if (filter == NULL && !add) {
6462                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6463                 return -ENOENT;
6464         }
6465
6466         if (add) {
6467                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6468                                 sizeof(struct ixgbe_5tuple_filter), 0);
6469                 if (filter == NULL)
6470                         return -ENOMEM;
6471                 rte_memcpy(&filter->filter_info,
6472                                  &filter_5tuple,
6473                                  sizeof(struct ixgbe_5tuple_filter_info));
6474                 filter->queue = ntuple_filter->queue;
6475                 ret = ixgbe_add_5tuple_filter(dev, filter);
6476                 if (ret < 0) {
6477                         rte_free(filter);
6478                         return ret;
6479                 }
6480         } else
6481                 ixgbe_remove_5tuple_filter(dev, filter);
6482
6483         return 0;
6484 }
6485
6486 /*
6487  * get a ntuple filter
6488  *
6489  * @param
6490  * dev: Pointer to struct rte_eth_dev.
6491  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6492  *
6493  * @return
6494  *    - On success, zero.
6495  *    - On failure, a negative value.
6496  */
6497 static int
6498 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6499                         struct rte_eth_ntuple_filter *ntuple_filter)
6500 {
6501         struct ixgbe_filter_info *filter_info =
6502                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6503         struct ixgbe_5tuple_filter_info filter_5tuple;
6504         struct ixgbe_5tuple_filter *filter;
6505         int ret;
6506
6507         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6508                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6509                 return -EINVAL;
6510         }
6511
6512         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6513         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6514         if (ret < 0)
6515                 return ret;
6516
6517         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6518                                          &filter_5tuple);
6519         if (filter == NULL) {
6520                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6521                 return -ENOENT;
6522         }
6523         ntuple_filter->queue = filter->queue;
6524         return 0;
6525 }
6526
6527 /*
6528  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6529  * @dev: pointer to rte_eth_dev structure
6530  * @filter_op:operation will be taken.
6531  * @arg: a pointer to specific structure corresponding to the filter_op
6532  *
6533  * @return
6534  *    - On success, zero.
6535  *    - On failure, a negative value.
6536  */
6537 static int
6538 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6539                                 enum rte_filter_op filter_op,
6540                                 void *arg)
6541 {
6542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6543         int ret;
6544
6545         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6546
6547         if (filter_op == RTE_ETH_FILTER_NOP)
6548                 return 0;
6549
6550         if (arg == NULL) {
6551                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6552                             filter_op);
6553                 return -EINVAL;
6554         }
6555
6556         switch (filter_op) {
6557         case RTE_ETH_FILTER_ADD:
6558                 ret = ixgbe_add_del_ntuple_filter(dev,
6559                         (struct rte_eth_ntuple_filter *)arg,
6560                         TRUE);
6561                 break;
6562         case RTE_ETH_FILTER_DELETE:
6563                 ret = ixgbe_add_del_ntuple_filter(dev,
6564                         (struct rte_eth_ntuple_filter *)arg,
6565                         FALSE);
6566                 break;
6567         case RTE_ETH_FILTER_GET:
6568                 ret = ixgbe_get_ntuple_filter(dev,
6569                         (struct rte_eth_ntuple_filter *)arg);
6570                 break;
6571         default:
6572                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6573                 ret = -EINVAL;
6574                 break;
6575         }
6576         return ret;
6577 }
6578
6579 int
6580 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6581                         struct rte_eth_ethertype_filter *filter,
6582                         bool add)
6583 {
6584         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6585         struct ixgbe_filter_info *filter_info =
6586                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6587         uint32_t etqf = 0;
6588         uint32_t etqs = 0;
6589         int ret;
6590         struct ixgbe_ethertype_filter ethertype_filter;
6591
6592         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6593                 return -EINVAL;
6594
6595         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6596                 filter->ether_type == ETHER_TYPE_IPv6) {
6597                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6598                         " ethertype filter.", filter->ether_type);
6599                 return -EINVAL;
6600         }
6601
6602         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6603                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6604                 return -EINVAL;
6605         }
6606         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6607                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6608                 return -EINVAL;
6609         }
6610
6611         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6612         if (ret >= 0 && add) {
6613                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6614                             filter->ether_type);
6615                 return -EEXIST;
6616         }
6617         if (ret < 0 && !add) {
6618                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6619                             filter->ether_type);
6620                 return -ENOENT;
6621         }
6622
6623         if (add) {
6624                 etqf = IXGBE_ETQF_FILTER_EN;
6625                 etqf |= (uint32_t)filter->ether_type;
6626                 etqs |= (uint32_t)((filter->queue <<
6627                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6628                                     IXGBE_ETQS_RX_QUEUE);
6629                 etqs |= IXGBE_ETQS_QUEUE_EN;
6630
6631                 ethertype_filter.ethertype = filter->ether_type;
6632                 ethertype_filter.etqf = etqf;
6633                 ethertype_filter.etqs = etqs;
6634                 ethertype_filter.conf = FALSE;
6635                 ret = ixgbe_ethertype_filter_insert(filter_info,
6636                                                     &ethertype_filter);
6637                 if (ret < 0) {
6638                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6639                         return -ENOSPC;
6640                 }
6641         } else {
6642                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6643                 if (ret < 0)
6644                         return -ENOSYS;
6645         }
6646         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6647         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6648         IXGBE_WRITE_FLUSH(hw);
6649
6650         return 0;
6651 }
6652
6653 static int
6654 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6655                         struct rte_eth_ethertype_filter *filter)
6656 {
6657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658         struct ixgbe_filter_info *filter_info =
6659                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6660         uint32_t etqf, etqs;
6661         int ret;
6662
6663         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6664         if (ret < 0) {
6665                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6666                             filter->ether_type);
6667                 return -ENOENT;
6668         }
6669
6670         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6671         if (etqf & IXGBE_ETQF_FILTER_EN) {
6672                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6673                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6674                 filter->flags = 0;
6675                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6676                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6677                 return 0;
6678         }
6679         return -ENOENT;
6680 }
6681
6682 /*
6683  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6684  * @dev: pointer to rte_eth_dev structure
6685  * @filter_op:operation will be taken.
6686  * @arg: a pointer to specific structure corresponding to the filter_op
6687  */
6688 static int
6689 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6690                                 enum rte_filter_op filter_op,
6691                                 void *arg)
6692 {
6693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         int ret;
6695
6696         MAC_TYPE_FILTER_SUP(hw->mac.type);
6697
6698         if (filter_op == RTE_ETH_FILTER_NOP)
6699                 return 0;
6700
6701         if (arg == NULL) {
6702                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6703                             filter_op);
6704                 return -EINVAL;
6705         }
6706
6707         switch (filter_op) {
6708         case RTE_ETH_FILTER_ADD:
6709                 ret = ixgbe_add_del_ethertype_filter(dev,
6710                         (struct rte_eth_ethertype_filter *)arg,
6711                         TRUE);
6712                 break;
6713         case RTE_ETH_FILTER_DELETE:
6714                 ret = ixgbe_add_del_ethertype_filter(dev,
6715                         (struct rte_eth_ethertype_filter *)arg,
6716                         FALSE);
6717                 break;
6718         case RTE_ETH_FILTER_GET:
6719                 ret = ixgbe_get_ethertype_filter(dev,
6720                         (struct rte_eth_ethertype_filter *)arg);
6721                 break;
6722         default:
6723                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6724                 ret = -EINVAL;
6725                 break;
6726         }
6727         return ret;
6728 }
6729
6730 static int
6731 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6732                      enum rte_filter_type filter_type,
6733                      enum rte_filter_op filter_op,
6734                      void *arg)
6735 {
6736         int ret = 0;
6737
6738         switch (filter_type) {
6739         case RTE_ETH_FILTER_NTUPLE:
6740                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6741                 break;
6742         case RTE_ETH_FILTER_ETHERTYPE:
6743                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6744                 break;
6745         case RTE_ETH_FILTER_SYN:
6746                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6747                 break;
6748         case RTE_ETH_FILTER_FDIR:
6749                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6750                 break;
6751         case RTE_ETH_FILTER_L2_TUNNEL:
6752                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6753                 break;
6754         case RTE_ETH_FILTER_GENERIC:
6755                 if (filter_op != RTE_ETH_FILTER_GET)
6756                         return -EINVAL;
6757                 *(const void **)arg = &ixgbe_flow_ops;
6758                 break;
6759         default:
6760                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6761                                                         filter_type);
6762                 ret = -EINVAL;
6763                 break;
6764         }
6765
6766         return ret;
6767 }
6768
6769 static u8 *
6770 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6771                         u8 **mc_addr_ptr, u32 *vmdq)
6772 {
6773         u8 *mc_addr;
6774
6775         *vmdq = 0;
6776         mc_addr = *mc_addr_ptr;
6777         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6778         return mc_addr;
6779 }
6780
6781 static int
6782 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6783                           struct ether_addr *mc_addr_set,
6784                           uint32_t nb_mc_addr)
6785 {
6786         struct ixgbe_hw *hw;
6787         u8 *mc_addr_list;
6788
6789         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6790         mc_addr_list = (u8 *)mc_addr_set;
6791         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6792                                          ixgbe_dev_addr_list_itr, TRUE);
6793 }
6794
6795 static uint64_t
6796 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6797 {
6798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799         uint64_t systime_cycles;
6800
6801         switch (hw->mac.type) {
6802         case ixgbe_mac_X550:
6803         case ixgbe_mac_X550EM_x:
6804         case ixgbe_mac_X550EM_a:
6805                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6806                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6807                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6808                                 * NSEC_PER_SEC;
6809                 break;
6810         default:
6811                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6812                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6813                                 << 32;
6814         }
6815
6816         return systime_cycles;
6817 }
6818
6819 static uint64_t
6820 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6821 {
6822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6823         uint64_t rx_tstamp_cycles;
6824
6825         switch (hw->mac.type) {
6826         case ixgbe_mac_X550:
6827         case ixgbe_mac_X550EM_x:
6828         case ixgbe_mac_X550EM_a:
6829                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6830                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6831                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6832                                 * NSEC_PER_SEC;
6833                 break;
6834         default:
6835                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6836                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6837                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6838                                 << 32;
6839         }
6840
6841         return rx_tstamp_cycles;
6842 }
6843
6844 static uint64_t
6845 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6846 {
6847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6848         uint64_t tx_tstamp_cycles;
6849
6850         switch (hw->mac.type) {
6851         case ixgbe_mac_X550:
6852         case ixgbe_mac_X550EM_x:
6853         case ixgbe_mac_X550EM_a:
6854                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6855                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6856                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6857                                 * NSEC_PER_SEC;
6858                 break;
6859         default:
6860                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6861                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6862                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6863                                 << 32;
6864         }
6865
6866         return tx_tstamp_cycles;
6867 }
6868
6869 static void
6870 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6871 {
6872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6873         struct ixgbe_adapter *adapter =
6874                 (struct ixgbe_adapter *)dev->data->dev_private;
6875         struct rte_eth_link link;
6876         uint32_t incval = 0;
6877         uint32_t shift = 0;
6878
6879         /* Get current link speed. */
6880         memset(&link, 0, sizeof(link));
6881         ixgbe_dev_link_update(dev, 1);
6882         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6883
6884         switch (link.link_speed) {
6885         case ETH_SPEED_NUM_100M:
6886                 incval = IXGBE_INCVAL_100;
6887                 shift = IXGBE_INCVAL_SHIFT_100;
6888                 break;
6889         case ETH_SPEED_NUM_1G:
6890                 incval = IXGBE_INCVAL_1GB;
6891                 shift = IXGBE_INCVAL_SHIFT_1GB;
6892                 break;
6893         case ETH_SPEED_NUM_10G:
6894         default:
6895                 incval = IXGBE_INCVAL_10GB;
6896                 shift = IXGBE_INCVAL_SHIFT_10GB;
6897                 break;
6898         }
6899
6900         switch (hw->mac.type) {
6901         case ixgbe_mac_X550:
6902         case ixgbe_mac_X550EM_x:
6903         case ixgbe_mac_X550EM_a:
6904                 /* Independent of link speed. */
6905                 incval = 1;
6906                 /* Cycles read will be interpreted as ns. */
6907                 shift = 0;
6908                 /* Fall-through */
6909         case ixgbe_mac_X540:
6910                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6911                 break;
6912         case ixgbe_mac_82599EB:
6913                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6914                 shift -= IXGBE_INCVAL_SHIFT_82599;
6915                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6916                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6917                 break;
6918         default:
6919                 /* Not supported. */
6920                 return;
6921         }
6922
6923         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6924         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6925         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6926
6927         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6928         adapter->systime_tc.cc_shift = shift;
6929         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6930
6931         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6932         adapter->rx_tstamp_tc.cc_shift = shift;
6933         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6934
6935         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6936         adapter->tx_tstamp_tc.cc_shift = shift;
6937         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6938 }
6939
6940 static int
6941 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6942 {
6943         struct ixgbe_adapter *adapter =
6944                         (struct ixgbe_adapter *)dev->data->dev_private;
6945
6946         adapter->systime_tc.nsec += delta;
6947         adapter->rx_tstamp_tc.nsec += delta;
6948         adapter->tx_tstamp_tc.nsec += delta;
6949
6950         return 0;
6951 }
6952
6953 static int
6954 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6955 {
6956         uint64_t ns;
6957         struct ixgbe_adapter *adapter =
6958                         (struct ixgbe_adapter *)dev->data->dev_private;
6959
6960         ns = rte_timespec_to_ns(ts);
6961         /* Set the timecounters to a new value. */
6962         adapter->systime_tc.nsec = ns;
6963         adapter->rx_tstamp_tc.nsec = ns;
6964         adapter->tx_tstamp_tc.nsec = ns;
6965
6966         return 0;
6967 }
6968
6969 static int
6970 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6971 {
6972         uint64_t ns, systime_cycles;
6973         struct ixgbe_adapter *adapter =
6974                         (struct ixgbe_adapter *)dev->data->dev_private;
6975
6976         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6977         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6978         *ts = rte_ns_to_timespec(ns);
6979
6980         return 0;
6981 }
6982
6983 static int
6984 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         uint32_t tsync_ctl;
6988         uint32_t tsauxc;
6989
6990         /* Stop the timesync system time. */
6991         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6992         /* Reset the timesync system time value. */
6993         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6994         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6995
6996         /* Enable system time for platforms where it isn't on by default. */
6997         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6998         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6999         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7000
7001         ixgbe_start_timecounters(dev);
7002
7003         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7004         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7005                         (ETHER_TYPE_1588 |
7006                          IXGBE_ETQF_FILTER_EN |
7007                          IXGBE_ETQF_1588));
7008
7009         /* Enable timestamping of received PTP packets. */
7010         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7011         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7012         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7013
7014         /* Enable timestamping of transmitted PTP packets. */
7015         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7016         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7017         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7018
7019         IXGBE_WRITE_FLUSH(hw);
7020
7021         return 0;
7022 }
7023
7024 static int
7025 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7026 {
7027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028         uint32_t tsync_ctl;
7029
7030         /* Disable timestamping of transmitted PTP packets. */
7031         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7032         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7033         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7034
7035         /* Disable timestamping of received PTP packets. */
7036         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7037         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7038         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7039
7040         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7041         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7042
7043         /* Stop incrementating the System Time registers. */
7044         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7045
7046         return 0;
7047 }
7048
7049 static int
7050 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7051                                  struct timespec *timestamp,
7052                                  uint32_t flags __rte_unused)
7053 {
7054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7055         struct ixgbe_adapter *adapter =
7056                 (struct ixgbe_adapter *)dev->data->dev_private;
7057         uint32_t tsync_rxctl;
7058         uint64_t rx_tstamp_cycles;
7059         uint64_t ns;
7060
7061         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7062         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7063                 return -EINVAL;
7064
7065         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7066         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7067         *timestamp = rte_ns_to_timespec(ns);
7068
7069         return  0;
7070 }
7071
7072 static int
7073 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7074                                  struct timespec *timestamp)
7075 {
7076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7077         struct ixgbe_adapter *adapter =
7078                 (struct ixgbe_adapter *)dev->data->dev_private;
7079         uint32_t tsync_txctl;
7080         uint64_t tx_tstamp_cycles;
7081         uint64_t ns;
7082
7083         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7084         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7085                 return -EINVAL;
7086
7087         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7088         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7089         *timestamp = rte_ns_to_timespec(ns);
7090
7091         return 0;
7092 }
7093
7094 static int
7095 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7096 {
7097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7098         int count = 0;
7099         int g_ind = 0;
7100         const struct reg_info *reg_group;
7101         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7102                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7103
7104         while ((reg_group = reg_set[g_ind++]))
7105                 count += ixgbe_regs_group_count(reg_group);
7106
7107         return count;
7108 }
7109
7110 static int
7111 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7112 {
7113         int count = 0;
7114         int g_ind = 0;
7115         const struct reg_info *reg_group;
7116
7117         while ((reg_group = ixgbevf_regs[g_ind++]))
7118                 count += ixgbe_regs_group_count(reg_group);
7119
7120         return count;
7121 }
7122
7123 static int
7124 ixgbe_get_regs(struct rte_eth_dev *dev,
7125               struct rte_dev_reg_info *regs)
7126 {
7127         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128         uint32_t *data = regs->data;
7129         int g_ind = 0;
7130         int count = 0;
7131         const struct reg_info *reg_group;
7132         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7133                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7134
7135         if (data == NULL) {
7136                 regs->length = ixgbe_get_reg_length(dev);
7137                 regs->width = sizeof(uint32_t);
7138                 return 0;
7139         }
7140
7141         /* Support only full register dump */
7142         if ((regs->length == 0) ||
7143             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7144                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7145                         hw->device_id;
7146                 while ((reg_group = reg_set[g_ind++]))
7147                         count += ixgbe_read_regs_group(dev, &data[count],
7148                                 reg_group);
7149                 return 0;
7150         }
7151
7152         return -ENOTSUP;
7153 }
7154
7155 static int
7156 ixgbevf_get_regs(struct rte_eth_dev *dev,
7157                 struct rte_dev_reg_info *regs)
7158 {
7159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7160         uint32_t *data = regs->data;
7161         int g_ind = 0;
7162         int count = 0;
7163         const struct reg_info *reg_group;
7164
7165         if (data == NULL) {
7166                 regs->length = ixgbevf_get_reg_length(dev);
7167                 regs->width = sizeof(uint32_t);
7168                 return 0;
7169         }
7170
7171         /* Support only full register dump */
7172         if ((regs->length == 0) ||
7173             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7174                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7175                         hw->device_id;
7176                 while ((reg_group = ixgbevf_regs[g_ind++]))
7177                         count += ixgbe_read_regs_group(dev, &data[count],
7178                                                       reg_group);
7179                 return 0;
7180         }
7181
7182         return -ENOTSUP;
7183 }
7184
7185 static int
7186 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7187 {
7188         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7189
7190         /* Return unit is byte count */
7191         return hw->eeprom.word_size * 2;
7192 }
7193
7194 static int
7195 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7196                 struct rte_dev_eeprom_info *in_eeprom)
7197 {
7198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7199         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7200         uint16_t *data = in_eeprom->data;
7201         int first, length;
7202
7203         first = in_eeprom->offset >> 1;
7204         length = in_eeprom->length >> 1;
7205         if ((first > hw->eeprom.word_size) ||
7206             ((first + length) > hw->eeprom.word_size))
7207                 return -EINVAL;
7208
7209         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7210
7211         return eeprom->ops.read_buffer(hw, first, length, data);
7212 }
7213
7214 static int
7215 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7216                 struct rte_dev_eeprom_info *in_eeprom)
7217 {
7218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7219         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7220         uint16_t *data = in_eeprom->data;
7221         int first, length;
7222
7223         first = in_eeprom->offset >> 1;
7224         length = in_eeprom->length >> 1;
7225         if ((first > hw->eeprom.word_size) ||
7226             ((first + length) > hw->eeprom.word_size))
7227                 return -EINVAL;
7228
7229         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7230
7231         return eeprom->ops.write_buffer(hw,  first, length, data);
7232 }
7233
7234 uint16_t
7235 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7236         switch (mac_type) {
7237         case ixgbe_mac_X550:
7238         case ixgbe_mac_X550EM_x:
7239         case ixgbe_mac_X550EM_a:
7240                 return ETH_RSS_RETA_SIZE_512;
7241         case ixgbe_mac_X550_vf:
7242         case ixgbe_mac_X550EM_x_vf:
7243         case ixgbe_mac_X550EM_a_vf:
7244                 return ETH_RSS_RETA_SIZE_64;
7245         default:
7246                 return ETH_RSS_RETA_SIZE_128;
7247         }
7248 }
7249
7250 uint32_t
7251 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7252         switch (mac_type) {
7253         case ixgbe_mac_X550:
7254         case ixgbe_mac_X550EM_x:
7255         case ixgbe_mac_X550EM_a:
7256                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7257                         return IXGBE_RETA(reta_idx >> 2);
7258                 else
7259                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7260         case ixgbe_mac_X550_vf:
7261         case ixgbe_mac_X550EM_x_vf:
7262         case ixgbe_mac_X550EM_a_vf:
7263                 return IXGBE_VFRETA(reta_idx >> 2);
7264         default:
7265                 return IXGBE_RETA(reta_idx >> 2);
7266         }
7267 }
7268
7269 uint32_t
7270 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7271         switch (mac_type) {
7272         case ixgbe_mac_X550_vf:
7273         case ixgbe_mac_X550EM_x_vf:
7274         case ixgbe_mac_X550EM_a_vf:
7275                 return IXGBE_VFMRQC;
7276         default:
7277                 return IXGBE_MRQC;
7278         }
7279 }
7280
7281 uint32_t
7282 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7283         switch (mac_type) {
7284         case ixgbe_mac_X550_vf:
7285         case ixgbe_mac_X550EM_x_vf:
7286         case ixgbe_mac_X550EM_a_vf:
7287                 return IXGBE_VFRSSRK(i);
7288         default:
7289                 return IXGBE_RSSRK(i);
7290         }
7291 }
7292
7293 bool
7294 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7295         switch (mac_type) {
7296         case ixgbe_mac_82599_vf:
7297         case ixgbe_mac_X540_vf:
7298                 return 0;
7299         default:
7300                 return 1;
7301         }
7302 }
7303
7304 static int
7305 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7306                         struct rte_eth_dcb_info *dcb_info)
7307 {
7308         struct ixgbe_dcb_config *dcb_config =
7309                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7310         struct ixgbe_dcb_tc_config *tc;
7311         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7312         uint8_t nb_tcs;
7313         uint8_t i, j;
7314
7315         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7316                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7317         else
7318                 dcb_info->nb_tcs = 1;
7319
7320         tc_queue = &dcb_info->tc_queue;
7321         nb_tcs = dcb_info->nb_tcs;
7322
7323         if (dcb_config->vt_mode) { /* vt is enabled*/
7324                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7325                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7326                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7327                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7328                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7329                         for (j = 0; j < nb_tcs; j++) {
7330                                 tc_queue->tc_rxq[0][j].base = j;
7331                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7332                                 tc_queue->tc_txq[0][j].base = j;
7333                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7334                         }
7335                 } else {
7336                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7337                                 for (j = 0; j < nb_tcs; j++) {
7338                                         tc_queue->tc_rxq[i][j].base =
7339                                                 i * nb_tcs + j;
7340                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7341                                         tc_queue->tc_txq[i][j].base =
7342                                                 i * nb_tcs + j;
7343                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7344                                 }
7345                         }
7346                 }
7347         } else { /* vt is disabled*/
7348                 struct rte_eth_dcb_rx_conf *rx_conf =
7349                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7350                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7351                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7352                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7353                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7354                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7355                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7356                         }
7357                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7358                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7359                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7360                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7361                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7362                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7363                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7364                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7365                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7366                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7367                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7368                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7369                         }
7370                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7371                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7372                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7373                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7374                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7375                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7376                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7377                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7378                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7379                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7380                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7381                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7382                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7383                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7384                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7385                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7386                 }
7387         }
7388         for (i = 0; i < dcb_info->nb_tcs; i++) {
7389                 tc = &dcb_config->tc_config[i];
7390                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7391         }
7392         return 0;
7393 }
7394
7395 /* Update e-tag ether type */
7396 static int
7397 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7398                             uint16_t ether_type)
7399 {
7400         uint32_t etag_etype;
7401
7402         if (hw->mac.type != ixgbe_mac_X550 &&
7403             hw->mac.type != ixgbe_mac_X550EM_x &&
7404             hw->mac.type != ixgbe_mac_X550EM_a) {
7405                 return -ENOTSUP;
7406         }
7407
7408         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7409         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7410         etag_etype |= ether_type;
7411         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7412         IXGBE_WRITE_FLUSH(hw);
7413
7414         return 0;
7415 }
7416
7417 /* Config l2 tunnel ether type */
7418 static int
7419 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7420                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7421 {
7422         int ret = 0;
7423         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7424         struct ixgbe_l2_tn_info *l2_tn_info =
7425                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7426
7427         if (l2_tunnel == NULL)
7428                 return -EINVAL;
7429
7430         switch (l2_tunnel->l2_tunnel_type) {
7431         case RTE_L2_TUNNEL_TYPE_E_TAG:
7432                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7433                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7434                 break;
7435         default:
7436                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7437                 ret = -EINVAL;
7438                 break;
7439         }
7440
7441         return ret;
7442 }
7443
7444 /* Enable e-tag tunnel */
7445 static int
7446 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7447 {
7448         uint32_t etag_etype;
7449
7450         if (hw->mac.type != ixgbe_mac_X550 &&
7451             hw->mac.type != ixgbe_mac_X550EM_x &&
7452             hw->mac.type != ixgbe_mac_X550EM_a) {
7453                 return -ENOTSUP;
7454         }
7455
7456         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7457         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7458         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7459         IXGBE_WRITE_FLUSH(hw);
7460
7461         return 0;
7462 }
7463
7464 /* Enable l2 tunnel */
7465 static int
7466 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7467                            enum rte_eth_tunnel_type l2_tunnel_type)
7468 {
7469         int ret = 0;
7470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7471         struct ixgbe_l2_tn_info *l2_tn_info =
7472                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7473
7474         switch (l2_tunnel_type) {
7475         case RTE_L2_TUNNEL_TYPE_E_TAG:
7476                 l2_tn_info->e_tag_en = TRUE;
7477                 ret = ixgbe_e_tag_enable(hw);
7478                 break;
7479         default:
7480                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7481                 ret = -EINVAL;
7482                 break;
7483         }
7484
7485         return ret;
7486 }
7487
7488 /* Disable e-tag tunnel */
7489 static int
7490 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7491 {
7492         uint32_t etag_etype;
7493
7494         if (hw->mac.type != ixgbe_mac_X550 &&
7495             hw->mac.type != ixgbe_mac_X550EM_x &&
7496             hw->mac.type != ixgbe_mac_X550EM_a) {
7497                 return -ENOTSUP;
7498         }
7499
7500         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7501         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7502         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7503         IXGBE_WRITE_FLUSH(hw);
7504
7505         return 0;
7506 }
7507
7508 /* Disable l2 tunnel */
7509 static int
7510 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7511                             enum rte_eth_tunnel_type l2_tunnel_type)
7512 {
7513         int ret = 0;
7514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515         struct ixgbe_l2_tn_info *l2_tn_info =
7516                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7517
7518         switch (l2_tunnel_type) {
7519         case RTE_L2_TUNNEL_TYPE_E_TAG:
7520                 l2_tn_info->e_tag_en = FALSE;
7521                 ret = ixgbe_e_tag_disable(hw);
7522                 break;
7523         default:
7524                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7525                 ret = -EINVAL;
7526                 break;
7527         }
7528
7529         return ret;
7530 }
7531
7532 static int
7533 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7534                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7535 {
7536         int ret = 0;
7537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7538         uint32_t i, rar_entries;
7539         uint32_t rar_low, rar_high;
7540
7541         if (hw->mac.type != ixgbe_mac_X550 &&
7542             hw->mac.type != ixgbe_mac_X550EM_x &&
7543             hw->mac.type != ixgbe_mac_X550EM_a) {
7544                 return -ENOTSUP;
7545         }
7546
7547         rar_entries = ixgbe_get_num_rx_addrs(hw);
7548
7549         for (i = 1; i < rar_entries; i++) {
7550                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7551                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7552                 if ((rar_high & IXGBE_RAH_AV) &&
7553                     (rar_high & IXGBE_RAH_ADTYPE) &&
7554                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7555                      l2_tunnel->tunnel_id)) {
7556                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7557                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7558
7559                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7560
7561                         return ret;
7562                 }
7563         }
7564
7565         return ret;
7566 }
7567
7568 static int
7569 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7570                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7571 {
7572         int ret = 0;
7573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7574         uint32_t i, rar_entries;
7575         uint32_t rar_low, rar_high;
7576
7577         if (hw->mac.type != ixgbe_mac_X550 &&
7578             hw->mac.type != ixgbe_mac_X550EM_x &&
7579             hw->mac.type != ixgbe_mac_X550EM_a) {
7580                 return -ENOTSUP;
7581         }
7582
7583         /* One entry for one tunnel. Try to remove potential existing entry. */
7584         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7585
7586         rar_entries = ixgbe_get_num_rx_addrs(hw);
7587
7588         for (i = 1; i < rar_entries; i++) {
7589                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7590                 if (rar_high & IXGBE_RAH_AV) {
7591                         continue;
7592                 } else {
7593                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7594                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7595                         rar_low = l2_tunnel->tunnel_id;
7596
7597                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7598                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7599
7600                         return ret;
7601                 }
7602         }
7603
7604         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7605                      " Please remove a rule before adding a new one.");
7606         return -EINVAL;
7607 }
7608
7609 static inline struct ixgbe_l2_tn_filter *
7610 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7611                           struct ixgbe_l2_tn_key *key)
7612 {
7613         int ret;
7614
7615         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7616         if (ret < 0)
7617                 return NULL;
7618
7619         return l2_tn_info->hash_map[ret];
7620 }
7621
7622 static inline int
7623 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7624                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7625 {
7626         int ret;
7627
7628         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7629                                &l2_tn_filter->key);
7630
7631         if (ret < 0) {
7632                 PMD_DRV_LOG(ERR,
7633                             "Failed to insert L2 tunnel filter"
7634                             " to hash table %d!",
7635                             ret);
7636                 return ret;
7637         }
7638
7639         l2_tn_info->hash_map[ret] = l2_tn_filter;
7640
7641         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7642
7643         return 0;
7644 }
7645
7646 static inline int
7647 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7648                           struct ixgbe_l2_tn_key *key)
7649 {
7650         int ret;
7651         struct ixgbe_l2_tn_filter *l2_tn_filter;
7652
7653         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7654
7655         if (ret < 0) {
7656                 PMD_DRV_LOG(ERR,
7657                             "No such L2 tunnel filter to delete %d!",
7658                             ret);
7659                 return ret;
7660         }
7661
7662         l2_tn_filter = l2_tn_info->hash_map[ret];
7663         l2_tn_info->hash_map[ret] = NULL;
7664
7665         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7666         rte_free(l2_tn_filter);
7667
7668         return 0;
7669 }
7670
7671 /* Add l2 tunnel filter */
7672 int
7673 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7674                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7675                                bool restore)
7676 {
7677         int ret;
7678         struct ixgbe_l2_tn_info *l2_tn_info =
7679                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7680         struct ixgbe_l2_tn_key key;
7681         struct ixgbe_l2_tn_filter *node;
7682
7683         if (!restore) {
7684                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7685                 key.tn_id = l2_tunnel->tunnel_id;
7686
7687                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7688
7689                 if (node) {
7690                         PMD_DRV_LOG(ERR,
7691                                     "The L2 tunnel filter already exists!");
7692                         return -EINVAL;
7693                 }
7694
7695                 node = rte_zmalloc("ixgbe_l2_tn",
7696                                    sizeof(struct ixgbe_l2_tn_filter),
7697                                    0);
7698                 if (!node)
7699                         return -ENOMEM;
7700
7701                 rte_memcpy(&node->key,
7702                                  &key,
7703                                  sizeof(struct ixgbe_l2_tn_key));
7704                 node->pool = l2_tunnel->pool;
7705                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7706                 if (ret < 0) {
7707                         rte_free(node);
7708                         return ret;
7709                 }
7710         }
7711
7712         switch (l2_tunnel->l2_tunnel_type) {
7713         case RTE_L2_TUNNEL_TYPE_E_TAG:
7714                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7715                 break;
7716         default:
7717                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7718                 ret = -EINVAL;
7719                 break;
7720         }
7721
7722         if ((!restore) && (ret < 0))
7723                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7724
7725         return ret;
7726 }
7727
7728 /* Delete l2 tunnel filter */
7729 int
7730 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7731                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7732 {
7733         int ret;
7734         struct ixgbe_l2_tn_info *l2_tn_info =
7735                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7736         struct ixgbe_l2_tn_key key;
7737
7738         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7739         key.tn_id = l2_tunnel->tunnel_id;
7740         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7741         if (ret < 0)
7742                 return ret;
7743
7744         switch (l2_tunnel->l2_tunnel_type) {
7745         case RTE_L2_TUNNEL_TYPE_E_TAG:
7746                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7747                 break;
7748         default:
7749                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7750                 ret = -EINVAL;
7751                 break;
7752         }
7753
7754         return ret;
7755 }
7756
7757 /**
7758  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7759  * @dev: pointer to rte_eth_dev structure
7760  * @filter_op:operation will be taken.
7761  * @arg: a pointer to specific structure corresponding to the filter_op
7762  */
7763 static int
7764 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7765                                   enum rte_filter_op filter_op,
7766                                   void *arg)
7767 {
7768         int ret;
7769
7770         if (filter_op == RTE_ETH_FILTER_NOP)
7771                 return 0;
7772
7773         if (arg == NULL) {
7774                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7775                             filter_op);
7776                 return -EINVAL;
7777         }
7778
7779         switch (filter_op) {
7780         case RTE_ETH_FILTER_ADD:
7781                 ret = ixgbe_dev_l2_tunnel_filter_add
7782                         (dev,
7783                          (struct rte_eth_l2_tunnel_conf *)arg,
7784                          FALSE);
7785                 break;
7786         case RTE_ETH_FILTER_DELETE:
7787                 ret = ixgbe_dev_l2_tunnel_filter_del
7788                         (dev,
7789                          (struct rte_eth_l2_tunnel_conf *)arg);
7790                 break;
7791         default:
7792                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7793                 ret = -EINVAL;
7794                 break;
7795         }
7796         return ret;
7797 }
7798
7799 static int
7800 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7801 {
7802         int ret = 0;
7803         uint32_t ctrl;
7804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7805
7806         if (hw->mac.type != ixgbe_mac_X550 &&
7807             hw->mac.type != ixgbe_mac_X550EM_x &&
7808             hw->mac.type != ixgbe_mac_X550EM_a) {
7809                 return -ENOTSUP;
7810         }
7811
7812         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7813         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7814         if (en)
7815                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7816         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7817
7818         return ret;
7819 }
7820
7821 /* Enable l2 tunnel forwarding */
7822 static int
7823 ixgbe_dev_l2_tunnel_forwarding_enable
7824         (struct rte_eth_dev *dev,
7825          enum rte_eth_tunnel_type l2_tunnel_type)
7826 {
7827         struct ixgbe_l2_tn_info *l2_tn_info =
7828                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7829         int ret = 0;
7830
7831         switch (l2_tunnel_type) {
7832         case RTE_L2_TUNNEL_TYPE_E_TAG:
7833                 l2_tn_info->e_tag_fwd_en = TRUE;
7834                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7835                 break;
7836         default:
7837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7838                 ret = -EINVAL;
7839                 break;
7840         }
7841
7842         return ret;
7843 }
7844
7845 /* Disable l2 tunnel forwarding */
7846 static int
7847 ixgbe_dev_l2_tunnel_forwarding_disable
7848         (struct rte_eth_dev *dev,
7849          enum rte_eth_tunnel_type l2_tunnel_type)
7850 {
7851         struct ixgbe_l2_tn_info *l2_tn_info =
7852                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7853         int ret = 0;
7854
7855         switch (l2_tunnel_type) {
7856         case RTE_L2_TUNNEL_TYPE_E_TAG:
7857                 l2_tn_info->e_tag_fwd_en = FALSE;
7858                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7859                 break;
7860         default:
7861                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7862                 ret = -EINVAL;
7863                 break;
7864         }
7865
7866         return ret;
7867 }
7868
7869 static int
7870 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7871                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7872                              bool en)
7873 {
7874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7875         int ret = 0;
7876         uint32_t vmtir, vmvir;
7877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7878
7879         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7880                 PMD_DRV_LOG(ERR,
7881                             "VF id %u should be less than %u",
7882                             l2_tunnel->vf_id,
7883                             pci_dev->max_vfs);
7884                 return -EINVAL;
7885         }
7886
7887         if (hw->mac.type != ixgbe_mac_X550 &&
7888             hw->mac.type != ixgbe_mac_X550EM_x &&
7889             hw->mac.type != ixgbe_mac_X550EM_a) {
7890                 return -ENOTSUP;
7891         }
7892
7893         if (en)
7894                 vmtir = l2_tunnel->tunnel_id;
7895         else
7896                 vmtir = 0;
7897
7898         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7899
7900         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7901         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7902         if (en)
7903                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7904         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7905
7906         return ret;
7907 }
7908
7909 /* Enable l2 tunnel tag insertion */
7910 static int
7911 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7912                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7913 {
7914         int ret = 0;
7915
7916         switch (l2_tunnel->l2_tunnel_type) {
7917         case RTE_L2_TUNNEL_TYPE_E_TAG:
7918                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7919                 break;
7920         default:
7921                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7922                 ret = -EINVAL;
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 /* Disable l2 tunnel tag insertion */
7930 static int
7931 ixgbe_dev_l2_tunnel_insertion_disable
7932         (struct rte_eth_dev *dev,
7933          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7934 {
7935         int ret = 0;
7936
7937         switch (l2_tunnel->l2_tunnel_type) {
7938         case RTE_L2_TUNNEL_TYPE_E_TAG:
7939                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7940                 break;
7941         default:
7942                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7943                 ret = -EINVAL;
7944                 break;
7945         }
7946
7947         return ret;
7948 }
7949
7950 static int
7951 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7952                              bool en)
7953 {
7954         int ret = 0;
7955         uint32_t qde;
7956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7957
7958         if (hw->mac.type != ixgbe_mac_X550 &&
7959             hw->mac.type != ixgbe_mac_X550EM_x &&
7960             hw->mac.type != ixgbe_mac_X550EM_a) {
7961                 return -ENOTSUP;
7962         }
7963
7964         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7965         if (en)
7966                 qde |= IXGBE_QDE_STRIP_TAG;
7967         else
7968                 qde &= ~IXGBE_QDE_STRIP_TAG;
7969         qde &= ~IXGBE_QDE_READ;
7970         qde |= IXGBE_QDE_WRITE;
7971         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7972
7973         return ret;
7974 }
7975
7976 /* Enable l2 tunnel tag stripping */
7977 static int
7978 ixgbe_dev_l2_tunnel_stripping_enable
7979         (struct rte_eth_dev *dev,
7980          enum rte_eth_tunnel_type l2_tunnel_type)
7981 {
7982         int ret = 0;
7983
7984         switch (l2_tunnel_type) {
7985         case RTE_L2_TUNNEL_TYPE_E_TAG:
7986                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7987                 break;
7988         default:
7989                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7990                 ret = -EINVAL;
7991                 break;
7992         }
7993
7994         return ret;
7995 }
7996
7997 /* Disable l2 tunnel tag stripping */
7998 static int
7999 ixgbe_dev_l2_tunnel_stripping_disable
8000         (struct rte_eth_dev *dev,
8001          enum rte_eth_tunnel_type l2_tunnel_type)
8002 {
8003         int ret = 0;
8004
8005         switch (l2_tunnel_type) {
8006         case RTE_L2_TUNNEL_TYPE_E_TAG:
8007                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8008                 break;
8009         default:
8010                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8011                 ret = -EINVAL;
8012                 break;
8013         }
8014
8015         return ret;
8016 }
8017
8018 /* Enable/disable l2 tunnel offload functions */
8019 static int
8020 ixgbe_dev_l2_tunnel_offload_set
8021         (struct rte_eth_dev *dev,
8022          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8023          uint32_t mask,
8024          uint8_t en)
8025 {
8026         int ret = 0;
8027
8028         if (l2_tunnel == NULL)
8029                 return -EINVAL;
8030
8031         ret = -EINVAL;
8032         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8033                 if (en)
8034                         ret = ixgbe_dev_l2_tunnel_enable(
8035                                 dev,
8036                                 l2_tunnel->l2_tunnel_type);
8037                 else
8038                         ret = ixgbe_dev_l2_tunnel_disable(
8039                                 dev,
8040                                 l2_tunnel->l2_tunnel_type);
8041         }
8042
8043         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8044                 if (en)
8045                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8046                                 dev,
8047                                 l2_tunnel);
8048                 else
8049                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8050                                 dev,
8051                                 l2_tunnel);
8052         }
8053
8054         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8055                 if (en)
8056                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8057                                 dev,
8058                                 l2_tunnel->l2_tunnel_type);
8059                 else
8060                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8061                                 dev,
8062                                 l2_tunnel->l2_tunnel_type);
8063         }
8064
8065         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8066                 if (en)
8067                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8068                                 dev,
8069                                 l2_tunnel->l2_tunnel_type);
8070                 else
8071                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8072                                 dev,
8073                                 l2_tunnel->l2_tunnel_type);
8074         }
8075
8076         return ret;
8077 }
8078
8079 static int
8080 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8081                         uint16_t port)
8082 {
8083         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8084         IXGBE_WRITE_FLUSH(hw);
8085
8086         return 0;
8087 }
8088
8089 /* There's only one register for VxLAN UDP port.
8090  * So, we cannot add several ports. Will update it.
8091  */
8092 static int
8093 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8094                      uint16_t port)
8095 {
8096         if (port == 0) {
8097                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8098                 return -EINVAL;
8099         }
8100
8101         return ixgbe_update_vxlan_port(hw, port);
8102 }
8103
8104 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8105  * UDP port, it must have a value.
8106  * So, will reset it to the original value 0.
8107  */
8108 static int
8109 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8110                      uint16_t port)
8111 {
8112         uint16_t cur_port;
8113
8114         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8115
8116         if (cur_port != port) {
8117                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8118                 return -EINVAL;
8119         }
8120
8121         return ixgbe_update_vxlan_port(hw, 0);
8122 }
8123
8124 /* Add UDP tunneling port */
8125 static int
8126 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8127                               struct rte_eth_udp_tunnel *udp_tunnel)
8128 {
8129         int ret = 0;
8130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131
8132         if (hw->mac.type != ixgbe_mac_X550 &&
8133             hw->mac.type != ixgbe_mac_X550EM_x &&
8134             hw->mac.type != ixgbe_mac_X550EM_a) {
8135                 return -ENOTSUP;
8136         }
8137
8138         if (udp_tunnel == NULL)
8139                 return -EINVAL;
8140
8141         switch (udp_tunnel->prot_type) {
8142         case RTE_TUNNEL_TYPE_VXLAN:
8143                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8144                 break;
8145
8146         case RTE_TUNNEL_TYPE_GENEVE:
8147         case RTE_TUNNEL_TYPE_TEREDO:
8148                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8149                 ret = -EINVAL;
8150                 break;
8151
8152         default:
8153                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8154                 ret = -EINVAL;
8155                 break;
8156         }
8157
8158         return ret;
8159 }
8160
8161 /* Remove UDP tunneling port */
8162 static int
8163 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8164                               struct rte_eth_udp_tunnel *udp_tunnel)
8165 {
8166         int ret = 0;
8167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8168
8169         if (hw->mac.type != ixgbe_mac_X550 &&
8170             hw->mac.type != ixgbe_mac_X550EM_x &&
8171             hw->mac.type != ixgbe_mac_X550EM_a) {
8172                 return -ENOTSUP;
8173         }
8174
8175         if (udp_tunnel == NULL)
8176                 return -EINVAL;
8177
8178         switch (udp_tunnel->prot_type) {
8179         case RTE_TUNNEL_TYPE_VXLAN:
8180                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8181                 break;
8182         case RTE_TUNNEL_TYPE_GENEVE:
8183         case RTE_TUNNEL_TYPE_TEREDO:
8184                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8185                 ret = -EINVAL;
8186                 break;
8187         default:
8188                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8189                 ret = -EINVAL;
8190                 break;
8191         }
8192
8193         return ret;
8194 }
8195
8196 static void
8197 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8198 {
8199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8200
8201         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8202 }
8203
8204 static void
8205 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8206 {
8207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8208
8209         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8210 }
8211
8212 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8213 {
8214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8215         u32 in_msg = 0;
8216
8217         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8218                 return;
8219
8220         /* PF reset VF event */
8221         if (in_msg == IXGBE_PF_CONTROL_MSG)
8222                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8223                                               NULL, NULL);
8224 }
8225
8226 static int
8227 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8228 {
8229         uint32_t eicr;
8230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231         struct ixgbe_interrupt *intr =
8232                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8233         ixgbevf_intr_disable(hw);
8234
8235         /* read-on-clear nic registers here */
8236         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8237         intr->flags = 0;
8238
8239         /* only one misc vector supported - mailbox */
8240         eicr &= IXGBE_VTEICR_MASK;
8241         if (eicr == IXGBE_MISC_VEC_ID)
8242                 intr->flags |= IXGBE_FLAG_MAILBOX;
8243
8244         return 0;
8245 }
8246
8247 static int
8248 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8249 {
8250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8251         struct ixgbe_interrupt *intr =
8252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8253
8254         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8255                 ixgbevf_mbx_process(dev);
8256                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8257         }
8258
8259         ixgbevf_intr_enable(hw);
8260
8261         return 0;
8262 }
8263
8264 static void
8265 ixgbevf_dev_interrupt_handler(void *param)
8266 {
8267         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8268
8269         ixgbevf_dev_interrupt_get_status(dev);
8270         ixgbevf_dev_interrupt_action(dev);
8271 }
8272
8273 /**
8274  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8275  *  @hw: pointer to hardware structure
8276  *
8277  *  Stops the transmit data path and waits for the HW to internally empty
8278  *  the Tx security block
8279  **/
8280 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8281 {
8282 #define IXGBE_MAX_SECTX_POLL 40
8283
8284         int i;
8285         int sectxreg;
8286
8287         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8288         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8289         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8290         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8291                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8292                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8293                         break;
8294                 /* Use interrupt-safe sleep just in case */
8295                 usec_delay(1000);
8296         }
8297
8298         /* For informational purposes only */
8299         if (i >= IXGBE_MAX_SECTX_POLL)
8300                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8301                          "path fully disabled.  Continuing with init.");
8302
8303         return IXGBE_SUCCESS;
8304 }
8305
8306 /**
8307  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8308  *  @hw: pointer to hardware structure
8309  *
8310  *  Enables the transmit data path.
8311  **/
8312 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8313 {
8314         uint32_t sectxreg;
8315
8316         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8317         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8318         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8319         IXGBE_WRITE_FLUSH(hw);
8320
8321         return IXGBE_SUCCESS;
8322 }
8323
8324 /* restore n-tuple filter */
8325 static inline void
8326 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8327 {
8328         struct ixgbe_filter_info *filter_info =
8329                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8330         struct ixgbe_5tuple_filter *node;
8331
8332         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8333                 ixgbe_inject_5tuple_filter(dev, node);
8334         }
8335 }
8336
8337 /* restore ethernet type filter */
8338 static inline void
8339 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8340 {
8341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342         struct ixgbe_filter_info *filter_info =
8343                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8344         int i;
8345
8346         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8347                 if (filter_info->ethertype_mask & (1 << i)) {
8348                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8349                                         filter_info->ethertype_filters[i].etqf);
8350                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8351                                         filter_info->ethertype_filters[i].etqs);
8352                         IXGBE_WRITE_FLUSH(hw);
8353                 }
8354         }
8355 }
8356
8357 /* restore SYN filter */
8358 static inline void
8359 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8360 {
8361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8362         struct ixgbe_filter_info *filter_info =
8363                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8364         uint32_t synqf;
8365
8366         synqf = filter_info->syn_info;
8367
8368         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8369                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8370                 IXGBE_WRITE_FLUSH(hw);
8371         }
8372 }
8373
8374 /* restore L2 tunnel filter */
8375 static inline void
8376 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8377 {
8378         struct ixgbe_l2_tn_info *l2_tn_info =
8379                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8380         struct ixgbe_l2_tn_filter *node;
8381         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8382
8383         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8384                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8385                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8386                 l2_tn_conf.pool           = node->pool;
8387                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8388         }
8389 }
8390
8391 static int
8392 ixgbe_filter_restore(struct rte_eth_dev *dev)
8393 {
8394         ixgbe_ntuple_filter_restore(dev);
8395         ixgbe_ethertype_filter_restore(dev);
8396         ixgbe_syn_filter_restore(dev);
8397         ixgbe_fdir_filter_restore(dev);
8398         ixgbe_l2_tn_filter_restore(dev);
8399
8400         return 0;
8401 }
8402
8403 static void
8404 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8405 {
8406         struct ixgbe_l2_tn_info *l2_tn_info =
8407                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8408         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8409
8410         if (l2_tn_info->e_tag_en)
8411                 (void)ixgbe_e_tag_enable(hw);
8412
8413         if (l2_tn_info->e_tag_fwd_en)
8414                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8415
8416         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8417 }
8418
8419 /* remove all the n-tuple filters */
8420 void
8421 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8422 {
8423         struct ixgbe_filter_info *filter_info =
8424                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8425         struct ixgbe_5tuple_filter *p_5tuple;
8426
8427         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8428                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8429 }
8430
8431 /* remove all the ether type filters */
8432 void
8433 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8434 {
8435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8436         struct ixgbe_filter_info *filter_info =
8437                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8438         int i;
8439
8440         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8441                 if (filter_info->ethertype_mask & (1 << i) &&
8442                     !filter_info->ethertype_filters[i].conf) {
8443                         (void)ixgbe_ethertype_filter_remove(filter_info,
8444                                                             (uint8_t)i);
8445                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8446                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8447                         IXGBE_WRITE_FLUSH(hw);
8448                 }
8449         }
8450 }
8451
8452 /* remove the SYN filter */
8453 void
8454 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8455 {
8456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8457         struct ixgbe_filter_info *filter_info =
8458                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8459
8460         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8461                 filter_info->syn_info = 0;
8462
8463                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8464                 IXGBE_WRITE_FLUSH(hw);
8465         }
8466 }
8467
8468 /* remove all the L2 tunnel filters */
8469 int
8470 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8471 {
8472         struct ixgbe_l2_tn_info *l2_tn_info =
8473                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8474         struct ixgbe_l2_tn_filter *l2_tn_filter;
8475         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8476         int ret = 0;
8477
8478         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8479                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8480                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8481                 l2_tn_conf.pool           = l2_tn_filter->pool;
8482                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8483                 if (ret < 0)
8484                         return ret;
8485         }
8486
8487         return 0;
8488 }
8489
8490 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8491 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8492 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8493 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8494 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8495 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");