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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
42 /* need update link, bit flag */
43 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
44 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
45 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
48 * Defines that were not part of ixgbe_type.h as they are not used by the
51 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
52 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
53 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
54 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
55 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
56 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
57 #define IXGBE_NB_STAT_MAPPING_REGS 32
58 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
59 #define IXGBE_VFTA_SIZE 128
60 #define IXGBE_VLAN_TAG_SIZE 4
61 #define IXGBE_MAX_RX_QUEUE_NUM 128
62 #define IXGBE_MAX_INTR_QUEUE_NUM 15
63 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
64 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
65 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
68 #define NBBY 8 /* number of bits in a byte */
70 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
72 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
73 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
74 #define IXGBE_EITR_ITR_INT_SHIFT 3
75 #define IXGBE_EITR_INTERVAL_US(us) \
76 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
77 IXGBE_EITR_ITR_INT_MASK)
80 /* Loopback operation modes */
81 /* 82599 specific loopback operation types */
82 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
83 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
85 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
87 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
88 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
89 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
91 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
93 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
94 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
95 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
96 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
98 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
99 #define IXGBE_ETQF_SHIFT 16
100 #define IXGBE_ETQF_UP_EN 0x00080000
101 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
102 #define IXGBE_ETQF_MAX_PRI 7
104 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
105 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
106 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
108 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
109 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
110 #define IXGBE_L34T_IMIR_LLI 0x00100000
111 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
112 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
113 #define IXGBE_5TUPLE_MAX_PRI 7
114 #define IXGBE_5TUPLE_MIN_PRI 1
116 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/
117 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000
118 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/
119 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0
121 #define IXGBE_RSS_OFFLOAD_ALL ( \
123 ETH_RSS_NONFRAG_IPV4_TCP | \
124 ETH_RSS_NONFRAG_IPV4_UDP | \
126 ETH_RSS_NONFRAG_IPV6_TCP | \
127 ETH_RSS_NONFRAG_IPV6_UDP | \
129 ETH_RSS_IPV6_TCP_EX | \
132 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
133 #define IXGBE_VF_MAXMSIVECTOR 1
135 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
136 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
139 * Information about the fdir mode.
142 struct ixgbe_hw_fdir_mask {
143 uint16_t vlan_tci_mask;
144 uint32_t src_ipv4_mask;
145 uint32_t dst_ipv4_mask;
146 uint16_t src_ipv6_mask;
147 uint16_t dst_ipv6_mask;
148 uint16_t src_port_mask;
149 uint16_t dst_port_mask;
150 uint16_t flex_bytes_mask;
151 uint8_t mac_addr_byte_mask;
152 uint32_t tunnel_id_mask;
153 uint8_t tunnel_type_mask;
156 struct ixgbe_hw_fdir_info {
157 struct ixgbe_hw_fdir_mask mask;
158 uint8_t flex_bytes_offset;
169 /* structure for interrupt relative data */
170 struct ixgbe_interrupt {
173 /*to save original mask during delayed handler */
174 uint32_t mask_original;
177 struct ixgbe_stat_mapping_registers {
178 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
179 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
183 uint32_t vfta[IXGBE_VFTA_SIZE];
186 struct ixgbe_hwstrip {
187 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
191 * VF data which used by PF host only
193 #define IXGBE_MAX_VF_MC_ENTRIES 30
194 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
195 #define IXGBE_MAX_UTA 128
197 struct ixgbe_uta_info {
198 uint8_t uc_filter_type;
200 uint32_t uta_shadow[IXGBE_MAX_UTA];
203 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
205 struct ixgbe_mirror_info {
206 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
207 /**< store PF mirror rules configuration*/
210 struct ixgbe_vf_info {
211 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
212 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
213 uint16_t num_vf_mc_hashes;
214 uint16_t default_vf_vlan_id;
215 uint16_t vlans_enabled;
217 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
219 uint8_t spoofchk_enabled;
224 * Possible l4type of 5tuple filters.
226 enum ixgbe_5tuple_protocol {
227 IXGBE_FILTER_PROTOCOL_TCP = 0,
228 IXGBE_FILTER_PROTOCOL_UDP,
229 IXGBE_FILTER_PROTOCOL_SCTP,
230 IXGBE_FILTER_PROTOCOL_NONE,
233 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
235 struct ixgbe_5tuple_filter_info {
240 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
241 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
242 used when more than one filter matches. */
243 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
244 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
245 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
246 src_port_mask:1, /* if mask is 1b, do not compare src port. */
247 proto_mask:1; /* if mask is 1b, do not compare protocol. */
250 /* 5tuple filter structure */
251 struct ixgbe_5tuple_filter {
252 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
253 uint16_t index; /* the index of 5tuple filter */
254 struct ixgbe_5tuple_filter_info filter_info;
255 uint16_t queue; /* rx queue assigned to */
258 #define IXGBE_5TUPLE_ARRAY_SIZE \
259 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
260 (sizeof(uint32_t) * NBBY))
263 * Structure to store filters' info.
265 struct ixgbe_filter_info {
266 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
267 /* store used ethertype filters*/
268 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
269 /* Bit mask for every used 5tuple filter */
270 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
271 struct ixgbe_5tuple_filter_list fivetuple_list;
275 * Structure to store private data for each driver instance (for each port).
277 struct ixgbe_adapter {
279 struct ixgbe_hw_stats stats;
280 struct ixgbe_hw_fdir_info fdir;
281 struct ixgbe_interrupt intr;
282 struct ixgbe_stat_mapping_registers stat_mappings;
283 struct ixgbe_vfta shadow_vfta;
284 struct ixgbe_hwstrip hwstrip;
285 struct ixgbe_dcb_config dcb_config;
286 struct ixgbe_mirror_info mr_data;
287 struct ixgbe_vf_info *vfdata;
288 struct ixgbe_uta_info uta_info;
289 #ifdef RTE_NIC_BYPASS
290 struct ixgbe_bypass_info bps;
291 #endif /* RTE_NIC_BYPASS */
292 struct ixgbe_filter_info filter;
294 bool rx_bulk_alloc_allowed;
296 struct rte_timecounter systime_tc;
297 struct rte_timecounter rx_tstamp_tc;
298 struct rte_timecounter tx_tstamp_tc;
301 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
302 (&((struct ixgbe_adapter *)adapter)->hw)
304 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
305 (&((struct ixgbe_adapter *)adapter)->stats)
307 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
308 (&((struct ixgbe_adapter *)adapter)->intr)
310 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
311 (&((struct ixgbe_adapter *)adapter)->fdir)
313 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
314 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
316 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
317 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
319 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
320 (&((struct ixgbe_adapter *)adapter)->hwstrip)
322 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
323 (&((struct ixgbe_adapter *)adapter)->dcb_config)
325 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
326 (&((struct ixgbe_adapter *)adapter)->vfdata)
328 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
329 (&((struct ixgbe_adapter *)adapter)->mr_data)
331 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
332 (&((struct ixgbe_adapter *)adapter)->uta_info)
334 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
335 (&((struct ixgbe_adapter *)adapter)->filter)
338 * RX/TX function prototypes
340 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
342 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
344 void ixgbe_dev_rx_queue_release(void *rxq);
346 void ixgbe_dev_tx_queue_release(void *txq);
348 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
349 uint16_t nb_rx_desc, unsigned int socket_id,
350 const struct rte_eth_rxconf *rx_conf,
351 struct rte_mempool *mb_pool);
353 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
354 uint16_t nb_tx_desc, unsigned int socket_id,
355 const struct rte_eth_txconf *tx_conf);
357 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
358 uint16_t rx_queue_id);
360 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
361 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
363 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
365 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
367 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
369 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
371 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
373 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
375 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
377 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
378 struct rte_eth_rxq_info *qinfo);
380 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
381 struct rte_eth_txq_info *qinfo);
383 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
385 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
387 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
389 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
392 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
395 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
396 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
397 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
398 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
400 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
403 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
406 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
407 struct rte_eth_rss_conf *rss_conf);
409 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
410 struct rte_eth_rss_conf *rss_conf);
412 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
414 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
416 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
418 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
420 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
423 * Flow director function prototypes
425 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
427 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
430 * misc function prototypes
432 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
434 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
436 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
438 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
440 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
442 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
444 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
446 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
448 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
450 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
451 enum rte_filter_op filter_op, void *arg);
452 #endif /* _IXGBE_ETHDEV_H_ */