drivers/net/ixgbe/ixgbe_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdarg.h>
  37 #include <errno.h>
  38 #include <sys/queue.h>
  39
  40 #include <rte_interrupts.h>
  41 #include <rte_log.h>
  42 #include <rte_debug.h>
  43 #include <rte_pci.h>
  44 #include <rte_ether.h>
  45 #include <rte_ethdev.h>
  46 #include <rte_malloc.h>
  47
  48 #include "ixgbe_logs.h"
  49 #include "base/ixgbe_api.h"
  50 #include "base/ixgbe_common.h"
  51 #include "ixgbe_ethdev.h"
  52
  53 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
  54 #define FDIRCTRL_PBALLOC_MASK           0x03
  55
  56 /* For calculating memory required for FDIR filters */
  57 #define PBALLOC_SIZE_SHIFT              15
  58
  59 /* Number of bits used to mask bucket hash for different pballoc sizes */
  60 #define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
  61 #define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
  62 #define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
  63 #define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
  64 #define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
  65 #define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
  66 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
  67 #define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
  68 #define IXGBE_MAX_FLX_SOURCE_OFF        62
  69 #define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
  70 #define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
  71
  72 #define IXGBE_FDIR_FLOW_TYPES ( \
  73         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  74         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  75         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  76         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  77         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  78         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  79         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  80         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
  81
  82 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
  83         uint8_t ipv6_addr[16]; \
  84         uint8_t i; \
  85         rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
  86         (ipv6m) = 0; \
  87         for (i = 0; i < sizeof(ipv6_addr); i++) { \
  88                 if (ipv6_addr[i] == UINT8_MAX) \
  89                         (ipv6m) |= 1 << i; \
  90                 else if (ipv6_addr[i] != 0) { \
  91                         PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
  92                         return -EINVAL; \
  93                 } \
  94         } \
  95 } while (0)
  96
  97 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
  98         uint8_t ipv6_addr[16]; \
  99         uint8_t i; \
 100         for (i = 0; i < sizeof(ipv6_addr); i++) { \
 101                 if ((ipv6m) & (1 << i)) \
 102                         ipv6_addr[i] = UINT8_MAX; \
 103                 else \
 104                         ipv6_addr[i] = 0; \
 105         } \
 106         rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
 107 } while (0)
 108
 109 #define DEFAULT_VXLAN_PORT 4789
 110 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
 111
 112 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
 113 static int fdir_set_input_mask(struct rte_eth_dev *dev,
 114                                const struct rte_eth_fdir_masks *input_mask);
 115 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
 116 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
 117 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 118                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
 119 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
 120 static int ixgbe_fdir_filter_to_atr_input(
 121                 const struct rte_eth_fdir_filter *fdir_filter,
 122                 union ixgbe_atr_input *input,
 123                 enum rte_fdir_mode mode);
 124 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 125                                  uint32_t key);
 126 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 127                 enum rte_fdir_pballoc_type pballoc);
 128 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 129                 enum rte_fdir_pballoc_type pballoc);
 130 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 131                         union ixgbe_atr_input *input, uint8_t queue,
 132                         uint32_t fdircmd, uint32_t fdirhash,
 133                         enum rte_fdir_mode mode);
 134 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 135                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
 136                 uint32_t fdirhash);
 137 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 138                               const struct rte_eth_fdir_filter *fdir_filter,
 139                               bool del,
 140                               bool update);
 141 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
 142 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
 143                         struct rte_eth_fdir_info *fdir_info);
 144 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
 145                         struct rte_eth_fdir_stats *fdir_stats);
 146
 147 /**
 148  * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
 149  * It adds extra configuration of fdirctrl that is common for all filter types.
 150  *
 151  *  Initialize Flow Director control registers
 152  *  @hw: pointer to hardware structure
 153  *  @fdirctrl: value to write to flow director control register
 154  **/
 155 static int
 156 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
 157 {
 158         int i;
 159
 160         PMD_INIT_FUNC_TRACE();
 161
 162         /* Prime the keys for hashing */
 163         IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
 164         IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 165
 166         /*
 167          * Continue setup of fdirctrl register bits:
 168          *  Set the maximum length per hash bucket to 0xA filters
 169          *  Send interrupt when 64 filters are left
 170          */
 171         fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 172                     (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 173
 174         /*
 175          * Poll init-done after we write the register.  Estimated times:
 176          *      10G: PBALLOC = 11b, timing is 60us
 177          *       1G: PBALLOC = 11b, timing is 600us
 178          *     100M: PBALLOC = 11b, timing is 6ms
 179          *
 180          *     Multiple these timings by 4 if under full Rx load
 181          *
 182          * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 183          * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 184          * this might not finish in our poll time, but we can live with that
 185          * for now.
 186          */
 187         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 188         IXGBE_WRITE_FLUSH(hw);
 189         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 190                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 191                                    IXGBE_FDIRCTRL_INIT_DONE)
 192                         break;
 193                 msec_delay(1);
 194         }
 195
 196         if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 197                 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
 198                 return -ETIMEDOUT;
 199         }
 200         return 0;
 201 }
 202
 203 /*
 204  * Set appropriate bits in fdirctrl for: variable reporting levels, moving
 205  * flexbytes matching field, and drop queue (only for perfect matching mode).
 206  */
 207 static inline int
 208 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 209 {
 210         *fdirctrl = 0;
 211
 212         switch (conf->pballoc) {
 213         case RTE_FDIR_PBALLOC_64K:
 214                 /* 8k - 1 signature filters */
 215                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
 216                 break;
 217         case RTE_FDIR_PBALLOC_128K:
 218                 /* 16k - 1 signature filters */
 219                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
 220                 break;
 221         case RTE_FDIR_PBALLOC_256K:
 222                 /* 32k - 1 signature filters */
 223                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 224                 break;
 225         default:
 226                 /* bad value */
 227                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
 228                 return -EINVAL;
 229         };
 230
 231         /* status flags: write hash & swindex in the rx descriptor */
 232         switch (conf->status) {
 233         case RTE_FDIR_NO_REPORT_STATUS:
 234                 /* do nothing, default mode */
 235                 break;
 236         case RTE_FDIR_REPORT_STATUS:
 237                 /* report status when the packet matches a fdir rule */
 238                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 239                 break;
 240         case RTE_FDIR_REPORT_STATUS_ALWAYS:
 241                 /* always report status */
 242                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
 243                 break;
 244         default:
 245                 /* bad value */
 246                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
 247                 return -EINVAL;
 248         };
 249
 250         *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
 251                      IXGBE_FDIRCTRL_FLEX_SHIFT;
 252
 253         if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
 254             conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 255                 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 256                 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
 257                 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 258                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
 259                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 260                 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 261                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
 262                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 263         }
 264
 265         return 0;
 266 }
 267
 268 /**
 269  * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
 270  *
 271  *  @hi_dword: Bits 31:16 mask to be bit swapped.
 272  *  @lo_dword: Bits 15:0  mask to be bit swapped.
 273  *
 274  *  Flow director uses several registers to store 2 x 16 bit masks with the
 275  *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
 276  *  mask affects the MS bit/byte of the target. This function reverses the
 277  *  bits in these masks.
 278  *  **/
 279 static inline uint32_t
 280 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 281 {
 282         uint32_t mask = hi_dword << 16;
 283
 284         mask |= lo_dword;
 285         mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 286         mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
 287         mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
 288         return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 289 }
 290
 291 /*
 292  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 293  * but makes use of the rte_fdir_masks structure to see which bits to set.
 294  */
 295 static int
 296 fdir_set_input_mask_82599(struct rte_eth_dev *dev)
 297 {
 298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 299         struct ixgbe_hw_fdir_info *info =
 300                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 301         /*
 302          * mask VM pool and DIPv6 since there are currently not supported
 303          * mask FLEX byte, it will be set in flex_conf
 304          */
 305         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
 306         uint32_t fdirtcpm;  /* TCP source and destination port masks. */
 307         uint32_t fdiripv6m; /* IPv6 source and destination masks. */
 308         volatile uint32_t *reg;
 309
 310         PMD_INIT_FUNC_TRACE();
 311
 312         /*
 313          * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 314          * are zero, then assume a full mask for that field. Also assume that
 315          * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 316          * cannot be masked out in this implementation.
 317          */
 318         if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
 319                 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
 320                 fdirm |= IXGBE_FDIRM_L4P;
 321
 322         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 323                 /* mask VLAN Priority */
 324                 fdirm |= IXGBE_FDIRM_VLANP;
 325         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 326                 /* mask VLAN ID */
 327                 fdirm |= IXGBE_FDIRM_VLANID;
 328         else if (info->mask.vlan_tci_mask == 0)
 329                 /* mask VLAN ID and Priority */
 330                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 331         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 332                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 333                 return -EINVAL;
 334         }
 335
 336         /* flex byte mask */
 337         if (info->mask.flex_bytes_mask == 0)
 338                 fdirm |= IXGBE_FDIRM_FLEX;
 339
 340         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 341
 342         /* store the TCP/UDP port masks, bit reversed from port layout */
 343         fdirtcpm = reverse_fdir_bitmasks(
 344                         rte_be_to_cpu_16(info->mask.dst_port_mask),
 345                         rte_be_to_cpu_16(info->mask.src_port_mask));
 346
 347         /* write all the same so that UDP, TCP and SCTP use the same mask
 348          * (little-endian)
 349          */
 350         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 351         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
 352         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
 353
 354         /* Store source and destination IPv4 masks (big-endian),
 355          * can not use IXGBE_WRITE_REG.
 356          */
 357         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
 358         *reg = ~(info->mask.src_ipv4_mask);
 359         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
 360         *reg = ~(info->mask.dst_ipv4_mask);
 361
 362         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
 363                 /*
 364                  * Store source and destination IPv6 masks (bit reversed)
 365                  */
 366                 fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
 367                             info->mask.src_ipv6_mask;
 368
 369                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
 370         }
 371
 372         return IXGBE_SUCCESS;
 373 }
 374
 375 /*
 376  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 377  * but makes use of the rte_fdir_masks structure to see which bits to set.
 378  */
 379 static int
 380 fdir_set_input_mask_x550(struct rte_eth_dev *dev)
 381 {
 382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 383         struct ixgbe_hw_fdir_info *info =
 384                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 385         /* mask VM pool and DIPv6 since there are currently not supported
 386          * mask FLEX byte, it will be set in flex_conf
 387          */
 388         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
 389                          IXGBE_FDIRM_FLEX;
 390         uint32_t fdiripv6m;
 391         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 392         uint16_t mac_mask;
 393
 394         PMD_INIT_FUNC_TRACE();
 395
 396         /* set the default UDP port for VxLAN */
 397         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 398                 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
 399
 400         /* some bits must be set for mac vlan or tunnel mode */
 401         fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
 402
 403         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 404                 /* mask VLAN Priority */
 405                 fdirm |= IXGBE_FDIRM_VLANP;
 406         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 407                 /* mask VLAN ID */
 408                 fdirm |= IXGBE_FDIRM_VLANID;
 409         else if (info->mask.vlan_tci_mask == 0)
 410                 /* mask VLAN ID and Priority */
 411                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 412         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 413                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 414                 return -EINVAL;
 415         }
 416
 417         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 418
 419         fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
 420         fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
 421         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 422                 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
 423                                 IXGBE_FDIRIP6M_TNI_VNI;
 424
 425         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 426                 fdiripv6m |= IXGBE_FDIRIP6M_INNER_MAC;
 427                 mac_mask = info->mask.mac_addr_byte_mask &
 428                         (IXGBE_FDIRIP6M_INNER_MAC >>
 429                         IXGBE_FDIRIP6M_INNER_MAC_SHIFT);
 430                 fdiripv6m &= ~((mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) &
 431                                 IXGBE_FDIRIP6M_INNER_MAC);
 432
 433                 switch (info->mask.tunnel_type_mask) {
 434                 case 0:
 435                         /* Mask turnnel type */
 436                         fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
 437                         break;
 438                 case 1:
 439                         break;
 440                 default:
 441                         PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
 442                         return -EINVAL;
 443                 }
 444
 445                 switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
 446                 case 0x0:
 447                         /* Mask vxlan id */
 448                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
 449                         break;
 450                 case 0x00FFFFFF:
 451                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
 452                         break;
 453                 case 0xFFFFFFFF:
 454                         break;
 455                 default:
 456                         PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
 457                         return -EINVAL;
 458                 }
 459         }
 460
 461         IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
 462         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
 463         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
 464         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
 465         IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
 466         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
 467
 468         return IXGBE_SUCCESS;
 469 }
 470
 471 static int
 472 ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
 473                                   const struct rte_eth_fdir_masks *input_mask)
 474 {
 475         struct ixgbe_hw_fdir_info *info =
 476                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 477         uint16_t dst_ipv6m = 0;
 478         uint16_t src_ipv6m = 0;
 479
 480         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 481         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 482         info->mask.src_port_mask = input_mask->src_port_mask;
 483         info->mask.dst_port_mask = input_mask->dst_port_mask;
 484         info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
 485         info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
 486         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
 487         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
 488         info->mask.src_ipv6_mask = src_ipv6m;
 489         info->mask.dst_ipv6_mask = dst_ipv6m;
 490
 491         return IXGBE_SUCCESS;
 492 }
 493
 494 static int
 495 ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
 496                                  const struct rte_eth_fdir_masks *input_mask)
 497 {
 498         struct ixgbe_hw_fdir_info *info =
 499                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 500
 501         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 502         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 503         info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
 504         info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
 505         info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
 506
 507         return IXGBE_SUCCESS;
 508 }
 509
 510 static int
 511 ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
 512                             const struct rte_eth_fdir_masks *input_mask)
 513 {
 514         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 515
 516         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 517             mode <= RTE_FDIR_MODE_PERFECT)
 518                 return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
 519         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 520                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 521                 return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
 522
 523         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 524         return -ENOTSUP;
 525 }
 526
 527 int
 528 ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
 529 {
 530         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 531
 532         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 533             mode <= RTE_FDIR_MODE_PERFECT)
 534                 return fdir_set_input_mask_82599(dev);
 535         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 536                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 537                 return fdir_set_input_mask_x550(dev);
 538
 539         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 540         return -ENOTSUP;
 541 }
 542
 543 int
 544 ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
 545                                 uint16_t offset)
 546 {
 547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 548         uint32_t fdirctrl;
 549         int i;
 550
 551         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
 552
 553         fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 554         fdirctrl |= ((offset >> 1) /* convert to word offset */
 555                 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 556
 557         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 558         IXGBE_WRITE_FLUSH(hw);
 559         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 560                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 561                         IXGBE_FDIRCTRL_INIT_DONE)
 562                         break;
 563                 msec_delay(1);
 564         }
 565         return 0;
 566 }
 567
 568 static int
 569 fdir_set_input_mask(struct rte_eth_dev *dev,
 570                     const struct rte_eth_fdir_masks *input_mask)
 571 {
 572         int ret;
 573
 574         ret = ixgbe_fdir_store_input_mask(dev, input_mask);
 575         if (ret)
 576                 return ret;
 577
 578         return ixgbe_fdir_set_input_mask(dev);
 579 }
 580
 581 /*
 582  * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
 583  * arguments are valid
 584  */
 585 static int
 586 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 587                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
 588 {
 589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 590         struct ixgbe_hw_fdir_info *info =
 591                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 592         const struct rte_eth_flex_payload_cfg *flex_cfg;
 593         const struct rte_eth_fdir_flex_mask *flex_mask;
 594         uint32_t fdirm;
 595         uint16_t flexbytes = 0;
 596         uint16_t i;
 597
 598         fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
 599
 600         if (conf == NULL) {
 601                 PMD_DRV_LOG(ERR, "NULL pointer.");
 602                 return -EINVAL;
 603         }
 604
 605         for (i = 0; i < conf->nb_payloads; i++) {
 606                 flex_cfg = &conf->flex_set[i];
 607                 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
 608                         PMD_DRV_LOG(ERR, "unsupported payload type.");
 609                         return -EINVAL;
 610                 }
 611                 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
 612                     (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
 613                     (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
 614                         *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 615                         *fdirctrl |=
 616                                 (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
 617                                         IXGBE_FDIRCTRL_FLEX_SHIFT;
 618                 } else {
 619                         PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
 620                         return -EINVAL;
 621                 }
 622         }
 623
 624         for (i = 0; i < conf->nb_flexmasks; i++) {
 625                 flex_mask = &conf->flex_mask[i];
 626                 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
 627                         PMD_DRV_LOG(ERR, "flexmask should be set globally.");
 628                         return -EINVAL;
 629                 }
 630                 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
 631                                         ((flex_mask->mask[1]) & 0xFF));
 632                 if (flexbytes == UINT16_MAX)
 633                         fdirm &= ~IXGBE_FDIRM_FLEX;
 634                 else if (flexbytes != 0) {
 635                         /* IXGBE_FDIRM_FLEX is set by default when set mask */
 636                         PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
 637                         return -EINVAL;
 638                 }
 639         }
 640         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 641         info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
 642         info->flex_bytes_offset = (uint8_t)((*fdirctrl &
 643                                             IXGBE_FDIRCTRL_FLEX_MASK) >>
 644                                             IXGBE_FDIRCTRL_FLEX_SHIFT);
 645         return 0;
 646 }
 647
 648 int
 649 ixgbe_fdir_configure(struct rte_eth_dev *dev)
 650 {
 651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 652         int err;
 653         uint32_t fdirctrl, pbsize;
 654         int i;
 655         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 656
 657         PMD_INIT_FUNC_TRACE();
 658
 659         if (hw->mac.type != ixgbe_mac_82599EB &&
 660                 hw->mac.type != ixgbe_mac_X540 &&
 661                 hw->mac.type != ixgbe_mac_X550 &&
 662                 hw->mac.type != ixgbe_mac_X550EM_x &&
 663                 hw->mac.type != ixgbe_mac_X550EM_a)
 664                 return -ENOSYS;
 665
 666         /* x550 supports mac-vlan and tunnel mode but other NICs not */
 667         if (hw->mac.type != ixgbe_mac_X550 &&
 668             hw->mac.type != ixgbe_mac_X550EM_x &&
 669             hw->mac.type != ixgbe_mac_X550EM_a &&
 670             mode != RTE_FDIR_MODE_SIGNATURE &&
 671             mode != RTE_FDIR_MODE_PERFECT)
 672                 return -ENOSYS;
 673
 674         err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
 675         if (err)
 676                 return err;
 677
 678         /*
 679          * Before enabling Flow Director, the Rx Packet Buffer size
 680          * must be reduced.  The new value is the current size minus
 681          * flow director memory usage size.
 682          */
 683         pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
 684         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
 685             (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 686
 687         /*
 688          * The defaults in the HW for RX PB 1-7 are not zero and so should be
 689          * initialized to zero for non DCB mode otherwise actual total RX PB
 690          * would be bigger than programmed and filter space would run into
 691          * the PB 0 region.
 692          */
 693         for (i = 1; i < 8; i++)
 694                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
 695
 696         err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
 697         if (err < 0) {
 698                 PMD_INIT_LOG(ERR, " Error on setting FD mask");
 699                 return err;
 700         }
 701         err = ixgbe_set_fdir_flex_conf(dev,
 702                 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
 703         if (err < 0) {
 704                 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
 705                 return err;
 706         }
 707
 708         err = fdir_enable_82599(hw, fdirctrl);
 709         if (err < 0) {
 710                 PMD_INIT_LOG(ERR, " Error on enabling FD.");
 711                 return err;
 712         }
 713         return 0;
 714 }
 715
 716 /*
 717  * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
 718  * by the IXGBE driver code.
 719  */
 720 static int
 721 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 722                 union ixgbe_atr_input *input, enum rte_fdir_mode mode)
 723 {
 724         input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
 725         input->formatted.flex_bytes = (uint16_t)(
 726                 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
 727                 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
 728
 729         switch (fdir_filter->input.flow_type) {
 730         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 731                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
 732                 break;
 733         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 734                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
 735                 break;
 736         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 737                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
 738                 break;
 739         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 740                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
 741                 break;
 742         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 743                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
 744                 break;
 745         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 746                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
 747                 break;
 748         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 749                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
 750                 break;
 751         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 752                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
 753                 break;
 754         default:
 755                 break;
 756         }
 757
 758         switch (fdir_filter->input.flow_type) {
 759         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 760         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 761                 input->formatted.src_port =
 762                         fdir_filter->input.flow.udp4_flow.src_port;
 763                 input->formatted.dst_port =
 764                         fdir_filter->input.flow.udp4_flow.dst_port;
 765                 /* fall-through */
 766         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 767         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 768         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 769                 input->formatted.src_ip[0] =
 770                         fdir_filter->input.flow.ip4_flow.src_ip;
 771                 input->formatted.dst_ip[0] =
 772                         fdir_filter->input.flow.ip4_flow.dst_ip;
 773                 break;
 774
 775         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 776         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 777                 input->formatted.src_port =
 778                         fdir_filter->input.flow.udp6_flow.src_port;
 779                 input->formatted.dst_port =
 780                         fdir_filter->input.flow.udp6_flow.dst_port;
 781                 /* fall-through */
 782         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 783         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 784         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 785                 rte_memcpy(input->formatted.src_ip,
 786                            fdir_filter->input.flow.ipv6_flow.src_ip,
 787                            sizeof(input->formatted.src_ip));
 788                 rte_memcpy(input->formatted.dst_ip,
 789                            fdir_filter->input.flow.ipv6_flow.dst_ip,
 790                            sizeof(input->formatted.dst_ip));
 791                 break;
 792         default:
 793                 break;
 794         }
 795
 796         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 797                 rte_memcpy(
 798                         input->formatted.inner_mac,
 799                         fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
 800                         sizeof(input->formatted.inner_mac));
 801         } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 802                 rte_memcpy(
 803                         input->formatted.inner_mac,
 804                         fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
 805                         sizeof(input->formatted.inner_mac));
 806                 if (fdir_filter->input.flow.tunnel_flow.tunnel_type ==
 807                                 RTE_FDIR_TUNNEL_TYPE_VXLAN)
 808                         input->formatted.tunnel_type =
 809                                         IXGBE_FDIR_VXLAN_TUNNEL_TYPE;
 810                 else if (fdir_filter->input.flow.tunnel_flow.tunnel_type ==
 811                                 RTE_FDIR_TUNNEL_TYPE_NVGRE)
 812                         input->formatted.tunnel_type =
 813                                         IXGBE_FDIR_NVGRE_TUNNEL_TYPE;
 814                 else
 815                         PMD_DRV_LOG(ERR, " invalid tunnel type arguments.");
 816
 817                 input->formatted.tni_vni =
 818                         fdir_filter->input.flow.tunnel_flow.tunnel_id >> 8;
 819         }
 820
 821         return 0;
 822 }
 823
 824 /*
 825  * The below function is taken from the FreeBSD IXGBE drivers release
 826  * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
 827  * before returning, as the signature hash can use 16bits.
 828  *
 829  * The newer driver has optimised functions for calculating bucket and
 830  * signature hashes. However they don't support IPv6 type packets for signature
 831  * filters so are not used here.
 832  *
 833  * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
 834  * set.
 835  *
 836  * Compute the hashes for SW ATR
 837  *  @stream: input bitstream to compute the hash on
 838  *  @key: 32-bit hash key
 839  **/
 840 static uint32_t
 841 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 842                                  uint32_t key)
 843 {
 844         /*
 845          * The algorithm is as follows:
 846          *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
 847          *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
 848          *    and A[n] x B[n] is bitwise AND between same length strings
 849          *
 850          *    K[n] is 16 bits, defined as:
 851          *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
 852          *       for n modulo 32 < 15, K[n] =
 853          *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 854          *
 855          *    S[n] is 16 bits, defined as:
 856          *       for n >= 15, S[n] = S[n:n - 15]
 857          *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 858          *
 859          *    To simplify for programming, the algorithm is implemented
 860          *    in software this way:
 861          *
 862          *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 863          *
 864          *    for (i = 0; i < 352; i+=32)
 865          *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
 866          *
 867          *    lo_hash_dword[15:0]  ^= Stream[15:0];
 868          *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
 869          *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
 870          *
 871          *    hi_hash_dword[31:0]  ^= Stream[351:320];
 872          *
 873          *    if (key[0])
 874          *        hash[15:0] ^= Stream[15:0];
 875          *
 876          *    for (i = 0; i < 16; i++) {
 877          *        if (key[i])
 878          *            hash[15:0] ^= lo_hash_dword[(i+15):i];
 879          *        if (key[i + 16])
 880          *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 881          *    }
 882          *
 883          */
 884         __be32 common_hash_dword = 0;
 885         u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 886         u32 hash_result = 0;
 887         u8 i;
 888
 889         /* record the flow_vm_vlan bits as they are a key part to the hash */
 890         flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 891
 892         /* generate common hash dword */
 893         for (i = 1; i <= 13; i++)
 894                 common_hash_dword ^= atr_input->dword_stream[i];
 895
 896         hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
 897
 898         /* low dword is word swapped version of common */
 899         lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 900
 901         /* apply flow ID/VM pool/VLAN ID bits to hash words */
 902         hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 903
 904         /* Process bits 0 and 16 */
 905         if (key & 0x0001)
 906                 hash_result ^= lo_hash_dword;
 907         if (key & 0x00010000)
 908                 hash_result ^= hi_hash_dword;
 909
 910         /*
 911          * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 912          * delay this because bit 0 of the stream should not be processed
 913          * so we do not add the vlan until after bit 0 was processed
 914          */
 915         lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 916
 917
 918         /* process the remaining 30 bits in the key 2 bits at a time */
 919         for (i = 15; i; i--) {
 920                 if (key & (0x0001 << i))
 921                         hash_result ^= lo_hash_dword >> i;
 922                 if (key & (0x00010000 << i))
 923                         hash_result ^= hi_hash_dword >> i;
 924         }
 925
 926         return hash_result;
 927 }
 928
 929 static uint32_t
 930 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 931                 enum rte_fdir_pballoc_type pballoc)
 932 {
 933         if (pballoc == RTE_FDIR_PBALLOC_256K)
 934                 return ixgbe_atr_compute_hash_82599(input,
 935                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 936                                 PERFECT_BUCKET_256KB_HASH_MASK;
 937         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 938                 return ixgbe_atr_compute_hash_82599(input,
 939                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 940                                 PERFECT_BUCKET_128KB_HASH_MASK;
 941         else
 942                 return ixgbe_atr_compute_hash_82599(input,
 943                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 944                                 PERFECT_BUCKET_64KB_HASH_MASK;
 945 }
 946
 947 /**
 948  * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
 949  * @hw: pointer to hardware structure
 950  */
 951 static inline int
 952 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
 953 {
 954         int i;
 955
 956         for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 957                 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
 958                 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
 959                         return 0;
 960                 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
 961         }
 962
 963         return -ETIMEDOUT;
 964 }
 965
 966 /*
 967  * Calculate the hash value needed for signature-match filters. In the FreeBSD
 968  * driver, this is done by the optimised function
 969  * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
 970  * doesn't support calculating a hash for an IPv6 filter.
 971  */
 972 static uint32_t
 973 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 974                 enum rte_fdir_pballoc_type pballoc)
 975 {
 976         uint32_t bucket_hash, sig_hash;
 977
 978         if (pballoc == RTE_FDIR_PBALLOC_256K)
 979                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 980                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 981                                 SIG_BUCKET_256KB_HASH_MASK;
 982         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 983                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 984                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 985                                 SIG_BUCKET_128KB_HASH_MASK;
 986         else
 987                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 988                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 989                                 SIG_BUCKET_64KB_HASH_MASK;
 990
 991         sig_hash = ixgbe_atr_compute_hash_82599(input,
 992                         IXGBE_ATR_SIGNATURE_HASH_KEY);
 993
 994         return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
 995 }
 996
 997 /*
 998  * This is based on ixgbe_fdir_write_perfect_filter_82599() in
 999  * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
1000  * added, and IPv6 support also added. The hash value is also pre-calculated
1001  * as the pballoc value is needed to do it.
1002  */
1003 static int
1004 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1005                         union ixgbe_atr_input *input, uint8_t queue,
1006                         uint32_t fdircmd, uint32_t fdirhash,
1007                         enum rte_fdir_mode mode)
1008 {
1009         uint32_t fdirport, fdirvlan;
1010         u32 addr_low, addr_high;
1011         u32 tunnel_type = 0;
1012         int err = 0;
1013         volatile uint32_t *reg;
1014
1015         if (mode == RTE_FDIR_MODE_PERFECT) {
1016                 /* record the IPv4 address (big-endian)
1017                  * can not use IXGBE_WRITE_REG.
1018                  */
1019                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
1020                 *reg = input->formatted.src_ip[0];
1021                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
1022                 *reg = input->formatted.dst_ip[0];
1023
1024                 /* record source and destination port (little-endian)*/
1025                 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1026                 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1027                 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1028                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1029         } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1030                    mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
1031                 /* for mac vlan and tunnel modes */
1032                 addr_low = ((u32)input->formatted.inner_mac[0] |
1033                             ((u32)input->formatted.inner_mac[1] << 8) |
1034                             ((u32)input->formatted.inner_mac[2] << 16) |
1035                             ((u32)input->formatted.inner_mac[3] << 24));
1036                 addr_high = ((u32)input->formatted.inner_mac[4] |
1037                              ((u32)input->formatted.inner_mac[5] << 8));
1038
1039                 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
1040                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1041                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
1042                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1043                 } else {
1044                         /* tunnel mode */
1045                         if (input->formatted.tunnel_type)
1046                                 tunnel_type = 0x80000000;
1047                         tunnel_type |= addr_high;
1048                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1049                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1050                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1051                                         input->formatted.tni_vni);
1052                 }
1053                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, 0);
1054                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, 0);
1055                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, 0);
1056         }
1057
1058         /* record vlan (little-endian) and flex_bytes(big-endian) */
1059         fdirvlan = input->formatted.flex_bytes;
1060         fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1061         fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1062         IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1063
1064         /* configure FDIRHASH register */
1065         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1066
1067         /*
1068          * flush all previous writes to make certain registers are
1069          * programmed prior to issuing the command
1070          */
1071         IXGBE_WRITE_FLUSH(hw);
1072
1073         /* configure FDIRCMD register */
1074         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1075                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1076         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1077         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1078         fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1079
1080         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1081
1082         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1083
1084         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1085         if (err < 0)
1086                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1087
1088         return err;
1089 }
1090
1091 /**
1092  * This function is based on ixgbe_atr_add_signature_filter_82599() in
1093  * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1094  * setting extra fields in the FDIRCMD register, and removes the code that was
1095  * verifying the flow_type field. According to the documentation, a flow type of
1096  * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1097  * work ok...
1098  *
1099  *  Adds a signature hash filter
1100  *  @hw: pointer to hardware structure
1101  *  @input: unique input dword
1102  *  @queue: queue index to direct traffic to
1103  *  @fdircmd: any extra flags to set in fdircmd register
1104  *  @fdirhash: pre-calculated hash value for the filter
1105  **/
1106 static int
1107 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1108                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1109                 uint32_t fdirhash)
1110 {
1111         int err = 0;
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         /* configure FDIRCMD register */
1116         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1117                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1118         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1119         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1120
1121         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1122         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1123
1124         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1125
1126         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1127         if (err < 0)
1128                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1129
1130         return err;
1131 }
1132
1133 /*
1134  * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1135  * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1136  * that it can be used for removing signature and perfect filters.
1137  */
1138 static int
1139 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1140 {
1141         uint32_t fdircmd = 0;
1142         int err = 0;
1143
1144         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1145
1146         /* flush hash to HW */
1147         IXGBE_WRITE_FLUSH(hw);
1148
1149         /* Query if filter is present */
1150         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1151
1152         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1153         if (err < 0) {
1154                 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1155                 return err;
1156         }
1157
1158         /* if filter exists in hardware then remove it */
1159         if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1160                 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1161                 IXGBE_WRITE_FLUSH(hw);
1162                 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1163                                 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1164         }
1165         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1166         if (err < 0)
1167                 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1168         return err;
1169
1170 }
1171
1172 static inline struct ixgbe_fdir_filter *
1173 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1174                          union ixgbe_atr_input *key)
1175 {
1176         int ret;
1177
1178         ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1179         if (ret < 0)
1180                 return NULL;
1181
1182         return fdir_info->hash_map[ret];
1183 }
1184
1185 static inline int
1186 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1187                          struct ixgbe_fdir_filter *fdir_filter)
1188 {
1189         int ret;
1190
1191         ret = rte_hash_add_key(fdir_info->hash_handle,
1192                                &fdir_filter->ixgbe_fdir);
1193
1194         if (ret < 0) {
1195                 PMD_DRV_LOG(ERR,
1196                             "Failed to insert fdir filter to hash table %d!",
1197                             ret);
1198                 return ret;
1199         }
1200
1201         fdir_info->hash_map[ret] = fdir_filter;
1202
1203         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1204
1205         return 0;
1206 }
1207
1208 static inline int
1209 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1210                          union ixgbe_atr_input *key)
1211 {
1212         int ret;
1213         struct ixgbe_fdir_filter *fdir_filter;
1214
1215         ret = rte_hash_del_key(fdir_info->hash_handle, key);
1216
1217         if (ret < 0) {
1218                 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1219                 return ret;
1220         }
1221
1222         fdir_filter = fdir_info->hash_map[ret];
1223         fdir_info->hash_map[ret] = NULL;
1224
1225         TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1226         rte_free(fdir_filter);
1227
1228         return 0;
1229 }
1230
1231 static int
1232 ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
1233                             const struct rte_eth_fdir_filter *fdir_filter,
1234                             struct ixgbe_fdir_rule *rule)
1235 {
1236         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1237         int err;
1238
1239         memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
1240
1241         err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
1242                                              &rule->ixgbe_fdir,
1243                                              fdir_mode);
1244         if (err)
1245                 return err;
1246
1247         rule->mode = fdir_mode;
1248         if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
1249                 rule->fdirflags = IXGBE_FDIRCMD_DROP;
1250         rule->queue = fdir_filter->action.rx_queue;
1251         rule->soft_id = fdir_filter->soft_id;
1252
1253         return 0;
1254 }
1255
1256 int
1257 ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
1258                           struct ixgbe_fdir_rule *rule,
1259                           bool del,
1260                           bool update)
1261 {
1262         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         uint32_t fdircmd_flags;
1264         uint32_t fdirhash;
1265         uint8_t queue;
1266         bool is_perfect = FALSE;
1267         int err;
1268         struct ixgbe_hw_fdir_info *info =
1269                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1270         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1271         struct ixgbe_fdir_filter *node;
1272         bool add_node = FALSE;
1273
1274         if (fdir_mode == RTE_FDIR_MODE_NONE ||
1275             fdir_mode != rule->mode)
1276                 return -ENOTSUP;
1277
1278         /*
1279          * Sanity check for x550.
1280          * When adding a new filter with flow type set to IPv4,
1281          * the flow director mask should be configed before,
1282          * and the L4 protocol and ports are masked.
1283          */
1284         if ((!del) &&
1285             (hw->mac.type == ixgbe_mac_X550 ||
1286              hw->mac.type == ixgbe_mac_X550EM_x ||
1287              hw->mac.type == ixgbe_mac_X550EM_a) &&
1288             (rule->ixgbe_fdir.formatted.flow_type ==
1289              IXGBE_ATR_FLOW_TYPE_IPV4 ||
1290              rule->ixgbe_fdir.formatted.flow_type ==
1291              IXGBE_ATR_FLOW_TYPE_IPV6) &&
1292             (info->mask.src_port_mask != 0 ||
1293              info->mask.dst_port_mask != 0) &&
1294             (rule->mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1295              rule->mode != RTE_FDIR_MODE_PERFECT_TUNNEL)) {
1296                 PMD_DRV_LOG(ERR, "By this device,"
1297                             " IPv4 is not supported without"
1298                             " L4 protocol and ports masked!");
1299                 return -ENOTSUP;
1300         }
1301
1302         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1303             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1304                 is_perfect = TRUE;
1305
1306         if (is_perfect) {
1307                 if (rule->ixgbe_fdir.formatted.flow_type &
1308                     IXGBE_ATR_L4TYPE_IPV6_MASK) {
1309                         PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1310                                     " perfect mode!");
1311                         return -ENOTSUP;
1312                 }
1313                 fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1314                                                           dev->data->dev_conf.fdir_conf.pballoc);
1315                 fdirhash |= rule->soft_id <<
1316                         IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1317         } else
1318                 fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1319                                                       dev->data->dev_conf.fdir_conf.pballoc);
1320
1321         if (del) {
1322                 err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1323                 if (err < 0)
1324                         return err;
1325
1326                 err = fdir_erase_filter_82599(hw, fdirhash);
1327                 if (err < 0)
1328                         PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1329                 else
1330                         PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1331                 return err;
1332         }
1333         /* add or update an fdir filter*/
1334         fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1335         if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1336                 if (is_perfect) {
1337                         queue = dev->data->dev_conf.fdir_conf.drop_queue;
1338                         fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1339                 } else {
1340                         PMD_DRV_LOG(ERR, "Drop option is not supported in"
1341                                     " signature mode.");
1342                         return -EINVAL;
1343                 }
1344         } else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
1345                 queue = (uint8_t)rule->queue;
1346         else
1347                 return -EINVAL;
1348
1349         node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
1350         if (node) {
1351                 if (update) {
1352                         node->fdirflags = fdircmd_flags;
1353                         node->fdirhash = fdirhash;
1354                         node->queue = queue;
1355                 } else {
1356                         PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1357                         return -EINVAL;
1358                 }
1359         } else {
1360                 add_node = TRUE;
1361                 node = rte_zmalloc("ixgbe_fdir",
1362                                    sizeof(struct ixgbe_fdir_filter),
1363                                    0);
1364                 if (!node)
1365                         return -ENOMEM;
1366                 rte_memcpy(&node->ixgbe_fdir,
1367                                  &rule->ixgbe_fdir,
1368                                  sizeof(union ixgbe_atr_input));
1369                 node->fdirflags = fdircmd_flags;
1370                 node->fdirhash = fdirhash;
1371                 node->queue = queue;
1372
1373                 err = ixgbe_insert_fdir_filter(info, node);
1374                 if (err < 0) {
1375                         rte_free(node);
1376                         return err;
1377                 }
1378         }
1379
1380         if (is_perfect) {
1381                 err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
1382                                                       queue, fdircmd_flags,
1383                                                       fdirhash, fdir_mode);
1384         } else {
1385                 err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
1386                                                       queue, fdircmd_flags,
1387                                                       fdirhash);
1388         }
1389         if (err < 0) {
1390                 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1391
1392                 if (add_node)
1393                         (void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1394         } else {
1395                 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1396         }
1397
1398         return err;
1399 }
1400
1401 /* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1402  * @dev: pointer to the structure rte_eth_dev
1403  * @fdir_filter: fdir filter entry
1404  * @del: 1 - delete, 0 - add
1405  * @update: 1 - update
1406  */
1407 static int
1408 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1409                           const struct rte_eth_fdir_filter *fdir_filter,
1410                           bool del,
1411                           bool update)
1412 {
1413         struct ixgbe_fdir_rule rule;
1414         int err;
1415
1416         err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
1417
1418         if (err)
1419                 return err;
1420
1421         return ixgbe_fdir_filter_program(dev, &rule, del, update);
1422 }
1423
1424 static int
1425 ixgbe_fdir_flush(struct rte_eth_dev *dev)
1426 {
1427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct ixgbe_hw_fdir_info *info =
1429                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1430         int ret;
1431
1432         ret = ixgbe_reinit_fdir_tables_82599(hw);
1433         if (ret < 0) {
1434                 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1435                 return ret;
1436         }
1437
1438         info->f_add = 0;
1439         info->f_remove = 0;
1440         info->add = 0;
1441         info->remove = 0;
1442
1443         return ret;
1444 }
1445
1446 #define FDIRENTRIES_NUM_SHIFT 10
1447 static void
1448 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1449 {
1450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         struct ixgbe_hw_fdir_info *info =
1452                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1453         uint32_t fdirctrl, max_num;
1454         uint8_t offset;
1455
1456         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1457         offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1458                         IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1459
1460         fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1461         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1462                         (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1463         if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1464             fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1465                 fdir_info->guarant_spc = max_num;
1466         else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1467                 fdir_info->guarant_spc = max_num * 4;
1468
1469         fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1470         fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1471         fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1472         IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1473                         fdir_info->mask.ipv6_mask.src_ip);
1474         IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1475                         fdir_info->mask.ipv6_mask.dst_ip);
1476         fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1477         fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1478         fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1479         fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1480         fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1481         fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1482
1483         if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1484             fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1485                 fdir_info->flow_types_mask[0] = 0;
1486         else
1487                 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1488
1489         fdir_info->flex_payload_unit = sizeof(uint16_t);
1490         fdir_info->max_flex_payload_segment_num = 1;
1491         fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1492         fdir_info->flex_conf.nb_payloads = 1;
1493         fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1494         fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1495         fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1496         fdir_info->flex_conf.nb_flexmasks = 1;
1497         fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1498         fdir_info->flex_conf.flex_mask[0].mask[0] =
1499                         (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1500         fdir_info->flex_conf.flex_mask[0].mask[1] =
1501                         (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1502 }
1503
1504 static void
1505 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1506 {
1507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508         struct ixgbe_hw_fdir_info *info =
1509                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1510         uint32_t reg, max_num;
1511         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1512
1513         /* Get the information from registers */
1514         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1515         info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1516                                      IXGBE_FDIRFREE_COLL_SHIFT);
1517         info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1518                                 IXGBE_FDIRFREE_FREE_SHIFT);
1519
1520         reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1521         info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1522                                    IXGBE_FDIRLEN_MAXHASH_SHIFT);
1523         info->maxlen  = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1524                                   IXGBE_FDIRLEN_MAXLEN_SHIFT);
1525
1526         reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1527         info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1528                 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1529         info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1530                 IXGBE_FDIRUSTAT_ADD_SHIFT;
1531
1532         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1533         info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1534                 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1535         info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1536                 IXGBE_FDIRFSTAT_FADD_SHIFT;
1537
1538         /*  Copy the new information in the fdir parameter */
1539         fdir_stats->collision = info->collision;
1540         fdir_stats->free = info->free;
1541         fdir_stats->maxhash = info->maxhash;
1542         fdir_stats->maxlen = info->maxlen;
1543         fdir_stats->remove = info->remove;
1544         fdir_stats->add = info->add;
1545         fdir_stats->f_remove = info->f_remove;
1546         fdir_stats->f_add = info->f_add;
1547
1548         reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1549         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1550                          (reg & FDIRCTRL_PBALLOC_MASK)));
1551         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1552             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1553                 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1554         else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1555                 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1556
1557 }
1558
1559 /*
1560  * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1561  * @dev: pointer to the structure rte_eth_dev
1562  * @filter_op:operation will be taken
1563  * @arg: a pointer to specific structure corresponding to the filter_op
1564  */
1565 int
1566 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1567                         enum rte_filter_op filter_op, void *arg)
1568 {
1569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570         int ret = 0;
1571
1572         if (hw->mac.type != ixgbe_mac_82599EB &&
1573                 hw->mac.type != ixgbe_mac_X540 &&
1574                 hw->mac.type != ixgbe_mac_X550 &&
1575                 hw->mac.type != ixgbe_mac_X550EM_x &&
1576                 hw->mac.type != ixgbe_mac_X550EM_a)
1577                 return -ENOTSUP;
1578
1579         if (filter_op == RTE_ETH_FILTER_NOP)
1580                 return 0;
1581
1582         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1583                 return -EINVAL;
1584
1585         switch (filter_op) {
1586         case RTE_ETH_FILTER_ADD:
1587                 ret = ixgbe_add_del_fdir_filter(dev,
1588                         (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1589                 break;
1590         case RTE_ETH_FILTER_UPDATE:
1591                 ret = ixgbe_add_del_fdir_filter(dev,
1592                         (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1593                 break;
1594         case RTE_ETH_FILTER_DELETE:
1595                 ret = ixgbe_add_del_fdir_filter(dev,
1596                         (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1597                 break;
1598         case RTE_ETH_FILTER_FLUSH:
1599                 ret = ixgbe_fdir_flush(dev);
1600                 break;
1601         case RTE_ETH_FILTER_INFO:
1602                 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1603                 break;
1604         case RTE_ETH_FILTER_STATS:
1605                 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1606                 break;
1607         default:
1608                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1609                 ret = -EINVAL;
1610                 break;
1611         }
1612         return ret;
1613 }
1614
1615 /* restore flow director filter */
1616 void
1617 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1618 {
1619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         struct ixgbe_hw_fdir_info *fdir_info =
1621                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1622         struct ixgbe_fdir_filter *node;
1623         bool is_perfect = FALSE;
1624         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1625
1626         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1627             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1628                 is_perfect = TRUE;
1629
1630         if (is_perfect) {
1631                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1632                         (void)fdir_write_perfect_filter_82599(hw,
1633                                                               &node->ixgbe_fdir,
1634                                                               node->queue,
1635                                                               node->fdirflags,
1636                                                               node->fdirhash,
1637                                                               fdir_mode);
1638                 }
1639         } else {
1640                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1641                         (void)fdir_add_signature_filter_82599(hw,
1642                                                               &node->ixgbe_fdir,
1643                                                               node->queue,
1644                                                               node->fdirflags,
1645                                                               node->fdirhash);
1646                 }
1647         }
1648 }
1649
1650 /* remove all the flow director filters */
1651 int
1652 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1653 {
1654         struct ixgbe_hw_fdir_info *fdir_info =
1655                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1656         struct ixgbe_fdir_filter *fdir_filter;
1657         struct ixgbe_fdir_filter *filter_flag;
1658         int ret = 0;
1659
1660         /* flush flow director */
1661         rte_hash_reset(fdir_info->hash_handle);
1662         memset(fdir_info->hash_map, 0,
1663                sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1664         filter_flag = TAILQ_FIRST(&fdir_info->fdir_list);
1665         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1666                 TAILQ_REMOVE(&fdir_info->fdir_list,
1667                              fdir_filter,
1668                              entries);
1669                 rte_free(fdir_filter);
1670         }
1671
1672         if (filter_flag != NULL)
1673                 ret = ixgbe_fdir_flush(dev);
1674
1675         return ret;
1676 }