drivers/net/ixgbe/ixgbe_ipsec.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_ethdev_pci.h>
   7 #include <rte_ip.h>
   8 #include <rte_jhash.h>
   9 #include <rte_security_driver.h>
  10 #include <rte_cryptodev.h>
  11 #include <rte_flow.h>
  12
  13 #include "base/ixgbe_type.h"
  14 #include "base/ixgbe_api.h"
  15 #include "ixgbe_ethdev.h"
  16 #include "ixgbe_ipsec.h"
  17
  18 #define RTE_IXGBE_REGISTER_POLL_WAIT_5_MS  5
  19
  20 #define IXGBE_WAIT_RREAD \
  21         IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
  22         IPSRXIDX_READ, RTE_IXGBE_REGISTER_POLL_WAIT_5_MS)
  23 #define IXGBE_WAIT_RWRITE \
  24         IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSRXIDX, reg_val, \
  25         IPSRXIDX_WRITE, RTE_IXGBE_REGISTER_POLL_WAIT_5_MS)
  26 #define IXGBE_WAIT_TREAD \
  27         IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSTXIDX, reg_val, \
  28         IPSRXIDX_READ, RTE_IXGBE_REGISTER_POLL_WAIT_5_MS)
  29 #define IXGBE_WAIT_TWRITE \
  30         IXGBE_WRITE_REG_THEN_POLL_MASK(hw, IXGBE_IPSTXIDX, reg_val, \
  31         IPSRXIDX_WRITE, RTE_IXGBE_REGISTER_POLL_WAIT_5_MS)
  32
  33 #define CMP_IP(a, b) (\
  34         (a).ipv6[0] == (b).ipv6[0] && \
  35         (a).ipv6[1] == (b).ipv6[1] && \
  36         (a).ipv6[2] == (b).ipv6[2] && \
  37         (a).ipv6[3] == (b).ipv6[3])
  38
  39
  40 static void
  41 ixgbe_crypto_clear_ipsec_tables(struct rte_eth_dev *dev)
  42 {
  43         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  44         struct ixgbe_ipsec *priv = IXGBE_DEV_PRIVATE_TO_IPSEC(
  45                                 dev->data->dev_private);
  46         int i = 0;
  47
  48         /* clear Rx IP table*/
  49         for (i = 0; i < IPSEC_MAX_RX_IP_COUNT; i++) {
  50                 uint16_t index = i << 3;
  51                 uint32_t reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_IP | index;
  52                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(0), 0);
  53                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(1), 0);
  54                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(2), 0);
  55                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(3), 0);
  56                 IXGBE_WAIT_RWRITE;
  57         }
  58
  59         /* clear Rx SPI and Rx/Tx SA tables*/
  60         for (i = 0; i < IPSEC_MAX_SA_COUNT; i++) {
  61                 uint32_t index = i << 3;
  62                 uint32_t reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_SPI | index;
  63                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, 0);
  64                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, 0);
  65                 IXGBE_WAIT_RWRITE;
  66                 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_KEY | index;
  67                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(0), 0);
  68                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(1), 0);
  69                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(2), 0);
  70                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(3), 0);
  71                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, 0);
  72                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, 0);
  73                 IXGBE_WAIT_RWRITE;
  74                 reg_val = IPSRXIDX_WRITE | index;
  75                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(0), 0);
  76                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(1), 0);
  77                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(2), 0);
  78                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(3), 0);
  79                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, 0);
  80                 IXGBE_WAIT_TWRITE;
  81         }
  82
  83         memset(priv->rx_ip_tbl, 0, sizeof(priv->rx_ip_tbl));
  84         memset(priv->rx_sa_tbl, 0, sizeof(priv->rx_sa_tbl));
  85         memset(priv->tx_sa_tbl, 0, sizeof(priv->tx_sa_tbl));
  86 }
  87
  88 static int
  89 ixgbe_crypto_add_sa(struct ixgbe_crypto_session *ic_session)
  90 {
  91         struct rte_eth_dev *dev = ic_session->dev;
  92         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  93         struct ixgbe_ipsec *priv = IXGBE_DEV_PRIVATE_TO_IPSEC(
  94                         dev->data->dev_private);
  95         uint32_t reg_val;
  96         int sa_index = -1;
  97
  98         if (ic_session->op == IXGBE_OP_AUTHENTICATED_DECRYPTION) {
  99                 int i, ip_index = -1;
 100
 101                 /* Find a match in the IP table*/
 102                 for (i = 0; i < IPSEC_MAX_RX_IP_COUNT; i++) {
 103                         if (CMP_IP(priv->rx_ip_tbl[i].ip,
 104                                    ic_session->dst_ip)) {
 105                                 ip_index = i;
 106                                 break;
 107                         }
 108                 }
 109                 /* If no match, find a free entry in the IP table*/
 110                 if (ip_index < 0) {
 111                         for (i = 0; i < IPSEC_MAX_RX_IP_COUNT; i++) {
 112                                 if (priv->rx_ip_tbl[i].ref_count == 0) {
 113                                         ip_index = i;
 114                                         break;
 115                                 }
 116                         }
 117                 }
 118
 119                 /* Fail if no match and no free entries*/
 120                 if (ip_index < 0) {
 121                         PMD_DRV_LOG(ERR,
 122                                     "No free entry left in the Rx IP table\n");
 123                         return -1;
 124                 }
 125
 126                 /* Find a free entry in the SA table*/
 127                 for (i = 0; i < IPSEC_MAX_SA_COUNT; i++) {
 128                         if (priv->rx_sa_tbl[i].used == 0) {
 129                                 sa_index = i;
 130                                 break;
 131                         }
 132                 }
 133                 /* Fail if no free entries*/
 134                 if (sa_index < 0) {
 135                         PMD_DRV_LOG(ERR,
 136                                     "No free entry left in the Rx SA table\n");
 137                         return -1;
 138                 }
 139
 140                 priv->rx_ip_tbl[ip_index].ip.ipv6[0] =
 141                                 ic_session->dst_ip.ipv6[0];
 142                 priv->rx_ip_tbl[ip_index].ip.ipv6[1] =
 143                                 ic_session->dst_ip.ipv6[1];
 144                 priv->rx_ip_tbl[ip_index].ip.ipv6[2] =
 145                                 ic_session->dst_ip.ipv6[2];
 146                 priv->rx_ip_tbl[ip_index].ip.ipv6[3] =
 147                                 ic_session->dst_ip.ipv6[3];
 148                 priv->rx_ip_tbl[ip_index].ref_count++;
 149
 150                 priv->rx_sa_tbl[sa_index].spi =
 151                         rte_cpu_to_be_32(ic_session->spi);
 152                 priv->rx_sa_tbl[sa_index].ip_index = ip_index;
 153                 priv->rx_sa_tbl[sa_index].mode = IPSRXMOD_VALID;
 154                 if (ic_session->op == IXGBE_OP_AUTHENTICATED_DECRYPTION)
 155                         priv->rx_sa_tbl[sa_index].mode |=
 156                                         (IPSRXMOD_PROTO | IPSRXMOD_DECRYPT);
 157                 if (ic_session->dst_ip.type == IPv6)
 158                         priv->rx_sa_tbl[sa_index].mode |= IPSRXMOD_IPV6;
 159                 priv->rx_sa_tbl[sa_index].used = 1;
 160
 161                 /* write IP table entry*/
 162                 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE |
 163                                 IPSRXIDX_TABLE_IP | (ip_index << 3);
 164                 if (priv->rx_ip_tbl[ip_index].ip.type == IPv4) {
 165                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(0), 0);
 166                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(1), 0);
 167                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(2), 0);
 168                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(3),
 169                                         priv->rx_ip_tbl[ip_index].ip.ipv4);
 170                 } else {
 171                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(0),
 172                                         priv->rx_ip_tbl[ip_index].ip.ipv6[0]);
 173                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(1),
 174                                         priv->rx_ip_tbl[ip_index].ip.ipv6[1]);
 175                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(2),
 176                                         priv->rx_ip_tbl[ip_index].ip.ipv6[2]);
 177                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(3),
 178                                         priv->rx_ip_tbl[ip_index].ip.ipv6[3]);
 179                 }
 180                 IXGBE_WAIT_RWRITE;
 181
 182                 /* write SPI table entry*/
 183                 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE |
 184                                 IPSRXIDX_TABLE_SPI | (sa_index << 3);
 185                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI,
 186                                 priv->rx_sa_tbl[sa_index].spi);
 187                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX,
 188                                 priv->rx_sa_tbl[sa_index].ip_index);
 189                 IXGBE_WAIT_RWRITE;
 190
 191                 /* write Key table entry*/
 192                 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE |
 193                                 IPSRXIDX_TABLE_KEY | (sa_index << 3);
 194                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(0),
 195                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[12]));
 196                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(1),
 197                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[8]));
 198                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(2),
 199                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[4]));
 200                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(3),
 201                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[0]));
 202                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT,
 203                                 rte_cpu_to_be_32(ic_session->salt));
 204                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD,
 205                                 priv->rx_sa_tbl[sa_index].mode);
 206                 IXGBE_WAIT_RWRITE;
 207
 208         } else { /* sess->dir == RTE_CRYPTO_OUTBOUND */
 209                 int i;
 210
 211                 /* Find a free entry in the SA table*/
 212                 for (i = 0; i < IPSEC_MAX_SA_COUNT; i++) {
 213                         if (priv->tx_sa_tbl[i].used == 0) {
 214                                 sa_index = i;
 215                                 break;
 216                         }
 217                 }
 218                 /* Fail if no free entries*/
 219                 if (sa_index < 0) {
 220                         PMD_DRV_LOG(ERR,
 221                                     "No free entry left in the Tx SA table\n");
 222                         return -1;
 223                 }
 224
 225                 priv->tx_sa_tbl[sa_index].spi =
 226                         rte_cpu_to_be_32(ic_session->spi);
 227                 priv->tx_sa_tbl[i].used = 1;
 228                 ic_session->sa_index = sa_index;
 229
 230                 /* write Key table entry*/
 231                 reg_val = IPSRXIDX_RX_EN | IPSRXIDX_WRITE | (sa_index << 3);
 232                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(0),
 233                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[12]));
 234                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(1),
 235                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[8]));
 236                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(2),
 237                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[4]));
 238                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(3),
 239                         rte_cpu_to_be_32(*(uint32_t *)&ic_session->key[0]));
 240                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT,
 241                                 rte_cpu_to_be_32(ic_session->salt));
 242                 IXGBE_WAIT_TWRITE;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int
 249 ixgbe_crypto_remove_sa(struct rte_eth_dev *dev,
 250                        struct ixgbe_crypto_session *ic_session)
 251 {
 252         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 253         struct ixgbe_ipsec *priv =
 254                         IXGBE_DEV_PRIVATE_TO_IPSEC(dev->data->dev_private);
 255         uint32_t reg_val;
 256         int sa_index = -1;
 257
 258         if (ic_session->op == IXGBE_OP_AUTHENTICATED_DECRYPTION) {
 259                 int i, ip_index = -1;
 260
 261                 /* Find a match in the IP table*/
 262                 for (i = 0; i < IPSEC_MAX_RX_IP_COUNT; i++) {
 263                         if (CMP_IP(priv->rx_ip_tbl[i].ip, ic_session->dst_ip)) {
 264                                 ip_index = i;
 265                                 break;
 266                         }
 267                 }
 268
 269                 /* Fail if no match*/
 270                 if (ip_index < 0) {
 271                         PMD_DRV_LOG(ERR,
 272                                     "Entry not found in the Rx IP table\n");
 273                         return -1;
 274                 }
 275
 276                 /* Find a free entry in the SA table*/
 277                 for (i = 0; i < IPSEC_MAX_SA_COUNT; i++) {
 278                         if (priv->rx_sa_tbl[i].spi ==
 279                                   rte_cpu_to_be_32(ic_session->spi)) {
 280                                 sa_index = i;
 281                                 break;
 282                         }
 283                 }
 284                 /* Fail if no match*/
 285                 if (sa_index < 0) {
 286                         PMD_DRV_LOG(ERR,
 287                                     "Entry not found in the Rx SA table\n");
 288                         return -1;
 289                 }
 290
 291                 /* Disable and clear Rx SPI and key table table entryes*/
 292                 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_SPI | (sa_index << 3);
 293                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, 0);
 294                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, 0);
 295                 IXGBE_WAIT_RWRITE;
 296                 reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_KEY | (sa_index << 3);
 297                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(0), 0);
 298                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(1), 0);
 299                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(2), 0);
 300                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(3), 0);
 301                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, 0);
 302                 IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, 0);
 303                 IXGBE_WAIT_RWRITE;
 304                 priv->rx_sa_tbl[sa_index].used = 0;
 305
 306                 /* If last used then clear the IP table entry*/
 307                 priv->rx_ip_tbl[ip_index].ref_count--;
 308                 if (priv->rx_ip_tbl[ip_index].ref_count == 0) {
 309                         reg_val = IPSRXIDX_WRITE | IPSRXIDX_TABLE_IP |
 310                                         (ip_index << 3);
 311                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(0), 0);
 312                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(1), 0);
 313                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(2), 0);
 314                         IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(3), 0);
 315                 }
 316         } else { /* session->dir == RTE_CRYPTO_OUTBOUND */
 317                 int i;
 318
 319                 /* Find a match in the SA table*/
 320                 for (i = 0; i < IPSEC_MAX_SA_COUNT; i++) {
 321                         if (priv->tx_sa_tbl[i].spi ==
 322                                     rte_cpu_to_be_32(ic_session->spi)) {
 323                                 sa_index = i;
 324                                 break;
 325                         }
 326                 }
 327                 /* Fail if no match entries*/
 328                 if (sa_index < 0) {
 329                         PMD_DRV_LOG(ERR,
 330                                     "Entry not found in the Tx SA table\n");
 331                         return -1;
 332                 }
 333                 reg_val = IPSRXIDX_WRITE | (sa_index << 3);
 334                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(0), 0);
 335                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(1), 0);
 336                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(2), 0);
 337                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(3), 0);
 338                 IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, 0);
 339                 IXGBE_WAIT_TWRITE;
 340
 341                 priv->tx_sa_tbl[sa_index].used = 0;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int
 348 ixgbe_crypto_create_session(void *device,
 349                 struct rte_security_session_conf *conf,
 350                 struct rte_security_session *session,
 351                 struct rte_mempool *mempool)
 352 {
 353         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device;
 354         struct ixgbe_crypto_session *ic_session = NULL;
 355         struct rte_crypto_aead_xform *aead_xform;
 356         struct rte_eth_conf *dev_conf = &eth_dev->data->dev_conf;
 357
 358         if (rte_mempool_get(mempool, (void **)&ic_session)) {
 359                 PMD_DRV_LOG(ERR, "Cannot get object from ic_session mempool");
 360                 return -ENOMEM;
 361         }
 362
 363         if (conf->crypto_xform->type != RTE_CRYPTO_SYM_XFORM_AEAD ||
 364                         conf->crypto_xform->aead.algo !=
 365                                         RTE_CRYPTO_AEAD_AES_GCM) {
 366                 PMD_DRV_LOG(ERR, "Unsupported crypto transformation mode\n");
 367                 return -ENOTSUP;
 368         }
 369         aead_xform = &conf->crypto_xform->aead;
 370
 371         if (conf->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {
 372                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_SECURITY) {
 373                         ic_session->op = IXGBE_OP_AUTHENTICATED_DECRYPTION;
 374                 } else {
 375                         PMD_DRV_LOG(ERR, "IPsec decryption not enabled\n");
 376                         return -ENOTSUP;
 377                 }
 378         } else {
 379                 if (dev_conf->txmode.offloads & DEV_TX_OFFLOAD_SECURITY) {
 380                         ic_session->op = IXGBE_OP_AUTHENTICATED_ENCRYPTION;
 381                 } else {
 382                         PMD_DRV_LOG(ERR, "IPsec encryption not enabled\n");
 383                         return -ENOTSUP;
 384                 }
 385         }
 386
 387         ic_session->key = aead_xform->key.data;
 388         memcpy(&ic_session->salt,
 389                &aead_xform->key.data[aead_xform->key.length], 4);
 390         ic_session->spi = conf->ipsec.spi;
 391         ic_session->dev = eth_dev;
 392
 393         set_sec_session_private_data(session, ic_session);
 394
 395         if (ic_session->op == IXGBE_OP_AUTHENTICATED_ENCRYPTION) {
 396                 if (ixgbe_crypto_add_sa(ic_session)) {
 397                         PMD_DRV_LOG(ERR, "Failed to add SA\n");
 398                         return -EPERM;
 399                 }
 400         }
 401
 402         return 0;
 403 }
 404
 405 static unsigned int
 406 ixgbe_crypto_session_get_size(__rte_unused void *device)
 407 {
 408         return sizeof(struct ixgbe_crypto_session);
 409 }
 410
 411 static int
 412 ixgbe_crypto_remove_session(void *device,
 413                 struct rte_security_session *session)
 414 {
 415         struct rte_eth_dev *eth_dev = device;
 416         struct ixgbe_crypto_session *ic_session =
 417                 (struct ixgbe_crypto_session *)
 418                 get_sec_session_private_data(session);
 419         struct rte_mempool *mempool = rte_mempool_from_obj(ic_session);
 420
 421         if (eth_dev != ic_session->dev) {
 422                 PMD_DRV_LOG(ERR, "Session not bound to this device\n");
 423                 return -ENODEV;
 424         }
 425
 426         if (ixgbe_crypto_remove_sa(eth_dev, ic_session)) {
 427                 PMD_DRV_LOG(ERR, "Failed to remove session\n");
 428                 return -EFAULT;
 429         }
 430
 431         rte_mempool_put(mempool, (void *)ic_session);
 432
 433         return 0;
 434 }
 435
 436 static inline uint8_t
 437 ixgbe_crypto_compute_pad_len(struct rte_mbuf *m)
 438 {
 439         if (m->nb_segs == 1) {
 440                 /* 16 bytes ICV + 2 bytes ESP trailer + payload padding size
 441                  * payload padding size is stored at <pkt_len - 18>
 442                  */
 443                 uint8_t *esp_pad_len = rte_pktmbuf_mtod_offset(m, uint8_t *,
 444                                         rte_pktmbuf_pkt_len(m) -
 445                                         (ESP_TRAILER_SIZE + ESP_ICV_SIZE));
 446                 return *esp_pad_len + ESP_TRAILER_SIZE + ESP_ICV_SIZE;
 447         }
 448         return 0;
 449 }
 450
 451 static int
 452 ixgbe_crypto_update_mb(void *device __rte_unused,
 453                 struct rte_security_session *session,
 454                        struct rte_mbuf *m, void *params __rte_unused)
 455 {
 456         struct ixgbe_crypto_session *ic_session =
 457                         get_sec_session_private_data(session);
 458         if (ic_session->op == IXGBE_OP_AUTHENTICATED_ENCRYPTION) {
 459                 union ixgbe_crypto_tx_desc_md *mdata =
 460                         (union ixgbe_crypto_tx_desc_md *)&m->udata64;
 461                 mdata->enc = 1;
 462                 mdata->sa_idx = ic_session->sa_index;
 463                 mdata->pad_len = ixgbe_crypto_compute_pad_len(m);
 464         }
 465         return 0;
 466 }
 467
 468
 469 static const struct rte_security_capability *
 470 ixgbe_crypto_capabilities_get(void *device __rte_unused)
 471 {
 472         static const struct rte_cryptodev_capabilities
 473         aes_gcm_gmac_crypto_capabilities[] = {
 474                 {       /* AES GMAC (128-bit) */
 475                         .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 476                         {.sym = {
 477                                 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
 478                                 {.auth = {
 479                                         .algo = RTE_CRYPTO_AUTH_AES_GMAC,
 480                                         .block_size = 16,
 481                                         .key_size = {
 482                                                 .min = 16,
 483                                                 .max = 16,
 484                                                 .increment = 0
 485                                         },
 486                                         .digest_size = {
 487                                                 .min = 16,
 488                                                 .max = 16,
 489                                                 .increment = 0
 490                                         },
 491                                         .iv_size = {
 492                                                 .min = 12,
 493                                                 .max = 12,
 494                                                 .increment = 0
 495                                         }
 496                                 }, }
 497                         }, }
 498                 },
 499                 {       /* AES GCM (128-bit) */
 500                         .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
 501                         {.sym = {
 502                                 .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
 503                                 {.aead = {
 504                                         .algo = RTE_CRYPTO_AEAD_AES_GCM,
 505                                         .block_size = 16,
 506                                         .key_size = {
 507                                                 .min = 16,
 508                                                 .max = 16,
 509                                                 .increment = 0
 510                                         },
 511                                         .digest_size = {
 512                                                 .min = 16,
 513                                                 .max = 16,
 514                                                 .increment = 0
 515                                         },
 516                                         .aad_size = {
 517                                                 .min = 0,
 518                                                 .max = 65535,
 519                                                 .increment = 1
 520                                         },
 521                                         .iv_size = {
 522                                                 .min = 12,
 523                                                 .max = 12,
 524                                                 .increment = 0
 525                                         }
 526                                 }, }
 527                         }, }
 528                 },
 529                 {
 530                         .op = RTE_CRYPTO_OP_TYPE_UNDEFINED,
 531                         {.sym = {
 532                                 .xform_type = RTE_CRYPTO_SYM_XFORM_NOT_SPECIFIED
 533                         }, }
 534                 },
 535         };
 536
 537         static const struct rte_security_capability
 538         ixgbe_security_capabilities[] = {
 539                 { /* IPsec Inline Crypto ESP Transport Egress */
 540                         .action = RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO,
 541                         .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
 542                         {.ipsec = {
 543                                 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
 544                                 .mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
 545                                 .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
 546                                 .options = { 0 }
 547                         } },
 548                         .crypto_capabilities = aes_gcm_gmac_crypto_capabilities,
 549                         .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
 550                 },
 551                 { /* IPsec Inline Crypto ESP Transport Ingress */
 552                         .action = RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO,
 553                         .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
 554                         {.ipsec = {
 555                                 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
 556                                 .mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
 557                                 .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
 558                                 .options = { 0 }
 559                         } },
 560                         .crypto_capabilities = aes_gcm_gmac_crypto_capabilities,
 561                         .ol_flags = 0
 562                 },
 563                 { /* IPsec Inline Crypto ESP Tunnel Egress */
 564                         .action = RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO,
 565                         .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
 566                         {.ipsec = {
 567                                 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
 568                                 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
 569                                 .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
 570                                 .options = { 0 }
 571                         } },
 572                         .crypto_capabilities = aes_gcm_gmac_crypto_capabilities,
 573                         .ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA
 574                 },
 575                 { /* IPsec Inline Crypto ESP Tunnel Ingress */
 576                         .action = RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO,
 577                         .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
 578                         {.ipsec = {
 579                                 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
 580                                 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
 581                                 .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
 582                                 .options = { 0 }
 583                         } },
 584                         .crypto_capabilities = aes_gcm_gmac_crypto_capabilities,
 585                         .ol_flags = 0
 586                 },
 587                 {
 588                         .action = RTE_SECURITY_ACTION_TYPE_NONE
 589                 }
 590         };
 591
 592         return ixgbe_security_capabilities;
 593 }
 594
 595
 596 int
 597 ixgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
 598 {
 599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 600         uint32_t reg;
 601
 602         /* sanity checks */
 603         if (dev->data->dev_conf.rxmode.enable_lro) {
 604                 PMD_DRV_LOG(ERR, "RSC and IPsec not supported");
 605                 return -1;
 606         }
 607         if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
 608                 PMD_DRV_LOG(ERR, "HW CRC strip needs to be enabled for IPsec");
 609                 return -1;
 610         }
 611
 612
 613         /* Set IXGBE_SECTXBUFFAF to 0x15 as required in the datasheet*/
 614         IXGBE_WRITE_REG(hw, IXGBE_SECTXBUFFAF, 0x15);
 615
 616         /* IFG needs to be set to 3 when we are using security. Otherwise a Tx
 617          * hang will occur with heavy traffic.
 618          */
 619         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
 620         reg = (reg & 0xFFFFFFF0) | 0x3;
 621         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
 622
 623         reg  = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 624         reg |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
 625         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg);
 626
 627         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SECURITY) {
 628                 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, 0);
 629                 reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 630                 if (reg != 0) {
 631                         PMD_DRV_LOG(ERR, "Error enabling Rx Crypto");
 632                         return -1;
 633                 }
 634         }
 635         if (dev->data->dev_conf.txmode.offloads & DEV_TX_OFFLOAD_SECURITY) {
 636                 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL,
 637                                 IXGBE_SECTXCTRL_STORE_FORWARD);
 638                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
 639                 if (reg != IXGBE_SECTXCTRL_STORE_FORWARD) {
 640                         PMD_DRV_LOG(ERR, "Error enabling Rx Crypto");
 641                         return -1;
 642                 }
 643         }
 644
 645         ixgbe_crypto_clear_ipsec_tables(dev);
 646
 647         return 0;
 648 }
 649
 650 int
 651 ixgbe_crypto_add_ingress_sa_from_flow(const void *sess,
 652                                       const void *ip_spec,
 653                                       uint8_t is_ipv6)
 654 {
 655         struct ixgbe_crypto_session *ic_session
 656                 = get_sec_session_private_data(sess);
 657
 658         if (ic_session->op == IXGBE_OP_AUTHENTICATED_DECRYPTION) {
 659                 if (is_ipv6) {
 660                         const struct rte_flow_item_ipv6 *ipv6 = ip_spec;
 661                         ic_session->src_ip.type = IPv6;
 662                         ic_session->dst_ip.type = IPv6;
 663                         rte_memcpy(ic_session->src_ip.ipv6,
 664                                    ipv6->hdr.src_addr, 16);
 665                         rte_memcpy(ic_session->dst_ip.ipv6,
 666                                    ipv6->hdr.dst_addr, 16);
 667                 } else {
 668                         const struct rte_flow_item_ipv4 *ipv4 = ip_spec;
 669                         ic_session->src_ip.type = IPv4;
 670                         ic_session->dst_ip.type = IPv4;
 671                         ic_session->src_ip.ipv4 = ipv4->hdr.src_addr;
 672                         ic_session->dst_ip.ipv4 = ipv4->hdr.dst_addr;
 673                 }
 674                 return ixgbe_crypto_add_sa(ic_session);
 675         }
 676
 677         return 0;
 678 }
 679
 680 static struct rte_security_ops ixgbe_security_ops = {
 681         .session_create = ixgbe_crypto_create_session,
 682         .session_update = NULL,
 683         .session_get_size = ixgbe_crypto_session_get_size,
 684         .session_stats_get = NULL,
 685         .session_destroy = ixgbe_crypto_remove_session,
 686         .set_pkt_metadata = ixgbe_crypto_update_mb,
 687         .capabilities_get = ixgbe_crypto_capabilities_get
 688 };
 689
 690 static int
 691 ixgbe_crypto_capable(struct rte_eth_dev *dev)
 692 {
 693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 694         uint32_t reg_i, reg, capable = 1;
 695         /* test if rx crypto can be enabled and then write back initial value*/
 696         reg_i = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 697         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, 0);
 698         reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 699         if (reg != 0)
 700                 capable = 0;
 701         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg_i);
 702         return capable;
 703 }
 704
 705 int
 706 ixgbe_ipsec_ctx_create(struct rte_eth_dev *dev)
 707 {
 708         struct rte_security_ctx *ctx = NULL;
 709
 710         if (ixgbe_crypto_capable(dev)) {
 711                 ctx = rte_malloc("rte_security_instances_ops",
 712                                  sizeof(struct rte_security_ctx), 0);
 713                 if (ctx) {
 714                         ctx->device = (void *)dev;
 715                         ctx->ops = &ixgbe_security_ops;
 716                         ctx->sess_cnt = 0;
 717                         dev->security_ctx = ctx;
 718                 } else {
 719                         return -ENOMEM;
 720                 }
 721         }
 722         return 0;
 723 }