drivers/net/ixgbe/ixgbe_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation.
   3  * Copyright 2014 6WIND S.A.
   4  */
   5
   6 #include <sys/queue.h>
   7
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <errno.h>
  12 #include <stdint.h>
  13 #include <stdarg.h>
  14 #include <unistd.h>
  15 #include <inttypes.h>
  16
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_pci.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_launch.h>
  27 #include <rte_eal.h>
  28 #include <rte_per_lcore.h>
  29 #include <rte_lcore.h>
  30 #include <rte_atomic.h>
  31 #include <rte_branch_prediction.h>
  32 #include <rte_mempool.h>
  33 #include <rte_malloc.h>
  34 #include <rte_mbuf.h>
  35 #include <rte_ether.h>
  36 #include <rte_ethdev_driver.h>
  37 #include <rte_prefetch.h>
  38 #include <rte_udp.h>
  39 #include <rte_tcp.h>
  40 #include <rte_sctp.h>
  41 #include <rte_string_fns.h>
  42 #include <rte_errno.h>
  43 #include <rte_ip.h>
  44 #include <rte_net.h>
  45
  46 #include "ixgbe_logs.h"
  47 #include "base/ixgbe_api.h"
  48 #include "base/ixgbe_vf.h"
  49 #include "ixgbe_ethdev.h"
  50 #include "base/ixgbe_dcb.h"
  51 #include "base/ixgbe_common.h"
  52 #include "ixgbe_rxtx.h"
  53
  54 #ifdef RTE_LIBRTE_IEEE1588
  55 #define IXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  56 #else
  57 #define IXGBE_TX_IEEE1588_TMST 0
  58 #endif
  59 /* Bit Mask to indicate what bits required for building TX context */
  60 #define IXGBE_TX_OFFLOAD_MASK (                  \
  61                 PKT_TX_OUTER_IPV6 |              \
  62                 PKT_TX_OUTER_IPV4 |              \
  63                 PKT_TX_IPV6 |                    \
  64                 PKT_TX_IPV4 |                    \
  65                 PKT_TX_VLAN_PKT |                \
  66                 PKT_TX_IP_CKSUM |                \
  67                 PKT_TX_L4_MASK |                 \
  68                 PKT_TX_TCP_SEG |                 \
  69                 PKT_TX_MACSEC |                  \
  70                 PKT_TX_OUTER_IP_CKSUM |          \
  71                 PKT_TX_SEC_OFFLOAD |     \
  72                 IXGBE_TX_IEEE1588_TMST)
  73
  74 #define IXGBE_TX_OFFLOAD_NOTSUP_MASK \
  75                 (PKT_TX_OFFLOAD_MASK ^ IXGBE_TX_OFFLOAD_MASK)
  76
  77 #if 1
  78 #define RTE_PMD_USE_PREFETCH
  79 #endif
  80
  81 #ifdef RTE_PMD_USE_PREFETCH
  82 /*
  83  * Prefetch a cache line into all cache levels.
  84  */
  85 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
  86 #else
  87 #define rte_ixgbe_prefetch(p)   do {} while (0)
  88 #endif
  89
  90 #ifdef RTE_IXGBE_INC_VECTOR
  91 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
  92                                     uint16_t nb_pkts);
  93 #endif
  94
  95 /*********************************************************************
  96  *
  97  *  TX functions
  98  *
  99  **********************************************************************/
 100
 101 /*
 102  * Check for descriptors with their DD bit set and free mbufs.
 103  * Return the total number of buffers freed.
 104  */
 105 static __rte_always_inline int
 106 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 107 {
 108         struct ixgbe_tx_entry *txep;
 109         uint32_t status;
 110         int i, nb_free = 0;
 111         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 112
 113         /* check DD bit on threshold descriptor */
 114         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 115         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 116                 return 0;
 117
 118         /*
 119          * first buffer to free from S/W ring is at index
 120          * tx_next_dd - (tx_rs_thresh-1)
 121          */
 122         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 123
 124         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 125                 /* free buffers one at a time */
 126                 m = rte_pktmbuf_prefree_seg(txep->mbuf);
 127                 txep->mbuf = NULL;
 128
 129                 if (unlikely(m == NULL))
 130                         continue;
 131
 132                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 133                     (nb_free > 0 && m->pool != free[0]->pool)) {
 134                         rte_mempool_put_bulk(free[0]->pool,
 135                                              (void **)free, nb_free);
 136                         nb_free = 0;
 137                 }
 138
 139                 free[nb_free++] = m;
 140         }
 141
 142         if (nb_free > 0)
 143                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 144
 145         /* buffers were freed, update counters */
 146         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 147         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 148         if (txq->tx_next_dd >= txq->nb_tx_desc)
 149                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 150
 151         return txq->tx_rs_thresh;
 152 }
 153
 154 /* Populate 4 descriptors with data from 4 mbufs */
 155 static inline void
 156 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 157 {
 158         uint64_t buf_dma_addr;
 159         uint32_t pkt_len;
 160         int i;
 161
 162         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 163                 buf_dma_addr = rte_mbuf_data_iova(*pkts);
 164                 pkt_len = (*pkts)->data_len;
 165
 166                 /* write data to descriptor */
 167                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 168
 169                 txdp->read.cmd_type_len =
 170                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 171
 172                 txdp->read.olinfo_status =
 173                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 174
 175                 rte_prefetch0(&(*pkts)->pool);
 176         }
 177 }
 178
 179 /* Populate 1 descriptor with data from 1 mbuf */
 180 static inline void
 181 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 182 {
 183         uint64_t buf_dma_addr;
 184         uint32_t pkt_len;
 185
 186         buf_dma_addr = rte_mbuf_data_iova(*pkts);
 187         pkt_len = (*pkts)->data_len;
 188
 189         /* write data to descriptor */
 190         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 191         txdp->read.cmd_type_len =
 192                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 193         txdp->read.olinfo_status =
 194                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 195         rte_prefetch0(&(*pkts)->pool);
 196 }
 197
 198 /*
 199  * Fill H/W descriptor ring with mbuf data.
 200  * Copy mbuf pointers to the S/W ring.
 201  */
 202 static inline void
 203 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 204                       uint16_t nb_pkts)
 205 {
 206         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 207         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 208         const int N_PER_LOOP = 4;
 209         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 210         int mainpart, leftover;
 211         int i, j;
 212
 213         /*
 214          * Process most of the packets in chunks of N pkts.  Any
 215          * leftover packets will get processed one at a time.
 216          */
 217         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 218         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 219         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 220                 /* Copy N mbuf pointers to the S/W ring */
 221                 for (j = 0; j < N_PER_LOOP; ++j) {
 222                         (txep + i + j)->mbuf = *(pkts + i + j);
 223                 }
 224                 tx4(txdp + i, pkts + i);
 225         }
 226
 227         if (unlikely(leftover > 0)) {
 228                 for (i = 0; i < leftover; ++i) {
 229                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 230                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 231                 }
 232         }
 233 }
 234
 235 static inline uint16_t
 236 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 237              uint16_t nb_pkts)
 238 {
 239         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 240         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 241         uint16_t n = 0;
 242
 243         /*
 244          * Begin scanning the H/W ring for done descriptors when the
 245          * number of available descriptors drops below tx_free_thresh.  For
 246          * each done descriptor, free the associated buffer.
 247          */
 248         if (txq->nb_tx_free < txq->tx_free_thresh)
 249                 ixgbe_tx_free_bufs(txq);
 250
 251         /* Only use descriptors that are available */
 252         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 253         if (unlikely(nb_pkts == 0))
 254                 return 0;
 255
 256         /* Use exactly nb_pkts descriptors */
 257         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 258
 259         /*
 260          * At this point, we know there are enough descriptors in the
 261          * ring to transmit all the packets.  This assumes that each
 262          * mbuf contains a single segment, and that no new offloads
 263          * are expected, which would require a new context descriptor.
 264          */
 265
 266         /*
 267          * See if we're going to wrap-around. If so, handle the top
 268          * of the descriptor ring first, then do the bottom.  If not,
 269          * the processing looks just like the "bottom" part anyway...
 270          */
 271         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 272                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 273                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 274
 275                 /*
 276                  * We know that the last descriptor in the ring will need to
 277                  * have its RS bit set because tx_rs_thresh has to be
 278                  * a divisor of the ring size
 279                  */
 280                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 281                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 282                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 283
 284                 txq->tx_tail = 0;
 285         }
 286
 287         /* Fill H/W descriptor ring with mbuf data */
 288         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 289         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 290
 291         /*
 292          * Determine if RS bit should be set
 293          * This is what we actually want:
 294          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 295          * but instead of subtracting 1 and doing >=, we can just do
 296          * greater than without subtracting.
 297          */
 298         if (txq->tx_tail > txq->tx_next_rs) {
 299                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 300                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 301                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 302                                                 txq->tx_rs_thresh);
 303                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 304                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 305         }
 306
 307         /*
 308          * Check for wrap-around. This would only happen if we used
 309          * up to the last descriptor in the ring, no more, no less.
 310          */
 311         if (txq->tx_tail >= txq->nb_tx_desc)
 312                 txq->tx_tail = 0;
 313
 314         /* update tail pointer */
 315         rte_wmb();
 316         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
 317
 318         return nb_pkts;
 319 }
 320
 321 uint16_t
 322 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 323                        uint16_t nb_pkts)
 324 {
 325         uint16_t nb_tx;
 326
 327         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 328         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 329                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 330
 331         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 332         nb_tx = 0;
 333         while (nb_pkts) {
 334                 uint16_t ret, n;
 335
 336                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 337                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 338                 nb_tx = (uint16_t)(nb_tx + ret);
 339                 nb_pkts = (uint16_t)(nb_pkts - ret);
 340                 if (ret < n)
 341                         break;
 342         }
 343
 344         return nb_tx;
 345 }
 346
 347 #ifdef RTE_IXGBE_INC_VECTOR
 348 static uint16_t
 349 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 350                     uint16_t nb_pkts)
 351 {
 352         uint16_t nb_tx = 0;
 353         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 354
 355         while (nb_pkts) {
 356                 uint16_t ret, num;
 357
 358                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 359                 ret = ixgbe_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
 360                                                  num);
 361                 nb_tx += ret;
 362                 nb_pkts -= ret;
 363                 if (ret < num)
 364                         break;
 365         }
 366
 367         return nb_tx;
 368 }
 369 #endif
 370
 371 static inline void
 372 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 373                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 374                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload,
 375                 __rte_unused uint64_t *mdata)
 376 {
 377         uint32_t type_tucmd_mlhl;
 378         uint32_t mss_l4len_idx = 0;
 379         uint32_t ctx_idx;
 380         uint32_t vlan_macip_lens;
 381         union ixgbe_tx_offload tx_offload_mask;
 382         uint32_t seqnum_seed = 0;
 383
 384         ctx_idx = txq->ctx_curr;
 385         tx_offload_mask.data[0] = 0;
 386         tx_offload_mask.data[1] = 0;
 387         type_tucmd_mlhl = 0;
 388
 389         /* Specify which HW CTX to upload. */
 390         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 391
 392         if (ol_flags & PKT_TX_VLAN_PKT) {
 393                 tx_offload_mask.vlan_tci |= ~0;
 394         }
 395
 396         /* check if TCP segmentation required for this packet */
 397         if (ol_flags & PKT_TX_TCP_SEG) {
 398                 /* implies IP cksum in IPv4 */
 399                 if (ol_flags & PKT_TX_IP_CKSUM)
 400                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 401                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 402                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 403                 else
 404                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 405                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 406                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 407
 408                 tx_offload_mask.l2_len |= ~0;
 409                 tx_offload_mask.l3_len |= ~0;
 410                 tx_offload_mask.l4_len |= ~0;
 411                 tx_offload_mask.tso_segsz |= ~0;
 412                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 413                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 414         } else { /* no TSO, check if hardware checksum is needed */
 415                 if (ol_flags & PKT_TX_IP_CKSUM) {
 416                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 417                         tx_offload_mask.l2_len |= ~0;
 418                         tx_offload_mask.l3_len |= ~0;
 419                 }
 420
 421                 switch (ol_flags & PKT_TX_L4_MASK) {
 422                 case PKT_TX_UDP_CKSUM:
 423                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 424                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 425                         mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 426                         tx_offload_mask.l2_len |= ~0;
 427                         tx_offload_mask.l3_len |= ~0;
 428                         break;
 429                 case PKT_TX_TCP_CKSUM:
 430                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 431                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 432                         mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 433                         tx_offload_mask.l2_len |= ~0;
 434                         tx_offload_mask.l3_len |= ~0;
 435                         break;
 436                 case PKT_TX_SCTP_CKSUM:
 437                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 438                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 439                         mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 440                         tx_offload_mask.l2_len |= ~0;
 441                         tx_offload_mask.l3_len |= ~0;
 442                         break;
 443                 default:
 444                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 445                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 446                         break;
 447                 }
 448         }
 449
 450         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 451                 tx_offload_mask.outer_l2_len |= ~0;
 452                 tx_offload_mask.outer_l3_len |= ~0;
 453                 tx_offload_mask.l2_len |= ~0;
 454                 seqnum_seed |= tx_offload.outer_l3_len
 455                                << IXGBE_ADVTXD_OUTER_IPLEN;
 456                 seqnum_seed |= tx_offload.l2_len
 457                                << IXGBE_ADVTXD_TUNNEL_LEN;
 458         }
 459 #ifdef RTE_LIBRTE_SECURITY
 460         if (ol_flags & PKT_TX_SEC_OFFLOAD) {
 461                 union ixgbe_crypto_tx_desc_md *md =
 462                                 (union ixgbe_crypto_tx_desc_md *)mdata;
 463                 seqnum_seed |=
 464                         (IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK & md->sa_idx);
 465                 type_tucmd_mlhl |= md->enc ?
 466                                 (IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP |
 467                                 IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN) : 0;
 468                 type_tucmd_mlhl |=
 469                         (md->pad_len & IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK);
 470                 tx_offload_mask.sa_idx |= ~0;
 471                 tx_offload_mask.sec_pad_len |= ~0;
 472         }
 473 #endif
 474
 475         txq->ctx_cache[ctx_idx].flags = ol_flags;
 476         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 477                 tx_offload_mask.data[0] & tx_offload.data[0];
 478         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 479                 tx_offload_mask.data[1] & tx_offload.data[1];
 480         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 481
 482         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 483         vlan_macip_lens = tx_offload.l3_len;
 484         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 485                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 486                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 487         else
 488                 vlan_macip_lens |= (tx_offload.l2_len <<
 489                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 490         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 491         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 492         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 493         ctx_txd->seqnum_seed     = seqnum_seed;
 494 }
 495
 496 /*
 497  * Check which hardware context can be used. Use the existing match
 498  * or create a new context descriptor.
 499  */
 500 static inline uint32_t
 501 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 502                    union ixgbe_tx_offload tx_offload)
 503 {
 504         /* If match with the current used context */
 505         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 506                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 507                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 508                      & tx_offload.data[0])) &&
 509                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 510                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 511                      & tx_offload.data[1]))))
 512                 return txq->ctx_curr;
 513
 514         /* What if match with the next context  */
 515         txq->ctx_curr ^= 1;
 516         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 517                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 518                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 519                      & tx_offload.data[0])) &&
 520                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 521                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 522                      & tx_offload.data[1]))))
 523                 return txq->ctx_curr;
 524
 525         /* Mismatch, use the previous context */
 526         return IXGBE_CTX_NUM;
 527 }
 528
 529 static inline uint32_t
 530 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 531 {
 532         uint32_t tmp = 0;
 533
 534         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 535                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 536         if (ol_flags & PKT_TX_IP_CKSUM)
 537                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 538         if (ol_flags & PKT_TX_TCP_SEG)
 539                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 540         return tmp;
 541 }
 542
 543 static inline uint32_t
 544 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 545 {
 546         uint32_t cmdtype = 0;
 547
 548         if (ol_flags & PKT_TX_VLAN_PKT)
 549                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 550         if (ol_flags & PKT_TX_TCP_SEG)
 551                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 552         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 553                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 554         if (ol_flags & PKT_TX_MACSEC)
 555                 cmdtype |= IXGBE_ADVTXD_MAC_LINKSEC;
 556         return cmdtype;
 557 }
 558
 559 /* Default RS bit threshold values */
 560 #ifndef DEFAULT_TX_RS_THRESH
 561 #define DEFAULT_TX_RS_THRESH   32
 562 #endif
 563 #ifndef DEFAULT_TX_FREE_THRESH
 564 #define DEFAULT_TX_FREE_THRESH 32
 565 #endif
 566
 567 /* Reset transmit descriptors after they have been used */
 568 static inline int
 569 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 570 {
 571         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 572         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 573         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 574         uint16_t nb_tx_desc = txq->nb_tx_desc;
 575         uint16_t desc_to_clean_to;
 576         uint16_t nb_tx_to_clean;
 577         uint32_t status;
 578
 579         /* Determine the last descriptor needing to be cleaned */
 580         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 581         if (desc_to_clean_to >= nb_tx_desc)
 582                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 583
 584         /* Check to make sure the last descriptor to clean is done */
 585         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 586         status = txr[desc_to_clean_to].wb.status;
 587         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 588                 PMD_TX_FREE_LOG(DEBUG,
 589                                 "TX descriptor %4u is not done"
 590                                 "(port=%d queue=%d)",
 591                                 desc_to_clean_to,
 592                                 txq->port_id, txq->queue_id);
 593                 /* Failed to clean any descriptors, better luck next time */
 594                 return -(1);
 595         }
 596
 597         /* Figure out how many descriptors will be cleaned */
 598         if (last_desc_cleaned > desc_to_clean_to)
 599                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 600                                                         desc_to_clean_to);
 601         else
 602                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 603                                                 last_desc_cleaned);
 604
 605         PMD_TX_FREE_LOG(DEBUG,
 606                         "Cleaning %4u TX descriptors: %4u to %4u "
 607                         "(port=%d queue=%d)",
 608                         nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 609                         txq->port_id, txq->queue_id);
 610
 611         /*
 612          * The last descriptor to clean is done, so that means all the
 613          * descriptors from the last descriptor that was cleaned
 614          * up to the last descriptor with the RS bit set
 615          * are done. Only reset the threshold descriptor.
 616          */
 617         txr[desc_to_clean_to].wb.status = 0;
 618
 619         /* Update the txq to reflect the last descriptor that was cleaned */
 620         txq->last_desc_cleaned = desc_to_clean_to;
 621         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 622
 623         /* No Error */
 624         return 0;
 625 }
 626
 627 uint16_t
 628 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 629                 uint16_t nb_pkts)
 630 {
 631         struct ixgbe_tx_queue *txq;
 632         struct ixgbe_tx_entry *sw_ring;
 633         struct ixgbe_tx_entry *txe, *txn;
 634         volatile union ixgbe_adv_tx_desc *txr;
 635         volatile union ixgbe_adv_tx_desc *txd, *txp;
 636         struct rte_mbuf     *tx_pkt;
 637         struct rte_mbuf     *m_seg;
 638         uint64_t buf_dma_addr;
 639         uint32_t olinfo_status;
 640         uint32_t cmd_type_len;
 641         uint32_t pkt_len;
 642         uint16_t slen;
 643         uint64_t ol_flags;
 644         uint16_t tx_id;
 645         uint16_t tx_last;
 646         uint16_t nb_tx;
 647         uint16_t nb_used;
 648         uint64_t tx_ol_req;
 649         uint32_t ctx = 0;
 650         uint32_t new_ctx;
 651         union ixgbe_tx_offload tx_offload;
 652 #ifdef RTE_LIBRTE_SECURITY
 653         uint8_t use_ipsec;
 654 #endif
 655
 656         tx_offload.data[0] = 0;
 657         tx_offload.data[1] = 0;
 658         txq = tx_queue;
 659         sw_ring = txq->sw_ring;
 660         txr     = txq->tx_ring;
 661         tx_id   = txq->tx_tail;
 662         txe = &sw_ring[tx_id];
 663         txp = NULL;
 664
 665         /* Determine if the descriptor ring needs to be cleaned. */
 666         if (txq->nb_tx_free < txq->tx_free_thresh)
 667                 ixgbe_xmit_cleanup(txq);
 668
 669         rte_prefetch0(&txe->mbuf->pool);
 670
 671         /* TX loop */
 672         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 673                 new_ctx = 0;
 674                 tx_pkt = *tx_pkts++;
 675                 pkt_len = tx_pkt->pkt_len;
 676
 677                 /*
 678                  * Determine how many (if any) context descriptors
 679                  * are needed for offload functionality.
 680                  */
 681                 ol_flags = tx_pkt->ol_flags;
 682 #ifdef RTE_LIBRTE_SECURITY
 683                 use_ipsec = txq->using_ipsec && (ol_flags & PKT_TX_SEC_OFFLOAD);
 684 #endif
 685
 686                 /* If hardware offload required */
 687                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 688                 if (tx_ol_req) {
 689                         tx_offload.l2_len = tx_pkt->l2_len;
 690                         tx_offload.l3_len = tx_pkt->l3_len;
 691                         tx_offload.l4_len = tx_pkt->l4_len;
 692                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 693                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 694                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 695                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 696 #ifdef RTE_LIBRTE_SECURITY
 697                         if (use_ipsec) {
 698                                 union ixgbe_crypto_tx_desc_md *ipsec_mdata =
 699                                         (union ixgbe_crypto_tx_desc_md *)
 700                                                         &tx_pkt->udata64;
 701                                 tx_offload.sa_idx = ipsec_mdata->sa_idx;
 702                                 tx_offload.sec_pad_len = ipsec_mdata->pad_len;
 703                         }
 704 #endif
 705
 706                         /* If new context need be built or reuse the exist ctx. */
 707                         ctx = what_advctx_update(txq, tx_ol_req,
 708                                 tx_offload);
 709                         /* Only allocate context descriptor if required*/
 710                         new_ctx = (ctx == IXGBE_CTX_NUM);
 711                         ctx = txq->ctx_curr;
 712                 }
 713
 714                 /*
 715                  * Keep track of how many descriptors are used this loop
 716                  * This will always be the number of segments + the number of
 717                  * Context descriptors required to transmit the packet
 718                  */
 719                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 720
 721                 if (txp != NULL &&
 722                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 723                         /* set RS on the previous packet in the burst */
 724                         txp->read.cmd_type_len |=
 725                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 726
 727                 /*
 728                  * The number of descriptors that must be allocated for a
 729                  * packet is the number of segments of that packet, plus 1
 730                  * Context Descriptor for the hardware offload, if any.
 731                  * Determine the last TX descriptor to allocate in the TX ring
 732                  * for the packet, starting from the current position (tx_id)
 733                  * in the ring.
 734                  */
 735                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 736
 737                 /* Circular ring */
 738                 if (tx_last >= txq->nb_tx_desc)
 739                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 740
 741                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 742                            " tx_first=%u tx_last=%u",
 743                            (unsigned) txq->port_id,
 744                            (unsigned) txq->queue_id,
 745                            (unsigned) pkt_len,
 746                            (unsigned) tx_id,
 747                            (unsigned) tx_last);
 748
 749                 /*
 750                  * Make sure there are enough TX descriptors available to
 751                  * transmit the entire packet.
 752                  * nb_used better be less than or equal to txq->tx_rs_thresh
 753                  */
 754                 if (nb_used > txq->nb_tx_free) {
 755                         PMD_TX_FREE_LOG(DEBUG,
 756                                         "Not enough free TX descriptors "
 757                                         "nb_used=%4u nb_free=%4u "
 758                                         "(port=%d queue=%d)",
 759                                         nb_used, txq->nb_tx_free,
 760                                         txq->port_id, txq->queue_id);
 761
 762                         if (ixgbe_xmit_cleanup(txq) != 0) {
 763                                 /* Could not clean any descriptors */
 764                                 if (nb_tx == 0)
 765                                         return 0;
 766                                 goto end_of_tx;
 767                         }
 768
 769                         /* nb_used better be <= txq->tx_rs_thresh */
 770                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 771                                 PMD_TX_FREE_LOG(DEBUG,
 772                                         "The number of descriptors needed to "
 773                                         "transmit the packet exceeds the "
 774                                         "RS bit threshold. This will impact "
 775                                         "performance."
 776                                         "nb_used=%4u nb_free=%4u "
 777                                         "tx_rs_thresh=%4u. "
 778                                         "(port=%d queue=%d)",
 779                                         nb_used, txq->nb_tx_free,
 780                                         txq->tx_rs_thresh,
 781                                         txq->port_id, txq->queue_id);
 782                                 /*
 783                                  * Loop here until there are enough TX
 784                                  * descriptors or until the ring cannot be
 785                                  * cleaned.
 786                                  */
 787                                 while (nb_used > txq->nb_tx_free) {
 788                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 789                                                 /*
 790                                                  * Could not clean any
 791                                                  * descriptors
 792                                                  */
 793                                                 if (nb_tx == 0)
 794                                                         return 0;
 795                                                 goto end_of_tx;
 796                                         }
 797                                 }
 798                         }
 799                 }
 800
 801                 /*
 802                  * By now there are enough free TX descriptors to transmit
 803                  * the packet.
 804                  */
 805
 806                 /*
 807                  * Set common flags of all TX Data Descriptors.
 808                  *
 809                  * The following bits must be set in all Data Descriptors:
 810                  *   - IXGBE_ADVTXD_DTYP_DATA
 811                  *   - IXGBE_ADVTXD_DCMD_DEXT
 812                  *
 813                  * The following bits must be set in the first Data Descriptor
 814                  * and are ignored in the other ones:
 815                  *   - IXGBE_ADVTXD_DCMD_IFCS
 816                  *   - IXGBE_ADVTXD_MAC_1588
 817                  *   - IXGBE_ADVTXD_DCMD_VLE
 818                  *
 819                  * The following bits must only be set in the last Data
 820                  * Descriptor:
 821                  *   - IXGBE_TXD_CMD_EOP
 822                  *
 823                  * The following bits can be set in any Data Descriptor, but
 824                  * are only set in the last Data Descriptor:
 825                  *   - IXGBE_TXD_CMD_RS
 826                  */
 827                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 828                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 829
 830 #ifdef RTE_LIBRTE_IEEE1588
 831                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 832                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 833 #endif
 834
 835                 olinfo_status = 0;
 836                 if (tx_ol_req) {
 837
 838                         if (ol_flags & PKT_TX_TCP_SEG) {
 839                                 /* when TSO is on, paylen in descriptor is the
 840                                  * not the packet len but the tcp payload len */
 841                                 pkt_len -= (tx_offload.l2_len +
 842                                         tx_offload.l3_len + tx_offload.l4_len);
 843                         }
 844
 845                         /*
 846                          * Setup the TX Advanced Context Descriptor if required
 847                          */
 848                         if (new_ctx) {
 849                                 volatile struct ixgbe_adv_tx_context_desc *
 850                                     ctx_txd;
 851
 852                                 ctx_txd = (volatile struct
 853                                     ixgbe_adv_tx_context_desc *)
 854                                     &txr[tx_id];
 855
 856                                 txn = &sw_ring[txe->next_id];
 857                                 rte_prefetch0(&txn->mbuf->pool);
 858
 859                                 if (txe->mbuf != NULL) {
 860                                         rte_pktmbuf_free_seg(txe->mbuf);
 861                                         txe->mbuf = NULL;
 862                                 }
 863
 864                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 865                                         tx_offload, &tx_pkt->udata64);
 866
 867                                 txe->last_id = tx_last;
 868                                 tx_id = txe->next_id;
 869                                 txe = txn;
 870                         }
 871
 872                         /*
 873                          * Setup the TX Advanced Data Descriptor,
 874                          * This path will go through
 875                          * whatever new/reuse the context descriptor
 876                          */
 877                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 878                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 879                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 880                 }
 881
 882                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 883 #ifdef RTE_LIBRTE_SECURITY
 884                 if (use_ipsec)
 885                         olinfo_status |= IXGBE_ADVTXD_POPTS_IPSEC;
 886 #endif
 887
 888                 m_seg = tx_pkt;
 889                 do {
 890                         txd = &txr[tx_id];
 891                         txn = &sw_ring[txe->next_id];
 892                         rte_prefetch0(&txn->mbuf->pool);
 893
 894                         if (txe->mbuf != NULL)
 895                                 rte_pktmbuf_free_seg(txe->mbuf);
 896                         txe->mbuf = m_seg;
 897
 898                         /*
 899                          * Set up Transmit Data Descriptor.
 900                          */
 901                         slen = m_seg->data_len;
 902                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
 903                         txd->read.buffer_addr =
 904                                 rte_cpu_to_le_64(buf_dma_addr);
 905                         txd->read.cmd_type_len =
 906                                 rte_cpu_to_le_32(cmd_type_len | slen);
 907                         txd->read.olinfo_status =
 908                                 rte_cpu_to_le_32(olinfo_status);
 909                         txe->last_id = tx_last;
 910                         tx_id = txe->next_id;
 911                         txe = txn;
 912                         m_seg = m_seg->next;
 913                 } while (m_seg != NULL);
 914
 915                 /*
 916                  * The last packet data descriptor needs End Of Packet (EOP)
 917                  */
 918                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 919                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 920                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 921
 922                 /* Set RS bit only on threshold packets' last descriptor */
 923                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 924                         PMD_TX_FREE_LOG(DEBUG,
 925                                         "Setting RS bit on TXD id="
 926                                         "%4u (port=%d queue=%d)",
 927                                         tx_last, txq->port_id, txq->queue_id);
 928
 929                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 930
 931                         /* Update txq RS bit counters */
 932                         txq->nb_tx_used = 0;
 933                         txp = NULL;
 934                 } else
 935                         txp = txd;
 936
 937                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 938         }
 939
 940 end_of_tx:
 941         /* set RS on last packet in the burst */
 942         if (txp != NULL)
 943                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 944
 945         rte_wmb();
 946
 947         /*
 948          * Set the Transmit Descriptor Tail (TDT)
 949          */
 950         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 951                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 952                    (unsigned) tx_id, (unsigned) nb_tx);
 953         IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 954         txq->tx_tail = tx_id;
 955
 956         return nb_tx;
 957 }
 958
 959 /*********************************************************************
 960  *
 961  *  TX prep functions
 962  *
 963  **********************************************************************/
 964 uint16_t
 965 ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 966 {
 967         int i, ret;
 968         uint64_t ol_flags;
 969         struct rte_mbuf *m;
 970         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 971
 972         for (i = 0; i < nb_pkts; i++) {
 973                 m = tx_pkts[i];
 974                 ol_flags = m->ol_flags;
 975
 976                 /**
 977                  * Check if packet meets requirements for number of segments
 978                  *
 979                  * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and
 980                  *       non-TSO
 981                  */
 982
 983                 if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) {
 984                         rte_errno = -EINVAL;
 985                         return i;
 986                 }
 987
 988                 if (ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) {
 989                         rte_errno = -ENOTSUP;
 990                         return i;
 991                 }
 992
 993 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 994                 ret = rte_validate_tx_offload(m);
 995                 if (ret != 0) {
 996                         rte_errno = ret;
 997                         return i;
 998                 }
 999 #endif
1000                 ret = rte_net_intel_cksum_prepare(m);
1001                 if (ret != 0) {
1002                         rte_errno = ret;
1003                         return i;
1004                 }
1005         }
1006
1007         return i;
1008 }
1009
1010 /*********************************************************************
1011  *
1012  *  RX functions
1013  *
1014  **********************************************************************/
1015
1016 #define IXGBE_PACKET_TYPE_ETHER                         0X00
1017 #define IXGBE_PACKET_TYPE_IPV4                          0X01
1018 #define IXGBE_PACKET_TYPE_IPV4_TCP                      0X11
1019 #define IXGBE_PACKET_TYPE_IPV4_UDP                      0X21
1020 #define IXGBE_PACKET_TYPE_IPV4_SCTP                     0X41
1021 #define IXGBE_PACKET_TYPE_IPV4_EXT                      0X03
1022 #define IXGBE_PACKET_TYPE_IPV4_EXT_TCP                  0X13
1023 #define IXGBE_PACKET_TYPE_IPV4_EXT_UDP                  0X23
1024 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP                 0X43
1025 #define IXGBE_PACKET_TYPE_IPV6                          0X04
1026 #define IXGBE_PACKET_TYPE_IPV6_TCP                      0X14
1027 #define IXGBE_PACKET_TYPE_IPV6_UDP                      0X24
1028 #define IXGBE_PACKET_TYPE_IPV6_SCTP                     0X44
1029 #define IXGBE_PACKET_TYPE_IPV6_EXT                      0X0C
1030 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP                  0X1C
1031 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP                  0X2C
1032 #define IXGBE_PACKET_TYPE_IPV6_EXT_SCTP                 0X4C
1033 #define IXGBE_PACKET_TYPE_IPV4_IPV6                     0X05
1034 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP                 0X15
1035 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP                 0X25
1036 #define IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP                0X45
1037 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6                 0X07
1038 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP             0X17
1039 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP             0X27
1040 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP            0X47
1041 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT                 0X0D
1042 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP             0X1D
1043 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP             0X2D
1044 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP            0X4D
1045 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT             0X0F
1046 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP         0X1F
1047 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP         0X2F
1048 #define IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP        0X4F
1049
1050 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
1051 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
1052 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
1053 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
1054 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
1055 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
1056 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP      0X13
1057 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP      0X23
1058 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
1059 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
1060 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
1061 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
1062 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP         0X44
1063 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
1064 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
1065 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
1066 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP     0X4C
1067 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
1068 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
1069 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
1070 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
1071 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
1072 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
1073
1074 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
1075 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
1076 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
1077 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
1078 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
1079 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
1080 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP      0X93
1081 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP      0XA3
1082 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
1083 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
1084 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
1085 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
1086 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP         0XC4
1087 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
1088 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
1089 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
1090 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP     0XCC
1091 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
1092 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
1093 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
1094 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
1095 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
1096 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
1097
1098 /**
1099  * Use 2 different table for normal packet and tunnel packet
1100  * to save the space.
1101  */
1102 const uint32_t
1103         ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
1104         [IXGBE_PACKET_TYPE_ETHER] = RTE_PTYPE_L2_ETHER,
1105         [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
1106                 RTE_PTYPE_L3_IPV4,
1107         [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1108                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1109         [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1110                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1111         [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1112                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1113         [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1114                 RTE_PTYPE_L3_IPV4_EXT,
1115         [IXGBE_PACKET_TYPE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1116                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
1117         [IXGBE_PACKET_TYPE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1118                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
1119         [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1120                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1121         [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1122                 RTE_PTYPE_L3_IPV6,
1123         [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1124                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1125         [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1126                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1127         [IXGBE_PACKET_TYPE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1128                 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP,
1129         [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1130                 RTE_PTYPE_L3_IPV6_EXT,
1131         [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1132                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1133         [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1134                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1135         [IXGBE_PACKET_TYPE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1136                 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_SCTP,
1137         [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1138                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1139                 RTE_PTYPE_INNER_L3_IPV6,
1140         [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1141                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1142                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1143         [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1144                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1145         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1146         [IXGBE_PACKET_TYPE_IPV4_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1147                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1148                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1149         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6] = RTE_PTYPE_L2_ETHER |
1150                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1151                 RTE_PTYPE_INNER_L3_IPV6,
1152         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1153                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1154                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1155         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1156                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1157                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1158         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1159                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1160                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1161         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1162                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1163                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1164         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1165                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1166                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1167         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1168                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1169                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1170         [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1171                 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1172                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1173         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1174                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1175                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1176         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1177                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1178                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1179         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1180                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1181                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1182         [IXGBE_PACKET_TYPE_IPV4_EXT_IPV6_EXT_SCTP] =
1183                 RTE_PTYPE_L2_ETHER |
1184                 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_IP |
1185                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1186 };
1187
1188 const uint32_t
1189         ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1190         [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1191                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1192                 RTE_PTYPE_INNER_L2_ETHER,
1193         [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1194                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1195                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1196         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1197                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1198                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1199         [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1200                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1201                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1202         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1203                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1204                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1205         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1206                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1207                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1208         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1209                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1210                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1211         [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1212                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1213                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1214                 RTE_PTYPE_INNER_L4_TCP,
1215         [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1216                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1217                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1218                 RTE_PTYPE_INNER_L4_TCP,
1219         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1220                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1221                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1222         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1223                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1224                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1225                 RTE_PTYPE_INNER_L4_TCP,
1226         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1227                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1228                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1229                 RTE_PTYPE_INNER_L3_IPV4,
1230         [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1231                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1232                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1233                 RTE_PTYPE_INNER_L4_UDP,
1234         [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1235                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1236                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1237                 RTE_PTYPE_INNER_L4_UDP,
1238         [IXGBE_PACKET_TYPE_NVGRE_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1239                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1240                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1241                 RTE_PTYPE_INNER_L4_SCTP,
1242         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1243                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1244                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1245         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1246                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1247                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1248                 RTE_PTYPE_INNER_L4_UDP,
1249         [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1250                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1251                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1252                 RTE_PTYPE_INNER_L4_SCTP,
1253         [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1254                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1255                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1256                 RTE_PTYPE_INNER_L3_IPV4,
1257         [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1258                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1259                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1260                 RTE_PTYPE_INNER_L4_SCTP,
1261         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1262                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1263                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1264                 RTE_PTYPE_INNER_L4_SCTP,
1265         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1266                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1267                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1268                 RTE_PTYPE_INNER_L4_TCP,
1269         [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1270                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1271                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1272                 RTE_PTYPE_INNER_L4_UDP,
1273
1274         [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1275                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1276                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1277         [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1278                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1279                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1280                 RTE_PTYPE_INNER_L3_IPV4,
1281         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1282                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1283                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1284                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1285         [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1286                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1287                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1288                 RTE_PTYPE_INNER_L3_IPV6,
1289         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1290                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1291                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1292                 RTE_PTYPE_INNER_L3_IPV4,
1293         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1294                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1295                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1296                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1297         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1298                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1299                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1300                 RTE_PTYPE_INNER_L3_IPV4,
1301         [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1302                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1303                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1304                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1305         [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1306                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1307                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1308                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1309         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1310                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1311                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1312                 RTE_PTYPE_INNER_L3_IPV4,
1313         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1314                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1315                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1316                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1317         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1318                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1319                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1320                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1321         [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1322                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1323                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1324                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1325         [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1326                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1327                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1328                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1329         [IXGBE_PACKET_TYPE_VXLAN_IPV6_SCTP] = RTE_PTYPE_L2_ETHER |
1330                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1331                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1332                 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_SCTP,
1333         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1334                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1335                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1336                 RTE_PTYPE_INNER_L3_IPV4,
1337         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1338                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1339                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1340                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1341         [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1342                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1343                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1344                 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_SCTP,
1345         [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1346                 RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1347                 RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1348                 RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1349         [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1350                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1351                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1352                 RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1353         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1354                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1355                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1356                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1357         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1358                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1359                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1360                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_TCP,
1361         [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1362                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1363                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1364                 RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_UDP,
1365 };
1366
1367 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
1368 static inline uint32_t
1369 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
1370 {
1371
1372         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1373                 return RTE_PTYPE_UNKNOWN;
1374
1375         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1376
1377         /* For tunnel packet */
1378         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1379                 /* Remove the tunnel bit to save the space. */
1380                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1381                 return ptype_table_tn[pkt_info];
1382         }
1383
1384         /**
1385          * For x550, if it's not tunnel,
1386          * tunnel type bit should be set to 0.
1387          * Reuse 82599's mask.
1388          */
1389         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1390
1391         return ptype_table[pkt_info];
1392 }
1393
1394 static inline uint64_t
1395 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1396 {
1397         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1398                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1399                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1400                 PKT_RX_RSS_HASH, 0, 0, 0,
1401                 0, 0, 0,  PKT_RX_FDIR,
1402         };
1403 #ifdef RTE_LIBRTE_IEEE1588
1404         static uint64_t ip_pkt_etqf_map[8] = {
1405                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1406                 0, 0, 0, 0,
1407         };
1408
1409         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1410                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1411                                 ip_rss_types_map[pkt_info & 0XF];
1412         else
1413                 return ip_rss_types_map[pkt_info & 0XF];
1414 #else
1415         return ip_rss_types_map[pkt_info & 0XF];
1416 #endif
1417 }
1418
1419 static inline uint64_t
1420 rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)
1421 {
1422         uint64_t pkt_flags;
1423
1424         /*
1425          * Check if VLAN present only.
1426          * Do not check whether L3/L4 rx checksum done by NIC or not,
1427          * That can be found from rte_eth_rxmode.offloads flag
1428          */
1429         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  vlan_flags : 0;
1430
1431 #ifdef RTE_LIBRTE_IEEE1588
1432         if (rx_status & IXGBE_RXD_STAT_TMST)
1433                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1434 #endif
1435         return pkt_flags;
1436 }
1437
1438 static inline uint64_t
1439 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1440 {
1441         uint64_t pkt_flags;
1442
1443         /*
1444          * Bit 31: IPE, IPv4 checksum error
1445          * Bit 30: L4I, L4I integrity error
1446          */
1447         static uint64_t error_to_pkt_flags_map[4] = {
1448                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
1449                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
1450                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
1451                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1452         };
1453         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1454                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1455
1456         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1457             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1458                 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1459         }
1460
1461 #ifdef RTE_LIBRTE_SECURITY
1462         if (rx_status & IXGBE_RXD_STAT_SECP) {
1463                 pkt_flags |= PKT_RX_SEC_OFFLOAD;
1464                 if (rx_status & IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG)
1465                         pkt_flags |= PKT_RX_SEC_OFFLOAD_FAILED;
1466         }
1467 #endif
1468
1469         return pkt_flags;
1470 }
1471
1472 /*
1473  * LOOK_AHEAD defines how many desc statuses to check beyond the
1474  * current descriptor.
1475  * It must be a pound define for optimal performance.
1476  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1477  * function only works with LOOK_AHEAD=8.
1478  */
1479 #define LOOK_AHEAD 8
1480 #if (LOOK_AHEAD != 8)
1481 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1482 #endif
1483 static inline int
1484 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1485 {
1486         volatile union ixgbe_adv_rx_desc *rxdp;
1487         struct ixgbe_rx_entry *rxep;
1488         struct rte_mbuf *mb;
1489         uint16_t pkt_len;
1490         uint64_t pkt_flags;
1491         int nb_dd;
1492         uint32_t s[LOOK_AHEAD];
1493         uint32_t pkt_info[LOOK_AHEAD];
1494         int i, j, nb_rx = 0;
1495         uint32_t status;
1496         uint64_t vlan_flags = rxq->vlan_flags;
1497
1498         /* get references to current descriptor and S/W ring entry */
1499         rxdp = &rxq->rx_ring[rxq->rx_tail];
1500         rxep = &rxq->sw_ring[rxq->rx_tail];
1501
1502         status = rxdp->wb.upper.status_error;
1503         /* check to make sure there is at least 1 packet to receive */
1504         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1505                 return 0;
1506
1507         /*
1508          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1509          * reference packets that are ready to be received.
1510          */
1511         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1512              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1513                 /* Read desc statuses backwards to avoid race condition */
1514                 for (j = 0; j < LOOK_AHEAD; j++)
1515                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1516
1517                 rte_smp_rmb();
1518
1519                 /* Compute how many status bits were set */
1520                 for (nb_dd = 0; nb_dd < LOOK_AHEAD &&
1521                                 (s[nb_dd] & IXGBE_RXDADV_STAT_DD); nb_dd++)
1522                         ;
1523
1524                 for (j = 0; j < nb_dd; j++)
1525                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1526                                                        lo_dword.data);
1527
1528                 nb_rx += nb_dd;
1529
1530                 /* Translate descriptor info to mbuf format */
1531                 for (j = 0; j < nb_dd; ++j) {
1532                         mb = rxep[j].mbuf;
1533                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1534                                   rxq->crc_len;
1535                         mb->data_len = pkt_len;
1536                         mb->pkt_len = pkt_len;
1537                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1538
1539                         /* convert descriptor fields to rte mbuf flags */
1540                         pkt_flags = rx_desc_status_to_pkt_flags(s[j],
1541                                 vlan_flags);
1542                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1543                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1544                                         ((uint16_t)pkt_info[j]);
1545                         mb->ol_flags = pkt_flags;
1546                         mb->packet_type =
1547                                 ixgbe_rxd_pkt_info_to_pkt_type
1548                                         (pkt_info[j], rxq->pkt_type_mask);
1549
1550                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1551                                 mb->hash.rss = rte_le_to_cpu_32(
1552                                     rxdp[j].wb.lower.hi_dword.rss);
1553                         else if (pkt_flags & PKT_RX_FDIR) {
1554                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1555                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1556                                     IXGBE_ATR_HASH_MASK;
1557                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1558                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1559                         }
1560                 }
1561
1562                 /* Move mbuf pointers from the S/W ring to the stage */
1563                 for (j = 0; j < LOOK_AHEAD; ++j) {
1564                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1565                 }
1566
1567                 /* stop if all requested packets could not be received */
1568                 if (nb_dd != LOOK_AHEAD)
1569                         break;
1570         }
1571
1572         /* clear software ring entries so we can cleanup correctly */
1573         for (i = 0; i < nb_rx; ++i) {
1574                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1575         }
1576
1577
1578         return nb_rx;
1579 }
1580
1581 static inline int
1582 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1583 {
1584         volatile union ixgbe_adv_rx_desc *rxdp;
1585         struct ixgbe_rx_entry *rxep;
1586         struct rte_mbuf *mb;
1587         uint16_t alloc_idx;
1588         __le64 dma_addr;
1589         int diag, i;
1590
1591         /* allocate buffers in bulk directly into the S/W ring */
1592         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1593         rxep = &rxq->sw_ring[alloc_idx];
1594         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1595                                     rxq->rx_free_thresh);
1596         if (unlikely(diag != 0))
1597                 return -ENOMEM;
1598
1599         rxdp = &rxq->rx_ring[alloc_idx];
1600         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1601                 /* populate the static rte mbuf fields */
1602                 mb = rxep[i].mbuf;
1603                 if (reset_mbuf) {
1604                         mb->port = rxq->port_id;
1605                 }
1606
1607                 rte_mbuf_refcnt_set(mb, 1);
1608                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1609
1610                 /* populate the descriptors */
1611                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1612                 rxdp[i].read.hdr_addr = 0;
1613                 rxdp[i].read.pkt_addr = dma_addr;
1614         }
1615
1616         /* update state of internal queue structure */
1617         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1618         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1619                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1620
1621         /* no errors */
1622         return 0;
1623 }
1624
1625 static inline uint16_t
1626 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1627                          uint16_t nb_pkts)
1628 {
1629         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1630         int i;
1631
1632         /* how many packets are ready to return? */
1633         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1634
1635         /* copy mbuf pointers to the application's packet list */
1636         for (i = 0; i < nb_pkts; ++i)
1637                 rx_pkts[i] = stage[i];
1638
1639         /* update internal queue state */
1640         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1641         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1642
1643         return nb_pkts;
1644 }
1645
1646 static inline uint16_t
1647 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1648              uint16_t nb_pkts)
1649 {
1650         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1651         uint16_t nb_rx = 0;
1652
1653         /* Any previously recv'd pkts will be returned from the Rx stage */
1654         if (rxq->rx_nb_avail)
1655                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1656
1657         /* Scan the H/W ring for packets to receive */
1658         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1659
1660         /* update internal queue state */
1661         rxq->rx_next_avail = 0;
1662         rxq->rx_nb_avail = nb_rx;
1663         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1664
1665         /* if required, allocate new buffers to replenish descriptors */
1666         if (rxq->rx_tail > rxq->rx_free_trigger) {
1667                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1668
1669                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1670                         int i, j;
1671
1672                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1673                                    "queue_id=%u", (unsigned) rxq->port_id,
1674                                    (unsigned) rxq->queue_id);
1675
1676                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1677                                 rxq->rx_free_thresh;
1678
1679                         /*
1680                          * Need to rewind any previous receives if we cannot
1681                          * allocate new buffers to replenish the old ones.
1682                          */
1683                         rxq->rx_nb_avail = 0;
1684                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1685                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1686                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1687
1688                         return 0;
1689                 }
1690
1691                 /* update tail pointer */
1692                 rte_wmb();
1693                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
1694                                             cur_free_trigger);
1695         }
1696
1697         if (rxq->rx_tail >= rxq->nb_rx_desc)
1698                 rxq->rx_tail = 0;
1699
1700         /* received any packets this loop? */
1701         if (rxq->rx_nb_avail)
1702                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1703
1704         return 0;
1705 }
1706
1707 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1708 uint16_t
1709 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1710                            uint16_t nb_pkts)
1711 {
1712         uint16_t nb_rx;
1713
1714         if (unlikely(nb_pkts == 0))
1715                 return 0;
1716
1717         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1718                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1719
1720         /* request is relatively large, chunk it up */
1721         nb_rx = 0;
1722         while (nb_pkts) {
1723                 uint16_t ret, n;
1724
1725                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1726                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1727                 nb_rx = (uint16_t)(nb_rx + ret);
1728                 nb_pkts = (uint16_t)(nb_pkts - ret);
1729                 if (ret < n)
1730                         break;
1731         }
1732
1733         return nb_rx;
1734 }
1735
1736 uint16_t
1737 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1738                 uint16_t nb_pkts)
1739 {
1740         struct ixgbe_rx_queue *rxq;
1741         volatile union ixgbe_adv_rx_desc *rx_ring;
1742         volatile union ixgbe_adv_rx_desc *rxdp;
1743         struct ixgbe_rx_entry *sw_ring;
1744         struct ixgbe_rx_entry *rxe;
1745         struct rte_mbuf *rxm;
1746         struct rte_mbuf *nmb;
1747         union ixgbe_adv_rx_desc rxd;
1748         uint64_t dma_addr;
1749         uint32_t staterr;
1750         uint32_t pkt_info;
1751         uint16_t pkt_len;
1752         uint16_t rx_id;
1753         uint16_t nb_rx;
1754         uint16_t nb_hold;
1755         uint64_t pkt_flags;
1756         uint64_t vlan_flags;
1757
1758         nb_rx = 0;
1759         nb_hold = 0;
1760         rxq = rx_queue;
1761         rx_id = rxq->rx_tail;
1762         rx_ring = rxq->rx_ring;
1763         sw_ring = rxq->sw_ring;
1764         vlan_flags = rxq->vlan_flags;
1765         while (nb_rx < nb_pkts) {
1766                 /*
1767                  * The order of operations here is important as the DD status
1768                  * bit must not be read after any other descriptor fields.
1769                  * rx_ring and rxdp are pointing to volatile data so the order
1770                  * of accesses cannot be reordered by the compiler. If they were
1771                  * not volatile, they could be reordered which could lead to
1772                  * using invalid descriptor fields when read from rxd.
1773                  */
1774                 rxdp = &rx_ring[rx_id];
1775                 staterr = rxdp->wb.upper.status_error;
1776                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1777                         break;
1778                 rxd = *rxdp;
1779
1780                 /*
1781                  * End of packet.
1782                  *
1783                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1784                  * is likely to be invalid and to be dropped by the various
1785                  * validation checks performed by the network stack.
1786                  *
1787                  * Allocate a new mbuf to replenish the RX ring descriptor.
1788                  * If the allocation fails:
1789                  *    - arrange for that RX descriptor to be the first one
1790                  *      being parsed the next time the receive function is
1791                  *      invoked [on the same queue].
1792                  *
1793                  *    - Stop parsing the RX ring and return immediately.
1794                  *
1795                  * This policy do not drop the packet received in the RX
1796                  * descriptor for which the allocation of a new mbuf failed.
1797                  * Thus, it allows that packet to be later retrieved if
1798                  * mbuf have been freed in the mean time.
1799                  * As a side effect, holding RX descriptors instead of
1800                  * systematically giving them back to the NIC may lead to
1801                  * RX ring exhaustion situations.
1802                  * However, the NIC can gracefully prevent such situations
1803                  * to happen by sending specific "back-pressure" flow control
1804                  * frames to its peer(s).
1805                  */
1806                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1807                            "ext_err_stat=0x%08x pkt_len=%u",
1808                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1809                            (unsigned) rx_id, (unsigned) staterr,
1810                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1811
1812                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1813                 if (nmb == NULL) {
1814                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1815                                    "queue_id=%u", (unsigned) rxq->port_id,
1816                                    (unsigned) rxq->queue_id);
1817                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1818                         break;
1819                 }
1820
1821                 nb_hold++;
1822                 rxe = &sw_ring[rx_id];
1823                 rx_id++;
1824                 if (rx_id == rxq->nb_rx_desc)
1825                         rx_id = 0;
1826
1827                 /* Prefetch next mbuf while processing current one. */
1828                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1829
1830                 /*
1831                  * When next RX descriptor is on a cache-line boundary,
1832                  * prefetch the next 4 RX descriptors and the next 8 pointers
1833                  * to mbufs.
1834                  */
1835                 if ((rx_id & 0x3) == 0) {
1836                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1837                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1838                 }
1839
1840                 rxm = rxe->mbuf;
1841                 rxe->mbuf = nmb;
1842                 dma_addr =
1843                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1844                 rxdp->read.hdr_addr = 0;
1845                 rxdp->read.pkt_addr = dma_addr;
1846
1847                 /*
1848                  * Initialize the returned mbuf.
1849                  * 1) setup generic mbuf fields:
1850                  *    - number of segments,
1851                  *    - next segment,
1852                  *    - packet length,
1853                  *    - RX port identifier.
1854                  * 2) integrate hardware offload data, if any:
1855                  *    - RSS flag & hash,
1856                  *    - IP checksum flag,
1857                  *    - VLAN TCI, if any,
1858                  *    - error flags.
1859                  */
1860                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1861                                       rxq->crc_len);
1862                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1863                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1864                 rxm->nb_segs = 1;
1865                 rxm->next = NULL;
1866                 rxm->pkt_len = pkt_len;
1867                 rxm->data_len = pkt_len;
1868                 rxm->port = rxq->port_id;
1869
1870                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1871                 /* Only valid if PKT_RX_VLAN set in pkt_flags */
1872                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1873
1874                 pkt_flags = rx_desc_status_to_pkt_flags(staterr, vlan_flags);
1875                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1876                 pkt_flags = pkt_flags |
1877                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1878                 rxm->ol_flags = pkt_flags;
1879                 rxm->packet_type =
1880                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1881                                                        rxq->pkt_type_mask);
1882
1883                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1884                         rxm->hash.rss = rte_le_to_cpu_32(
1885                                                 rxd.wb.lower.hi_dword.rss);
1886                 else if (pkt_flags & PKT_RX_FDIR) {
1887                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1888                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1889                                         IXGBE_ATR_HASH_MASK;
1890                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1891                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1892                 }
1893                 /*
1894                  * Store the mbuf address into the next entry of the array
1895                  * of returned packets.
1896                  */
1897                 rx_pkts[nb_rx++] = rxm;
1898         }
1899         rxq->rx_tail = rx_id;
1900
1901         /*
1902          * If the number of free RX descriptors is greater than the RX free
1903          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1904          * register.
1905          * Update the RDT with the value of the last processed RX descriptor
1906          * minus 1, to guarantee that the RDT register is never equal to the
1907          * RDH register, which creates a "full" ring situtation from the
1908          * hardware point of view...
1909          */
1910         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1911         if (nb_hold > rxq->rx_free_thresh) {
1912                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1913                            "nb_hold=%u nb_rx=%u",
1914                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1915                            (unsigned) rx_id, (unsigned) nb_hold,
1916                            (unsigned) nb_rx);
1917                 rx_id = (uint16_t) ((rx_id == 0) ?
1918                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1919                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1920                 nb_hold = 0;
1921         }
1922         rxq->nb_rx_hold = nb_hold;
1923         return nb_rx;
1924 }
1925
1926 /**
1927  * Detect an RSC descriptor.
1928  */
1929 static inline uint32_t
1930 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1931 {
1932         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1933                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1934 }
1935
1936 /**
1937  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1938  *
1939  * Fill the following info in the HEAD buffer of the Rx cluster:
1940  *    - RX port identifier
1941  *    - hardware offload data, if any:
1942  *      - RSS flag & hash
1943  *      - IP checksum flag
1944  *      - VLAN TCI, if any
1945  *      - error flags
1946  * @head HEAD of the packet cluster
1947  * @desc HW descriptor to get data from
1948  * @rxq Pointer to the Rx queue
1949  */
1950 static inline void
1951 ixgbe_fill_cluster_head_buf(
1952         struct rte_mbuf *head,
1953         union ixgbe_adv_rx_desc *desc,
1954         struct ixgbe_rx_queue *rxq,
1955         uint32_t staterr)
1956 {
1957         uint32_t pkt_info;
1958         uint64_t pkt_flags;
1959
1960         head->port = rxq->port_id;
1961
1962         /* The vlan_tci field is only valid when PKT_RX_VLAN is
1963          * set in the pkt_flags field.
1964          */
1965         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1966         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1967         pkt_flags = rx_desc_status_to_pkt_flags(staterr, rxq->vlan_flags);
1968         pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1969         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1970         head->ol_flags = pkt_flags;
1971         head->packet_type =
1972                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1973
1974         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1975                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1976         else if (pkt_flags & PKT_RX_FDIR) {
1977                 head->hash.fdir.hash =
1978                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1979                                                           & IXGBE_ATR_HASH_MASK;
1980                 head->hash.fdir.id =
1981                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1982         }
1983 }
1984
1985 /**
1986  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1987  *
1988  * @rx_queue Rx queue handle
1989  * @rx_pkts table of received packets
1990  * @nb_pkts size of rx_pkts table
1991  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1992  *
1993  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1994  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1995  *
1996  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1997  * 1) When non-EOP RSC completion arrives:
1998  *    a) Update the HEAD of the current RSC aggregation cluster with the new
1999  *       segment's data length.
2000  *    b) Set the "next" pointer of the current segment to point to the segment
2001  *       at the NEXTP index.
2002  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
2003  *       in the sw_rsc_ring.
2004  * 2) When EOP arrives we just update the cluster's total length and offload
2005  *    flags and deliver the cluster up to the upper layers. In our case - put it
2006  *    in the rx_pkts table.
2007  *
2008  * Returns the number of received packets/clusters (according to the "bulk
2009  * receive" interface).
2010  */
2011 static inline uint16_t
2012 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
2013                     bool bulk_alloc)
2014 {
2015         struct ixgbe_rx_queue *rxq = rx_queue;
2016         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
2017         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
2018         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
2019         uint16_t rx_id = rxq->rx_tail;
2020         uint16_t nb_rx = 0;
2021         uint16_t nb_hold = rxq->nb_rx_hold;
2022         uint16_t prev_id = rxq->rx_tail;
2023
2024         while (nb_rx < nb_pkts) {
2025                 bool eop;
2026                 struct ixgbe_rx_entry *rxe;
2027                 struct ixgbe_scattered_rx_entry *sc_entry;
2028                 struct ixgbe_scattered_rx_entry *next_sc_entry;
2029                 struct ixgbe_rx_entry *next_rxe = NULL;
2030                 struct rte_mbuf *first_seg;
2031                 struct rte_mbuf *rxm;
2032                 struct rte_mbuf *nmb;
2033                 union ixgbe_adv_rx_desc rxd;
2034                 uint16_t data_len;
2035                 uint16_t next_id;
2036                 volatile union ixgbe_adv_rx_desc *rxdp;
2037                 uint32_t staterr;
2038
2039 next_desc:
2040                 /*
2041                  * The code in this whole file uses the volatile pointer to
2042                  * ensure the read ordering of the status and the rest of the
2043                  * descriptor fields (on the compiler level only!!!). This is so
2044                  * UGLY - why not to just use the compiler barrier instead? DPDK
2045                  * even has the rte_compiler_barrier() for that.
2046                  *
2047                  * But most importantly this is just wrong because this doesn't
2048                  * ensure memory ordering in a general case at all. For
2049                  * instance, DPDK is supposed to work on Power CPUs where
2050                  * compiler barrier may just not be enough!
2051                  *
2052                  * I tried to write only this function properly to have a
2053                  * starting point (as a part of an LRO/RSC series) but the
2054                  * compiler cursed at me when I tried to cast away the
2055                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
2056                  * keeping it the way it is for now.
2057                  *
2058                  * The code in this file is broken in so many other places and
2059                  * will just not work on a big endian CPU anyway therefore the
2060                  * lines below will have to be revisited together with the rest
2061                  * of the ixgbe PMD.
2062                  *
2063                  * TODO:
2064                  *    - Get rid of "volatile" and let the compiler do its job.
2065                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
2066                  *      memory ordering below.
2067                  */
2068                 rxdp = &rx_ring[rx_id];
2069                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
2070
2071                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
2072                         break;
2073
2074                 rxd = *rxdp;
2075
2076                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
2077                                   "staterr=0x%x data_len=%u",
2078                            rxq->port_id, rxq->queue_id, rx_id, staterr,
2079                            rte_le_to_cpu_16(rxd.wb.upper.length));
2080
2081                 if (!bulk_alloc) {
2082                         nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
2083                         if (nmb == NULL) {
2084                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
2085                                                   "port_id=%u queue_id=%u",
2086                                            rxq->port_id, rxq->queue_id);
2087
2088                                 rte_eth_devices[rxq->port_id].data->
2089                                                         rx_mbuf_alloc_failed++;
2090                                 break;
2091                         }
2092                 } else if (nb_hold > rxq->rx_free_thresh) {
2093                         uint16_t next_rdt = rxq->rx_free_trigger;
2094
2095                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
2096                                 rte_wmb();
2097                                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
2098                                                             next_rdt);
2099                                 nb_hold -= rxq->rx_free_thresh;
2100                         } else {
2101                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
2102                                                   "port_id=%u queue_id=%u",
2103                                            rxq->port_id, rxq->queue_id);
2104
2105                                 rte_eth_devices[rxq->port_id].data->
2106                                                         rx_mbuf_alloc_failed++;
2107                                 break;
2108                         }
2109                 }
2110
2111                 nb_hold++;
2112                 rxe = &sw_ring[rx_id];
2113                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
2114
2115                 next_id = rx_id + 1;
2116                 if (next_id == rxq->nb_rx_desc)
2117                         next_id = 0;
2118
2119                 /* Prefetch next mbuf while processing current one. */
2120                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
2121
2122                 /*
2123                  * When next RX descriptor is on a cache-line boundary,
2124                  * prefetch the next 4 RX descriptors and the next 4 pointers
2125                  * to mbufs.
2126                  */
2127                 if ((next_id & 0x3) == 0) {
2128                         rte_ixgbe_prefetch(&rx_ring[next_id]);
2129                         rte_ixgbe_prefetch(&sw_ring[next_id]);
2130                 }
2131
2132                 rxm = rxe->mbuf;
2133
2134                 if (!bulk_alloc) {
2135                         __le64 dma =
2136                           rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2137                         /*
2138                          * Update RX descriptor with the physical address of the
2139                          * new data buffer of the new allocated mbuf.
2140                          */
2141                         rxe->mbuf = nmb;
2142
2143                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
2144                         rxdp->read.hdr_addr = 0;
2145                         rxdp->read.pkt_addr = dma;
2146                 } else
2147                         rxe->mbuf = NULL;
2148
2149                 /*
2150                  * Set data length & data buffer address of mbuf.
2151                  */
2152                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
2153                 rxm->data_len = data_len;
2154
2155                 if (!eop) {
2156                         uint16_t nextp_id;
2157                         /*
2158                          * Get next descriptor index:
2159                          *  - For RSC it's in the NEXTP field.
2160                          *  - For a scattered packet - it's just a following
2161                          *    descriptor.
2162                          */
2163                         if (ixgbe_rsc_count(&rxd))
2164                                 nextp_id =
2165                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
2166                                                        IXGBE_RXDADV_NEXTP_SHIFT;
2167                         else
2168                                 nextp_id = next_id;
2169
2170                         next_sc_entry = &sw_sc_ring[nextp_id];
2171                         next_rxe = &sw_ring[nextp_id];
2172                         rte_ixgbe_prefetch(next_rxe);
2173                 }
2174
2175                 sc_entry = &sw_sc_ring[rx_id];
2176                 first_seg = sc_entry->fbuf;
2177                 sc_entry->fbuf = NULL;
2178
2179                 /*
2180                  * If this is the first buffer of the received packet,
2181                  * set the pointer to the first mbuf of the packet and
2182                  * initialize its context.
2183                  * Otherwise, update the total length and the number of segments
2184                  * of the current scattered packet, and update the pointer to
2185                  * the last mbuf of the current packet.
2186                  */
2187                 if (first_seg == NULL) {
2188                         first_seg = rxm;
2189                         first_seg->pkt_len = data_len;
2190                         first_seg->nb_segs = 1;
2191                 } else {
2192                         first_seg->pkt_len += data_len;
2193                         first_seg->nb_segs++;
2194                 }
2195
2196                 prev_id = rx_id;
2197                 rx_id = next_id;
2198
2199                 /*
2200                  * If this is not the last buffer of the received packet, update
2201                  * the pointer to the first mbuf at the NEXTP entry in the
2202                  * sw_sc_ring and continue to parse the RX ring.
2203                  */
2204                 if (!eop && next_rxe) {
2205                         rxm->next = next_rxe->mbuf;
2206                         next_sc_entry->fbuf = first_seg;
2207                         goto next_desc;
2208                 }
2209
2210                 /* Initialize the first mbuf of the returned packet */
2211                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2212
2213                 /*
2214                  * Deal with the case, when HW CRC srip is disabled.
2215                  * That can't happen when LRO is enabled, but still could
2216                  * happen for scattered RX mode.
2217                  */
2218                 first_seg->pkt_len -= rxq->crc_len;
2219                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2220                         struct rte_mbuf *lp;
2221
2222                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2223                                 ;
2224
2225                         first_seg->nb_segs--;
2226                         lp->data_len -= rxq->crc_len - rxm->data_len;
2227                         lp->next = NULL;
2228                         rte_pktmbuf_free_seg(rxm);
2229                 } else
2230                         rxm->data_len -= rxq->crc_len;
2231
2232                 /* Prefetch data of first segment, if configured to do so. */
2233                 rte_packet_prefetch((char *)first_seg->buf_addr +
2234                         first_seg->data_off);
2235
2236                 /*
2237                  * Store the mbuf address into the next entry of the array
2238                  * of returned packets.
2239                  */
2240                 rx_pkts[nb_rx++] = first_seg;
2241         }
2242
2243         /*
2244          * Record index of the next RX descriptor to probe.
2245          */
2246         rxq->rx_tail = rx_id;
2247
2248         /*
2249          * If the number of free RX descriptors is greater than the RX free
2250          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2251          * register.
2252          * Update the RDT with the value of the last processed RX descriptor
2253          * minus 1, to guarantee that the RDT register is never equal to the
2254          * RDH register, which creates a "full" ring situtation from the
2255          * hardware point of view...
2256          */
2257         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2258                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2259                            "nb_hold=%u nb_rx=%u",
2260                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2261
2262                 rte_wmb();
2263                 IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
2264                 nb_hold = 0;
2265         }
2266
2267         rxq->nb_rx_hold = nb_hold;
2268         return nb_rx;
2269 }
2270
2271 uint16_t
2272 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2273                                  uint16_t nb_pkts)
2274 {
2275         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2276 }
2277
2278 uint16_t
2279 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2280                                uint16_t nb_pkts)
2281 {
2282         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2283 }
2284
2285 /*********************************************************************
2286  *
2287  *  Queue management functions
2288  *
2289  **********************************************************************/
2290
2291 static void __attribute__((cold))
2292 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2293 {
2294         unsigned i;
2295
2296         if (txq->sw_ring != NULL) {
2297                 for (i = 0; i < txq->nb_tx_desc; i++) {
2298                         if (txq->sw_ring[i].mbuf != NULL) {
2299                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2300                                 txq->sw_ring[i].mbuf = NULL;
2301                         }
2302                 }
2303         }
2304 }
2305
2306 static void __attribute__((cold))
2307 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2308 {
2309         if (txq != NULL &&
2310             txq->sw_ring != NULL)
2311                 rte_free(txq->sw_ring);
2312 }
2313
2314 static void __attribute__((cold))
2315 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2316 {
2317         if (txq != NULL && txq->ops != NULL) {
2318                 txq->ops->release_mbufs(txq);
2319                 txq->ops->free_swring(txq);
2320                 rte_free(txq);
2321         }
2322 }
2323
2324 void __attribute__((cold))
2325 ixgbe_dev_tx_queue_release(void *txq)
2326 {
2327         ixgbe_tx_queue_release(txq);
2328 }
2329
2330 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2331 static void __attribute__((cold))
2332 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2333 {
2334         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2335         struct ixgbe_tx_entry *txe = txq->sw_ring;
2336         uint16_t prev, i;
2337
2338         /* Zero out HW ring memory */
2339         for (i = 0; i < txq->nb_tx_desc; i++) {
2340                 txq->tx_ring[i] = zeroed_desc;
2341         }
2342
2343         /* Initialize SW ring entries */
2344         prev = (uint16_t) (txq->nb_tx_desc - 1);
2345         for (i = 0; i < txq->nb_tx_desc; i++) {
2346                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2347
2348                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2349                 txe[i].mbuf = NULL;
2350                 txe[i].last_id = i;
2351                 txe[prev].next_id = i;
2352                 prev = i;
2353         }
2354
2355         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2356         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2357
2358         txq->tx_tail = 0;
2359         txq->nb_tx_used = 0;
2360         /*
2361          * Always allow 1 descriptor to be un-allocated to avoid
2362          * a H/W race condition
2363          */
2364         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2365         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2366         txq->ctx_curr = 0;
2367         memset((void *)&txq->ctx_cache, 0,
2368                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2369 }
2370
2371 static const struct ixgbe_txq_ops def_txq_ops = {
2372         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2373         .free_swring = ixgbe_tx_free_swring,
2374         .reset = ixgbe_reset_tx_queue,
2375 };
2376
2377 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2378  * the queue parameters. Used in tx_queue_setup by primary process and then
2379  * in dev_init by secondary process when attaching to an existing ethdev.
2380  */
2381 void __attribute__((cold))
2382 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2383 {
2384         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2385         if ((txq->offloads == 0) &&
2386 #ifdef RTE_LIBRTE_SECURITY
2387                         !(txq->using_ipsec) &&
2388 #endif
2389                         (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2390                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2391                 dev->tx_pkt_prepare = NULL;
2392 #ifdef RTE_IXGBE_INC_VECTOR
2393                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2394                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2395                                         ixgbe_txq_vec_setup(txq) == 0)) {
2396                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2397                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2398                 } else
2399 #endif
2400                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2401         } else {
2402                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2403                 PMD_INIT_LOG(DEBUG,
2404                                 " - offloads = 0x%" PRIx64,
2405                                 txq->offloads);
2406                 PMD_INIT_LOG(DEBUG,
2407                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2408                                 (unsigned long)txq->tx_rs_thresh,
2409                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2410                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2411                 dev->tx_pkt_prepare = ixgbe_prep_pkts;
2412         }
2413 }
2414
2415 uint64_t
2416 ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev)
2417 {
2418         RTE_SET_USED(dev);
2419
2420         return 0;
2421 }
2422
2423 uint64_t
2424 ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
2425 {
2426         uint64_t tx_offload_capa;
2427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428
2429         tx_offload_capa =
2430                 DEV_TX_OFFLOAD_VLAN_INSERT |
2431                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2432                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2433                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2434                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2435                 DEV_TX_OFFLOAD_TCP_TSO     |
2436                 DEV_TX_OFFLOAD_MULTI_SEGS;
2437
2438         if (hw->mac.type == ixgbe_mac_82599EB ||
2439             hw->mac.type == ixgbe_mac_X540)
2440                 tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
2441
2442         if (hw->mac.type == ixgbe_mac_X550 ||
2443             hw->mac.type == ixgbe_mac_X550EM_x ||
2444             hw->mac.type == ixgbe_mac_X550EM_a)
2445                 tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2446
2447 #ifdef RTE_LIBRTE_SECURITY
2448         if (dev->security_ctx)
2449                 tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2450 #endif
2451         return tx_offload_capa;
2452 }
2453
2454 int __attribute__((cold))
2455 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2456                          uint16_t queue_idx,
2457                          uint16_t nb_desc,
2458                          unsigned int socket_id,
2459                          const struct rte_eth_txconf *tx_conf)
2460 {
2461         const struct rte_memzone *tz;
2462         struct ixgbe_tx_queue *txq;
2463         struct ixgbe_hw     *hw;
2464         uint16_t tx_rs_thresh, tx_free_thresh;
2465         uint64_t offloads;
2466
2467         PMD_INIT_FUNC_TRACE();
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469
2470         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2471
2472         /*
2473          * Validate number of transmit descriptors.
2474          * It must not exceed hardware maximum, and must be multiple
2475          * of IXGBE_ALIGN.
2476          */
2477         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2478                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2479                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2480                 return -EINVAL;
2481         }
2482
2483         /*
2484          * The following two parameters control the setting of the RS bit on
2485          * transmit descriptors.
2486          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2487          * descriptors have been used.
2488          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2489          * descriptors are used or if the number of descriptors required
2490          * to transmit a packet is greater than the number of free TX
2491          * descriptors.
2492          * The following constraints must be satisfied:
2493          *  tx_rs_thresh must be greater than 0.
2494          *  tx_rs_thresh must be less than the size of the ring minus 2.
2495          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2496          *  tx_rs_thresh must be a divisor of the ring size.
2497          *  tx_free_thresh must be greater than 0.
2498          *  tx_free_thresh must be less than the size of the ring minus 3.
2499          * One descriptor in the TX ring is used as a sentinel to avoid a
2500          * H/W race condition, hence the maximum threshold constraints.
2501          * When set to zero use default values.
2502          */
2503         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2504                         tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2505         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2506                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2507         if (tx_rs_thresh >= (nb_desc - 2)) {
2508                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2509                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2510                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2511                         (int)dev->data->port_id, (int)queue_idx);
2512                 return -(EINVAL);
2513         }
2514         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2515                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2516                         "(tx_rs_thresh=%u port=%d queue=%d)",
2517                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2518                         (int)dev->data->port_id, (int)queue_idx);
2519                 return -(EINVAL);
2520         }
2521         if (tx_free_thresh >= (nb_desc - 3)) {
2522                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2523                              "tx_free_thresh must be less than the number of "
2524                              "TX descriptors minus 3. (tx_free_thresh=%u "
2525                              "port=%d queue=%d)",
2526                              (unsigned int)tx_free_thresh,
2527                              (int)dev->data->port_id, (int)queue_idx);
2528                 return -(EINVAL);
2529         }
2530         if (tx_rs_thresh > tx_free_thresh) {
2531                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2532                              "tx_free_thresh. (tx_free_thresh=%u "
2533                              "tx_rs_thresh=%u port=%d queue=%d)",
2534                              (unsigned int)tx_free_thresh,
2535                              (unsigned int)tx_rs_thresh,
2536                              (int)dev->data->port_id,
2537                              (int)queue_idx);
2538                 return -(EINVAL);
2539         }
2540         if ((nb_desc % tx_rs_thresh) != 0) {
2541                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2542                              "number of TX descriptors. (tx_rs_thresh=%u "
2543                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2544                              (int)dev->data->port_id, (int)queue_idx);
2545                 return -(EINVAL);
2546         }
2547
2548         /*
2549          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2550          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2551          * by the NIC and all descriptors are written back after the NIC
2552          * accumulates WTHRESH descriptors.
2553          */
2554         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2555                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2556                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2557                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2558                              (int)dev->data->port_id, (int)queue_idx);
2559                 return -(EINVAL);
2560         }
2561
2562         /* Free memory prior to re-allocation if needed... */
2563         if (dev->data->tx_queues[queue_idx] != NULL) {
2564                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2565                 dev->data->tx_queues[queue_idx] = NULL;
2566         }
2567
2568         /* First allocate the tx queue data structure */
2569         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2570                                  RTE_CACHE_LINE_SIZE, socket_id);
2571         if (txq == NULL)
2572                 return -ENOMEM;
2573
2574         /*
2575          * Allocate TX ring hardware descriptors. A memzone large enough to
2576          * handle the maximum ring size is allocated in order to allow for
2577          * resizing in later calls to the queue setup function.
2578          */
2579         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2580                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2581                         IXGBE_ALIGN, socket_id);
2582         if (tz == NULL) {
2583                 ixgbe_tx_queue_release(txq);
2584                 return -ENOMEM;
2585         }
2586
2587         txq->nb_tx_desc = nb_desc;
2588         txq->tx_rs_thresh = tx_rs_thresh;
2589         txq->tx_free_thresh = tx_free_thresh;
2590         txq->pthresh = tx_conf->tx_thresh.pthresh;
2591         txq->hthresh = tx_conf->tx_thresh.hthresh;
2592         txq->wthresh = tx_conf->tx_thresh.wthresh;
2593         txq->queue_id = queue_idx;
2594         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2595                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2596         txq->port_id = dev->data->port_id;
2597         txq->offloads = offloads;
2598         txq->ops = &def_txq_ops;
2599         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2600 #ifdef RTE_LIBRTE_SECURITY
2601         txq->using_ipsec = !!(dev->data->dev_conf.txmode.offloads &
2602                         DEV_TX_OFFLOAD_SECURITY);
2603 #endif
2604
2605         /*
2606          * Modification to set VFTDT for virtual function if vf is detected
2607          */
2608         if (hw->mac.type == ixgbe_mac_82599_vf ||
2609             hw->mac.type == ixgbe_mac_X540_vf ||
2610             hw->mac.type == ixgbe_mac_X550_vf ||
2611             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2612             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2613                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2614         else
2615                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2616
2617         txq->tx_ring_phys_addr = tz->iova;
2618         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2619
2620         /* Allocate software ring */
2621         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2622                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2623                                 RTE_CACHE_LINE_SIZE, socket_id);
2624         if (txq->sw_ring == NULL) {
2625                 ixgbe_tx_queue_release(txq);
2626                 return -ENOMEM;
2627         }
2628         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2629                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2630
2631         /* set up vector or scalar TX function as appropriate */
2632         ixgbe_set_tx_function(dev, txq);
2633
2634         txq->ops->reset(txq);
2635
2636         dev->data->tx_queues[queue_idx] = txq;
2637
2638
2639         return 0;
2640 }
2641
2642 /**
2643  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2644  *
2645  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2646  * in the sw_rsc_ring is not set to NULL but rather points to the next
2647  * mbuf of this RSC aggregation (that has not been completed yet and still
2648  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2649  * will just free first "nb_segs" segments of the cluster explicitly by calling
2650  * an rte_pktmbuf_free_seg().
2651  *
2652  * @m scattered cluster head
2653  */
2654 static void __attribute__((cold))
2655 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2656 {
2657         uint16_t i, nb_segs = m->nb_segs;
2658         struct rte_mbuf *next_seg;
2659
2660         for (i = 0; i < nb_segs; i++) {
2661                 next_seg = m->next;
2662                 rte_pktmbuf_free_seg(m);
2663                 m = next_seg;
2664         }
2665 }
2666
2667 static void __attribute__((cold))
2668 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2669 {
2670         unsigned i;
2671
2672 #ifdef RTE_IXGBE_INC_VECTOR
2673         /* SSE Vector driver has a different way of releasing mbufs. */
2674         if (rxq->rx_using_sse) {
2675                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2676                 return;
2677         }
2678 #endif
2679
2680         if (rxq->sw_ring != NULL) {
2681                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2682                         if (rxq->sw_ring[i].mbuf != NULL) {
2683                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2684                                 rxq->sw_ring[i].mbuf = NULL;
2685                         }
2686                 }
2687                 if (rxq->rx_nb_avail) {
2688                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2689                                 struct rte_mbuf *mb;
2690
2691                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2692                                 rte_pktmbuf_free_seg(mb);
2693                         }
2694                         rxq->rx_nb_avail = 0;
2695                 }
2696         }
2697
2698         if (rxq->sw_sc_ring)
2699                 for (i = 0; i < rxq->nb_rx_desc; i++)
2700                         if (rxq->sw_sc_ring[i].fbuf) {
2701                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2702                                 rxq->sw_sc_ring[i].fbuf = NULL;
2703                         }
2704 }
2705
2706 static void __attribute__((cold))
2707 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2708 {
2709         if (rxq != NULL) {
2710                 ixgbe_rx_queue_release_mbufs(rxq);
2711                 rte_free(rxq->sw_ring);
2712                 rte_free(rxq->sw_sc_ring);
2713                 rte_free(rxq);
2714         }
2715 }
2716
2717 void __attribute__((cold))
2718 ixgbe_dev_rx_queue_release(void *rxq)
2719 {
2720         ixgbe_rx_queue_release(rxq);
2721 }
2722
2723 /*
2724  * Check if Rx Burst Bulk Alloc function can be used.
2725  * Return
2726  *        0: the preconditions are satisfied and the bulk allocation function
2727  *           can be used.
2728  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2729  *           function must be used.
2730  */
2731 static inline int __attribute__((cold))
2732 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2733 {
2734         int ret = 0;
2735
2736         /*
2737          * Make sure the following pre-conditions are satisfied:
2738          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2739          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2740          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2741          * Scattered packets are not supported.  This should be checked
2742          * outside of this function.
2743          */
2744         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2745                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2746                              "rxq->rx_free_thresh=%d, "
2747                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2748                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2749                 ret = -EINVAL;
2750         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2751                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2752                              "rxq->rx_free_thresh=%d, "
2753                              "rxq->nb_rx_desc=%d",
2754                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2755                 ret = -EINVAL;
2756         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2757                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2758                              "rxq->nb_rx_desc=%d, "
2759                              "rxq->rx_free_thresh=%d",
2760                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2761                 ret = -EINVAL;
2762         }
2763
2764         return ret;
2765 }
2766
2767 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2768 static void __attribute__((cold))
2769 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2770 {
2771         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2772         unsigned i;
2773         uint16_t len = rxq->nb_rx_desc;
2774
2775         /*
2776          * By default, the Rx queue setup function allocates enough memory for
2777          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2778          * extra memory at the end of the descriptor ring to be zero'd out.
2779          */
2780         if (adapter->rx_bulk_alloc_allowed)
2781                 /* zero out extra memory */
2782                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2783
2784         /*
2785          * Zero out HW ring memory. Zero out extra memory at the end of
2786          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2787          * reads extra memory as zeros.
2788          */
2789         for (i = 0; i < len; i++) {
2790                 rxq->rx_ring[i] = zeroed_desc;
2791         }
2792
2793         /*
2794          * initialize extra software ring entries. Space for these extra
2795          * entries is always allocated
2796          */
2797         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2798         for (i = rxq->nb_rx_desc; i < len; ++i) {
2799                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2800         }
2801
2802         rxq->rx_nb_avail = 0;
2803         rxq->rx_next_avail = 0;
2804         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2805         rxq->rx_tail = 0;
2806         rxq->nb_rx_hold = 0;
2807         rxq->pkt_first_seg = NULL;
2808         rxq->pkt_last_seg = NULL;
2809
2810 #ifdef RTE_IXGBE_INC_VECTOR
2811         rxq->rxrearm_start = 0;
2812         rxq->rxrearm_nb = 0;
2813 #endif
2814 }
2815
2816 static int
2817 ixgbe_is_vf(struct rte_eth_dev *dev)
2818 {
2819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820
2821         switch (hw->mac.type) {
2822         case ixgbe_mac_82599_vf:
2823         case ixgbe_mac_X540_vf:
2824         case ixgbe_mac_X550_vf:
2825         case ixgbe_mac_X550EM_x_vf:
2826         case ixgbe_mac_X550EM_a_vf:
2827                 return 1;
2828         default:
2829                 return 0;
2830         }
2831 }
2832
2833 uint64_t
2834 ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev)
2835 {
2836         uint64_t offloads = 0;
2837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838
2839         if (hw->mac.type != ixgbe_mac_82598EB)
2840                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2841
2842         return offloads;
2843 }
2844
2845 uint64_t
2846 ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
2847 {
2848         uint64_t offloads;
2849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850
2851         offloads = DEV_RX_OFFLOAD_IPV4_CKSUM  |
2852                    DEV_RX_OFFLOAD_UDP_CKSUM   |
2853                    DEV_RX_OFFLOAD_TCP_CKSUM   |
2854                    DEV_RX_OFFLOAD_KEEP_CRC    |
2855                    DEV_RX_OFFLOAD_JUMBO_FRAME |
2856                    DEV_RX_OFFLOAD_SCATTER;
2857
2858         if (hw->mac.type == ixgbe_mac_82598EB)
2859                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2860
2861         if (ixgbe_is_vf(dev) == 0)
2862                 offloads |= (DEV_RX_OFFLOAD_VLAN_FILTER |
2863                              DEV_RX_OFFLOAD_VLAN_EXTEND);
2864
2865         /*
2866          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2867          * mode.
2868          */
2869         if ((hw->mac.type == ixgbe_mac_82599EB ||
2870              hw->mac.type == ixgbe_mac_X540) &&
2871             !RTE_ETH_DEV_SRIOV(dev).active)
2872                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
2873
2874         if (hw->mac.type == ixgbe_mac_82599EB ||
2875             hw->mac.type == ixgbe_mac_X540)
2876                 offloads |= DEV_RX_OFFLOAD_MACSEC_STRIP;
2877
2878         if (hw->mac.type == ixgbe_mac_X550 ||
2879             hw->mac.type == ixgbe_mac_X550EM_x ||
2880             hw->mac.type == ixgbe_mac_X550EM_a)
2881                 offloads |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2882
2883 #ifdef RTE_LIBRTE_SECURITY
2884         if (dev->security_ctx)
2885                 offloads |= DEV_RX_OFFLOAD_SECURITY;
2886 #endif
2887
2888         return offloads;
2889 }
2890
2891 int __attribute__((cold))
2892 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2893                          uint16_t queue_idx,
2894                          uint16_t nb_desc,
2895                          unsigned int socket_id,
2896                          const struct rte_eth_rxconf *rx_conf,
2897                          struct rte_mempool *mp)
2898 {
2899         const struct rte_memzone *rz;
2900         struct ixgbe_rx_queue *rxq;
2901         struct ixgbe_hw     *hw;
2902         uint16_t len;
2903         struct ixgbe_adapter *adapter =
2904                 (struct ixgbe_adapter *)dev->data->dev_private;
2905         uint64_t offloads;
2906
2907         PMD_INIT_FUNC_TRACE();
2908         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2909
2910         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
2911
2912         /*
2913          * Validate number of receive descriptors.
2914          * It must not exceed hardware maximum, and must be multiple
2915          * of IXGBE_ALIGN.
2916          */
2917         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2918                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2919                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2920                 return -EINVAL;
2921         }
2922
2923         /* Free memory prior to re-allocation if needed... */
2924         if (dev->data->rx_queues[queue_idx] != NULL) {
2925                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2926                 dev->data->rx_queues[queue_idx] = NULL;
2927         }
2928
2929         /* First allocate the rx queue data structure */
2930         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2931                                  RTE_CACHE_LINE_SIZE, socket_id);
2932         if (rxq == NULL)
2933                 return -ENOMEM;
2934         rxq->mb_pool = mp;
2935         rxq->nb_rx_desc = nb_desc;
2936         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2937         rxq->queue_id = queue_idx;
2938         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2939                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2940         rxq->port_id = dev->data->port_id;
2941         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
2942                 rxq->crc_len = ETHER_CRC_LEN;
2943         else
2944                 rxq->crc_len = 0;
2945         rxq->drop_en = rx_conf->rx_drop_en;
2946         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2947         rxq->offloads = offloads;
2948
2949         /*
2950          * The packet type in RX descriptor is different for different NICs.
2951          * Some bits are used for x550 but reserved for other NICS.
2952          * So set different masks for different NICs.
2953          */
2954         if (hw->mac.type == ixgbe_mac_X550 ||
2955             hw->mac.type == ixgbe_mac_X550EM_x ||
2956             hw->mac.type == ixgbe_mac_X550EM_a ||
2957             hw->mac.type == ixgbe_mac_X550_vf ||
2958             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2959             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2960                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2961         else
2962                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2963
2964         /*
2965          * Allocate RX ring hardware descriptors. A memzone large enough to
2966          * handle the maximum ring size is allocated in order to allow for
2967          * resizing in later calls to the queue setup function.
2968          */
2969         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2970                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
2971         if (rz == NULL) {
2972                 ixgbe_rx_queue_release(rxq);
2973                 return -ENOMEM;
2974         }
2975
2976         /*
2977          * Zero init all the descriptors in the ring.
2978          */
2979         memset(rz->addr, 0, RX_RING_SZ);
2980
2981         /*
2982          * Modified to setup VFRDT for Virtual Function
2983          */
2984         if (hw->mac.type == ixgbe_mac_82599_vf ||
2985             hw->mac.type == ixgbe_mac_X540_vf ||
2986             hw->mac.type == ixgbe_mac_X550_vf ||
2987             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2988             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2989                 rxq->rdt_reg_addr =
2990                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2991                 rxq->rdh_reg_addr =
2992                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2993         } else {
2994                 rxq->rdt_reg_addr =
2995                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2996                 rxq->rdh_reg_addr =
2997                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2998         }
2999
3000         rxq->rx_ring_phys_addr = rz->iova;
3001         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
3002
3003         /*
3004          * Certain constraints must be met in order to use the bulk buffer
3005          * allocation Rx burst function. If any of Rx queues doesn't meet them
3006          * the feature should be disabled for the whole port.
3007          */
3008         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
3009                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
3010                                     "preconditions - canceling the feature for "
3011                                     "the whole port[%d]",
3012                              rxq->queue_id, rxq->port_id);
3013                 adapter->rx_bulk_alloc_allowed = false;
3014         }
3015
3016         /*
3017          * Allocate software ring. Allow for space at the end of the
3018          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
3019          * function does not access an invalid memory region.
3020          */
3021         len = nb_desc;
3022         if (adapter->rx_bulk_alloc_allowed)
3023                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
3024
3025         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
3026                                           sizeof(struct ixgbe_rx_entry) * len,
3027                                           RTE_CACHE_LINE_SIZE, socket_id);
3028         if (!rxq->sw_ring) {
3029                 ixgbe_rx_queue_release(rxq);
3030                 return -ENOMEM;
3031         }
3032
3033         /*
3034          * Always allocate even if it's not going to be needed in order to
3035          * simplify the code.
3036          *
3037          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
3038          * be requested in ixgbe_dev_rx_init(), which is called later from
3039          * dev_start() flow.
3040          */
3041         rxq->sw_sc_ring =
3042                 rte_zmalloc_socket("rxq->sw_sc_ring",
3043                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
3044                                    RTE_CACHE_LINE_SIZE, socket_id);
3045         if (!rxq->sw_sc_ring) {
3046                 ixgbe_rx_queue_release(rxq);
3047                 return -ENOMEM;
3048         }
3049
3050         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
3051                             "dma_addr=0x%"PRIx64,
3052                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
3053                      rxq->rx_ring_phys_addr);
3054
3055         if (!rte_is_power_of_2(nb_desc)) {
3056                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
3057                                     "preconditions - canceling the feature for "
3058                                     "the whole port[%d]",
3059                              rxq->queue_id, rxq->port_id);
3060                 adapter->rx_vec_allowed = false;
3061         } else
3062                 ixgbe_rxq_vec_setup(rxq);
3063
3064         dev->data->rx_queues[queue_idx] = rxq;
3065
3066         ixgbe_reset_rx_queue(adapter, rxq);
3067
3068         return 0;
3069 }
3070
3071 uint32_t
3072 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3073 {
3074 #define IXGBE_RXQ_SCAN_INTERVAL 4
3075         volatile union ixgbe_adv_rx_desc *rxdp;
3076         struct ixgbe_rx_queue *rxq;
3077         uint32_t desc = 0;
3078
3079         rxq = dev->data->rx_queues[rx_queue_id];
3080         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
3081
3082         while ((desc < rxq->nb_rx_desc) &&
3083                 (rxdp->wb.upper.status_error &
3084                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
3085                 desc += IXGBE_RXQ_SCAN_INTERVAL;
3086                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
3087                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
3088                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
3089                                 desc - rxq->nb_rx_desc]);
3090         }
3091
3092         return desc;
3093 }
3094
3095 int
3096 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
3097 {
3098         volatile union ixgbe_adv_rx_desc *rxdp;
3099         struct ixgbe_rx_queue *rxq = rx_queue;
3100         uint32_t desc;
3101
3102         if (unlikely(offset >= rxq->nb_rx_desc))
3103                 return 0;
3104         desc = rxq->rx_tail + offset;
3105         if (desc >= rxq->nb_rx_desc)
3106                 desc -= rxq->nb_rx_desc;
3107
3108         rxdp = &rxq->rx_ring[desc];
3109         return !!(rxdp->wb.upper.status_error &
3110                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
3111 }
3112
3113 int
3114 ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
3115 {
3116         struct ixgbe_rx_queue *rxq = rx_queue;
3117         volatile uint32_t *status;
3118         uint32_t nb_hold, desc;
3119
3120         if (unlikely(offset >= rxq->nb_rx_desc))
3121                 return -EINVAL;
3122
3123 #ifdef RTE_IXGBE_INC_VECTOR
3124         if (rxq->rx_using_sse)
3125                 nb_hold = rxq->rxrearm_nb;
3126         else
3127 #endif
3128                 nb_hold = rxq->nb_rx_hold;
3129         if (offset >= rxq->nb_rx_desc - nb_hold)
3130                 return RTE_ETH_RX_DESC_UNAVAIL;
3131
3132         desc = rxq->rx_tail + offset;
3133         if (desc >= rxq->nb_rx_desc)
3134                 desc -= rxq->nb_rx_desc;
3135
3136         status = &rxq->rx_ring[desc].wb.upper.status_error;
3137         if (*status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))
3138                 return RTE_ETH_RX_DESC_DONE;
3139
3140         return RTE_ETH_RX_DESC_AVAIL;
3141 }
3142
3143 int
3144 ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
3145 {
3146         struct ixgbe_tx_queue *txq = tx_queue;
3147         volatile uint32_t *status;
3148         uint32_t desc;
3149
3150         if (unlikely(offset >= txq->nb_tx_desc))
3151                 return -EINVAL;
3152
3153         desc = txq->tx_tail + offset;
3154         /* go to next desc that has the RS bit */
3155         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
3156                 txq->tx_rs_thresh;
3157         if (desc >= txq->nb_tx_desc) {
3158                 desc -= txq->nb_tx_desc;
3159                 if (desc >= txq->nb_tx_desc)
3160                         desc -= txq->nb_tx_desc;
3161         }
3162
3163         status = &txq->tx_ring[desc].wb.status;
3164         if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))
3165                 return RTE_ETH_TX_DESC_DONE;
3166
3167         return RTE_ETH_TX_DESC_FULL;
3168 }
3169
3170 void __attribute__((cold))
3171 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
3172 {
3173         unsigned i;
3174         struct ixgbe_adapter *adapter =
3175                 (struct ixgbe_adapter *)dev->data->dev_private;
3176
3177         PMD_INIT_FUNC_TRACE();
3178
3179         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3180                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
3181
3182                 if (txq != NULL) {
3183                         txq->ops->release_mbufs(txq);
3184                         txq->ops->reset(txq);
3185                 }
3186         }
3187
3188         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3189                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
3190
3191                 if (rxq != NULL) {
3192                         ixgbe_rx_queue_release_mbufs(rxq);
3193                         ixgbe_reset_rx_queue(adapter, rxq);
3194                 }
3195         }
3196 }
3197
3198 void
3199 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
3200 {
3201         unsigned i;
3202
3203         PMD_INIT_FUNC_TRACE();
3204
3205         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3206                 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
3207                 dev->data->rx_queues[i] = NULL;
3208         }
3209         dev->data->nb_rx_queues = 0;
3210
3211         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3212                 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
3213                 dev->data->tx_queues[i] = NULL;
3214         }
3215         dev->data->nb_tx_queues = 0;
3216 }
3217
3218 /*********************************************************************
3219  *
3220  *  Device RX/TX init functions
3221  *
3222  **********************************************************************/
3223
3224 /**
3225  * Receive Side Scaling (RSS)
3226  * See section 7.1.2.8 in the following document:
3227  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
3228  *
3229  * Principles:
3230  * The source and destination IP addresses of the IP header and the source
3231  * and destination ports of TCP/UDP headers, if any, of received packets are
3232  * hashed against a configurable random key to compute a 32-bit RSS hash result.
3233  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
3234  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
3235  * RSS output index which is used as the RX queue index where to store the
3236  * received packets.
3237  * The following output is supplied in the RX write-back descriptor:
3238  *     - 32-bit result of the Microsoft RSS hash function,
3239  *     - 4-bit RSS type field.
3240  */
3241
3242 /*
3243  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
3244  * Used as the default key.
3245  */
3246 static uint8_t rss_intel_key[40] = {
3247         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
3248         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
3249         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
3250         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
3251         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
3252 };
3253
3254 static void
3255 ixgbe_rss_disable(struct rte_eth_dev *dev)
3256 {
3257         struct ixgbe_hw *hw;
3258         uint32_t mrqc;
3259         uint32_t mrqc_reg;
3260
3261         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3262         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3263         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3264         mrqc &= ~IXGBE_MRQC_RSSEN;
3265         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3266 }
3267
3268 static void
3269 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
3270 {
3271         uint8_t  *hash_key;
3272         uint32_t mrqc;
3273         uint32_t rss_key;
3274         uint64_t rss_hf;
3275         uint16_t i;
3276         uint32_t mrqc_reg;
3277         uint32_t rssrk_reg;
3278
3279         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3280         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3281
3282         hash_key = rss_conf->rss_key;
3283         if (hash_key != NULL) {
3284                 /* Fill in RSS hash key */
3285                 for (i = 0; i < 10; i++) {
3286                         rss_key  = hash_key[(i * 4)];
3287                         rss_key |= hash_key[(i * 4) + 1] << 8;
3288                         rss_key |= hash_key[(i * 4) + 2] << 16;
3289                         rss_key |= hash_key[(i * 4) + 3] << 24;
3290                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
3291                 }
3292         }
3293
3294         /* Set configured hashing protocols in MRQC register */
3295         rss_hf = rss_conf->rss_hf;
3296         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
3297         if (rss_hf & ETH_RSS_IPV4)
3298                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
3299         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
3300                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
3301         if (rss_hf & ETH_RSS_IPV6)
3302                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
3303         if (rss_hf & ETH_RSS_IPV6_EX)
3304                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
3305         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
3306                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3307         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
3308                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
3309         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
3310                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3311         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
3312                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3313         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
3314                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
3315         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
3316 }
3317
3318 int
3319 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
3320                           struct rte_eth_rss_conf *rss_conf)
3321 {
3322         struct ixgbe_hw *hw;
3323         uint32_t mrqc;
3324         uint64_t rss_hf;
3325         uint32_t mrqc_reg;
3326
3327         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328
3329         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3330                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
3331                         "NIC.");
3332                 return -ENOTSUP;
3333         }
3334         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3335
3336         /*
3337          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
3338          *     "RSS enabling cannot be done dynamically while it must be
3339          *      preceded by a software reset"
3340          * Before changing anything, first check that the update RSS operation
3341          * does not attempt to disable RSS, if RSS was enabled at
3342          * initialization time, or does not attempt to enable RSS, if RSS was
3343          * disabled at initialization time.
3344          */
3345         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
3346         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3347         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
3348                 if (rss_hf != 0) /* Enable RSS */
3349                         return -(EINVAL);
3350                 return 0; /* Nothing to do */
3351         }
3352         /* RSS enabled */
3353         if (rss_hf == 0) /* Disable RSS */
3354                 return -(EINVAL);
3355         ixgbe_hw_rss_hash_set(hw, rss_conf);
3356         return 0;
3357 }
3358
3359 int
3360 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3361                             struct rte_eth_rss_conf *rss_conf)
3362 {
3363         struct ixgbe_hw *hw;
3364         uint8_t *hash_key;
3365         uint32_t mrqc;
3366         uint32_t rss_key;
3367         uint64_t rss_hf;
3368         uint16_t i;
3369         uint32_t mrqc_reg;
3370         uint32_t rssrk_reg;
3371
3372         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3373         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3374         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3375         hash_key = rss_conf->rss_key;
3376         if (hash_key != NULL) {
3377                 /* Return RSS hash key */
3378                 for (i = 0; i < 10; i++) {
3379                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3380                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3381                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3382                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3383                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3384                 }
3385         }
3386
3387         /* Get RSS functions configured in MRQC register */
3388         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3389         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3390                 rss_conf->rss_hf = 0;
3391                 return 0;
3392         }
3393         rss_hf = 0;
3394         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3395                 rss_hf |= ETH_RSS_IPV4;
3396         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3397                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3398         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3399                 rss_hf |= ETH_RSS_IPV6;
3400         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3401                 rss_hf |= ETH_RSS_IPV6_EX;
3402         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3403                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3404         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3405                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3406         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3407                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3408         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3409                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3410         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3411                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3412         rss_conf->rss_hf = rss_hf;
3413         return 0;
3414 }
3415
3416 static void
3417 ixgbe_rss_configure(struct rte_eth_dev *dev)
3418 {
3419         struct rte_eth_rss_conf rss_conf;
3420         struct ixgbe_hw *hw;
3421         uint32_t reta;
3422         uint16_t i;
3423         uint16_t j;
3424         uint16_t sp_reta_size;
3425         uint32_t reta_reg;
3426
3427         PMD_INIT_FUNC_TRACE();
3428         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3429
3430         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3431
3432         /*
3433          * Fill in redirection table
3434          * The byte-swap is needed because NIC registers are in
3435          * little-endian order.
3436          */
3437         reta = 0;
3438         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3439                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3440
3441                 if (j == dev->data->nb_rx_queues)
3442                         j = 0;
3443                 reta = (reta << 8) | j;
3444                 if ((i & 3) == 3)
3445                         IXGBE_WRITE_REG(hw, reta_reg,
3446                                         rte_bswap32(reta));
3447         }
3448
3449         /*
3450          * Configure the RSS key and the RSS protocols used to compute
3451          * the RSS hash of input packets.
3452          */
3453         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3454         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3455                 ixgbe_rss_disable(dev);
3456                 return;
3457         }
3458         if (rss_conf.rss_key == NULL)
3459                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3460         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3461 }
3462
3463 #define NUM_VFTA_REGISTERS 128
3464 #define NIC_RX_BUFFER_SIZE 0x200
3465 #define X550_RX_BUFFER_SIZE 0x180
3466
3467 static void
3468 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3469 {
3470         struct rte_eth_vmdq_dcb_conf *cfg;
3471         struct ixgbe_hw *hw;
3472         enum rte_eth_nb_pools num_pools;
3473         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3474         uint16_t pbsize;
3475         uint8_t nb_tcs; /* number of traffic classes */
3476         int i;
3477
3478         PMD_INIT_FUNC_TRACE();
3479         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3481         num_pools = cfg->nb_queue_pools;
3482         /* Check we have a valid number of pools */
3483         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3484                 ixgbe_rss_disable(dev);
3485                 return;
3486         }
3487         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3488         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3489
3490         /*
3491          * RXPBSIZE
3492          * split rx buffer up into sections, each for 1 traffic class
3493          */
3494         switch (hw->mac.type) {
3495         case ixgbe_mac_X550:
3496         case ixgbe_mac_X550EM_x:
3497         case ixgbe_mac_X550EM_a:
3498                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3499                 break;
3500         default:
3501                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3502                 break;
3503         }
3504         for (i = 0; i < nb_tcs; i++) {
3505                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3506
3507                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3508                 /* clear 10 bits. */
3509                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3510                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3511         }
3512         /* zero alloc all unused TCs */
3513         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3514                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3515
3516                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3517                 /* clear 10 bits. */
3518                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3519         }
3520
3521         /* MRQC: enable vmdq and dcb */
3522         mrqc = (num_pools == ETH_16_POOLS) ?
3523                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3524         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3525
3526         /* PFVTCTL: turn on virtualisation and set the default pool */
3527         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3528         if (cfg->enable_default_pool) {
3529                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3530         } else {
3531                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3532         }
3533
3534         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3535
3536         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3537         queue_mapping = 0;
3538         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3539                 /*
3540                  * mapping is done with 3 bits per priority,
3541                  * so shift by i*3 each time
3542                  */
3543                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3544
3545         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3546
3547         /* RTRPCS: DCB related */
3548         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3549
3550         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3551         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3552         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3553         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3554
3555         /* VFTA - enable all vlan filters */
3556         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3557                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3558         }
3559
3560         /* VFRE: pool enabling for receive - 16 or 32 */
3561         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3562                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3563
3564         /*
3565          * MPSAR - allow pools to read specific mac addresses
3566          * In this case, all pools should be able to read from mac addr 0
3567          */
3568         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3569         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3570
3571         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3572         for (i = 0; i < cfg->nb_pool_maps; i++) {
3573                 /* set vlan id in VF register and set the valid bit */
3574                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3575                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3576                 /*
3577                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3578                  * pools, we only need to use the first half of the register
3579                  * i.e. bits 0-31
3580                  */
3581                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3582         }
3583 }
3584
3585 /**
3586  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3587  * @dev: pointer to eth_dev structure
3588  * @dcb_config: pointer to ixgbe_dcb_config structure
3589  */
3590 static void
3591 ixgbe_dcb_tx_hw_config(struct rte_eth_dev *dev,
3592                        struct ixgbe_dcb_config *dcb_config)
3593 {
3594         uint32_t reg;
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596
3597         PMD_INIT_FUNC_TRACE();
3598         if (hw->mac.type != ixgbe_mac_82598EB) {
3599                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3600                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3601                 reg |= IXGBE_RTTDCS_ARBDIS;
3602                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3603
3604                 /* Enable DCB for Tx with 8 TCs */
3605                 if (dcb_config->num_tcs.pg_tcs == 8) {
3606                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3607                 } else {
3608                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3609                 }
3610                 if (dcb_config->vt_mode)
3611                         reg |= IXGBE_MTQC_VT_ENA;
3612                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3613
3614                 /* Enable the Tx desc arbiter */
3615                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3616                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3617                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3618
3619                 /* Enable Security TX Buffer IFG for DCB */
3620                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3621                 reg |= IXGBE_SECTX_DCB;
3622                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3623         }
3624 }
3625
3626 /**
3627  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3628  * @dev: pointer to rte_eth_dev structure
3629  * @dcb_config: pointer to ixgbe_dcb_config structure
3630  */
3631 static void
3632 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3633                         struct ixgbe_dcb_config *dcb_config)
3634 {
3635         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3636                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3637         struct ixgbe_hw *hw =
3638                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639
3640         PMD_INIT_FUNC_TRACE();
3641         if (hw->mac.type != ixgbe_mac_82598EB)
3642                 /*PF VF Transmit Enable*/
3643                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3644                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3645
3646         /*Configure general DCB TX parameters*/
3647         ixgbe_dcb_tx_hw_config(dev, dcb_config);
3648 }
3649
3650 static void
3651 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3652                         struct ixgbe_dcb_config *dcb_config)
3653 {
3654         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3655                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3656         struct ixgbe_dcb_tc_config *tc;
3657         uint8_t i, j;
3658
3659         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3660         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3661                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3662                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3663         } else {
3664                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3665                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3666         }
3667
3668         /* Initialize User Priority to Traffic Class mapping */
3669         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3670                 tc = &dcb_config->tc_config[j];
3671                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3672         }
3673
3674         /* User Priority to Traffic Class mapping */
3675         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3676                 j = vmdq_rx_conf->dcb_tc[i];
3677                 tc = &dcb_config->tc_config[j];
3678                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3679                                                 (uint8_t)(1 << i);
3680         }
3681 }
3682
3683 static void
3684 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3685                         struct ixgbe_dcb_config *dcb_config)
3686 {
3687         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3688                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3689         struct ixgbe_dcb_tc_config *tc;
3690         uint8_t i, j;
3691
3692         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3693         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3694                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3695                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3696         } else {
3697                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3698                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3699         }
3700
3701         /* Initialize User Priority to Traffic Class mapping */
3702         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3703                 tc = &dcb_config->tc_config[j];
3704                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3705         }
3706
3707         /* User Priority to Traffic Class mapping */
3708         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3709                 j = vmdq_tx_conf->dcb_tc[i];
3710                 tc = &dcb_config->tc_config[j];
3711                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3712                                                 (uint8_t)(1 << i);
3713         }
3714 }
3715
3716 static void
3717 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3718                 struct ixgbe_dcb_config *dcb_config)
3719 {
3720         struct rte_eth_dcb_rx_conf *rx_conf =
3721                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3722         struct ixgbe_dcb_tc_config *tc;
3723         uint8_t i, j;
3724
3725         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3726         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3727
3728         /* Initialize User Priority to Traffic Class mapping */
3729         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3730                 tc = &dcb_config->tc_config[j];
3731                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0;
3732         }
3733
3734         /* User Priority to Traffic Class mapping */
3735         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3736                 j = rx_conf->dcb_tc[i];
3737                 tc = &dcb_config->tc_config[j];
3738                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap |=
3739                                                 (uint8_t)(1 << i);
3740         }
3741 }
3742
3743 static void
3744 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3745                 struct ixgbe_dcb_config *dcb_config)
3746 {
3747         struct rte_eth_dcb_tx_conf *tx_conf =
3748                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3749         struct ixgbe_dcb_tc_config *tc;
3750         uint8_t i, j;
3751
3752         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3753         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3754
3755         /* Initialize User Priority to Traffic Class mapping */
3756         for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
3757                 tc = &dcb_config->tc_config[j];
3758                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0;
3759         }
3760
3761         /* User Priority to Traffic Class mapping */
3762         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3763                 j = tx_conf->dcb_tc[i];
3764                 tc = &dcb_config->tc_config[j];
3765                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap |=
3766                                                 (uint8_t)(1 << i);
3767         }
3768 }
3769
3770 /**
3771  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3772  * @dev: pointer to eth_dev structure
3773  * @dcb_config: pointer to ixgbe_dcb_config structure
3774  */
3775 static void
3776 ixgbe_dcb_rx_hw_config(struct rte_eth_dev *dev,
3777                        struct ixgbe_dcb_config *dcb_config)
3778 {
3779         uint32_t reg;
3780         uint32_t vlanctrl;
3781         uint8_t i;
3782         uint32_t q;
3783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784
3785         PMD_INIT_FUNC_TRACE();
3786         /*
3787          * Disable the arbiter before changing parameters
3788          * (always enable recycle mode; WSP)
3789          */
3790         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3791         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3792
3793         if (hw->mac.type != ixgbe_mac_82598EB) {
3794                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3795                 if (dcb_config->num_tcs.pg_tcs == 4) {
3796                         if (dcb_config->vt_mode)
3797                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3798                                         IXGBE_MRQC_VMDQRT4TCEN;
3799                         else {
3800                                 /* no matter the mode is DCB or DCB_RSS, just
3801                                  * set the MRQE to RSSXTCEN. RSS is controlled
3802                                  * by RSS_FIELD
3803                                  */
3804                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3805                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3806                                         IXGBE_MRQC_RTRSS4TCEN;
3807                         }
3808                 }
3809                 if (dcb_config->num_tcs.pg_tcs == 8) {
3810                         if (dcb_config->vt_mode)
3811                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3812                                         IXGBE_MRQC_VMDQRT8TCEN;
3813                         else {
3814                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3815                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3816                                         IXGBE_MRQC_RTRSS8TCEN;
3817                         }
3818                 }
3819
3820                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3821
3822                 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3823                         /* Disable drop for all queues in VMDQ mode*/
3824                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3825                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3826                                                 (IXGBE_QDE_WRITE |
3827                                                  (q << IXGBE_QDE_IDX_SHIFT)));
3828                 } else {
3829                         /* Enable drop for all queues in SRIOV mode */
3830                         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3831                                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3832                                                 (IXGBE_QDE_WRITE |
3833                                                  (q << IXGBE_QDE_IDX_SHIFT) |
3834                                                  IXGBE_QDE_ENABLE));
3835                 }
3836         }
3837
3838         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3839         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3840         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3841         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3842
3843         /* VFTA - enable all vlan filters */
3844         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3845                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3846         }
3847
3848         /*
3849          * Configure Rx packet plane (recycle mode; WSP) and
3850          * enable arbiter
3851          */
3852         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3853         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3854 }
3855
3856 static void
3857 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3858                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3859 {
3860         switch (hw->mac.type) {
3861         case ixgbe_mac_82598EB:
3862                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3863                 break;
3864         case ixgbe_mac_82599EB:
3865         case ixgbe_mac_X540:
3866         case ixgbe_mac_X550:
3867         case ixgbe_mac_X550EM_x:
3868         case ixgbe_mac_X550EM_a:
3869                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3870                                                   tsa, map);
3871                 break;
3872         default:
3873                 break;
3874         }
3875 }
3876
3877 static void
3878 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3879                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3880 {
3881         switch (hw->mac.type) {
3882         case ixgbe_mac_82598EB:
3883                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3884                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3885                 break;
3886         case ixgbe_mac_82599EB:
3887         case ixgbe_mac_X540:
3888         case ixgbe_mac_X550:
3889         case ixgbe_mac_X550EM_x:
3890         case ixgbe_mac_X550EM_a:
3891                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3892                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3893                 break;
3894         default:
3895                 break;
3896         }
3897 }
3898
3899 #define DCB_RX_CONFIG  1
3900 #define DCB_TX_CONFIG  1
3901 #define DCB_TX_PB      1024
3902 /**
3903  * ixgbe_dcb_hw_configure - Enable DCB and configure
3904  * general DCB in VT mode and non-VT mode parameters
3905  * @dev: pointer to rte_eth_dev structure
3906  * @dcb_config: pointer to ixgbe_dcb_config structure
3907  */
3908 static int
3909 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3910                         struct ixgbe_dcb_config *dcb_config)
3911 {
3912         int     ret = 0;
3913         uint8_t i, pfc_en, nb_tcs;
3914         uint16_t pbsize, rx_buffer_size;
3915         uint8_t config_dcb_rx = 0;
3916         uint8_t config_dcb_tx = 0;
3917         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3918         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3919         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3920         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3921         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3922         struct ixgbe_dcb_tc_config *tc;
3923         uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3924         struct ixgbe_hw *hw =
3925                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926         struct ixgbe_bw_conf *bw_conf =
3927                 IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
3928
3929         switch (dev->data->dev_conf.rxmode.mq_mode) {
3930         case ETH_MQ_RX_VMDQ_DCB:
3931                 dcb_config->vt_mode = true;
3932                 if (hw->mac.type != ixgbe_mac_82598EB) {
3933                         config_dcb_rx = DCB_RX_CONFIG;
3934                         /*
3935                          *get dcb and VT rx configuration parameters
3936                          *from rte_eth_conf
3937                          */
3938                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3939                         /*Configure general VMDQ and DCB RX parameters*/
3940                         ixgbe_vmdq_dcb_configure(dev);
3941                 }
3942                 break;
3943         case ETH_MQ_RX_DCB:
3944         case ETH_MQ_RX_DCB_RSS:
3945                 dcb_config->vt_mode = false;
3946                 config_dcb_rx = DCB_RX_CONFIG;
3947                 /* Get dcb TX configuration parameters from rte_eth_conf */
3948                 ixgbe_dcb_rx_config(dev, dcb_config);
3949                 /*Configure general DCB RX parameters*/
3950                 ixgbe_dcb_rx_hw_config(dev, dcb_config);
3951                 break;
3952         default:
3953                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3954                 break;
3955         }
3956         switch (dev->data->dev_conf.txmode.mq_mode) {
3957         case ETH_MQ_TX_VMDQ_DCB:
3958                 dcb_config->vt_mode = true;
3959                 config_dcb_tx = DCB_TX_CONFIG;
3960                 /* get DCB and VT TX configuration parameters
3961                  * from rte_eth_conf
3962                  */
3963                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3964                 /*Configure general VMDQ and DCB TX parameters*/
3965                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3966                 break;
3967
3968         case ETH_MQ_TX_DCB:
3969                 dcb_config->vt_mode = false;
3970                 config_dcb_tx = DCB_TX_CONFIG;
3971                 /*get DCB TX configuration parameters from rte_eth_conf*/
3972                 ixgbe_dcb_tx_config(dev, dcb_config);
3973                 /*Configure general DCB TX parameters*/
3974                 ixgbe_dcb_tx_hw_config(dev, dcb_config);
3975                 break;
3976         default:
3977                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3978                 break;
3979         }
3980
3981         nb_tcs = dcb_config->num_tcs.pfc_tcs;
3982         /* Unpack map */
3983         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3984         if (nb_tcs == ETH_4_TCS) {
3985                 /* Avoid un-configured priority mapping to TC0 */
3986                 uint8_t j = 4;
3987                 uint8_t mask = 0xFF;
3988
3989                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3990                         mask = (uint8_t)(mask & (~(1 << map[i])));
3991                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3992                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3993                                 map[j++] = i;
3994                         mask >>= 1;
3995                 }
3996                 /* Re-configure 4 TCs BW */
3997                 for (i = 0; i < nb_tcs; i++) {
3998                         tc = &dcb_config->tc_config[i];
3999                         if (bw_conf->tc_num != nb_tcs)
4000                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4001                                         (uint8_t)(100 / nb_tcs);
4002                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4003                                                 (uint8_t)(100 / nb_tcs);
4004                 }
4005                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4006                         tc = &dcb_config->tc_config[i];
4007                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
4008                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
4009                 }
4010         } else {
4011                 /* Re-configure 8 TCs BW */
4012                 for (i = 0; i < nb_tcs; i++) {
4013                         tc = &dcb_config->tc_config[i];
4014                         if (bw_conf->tc_num != nb_tcs)
4015                                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
4016                                         (uint8_t)(100 / nb_tcs + (i & 1));
4017                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
4018                                 (uint8_t)(100 / nb_tcs + (i & 1));
4019                 }
4020         }
4021
4022         switch (hw->mac.type) {
4023         case ixgbe_mac_X550:
4024         case ixgbe_mac_X550EM_x:
4025         case ixgbe_mac_X550EM_a:
4026                 rx_buffer_size = X550_RX_BUFFER_SIZE;
4027                 break;
4028         default:
4029                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
4030                 break;
4031         }
4032
4033         if (config_dcb_rx) {
4034                 /* Set RX buffer size */
4035                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4036                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
4037
4038                 for (i = 0; i < nb_tcs; i++) {
4039                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
4040                 }
4041                 /* zero alloc all unused TCs */
4042                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4043                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4044                 }
4045         }
4046         if (config_dcb_tx) {
4047                 /* Only support an equally distributed
4048                  *  Tx packet buffer strategy.
4049                  */
4050                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
4051                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
4052
4053                 for (i = 0; i < nb_tcs; i++) {
4054                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4055                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4056                 }
4057                 /* Clear unused TCs, if any, to zero buffer size*/
4058                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
4059                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4060                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4061                 }
4062         }
4063
4064         /*Calculates traffic class credits*/
4065         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4066                                 IXGBE_DCB_TX_CONFIG);
4067         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
4068                                 IXGBE_DCB_RX_CONFIG);
4069
4070         if (config_dcb_rx) {
4071                 /* Unpack CEE standard containers */
4072                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
4073                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4074                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
4075                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
4076                 /* Configure PG(ETS) RX */
4077                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
4078         }
4079
4080         if (config_dcb_tx) {
4081                 /* Unpack CEE standard containers */
4082                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
4083                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
4084                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
4085                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
4086                 /* Configure PG(ETS) TX */
4087                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
4088         }
4089
4090         /*Configure queue statistics registers*/
4091         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
4092
4093         /* Check if the PFC is supported */
4094         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
4095                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
4096                 for (i = 0; i < nb_tcs; i++) {
4097                         /*
4098                         * If the TC count is 8,and the default high_water is 48,
4099                         * the low_water is 16 as default.
4100                         */
4101                         hw->fc.high_water[i] = (pbsize * 3) / 4;
4102                         hw->fc.low_water[i] = pbsize / 4;
4103                         /* Enable pfc for this TC */
4104                         tc = &dcb_config->tc_config[i];
4105                         tc->pfc = ixgbe_dcb_pfc_enabled;
4106                 }
4107                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
4108                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
4109                         pfc_en &= 0x0F;
4110                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
4111         }
4112
4113         return ret;
4114 }
4115
4116 /**
4117  * ixgbe_configure_dcb - Configure DCB  Hardware
4118  * @dev: pointer to rte_eth_dev
4119  */
4120 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
4121 {
4122         struct ixgbe_dcb_config *dcb_cfg =
4123                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4124         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
4125
4126         PMD_INIT_FUNC_TRACE();
4127
4128         /* check support mq_mode for DCB */
4129         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
4130             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
4131             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
4132                 return;
4133
4134         if (dev->data->nb_rx_queues > ETH_DCB_NUM_QUEUES)
4135                 return;
4136
4137         /** Configure DCB hardware **/
4138         ixgbe_dcb_hw_configure(dev, dcb_cfg);
4139 }
4140
4141 /*
4142  * VMDq only support for 10 GbE NIC.
4143  */
4144 static void
4145 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
4146 {
4147         struct rte_eth_vmdq_rx_conf *cfg;
4148         struct ixgbe_hw *hw;
4149         enum rte_eth_nb_pools num_pools;
4150         uint32_t mrqc, vt_ctl, vlanctrl;
4151         uint32_t vmolr = 0;
4152         int i;
4153
4154         PMD_INIT_FUNC_TRACE();
4155         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4156         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
4157         num_pools = cfg->nb_queue_pools;
4158
4159         ixgbe_rss_disable(dev);
4160
4161         /* MRQC: enable vmdq */
4162         mrqc = IXGBE_MRQC_VMDQEN;
4163         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4164
4165         /* PFVTCTL: turn on virtualisation and set the default pool */
4166         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
4167         if (cfg->enable_default_pool)
4168                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
4169         else
4170                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
4171
4172         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
4173
4174         for (i = 0; i < (int)num_pools; i++) {
4175                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
4176                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
4177         }
4178
4179         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
4180         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4181         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
4182         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
4183
4184         /* VFTA - enable all vlan filters */
4185         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
4186                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
4187
4188         /* VFRE: pool enabling for receive - 64 */
4189         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
4190         if (num_pools == ETH_64_POOLS)
4191                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
4192
4193         /*
4194          * MPSAR - allow pools to read specific mac addresses
4195          * In this case, all pools should be able to read from mac addr 0
4196          */
4197         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
4198         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
4199
4200         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
4201         for (i = 0; i < cfg->nb_pool_maps; i++) {
4202                 /* set vlan id in VF register and set the valid bit */
4203                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
4204                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
4205                 /*
4206                  * Put the allowed pools in VFB reg. As we only have 16 or 64
4207                  * pools, we only need to use the first half of the register
4208                  * i.e. bits 0-31
4209                  */
4210                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
4211                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
4212                                         (cfg->pool_map[i].pools & UINT32_MAX));
4213                 else
4214                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
4215                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
4216
4217         }
4218
4219         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
4220         if (cfg->enable_loop_back) {
4221                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4222                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
4223                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
4224         }
4225
4226         IXGBE_WRITE_FLUSH(hw);
4227 }
4228
4229 /*
4230  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
4231  * @hw: pointer to hardware structure
4232  */
4233 static void
4234 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
4235 {
4236         uint32_t reg;
4237         uint32_t q;
4238
4239         PMD_INIT_FUNC_TRACE();
4240         /*PF VF Transmit Enable*/
4241         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
4242         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
4243
4244         /* Disable the Tx desc arbiter so that MTQC can be changed */
4245         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4246         reg |= IXGBE_RTTDCS_ARBDIS;
4247         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4248
4249         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4250         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
4251
4252         /* Disable drop for all queues */
4253         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
4254                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
4255                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
4256
4257         /* Enable the Tx desc arbiter */
4258         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4259         reg &= ~IXGBE_RTTDCS_ARBDIS;
4260         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
4261
4262         IXGBE_WRITE_FLUSH(hw);
4263 }
4264
4265 static int __attribute__((cold))
4266 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
4267 {
4268         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
4269         uint64_t dma_addr;
4270         unsigned int i;
4271
4272         /* Initialize software ring entries */
4273         for (i = 0; i < rxq->nb_rx_desc; i++) {
4274                 volatile union ixgbe_adv_rx_desc *rxd;
4275                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
4276
4277                 if (mbuf == NULL) {
4278                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
4279                                      (unsigned) rxq->queue_id);
4280                         return -ENOMEM;
4281                 }
4282
4283                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
4284                 mbuf->port = rxq->port_id;
4285
4286                 dma_addr =
4287                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
4288                 rxd = &rxq->rx_ring[i];
4289                 rxd->read.hdr_addr = 0;
4290                 rxd->read.pkt_addr = dma_addr;
4291                 rxe[i].mbuf = mbuf;
4292         }
4293
4294         return 0;
4295 }
4296
4297 static int
4298 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
4299 {
4300         struct ixgbe_hw *hw;
4301         uint32_t mrqc;
4302
4303         ixgbe_rss_configure(dev);
4304
4305         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4306
4307         /* MRQC: enable VF RSS */
4308         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
4309         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
4310         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4311         case ETH_64_POOLS:
4312                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
4313                 break;
4314
4315         case ETH_32_POOLS:
4316                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
4317                 break;
4318
4319         default:
4320                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
4321                 return -EINVAL;
4322         }
4323
4324         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4325
4326         return 0;
4327 }
4328
4329 static int
4330 ixgbe_config_vf_default(struct rte_eth_dev *dev)
4331 {
4332         struct ixgbe_hw *hw =
4333                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334
4335         switch (RTE_ETH_DEV_SRIOV(dev).active) {
4336         case ETH_64_POOLS:
4337                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4338                         IXGBE_MRQC_VMDQEN);
4339                 break;
4340
4341         case ETH_32_POOLS:
4342                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4343                         IXGBE_MRQC_VMDQRT4TCEN);
4344                 break;
4345
4346         case ETH_16_POOLS:
4347                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
4348                         IXGBE_MRQC_VMDQRT8TCEN);
4349                 break;
4350         default:
4351                 PMD_INIT_LOG(ERR,
4352                         "invalid pool number in IOV mode");
4353                 break;
4354         }
4355         return 0;
4356 }
4357
4358 static int
4359 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
4360 {
4361         struct ixgbe_hw *hw =
4362                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363
4364         if (hw->mac.type == ixgbe_mac_82598EB)
4365                 return 0;
4366
4367         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4368                 /*
4369                  * SRIOV inactive scheme
4370                  * any DCB/RSS w/o VMDq multi-queue setting
4371                  */
4372                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4373                 case ETH_MQ_RX_RSS:
4374                 case ETH_MQ_RX_DCB_RSS:
4375                 case ETH_MQ_RX_VMDQ_RSS:
4376                         ixgbe_rss_configure(dev);
4377                         break;
4378
4379                 case ETH_MQ_RX_VMDQ_DCB:
4380                         ixgbe_vmdq_dcb_configure(dev);
4381                         break;
4382
4383                 case ETH_MQ_RX_VMDQ_ONLY:
4384                         ixgbe_vmdq_rx_hw_configure(dev);
4385                         break;
4386
4387                 case ETH_MQ_RX_NONE:
4388                 default:
4389                         /* if mq_mode is none, disable rss mode.*/
4390                         ixgbe_rss_disable(dev);
4391                         break;
4392                 }
4393         } else {
4394                 /* SRIOV active scheme
4395                  * Support RSS together with SRIOV.
4396                  */
4397                 switch (dev->data->dev_conf.rxmode.mq_mode) {
4398                 case ETH_MQ_RX_RSS:
4399                 case ETH_MQ_RX_VMDQ_RSS:
4400                         ixgbe_config_vf_rss(dev);
4401                         break;
4402                 case ETH_MQ_RX_VMDQ_DCB:
4403                 case ETH_MQ_RX_DCB:
4404                 /* In SRIOV, the configuration is the same as VMDq case */
4405                         ixgbe_vmdq_dcb_configure(dev);
4406                         break;
4407                 /* DCB/RSS together with SRIOV is not supported */
4408                 case ETH_MQ_RX_VMDQ_DCB_RSS:
4409                 case ETH_MQ_RX_DCB_RSS:
4410                         PMD_INIT_LOG(ERR,
4411                                 "Could not support DCB/RSS with VMDq & SRIOV");
4412                         return -1;
4413                 default:
4414                         ixgbe_config_vf_default(dev);
4415                         break;
4416                 }
4417         }
4418
4419         return 0;
4420 }
4421
4422 static int
4423 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4424 {
4425         struct ixgbe_hw *hw =
4426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427         uint32_t mtqc;
4428         uint32_t rttdcs;
4429
4430         if (hw->mac.type == ixgbe_mac_82598EB)
4431                 return 0;
4432
4433         /* disable arbiter before setting MTQC */
4434         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4435         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4436         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4437
4438         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4439                 /*
4440                  * SRIOV inactive scheme
4441                  * any DCB w/o VMDq multi-queue setting
4442                  */
4443                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4444                         ixgbe_vmdq_tx_hw_configure(hw);
4445                 else {
4446                         mtqc = IXGBE_MTQC_64Q_1PB;
4447                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4448                 }
4449         } else {
4450                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4451
4452                 /*
4453                  * SRIOV active scheme
4454                  * FIXME if support DCB together with VMDq & SRIOV
4455                  */
4456                 case ETH_64_POOLS:
4457                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4458                         break;
4459                 case ETH_32_POOLS:
4460                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4461                         break;
4462                 case ETH_16_POOLS:
4463                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4464                                 IXGBE_MTQC_8TC_8TQ;
4465                         break;
4466                 default:
4467                         mtqc = IXGBE_MTQC_64Q_1PB;
4468                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4469                 }
4470                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4471         }
4472
4473         /* re-enable arbiter */
4474         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4475         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4476
4477         return 0;
4478 }
4479
4480 /**
4481  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4482  *
4483  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4484  * spec rev. 3.0 chapter 8.2.3.8.13.
4485  *
4486  * @pool Memory pool of the Rx queue
4487  */
4488 static inline uint32_t
4489 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4490 {
4491         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4492
4493         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4494         uint16_t maxdesc =
4495                 IPV4_MAX_PKT_LEN /
4496                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4497
4498         if (maxdesc >= 16)
4499                 return IXGBE_RSCCTL_MAXDESC_16;
4500         else if (maxdesc >= 8)
4501                 return IXGBE_RSCCTL_MAXDESC_8;
4502         else if (maxdesc >= 4)
4503                 return IXGBE_RSCCTL_MAXDESC_4;
4504         else
4505                 return IXGBE_RSCCTL_MAXDESC_1;
4506 }
4507
4508 /**
4509  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4510  * interrupt
4511  *
4512  * (Taken from FreeBSD tree)
4513  * (yes this is all very magic and confusing :)
4514  *
4515  * @dev port handle
4516  * @entry the register array entry
4517  * @vector the MSIX vector for this queue
4518  * @type RX/TX/MISC
4519  */
4520 static void
4521 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4522 {
4523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         u32 ivar, index;
4525
4526         vector |= IXGBE_IVAR_ALLOC_VAL;
4527
4528         switch (hw->mac.type) {
4529
4530         case ixgbe_mac_82598EB:
4531                 if (type == -1)
4532                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4533                 else
4534                         entry += (type * 64);
4535                 index = (entry >> 2) & 0x1F;
4536                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4537                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4538                 ivar |= (vector << (8 * (entry & 0x3)));
4539                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4540                 break;
4541
4542         case ixgbe_mac_82599EB:
4543         case ixgbe_mac_X540:
4544                 if (type == -1) { /* MISC IVAR */
4545                         index = (entry & 1) * 8;
4546                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4547                         ivar &= ~(0xFF << index);
4548                         ivar |= (vector << index);
4549                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4550                 } else {        /* RX/TX IVARS */
4551                         index = (16 * (entry & 1)) + (8 * type);
4552                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4553                         ivar &= ~(0xFF << index);
4554                         ivar |= (vector << index);
4555                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4556                 }
4557
4558                 break;
4559
4560         default:
4561                 break;
4562         }
4563 }
4564
4565 void __attribute__((cold))
4566 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4567 {
4568         uint16_t i, rx_using_sse;
4569         struct ixgbe_adapter *adapter =
4570                 (struct ixgbe_adapter *)dev->data->dev_private;
4571
4572         /*
4573          * In order to allow Vector Rx there are a few configuration
4574          * conditions to be met and Rx Bulk Allocation should be allowed.
4575          */
4576         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4577             !adapter->rx_bulk_alloc_allowed) {
4578                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4579                                     "preconditions or RTE_IXGBE_INC_VECTOR is "
4580                                     "not enabled",
4581                              dev->data->port_id);
4582
4583                 adapter->rx_vec_allowed = false;
4584         }
4585
4586         /*
4587          * Initialize the appropriate LRO callback.
4588          *
4589          * If all queues satisfy the bulk allocation preconditions
4590          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4591          * Otherwise use a single allocation version.
4592          */
4593         if (dev->data->lro) {
4594                 if (adapter->rx_bulk_alloc_allowed) {
4595                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4596                                            "allocation version");
4597                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4598                 } else {
4599                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4600                                            "allocation version");
4601                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4602                 }
4603         } else if (dev->data->scattered_rx) {
4604                 /*
4605                  * Set the non-LRO scattered callback: there are Vector and
4606                  * single allocation versions.
4607                  */
4608                 if (adapter->rx_vec_allowed) {
4609                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4610                                             "callback (port=%d).",
4611                                      dev->data->port_id);
4612
4613                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4614                 } else if (adapter->rx_bulk_alloc_allowed) {
4615                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4616                                            "allocation callback (port=%d).",
4617                                      dev->data->port_id);
4618                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4619                 } else {
4620                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4621                                             "single allocation) "
4622                                             "Scattered Rx callback "
4623                                             "(port=%d).",
4624                                      dev->data->port_id);
4625
4626                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4627                 }
4628         /*
4629          * Below we set "simple" callbacks according to port/queues parameters.
4630          * If parameters allow we are going to choose between the following
4631          * callbacks:
4632          *    - Vector
4633          *    - Bulk Allocation
4634          *    - Single buffer allocation (the simplest one)
4635          */
4636         } else if (adapter->rx_vec_allowed) {
4637                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4638                                     "burst size no less than %d (port=%d).",
4639                              RTE_IXGBE_DESCS_PER_LOOP,
4640                              dev->data->port_id);
4641
4642                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4643         } else if (adapter->rx_bulk_alloc_allowed) {
4644                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4645                                     "satisfied. Rx Burst Bulk Alloc function "
4646                                     "will be used on port=%d.",
4647                              dev->data->port_id);
4648
4649                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4650         } else {
4651                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4652                                     "satisfied, or Scattered Rx is requested "
4653                                     "(port=%d).",
4654                              dev->data->port_id);
4655
4656                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4657         }
4658
4659         /* Propagate information about RX function choice through all queues. */
4660
4661         rx_using_sse =
4662                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4663                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4664
4665         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4666                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4667
4668                 rxq->rx_using_sse = rx_using_sse;
4669 #ifdef RTE_LIBRTE_SECURITY
4670                 rxq->using_ipsec = !!(dev->data->dev_conf.rxmode.offloads &
4671                                 DEV_RX_OFFLOAD_SECURITY);
4672 #endif
4673         }
4674 }
4675
4676 /**
4677  * ixgbe_set_rsc - configure RSC related port HW registers
4678  *
4679  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4680  * of 82599 Spec (x540 configuration is virtually the same).
4681  *
4682  * @dev port handle
4683  *
4684  * Returns 0 in case of success or a non-zero error code
4685  */
4686 static int
4687 ixgbe_set_rsc(struct rte_eth_dev *dev)
4688 {
4689         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4691         struct rte_eth_dev_info dev_info = { 0 };
4692         bool rsc_capable = false;
4693         uint16_t i;
4694         uint32_t rdrxctl;
4695         uint32_t rfctl;
4696
4697         /* Sanity check */
4698         dev->dev_ops->dev_infos_get(dev, &dev_info);
4699         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4700                 rsc_capable = true;
4701
4702         if (!rsc_capable && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4703                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4704                                    "support it");
4705                 return -EINVAL;
4706         }
4707
4708         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4709
4710         if ((rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC) &&
4711              (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO)) {
4712                 /*
4713                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4714                  * 3.0 RSC configuration requires HW CRC stripping being
4715                  * enabled. If user requested both HW CRC stripping off
4716                  * and RSC on - return an error.
4717                  */
4718                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4719                                     "is disabled");
4720                 return -EINVAL;
4721         }
4722
4723         /* RFCTL configuration  */
4724         rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4725         if ((rsc_capable) && (rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4726                 /*
4727                  * Since NFS packets coalescing is not supported - clear
4728                  * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4729                  * enabled.
4730                  */
4731                 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4732                            IXGBE_RFCTL_NFSR_DIS);
4733         else
4734                 rfctl |= IXGBE_RFCTL_RSC_DIS;
4735         IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4736
4737         /* If LRO hasn't been requested - we are done here. */
4738         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_TCP_LRO))
4739                 return 0;
4740
4741         /* Set RDRXCTL.RSCACKC bit */
4742         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4743         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4744         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4745
4746         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4747         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4748                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4749                 uint32_t srrctl =
4750                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4751                 uint32_t rscctl =
4752                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4753                 uint32_t psrtype =
4754                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4755                 uint32_t eitr =
4756                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4757
4758                 /*
4759                  * ixgbe PMD doesn't support header-split at the moment.
4760                  *
4761                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4762                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4763                  * should be configured even if header split is not
4764                  * enabled. We will configure it 128 bytes following the
4765                  * recommendation in the spec.
4766                  */
4767                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4768                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4769                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4770
4771                 /*
4772                  * TODO: Consider setting the Receive Descriptor Minimum
4773                  * Threshold Size for an RSC case. This is not an obviously
4774                  * beneficiary option but the one worth considering...
4775                  */
4776
4777                 rscctl |= IXGBE_RSCCTL_RSCEN;
4778                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4779                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4780
4781                 /*
4782                  * RSC: Set ITR interval corresponding to 2K ints/s.
4783                  *
4784                  * Full-sized RSC aggregations for a 10Gb/s link will
4785                  * arrive at about 20K aggregation/s rate.
4786                  *
4787                  * 2K inst/s rate will make only 10% of the
4788                  * aggregations to be closed due to the interrupt timer
4789                  * expiration for a streaming at wire-speed case.
4790                  *
4791                  * For a sparse streaming case this setting will yield
4792                  * at most 500us latency for a single RSC aggregation.
4793                  */
4794                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4795                 eitr |= IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT);
4796                 eitr |= IXGBE_EITR_CNT_WDIS;
4797
4798                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4799                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4800                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4801                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4802
4803                 /*
4804                  * RSC requires the mapping of the queue to the
4805                  * interrupt vector.
4806                  */
4807                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4808         }
4809
4810         dev->data->lro = 1;
4811
4812         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4813
4814         return 0;
4815 }
4816
4817 /*
4818  * Initializes Receive Unit.
4819  */
4820 int __attribute__((cold))
4821 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4822 {
4823         struct ixgbe_hw     *hw;
4824         struct ixgbe_rx_queue *rxq;
4825         uint64_t bus_addr;
4826         uint32_t rxctrl;
4827         uint32_t fctrl;
4828         uint32_t hlreg0;
4829         uint32_t maxfrs;
4830         uint32_t srrctl;
4831         uint32_t rdrxctl;
4832         uint32_t rxcsum;
4833         uint16_t buf_size;
4834         uint16_t i;
4835         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4836         int rc;
4837
4838         PMD_INIT_FUNC_TRACE();
4839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4840
4841         /*
4842          * Make sure receives are disabled while setting
4843          * up the RX context (registers, descriptor rings, etc.).
4844          */
4845         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4846         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4847
4848         /* Enable receipt of broadcasted frames */
4849         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4850         fctrl |= IXGBE_FCTRL_BAM;
4851         fctrl |= IXGBE_FCTRL_DPF;
4852         fctrl |= IXGBE_FCTRL_PMCF;
4853         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4854
4855         /*
4856          * Configure CRC stripping, if any.
4857          */
4858         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4859         if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4860                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4861         else
4862                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4863
4864         /*
4865          * Configure jumbo frame support, if any.
4866          */
4867         if (rx_conf->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
4868                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4869                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4870                 maxfrs &= 0x0000FFFF;
4871                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4872                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4873         } else
4874                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4875
4876         /*
4877          * If loopback mode is configured for 82599, set LPBK bit.
4878          */
4879         if (hw->mac.type == ixgbe_mac_82599EB &&
4880                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4881                 hlreg0 |= IXGBE_HLREG0_LPBK;
4882         else
4883                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4884
4885         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4886
4887         /*
4888          * Assume no header split and no VLAN strip support
4889          * on any Rx queue first .
4890          */
4891         rx_conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
4892         /* Setup RX queues */
4893         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4894                 rxq = dev->data->rx_queues[i];
4895
4896                 /*
4897                  * Reset crc_len in case it was changed after queue setup by a
4898                  * call to configure.
4899                  */
4900                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4901                         rxq->crc_len = ETHER_CRC_LEN;
4902                 else
4903                         rxq->crc_len = 0;
4904
4905                 /* Setup the Base and Length of the Rx Descriptor Rings */
4906                 bus_addr = rxq->rx_ring_phys_addr;
4907                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4908                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4909                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4910                                 (uint32_t)(bus_addr >> 32));
4911                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4912                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4913                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4914                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4915
4916                 /* Configure the SRRCTL register */
4917                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4918
4919                 /* Set if packets are dropped when no descriptors available */
4920                 if (rxq->drop_en)
4921                         srrctl |= IXGBE_SRRCTL_DROP_EN;
4922
4923                 /*
4924                  * Configure the RX buffer size in the BSIZEPACKET field of
4925                  * the SRRCTL register of the queue.
4926                  * The value is in 1 KB resolution. Valid values can be from
4927                  * 1 KB to 16 KB.
4928                  */
4929                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4930                         RTE_PKTMBUF_HEADROOM);
4931                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4932                            IXGBE_SRRCTL_BSIZEPKT_MASK);
4933
4934                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4935
4936                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4937                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4938
4939                 /* It adds dual VLAN length for supporting dual VLAN */
4940                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4941                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4942                         dev->data->scattered_rx = 1;
4943                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4944                         rx_conf->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
4945         }
4946
4947         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
4948                 dev->data->scattered_rx = 1;
4949
4950         /*
4951          * Device configured with multiple RX queues.
4952          */
4953         ixgbe_dev_mq_rx_configure(dev);
4954
4955         /*
4956          * Setup the Checksum Register.
4957          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4958          * Enable IP/L4 checkum computation by hardware if requested to do so.
4959          */
4960         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4961         rxcsum |= IXGBE_RXCSUM_PCSD;
4962         if (rx_conf->offloads & DEV_RX_OFFLOAD_CHECKSUM)
4963                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4964         else
4965                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4966
4967         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4968
4969         if (hw->mac.type == ixgbe_mac_82599EB ||
4970             hw->mac.type == ixgbe_mac_X540) {
4971                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4972                 if (rx_conf->offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4973                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4974                 else
4975                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4976                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4977                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4978         }
4979
4980         rc = ixgbe_set_rsc(dev);
4981         if (rc)
4982                 return rc;
4983
4984         ixgbe_set_rx_function(dev);
4985
4986         return 0;
4987 }
4988
4989 /*
4990  * Initializes Transmit Unit.
4991  */
4992 void __attribute__((cold))
4993 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4994 {
4995         struct ixgbe_hw     *hw;
4996         struct ixgbe_tx_queue *txq;
4997         uint64_t bus_addr;
4998         uint32_t hlreg0;
4999         uint32_t txctrl;
5000         uint16_t i;
5001
5002         PMD_INIT_FUNC_TRACE();
5003         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004
5005         /* Enable TX CRC (checksum offload requirement) and hw padding
5006          * (TSO requirement)
5007          */
5008         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5009         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
5010         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5011
5012         /* Setup the Base and Length of the Tx Descriptor Rings */
5013         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5014                 txq = dev->data->tx_queues[i];
5015
5016                 bus_addr = txq->tx_ring_phys_addr;
5017                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
5018                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5019                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
5020                                 (uint32_t)(bus_addr >> 32));
5021                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
5022                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5023                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5024                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5025                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5026
5027                 /*
5028                  * Disable Tx Head Writeback RO bit, since this hoses
5029                  * bookkeeping if things aren't delivered in order.
5030                  */
5031                 switch (hw->mac.type) {
5032                 case ixgbe_mac_82598EB:
5033                         txctrl = IXGBE_READ_REG(hw,
5034                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
5035                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5036                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
5037                                         txctrl);
5038                         break;
5039
5040                 case ixgbe_mac_82599EB:
5041                 case ixgbe_mac_X540:
5042                 case ixgbe_mac_X550:
5043                 case ixgbe_mac_X550EM_x:
5044                 case ixgbe_mac_X550EM_a:
5045                 default:
5046                         txctrl = IXGBE_READ_REG(hw,
5047                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
5048                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5049                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
5050                                         txctrl);
5051                         break;
5052                 }
5053         }
5054
5055         /* Device configured with multiple TX queues. */
5056         ixgbe_dev_mq_tx_configure(dev);
5057 }
5058
5059 /*
5060  * Set up link for 82599 loopback mode Tx->Rx.
5061  */
5062 static inline void __attribute__((cold))
5063 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
5064 {
5065         PMD_INIT_FUNC_TRACE();
5066
5067         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
5068                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
5069                                 IXGBE_SUCCESS) {
5070                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
5071                         /* ignore error */
5072                         return;
5073                 }
5074         }
5075
5076         /* Restart link */
5077         IXGBE_WRITE_REG(hw,
5078                         IXGBE_AUTOC,
5079                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
5080         ixgbe_reset_pipeline_82599(hw);
5081
5082         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
5083         msec_delay(50);
5084 }
5085
5086
5087 /*
5088  * Start Transmit and Receive Units.
5089  */
5090 int __attribute__((cold))
5091 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
5092 {
5093         struct ixgbe_hw     *hw;
5094         struct ixgbe_tx_queue *txq;
5095         struct ixgbe_rx_queue *rxq;
5096         uint32_t txdctl;
5097         uint32_t dmatxctl;
5098         uint32_t rxctrl;
5099         uint16_t i;
5100         int ret = 0;
5101
5102         PMD_INIT_FUNC_TRACE();
5103         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5104
5105         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5106                 txq = dev->data->tx_queues[i];
5107                 /* Setup Transmit Threshold Registers */
5108                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5109                 txdctl |= txq->pthresh & 0x7F;
5110                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5111                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5112                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5113         }
5114
5115         if (hw->mac.type != ixgbe_mac_82598EB) {
5116                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
5117                 dmatxctl |= IXGBE_DMATXCTL_TE;
5118                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
5119         }
5120
5121         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5122                 txq = dev->data->tx_queues[i];
5123                 if (!txq->tx_deferred_start) {
5124                         ret = ixgbe_dev_tx_queue_start(dev, i);
5125                         if (ret < 0)
5126                                 return ret;
5127                 }
5128         }
5129
5130         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5131                 rxq = dev->data->rx_queues[i];
5132                 if (!rxq->rx_deferred_start) {
5133                         ret = ixgbe_dev_rx_queue_start(dev, i);
5134                         if (ret < 0)
5135                                 return ret;
5136                 }
5137         }
5138
5139         /* Enable Receive engine */
5140         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5141         if (hw->mac.type == ixgbe_mac_82598EB)
5142                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
5143         rxctrl |= IXGBE_RXCTRL_RXEN;
5144         hw->mac.ops.enable_rx_dma(hw, rxctrl);
5145
5146         /* If loopback mode is enabled for 82599, set up the link accordingly */
5147         if (hw->mac.type == ixgbe_mac_82599EB &&
5148                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
5149                 ixgbe_setup_loopback_link_82599(hw);
5150
5151 #ifdef RTE_LIBRTE_SECURITY
5152         if ((dev->data->dev_conf.rxmode.offloads &
5153                         DEV_RX_OFFLOAD_SECURITY) ||
5154                 (dev->data->dev_conf.txmode.offloads &
5155                         DEV_TX_OFFLOAD_SECURITY)) {
5156                 ret = ixgbe_crypto_enable_ipsec(dev);
5157                 if (ret != 0) {
5158                         PMD_DRV_LOG(ERR,
5159                                     "ixgbe_crypto_enable_ipsec fails with %d.",
5160                                     ret);
5161                         return ret;
5162                 }
5163         }
5164 #endif
5165
5166         return 0;
5167 }
5168
5169 /*
5170  * Start Receive Units for specified queue.
5171  */
5172 int __attribute__((cold))
5173 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5174 {
5175         struct ixgbe_hw     *hw;
5176         struct ixgbe_rx_queue *rxq;
5177         uint32_t rxdctl;
5178         int poll_ms;
5179
5180         PMD_INIT_FUNC_TRACE();
5181         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182
5183         rxq = dev->data->rx_queues[rx_queue_id];
5184
5185         /* Allocate buffers for descriptor rings */
5186         if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
5187                 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
5188                              rx_queue_id);
5189                 return -1;
5190         }
5191         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5192         rxdctl |= IXGBE_RXDCTL_ENABLE;
5193         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5194
5195         /* Wait until RX Enable ready */
5196         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5197         do {
5198                 rte_delay_ms(1);
5199                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5200         } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5201         if (!poll_ms)
5202                 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", rx_queue_id);
5203         rte_wmb();
5204         IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
5205         IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
5206         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5207
5208         return 0;
5209 }
5210
5211 /*
5212  * Stop Receive Units for specified queue.
5213  */
5214 int __attribute__((cold))
5215 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
5216 {
5217         struct ixgbe_hw     *hw;
5218         struct ixgbe_adapter *adapter =
5219                 (struct ixgbe_adapter *)dev->data->dev_private;
5220         struct ixgbe_rx_queue *rxq;
5221         uint32_t rxdctl;
5222         int poll_ms;
5223
5224         PMD_INIT_FUNC_TRACE();
5225         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5226
5227         rxq = dev->data->rx_queues[rx_queue_id];
5228
5229         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5230         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5231         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
5232
5233         /* Wait until RX Enable bit clear */
5234         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5235         do {
5236                 rte_delay_ms(1);
5237                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
5238         } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
5239         if (!poll_ms)
5240                 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d", rx_queue_id);
5241
5242         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5243
5244         ixgbe_rx_queue_release_mbufs(rxq);
5245         ixgbe_reset_rx_queue(adapter, rxq);
5246         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5247
5248         return 0;
5249 }
5250
5251
5252 /*
5253  * Start Transmit Units for specified queue.
5254  */
5255 int __attribute__((cold))
5256 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5257 {
5258         struct ixgbe_hw     *hw;
5259         struct ixgbe_tx_queue *txq;
5260         uint32_t txdctl;
5261         int poll_ms;
5262
5263         PMD_INIT_FUNC_TRACE();
5264         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265
5266         txq = dev->data->tx_queues[tx_queue_id];
5267         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5268         txdctl |= IXGBE_TXDCTL_ENABLE;
5269         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5270
5271         /* Wait until TX Enable ready */
5272         if (hw->mac.type == ixgbe_mac_82599EB) {
5273                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5274                 do {
5275                         rte_delay_ms(1);
5276                         txdctl = IXGBE_READ_REG(hw,
5277                                 IXGBE_TXDCTL(txq->reg_idx));
5278                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5279                 if (!poll_ms)
5280                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d",
5281                                 tx_queue_id);
5282         }
5283         rte_wmb();
5284         IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
5285         IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
5286         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
5287
5288         return 0;
5289 }
5290
5291 /*
5292  * Stop Transmit Units for specified queue.
5293  */
5294 int __attribute__((cold))
5295 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
5296 {
5297         struct ixgbe_hw     *hw;
5298         struct ixgbe_tx_queue *txq;
5299         uint32_t txdctl;
5300         uint32_t txtdh, txtdt;
5301         int poll_ms;
5302
5303         PMD_INIT_FUNC_TRACE();
5304         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5305
5306         txq = dev->data->tx_queues[tx_queue_id];
5307
5308         /* Wait until TX queue is empty */
5309         if (hw->mac.type == ixgbe_mac_82599EB) {
5310                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5311                 do {
5312                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
5313                         txtdh = IXGBE_READ_REG(hw,
5314                                                IXGBE_TDH(txq->reg_idx));
5315                         txtdt = IXGBE_READ_REG(hw,
5316                                                IXGBE_TDT(txq->reg_idx));
5317                 } while (--poll_ms && (txtdh != txtdt));
5318                 if (!poll_ms)
5319                         PMD_INIT_LOG(ERR,
5320                                 "Tx Queue %d is not empty when stopping.",
5321                                 tx_queue_id);
5322         }
5323
5324         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
5325         txdctl &= ~IXGBE_TXDCTL_ENABLE;
5326         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
5327
5328         /* Wait until TX Enable bit clear */
5329         if (hw->mac.type == ixgbe_mac_82599EB) {
5330                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
5331                 do {
5332                         rte_delay_ms(1);
5333                         txdctl = IXGBE_READ_REG(hw,
5334                                                 IXGBE_TXDCTL(txq->reg_idx));
5335                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
5336                 if (!poll_ms)
5337                         PMD_INIT_LOG(ERR, "Could not disable Tx Queue %d",
5338                                 tx_queue_id);
5339         }
5340
5341         if (txq->ops != NULL) {
5342                 txq->ops->release_mbufs(txq);
5343                 txq->ops->reset(txq);
5344         }
5345         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
5346
5347         return 0;
5348 }
5349
5350 void
5351 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5352         struct rte_eth_rxq_info *qinfo)
5353 {
5354         struct ixgbe_rx_queue *rxq;
5355
5356         rxq = dev->data->rx_queues[queue_id];
5357
5358         qinfo->mp = rxq->mb_pool;
5359         qinfo->scattered_rx = dev->data->scattered_rx;
5360         qinfo->nb_desc = rxq->nb_rx_desc;
5361
5362         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
5363         qinfo->conf.rx_drop_en = rxq->drop_en;
5364         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
5365         qinfo->conf.offloads = rxq->offloads;
5366 }
5367
5368 void
5369 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
5370         struct rte_eth_txq_info *qinfo)
5371 {
5372         struct ixgbe_tx_queue *txq;
5373
5374         txq = dev->data->tx_queues[queue_id];
5375
5376         qinfo->nb_desc = txq->nb_tx_desc;
5377
5378         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
5379         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
5380         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
5381
5382         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
5383         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
5384         qinfo->conf.offloads = txq->offloads;
5385         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
5386 }
5387
5388 /*
5389  * [VF] Initializes Receive Unit.
5390  */
5391 int __attribute__((cold))
5392 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
5393 {
5394         struct ixgbe_hw     *hw;
5395         struct ixgbe_rx_queue *rxq;
5396         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
5397         uint64_t bus_addr;
5398         uint32_t srrctl, psrtype = 0;
5399         uint16_t buf_size;
5400         uint16_t i;
5401         int ret;
5402
5403         PMD_INIT_FUNC_TRACE();
5404         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405
5406         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5407                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5408                         "it should be power of 2");
5409                 return -1;
5410         }
5411
5412         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5413                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5414                         "it should be equal to or less than %d",
5415                         hw->mac.max_rx_queues);
5416                 return -1;
5417         }
5418
5419         /*
5420          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5421          * disables the VF receipt of packets if the PF MTU is > 1500.
5422          * This is done to deal with 82599 limitations that imposes
5423          * the PF and all VFs to share the same MTU.
5424          * Then, the PF driver enables again the VF receipt of packet when
5425          * the VF driver issues a IXGBE_VF_SET_LPE request.
5426          * In the meantime, the VF device cannot be used, even if the VF driver
5427          * and the Guest VM network stack are ready to accept packets with a
5428          * size up to the PF MTU.
5429          * As a work-around to this PF behaviour, force the call to
5430          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5431          * VF packets received can work in all cases.
5432          */
5433         ixgbevf_rlpml_set_vf(hw,
5434                 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5435
5436         /*
5437          * Assume no header split and no VLAN strip support
5438          * on any Rx queue first .
5439          */
5440         rxmode->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
5441         /* Setup RX queues */
5442         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5443                 rxq = dev->data->rx_queues[i];
5444
5445                 /* Allocate buffers for descriptor rings */
5446                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5447                 if (ret)
5448                         return ret;
5449
5450                 /* Setup the Base and Length of the Rx Descriptor Rings */
5451                 bus_addr = rxq->rx_ring_phys_addr;
5452
5453                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5454                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5455                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5456                                 (uint32_t)(bus_addr >> 32));
5457                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5458                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5459                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5460                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5461
5462
5463                 /* Configure the SRRCTL register */
5464                 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5465
5466                 /* Set if packets are dropped when no descriptors available */
5467                 if (rxq->drop_en)
5468                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5469
5470                 /*
5471                  * Configure the RX buffer size in the BSIZEPACKET field of
5472                  * the SRRCTL register of the queue.
5473                  * The value is in 1 KB resolution. Valid values can be from
5474                  * 1 KB to 16 KB.
5475                  */
5476                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5477                         RTE_PKTMBUF_HEADROOM);
5478                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5479                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5480
5481                 /*
5482                  * VF modification to write virtual function SRRCTL register
5483                  */
5484                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5485
5486                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5487                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5488
5489                 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER ||
5490                     /* It adds dual VLAN length for supporting dual VLAN */
5491                     (rxmode->max_rx_pkt_len +
5492                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5493                         if (!dev->data->scattered_rx)
5494                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5495                         dev->data->scattered_rx = 1;
5496                 }
5497
5498                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
5499                         rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
5500         }
5501
5502         /* Set RQPL for VF RSS according to max Rx queue */
5503         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5504                 IXGBE_PSRTYPE_RQPL_SHIFT;
5505         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5506
5507         ixgbe_set_rx_function(dev);
5508
5509         return 0;
5510 }
5511
5512 /*
5513  * [VF] Initializes Transmit Unit.
5514  */
5515 void __attribute__((cold))
5516 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5517 {
5518         struct ixgbe_hw     *hw;
5519         struct ixgbe_tx_queue *txq;
5520         uint64_t bus_addr;
5521         uint32_t txctrl;
5522         uint16_t i;
5523
5524         PMD_INIT_FUNC_TRACE();
5525         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5526
5527         /* Setup the Base and Length of the Tx Descriptor Rings */
5528         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5529                 txq = dev->data->tx_queues[i];
5530                 bus_addr = txq->tx_ring_phys_addr;
5531                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5532                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5533                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5534                                 (uint32_t)(bus_addr >> 32));
5535                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5536                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5537                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5538                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5539                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5540
5541                 /*
5542                  * Disable Tx Head Writeback RO bit, since this hoses
5543                  * bookkeeping if things aren't delivered in order.
5544                  */
5545                 txctrl = IXGBE_READ_REG(hw,
5546                                 IXGBE_VFDCA_TXCTRL(i));
5547                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5548                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5549                                 txctrl);
5550         }
5551 }
5552
5553 /*
5554  * [VF] Start Transmit and Receive Units.
5555  */
5556 void __attribute__((cold))
5557 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5558 {
5559         struct ixgbe_hw     *hw;
5560         struct ixgbe_tx_queue *txq;
5561         struct ixgbe_rx_queue *rxq;
5562         uint32_t txdctl;
5563         uint32_t rxdctl;
5564         uint16_t i;
5565         int poll_ms;
5566
5567         PMD_INIT_FUNC_TRACE();
5568         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5569
5570         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5571                 txq = dev->data->tx_queues[i];
5572                 /* Setup Transmit Threshold Registers */
5573                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5574                 txdctl |= txq->pthresh & 0x7F;
5575                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5576                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5577                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5578         }
5579
5580         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5581
5582                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5583                 txdctl |= IXGBE_TXDCTL_ENABLE;
5584                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5585
5586                 poll_ms = 10;
5587                 /* Wait until TX Enable ready */
5588                 do {
5589                         rte_delay_ms(1);
5590                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5591                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5592                 if (!poll_ms)
5593                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5594         }
5595         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5596
5597                 rxq = dev->data->rx_queues[i];
5598
5599                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5600                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5601                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5602
5603                 /* Wait until RX Enable ready */
5604                 poll_ms = 10;
5605                 do {
5606                         rte_delay_ms(1);
5607                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5608                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5609                 if (!poll_ms)
5610                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5611                 rte_wmb();
5612                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5613
5614         }
5615 }
5616
5617 int
5618 ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
5619                     const struct rte_flow_action_rss *in)
5620 {
5621         if (in->key_len > RTE_DIM(out->key) ||
5622             in->queue_num > RTE_DIM(out->queue))
5623                 return -EINVAL;
5624         out->conf = (struct rte_flow_action_rss){
5625                 .func = in->func,
5626                 .level = in->level,
5627                 .types = in->types,
5628                 .key_len = in->key_len,
5629                 .queue_num = in->queue_num,
5630                 .key = memcpy(out->key, in->key, in->key_len),
5631                 .queue = memcpy(out->queue, in->queue,
5632                                 sizeof(*in->queue) * in->queue_num),
5633         };
5634         return 0;
5635 }
5636
5637 int
5638 ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
5639                       const struct rte_flow_action_rss *with)
5640 {
5641         return (comp->func == with->func &&
5642                 comp->level == with->level &&
5643                 comp->types == with->types &&
5644                 comp->key_len == with->key_len &&
5645                 comp->queue_num == with->queue_num &&
5646                 !memcmp(comp->key, with->key, with->key_len) &&
5647                 !memcmp(comp->queue, with->queue,
5648                         sizeof(*with->queue) * with->queue_num));
5649 }
5650
5651 int
5652 ixgbe_config_rss_filter(struct rte_eth_dev *dev,
5653                 struct ixgbe_rte_flow_rss_conf *conf, bool add)
5654 {
5655         struct ixgbe_hw *hw;
5656         uint32_t reta;
5657         uint16_t i;
5658         uint16_t j;
5659         uint16_t sp_reta_size;
5660         uint32_t reta_reg;
5661         struct rte_eth_rss_conf rss_conf = {
5662                 .rss_key = conf->conf.key_len ?
5663                         (void *)(uintptr_t)conf->conf.key : NULL,
5664                 .rss_key_len = conf->conf.key_len,
5665                 .rss_hf = conf->conf.types,
5666         };
5667         struct ixgbe_filter_info *filter_info =
5668                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5669
5670         PMD_INIT_FUNC_TRACE();
5671         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672
5673         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5674
5675         if (!add) {
5676                 if (ixgbe_action_rss_same(&filter_info->rss_info.conf,
5677                                           &conf->conf)) {
5678                         ixgbe_rss_disable(dev);
5679                         memset(&filter_info->rss_info, 0,
5680                                 sizeof(struct ixgbe_rte_flow_rss_conf));
5681                         return 0;
5682                 }
5683                 return -EINVAL;
5684         }
5685
5686         if (filter_info->rss_info.conf.queue_num)
5687                 return -EINVAL;
5688         /* Fill in redirection table
5689          * The byte-swap is needed because NIC registers are in
5690          * little-endian order.
5691          */
5692         reta = 0;
5693         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
5694                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5695
5696                 if (j == conf->conf.queue_num)
5697                         j = 0;
5698                 reta = (reta << 8) | conf->conf.queue[j];
5699                 if ((i & 3) == 3)
5700                         IXGBE_WRITE_REG(hw, reta_reg,
5701                                         rte_bswap32(reta));
5702         }
5703
5704         /* Configure the RSS key and the RSS protocols used to compute
5705          * the RSS hash of input packets.
5706          */
5707         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
5708                 ixgbe_rss_disable(dev);
5709                 return 0;
5710         }
5711         if (rss_conf.rss_key == NULL)
5712                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
5713         ixgbe_hw_rss_hash_set(hw, &rss_conf);
5714
5715         if (ixgbe_rss_conf_init(&filter_info->rss_info, &conf->conf))
5716                 return -EINVAL;
5717
5718         return 0;
5719 }
5720
5721 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5722 __rte_weak int
5723 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5724 {
5725         return -1;
5726 }
5727
5728 __rte_weak uint16_t
5729 ixgbe_recv_pkts_vec(
5730         void __rte_unused *rx_queue,
5731         struct rte_mbuf __rte_unused **rx_pkts,
5732         uint16_t __rte_unused nb_pkts)
5733 {
5734         return 0;
5735 }
5736
5737 __rte_weak uint16_t
5738 ixgbe_recv_scattered_pkts_vec(
5739         void __rte_unused *rx_queue,
5740         struct rte_mbuf __rte_unused **rx_pkts,
5741         uint16_t __rte_unused nb_pkts)
5742 {
5743         return 0;
5744 }
5745
5746 __rte_weak int
5747 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5748 {
5749         return -1;
5750 }