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34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* --------------------------CONFIG VALUES------------------------ */
47 /* CN23xx IQ configuration macros */
48 #define CN23XX_MAX_RINGS_PER_PF 64
49 #define CN23XX_MAX_RINGS_PER_VF 8
51 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
52 #define CN23XX_MAX_IQ_DESCRIPTORS 512
53 #define CN23XX_MIN_IQ_DESCRIPTORS 128
55 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
56 #define CN23XX_MAX_OQ_DESCRIPTORS 512
57 #define CN23XX_MIN_OQ_DESCRIPTORS 128
58 #define CN23XX_OQ_BUF_SIZE 1536
60 #define CN23XX_OQ_REFIL_THRESHOLD 16
62 #define CN23XX_DEFAULT_NUM_PORTS 1
64 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
66 /* common OCTEON configuration macros */
67 #define OCTEON_64BYTE_INSTR 64
68 #define OCTEON_OQ_INFOPTR_MODE 1
70 /* Max IOQs per LIO Link */
71 #define LIO_MAX_IOQS_PER_IF 64
77 #define LIO_23XX_NAME "23xx"
79 #define LIO_DEV_RUNNING 0xc
81 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
82 ((cfg)->default_config->oq.refill_threshold)
83 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
84 ((cfg)->default_config->num_def_tx_descs)
86 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
88 /* The following config values are fixed and should not be modified. */
90 /* Maximum number of Instruction queues */
91 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
93 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
94 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
96 #define LIO_DEVICE_NAME_LEN 32
97 #define LIO_BASE_MAJOR_VERSION 1
98 #define LIO_BASE_MINOR_VERSION 5
99 #define LIO_BASE_MICRO_VERSION 1
101 #define LIO_FW_VERSION_LENGTH 32
103 /** Tag types used by Octeon cores in its work. */
104 enum octeon_tag_type {
105 OCTEON_ORDERED_TAG = 0,
106 OCTEON_ATOMIC_TAG = 1,
109 /* pre-defined host->NIC tag values */
110 #define LIO_CONTROL (0x11111110)
111 #define LIO_DATA(i) (0x11111111 + (i))
113 /* used for NIC operations */
116 /* Subcodes are used by host driver/apps to identify the sub-operation
117 * for the core. They only need to by unique for a given subsystem.
119 #define LIO_OPCODE_SUBCODE(op, sub) \
120 ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
122 /** LIO_OPCODE subcodes */
123 /* This subcode is sent by core PCI driver to indicate cores are ready. */
124 #define LIO_OPCODE_NW_DATA 0x02 /* network packet data */
125 #define LIO_OPCODE_CMD 0x03
126 #define LIO_OPCODE_INFO 0x04
127 #define LIO_OPCODE_PORT_STATS 0x05
128 #define LIO_OPCODE_IF_CFG 0x09
130 #define LIO_MIN_RX_BUF_SIZE 64
131 #define LIO_MAX_RX_PKTLEN (64 * 1024)
133 /* NIC Command types */
134 #define LIO_CMD_CHANGE_DEVFLAGS 0x3
135 #define LIO_CMD_RX_CTL 0x4
136 #define LIO_CMD_CLEAR_STATS 0x6
137 #define LIO_CMD_SET_RSS 0xD
138 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10
139 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11
140 #define LIO_CMD_ADD_VLAN_FILTER 0x17
141 #define LIO_CMD_DEL_VLAN_FILTER 0x18
142 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19
144 #define LIO_CMD_VXLAN_PORT_ADD 0x0
145 #define LIO_CMD_VXLAN_PORT_DEL 0x1
146 #define LIO_CMD_RXCSUM_ENABLE 0x0
147 #define LIO_CMD_TXCSUM_ENABLE 0x0
149 /* RX(packets coming from wire) Checksum verification flags */
151 #define LIO_L4_CSUM_VERIFIED 0x1
152 #define LIO_IP_CSUM_VERIFIED 0x2
155 #define LIO_RSS_PARAM_DISABLE_RSS 0x10
156 #define LIO_RSS_PARAM_HASH_KEY_UNCHANGED 0x08
157 #define LIO_RSS_PARAM_ITABLE_UNCHANGED 0x04
158 #define LIO_RSS_PARAM_HASH_INFO_UNCHANGED 0x02
160 #define LIO_RSS_HASH_IPV4 0x100
161 #define LIO_RSS_HASH_TCP_IPV4 0x200
162 #define LIO_RSS_HASH_IPV6 0x400
163 #define LIO_RSS_HASH_TCP_IPV6 0x1000
164 #define LIO_RSS_HASH_IPV6_EX 0x800
165 #define LIO_RSS_HASH_TCP_IPV6_EX 0x2000
167 #define LIO_RSS_OFFLOAD_ALL ( \
168 LIO_RSS_HASH_IPV4 | \
169 LIO_RSS_HASH_TCP_IPV4 | \
170 LIO_RSS_HASH_IPV6 | \
171 LIO_RSS_HASH_TCP_IPV6 | \
172 LIO_RSS_HASH_IPV6_EX | \
173 LIO_RSS_HASH_TCP_IPV6_EX)
175 #define LIO_RSS_MAX_TABLE_SZ 128
176 #define LIO_RSS_MAX_KEY_SZ 40
177 #define LIO_RSS_PARAM_SIZE 16
179 /* Interface flags communicated between host driver and core app. */
181 LIO_IFFLAG_ALLMULTI = 0x02,
182 LIO_IFFLAG_UNICAST = 0x10
185 /* Routines for reading and writing CSRs */
186 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
187 #define lio_write_csr(lio_dev, reg_off, value) \
189 typeof(lio_dev) _dev = lio_dev; \
190 typeof(reg_off) _reg_off = reg_off; \
191 typeof(value) _value = value; \
193 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
194 (unsigned long)_reg_off, \
195 (unsigned long)_value); \
196 rte_write32(_value, _dev->hw_addr + _reg_off); \
199 #define lio_write_csr64(lio_dev, reg_off, val64) \
201 typeof(lio_dev) _dev = lio_dev; \
202 typeof(reg_off) _reg_off = reg_off; \
203 typeof(val64) _val64 = val64; \
206 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
207 (unsigned long)_reg_off, \
208 (unsigned long long)_val64); \
209 rte_write64(_val64, _dev->hw_addr + _reg_off); \
212 #define lio_read_csr(lio_dev, reg_off) \
214 typeof(lio_dev) _dev = lio_dev; \
215 typeof(reg_off) _reg_off = reg_off; \
216 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
218 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
219 (unsigned long)_reg_off, \
220 (unsigned long)val); \
224 #define lio_read_csr64(lio_dev, reg_off) \
226 typeof(lio_dev) _dev = lio_dev; \
227 typeof(reg_off) _reg_off = reg_off; \
228 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
231 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
232 (unsigned long)_reg_off, \
233 (unsigned long long)val64); \
237 #define lio_write_csr(lio_dev, reg_off, value) \
238 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
240 #define lio_write_csr64(lio_dev, reg_off, val64) \
241 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
243 #define lio_read_csr(lio_dev, reg_off) \
244 rte_read32((lio_dev)->hw_addr + (reg_off))
246 #define lio_read_csr64(lio_dev, reg_off) \
247 rte_read64((lio_dev)->hw_addr + (reg_off))
249 #endif /* _LIO_HW_DEFS_H_ */