drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9
  10 /* Verbs header. */
  11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  12 #ifdef PEDANTIC
  13 #pragma GCC diagnostic ignored "-Wpedantic"
  14 #endif
  15 #include <infiniband/verbs.h>
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic error "-Wpedantic"
  18 #endif
  19
  20 #include <rte_common.h>
  21 #include <rte_ether.h>
  22 #include <rte_eth_ctrl.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_defs.h"
  32 #include "mlx5_prm.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35
  36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  37
  38 /**
  39  * Validate META item.
  40  *
  41  * @param[in] dev
  42  *   Pointer to the rte_eth_dev structure.
  43  * @param[in] item
  44  *   Item specification.
  45  * @param[in] attr
  46  *   Attributes of flow that includes this item.
  47  * @param[out] error
  48  *   Pointer to error structure.
  49  *
  50  * @return
  51  *   0 on success, a negative errno value otherwise and rte_errno is set.
  52  */
  53 static int
  54 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
  55                            const struct rte_flow_item *item,
  56                            const struct rte_flow_attr *attr,
  57                            struct rte_flow_error *error)
  58 {
  59         const struct rte_flow_item_meta *spec = item->spec;
  60         const struct rte_flow_item_meta *mask = item->mask;
  61         const struct rte_flow_item_meta nic_mask = {
  62                 .data = RTE_BE32(UINT32_MAX)
  63         };
  64         int ret;
  65         uint64_t offloads = dev->data->dev_conf.txmode.offloads;
  66
  67         if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
  68                 return rte_flow_error_set(error, EPERM,
  69                                           RTE_FLOW_ERROR_TYPE_ITEM,
  70                                           NULL,
  71                                           "match on metadata offload "
  72                                           "configuration is off for this port");
  73         if (!spec)
  74                 return rte_flow_error_set(error, EINVAL,
  75                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  76                                           item->spec,
  77                                           "data cannot be empty");
  78         if (!spec->data)
  79                 return rte_flow_error_set(error, EINVAL,
  80                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  81                                           NULL,
  82                                           "data cannot be zero");
  83         if (!mask)
  84                 mask = &rte_flow_item_meta_mask;
  85         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
  86                                         (const uint8_t *)&nic_mask,
  87                                         sizeof(struct rte_flow_item_meta),
  88                                         error);
  89         if (ret < 0)
  90                 return ret;
  91         if (attr->ingress)
  92                 return rte_flow_error_set(error, ENOTSUP,
  93                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
  94                                           NULL,
  95                                           "pattern not supported for ingress");
  96         return 0;
  97 }
  98
  99 /**
 100  * Validate the L2 encap action.
 101  *
 102  * @param[in] action_flags
 103  *   Holds the actions detected until now.
 104  * @param[in] action
 105  *   Pointer to the encap action.
 106  * @param[in] attr
 107  *   Pointer to flow attributes
 108  * @param[out] error
 109  *   Pointer to error structure.
 110  *
 111  * @return
 112  *   0 on success, a negative errno value otherwise and rte_errno is set.
 113  */
 114 static int
 115 flow_dv_validate_action_l2_encap(uint64_t action_flags,
 116                                  const struct rte_flow_action *action,
 117                                  const struct rte_flow_attr *attr,
 118                                  struct rte_flow_error *error)
 119 {
 120         if (!(action->conf))
 121                 return rte_flow_error_set(error, EINVAL,
 122                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 123                                           "configuration cannot be null");
 124         if (action_flags & MLX5_FLOW_ACTION_DROP)
 125                 return rte_flow_error_set(error, EINVAL,
 126                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 127                                           "can't drop and encap in same flow");
 128         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 129                 return rte_flow_error_set(error, EINVAL,
 130                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 131                                           "can only have a single encap or"
 132                                           " decap action in a flow");
 133         if (attr->ingress)
 134                 return rte_flow_error_set(error, ENOTSUP,
 135                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 136                                           NULL,
 137                                           "encap action not supported for "
 138                                           "ingress");
 139         return 0;
 140 }
 141
 142 /**
 143  * Validate the L2 decap action.
 144  *
 145  * @param[in] action_flags
 146  *   Holds the actions detected until now.
 147  * @param[in] attr
 148  *   Pointer to flow attributes
 149  * @param[out] error
 150  *   Pointer to error structure.
 151  *
 152  * @return
 153  *   0 on success, a negative errno value otherwise and rte_errno is set.
 154  */
 155 static int
 156 flow_dv_validate_action_l2_decap(uint64_t action_flags,
 157                                  const struct rte_flow_attr *attr,
 158                                  struct rte_flow_error *error)
 159 {
 160         if (action_flags & MLX5_FLOW_ACTION_DROP)
 161                 return rte_flow_error_set(error, EINVAL,
 162                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 163                                           "can't drop and decap in same flow");
 164         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 165                 return rte_flow_error_set(error, EINVAL,
 166                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 167                                           "can only have a single encap or"
 168                                           " decap action in a flow");
 169         if (attr->egress)
 170                 return rte_flow_error_set(error, ENOTSUP,
 171                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 172                                           NULL,
 173                                           "decap action not supported for "
 174                                           "egress");
 175         return 0;
 176 }
 177
 178 /**
 179  * Validate the raw encap action.
 180  *
 181  * @param[in] action_flags
 182  *   Holds the actions detected until now.
 183  * @param[in] action
 184  *   Pointer to the encap action.
 185  * @param[in] attr
 186  *   Pointer to flow attributes
 187  * @param[out] error
 188  *   Pointer to error structure.
 189  *
 190  * @return
 191  *   0 on success, a negative errno value otherwise and rte_errno is set.
 192  */
 193 static int
 194 flow_dv_validate_action_raw_encap(uint64_t action_flags,
 195                                   const struct rte_flow_action *action,
 196                                   const struct rte_flow_attr *attr,
 197                                   struct rte_flow_error *error)
 198 {
 199         if (!(action->conf))
 200                 return rte_flow_error_set(error, EINVAL,
 201                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 202                                           "configuration cannot be null");
 203         if (action_flags & MLX5_FLOW_ACTION_DROP)
 204                 return rte_flow_error_set(error, EINVAL,
 205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 206                                           "can't drop and encap in same flow");
 207         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 208                 return rte_flow_error_set(error, EINVAL,
 209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 210                                           "can only have a single encap"
 211                                           " action in a flow");
 212         /* encap without preceding decap is not supported for ingress */
 213         if (attr->ingress && !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
 214                 return rte_flow_error_set(error, ENOTSUP,
 215                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 216                                           NULL,
 217                                           "encap action not supported for "
 218                                           "ingress");
 219         return 0;
 220 }
 221
 222 /**
 223  * Validate the raw decap action.
 224  *
 225  * @param[in] action_flags
 226  *   Holds the actions detected until now.
 227  * @param[in] action
 228  *   Pointer to the encap action.
 229  * @param[in] attr
 230  *   Pointer to flow attributes
 231  * @param[out] error
 232  *   Pointer to error structure.
 233  *
 234  * @return
 235  *   0 on success, a negative errno value otherwise and rte_errno is set.
 236  */
 237 static int
 238 flow_dv_validate_action_raw_decap(uint64_t action_flags,
 239                                   const struct rte_flow_action *action,
 240                                   const struct rte_flow_attr *attr,
 241                                   struct rte_flow_error *error)
 242 {
 243         if (action_flags & MLX5_FLOW_ACTION_DROP)
 244                 return rte_flow_error_set(error, EINVAL,
 245                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 246                                           "can't drop and decap in same flow");
 247         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 248                 return rte_flow_error_set(error, EINVAL,
 249                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 250                                           "can't have encap action before"
 251                                           " decap action");
 252         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
 253                 return rte_flow_error_set(error, EINVAL,
 254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 255                                           "can only have a single decap"
 256                                           " action in a flow");
 257         /* decap action is valid on egress only if it is followed by encap */
 258         if (attr->egress) {
 259                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
 260                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
 261                        action++) {
 262                 }
 263                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
 264                         return rte_flow_error_set
 265                                         (error, ENOTSUP,
 266                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 267                                          NULL, "decap action not supported"
 268                                          " for egress");
 269         }
 270         return 0;
 271 }
 272
 273
 274 /**
 275  * Find existing encap/decap resource or create and register a new one.
 276  *
 277  * @param dev[in, out]
 278  *   Pointer to rte_eth_dev structure.
 279  * @param[in, out] resource
 280  *   Pointer to encap/decap resource.
 281  * @parm[in, out] dev_flow
 282  *   Pointer to the dev_flow.
 283  * @param[out] error
 284  *   pointer to error structure.
 285  *
 286  * @return
 287  *   0 on success otherwise -errno and errno is set.
 288  */
 289 static int
 290 flow_dv_encap_decap_resource_register
 291                         (struct rte_eth_dev *dev,
 292                          struct mlx5_flow_dv_encap_decap_resource *resource,
 293                          struct mlx5_flow *dev_flow,
 294                          struct rte_flow_error *error)
 295 {
 296         struct priv *priv = dev->data->dev_private;
 297         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
 298
 299         /* Lookup a matching resource from cache. */
 300         LIST_FOREACH(cache_resource, &priv->encaps_decaps, next) {
 301                 if (resource->reformat_type == cache_resource->reformat_type &&
 302                     resource->ft_type == cache_resource->ft_type &&
 303                     resource->size == cache_resource->size &&
 304                     !memcmp((const void *)resource->buf,
 305                             (const void *)cache_resource->buf,
 306                             resource->size)) {
 307                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
 308                                 (void *)cache_resource,
 309                                 rte_atomic32_read(&cache_resource->refcnt));
 310                         rte_atomic32_inc(&cache_resource->refcnt);
 311                         dev_flow->dv.encap_decap = cache_resource;
 312                         return 0;
 313                 }
 314         }
 315         /* Register new encap/decap resource. */
 316         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
 317         if (!cache_resource)
 318                 return rte_flow_error_set(error, ENOMEM,
 319                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
 320                                           "cannot allocate resource memory");
 321         *cache_resource = *resource;
 322         cache_resource->verbs_action =
 323                 mlx5_glue->dv_create_flow_action_packet_reformat
 324                         (priv->ctx, cache_resource->size,
 325                          (cache_resource->size ? cache_resource->buf : NULL),
 326                          cache_resource->reformat_type,
 327                          cache_resource->ft_type);
 328         if (!cache_resource->verbs_action) {
 329                 rte_free(cache_resource);
 330                 return rte_flow_error_set(error, ENOMEM,
 331                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 332                                           NULL, "cannot create action");
 333         }
 334         rte_atomic32_init(&cache_resource->refcnt);
 335         rte_atomic32_inc(&cache_resource->refcnt);
 336         LIST_INSERT_HEAD(&priv->encaps_decaps, cache_resource, next);
 337         dev_flow->dv.encap_decap = cache_resource;
 338         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
 339                 (void *)cache_resource,
 340                 rte_atomic32_read(&cache_resource->refcnt));
 341         return 0;
 342 }
 343
 344 /**
 345  * Get the size of specific rte_flow_item_type
 346  *
 347  * @param[in] item_type
 348  *   Tested rte_flow_item_type.
 349  *
 350  * @return
 351  *   sizeof struct item_type, 0 if void or irrelevant.
 352  */
 353 static size_t
 354 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
 355 {
 356         size_t retval;
 357
 358         switch (item_type) {
 359         case RTE_FLOW_ITEM_TYPE_ETH:
 360                 retval = sizeof(struct rte_flow_item_eth);
 361                 break;
 362         case RTE_FLOW_ITEM_TYPE_VLAN:
 363                 retval = sizeof(struct rte_flow_item_vlan);
 364                 break;
 365         case RTE_FLOW_ITEM_TYPE_IPV4:
 366                 retval = sizeof(struct rte_flow_item_ipv4);
 367                 break;
 368         case RTE_FLOW_ITEM_TYPE_IPV6:
 369                 retval = sizeof(struct rte_flow_item_ipv6);
 370                 break;
 371         case RTE_FLOW_ITEM_TYPE_UDP:
 372                 retval = sizeof(struct rte_flow_item_udp);
 373                 break;
 374         case RTE_FLOW_ITEM_TYPE_TCP:
 375                 retval = sizeof(struct rte_flow_item_tcp);
 376                 break;
 377         case RTE_FLOW_ITEM_TYPE_VXLAN:
 378                 retval = sizeof(struct rte_flow_item_vxlan);
 379                 break;
 380         case RTE_FLOW_ITEM_TYPE_GRE:
 381                 retval = sizeof(struct rte_flow_item_gre);
 382                 break;
 383         case RTE_FLOW_ITEM_TYPE_NVGRE:
 384                 retval = sizeof(struct rte_flow_item_nvgre);
 385                 break;
 386         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 387                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
 388                 break;
 389         case RTE_FLOW_ITEM_TYPE_MPLS:
 390                 retval = sizeof(struct rte_flow_item_mpls);
 391                 break;
 392         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
 393         default:
 394                 retval = 0;
 395                 break;
 396         }
 397         return retval;
 398 }
 399
 400 #define MLX5_ENCAP_IPV4_VERSION         0x40
 401 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
 402 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
 403 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
 404 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
 405 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
 406 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
 407
 408 /**
 409  * Convert the encap action data from list of rte_flow_item to raw buffer
 410  *
 411  * @param[in] items
 412  *   Pointer to rte_flow_item objects list.
 413  * @param[out] buf
 414  *   Pointer to the output buffer.
 415  * @param[out] size
 416  *   Pointer to the output buffer size.
 417  * @param[out] error
 418  *   Pointer to the error structure.
 419  *
 420  * @return
 421  *   0 on success, a negative errno value otherwise and rte_errno is set.
 422  */
 423 static int
 424 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
 425                            size_t *size, struct rte_flow_error *error)
 426 {
 427         struct ether_hdr *eth = NULL;
 428         struct vlan_hdr *vlan = NULL;
 429         struct ipv4_hdr *ipv4 = NULL;
 430         struct ipv6_hdr *ipv6 = NULL;
 431         struct udp_hdr *udp = NULL;
 432         struct vxlan_hdr *vxlan = NULL;
 433         struct vxlan_gpe_hdr *vxlan_gpe = NULL;
 434         struct gre_hdr *gre = NULL;
 435         size_t len;
 436         size_t temp_size = 0;
 437
 438         if (!items)
 439                 return rte_flow_error_set(error, EINVAL,
 440                                           RTE_FLOW_ERROR_TYPE_ACTION,
 441                                           NULL, "invalid empty data");
 442         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 443                 len = flow_dv_get_item_len(items->type);
 444                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
 445                         return rte_flow_error_set(error, EINVAL,
 446                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 447                                                   (void *)items->type,
 448                                                   "items total size is too big"
 449                                                   " for encap action");
 450                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
 451                 switch (items->type) {
 452                 case RTE_FLOW_ITEM_TYPE_ETH:
 453                         eth = (struct ether_hdr *)&buf[temp_size];
 454                         break;
 455                 case RTE_FLOW_ITEM_TYPE_VLAN:
 456                         vlan = (struct vlan_hdr *)&buf[temp_size];
 457                         if (!eth)
 458                                 return rte_flow_error_set(error, EINVAL,
 459                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 460                                                 (void *)items->type,
 461                                                 "eth header not found");
 462                         if (!eth->ether_type)
 463                                 eth->ether_type = RTE_BE16(ETHER_TYPE_VLAN);
 464                         break;
 465                 case RTE_FLOW_ITEM_TYPE_IPV4:
 466                         ipv4 = (struct ipv4_hdr *)&buf[temp_size];
 467                         if (!vlan && !eth)
 468                                 return rte_flow_error_set(error, EINVAL,
 469                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 470                                                 (void *)items->type,
 471                                                 "neither eth nor vlan"
 472                                                 " header found");
 473                         if (vlan && !vlan->eth_proto)
 474                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv4);
 475                         else if (eth && !eth->ether_type)
 476                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv4);
 477                         if (!ipv4->version_ihl)
 478                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
 479                                                     MLX5_ENCAP_IPV4_IHL_MIN;
 480                         if (!ipv4->time_to_live)
 481                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
 482                         break;
 483                 case RTE_FLOW_ITEM_TYPE_IPV6:
 484                         ipv6 = (struct ipv6_hdr *)&buf[temp_size];
 485                         if (!vlan && !eth)
 486                                 return rte_flow_error_set(error, EINVAL,
 487                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 488                                                 (void *)items->type,
 489                                                 "neither eth nor vlan"
 490                                                 " header found");
 491                         if (vlan && !vlan->eth_proto)
 492                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv6);
 493                         else if (eth && !eth->ether_type)
 494                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv6);
 495                         if (!ipv6->vtc_flow)
 496                                 ipv6->vtc_flow =
 497                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
 498                         if (!ipv6->hop_limits)
 499                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
 500                         break;
 501                 case RTE_FLOW_ITEM_TYPE_UDP:
 502                         udp = (struct udp_hdr *)&buf[temp_size];
 503                         if (!ipv4 && !ipv6)
 504                                 return rte_flow_error_set(error, EINVAL,
 505                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 506                                                 (void *)items->type,
 507                                                 "ip header not found");
 508                         if (ipv4 && !ipv4->next_proto_id)
 509                                 ipv4->next_proto_id = IPPROTO_UDP;
 510                         else if (ipv6 && !ipv6->proto)
 511                                 ipv6->proto = IPPROTO_UDP;
 512                         break;
 513                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 514                         vxlan = (struct vxlan_hdr *)&buf[temp_size];
 515                         if (!udp)
 516                                 return rte_flow_error_set(error, EINVAL,
 517                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 518                                                 (void *)items->type,
 519                                                 "udp header not found");
 520                         if (!udp->dst_port)
 521                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
 522                         if (!vxlan->vx_flags)
 523                                 vxlan->vx_flags =
 524                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
 525                         break;
 526                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 527                         vxlan_gpe = (struct vxlan_gpe_hdr *)&buf[temp_size];
 528                         if (!udp)
 529                                 return rte_flow_error_set(error, EINVAL,
 530                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 531                                                 (void *)items->type,
 532                                                 "udp header not found");
 533                         if (!vxlan_gpe->proto)
 534                                 return rte_flow_error_set(error, EINVAL,
 535                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 536                                                 (void *)items->type,
 537                                                 "next protocol not found");
 538                         if (!udp->dst_port)
 539                                 udp->dst_port =
 540                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
 541                         if (!vxlan_gpe->vx_flags)
 542                                 vxlan_gpe->vx_flags =
 543                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
 544                         break;
 545                 case RTE_FLOW_ITEM_TYPE_GRE:
 546                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 547                         gre = (struct gre_hdr *)&buf[temp_size];
 548                         if (!gre->proto)
 549                                 return rte_flow_error_set(error, EINVAL,
 550                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 551                                                 (void *)items->type,
 552                                                 "next protocol not found");
 553                         if (!ipv4 && !ipv6)
 554                                 return rte_flow_error_set(error, EINVAL,
 555                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 556                                                 (void *)items->type,
 557                                                 "ip header not found");
 558                         if (ipv4 && !ipv4->next_proto_id)
 559                                 ipv4->next_proto_id = IPPROTO_GRE;
 560                         else if (ipv6 && !ipv6->proto)
 561                                 ipv6->proto = IPPROTO_GRE;
 562                         break;
 563                 case RTE_FLOW_ITEM_TYPE_VOID:
 564                         break;
 565                 default:
 566                         return rte_flow_error_set(error, EINVAL,
 567                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 568                                                   (void *)items->type,
 569                                                   "unsupported item type");
 570                         break;
 571                 }
 572                 temp_size += len;
 573         }
 574         *size = temp_size;
 575         return 0;
 576 }
 577
 578 /**
 579  * Convert L2 encap action to DV specification.
 580  *
 581  * @param[in] dev
 582  *   Pointer to rte_eth_dev structure.
 583  * @param[in] action
 584  *   Pointer to action structure.
 585  * @param[in, out] dev_flow
 586  *   Pointer to the mlx5_flow.
 587  * @param[out] error
 588  *   Pointer to the error structure.
 589  *
 590  * @return
 591  *   0 on success, a negative errno value otherwise and rte_errno is set.
 592  */
 593 static int
 594 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
 595                                const struct rte_flow_action *action,
 596                                struct mlx5_flow *dev_flow,
 597                                struct rte_flow_error *error)
 598 {
 599         const struct rte_flow_item *encap_data;
 600         const struct rte_flow_action_raw_encap *raw_encap_data;
 601         struct mlx5_flow_dv_encap_decap_resource res = {
 602                 .reformat_type =
 603                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
 604                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
 605         };
 606
 607         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
 608                 raw_encap_data =
 609                         (const struct rte_flow_action_raw_encap *)action->conf;
 610                 res.size = raw_encap_data->size;
 611                 memcpy(res.buf, raw_encap_data->data, res.size);
 612         } else {
 613                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
 614                         encap_data =
 615                                 ((const struct rte_flow_action_vxlan_encap *)
 616                                                 action->conf)->definition;
 617                 else
 618                         encap_data =
 619                                 ((const struct rte_flow_action_nvgre_encap *)
 620                                                 action->conf)->definition;
 621                 if (flow_dv_convert_encap_data(encap_data, res.buf,
 622                                                &res.size, error))
 623                         return -rte_errno;
 624         }
 625         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 626                 return rte_flow_error_set(error, EINVAL,
 627                                           RTE_FLOW_ERROR_TYPE_ACTION,
 628                                           NULL, "can't create L2 encap action");
 629         return 0;
 630 }
 631
 632 /**
 633  * Convert L2 decap action to DV specification.
 634  *
 635  * @param[in] dev
 636  *   Pointer to rte_eth_dev structure.
 637  * @param[in, out] dev_flow
 638  *   Pointer to the mlx5_flow.
 639  * @param[out] error
 640  *   Pointer to the error structure.
 641  *
 642  * @return
 643  *   0 on success, a negative errno value otherwise and rte_errno is set.
 644  */
 645 static int
 646 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
 647                                struct mlx5_flow *dev_flow,
 648                                struct rte_flow_error *error)
 649 {
 650         struct mlx5_flow_dv_encap_decap_resource res = {
 651                 .size = 0,
 652                 .reformat_type =
 653                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
 654                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
 655         };
 656
 657         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 658                 return rte_flow_error_set(error, EINVAL,
 659                                           RTE_FLOW_ERROR_TYPE_ACTION,
 660                                           NULL, "can't create L2 decap action");
 661         return 0;
 662 }
 663
 664 /**
 665  * Convert raw decap/encap (L3 tunnel) action to DV specification.
 666  *
 667  * @param[in] dev
 668  *   Pointer to rte_eth_dev structure.
 669  * @param[in] action
 670  *   Pointer to action structure.
 671  * @param[in, out] dev_flow
 672  *   Pointer to the mlx5_flow.
 673  * @param[in] attr
 674  *   Pointer to the flow attributes.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
 683                                 const struct rte_flow_action *action,
 684                                 struct mlx5_flow *dev_flow,
 685                                 const struct rte_flow_attr *attr,
 686                                 struct rte_flow_error *error)
 687 {
 688         const struct rte_flow_action_raw_encap *encap_data;
 689         struct mlx5_flow_dv_encap_decap_resource res;
 690
 691         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
 692         res.size = encap_data->size;
 693         memcpy(res.buf, encap_data->data, res.size);
 694         res.reformat_type = attr->egress ?
 695                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
 696                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
 697         res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
 698                                      MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
 699         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 700                 return rte_flow_error_set(error, EINVAL,
 701                                           RTE_FLOW_ERROR_TYPE_ACTION,
 702                                           NULL, "can't create encap action");
 703         return 0;
 704 }
 705
 706 /**
 707  * Verify the @p attributes will be correctly understood by the NIC and store
 708  * them in the @p flow if everything is correct.
 709  *
 710  * @param[in] dev
 711  *   Pointer to dev struct.
 712  * @param[in] attributes
 713  *   Pointer to flow attributes
 714  * @param[out] error
 715  *   Pointer to error structure.
 716  *
 717  * @return
 718  *   0 on success, a negative errno value otherwise and rte_errno is set.
 719  */
 720 static int
 721 flow_dv_validate_attributes(struct rte_eth_dev *dev,
 722                             const struct rte_flow_attr *attributes,
 723                             struct rte_flow_error *error)
 724 {
 725         struct priv *priv = dev->data->dev_private;
 726         uint32_t priority_max = priv->config.flow_prio - 1;
 727
 728         if (attributes->group)
 729                 return rte_flow_error_set(error, ENOTSUP,
 730                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
 731                                           NULL,
 732                                           "groups is not supported");
 733         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
 734             attributes->priority >= priority_max)
 735                 return rte_flow_error_set(error, ENOTSUP,
 736                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
 737                                           NULL,
 738                                           "priority out of range");
 739         if (attributes->transfer)
 740                 return rte_flow_error_set(error, ENOTSUP,
 741                                           RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
 742                                           NULL,
 743                                           "transfer is not supported");
 744         if (!(attributes->egress ^ attributes->ingress))
 745                 return rte_flow_error_set(error, ENOTSUP,
 746                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
 747                                           "must specify exactly one of "
 748                                           "ingress or egress");
 749         return 0;
 750 }
 751
 752 /**
 753  * Internal validation function. For validating both actions and items.
 754  *
 755  * @param[in] dev
 756  *   Pointer to the rte_eth_dev structure.
 757  * @param[in] attr
 758  *   Pointer to the flow attributes.
 759  * @param[in] items
 760  *   Pointer to the list of items.
 761  * @param[in] actions
 762  *   Pointer to the list of actions.
 763  * @param[out] error
 764  *   Pointer to the error structure.
 765  *
 766  * @return
 767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
 768  */
 769 static int
 770 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 771                  const struct rte_flow_item items[],
 772                  const struct rte_flow_action actions[],
 773                  struct rte_flow_error *error)
 774 {
 775         int ret;
 776         uint64_t action_flags = 0;
 777         uint64_t item_flags = 0;
 778         int tunnel = 0;
 779         uint8_t next_protocol = 0xff;
 780         int actions_n = 0;
 781
 782         if (items == NULL)
 783                 return -1;
 784         ret = flow_dv_validate_attributes(dev, attr, error);
 785         if (ret < 0)
 786                 return ret;
 787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 788                 tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
 789                 switch (items->type) {
 790                 case RTE_FLOW_ITEM_TYPE_VOID:
 791                         break;
 792                 case RTE_FLOW_ITEM_TYPE_ETH:
 793                         ret = mlx5_flow_validate_item_eth(items, item_flags,
 794                                                           error);
 795                         if (ret < 0)
 796                                 return ret;
 797                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
 798                                                MLX5_FLOW_LAYER_OUTER_L2;
 799                         break;
 800                 case RTE_FLOW_ITEM_TYPE_VLAN:
 801                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
 802                                                            error);
 803                         if (ret < 0)
 804                                 return ret;
 805                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
 806                                                MLX5_FLOW_LAYER_OUTER_VLAN;
 807                         break;
 808                 case RTE_FLOW_ITEM_TYPE_IPV4:
 809                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
 810                                                            error);
 811                         if (ret < 0)
 812                                 return ret;
 813                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
 814                                                MLX5_FLOW_LAYER_OUTER_L3_IPV4;
 815                         if (items->mask != NULL &&
 816                             ((const struct rte_flow_item_ipv4 *)
 817                              items->mask)->hdr.next_proto_id) {
 818                                 next_protocol =
 819                                         ((const struct rte_flow_item_ipv4 *)
 820                                          (items->spec))->hdr.next_proto_id;
 821                                 next_protocol &=
 822                                         ((const struct rte_flow_item_ipv4 *)
 823                                          (items->mask))->hdr.next_proto_id;
 824                         } else {
 825                                 /* Reset for inner layer. */
 826                                 next_protocol = 0xff;
 827                         }
 828                         break;
 829                 case RTE_FLOW_ITEM_TYPE_IPV6:
 830                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
 831                                                            error);
 832                         if (ret < 0)
 833                                 return ret;
 834                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
 835                                                MLX5_FLOW_LAYER_OUTER_L3_IPV6;
 836                         if (items->mask != NULL &&
 837                             ((const struct rte_flow_item_ipv6 *)
 838                              items->mask)->hdr.proto) {
 839                                 next_protocol =
 840                                         ((const struct rte_flow_item_ipv6 *)
 841                                          items->spec)->hdr.proto;
 842                                 next_protocol &=
 843                                         ((const struct rte_flow_item_ipv6 *)
 844                                          items->mask)->hdr.proto;
 845                         } else {
 846                                 /* Reset for inner layer. */
 847                                 next_protocol = 0xff;
 848                         }
 849                         break;
 850                 case RTE_FLOW_ITEM_TYPE_TCP:
 851                         ret = mlx5_flow_validate_item_tcp
 852                                                 (items, item_flags,
 853                                                  next_protocol,
 854                                                  &rte_flow_item_tcp_mask,
 855                                                  error);
 856                         if (ret < 0)
 857                                 return ret;
 858                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
 859                                                MLX5_FLOW_LAYER_OUTER_L4_TCP;
 860                         break;
 861                 case RTE_FLOW_ITEM_TYPE_UDP:
 862                         ret = mlx5_flow_validate_item_udp(items, item_flags,
 863                                                           next_protocol,
 864                                                           error);
 865                         if (ret < 0)
 866                                 return ret;
 867                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
 868                                                MLX5_FLOW_LAYER_OUTER_L4_UDP;
 869                         break;
 870                 case RTE_FLOW_ITEM_TYPE_GRE:
 871                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 872                         ret = mlx5_flow_validate_item_gre(items, item_flags,
 873                                                           next_protocol, error);
 874                         if (ret < 0)
 875                                 return ret;
 876                         item_flags |= MLX5_FLOW_LAYER_GRE;
 877                         break;
 878                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 879                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 880                                                             error);
 881                         if (ret < 0)
 882                                 return ret;
 883                         item_flags |= MLX5_FLOW_LAYER_VXLAN;
 884                         break;
 885                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 886                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
 887                                                                 item_flags, dev,
 888                                                                 error);
 889                         if (ret < 0)
 890                                 return ret;
 891                         item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
 892                         break;
 893                 case RTE_FLOW_ITEM_TYPE_META:
 894                         ret = flow_dv_validate_item_meta(dev, items, attr,
 895                                                          error);
 896                         if (ret < 0)
 897                                 return ret;
 898                         item_flags |= MLX5_FLOW_ITEM_METADATA;
 899                         break;
 900                 default:
 901                         return rte_flow_error_set(error, ENOTSUP,
 902                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 903                                                   NULL, "item not supported");
 904                 }
 905         }
 906         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
 907                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
 908                         return rte_flow_error_set(error, ENOTSUP,
 909                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 910                                                   actions, "too many actions");
 911                 switch (actions->type) {
 912                 case RTE_FLOW_ACTION_TYPE_VOID:
 913                         break;
 914                 case RTE_FLOW_ACTION_TYPE_FLAG:
 915                         ret = mlx5_flow_validate_action_flag(action_flags,
 916                                                              attr, error);
 917                         if (ret < 0)
 918                                 return ret;
 919                         action_flags |= MLX5_FLOW_ACTION_FLAG;
 920                         ++actions_n;
 921                         break;
 922                 case RTE_FLOW_ACTION_TYPE_MARK:
 923                         ret = mlx5_flow_validate_action_mark(actions,
 924                                                              action_flags,
 925                                                              attr, error);
 926                         if (ret < 0)
 927                                 return ret;
 928                         action_flags |= MLX5_FLOW_ACTION_MARK;
 929                         ++actions_n;
 930                         break;
 931                 case RTE_FLOW_ACTION_TYPE_DROP:
 932                         ret = mlx5_flow_validate_action_drop(action_flags,
 933                                                              attr, error);
 934                         if (ret < 0)
 935                                 return ret;
 936                         action_flags |= MLX5_FLOW_ACTION_DROP;
 937                         ++actions_n;
 938                         break;
 939                 case RTE_FLOW_ACTION_TYPE_QUEUE:
 940                         ret = mlx5_flow_validate_action_queue(actions,
 941                                                               action_flags, dev,
 942                                                               attr, error);
 943                         if (ret < 0)
 944                                 return ret;
 945                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
 946                         ++actions_n;
 947                         break;
 948                 case RTE_FLOW_ACTION_TYPE_RSS:
 949                         ret = mlx5_flow_validate_action_rss(actions,
 950                                                             action_flags, dev,
 951                                                             attr, error);
 952                         if (ret < 0)
 953                                 return ret;
 954                         action_flags |= MLX5_FLOW_ACTION_RSS;
 955                         ++actions_n;
 956                         break;
 957                 case RTE_FLOW_ACTION_TYPE_COUNT:
 958                         ret = mlx5_flow_validate_action_count(dev, attr, error);
 959                         if (ret < 0)
 960                                 return ret;
 961                         action_flags |= MLX5_FLOW_ACTION_COUNT;
 962                         ++actions_n;
 963                         break;
 964                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
 965                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
 966                         ret = flow_dv_validate_action_l2_encap(action_flags,
 967                                                                actions, attr,
 968                                                                error);
 969                         if (ret < 0)
 970                                 return ret;
 971                         action_flags |= actions->type ==
 972                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
 973                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
 974                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
 975                         ++actions_n;
 976                         break;
 977                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
 978                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
 979                         ret = flow_dv_validate_action_l2_decap(action_flags,
 980                                                                attr, error);
 981                         if (ret < 0)
 982                                 return ret;
 983                         action_flags |= actions->type ==
 984                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
 985                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
 986                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
 987                         ++actions_n;
 988                         break;
 989                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
 990                         ret = flow_dv_validate_action_raw_encap(action_flags,
 991                                                                 actions, attr,
 992                                                                 error);
 993                         if (ret < 0)
 994                                 return ret;
 995                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
 996                         ++actions_n;
 997                         break;
 998                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
 999                         ret = flow_dv_validate_action_raw_decap(action_flags,
1000                                                                 actions, attr,
1001                                                                 error);
1002                         if (ret < 0)
1003                                 return ret;
1004                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
1005                         ++actions_n;
1006                         break;
1007                 default:
1008                         return rte_flow_error_set(error, ENOTSUP,
1009                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1010                                                   actions,
1011                                                   "action not supported");
1012                 }
1013         }
1014         if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
1015                 return rte_flow_error_set(error, EINVAL,
1016                                           RTE_FLOW_ERROR_TYPE_ACTION, actions,
1017                                           "no fate action is found");
1018         return 0;
1019 }
1020
1021 /**
1022  * Internal preparation function. Allocates the DV flow size,
1023  * this size is constant.
1024  *
1025  * @param[in] attr
1026  *   Pointer to the flow attributes.
1027  * @param[in] items
1028  *   Pointer to the list of items.
1029  * @param[in] actions
1030  *   Pointer to the list of actions.
1031  * @param[out] error
1032  *   Pointer to the error structure.
1033  *
1034  * @return
1035  *   Pointer to mlx5_flow object on success,
1036  *   otherwise NULL and rte_ernno is set.
1037  */
1038 static struct mlx5_flow *
1039 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
1040                 const struct rte_flow_item items[] __rte_unused,
1041                 const struct rte_flow_action actions[] __rte_unused,
1042                 struct rte_flow_error *error)
1043 {
1044         uint32_t size = sizeof(struct mlx5_flow);
1045         struct mlx5_flow *flow;
1046
1047         flow = rte_calloc(__func__, 1, size, 0);
1048         if (!flow) {
1049                 rte_flow_error_set(error, ENOMEM,
1050                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1051                                    "not enough memory to create flow");
1052                 return NULL;
1053         }
1054         flow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);
1055         return flow;
1056 }
1057
1058 #ifndef NDEBUG
1059 /**
1060  * Sanity check for match mask and value. Similar to check_valid_spec() in
1061  * kernel driver. If unmasked bit is present in value, it returns failure.
1062  *
1063  * @param match_mask
1064  *   pointer to match mask buffer.
1065  * @param match_value
1066  *   pointer to match value buffer.
1067  *
1068  * @return
1069  *   0 if valid, -EINVAL otherwise.
1070  */
1071 static int
1072 flow_dv_check_valid_spec(void *match_mask, void *match_value)
1073 {
1074         uint8_t *m = match_mask;
1075         uint8_t *v = match_value;
1076         unsigned int i;
1077
1078         for (i = 0; i < MLX5_ST_SZ_DB(fte_match_param); ++i) {
1079                 if (v[i] & ~m[i]) {
1080                         DRV_LOG(ERR,
1081                                 "match_value differs from match_criteria"
1082                                 " %p[%u] != %p[%u]",
1083                                 match_value, i, match_mask, i);
1084                         return -EINVAL;
1085                 }
1086         }
1087         return 0;
1088 }
1089 #endif
1090
1091 /**
1092  * Add Ethernet item to matcher and to the value.
1093  *
1094  * @param[in, out] matcher
1095  *   Flow matcher.
1096  * @param[in, out] key
1097  *   Flow matcher value.
1098  * @param[in] item
1099  *   Flow pattern to translate.
1100  * @param[in] inner
1101  *   Item is inner pattern.
1102  */
1103 static void
1104 flow_dv_translate_item_eth(void *matcher, void *key,
1105                            const struct rte_flow_item *item, int inner)
1106 {
1107         const struct rte_flow_item_eth *eth_m = item->mask;
1108         const struct rte_flow_item_eth *eth_v = item->spec;
1109         const struct rte_flow_item_eth nic_mask = {
1110                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1111                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1112                 .type = RTE_BE16(0xffff),
1113         };
1114         void *headers_m;
1115         void *headers_v;
1116         char *l24_v;
1117         unsigned int i;
1118
1119         if (!eth_v)
1120                 return;
1121         if (!eth_m)
1122                 eth_m = &nic_mask;
1123         if (inner) {
1124                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1125                                          inner_headers);
1126                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1127         } else {
1128                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1129                                          outer_headers);
1130                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1131         }
1132         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
1133                &eth_m->dst, sizeof(eth_m->dst));
1134         /* The value must be in the range of the mask. */
1135         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
1136         for (i = 0; i < sizeof(eth_m->dst); ++i)
1137                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
1138         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
1139                &eth_m->src, sizeof(eth_m->src));
1140         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
1141         /* The value must be in the range of the mask. */
1142         for (i = 0; i < sizeof(eth_m->dst); ++i)
1143                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
1144         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
1145                  rte_be_to_cpu_16(eth_m->type));
1146         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
1147         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
1148 }
1149
1150 /**
1151  * Add VLAN item to matcher and to the value.
1152  *
1153  * @param[in, out] matcher
1154  *   Flow matcher.
1155  * @param[in, out] key
1156  *   Flow matcher value.
1157  * @param[in] item
1158  *   Flow pattern to translate.
1159  * @param[in] inner
1160  *   Item is inner pattern.
1161  */
1162 static void
1163 flow_dv_translate_item_vlan(void *matcher, void *key,
1164                             const struct rte_flow_item *item,
1165                             int inner)
1166 {
1167         const struct rte_flow_item_vlan *vlan_m = item->mask;
1168         const struct rte_flow_item_vlan *vlan_v = item->spec;
1169         const struct rte_flow_item_vlan nic_mask = {
1170                 .tci = RTE_BE16(0x0fff),
1171                 .inner_type = RTE_BE16(0xffff),
1172         };
1173         void *headers_m;
1174         void *headers_v;
1175         uint16_t tci_m;
1176         uint16_t tci_v;
1177
1178         if (!vlan_v)
1179                 return;
1180         if (!vlan_m)
1181                 vlan_m = &nic_mask;
1182         if (inner) {
1183                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1184                                          inner_headers);
1185                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1186         } else {
1187                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1188                                          outer_headers);
1189                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1190         }
1191         tci_m = rte_be_to_cpu_16(vlan_m->tci);
1192         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
1193         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
1194         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
1195         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
1196         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
1197         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
1198         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
1199         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
1200         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
1201 }
1202
1203 /**
1204  * Add IPV4 item to matcher and to the value.
1205  *
1206  * @param[in, out] matcher
1207  *   Flow matcher.
1208  * @param[in, out] key
1209  *   Flow matcher value.
1210  * @param[in] item
1211  *   Flow pattern to translate.
1212  * @param[in] inner
1213  *   Item is inner pattern.
1214  */
1215 static void
1216 flow_dv_translate_item_ipv4(void *matcher, void *key,
1217                             const struct rte_flow_item *item,
1218                             int inner)
1219 {
1220         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
1221         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
1222         const struct rte_flow_item_ipv4 nic_mask = {
1223                 .hdr = {
1224                         .src_addr = RTE_BE32(0xffffffff),
1225                         .dst_addr = RTE_BE32(0xffffffff),
1226                         .type_of_service = 0xff,
1227                         .next_proto_id = 0xff,
1228                 },
1229         };
1230         void *headers_m;
1231         void *headers_v;
1232         char *l24_m;
1233         char *l24_v;
1234         uint8_t tos;
1235
1236         if (inner) {
1237                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1238                                          inner_headers);
1239                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1240         } else {
1241                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1242                                          outer_headers);
1243                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1244         }
1245         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1246         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
1247         if (!ipv4_v)
1248                 return;
1249         if (!ipv4_m)
1250                 ipv4_m = &nic_mask;
1251         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1252                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1253         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1254                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1255         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
1256         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
1257         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1258                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1259         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1260                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1261         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
1262         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
1263         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
1264         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
1265                  ipv4_m->hdr.type_of_service);
1266         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
1267         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
1268                  ipv4_m->hdr.type_of_service >> 2);
1269         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
1270         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1271                  ipv4_m->hdr.next_proto_id);
1272         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1273                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
1274 }
1275
1276 /**
1277  * Add IPV6 item to matcher and to the value.
1278  *
1279  * @param[in, out] matcher
1280  *   Flow matcher.
1281  * @param[in, out] key
1282  *   Flow matcher value.
1283  * @param[in] item
1284  *   Flow pattern to translate.
1285  * @param[in] inner
1286  *   Item is inner pattern.
1287  */
1288 static void
1289 flow_dv_translate_item_ipv6(void *matcher, void *key,
1290                             const struct rte_flow_item *item,
1291                             int inner)
1292 {
1293         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
1294         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
1295         const struct rte_flow_item_ipv6 nic_mask = {
1296                 .hdr = {
1297                         .src_addr =
1298                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1299                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1300                         .dst_addr =
1301                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1302                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1303                         .vtc_flow = RTE_BE32(0xffffffff),
1304                         .proto = 0xff,
1305                         .hop_limits = 0xff,
1306                 },
1307         };
1308         void *headers_m;
1309         void *headers_v;
1310         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1311         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1312         char *l24_m;
1313         char *l24_v;
1314         uint32_t vtc_m;
1315         uint32_t vtc_v;
1316         int i;
1317         int size;
1318
1319         if (inner) {
1320                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1321                                          inner_headers);
1322                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1323         } else {
1324                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1325                                          outer_headers);
1326                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1327         }
1328         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1329         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
1330         if (!ipv6_v)
1331                 return;
1332         if (!ipv6_m)
1333                 ipv6_m = &nic_mask;
1334         size = sizeof(ipv6_m->hdr.dst_addr);
1335         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1336                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1337         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1338                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1339         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
1340         for (i = 0; i < size; ++i)
1341                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
1342         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1343                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1344         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1345                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1346         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
1347         for (i = 0; i < size; ++i)
1348                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
1349         /* TOS. */
1350         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
1351         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
1352         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
1353         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
1354         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
1355         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
1356         /* Label. */
1357         if (inner) {
1358                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
1359                          vtc_m);
1360                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
1361                          vtc_v);
1362         } else {
1363                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
1364                          vtc_m);
1365                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
1366                          vtc_v);
1367         }
1368         /* Protocol. */
1369         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1370                  ipv6_m->hdr.proto);
1371         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1372                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
1373 }
1374
1375 /**
1376  * Add TCP item to matcher and to the value.
1377  *
1378  * @param[in, out] matcher
1379  *   Flow matcher.
1380  * @param[in, out] key
1381  *   Flow matcher value.
1382  * @param[in] item
1383  *   Flow pattern to translate.
1384  * @param[in] inner
1385  *   Item is inner pattern.
1386  */
1387 static void
1388 flow_dv_translate_item_tcp(void *matcher, void *key,
1389                            const struct rte_flow_item *item,
1390                            int inner)
1391 {
1392         const struct rte_flow_item_tcp *tcp_m = item->mask;
1393         const struct rte_flow_item_tcp *tcp_v = item->spec;
1394         void *headers_m;
1395         void *headers_v;
1396
1397         if (inner) {
1398                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1399                                          inner_headers);
1400                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1401         } else {
1402                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1403                                          outer_headers);
1404                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1405         }
1406         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1407         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
1408         if (!tcp_v)
1409                 return;
1410         if (!tcp_m)
1411                 tcp_m = &rte_flow_item_tcp_mask;
1412         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
1413                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
1414         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1415                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
1416         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
1417                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
1418         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1419                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
1420 }
1421
1422 /**
1423  * Add UDP item to matcher and to the value.
1424  *
1425  * @param[in, out] matcher
1426  *   Flow matcher.
1427  * @param[in, out] key
1428  *   Flow matcher value.
1429  * @param[in] item
1430  *   Flow pattern to translate.
1431  * @param[in] inner
1432  *   Item is inner pattern.
1433  */
1434 static void
1435 flow_dv_translate_item_udp(void *matcher, void *key,
1436                            const struct rte_flow_item *item,
1437                            int inner)
1438 {
1439         const struct rte_flow_item_udp *udp_m = item->mask;
1440         const struct rte_flow_item_udp *udp_v = item->spec;
1441         void *headers_m;
1442         void *headers_v;
1443
1444         if (inner) {
1445                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1446                                          inner_headers);
1447                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1448         } else {
1449                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1450                                          outer_headers);
1451                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1452         }
1453         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1454         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1455         if (!udp_v)
1456                 return;
1457         if (!udp_m)
1458                 udp_m = &rte_flow_item_udp_mask;
1459         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
1460                  rte_be_to_cpu_16(udp_m->hdr.src_port));
1461         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1462                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
1463         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
1464                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
1465         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1466                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
1467 }
1468
1469 /**
1470  * Add GRE item to matcher and to the value.
1471  *
1472  * @param[in, out] matcher
1473  *   Flow matcher.
1474  * @param[in, out] key
1475  *   Flow matcher value.
1476  * @param[in] item
1477  *   Flow pattern to translate.
1478  * @param[in] inner
1479  *   Item is inner pattern.
1480  */
1481 static void
1482 flow_dv_translate_item_gre(void *matcher, void *key,
1483                            const struct rte_flow_item *item,
1484                            int inner)
1485 {
1486         const struct rte_flow_item_gre *gre_m = item->mask;
1487         const struct rte_flow_item_gre *gre_v = item->spec;
1488         void *headers_m;
1489         void *headers_v;
1490         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1491         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1492
1493         if (inner) {
1494                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1495                                          inner_headers);
1496                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1497         } else {
1498                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1499                                          outer_headers);
1500                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1501         }
1502         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1503         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
1504         if (!gre_v)
1505                 return;
1506         if (!gre_m)
1507                 gre_m = &rte_flow_item_gre_mask;
1508         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
1509                  rte_be_to_cpu_16(gre_m->protocol));
1510         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
1511                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
1512 }
1513
1514 /**
1515  * Add NVGRE item to matcher and to the value.
1516  *
1517  * @param[in, out] matcher
1518  *   Flow matcher.
1519  * @param[in, out] key
1520  *   Flow matcher value.
1521  * @param[in] item
1522  *   Flow pattern to translate.
1523  * @param[in] inner
1524  *   Item is inner pattern.
1525  */
1526 static void
1527 flow_dv_translate_item_nvgre(void *matcher, void *key,
1528                              const struct rte_flow_item *item,
1529                              int inner)
1530 {
1531         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
1532         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
1533         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1534         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1535         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
1536         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
1537         char *gre_key_m;
1538         char *gre_key_v;
1539         int size;
1540         int i;
1541
1542         flow_dv_translate_item_gre(matcher, key, item, inner);
1543         if (!nvgre_v)
1544                 return;
1545         if (!nvgre_m)
1546                 nvgre_m = &rte_flow_item_nvgre_mask;
1547         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
1548         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
1549         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
1550         memcpy(gre_key_m, tni_flow_id_m, size);
1551         for (i = 0; i < size; ++i)
1552                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
1553 }
1554
1555 /**
1556  * Add VXLAN item to matcher and to the value.
1557  *
1558  * @param[in, out] matcher
1559  *   Flow matcher.
1560  * @param[in, out] key
1561  *   Flow matcher value.
1562  * @param[in] item
1563  *   Flow pattern to translate.
1564  * @param[in] inner
1565  *   Item is inner pattern.
1566  */
1567 static void
1568 flow_dv_translate_item_vxlan(void *matcher, void *key,
1569                              const struct rte_flow_item *item,
1570                              int inner)
1571 {
1572         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
1573         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
1574         void *headers_m;
1575         void *headers_v;
1576         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1577         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1578         char *vni_m;
1579         char *vni_v;
1580         uint16_t dport;
1581         int size;
1582         int i;
1583
1584         if (inner) {
1585                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1586                                          inner_headers);
1587                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1588         } else {
1589                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1590                                          outer_headers);
1591                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1592         }
1593         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
1594                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
1595         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
1596                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
1597                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
1598         }
1599         if (!vxlan_v)
1600                 return;
1601         if (!vxlan_m)
1602                 vxlan_m = &rte_flow_item_vxlan_mask;
1603         size = sizeof(vxlan_m->vni);
1604         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
1605         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
1606         memcpy(vni_m, vxlan_m->vni, size);
1607         for (i = 0; i < size; ++i)
1608                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
1609 }
1610
1611 /**
1612  * Add META item to matcher
1613  *
1614  * @param[in, out] matcher
1615  *   Flow matcher.
1616  * @param[in, out] key
1617  *   Flow matcher value.
1618  * @param[in] item
1619  *   Flow pattern to translate.
1620  * @param[in] inner
1621  *   Item is inner pattern.
1622  */
1623 static void
1624 flow_dv_translate_item_meta(void *matcher, void *key,
1625                             const struct rte_flow_item *item)
1626 {
1627         const struct rte_flow_item_meta *meta_m;
1628         const struct rte_flow_item_meta *meta_v;
1629         void *misc2_m =
1630                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
1631         void *misc2_v =
1632                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
1633
1634         meta_m = (const void *)item->mask;
1635         if (!meta_m)
1636                 meta_m = &rte_flow_item_meta_mask;
1637         meta_v = (const void *)item->spec;
1638         if (meta_v) {
1639                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
1640                          rte_be_to_cpu_32(meta_m->data));
1641                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
1642                          rte_be_to_cpu_32(meta_v->data & meta_m->data));
1643         }
1644 }
1645
1646 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
1647
1648 #define HEADER_IS_ZERO(match_criteria, headers)                              \
1649         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
1650                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1651
1652 /**
1653  * Calculate flow matcher enable bitmap.
1654  *
1655  * @param match_criteria
1656  *   Pointer to flow matcher criteria.
1657  *
1658  * @return
1659  *   Bitmap of enabled fields.
1660  */
1661 static uint8_t
1662 flow_dv_matcher_enable(uint32_t *match_criteria)
1663 {
1664         uint8_t match_criteria_enable;
1665
1666         match_criteria_enable =
1667                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1668                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
1669         match_criteria_enable |=
1670                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1671                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
1672         match_criteria_enable |=
1673                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1674                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
1675         match_criteria_enable |=
1676                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
1677                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
1678
1679         return match_criteria_enable;
1680 }
1681
1682 /**
1683  * Register the flow matcher.
1684  *
1685  * @param dev[in, out]
1686  *   Pointer to rte_eth_dev structure.
1687  * @param[in, out] matcher
1688  *   Pointer to flow matcher.
1689  * @parm[in, out] dev_flow
1690  *   Pointer to the dev_flow.
1691  * @param[out] error
1692  *   pointer to error structure.
1693  *
1694  * @return
1695  *   0 on success otherwise -errno and errno is set.
1696  */
1697 static int
1698 flow_dv_matcher_register(struct rte_eth_dev *dev,
1699                          struct mlx5_flow_dv_matcher *matcher,
1700                          struct mlx5_flow *dev_flow,
1701                          struct rte_flow_error *error)
1702 {
1703         struct priv *priv = dev->data->dev_private;
1704         struct mlx5_flow_dv_matcher *cache_matcher;
1705         struct mlx5dv_flow_matcher_attr dv_attr = {
1706                 .type = IBV_FLOW_ATTR_NORMAL,
1707                 .match_mask = (void *)&matcher->mask,
1708         };
1709
1710         /* Lookup from cache. */
1711         LIST_FOREACH(cache_matcher, &priv->matchers, next) {
1712                 if (matcher->crc == cache_matcher->crc &&
1713                     matcher->priority == cache_matcher->priority &&
1714                     matcher->egress == cache_matcher->egress &&
1715                     !memcmp((const void *)matcher->mask.buf,
1716                             (const void *)cache_matcher->mask.buf,
1717                             cache_matcher->mask.size)) {
1718                         DRV_LOG(DEBUG,
1719                                 "priority %hd use %s matcher %p: refcnt %d++",
1720                                 cache_matcher->priority,
1721                                 cache_matcher->egress ? "tx" : "rx",
1722                                 (void *)cache_matcher,
1723                                 rte_atomic32_read(&cache_matcher->refcnt));
1724                         rte_atomic32_inc(&cache_matcher->refcnt);
1725                         dev_flow->dv.matcher = cache_matcher;
1726                         return 0;
1727                 }
1728         }
1729         /* Register new matcher. */
1730         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
1731         if (!cache_matcher)
1732                 return rte_flow_error_set(error, ENOMEM,
1733                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1734                                           "cannot allocate matcher memory");
1735         *cache_matcher = *matcher;
1736         dv_attr.match_criteria_enable =
1737                 flow_dv_matcher_enable(cache_matcher->mask.buf);
1738         dv_attr.priority = matcher->priority;
1739         if (matcher->egress)
1740                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
1741         cache_matcher->matcher_object =
1742                 mlx5_glue->dv_create_flow_matcher(priv->ctx, &dv_attr);
1743         if (!cache_matcher->matcher_object) {
1744                 rte_free(cache_matcher);
1745                 return rte_flow_error_set(error, ENOMEM,
1746                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1747                                           NULL, "cannot create matcher");
1748         }
1749         rte_atomic32_inc(&cache_matcher->refcnt);
1750         LIST_INSERT_HEAD(&priv->matchers, cache_matcher, next);
1751         dev_flow->dv.matcher = cache_matcher;
1752         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
1753                 cache_matcher->priority,
1754                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
1755                 rte_atomic32_read(&cache_matcher->refcnt));
1756         return 0;
1757 }
1758
1759 /**
1760  * Fill the flow with DV spec.
1761  *
1762  * @param[in] dev
1763  *   Pointer to rte_eth_dev structure.
1764  * @param[in, out] dev_flow
1765  *   Pointer to the sub flow.
1766  * @param[in] attr
1767  *   Pointer to the flow attributes.
1768  * @param[in] items
1769  *   Pointer to the list of items.
1770  * @param[in] actions
1771  *   Pointer to the list of actions.
1772  * @param[out] error
1773  *   Pointer to the error structure.
1774  *
1775  * @return
1776  *   0 on success, a negative errno value otherwise and rte_ernno is set.
1777  */
1778 static int
1779 flow_dv_translate(struct rte_eth_dev *dev,
1780                   struct mlx5_flow *dev_flow,
1781                   const struct rte_flow_attr *attr,
1782                   const struct rte_flow_item items[],
1783                   const struct rte_flow_action actions[],
1784                   struct rte_flow_error *error)
1785 {
1786         struct priv *priv = dev->data->dev_private;
1787         struct rte_flow *flow = dev_flow->flow;
1788         uint64_t item_flags = 0;
1789         uint64_t action_flags = 0;
1790         uint64_t priority = attr->priority;
1791         struct mlx5_flow_dv_matcher matcher = {
1792                 .mask = {
1793                         .size = sizeof(matcher.mask.buf),
1794                 },
1795         };
1796         int actions_n = 0;
1797
1798         if (priority == MLX5_FLOW_PRIO_RSVD)
1799                 priority = priv->config.flow_prio - 1;
1800         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
1801                 const struct rte_flow_action_queue *queue;
1802                 const struct rte_flow_action_rss *rss;
1803                 const struct rte_flow_action *action = actions;
1804                 const uint8_t *rss_key;
1805
1806                 switch (actions->type) {
1807                 case RTE_FLOW_ACTION_TYPE_VOID:
1808                         break;
1809                 case RTE_FLOW_ACTION_TYPE_FLAG:
1810                         dev_flow->dv.actions[actions_n].type =
1811                                 MLX5DV_FLOW_ACTION_TAG;
1812                         dev_flow->dv.actions[actions_n].tag_value =
1813                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
1814                         actions_n++;
1815                         action_flags |= MLX5_FLOW_ACTION_FLAG;
1816                         break;
1817                 case RTE_FLOW_ACTION_TYPE_MARK:
1818                         dev_flow->dv.actions[actions_n].type =
1819                                 MLX5DV_FLOW_ACTION_TAG;
1820                         dev_flow->dv.actions[actions_n].tag_value =
1821                                 mlx5_flow_mark_set
1822                                 (((const struct rte_flow_action_mark *)
1823                                   (actions->conf))->id);
1824                         actions_n++;
1825                         action_flags |= MLX5_FLOW_ACTION_MARK;
1826                         break;
1827                 case RTE_FLOW_ACTION_TYPE_DROP:
1828                         dev_flow->dv.actions[actions_n].type =
1829                                 MLX5DV_FLOW_ACTION_DROP;
1830                         action_flags |= MLX5_FLOW_ACTION_DROP;
1831                         break;
1832                 case RTE_FLOW_ACTION_TYPE_QUEUE:
1833                         queue = actions->conf;
1834                         flow->rss.queue_num = 1;
1835                         (*flow->queue)[0] = queue->index;
1836                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
1837                         break;
1838                 case RTE_FLOW_ACTION_TYPE_RSS:
1839                         rss = actions->conf;
1840                         if (flow->queue)
1841                                 memcpy((*flow->queue), rss->queue,
1842                                        rss->queue_num * sizeof(uint16_t));
1843                         flow->rss.queue_num = rss->queue_num;
1844                         /* NULL RSS key indicates default RSS key. */
1845                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
1846                         memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
1847                         /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
1848                         flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
1849                         flow->rss.level = rss->level;
1850                         action_flags |= MLX5_FLOW_ACTION_RSS;
1851                         break;
1852                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
1853                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
1854                         if (flow_dv_create_action_l2_encap(dev, actions,
1855                                                            dev_flow, error))
1856                                 return -rte_errno;
1857                         dev_flow->dv.actions[actions_n].type =
1858                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1859                         dev_flow->dv.actions[actions_n].action =
1860                                 dev_flow->dv.encap_decap->verbs_action;
1861                         actions_n++;
1862                         action_flags |= actions->type ==
1863                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
1864                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
1865                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
1866                         break;
1867                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
1868                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
1869                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
1870                                                            error))
1871                                 return -rte_errno;
1872                         dev_flow->dv.actions[actions_n].type =
1873                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1874                         dev_flow->dv.actions[actions_n].action =
1875                                 dev_flow->dv.encap_decap->verbs_action;
1876                         actions_n++;
1877                         action_flags |= actions->type ==
1878                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
1879                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
1880                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
1881                         break;
1882                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
1883                         /* Handle encap with preceding decap. */
1884                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
1885                                 if (flow_dv_create_action_raw_encap
1886                                         (dev, actions, dev_flow, attr, error))
1887                                         return -rte_errno;
1888                                 dev_flow->dv.actions[actions_n].type =
1889                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1890                                 dev_flow->dv.actions[actions_n].action =
1891                                         dev_flow->dv.encap_decap->verbs_action;
1892                         } else {
1893                                 /* Handle encap without preceding decap. */
1894                                 if (flow_dv_create_action_l2_encap(dev, actions,
1895                                                                    dev_flow,
1896                                                                    error))
1897                                         return -rte_errno;
1898                                 dev_flow->dv.actions[actions_n].type =
1899                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1900                                 dev_flow->dv.actions[actions_n].action =
1901                                         dev_flow->dv.encap_decap->verbs_action;
1902                         }
1903                         actions_n++;
1904                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
1905                         break;
1906                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
1907                         /* Check if this decap is followed by encap. */
1908                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1909                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1910                                action++) {
1911                         }
1912                         /* Handle decap only if it isn't followed by encap. */
1913                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1914                                 if (flow_dv_create_action_l2_decap(dev,
1915                                                                    dev_flow,
1916                                                                    error))
1917                                         return -rte_errno;
1918                                 dev_flow->dv.actions[actions_n].type =
1919                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1920                                 dev_flow->dv.actions[actions_n].action =
1921                                         dev_flow->dv.encap_decap->verbs_action;
1922                                 actions_n++;
1923                         }
1924                         /* If decap is followed by encap, handle it at encap. */
1925                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
1926                         break;
1927                 default:
1928                         break;
1929                 }
1930         }
1931         dev_flow->dv.actions_n = actions_n;
1932         flow->actions = action_flags;
1933         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1934                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1935                 void *match_mask = matcher.mask.buf;
1936                 void *match_value = dev_flow->dv.value.buf;
1937
1938                 switch (items->type) {
1939                 case RTE_FLOW_ITEM_TYPE_ETH:
1940                         flow_dv_translate_item_eth(match_mask, match_value,
1941                                                    items, tunnel);
1942                         matcher.priority = MLX5_PRIORITY_MAP_L2;
1943                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
1944                                                MLX5_FLOW_LAYER_OUTER_L2;
1945                         break;
1946                 case RTE_FLOW_ITEM_TYPE_VLAN:
1947                         flow_dv_translate_item_vlan(match_mask, match_value,
1948                                                     items, tunnel);
1949                         matcher.priority = MLX5_PRIORITY_MAP_L2;
1950                         item_flags |= tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
1951                                                 MLX5_FLOW_LAYER_INNER_VLAN) :
1952                                                (MLX5_FLOW_LAYER_OUTER_L2 |
1953                                                 MLX5_FLOW_LAYER_OUTER_VLAN);
1954                         break;
1955                 case RTE_FLOW_ITEM_TYPE_IPV4:
1956                         flow_dv_translate_item_ipv4(match_mask, match_value,
1957                                                     items, tunnel);
1958                         matcher.priority = MLX5_PRIORITY_MAP_L3;
1959                         dev_flow->dv.hash_fields |=
1960                                 mlx5_flow_hashfields_adjust
1961                                         (dev_flow, tunnel,
1962                                          MLX5_IPV4_LAYER_TYPES,
1963                                          MLX5_IPV4_IBV_RX_HASH);
1964                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
1965                                                MLX5_FLOW_LAYER_OUTER_L3_IPV4;
1966                         break;
1967                 case RTE_FLOW_ITEM_TYPE_IPV6:
1968                         flow_dv_translate_item_ipv6(match_mask, match_value,
1969                                                     items, tunnel);
1970                         matcher.priority = MLX5_PRIORITY_MAP_L3;
1971                         dev_flow->dv.hash_fields |=
1972                                 mlx5_flow_hashfields_adjust
1973                                         (dev_flow, tunnel,
1974                                          MLX5_IPV6_LAYER_TYPES,
1975                                          MLX5_IPV6_IBV_RX_HASH);
1976                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
1977                                                MLX5_FLOW_LAYER_OUTER_L3_IPV6;
1978                         break;
1979                 case RTE_FLOW_ITEM_TYPE_TCP:
1980                         flow_dv_translate_item_tcp(match_mask, match_value,
1981                                                    items, tunnel);
1982                         matcher.priority = MLX5_PRIORITY_MAP_L4;
1983                         dev_flow->dv.hash_fields |=
1984                                 mlx5_flow_hashfields_adjust
1985                                         (dev_flow, tunnel, ETH_RSS_TCP,
1986                                          IBV_RX_HASH_SRC_PORT_TCP |
1987                                          IBV_RX_HASH_DST_PORT_TCP);
1988                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
1989                                                MLX5_FLOW_LAYER_OUTER_L4_TCP;
1990                         break;
1991                 case RTE_FLOW_ITEM_TYPE_UDP:
1992                         flow_dv_translate_item_udp(match_mask, match_value,
1993                                                    items, tunnel);
1994                         matcher.priority = MLX5_PRIORITY_MAP_L4;
1995                         dev_flow->dv.hash_fields |=
1996                                 mlx5_flow_hashfields_adjust
1997                                         (dev_flow, tunnel, ETH_RSS_UDP,
1998                                          IBV_RX_HASH_SRC_PORT_UDP |
1999                                          IBV_RX_HASH_DST_PORT_UDP);
2000                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
2001                                                MLX5_FLOW_LAYER_OUTER_L4_UDP;
2002                         break;
2003                 case RTE_FLOW_ITEM_TYPE_GRE:
2004                         flow_dv_translate_item_gre(match_mask, match_value,
2005                                                    items, tunnel);
2006                         item_flags |= MLX5_FLOW_LAYER_GRE;
2007                         break;
2008                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2009                         flow_dv_translate_item_nvgre(match_mask, match_value,
2010                                                      items, tunnel);
2011                         item_flags |= MLX5_FLOW_LAYER_GRE;
2012                         break;
2013                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2014                         flow_dv_translate_item_vxlan(match_mask, match_value,
2015                                                      items, tunnel);
2016                         item_flags |= MLX5_FLOW_LAYER_VXLAN;
2017                         break;
2018                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2019                         flow_dv_translate_item_vxlan(match_mask, match_value,
2020                                                      items, tunnel);
2021                         item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
2022                         break;
2023                 case RTE_FLOW_ITEM_TYPE_META:
2024                         flow_dv_translate_item_meta(match_mask, match_value,
2025                                                     items);
2026                         item_flags |= MLX5_FLOW_ITEM_METADATA;
2027                         break;
2028                 default:
2029                         break;
2030                 }
2031         }
2032         assert(!flow_dv_check_valid_spec(matcher.mask.buf,
2033                                          dev_flow->dv.value.buf));
2034         dev_flow->layers = item_flags;
2035         /* Register matcher. */
2036         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
2037                                     matcher.mask.size);
2038         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
2039                                                      matcher.priority);
2040         matcher.egress = attr->egress;
2041         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
2042                 return -rte_errno;
2043         return 0;
2044 }
2045
2046 /**
2047  * Apply the flow to the NIC.
2048  *
2049  * @param[in] dev
2050  *   Pointer to the Ethernet device structure.
2051  * @param[in, out] flow
2052  *   Pointer to flow structure.
2053  * @param[out] error
2054  *   Pointer to error structure.
2055  *
2056  * @return
2057  *   0 on success, a negative errno value otherwise and rte_errno is set.
2058  */
2059 static int
2060 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
2061               struct rte_flow_error *error)
2062 {
2063         struct mlx5_flow_dv *dv;
2064         struct mlx5_flow *dev_flow;
2065         int n;
2066         int err;
2067
2068         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2069                 dv = &dev_flow->dv;
2070                 n = dv->actions_n;
2071                 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
2072                         dv->hrxq = mlx5_hrxq_drop_new(dev);
2073                         if (!dv->hrxq) {
2074                                 rte_flow_error_set
2075                                         (error, errno,
2076                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2077                                          "cannot get drop hash queue");
2078                                 goto error;
2079                         }
2080                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2081                         dv->actions[n].qp = dv->hrxq->qp;
2082                         n++;
2083                 } else if (flow->actions &
2084                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
2085                         struct mlx5_hrxq *hrxq;
2086
2087                         hrxq = mlx5_hrxq_get(dev, flow->key,
2088                                              MLX5_RSS_HASH_KEY_LEN,
2089                                              dv->hash_fields,
2090                                              (*flow->queue),
2091                                              flow->rss.queue_num);
2092                         if (!hrxq)
2093                                 hrxq = mlx5_hrxq_new
2094                                         (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
2095                                          dv->hash_fields, (*flow->queue),
2096                                          flow->rss.queue_num,
2097                                          !!(dev_flow->layers &
2098                                             MLX5_FLOW_LAYER_TUNNEL));
2099                         if (!hrxq) {
2100                                 rte_flow_error_set
2101                                         (error, rte_errno,
2102                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2103                                          "cannot get hash queue");
2104                                 goto error;
2105                         }
2106                         dv->hrxq = hrxq;
2107                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2108                         dv->actions[n].qp = hrxq->qp;
2109                         n++;
2110                 }
2111                 dv->flow =
2112                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
2113                                                   (void *)&dv->value, n,
2114                                                   dv->actions);
2115                 if (!dv->flow) {
2116                         rte_flow_error_set(error, errno,
2117                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2118                                            NULL,
2119                                            "hardware refuses to create flow");
2120                         goto error;
2121                 }
2122         }
2123         return 0;
2124 error:
2125         err = rte_errno; /* Save rte_errno before cleanup. */
2126         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2127                 struct mlx5_flow_dv *dv = &dev_flow->dv;
2128                 if (dv->hrxq) {
2129                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2130                                 mlx5_hrxq_drop_release(dev);
2131                         else
2132                                 mlx5_hrxq_release(dev, dv->hrxq);
2133                         dv->hrxq = NULL;
2134                 }
2135         }
2136         rte_errno = err; /* Restore rte_errno. */
2137         return -rte_errno;
2138 }
2139
2140 /**
2141  * Release the flow matcher.
2142  *
2143  * @param dev
2144  *   Pointer to Ethernet device.
2145  * @param flow
2146  *   Pointer to mlx5_flow.
2147  *
2148  * @return
2149  *   1 while a reference on it exists, 0 when freed.
2150  */
2151 static int
2152 flow_dv_matcher_release(struct rte_eth_dev *dev,
2153                         struct mlx5_flow *flow)
2154 {
2155         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
2156
2157         assert(matcher->matcher_object);
2158         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
2159                 dev->data->port_id, (void *)matcher,
2160                 rte_atomic32_read(&matcher->refcnt));
2161         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
2162                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
2163                            (matcher->matcher_object));
2164                 LIST_REMOVE(matcher, next);
2165                 rte_free(matcher);
2166                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
2167                         dev->data->port_id, (void *)matcher);
2168                 return 0;
2169         }
2170         return 1;
2171 }
2172
2173 /**
2174  * Release an encap/decap resource.
2175  *
2176  * @param flow
2177  *   Pointer to mlx5_flow.
2178  *
2179  * @return
2180  *   1 while a reference on it exists, 0 when freed.
2181  */
2182 static int
2183 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
2184 {
2185         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
2186                                                 flow->dv.encap_decap;
2187
2188         assert(cache_resource->verbs_action);
2189         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
2190                 (void *)cache_resource,
2191                 rte_atomic32_read(&cache_resource->refcnt));
2192         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
2193                 claim_zero(mlx5_glue->destroy_flow_action
2194                                 (cache_resource->verbs_action));
2195                 LIST_REMOVE(cache_resource, next);
2196                 rte_free(cache_resource);
2197                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
2198                         (void *)cache_resource);
2199                 return 0;
2200         }
2201         return 1;
2202 }
2203
2204 /**
2205  * Remove the flow from the NIC but keeps it in memory.
2206  *
2207  * @param[in] dev
2208  *   Pointer to Ethernet device.
2209  * @param[in, out] flow
2210  *   Pointer to flow structure.
2211  */
2212 static void
2213 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
2214 {
2215         struct mlx5_flow_dv *dv;
2216         struct mlx5_flow *dev_flow;
2217
2218         if (!flow)
2219                 return;
2220         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2221                 dv = &dev_flow->dv;
2222                 if (dv->flow) {
2223                         claim_zero(mlx5_glue->destroy_flow(dv->flow));
2224                         dv->flow = NULL;
2225                 }
2226                 if (dv->hrxq) {
2227                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2228                                 mlx5_hrxq_drop_release(dev);
2229                         else
2230                                 mlx5_hrxq_release(dev, dv->hrxq);
2231                         dv->hrxq = NULL;
2232                 }
2233         }
2234         if (flow->counter)
2235                 flow->counter = NULL;
2236 }
2237
2238 /**
2239  * Remove the flow from the NIC and the memory.
2240  *
2241  * @param[in] dev
2242  *   Pointer to the Ethernet device structure.
2243  * @param[in, out] flow
2244  *   Pointer to flow structure.
2245  */
2246 static void
2247 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
2248 {
2249         struct mlx5_flow *dev_flow;
2250
2251         if (!flow)
2252                 return;
2253         flow_dv_remove(dev, flow);
2254         while (!LIST_EMPTY(&flow->dev_flows)) {
2255                 dev_flow = LIST_FIRST(&flow->dev_flows);
2256                 LIST_REMOVE(dev_flow, next);
2257                 if (dev_flow->dv.matcher)
2258                         flow_dv_matcher_release(dev, dev_flow);
2259                 if (dev_flow->dv.encap_decap)
2260                         flow_dv_encap_decap_resource_release(dev_flow);
2261                 rte_free(dev_flow);
2262         }
2263 }
2264
2265 /**
2266  * Query a flow.
2267  *
2268  * @see rte_flow_query()
2269  * @see rte_flow_ops
2270  */
2271 static int
2272 flow_dv_query(struct rte_eth_dev *dev __rte_unused,
2273               struct rte_flow *flow __rte_unused,
2274               const struct rte_flow_action *actions __rte_unused,
2275               void *data __rte_unused,
2276               struct rte_flow_error *error __rte_unused)
2277 {
2278         rte_errno = ENOTSUP;
2279         return -rte_errno;
2280 }
2281
2282
2283 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
2284         .validate = flow_dv_validate,
2285         .prepare = flow_dv_prepare,
2286         .translate = flow_dv_translate,
2287         .apply = flow_dv_apply,
2288         .remove = flow_dv_remove,
2289         .destroy = flow_dv_destroy,
2290         .query = flow_dv_query,
2291 };
2292
2293 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */