4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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40 #include <sys/queue.h>
43 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
45 #pragma GCC diagnostic ignored "-Wpedantic"
47 #include <infiniband/verbs.h>
48 #include <infiniband/mlx5dv.h>
50 #pragma GCC diagnostic error "-Wpedantic"
54 #include <rte_malloc.h>
55 #include <rte_ethdev.h>
56 #include <rte_common.h>
57 #include <rte_interrupts.h>
58 #include <rte_debug.h>
62 #include "mlx5_rxtx.h"
63 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
67 /* Default RSS hash key also used for ConnectX-3. */
68 uint8_t rss_hash_default_key[] = {
69 0x2c, 0xc6, 0x81, 0xd1,
70 0x5b, 0xdb, 0xf4, 0xf7,
71 0xfc, 0xa2, 0x83, 0x19,
72 0xdb, 0x1a, 0x3e, 0x94,
73 0x6b, 0x9e, 0x38, 0xd9,
74 0x2c, 0x9c, 0x03, 0xd1,
75 0xad, 0x99, 0x44, 0xa7,
76 0xd9, 0x56, 0x3d, 0x59,
77 0x06, 0x3c, 0x25, 0xf3,
78 0xfc, 0x1f, 0xdc, 0x2a,
81 /* Length of the default RSS hash key. */
82 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
85 * Allocate RX queue elements.
88 * Pointer to RX queue structure.
91 * 0 on success, a negative errno value otherwise and rte_errno is set.
94 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
96 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
97 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
101 /* Iterate on segments. */
102 for (i = 0; (i != elts_n); ++i) {
103 struct rte_mbuf *buf;
105 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
107 DRV_LOG(ERR, "port %u empty mbuf pool",
108 PORT_ID(rxq_ctrl->priv));
112 /* Headroom is reserved by rte_pktmbuf_alloc(). */
113 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
114 /* Buffer is supposed to be empty. */
115 assert(rte_pktmbuf_data_len(buf) == 0);
116 assert(rte_pktmbuf_pkt_len(buf) == 0);
118 /* Only the first segment keeps headroom. */
120 SET_DATA_OFF(buf, 0);
121 PORT(buf) = rxq_ctrl->rxq.port_id;
122 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
123 PKT_LEN(buf) = DATA_LEN(buf);
125 (*rxq_ctrl->rxq.elts)[i] = buf;
127 /* If Rx vector is activated. */
128 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
129 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
130 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
133 /* Initialize default rearm_data for vPMD. */
134 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
135 rte_mbuf_refcnt_set(mbuf_init, 1);
136 mbuf_init->nb_segs = 1;
137 mbuf_init->port = rxq->port_id;
139 * prevent compiler reordering:
140 * rearm_data covers previous fields.
142 rte_compiler_barrier();
143 rxq->mbuf_initializer =
144 *(uint64_t *)&mbuf_init->rearm_data;
145 /* Padding with a fake mbuf for vectorized Rx. */
146 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
147 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
150 "port %u Rx queue %u allocated and configured %u segments"
152 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx, elts_n,
153 elts_n / (1 << rxq_ctrl->rxq.sges_n));
156 err = rte_errno; /* Save rte_errno before cleanup. */
158 for (i = 0; (i != elts_n); ++i) {
159 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
160 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
161 (*rxq_ctrl->rxq.elts)[i] = NULL;
163 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
164 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
165 rte_errno = err; /* Restore rte_errno. */
170 * Free RX queue elements.
173 * Pointer to RX queue structure.
176 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
178 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
179 const uint16_t q_n = (1 << rxq->elts_n);
180 const uint16_t q_mask = q_n - 1;
181 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
184 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
185 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
186 if (rxq->elts == NULL)
189 * Some mbuf in the Ring belongs to the application. They cannot be
192 if (mlx5_rxq_check_vec_support(rxq) > 0) {
193 for (i = 0; i < used; ++i)
194 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
195 rxq->rq_pi = rxq->rq_ci;
197 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
198 if ((*rxq->elts)[i] != NULL)
199 rte_pktmbuf_free_seg((*rxq->elts)[i]);
200 (*rxq->elts)[i] = NULL;
205 * Clean up a RX queue.
207 * Destroy objects, free allocated memory and reset the structure for reuse.
210 * Pointer to RX queue structure.
213 mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl)
215 DRV_LOG(DEBUG, "port %u cleaning up Rx queue %u",
216 PORT_ID(rxq_ctrl->priv), rxq_ctrl->idx);
218 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
219 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
225 * Pointer to Ethernet device structure.
229 * Number of descriptors to configure in queue.
231 * NUMA socket on which memory must be allocated.
233 * Thresholds parameters.
235 * Memory pool for buffer allocations.
238 * 0 on success, a negative errno value otherwise and rte_errno is set.
241 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
243 const struct rte_eth_rxconf *conf __rte_unused,
244 struct rte_mempool *mp)
246 struct priv *priv = dev->data->dev_private;
247 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
248 struct mlx5_rxq_ctrl *rxq_ctrl =
249 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
251 if (!rte_is_power_of_2(desc)) {
252 desc = 1 << log2above(desc);
254 "port %u increased number of descriptors in Rx queue %u"
255 " to the next power of two (%d)",
256 dev->data->port_id, idx, desc);
258 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
259 dev->data->port_id, idx, desc);
260 if (idx >= priv->rxqs_n) {
261 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
262 dev->data->port_id, idx, priv->rxqs_n);
263 rte_errno = EOVERFLOW;
266 if (!mlx5_rxq_releasable(dev, idx)) {
267 DRV_LOG(ERR, "port %u unable to release queue index %u",
268 dev->data->port_id, idx);
272 mlx5_rxq_release(dev, idx);
273 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, mp);
275 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
276 dev->data->port_id, idx);
280 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
281 dev->data->port_id, idx);
282 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
287 * DPDK callback to release a RX queue.
290 * Generic RX queue pointer.
293 mlx5_rx_queue_release(void *dpdk_rxq)
295 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
296 struct mlx5_rxq_ctrl *rxq_ctrl;
301 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
302 priv = rxq_ctrl->priv;
303 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx))
304 rte_panic("port %u Rx queue %u is still used by a flow and"
305 " cannot be removed\n",
306 PORT_ID(priv), rxq_ctrl->idx);
307 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.stats.idx);
311 * Allocate queue vector and fill epoll fd list for Rx interrupts.
314 * Pointer to Ethernet device.
317 * 0 on success, a negative errno value otherwise and rte_errno is set.
320 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
322 struct priv *priv = dev->data->dev_private;
324 unsigned int rxqs_n = priv->rxqs_n;
325 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
326 unsigned int count = 0;
327 struct rte_intr_handle *intr_handle = dev->intr_handle;
329 if (!dev->data->dev_conf.intr_conf.rxq)
331 mlx5_rx_intr_vec_disable(dev);
332 intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
333 if (intr_handle->intr_vec == NULL) {
335 "port %u failed to allocate memory for interrupt"
336 " vector, Rx interrupts will not be supported",
341 intr_handle->type = RTE_INTR_HANDLE_EXT;
342 for (i = 0; i != n; ++i) {
343 /* This rxq ibv must not be released in this function. */
344 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
349 /* Skip queues that cannot request interrupts. */
350 if (!rxq_ibv || !rxq_ibv->channel) {
351 /* Use invalid intr_vec[] index to disable entry. */
352 intr_handle->intr_vec[i] =
353 RTE_INTR_VEC_RXTX_OFFSET +
354 RTE_MAX_RXTX_INTR_VEC_ID;
357 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
359 "port %u too many Rx queues for interrupt"
360 " vector size (%d), Rx interrupts cannot be"
362 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
363 mlx5_rx_intr_vec_disable(dev);
367 fd = rxq_ibv->channel->fd;
368 flags = fcntl(fd, F_GETFL);
369 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
373 "port %u failed to make Rx interrupt file"
374 " descriptor %d non-blocking for queue index"
376 dev->data->port_id, fd, i);
377 mlx5_rx_intr_vec_disable(dev);
380 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
381 intr_handle->efds[count] = fd;
385 mlx5_rx_intr_vec_disable(dev);
387 intr_handle->nb_efd = count;
392 * Clean up Rx interrupts handler.
395 * Pointer to Ethernet device.
398 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
400 struct priv *priv = dev->data->dev_private;
401 struct rte_intr_handle *intr_handle = dev->intr_handle;
403 unsigned int rxqs_n = priv->rxqs_n;
404 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
406 if (!dev->data->dev_conf.intr_conf.rxq)
408 if (!intr_handle->intr_vec)
410 for (i = 0; i != n; ++i) {
411 struct mlx5_rxq_ctrl *rxq_ctrl;
412 struct mlx5_rxq_data *rxq_data;
414 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
415 RTE_MAX_RXTX_INTR_VEC_ID)
418 * Need to access directly the queue to release the reference
419 * kept in priv_rx_intr_vec_enable().
421 rxq_data = (*priv->rxqs)[i];
422 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
423 mlx5_rxq_ibv_release(rxq_ctrl->ibv);
426 rte_intr_free_epoll_fd(intr_handle);
427 if (intr_handle->intr_vec)
428 free(intr_handle->intr_vec);
429 intr_handle->nb_efd = 0;
430 intr_handle->intr_vec = NULL;
434 * MLX5 CQ notification .
437 * Pointer to receive queue structure.
439 * Sequence number per receive queue .
442 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
445 uint32_t doorbell_hi;
447 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
449 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
450 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
451 doorbell = (uint64_t)doorbell_hi << 32;
452 doorbell |= rxq->cqn;
453 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
455 rte_write64(rte_cpu_to_be_64(doorbell), cq_db_reg);
459 * DPDK callback for Rx queue interrupt enable.
462 * Pointer to Ethernet device structure.
467 * 0 on success, a negative errno value otherwise and rte_errno is set.
470 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
472 struct priv *priv = dev->data->dev_private;
473 struct mlx5_rxq_data *rxq_data;
474 struct mlx5_rxq_ctrl *rxq_ctrl;
476 rxq_data = (*priv->rxqs)[rx_queue_id];
481 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
483 struct mlx5_rxq_ibv *rxq_ibv;
485 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
490 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
491 mlx5_rxq_ibv_release(rxq_ibv);
497 * DPDK callback for Rx queue interrupt disable.
500 * Pointer to Ethernet device structure.
505 * 0 on success, a negative errno value otherwise and rte_errno is set.
508 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
510 struct priv *priv = dev->data->dev_private;
511 struct mlx5_rxq_data *rxq_data;
512 struct mlx5_rxq_ctrl *rxq_ctrl;
513 struct mlx5_rxq_ibv *rxq_ibv = NULL;
514 struct ibv_cq *ev_cq;
518 rxq_data = (*priv->rxqs)[rx_queue_id];
523 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
526 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
531 ret = ibv_get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
532 if (ret || ev_cq != rxq_ibv->cq) {
536 rxq_data->cq_arm_sn++;
537 ibv_ack_cq_events(rxq_ibv->cq, 1);
540 ret = rte_errno; /* Save rte_errno before cleanup. */
542 mlx5_rxq_ibv_release(rxq_ibv);
543 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
544 dev->data->port_id, rx_queue_id);
545 rte_errno = ret; /* Restore rte_errno. */
550 * Create the Rx queue Verbs object.
553 * Pointer to Ethernet device.
555 * Queue index in DPDK Rx queue array
558 * The Verbs object initialised, NULL otherwise and rte_errno is set.
560 struct mlx5_rxq_ibv *
561 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
563 struct priv *priv = dev->data->dev_private;
564 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
565 struct mlx5_rxq_ctrl *rxq_ctrl =
566 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
567 struct ibv_wq_attr mod;
570 struct ibv_cq_init_attr_ex ibv;
571 struct mlx5dv_cq_init_attr mlx5;
573 struct ibv_wq_init_attr wq;
574 struct ibv_cq_ex cq_attr;
576 unsigned int cqe_n = (1 << rxq_data->elts_n) - 1;
577 struct mlx5_rxq_ibv *tmpl;
578 struct mlx5dv_cq cq_info;
579 struct mlx5dv_rwq rwq;
582 struct mlx5dv_obj obj;
585 assert(!rxq_ctrl->ibv);
586 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
587 priv->verbs_alloc_ctx.obj = rxq_ctrl;
588 tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
592 "port %u Rx queue %u cannot allocate verbs resources",
593 dev->data->port_id, rxq_ctrl->idx);
597 tmpl->rxq_ctrl = rxq_ctrl;
599 tmpl->channel = ibv_create_comp_channel(priv->ctx);
600 if (!tmpl->channel) {
601 DRV_LOG(ERR, "port %u: comp channel creation failure",
607 attr.cq.ibv = (struct ibv_cq_init_attr_ex){
609 .channel = tmpl->channel,
612 attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
615 if (priv->cqe_comp && !rxq_data->hw_timestamp) {
616 attr.cq.mlx5.comp_mask |=
617 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
618 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
620 * For vectorized Rx, it must not be doubled in order to
621 * make cq_ci and rq_ci aligned.
623 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
624 attr.cq.ibv.cqe *= 2;
625 } else if (priv->cqe_comp && rxq_data->hw_timestamp) {
627 "port %u Rx CQE compression is disabled for HW"
631 tmpl->cq = ibv_cq_ex_to_cq(mlx5dv_create_cq(priv->ctx, &attr.cq.ibv,
633 if (tmpl->cq == NULL) {
634 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
635 dev->data->port_id, idx);
639 DRV_LOG(DEBUG, "port %u priv->device_attr.max_qp_wr is %d",
640 dev->data->port_id, priv->device_attr.orig_attr.max_qp_wr);
641 DRV_LOG(DEBUG, "port %u priv->device_attr.max_sge is %d",
642 dev->data->port_id, priv->device_attr.orig_attr.max_sge);
643 attr.wq = (struct ibv_wq_init_attr){
644 .wq_context = NULL, /* Could be useful in the future. */
645 .wq_type = IBV_WQT_RQ,
646 /* Max number of outstanding WRs. */
647 .max_wr = (1 << rxq_data->elts_n) >> rxq_data->sges_n,
648 /* Max number of scatter/gather elements in a WR. */
649 .max_sge = 1 << rxq_data->sges_n,
653 IBV_WQ_FLAGS_CVLAN_STRIPPING |
655 .create_flags = (rxq_data->vlan_strip ?
656 IBV_WQ_FLAGS_CVLAN_STRIPPING :
659 /* By default, FCS (CRC) is stripped by hardware. */
660 if (rxq_data->crc_present) {
661 attr.wq.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
662 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
664 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
665 if (priv->hw_padding) {
666 attr.wq.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
667 attr.wq.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
670 tmpl->wq = ibv_create_wq(priv->ctx, &attr.wq);
671 if (tmpl->wq == NULL) {
672 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
673 dev->data->port_id, idx);
678 * Make sure number of WRs*SGEs match expectations since a queue
679 * cannot allocate more than "desc" buffers.
681 if (((int)attr.wq.max_wr !=
682 ((1 << rxq_data->elts_n) >> rxq_data->sges_n)) ||
683 ((int)attr.wq.max_sge != (1 << rxq_data->sges_n))) {
685 "port %u Rx queue %u requested %u*%u but got %u*%u"
687 dev->data->port_id, idx,
688 ((1 << rxq_data->elts_n) >> rxq_data->sges_n),
689 (1 << rxq_data->sges_n),
690 attr.wq.max_wr, attr.wq.max_sge);
694 /* Change queue state to ready. */
695 mod = (struct ibv_wq_attr){
696 .attr_mask = IBV_WQ_ATTR_STATE,
697 .wq_state = IBV_WQS_RDY,
699 ret = ibv_modify_wq(tmpl->wq, &mod);
702 "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
703 dev->data->port_id, idx);
707 obj.cq.in = tmpl->cq;
708 obj.cq.out = &cq_info;
709 obj.rwq.in = tmpl->wq;
711 ret = mlx5dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
716 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
718 "port %u wrong MLX5_CQE_SIZE environment variable"
719 " value: it should be set to %u",
720 dev->data->port_id, RTE_CACHE_LINE_SIZE);
724 /* Fill the rings. */
725 rxq_data->wqes = (volatile struct mlx5_wqe_data_seg (*)[])
727 for (i = 0; (i != (unsigned int)(1 << rxq_data->elts_n)); ++i) {
728 struct rte_mbuf *buf = (*rxq_data->elts)[i];
729 volatile struct mlx5_wqe_data_seg *scat = &(*rxq_data->wqes)[i];
730 uintptr_t addr = rte_pktmbuf_mtod(buf, uintptr_t);
732 /* scat->addr must be able to store a pointer. */
733 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
734 *scat = (struct mlx5_wqe_data_seg){
735 .addr = rte_cpu_to_be_64(addr),
736 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
737 .lkey = mlx5_rx_mb2mr(rxq_data, buf)
740 rxq_data->rq_db = rwq.dbrec;
741 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
745 rxq_data->zip = (struct rxq_zip){
748 rxq_data->cq_db = cq_info.dbrec;
749 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
750 rxq_data->cq_uar = cq_info.cq_uar;
751 rxq_data->cqn = cq_info.cqn;
752 rxq_data->cq_arm_sn = 0;
753 /* Update doorbell counter. */
754 rxq_data->rq_ci = (1 << rxq_data->elts_n) >> rxq_data->sges_n;
756 *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
757 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
759 rte_atomic32_inc(&tmpl->refcnt);
760 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
761 dev->data->port_id, idx, rte_atomic32_read(&tmpl->refcnt));
762 LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
763 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
766 ret = rte_errno; /* Save rte_errno before cleanup. */
768 claim_zero(ibv_destroy_wq(tmpl->wq));
770 claim_zero(ibv_destroy_cq(tmpl->cq));
772 claim_zero(ibv_destroy_comp_channel(tmpl->channel));
773 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
774 rte_errno = ret; /* Restore rte_errno. */
779 * Get an Rx queue Verbs object.
782 * Pointer to Ethernet device.
784 * Queue index in DPDK Rx queue array
787 * The Verbs object if it exists.
789 struct mlx5_rxq_ibv *
790 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
792 struct priv *priv = dev->data->dev_private;
793 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
794 struct mlx5_rxq_ctrl *rxq_ctrl;
796 if (idx >= priv->rxqs_n)
800 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
802 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
803 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
804 dev->data->port_id, rxq_ctrl->idx,
805 rte_atomic32_read(&rxq_ctrl->ibv->refcnt));
807 return rxq_ctrl->ibv;
811 * Release an Rx verbs queue object.
814 * Verbs Rx queue object.
817 * 1 while a reference on it exists, 0 when freed.
820 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
825 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u: refcnt %d",
826 PORT_ID(rxq_ibv->rxq_ctrl->priv),
827 rxq_ibv->rxq_ctrl->idx, rte_atomic32_read(&rxq_ibv->refcnt));
828 if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
829 rxq_free_elts(rxq_ibv->rxq_ctrl);
830 claim_zero(ibv_destroy_wq(rxq_ibv->wq));
831 claim_zero(ibv_destroy_cq(rxq_ibv->cq));
832 if (rxq_ibv->channel)
833 claim_zero(ibv_destroy_comp_channel(rxq_ibv->channel));
834 LIST_REMOVE(rxq_ibv, next);
842 * Verify the Verbs Rx queue list is empty
845 * Pointer to Ethernet device.
848 * The number of object not released.
851 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
853 struct priv *priv = dev->data->dev_private;
855 struct mlx5_rxq_ibv *rxq_ibv;
857 LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
858 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
859 dev->data->port_id, rxq_ibv->rxq_ctrl->idx);
866 * Return true if a single reference exists on the object.
869 * Verbs Rx queue object.
872 mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv)
875 return (rte_atomic32_read(&rxq_ibv->refcnt) == 1);
879 * Create a DPDK Rx queue.
882 * Pointer to Ethernet device.
886 * Number of descriptors to configure in queue.
888 * NUMA socket on which memory must be allocated.
891 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
893 struct mlx5_rxq_ctrl *
894 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
895 unsigned int socket, struct rte_mempool *mp)
897 struct priv *priv = dev->data->dev_private;
898 struct mlx5_rxq_ctrl *tmpl;
899 const uint16_t desc_n =
900 desc + priv->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
901 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
902 const unsigned int mr_n = MR_TABLE_SZ(priv->mr_n);
904 tmpl = rte_calloc_socket("RXQ", 1,
906 desc_n * sizeof(struct rte_mbuf *) +
907 mr_n * sizeof(struct mlx5_mr_cache),
913 tmpl->socket = socket;
914 if (dev->data->dev_conf.intr_conf.rxq)
916 /* Enable scattered packets support for this queue if necessary. */
917 assert(mb_len >= RTE_PKTMBUF_HEADROOM);
918 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
919 (mb_len - RTE_PKTMBUF_HEADROOM)) {
920 tmpl->rxq.sges_n = 0;
921 } else if (dev->data->dev_conf.rxmode.enable_scatter) {
923 RTE_PKTMBUF_HEADROOM +
924 dev->data->dev_conf.rxmode.max_rx_pkt_len;
928 * Determine the number of SGEs needed for a full packet
929 * and round it to the next power of two.
931 sges_n = log2above((size / mb_len) + !!(size % mb_len));
932 tmpl->rxq.sges_n = sges_n;
933 /* Make sure rxq.sges_n did not overflow. */
934 size = mb_len * (1 << tmpl->rxq.sges_n);
935 size -= RTE_PKTMBUF_HEADROOM;
936 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
938 "port %u too many SGEs (%u) needed to handle"
939 " requested maximum packet size %u",
942 dev->data->dev_conf.rxmode.max_rx_pkt_len);
943 rte_errno = EOVERFLOW;
948 "port %u the requested maximum Rx packet size (%u) is"
949 " larger than a single mbuf (%u) and scattered mode has"
950 " not been requested",
952 dev->data->dev_conf.rxmode.max_rx_pkt_len,
953 mb_len - RTE_PKTMBUF_HEADROOM);
955 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
956 dev->data->port_id, 1 << tmpl->rxq.sges_n);
957 if (desc % (1 << tmpl->rxq.sges_n)) {
959 "port %u number of Rx queue descriptors (%u) is not a"
960 " multiple of SGEs per packet (%u)",
963 1 << tmpl->rxq.sges_n);
967 /* Toggle RX checksum offload if hardware supports it. */
969 tmpl->rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
970 if (priv->hw_csum_l2tun)
971 tmpl->rxq.csum_l2tun =
972 !!dev->data->dev_conf.rxmode.hw_ip_checksum;
973 tmpl->rxq.hw_timestamp =
974 !!dev->data->dev_conf.rxmode.hw_timestamp;
975 /* Configure VLAN stripping. */
976 tmpl->rxq.vlan_strip = (priv->hw_vlan_strip &&
977 !!dev->data->dev_conf.rxmode.hw_vlan_strip);
978 /* By default, FCS (CRC) is stripped by hardware. */
979 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
980 tmpl->rxq.crc_present = 0;
981 } else if (priv->hw_fcs_strip) {
982 tmpl->rxq.crc_present = 1;
985 "port %u CRC stripping has been disabled but will"
986 " still be performed by hardware, make sure MLNX_OFED"
987 " and firmware are up to date",
989 tmpl->rxq.crc_present = 0;
992 "port %u CRC stripping is %s, %u bytes will be subtracted from"
993 " incoming frames to hide it",
995 tmpl->rxq.crc_present ? "disabled" : "enabled",
996 tmpl->rxq.crc_present << 2);
998 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
999 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1000 tmpl->rxq.port_id = dev->data->port_id;
1003 tmpl->rxq.stats.idx = idx;
1004 tmpl->rxq.elts_n = log2above(desc);
1005 tmpl->rxq.rq_repl_thresh =
1006 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1008 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1009 tmpl->rxq.mr_ctrl.cache_bh =
1010 (struct mlx5_mr_cache (*)[mr_n])&(*tmpl->rxq.elts)[desc_n];
1011 tmpl->rxq.mr_ctrl.bh_n =
1012 mlx5_mr_update_mp(dev, *tmpl->rxq.mr_ctrl.cache_bh,
1013 tmpl->rxq.mr_ctrl.bh_n, mp);
1014 DRV_LOG(DEBUG, "Rx MR lookup table: %u entires built",
1015 MR_N(tmpl->rxq.mr_ctrl.bh_n));
1017 rte_atomic32_inc(&tmpl->refcnt);
1018 DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d", dev->data->port_id,
1019 idx, rte_atomic32_read(&tmpl->refcnt));
1020 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1031 * Pointer to Ethernet device.
1036 * A pointer to the queue if it exists, NULL otherwise.
1038 struct mlx5_rxq_ctrl *
1039 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1041 struct priv *priv = dev->data->dev_private;
1042 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1044 if ((*priv->rxqs)[idx]) {
1045 rxq_ctrl = container_of((*priv->rxqs)[idx],
1046 struct mlx5_rxq_ctrl,
1048 mlx5_rxq_ibv_get(dev, idx);
1049 rte_atomic32_inc(&rxq_ctrl->refcnt);
1050 DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d",
1051 dev->data->port_id, rxq_ctrl->idx,
1052 rte_atomic32_read(&rxq_ctrl->refcnt));
1058 * Release a Rx queue.
1061 * Pointer to Ethernet device.
1066 * 1 while a reference on it exists, 0 when freed.
1069 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1071 struct priv *priv = dev->data->dev_private;
1072 struct mlx5_rxq_ctrl *rxq_ctrl;
1074 if (!(*priv->rxqs)[idx])
1076 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1077 assert(rxq_ctrl->priv);
1078 if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1079 rxq_ctrl->ibv = NULL;
1080 DRV_LOG(DEBUG, "port %u Rx queue %u: refcnt %d", dev->data->port_id,
1081 rxq_ctrl->idx, rte_atomic32_read(&rxq_ctrl->refcnt));
1082 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1083 LIST_REMOVE(rxq_ctrl, next);
1085 (*priv->rxqs)[idx] = NULL;
1092 * Verify if the queue can be released.
1095 * Pointer to Ethernet device.
1100 * 1 if the queue can be released, negative errno otherwise and rte_errno is
1104 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
1106 struct priv *priv = dev->data->dev_private;
1107 struct mlx5_rxq_ctrl *rxq_ctrl;
1109 if (!(*priv->rxqs)[idx]) {
1113 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1114 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
1118 * Verify the Rx Queue list is empty
1121 * Pointer to Ethernet device.
1124 * The number of object not released.
1127 mlx5_rxq_verify(struct rte_eth_dev *dev)
1129 struct priv *priv = dev->data->dev_private;
1130 struct mlx5_rxq_ctrl *rxq_ctrl;
1133 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1134 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1135 dev->data->port_id, rxq_ctrl->idx);
1142 * Create an indirection table.
1145 * Pointer to Ethernet device.
1147 * Queues entering in the indirection table.
1149 * Number of queues in the array.
1152 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1154 struct mlx5_ind_table_ibv *
1155 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, uint16_t queues[],
1158 struct priv *priv = dev->data->dev_private;
1159 struct mlx5_ind_table_ibv *ind_tbl;
1160 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1161 log2above(queues_n) :
1162 log2above(priv->ind_table_max_size);
1163 struct ibv_wq *wq[1 << wq_n];
1167 ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1168 queues_n * sizeof(uint16_t), 0);
1173 for (i = 0; i != queues_n; ++i) {
1174 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1178 wq[i] = rxq->ibv->wq;
1179 ind_tbl->queues[i] = queues[i];
1181 ind_tbl->queues_n = queues_n;
1182 /* Finalise indirection table. */
1183 for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1185 ind_tbl->ind_table = ibv_create_rwq_ind_table(
1187 &(struct ibv_rwq_ind_table_init_attr){
1188 .log_ind_tbl_size = wq_n,
1192 if (!ind_tbl->ind_table) {
1196 rte_atomic32_inc(&ind_tbl->refcnt);
1197 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1198 DRV_LOG(DEBUG, "port %u indirection table %p: refcnt %d",
1199 dev->data->port_id, (void *)ind_tbl,
1200 rte_atomic32_read(&ind_tbl->refcnt));
1204 DRV_LOG(DEBUG, "port %u cannot create indirection table",
1205 dev->data->port_id);
1210 * Get an indirection table.
1213 * Pointer to Ethernet device.
1215 * Queues entering in the indirection table.
1217 * Number of queues in the array.
1220 * An indirection table if found.
1222 struct mlx5_ind_table_ibv *
1223 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, uint16_t queues[],
1226 struct priv *priv = dev->data->dev_private;
1227 struct mlx5_ind_table_ibv *ind_tbl;
1229 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1230 if ((ind_tbl->queues_n == queues_n) &&
1231 (memcmp(ind_tbl->queues, queues,
1232 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1239 rte_atomic32_inc(&ind_tbl->refcnt);
1240 DRV_LOG(DEBUG, "port %u indirection table %p: refcnt %d",
1241 dev->data->port_id, (void *)ind_tbl,
1242 rte_atomic32_read(&ind_tbl->refcnt));
1243 for (i = 0; i != ind_tbl->queues_n; ++i)
1244 mlx5_rxq_get(dev, ind_tbl->queues[i]);
1250 * Release an indirection table.
1253 * Pointer to Ethernet device.
1255 * Indirection table to release.
1258 * 1 while a reference on it exists, 0 when freed.
1261 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1262 struct mlx5_ind_table_ibv *ind_tbl)
1266 DRV_LOG(DEBUG, "port %u indirection table %p: refcnt %d",
1267 dev->data->port_id, (void *)ind_tbl,
1268 rte_atomic32_read(&ind_tbl->refcnt));
1269 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1270 claim_zero(ibv_destroy_rwq_ind_table(ind_tbl->ind_table));
1271 for (i = 0; i != ind_tbl->queues_n; ++i)
1272 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1273 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1274 LIST_REMOVE(ind_tbl, next);
1282 * Verify the Rx Queue list is empty
1285 * Pointer to Ethernet device.
1288 * The number of object not released.
1291 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1293 struct priv *priv = dev->data->dev_private;
1294 struct mlx5_ind_table_ibv *ind_tbl;
1297 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1299 "port %u Verbs indirection table %p still referenced",
1300 dev->data->port_id, (void *)ind_tbl);
1307 * Create an Rx Hash queue.
1310 * Pointer to Ethernet device.
1312 * RSS key for the Rx hash queue.
1313 * @param rss_key_len
1315 * @param hash_fields
1316 * Verbs protocol hash field to make the RSS on.
1318 * Queues entering in hash queue. In case of empty hash_fields only the
1319 * first queue index will be taken for the indirection table.
1324 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1327 mlx5_hrxq_new(struct rte_eth_dev *dev, uint8_t *rss_key, uint8_t rss_key_len,
1328 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1330 struct priv *priv = dev->data->dev_private;
1331 struct mlx5_hrxq *hrxq;
1332 struct mlx5_ind_table_ibv *ind_tbl;
1336 queues_n = hash_fields ? queues_n : 1;
1337 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1339 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1344 qp = ibv_create_qp_ex(
1346 &(struct ibv_qp_init_attr_ex){
1347 .qp_type = IBV_QPT_RAW_PACKET,
1349 IBV_QP_INIT_ATTR_PD |
1350 IBV_QP_INIT_ATTR_IND_TABLE |
1351 IBV_QP_INIT_ATTR_RX_HASH,
1352 .rx_hash_conf = (struct ibv_rx_hash_conf){
1353 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1354 .rx_hash_key_len = rss_key_len,
1355 .rx_hash_key = rss_key,
1356 .rx_hash_fields_mask = hash_fields,
1358 .rwq_ind_tbl = ind_tbl->ind_table,
1365 hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1368 hrxq->ind_table = ind_tbl;
1370 hrxq->rss_key_len = rss_key_len;
1371 hrxq->hash_fields = hash_fields;
1372 memcpy(hrxq->rss_key, rss_key, rss_key_len);
1373 rte_atomic32_inc(&hrxq->refcnt);
1374 LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1375 DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1376 dev->data->port_id, (void *)hrxq,
1377 rte_atomic32_read(&hrxq->refcnt));
1380 err = rte_errno; /* Save rte_errno before cleanup. */
1381 mlx5_ind_table_ibv_release(dev, ind_tbl);
1383 claim_zero(ibv_destroy_qp(qp));
1384 rte_errno = err; /* Restore rte_errno. */
1389 * Get an Rx Hash queue.
1392 * Pointer to Ethernet device.
1394 * RSS configuration for the Rx hash queue.
1396 * Queues entering in hash queue. In case of empty hash_fields only the
1397 * first queue index will be taken for the indirection table.
1402 * An hash Rx queue on success.
1405 mlx5_hrxq_get(struct rte_eth_dev *dev, uint8_t *rss_key, uint8_t rss_key_len,
1406 uint64_t hash_fields, uint16_t queues[], uint16_t queues_n)
1408 struct priv *priv = dev->data->dev_private;
1409 struct mlx5_hrxq *hrxq;
1411 queues_n = hash_fields ? queues_n : 1;
1412 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1413 struct mlx5_ind_table_ibv *ind_tbl;
1415 if (hrxq->rss_key_len != rss_key_len)
1417 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1419 if (hrxq->hash_fields != hash_fields)
1421 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1424 if (ind_tbl != hrxq->ind_table) {
1425 mlx5_ind_table_ibv_release(dev, ind_tbl);
1428 rte_atomic32_inc(&hrxq->refcnt);
1429 DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1430 dev->data->port_id, (void *)hrxq,
1431 rte_atomic32_read(&hrxq->refcnt));
1438 * Release the hash Rx queue.
1441 * Pointer to Ethernet device.
1443 * Pointer to Hash Rx queue to release.
1446 * 1 while a reference on it exists, 0 when freed.
1449 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1451 DRV_LOG(DEBUG, "port %u hash Rx queue %p: refcnt %d",
1452 dev->data->port_id, (void *)hrxq,
1453 rte_atomic32_read(&hrxq->refcnt));
1454 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1455 claim_zero(ibv_destroy_qp(hrxq->qp));
1456 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1457 LIST_REMOVE(hrxq, next);
1461 claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1466 * Verify the Rx Queue list is empty
1469 * Pointer to Ethernet device.
1472 * The number of object not released.
1475 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1477 struct priv *priv = dev->data->dev_private;
1478 struct mlx5_hrxq *hrxq;
1481 LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1483 "port %u Verbs hash Rx queue %p still referenced",
1484 dev->data->port_id, (void *)hrxq);