drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_TCP;
 119         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_TCP;
 121         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_TCP;
 125         /* UDP */
 126         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_UDP;
 128         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_UDP;
 130         /* Repeat with outer_l3_type being set. Just in case. */
 131         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_NONFRAG;
 133         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_NONFRAG;
 135         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_FRAG;
 137         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_FRAG;
 139         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 140                      RTE_PTYPE_L4_TCP;
 141         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 142                      RTE_PTYPE_L4_TCP;
 143         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_L4_TCP;
 145         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 146                      RTE_PTYPE_L4_TCP;
 147         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_L4_TCP;
 149         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_L4_TCP;
 151         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_L4_UDP;
 153         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_L4_UDP;
 155         /* Tunneled - L3 */
 156         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_NONFRAG;
 159         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_NONFRAG;
 162         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_NONFRAG;
 165         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L4_NONFRAG;
 168         /* Tunneled - Fragmented */
 169         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_FRAG;
 172         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_FRAG;
 175         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_FRAG;
 178         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_FRAG;
 181         /* Tunneled - TCP */
 182         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_TCP;
 185         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_TCP;
 188         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_TCP;
 191         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_TCP;
 194         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_TCP;
 197         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_TCP;
 200         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_TCP;
 203         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_TCP;
 206         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_TCP;
 209         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_TCP;
 212         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 213                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L4_TCP;
 215         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 216                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 217                      RTE_PTYPE_INNER_L4_TCP;
 218         /* Tunneled - UDP */
 219         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 220                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 221                      RTE_PTYPE_INNER_L4_UDP;
 222         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 224                      RTE_PTYPE_INNER_L4_UDP;
 225         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 226                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 227                      RTE_PTYPE_INNER_L4_UDP;
 228         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 229                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 230                      RTE_PTYPE_INNER_L4_UDP;
 231 }
 232
 233 /**
 234  * Return the size of tailroom of WQ.
 235  *
 236  * @param txq
 237  *   Pointer to TX queue structure.
 238  * @param addr
 239  *   Pointer to tail of WQ.
 240  *
 241  * @return
 242  *   Size of tailroom.
 243  */
 244 static inline size_t
 245 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 246 {
 247         size_t tailroom;
 248         tailroom = (uintptr_t)(txq->wqes) +
 249                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 250                    (uintptr_t)addr;
 251         return tailroom;
 252 }
 253
 254 /**
 255  * Copy data to tailroom of circular queue.
 256  *
 257  * @param dst
 258  *   Pointer to destination.
 259  * @param src
 260  *   Pointer to source.
 261  * @param n
 262  *   Number of bytes to copy.
 263  * @param base
 264  *   Pointer to head of queue.
 265  * @param tailroom
 266  *   Size of tailroom from dst.
 267  *
 268  * @return
 269  *   Pointer after copied data.
 270  */
 271 static inline void *
 272 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 273                 void *base, size_t tailroom)
 274 {
 275         void *ret;
 276
 277         if (n > tailroom) {
 278                 rte_memcpy(dst, src, tailroom);
 279                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 280                            n - tailroom);
 281                 ret = (uint8_t *)base + n - tailroom;
 282         } else {
 283                 rte_memcpy(dst, src, n);
 284                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 285         }
 286         return ret;
 287 }
 288
 289 /**
 290  * DPDK callback to check the status of a tx descriptor.
 291  *
 292  * @param tx_queue
 293  *   The tx queue.
 294  * @param[in] offset
 295  *   The index of the descriptor in the ring.
 296  *
 297  * @return
 298  *   The status of the tx descriptor.
 299  */
 300 int
 301 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 302 {
 303         struct mlx5_txq_data *txq = tx_queue;
 304         uint16_t used;
 305
 306         mlx5_tx_complete(txq);
 307         used = txq->elts_head - txq->elts_tail;
 308         if (offset < used)
 309                 return RTE_ETH_TX_DESC_FULL;
 310         return RTE_ETH_TX_DESC_DONE;
 311 }
 312
 313 /**
 314  * DPDK callback to check the status of a rx descriptor.
 315  *
 316  * @param rx_queue
 317  *   The rx queue.
 318  * @param[in] offset
 319  *   The index of the descriptor in the ring.
 320  *
 321  * @return
 322  *   The status of the tx descriptor.
 323  */
 324 int
 325 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 326 {
 327         struct mlx5_rxq_data *rxq = rx_queue;
 328         struct rxq_zip *zip = &rxq->zip;
 329         volatile struct mlx5_cqe *cqe;
 330         const unsigned int cqe_n = (1 << rxq->cqe_n);
 331         const unsigned int cqe_cnt = cqe_n - 1;
 332         unsigned int cq_ci;
 333         unsigned int used;
 334
 335         /* if we are processing a compressed cqe */
 336         if (zip->ai) {
 337                 used = zip->cqe_cnt - zip->ca;
 338                 cq_ci = zip->cq_ci;
 339         } else {
 340                 used = 0;
 341                 cq_ci = rxq->cq_ci;
 342         }
 343         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 344         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 345                 int8_t op_own;
 346                 unsigned int n;
 347
 348                 op_own = cqe->op_own;
 349                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 350                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 351                 else
 352                         n = 1;
 353                 cq_ci += n;
 354                 used += n;
 355                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 356         }
 357         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 358         if (offset < used)
 359                 return RTE_ETH_RX_DESC_DONE;
 360         return RTE_ETH_RX_DESC_AVAIL;
 361 }
 362
 363 /**
 364  * DPDK callback for TX.
 365  *
 366  * @param dpdk_txq
 367  *   Generic pointer to TX queue structure.
 368  * @param[in] pkts
 369  *   Packets to transmit.
 370  * @param pkts_n
 371  *   Number of packets in array.
 372  *
 373  * @return
 374  *   Number of packets successfully transmitted (<= pkts_n).
 375  */
 376 uint16_t
 377 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 378 {
 379         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 380         uint16_t elts_head = txq->elts_head;
 381         const uint16_t elts_n = 1 << txq->elts_n;
 382         const uint16_t elts_m = elts_n - 1;
 383         unsigned int i = 0;
 384         unsigned int j = 0;
 385         unsigned int k = 0;
 386         uint16_t max_elts;
 387         unsigned int max_inline = txq->max_inline;
 388         const unsigned int inline_en = !!max_inline && txq->inline_en;
 389         uint16_t max_wqe;
 390         unsigned int comp;
 391         volatile struct mlx5_wqe_v *wqe = NULL;
 392         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 393         unsigned int segs_n = 0;
 394         struct rte_mbuf *buf = NULL;
 395         uint8_t *raw;
 396
 397         if (unlikely(!pkts_n))
 398                 return 0;
 399         /* Prefetch first packet cacheline. */
 400         rte_prefetch0(*pkts);
 401         /* Start processing. */
 402         mlx5_tx_complete(txq);
 403         max_elts = (elts_n - (elts_head - txq->elts_tail));
 404         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 405         if (unlikely(!max_wqe))
 406                 return 0;
 407         do {
 408                 volatile rte_v128u32_t *dseg = NULL;
 409                 uint32_t length;
 410                 unsigned int ds = 0;
 411                 unsigned int sg = 0; /* counter of additional segs attached. */
 412                 uintptr_t addr;
 413                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 414                 uint16_t tso_header_sz = 0;
 415                 uint16_t ehdr;
 416                 uint8_t cs_flags;
 417                 uint64_t tso = 0;
 418                 uint16_t tso_segsz = 0;
 419 #ifdef MLX5_PMD_SOFT_COUNTERS
 420                 uint32_t total_length = 0;
 421 #endif
 422
 423                 /* first_seg */
 424                 buf = *pkts;
 425                 segs_n = buf->nb_segs;
 426                 /*
 427                  * Make sure there is enough room to store this packet and
 428                  * that one ring entry remains unused.
 429                  */
 430                 assert(segs_n);
 431                 if (max_elts < segs_n)
 432                         break;
 433                 max_elts -= segs_n;
 434                 --segs_n;
 435                 if (unlikely(--max_wqe == 0))
 436                         break;
 437                 wqe = (volatile struct mlx5_wqe_v *)
 438                         tx_mlx5_wqe(txq, txq->wqe_ci);
 439                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 440                 if (pkts_n - i > 1)
 441                         rte_prefetch0(*(pkts + 1));
 442                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 443                 length = DATA_LEN(buf);
 444                 ehdr = (((uint8_t *)addr)[1] << 8) |
 445                        ((uint8_t *)addr)[0];
 446 #ifdef MLX5_PMD_SOFT_COUNTERS
 447                 total_length = length;
 448 #endif
 449                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 450                         txq->stats.oerrors++;
 451                         break;
 452                 }
 453                 /* Update element. */
 454                 (*txq->elts)[elts_head & elts_m] = buf;
 455                 /* Prefetch next buffer data. */
 456                 if (pkts_n - i > 1)
 457                         rte_prefetch0(
 458                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 459                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 460                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 461                 /* Replace the Ethernet type by the VLAN if necessary. */
 462                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 463                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 464                                                          buf->vlan_tci);
 465                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 466
 467                         addr += 2;
 468                         length -= 2;
 469                         /* Copy Destination and source mac address. */
 470                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 471                         /* Copy VLAN. */
 472                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 473                         /* Copy missing two bytes to end the DSeg. */
 474                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 475                                ((uint8_t *)addr) + len, 2);
 476                         addr += len + 2;
 477                         length -= (len + 2);
 478                 } else {
 479                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 480                                MLX5_WQE_DWORD_SIZE);
 481                         length -= pkt_inline_sz;
 482                         addr += pkt_inline_sz;
 483                 }
 484                 raw += MLX5_WQE_DWORD_SIZE;
 485                 if (txq->tso_en) {
 486                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 487                         if (tso) {
 488                                 uintptr_t end = (uintptr_t)
 489                                                 (((uintptr_t)txq->wqes) +
 490                                                 (1 << txq->wqe_n) *
 491                                                 MLX5_WQE_SIZE);
 492                                 unsigned int copy_b;
 493                                 uint8_t vlan_sz = (buf->ol_flags &
 494                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 495                                 const uint64_t is_tunneled =
 496                                                         buf->ol_flags &
 497                                                         (PKT_TX_TUNNEL_GRE |
 498                                                          PKT_TX_TUNNEL_VXLAN);
 499
 500                                 tso_header_sz = buf->l2_len + vlan_sz +
 501                                                 buf->l3_len + buf->l4_len;
 502                                 tso_segsz = buf->tso_segsz;
 503                                 if (unlikely(tso_segsz == 0)) {
 504                                         txq->stats.oerrors++;
 505                                         break;
 506                                 }
 507                                 if (is_tunneled && txq->tunnel_en) {
 508                                         tso_header_sz += buf->outer_l2_len +
 509                                                          buf->outer_l3_len;
 510                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 511                                 } else {
 512                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 513                                 }
 514                                 if (unlikely(tso_header_sz >
 515                                              MLX5_MAX_TSO_HEADER)) {
 516                                         txq->stats.oerrors++;
 517                                         break;
 518                                 }
 519                                 copy_b = tso_header_sz - pkt_inline_sz;
 520                                 /* First seg must contain all headers. */
 521                                 assert(copy_b <= length);
 522                                 if (copy_b &&
 523                                    ((end - (uintptr_t)raw) > copy_b)) {
 524                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 525                                                       1 + 3) / 4;
 526
 527                                         if (unlikely(max_wqe < n))
 528                                                 break;
 529                                         max_wqe -= n;
 530                                         rte_memcpy((void *)raw,
 531                                                    (void *)addr, copy_b);
 532                                         addr += copy_b;
 533                                         length -= copy_b;
 534                                         /* Include padding for TSO header. */
 535                                         copy_b = MLX5_WQE_DS(copy_b) *
 536                                                  MLX5_WQE_DWORD_SIZE;
 537                                         pkt_inline_sz += copy_b;
 538                                         raw += copy_b;
 539                                 } else {
 540                                         /* NOP WQE. */
 541                                         wqe->ctrl = (rte_v128u32_t){
 542                                                      rte_cpu_to_be_32(
 543                                                         txq->wqe_ci << 8),
 544                                                      rte_cpu_to_be_32(
 545                                                         txq->qp_num_8s | 1),
 546                                                      0,
 547                                                      0,
 548                                         };
 549                                         ds = 1;
 550 #ifdef MLX5_PMD_SOFT_COUNTERS
 551                                         total_length = 0;
 552 #endif
 553                                         k++;
 554                                         goto next_wqe;
 555                                 }
 556                         }
 557                 }
 558                 /* Inline if enough room. */
 559                 if (inline_en || tso) {
 560                         uint32_t inl;
 561                         uintptr_t end = (uintptr_t)
 562                                 (((uintptr_t)txq->wqes) +
 563                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 564                         unsigned int inline_room = max_inline *
 565                                                    RTE_CACHE_LINE_SIZE -
 566                                                    (pkt_inline_sz - 2) -
 567                                                    !!tso * sizeof(inl);
 568                         uintptr_t addr_end = (addr + inline_room) &
 569                                              ~(RTE_CACHE_LINE_SIZE - 1);
 570                         unsigned int copy_b = (addr_end > addr) ?
 571                                 RTE_MIN((addr_end - addr), length) :
 572                                 0;
 573
 574                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 575                                 /*
 576                                  * One Dseg remains in the current WQE.  To
 577                                  * keep the computation positive, it is
 578                                  * removed after the bytes to Dseg conversion.
 579                                  */
 580                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 581
 582                                 if (unlikely(max_wqe < n))
 583                                         break;
 584                                 max_wqe -= n;
 585                                 if (tso) {
 586                                         inl = rte_cpu_to_be_32(copy_b |
 587                                                                MLX5_INLINE_SEG);
 588                                         rte_memcpy((void *)raw,
 589                                                    (void *)&inl, sizeof(inl));
 590                                         raw += sizeof(inl);
 591                                         pkt_inline_sz += sizeof(inl);
 592                                 }
 593                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 594                                 addr += copy_b;
 595                                 length -= copy_b;
 596                                 pkt_inline_sz += copy_b;
 597                         }
 598                         /*
 599                          * 2 DWORDs consumed by the WQE header + ETH segment +
 600                          * the size of the inline part of the packet.
 601                          */
 602                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 603                         if (length > 0) {
 604                                 if (ds % (MLX5_WQE_SIZE /
 605                                           MLX5_WQE_DWORD_SIZE) == 0) {
 606                                         if (unlikely(--max_wqe == 0))
 607                                                 break;
 608                                         dseg = (volatile rte_v128u32_t *)
 609                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 610                                                            ds / 4);
 611                                 } else {
 612                                         dseg = (volatile rte_v128u32_t *)
 613                                                 ((uintptr_t)wqe +
 614                                                  (ds * MLX5_WQE_DWORD_SIZE));
 615                                 }
 616                                 goto use_dseg;
 617                         } else if (!segs_n) {
 618                                 goto next_pkt;
 619                         } else {
 620                                 /* dseg will be advance as part of next_seg */
 621                                 dseg = (volatile rte_v128u32_t *)
 622                                         ((uintptr_t)wqe +
 623                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 624                                 goto next_seg;
 625                         }
 626                 } else {
 627                         /*
 628                          * No inline has been done in the packet, only the
 629                          * Ethernet Header as been stored.
 630                          */
 631                         dseg = (volatile rte_v128u32_t *)
 632                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 633                         ds = 3;
 634 use_dseg:
 635                         /* Add the remaining packet as a simple ds. */
 636                         addr = rte_cpu_to_be_64(addr);
 637                         *dseg = (rte_v128u32_t){
 638                                 rte_cpu_to_be_32(length),
 639                                 mlx5_tx_mb2mr(txq, buf),
 640                                 addr,
 641                                 addr >> 32,
 642                         };
 643                         ++ds;
 644                         if (!segs_n)
 645                                 goto next_pkt;
 646                 }
 647 next_seg:
 648                 assert(buf);
 649                 assert(ds);
 650                 assert(wqe);
 651                 /*
 652                  * Spill on next WQE when the current one does not have
 653                  * enough room left. Size of WQE must a be a multiple
 654                  * of data segment size.
 655                  */
 656                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 657                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 658                         if (unlikely(--max_wqe == 0))
 659                                 break;
 660                         dseg = (volatile rte_v128u32_t *)
 661                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 662                         rte_prefetch0(tx_mlx5_wqe(txq,
 663                                                   txq->wqe_ci + ds / 4 + 1));
 664                 } else {
 665                         ++dseg;
 666                 }
 667                 ++ds;
 668                 buf = buf->next;
 669                 assert(buf);
 670                 length = DATA_LEN(buf);
 671 #ifdef MLX5_PMD_SOFT_COUNTERS
 672                 total_length += length;
 673 #endif
 674                 /* Store segment information. */
 675                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 676                 *dseg = (rte_v128u32_t){
 677                         rte_cpu_to_be_32(length),
 678                         mlx5_tx_mb2mr(txq, buf),
 679                         addr,
 680                         addr >> 32,
 681                 };
 682                 (*txq->elts)[++elts_head & elts_m] = buf;
 683                 ++sg;
 684                 /* Advance counter only if all segs are successfully posted. */
 685                 if (sg < segs_n)
 686                         goto next_seg;
 687                 else
 688                         j += sg;
 689 next_pkt:
 690                 if (ds > MLX5_DSEG_MAX) {
 691                         txq->stats.oerrors++;
 692                         break;
 693                 }
 694                 ++elts_head;
 695                 ++pkts;
 696                 ++i;
 697                 /* Initialize known and common part of the WQE structure. */
 698                 if (tso) {
 699                         wqe->ctrl = (rte_v128u32_t){
 700                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 701                                                  MLX5_OPCODE_TSO),
 702                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 703                                 0,
 704                                 0,
 705                         };
 706                         wqe->eseg = (rte_v128u32_t){
 707                                 0,
 708                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 709                                 0,
 710                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 711                         };
 712                 } else {
 713                         wqe->ctrl = (rte_v128u32_t){
 714                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 715                                                  MLX5_OPCODE_SEND),
 716                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 717                                 0,
 718                                 0,
 719                         };
 720                         wqe->eseg = (rte_v128u32_t){
 721                                 0,
 722                                 cs_flags,
 723                                 0,
 724                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 725                         };
 726                 }
 727 next_wqe:
 728                 txq->wqe_ci += (ds + 3) / 4;
 729                 /* Save the last successful WQE for completion request */
 730                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 731 #ifdef MLX5_PMD_SOFT_COUNTERS
 732                 /* Increment sent bytes counter. */
 733                 txq->stats.obytes += total_length;
 734 #endif
 735         } while (i < pkts_n);
 736         /* Take a shortcut if nothing must be sent. */
 737         if (unlikely((i + k) == 0))
 738                 return 0;
 739         txq->elts_head += (i + j);
 740         /* Check whether completion threshold has been reached. */
 741         comp = txq->elts_comp + i + j + k;
 742         if (comp >= MLX5_TX_COMP_THRESH) {
 743                 /* A CQE slot must always be available. */
 744                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
 745                 /* Request completion on last WQE. */
 746                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 747                 /* Save elts_head in unused "immediate" field of WQE. */
 748                 last_wqe->ctrl3 = txq->elts_head;
 749                 txq->elts_comp = 0;
 750         } else {
 751                 txq->elts_comp = comp;
 752         }
 753 #ifdef MLX5_PMD_SOFT_COUNTERS
 754         /* Increment sent packets counter. */
 755         txq->stats.opackets += i;
 756 #endif
 757         /* Ring QP doorbell. */
 758         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 759         return i;
 760 }
 761
 762 /**
 763  * Open a MPW session.
 764  *
 765  * @param txq
 766  *   Pointer to TX queue structure.
 767  * @param mpw
 768  *   Pointer to MPW session structure.
 769  * @param length
 770  *   Packet length.
 771  */
 772 static inline void
 773 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 774 {
 775         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 776         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 777                 (volatile struct mlx5_wqe_data_seg (*)[])
 778                 tx_mlx5_wqe(txq, idx + 1);
 779
 780         mpw->state = MLX5_MPW_STATE_OPENED;
 781         mpw->pkts_n = 0;
 782         mpw->len = length;
 783         mpw->total_len = 0;
 784         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 785         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 786         mpw->wqe->eseg.inline_hdr_sz = 0;
 787         mpw->wqe->eseg.rsvd0 = 0;
 788         mpw->wqe->eseg.rsvd1 = 0;
 789         mpw->wqe->eseg.rsvd2 = 0;
 790         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 791                                              (txq->wqe_ci << 8) |
 792                                              MLX5_OPCODE_TSO);
 793         mpw->wqe->ctrl[2] = 0;
 794         mpw->wqe->ctrl[3] = 0;
 795         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 796                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 797         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 798                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 799         mpw->data.dseg[2] = &(*dseg)[0];
 800         mpw->data.dseg[3] = &(*dseg)[1];
 801         mpw->data.dseg[4] = &(*dseg)[2];
 802 }
 803
 804 /**
 805  * Close a MPW session.
 806  *
 807  * @param txq
 808  *   Pointer to TX queue structure.
 809  * @param mpw
 810  *   Pointer to MPW session structure.
 811  */
 812 static inline void
 813 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 814 {
 815         unsigned int num = mpw->pkts_n;
 816
 817         /*
 818          * Store size in multiple of 16 bytes. Control and Ethernet segments
 819          * count as 2.
 820          */
 821         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 822         mpw->state = MLX5_MPW_STATE_CLOSED;
 823         if (num < 3)
 824                 ++txq->wqe_ci;
 825         else
 826                 txq->wqe_ci += 2;
 827         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 828         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 829 }
 830
 831 /**
 832  * DPDK callback for TX with MPW support.
 833  *
 834  * @param dpdk_txq
 835  *   Generic pointer to TX queue structure.
 836  * @param[in] pkts
 837  *   Packets to transmit.
 838  * @param pkts_n
 839  *   Number of packets in array.
 840  *
 841  * @return
 842  *   Number of packets successfully transmitted (<= pkts_n).
 843  */
 844 uint16_t
 845 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 846 {
 847         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 848         uint16_t elts_head = txq->elts_head;
 849         const uint16_t elts_n = 1 << txq->elts_n;
 850         const uint16_t elts_m = elts_n - 1;
 851         unsigned int i = 0;
 852         unsigned int j = 0;
 853         uint16_t max_elts;
 854         uint16_t max_wqe;
 855         unsigned int comp;
 856         struct mlx5_mpw mpw = {
 857                 .state = MLX5_MPW_STATE_CLOSED,
 858         };
 859
 860         if (unlikely(!pkts_n))
 861                 return 0;
 862         /* Prefetch first packet cacheline. */
 863         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 864         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 865         /* Start processing. */
 866         mlx5_tx_complete(txq);
 867         max_elts = (elts_n - (elts_head - txq->elts_tail));
 868         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 869         if (unlikely(!max_wqe))
 870                 return 0;
 871         do {
 872                 struct rte_mbuf *buf = *(pkts++);
 873                 uint32_t length;
 874                 unsigned int segs_n = buf->nb_segs;
 875                 uint32_t cs_flags;
 876
 877                 /*
 878                  * Make sure there is enough room to store this packet and
 879                  * that one ring entry remains unused.
 880                  */
 881                 assert(segs_n);
 882                 if (max_elts < segs_n)
 883                         break;
 884                 /* Do not bother with large packets MPW cannot handle. */
 885                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 886                         txq->stats.oerrors++;
 887                         break;
 888                 }
 889                 max_elts -= segs_n;
 890                 --pkts_n;
 891                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 892                 /* Retrieve packet information. */
 893                 length = PKT_LEN(buf);
 894                 assert(length);
 895                 /* Start new session if packet differs. */
 896                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 897                     ((mpw.len != length) ||
 898                      (segs_n != 1) ||
 899                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 900                         mlx5_mpw_close(txq, &mpw);
 901                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 902                         /*
 903                          * Multi-Packet WQE consumes at most two WQE.
 904                          * mlx5_mpw_new() expects to be able to use such
 905                          * resources.
 906                          */
 907                         if (unlikely(max_wqe < 2))
 908                                 break;
 909                         max_wqe -= 2;
 910                         mlx5_mpw_new(txq, &mpw, length);
 911                         mpw.wqe->eseg.cs_flags = cs_flags;
 912                 }
 913                 /* Multi-segment packets must be alone in their MPW. */
 914                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 915 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 916                 length = 0;
 917 #endif
 918                 do {
 919                         volatile struct mlx5_wqe_data_seg *dseg;
 920                         uintptr_t addr;
 921
 922                         assert(buf);
 923                         (*txq->elts)[elts_head++ & elts_m] = buf;
 924                         dseg = mpw.data.dseg[mpw.pkts_n];
 925                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 926                         *dseg = (struct mlx5_wqe_data_seg){
 927                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 928                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 929                                 .addr = rte_cpu_to_be_64(addr),
 930                         };
 931 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 932                         length += DATA_LEN(buf);
 933 #endif
 934                         buf = buf->next;
 935                         ++mpw.pkts_n;
 936                         ++j;
 937                 } while (--segs_n);
 938                 assert(length == mpw.len);
 939                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 940                         mlx5_mpw_close(txq, &mpw);
 941 #ifdef MLX5_PMD_SOFT_COUNTERS
 942                 /* Increment sent bytes counter. */
 943                 txq->stats.obytes += length;
 944 #endif
 945                 ++i;
 946         } while (pkts_n);
 947         /* Take a shortcut if nothing must be sent. */
 948         if (unlikely(i == 0))
 949                 return 0;
 950         /* Check whether completion threshold has been reached. */
 951         /* "j" includes both packets and segments. */
 952         comp = txq->elts_comp + j;
 953         if (comp >= MLX5_TX_COMP_THRESH) {
 954                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 955
 956                 /* A CQE slot must always be available. */
 957                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
 958                 /* Request completion on last WQE. */
 959                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 960                 /* Save elts_head in unused "immediate" field of WQE. */
 961                 wqe->ctrl[3] = elts_head;
 962                 txq->elts_comp = 0;
 963         } else {
 964                 txq->elts_comp = comp;
 965         }
 966 #ifdef MLX5_PMD_SOFT_COUNTERS
 967         /* Increment sent packets counter. */
 968         txq->stats.opackets += i;
 969 #endif
 970         /* Ring QP doorbell. */
 971         if (mpw.state == MLX5_MPW_STATE_OPENED)
 972                 mlx5_mpw_close(txq, &mpw);
 973         mlx5_tx_dbrec(txq, mpw.wqe);
 974         txq->elts_head = elts_head;
 975         return i;
 976 }
 977
 978 /**
 979  * Open a MPW inline session.
 980  *
 981  * @param txq
 982  *   Pointer to TX queue structure.
 983  * @param mpw
 984  *   Pointer to MPW session structure.
 985  * @param length
 986  *   Packet length.
 987  */
 988 static inline void
 989 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 990                     uint32_t length)
 991 {
 992         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 993         struct mlx5_wqe_inl_small *inl;
 994
 995         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 996         mpw->pkts_n = 0;
 997         mpw->len = length;
 998         mpw->total_len = 0;
 999         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1000         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1001                                              (txq->wqe_ci << 8) |
1002                                              MLX5_OPCODE_TSO);
1003         mpw->wqe->ctrl[2] = 0;
1004         mpw->wqe->ctrl[3] = 0;
1005         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1006         mpw->wqe->eseg.inline_hdr_sz = 0;
1007         mpw->wqe->eseg.cs_flags = 0;
1008         mpw->wqe->eseg.rsvd0 = 0;
1009         mpw->wqe->eseg.rsvd1 = 0;
1010         mpw->wqe->eseg.rsvd2 = 0;
1011         inl = (struct mlx5_wqe_inl_small *)
1012                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1013         mpw->data.raw = (uint8_t *)&inl->raw;
1014 }
1015
1016 /**
1017  * Close a MPW inline session.
1018  *
1019  * @param txq
1020  *   Pointer to TX queue structure.
1021  * @param mpw
1022  *   Pointer to MPW session structure.
1023  */
1024 static inline void
1025 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1026 {
1027         unsigned int size;
1028         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1029                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1030
1031         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1032         /*
1033          * Store size in multiple of 16 bytes. Control and Ethernet segments
1034          * count as 2.
1035          */
1036         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1037                                              MLX5_WQE_DS(size));
1038         mpw->state = MLX5_MPW_STATE_CLOSED;
1039         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1040         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1041 }
1042
1043 /**
1044  * DPDK callback for TX with MPW inline support.
1045  *
1046  * @param dpdk_txq
1047  *   Generic pointer to TX queue structure.
1048  * @param[in] pkts
1049  *   Packets to transmit.
1050  * @param pkts_n
1051  *   Number of packets in array.
1052  *
1053  * @return
1054  *   Number of packets successfully transmitted (<= pkts_n).
1055  */
1056 uint16_t
1057 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1058                          uint16_t pkts_n)
1059 {
1060         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1061         uint16_t elts_head = txq->elts_head;
1062         const uint16_t elts_n = 1 << txq->elts_n;
1063         const uint16_t elts_m = elts_n - 1;
1064         unsigned int i = 0;
1065         unsigned int j = 0;
1066         uint16_t max_elts;
1067         uint16_t max_wqe;
1068         unsigned int comp;
1069         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1070         struct mlx5_mpw mpw = {
1071                 .state = MLX5_MPW_STATE_CLOSED,
1072         };
1073         /*
1074          * Compute the maximum number of WQE which can be consumed by inline
1075          * code.
1076          * - 2 DSEG for:
1077          *   - 1 control segment,
1078          *   - 1 Ethernet segment,
1079          * - N Dseg from the inline request.
1080          */
1081         const unsigned int wqe_inl_n =
1082                 ((2 * MLX5_WQE_DWORD_SIZE +
1083                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1084                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1085
1086         if (unlikely(!pkts_n))
1087                 return 0;
1088         /* Prefetch first packet cacheline. */
1089         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1090         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1091         /* Start processing. */
1092         mlx5_tx_complete(txq);
1093         max_elts = (elts_n - (elts_head - txq->elts_tail));
1094         do {
1095                 struct rte_mbuf *buf = *(pkts++);
1096                 uintptr_t addr;
1097                 uint32_t length;
1098                 unsigned int segs_n = buf->nb_segs;
1099                 uint8_t cs_flags;
1100
1101                 /*
1102                  * Make sure there is enough room to store this packet and
1103                  * that one ring entry remains unused.
1104                  */
1105                 assert(segs_n);
1106                 if (max_elts < segs_n)
1107                         break;
1108                 /* Do not bother with large packets MPW cannot handle. */
1109                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1110                         txq->stats.oerrors++;
1111                         break;
1112                 }
1113                 max_elts -= segs_n;
1114                 --pkts_n;
1115                 /*
1116                  * Compute max_wqe in case less WQE were consumed in previous
1117                  * iteration.
1118                  */
1119                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1120                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1121                 /* Retrieve packet information. */
1122                 length = PKT_LEN(buf);
1123                 /* Start new session if packet differs. */
1124                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1125                         if ((mpw.len != length) ||
1126                             (segs_n != 1) ||
1127                             (mpw.wqe->eseg.cs_flags != cs_flags))
1128                                 mlx5_mpw_close(txq, &mpw);
1129                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1130                         if ((mpw.len != length) ||
1131                             (segs_n != 1) ||
1132                             (length > inline_room) ||
1133                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1134                                 mlx5_mpw_inline_close(txq, &mpw);
1135                                 inline_room =
1136                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1137                         }
1138                 }
1139                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1140                         if ((segs_n != 1) ||
1141                             (length > inline_room)) {
1142                                 /*
1143                                  * Multi-Packet WQE consumes at most two WQE.
1144                                  * mlx5_mpw_new() expects to be able to use
1145                                  * such resources.
1146                                  */
1147                                 if (unlikely(max_wqe < 2))
1148                                         break;
1149                                 max_wqe -= 2;
1150                                 mlx5_mpw_new(txq, &mpw, length);
1151                                 mpw.wqe->eseg.cs_flags = cs_flags;
1152                         } else {
1153                                 if (unlikely(max_wqe < wqe_inl_n))
1154                                         break;
1155                                 max_wqe -= wqe_inl_n;
1156                                 mlx5_mpw_inline_new(txq, &mpw, length);
1157                                 mpw.wqe->eseg.cs_flags = cs_flags;
1158                         }
1159                 }
1160                 /* Multi-segment packets must be alone in their MPW. */
1161                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1162                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1163                         assert(inline_room ==
1164                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1165 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1166                         length = 0;
1167 #endif
1168                         do {
1169                                 volatile struct mlx5_wqe_data_seg *dseg;
1170
1171                                 assert(buf);
1172                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1173                                 dseg = mpw.data.dseg[mpw.pkts_n];
1174                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1175                                 *dseg = (struct mlx5_wqe_data_seg){
1176                                         .byte_count =
1177                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1178                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1179                                         .addr = rte_cpu_to_be_64(addr),
1180                                 };
1181 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1182                                 length += DATA_LEN(buf);
1183 #endif
1184                                 buf = buf->next;
1185                                 ++mpw.pkts_n;
1186                                 ++j;
1187                         } while (--segs_n);
1188                         assert(length == mpw.len);
1189                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1190                                 mlx5_mpw_close(txq, &mpw);
1191                 } else {
1192                         unsigned int max;
1193
1194                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1195                         assert(length <= inline_room);
1196                         assert(length == DATA_LEN(buf));
1197                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1198                         (*txq->elts)[elts_head++ & elts_m] = buf;
1199                         /* Maximum number of bytes before wrapping. */
1200                         max = ((((uintptr_t)(txq->wqes)) +
1201                                 (1 << txq->wqe_n) *
1202                                 MLX5_WQE_SIZE) -
1203                                (uintptr_t)mpw.data.raw);
1204                         if (length > max) {
1205                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1206                                            (void *)addr,
1207                                            max);
1208                                 mpw.data.raw = (volatile void *)txq->wqes;
1209                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1210                                            (void *)(addr + max),
1211                                            length - max);
1212                                 mpw.data.raw += length - max;
1213                         } else {
1214                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1215                                            (void *)addr,
1216                                            length);
1217
1218                                 if (length == max)
1219                                         mpw.data.raw =
1220                                                 (volatile void *)txq->wqes;
1221                                 else
1222                                         mpw.data.raw += length;
1223                         }
1224                         ++mpw.pkts_n;
1225                         mpw.total_len += length;
1226                         ++j;
1227                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1228                                 mlx5_mpw_inline_close(txq, &mpw);
1229                                 inline_room =
1230                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1231                         } else {
1232                                 inline_room -= length;
1233                         }
1234                 }
1235 #ifdef MLX5_PMD_SOFT_COUNTERS
1236                 /* Increment sent bytes counter. */
1237                 txq->stats.obytes += length;
1238 #endif
1239                 ++i;
1240         } while (pkts_n);
1241         /* Take a shortcut if nothing must be sent. */
1242         if (unlikely(i == 0))
1243                 return 0;
1244         /* Check whether completion threshold has been reached. */
1245         /* "j" includes both packets and segments. */
1246         comp = txq->elts_comp + j;
1247         if (comp >= MLX5_TX_COMP_THRESH) {
1248                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1249
1250                 /* A CQE slot must always be available. */
1251                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1252                 /* Request completion on last WQE. */
1253                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1254                 /* Save elts_head in unused "immediate" field of WQE. */
1255                 wqe->ctrl[3] = elts_head;
1256                 txq->elts_comp = 0;
1257         } else {
1258                 txq->elts_comp = comp;
1259         }
1260 #ifdef MLX5_PMD_SOFT_COUNTERS
1261         /* Increment sent packets counter. */
1262         txq->stats.opackets += i;
1263 #endif
1264         /* Ring QP doorbell. */
1265         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1266                 mlx5_mpw_inline_close(txq, &mpw);
1267         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1268                 mlx5_mpw_close(txq, &mpw);
1269         mlx5_tx_dbrec(txq, mpw.wqe);
1270         txq->elts_head = elts_head;
1271         return i;
1272 }
1273
1274 /**
1275  * Open an Enhanced MPW session.
1276  *
1277  * @param txq
1278  *   Pointer to TX queue structure.
1279  * @param mpw
1280  *   Pointer to MPW session structure.
1281  * @param length
1282  *   Packet length.
1283  */
1284 static inline void
1285 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1286 {
1287         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1288
1289         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1290         mpw->pkts_n = 0;
1291         mpw->total_len = sizeof(struct mlx5_wqe);
1292         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1293         mpw->wqe->ctrl[0] =
1294                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1295                                  (txq->wqe_ci << 8) |
1296                                  MLX5_OPCODE_ENHANCED_MPSW);
1297         mpw->wqe->ctrl[2] = 0;
1298         mpw->wqe->ctrl[3] = 0;
1299         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1300         if (unlikely(padding)) {
1301                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1302
1303                 /* Pad the first 2 DWORDs with zero-length inline header. */
1304                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1305                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1306                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1307                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1308                 /* Start from the next WQEBB. */
1309                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1310         } else {
1311                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1312         }
1313 }
1314
1315 /**
1316  * Close an Enhanced MPW session.
1317  *
1318  * @param txq
1319  *   Pointer to TX queue structure.
1320  * @param mpw
1321  *   Pointer to MPW session structure.
1322  *
1323  * @return
1324  *   Number of consumed WQEs.
1325  */
1326 static inline uint16_t
1327 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1328 {
1329         uint16_t ret;
1330
1331         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1332          * count as 2.
1333          */
1334         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1335                                              MLX5_WQE_DS(mpw->total_len));
1336         mpw->state = MLX5_MPW_STATE_CLOSED;
1337         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1338         txq->wqe_ci += ret;
1339         return ret;
1340 }
1341
1342 /**
1343  * DPDK callback for TX with Enhanced MPW support.
1344  *
1345  * @param dpdk_txq
1346  *   Generic pointer to TX queue structure.
1347  * @param[in] pkts
1348  *   Packets to transmit.
1349  * @param pkts_n
1350  *   Number of packets in array.
1351  *
1352  * @return
1353  *   Number of packets successfully transmitted (<= pkts_n).
1354  */
1355 uint16_t
1356 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1357 {
1358         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1359         uint16_t elts_head = txq->elts_head;
1360         const uint16_t elts_n = 1 << txq->elts_n;
1361         const uint16_t elts_m = elts_n - 1;
1362         unsigned int i = 0;
1363         unsigned int j = 0;
1364         uint16_t max_elts;
1365         uint16_t max_wqe;
1366         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1367         unsigned int mpw_room = 0;
1368         unsigned int inl_pad = 0;
1369         uint32_t inl_hdr;
1370         struct mlx5_mpw mpw = {
1371                 .state = MLX5_MPW_STATE_CLOSED,
1372         };
1373
1374         if (unlikely(!pkts_n))
1375                 return 0;
1376         /* Start processing. */
1377         mlx5_tx_complete(txq);
1378         max_elts = (elts_n - (elts_head - txq->elts_tail));
1379         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1380         if (unlikely(!max_wqe))
1381                 return 0;
1382         do {
1383                 struct rte_mbuf *buf = *(pkts++);
1384                 uintptr_t addr;
1385                 unsigned int do_inline = 0; /* Whether inline is possible. */
1386                 uint32_t length;
1387                 unsigned int segs_n = buf->nb_segs;
1388                 uint8_t cs_flags;
1389
1390                 /*
1391                  * Make sure there is enough room to store this packet and
1392                  * that one ring entry remains unused.
1393                  */
1394                 assert(segs_n);
1395                 if (max_elts - j < segs_n)
1396                         break;
1397                 /* Do not bother with large packets MPW cannot handle. */
1398                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1399                         txq->stats.oerrors++;
1400                         break;
1401                 }
1402                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1403                 /* Retrieve packet information. */
1404                 length = PKT_LEN(buf);
1405                 /* Start new session if:
1406                  * - multi-segment packet
1407                  * - no space left even for a dseg
1408                  * - next packet can be inlined with a new WQE
1409                  * - cs_flag differs
1410                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1411                  * segmented packet.
1412                  */
1413                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1414                         if ((segs_n != 1) ||
1415                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1416                               mpw_room) ||
1417                             (length <= txq->inline_max_packet_sz &&
1418                              inl_pad + sizeof(inl_hdr) + length >
1419                               mpw_room) ||
1420                             (mpw.wqe->eseg.cs_flags != cs_flags))
1421                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1422                 }
1423                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1424                         if (unlikely(segs_n != 1)) {
1425                                 /* Fall back to legacy MPW.
1426                                  * A MPW session consumes 2 WQEs at most to
1427                                  * include MLX5_MPW_DSEG_MAX pointers.
1428                                  */
1429                                 if (unlikely(max_wqe < 2))
1430                                         break;
1431                                 mlx5_mpw_new(txq, &mpw, length);
1432                         } else {
1433                                 /* In Enhanced MPW, inline as much as the budget
1434                                  * is allowed. The remaining space is to be
1435                                  * filled with dsegs. If the title WQEBB isn't
1436                                  * padded, it will have 2 dsegs there.
1437                                  */
1438                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1439                                             (max_inline ? max_inline :
1440                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1441                                             MLX5_WQE_SIZE);
1442                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1443                                               mpw_room))
1444                                         break;
1445                                 /* Don't pad the title WQEBB to not waste WQ. */
1446                                 mlx5_empw_new(txq, &mpw, 0);
1447                                 mpw_room -= mpw.total_len;
1448                                 inl_pad = 0;
1449                                 do_inline =
1450                                         length <= txq->inline_max_packet_sz &&
1451                                         sizeof(inl_hdr) + length <= mpw_room &&
1452                                         !txq->mpw_hdr_dseg;
1453                         }
1454                         mpw.wqe->eseg.cs_flags = cs_flags;
1455                 } else {
1456                         /* Evaluate whether the next packet can be inlined.
1457                          * Inlininig is possible when:
1458                          * - length is less than configured value
1459                          * - length fits for remaining space
1460                          * - not required to fill the title WQEBB with dsegs
1461                          */
1462                         do_inline =
1463                                 length <= txq->inline_max_packet_sz &&
1464                                 inl_pad + sizeof(inl_hdr) + length <=
1465                                  mpw_room &&
1466                                 (!txq->mpw_hdr_dseg ||
1467                                  mpw.total_len >= MLX5_WQE_SIZE);
1468                 }
1469                 /* Multi-segment packets must be alone in their MPW. */
1470                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1471                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1472 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1473                         length = 0;
1474 #endif
1475                         do {
1476                                 volatile struct mlx5_wqe_data_seg *dseg;
1477
1478                                 assert(buf);
1479                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1480                                 dseg = mpw.data.dseg[mpw.pkts_n];
1481                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1482                                 *dseg = (struct mlx5_wqe_data_seg){
1483                                         .byte_count = rte_cpu_to_be_32(
1484                                                                 DATA_LEN(buf)),
1485                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1486                                         .addr = rte_cpu_to_be_64(addr),
1487                                 };
1488 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1489                                 length += DATA_LEN(buf);
1490 #endif
1491                                 buf = buf->next;
1492                                 ++j;
1493                                 ++mpw.pkts_n;
1494                         } while (--segs_n);
1495                         /* A multi-segmented packet takes one MPW session.
1496                          * TODO: Pack more multi-segmented packets if possible.
1497                          */
1498                         mlx5_mpw_close(txq, &mpw);
1499                         if (mpw.pkts_n < 3)
1500                                 max_wqe--;
1501                         else
1502                                 max_wqe -= 2;
1503                 } else if (max_inline && do_inline) {
1504                         /* Inline packet into WQE. */
1505                         unsigned int max;
1506
1507                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1508                         assert(length == DATA_LEN(buf));
1509                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1510                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1511                         mpw.data.raw = (volatile void *)
1512                                 ((uintptr_t)mpw.data.raw + inl_pad);
1513                         max = tx_mlx5_wq_tailroom(txq,
1514                                         (void *)(uintptr_t)mpw.data.raw);
1515                         /* Copy inline header. */
1516                         mpw.data.raw = (volatile void *)
1517                                 mlx5_copy_to_wq(
1518                                           (void *)(uintptr_t)mpw.data.raw,
1519                                           &inl_hdr,
1520                                           sizeof(inl_hdr),
1521                                           (void *)(uintptr_t)txq->wqes,
1522                                           max);
1523                         max = tx_mlx5_wq_tailroom(txq,
1524                                         (void *)(uintptr_t)mpw.data.raw);
1525                         /* Copy packet data. */
1526                         mpw.data.raw = (volatile void *)
1527                                 mlx5_copy_to_wq(
1528                                           (void *)(uintptr_t)mpw.data.raw,
1529                                           (void *)addr,
1530                                           length,
1531                                           (void *)(uintptr_t)txq->wqes,
1532                                           max);
1533                         ++mpw.pkts_n;
1534                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1535                         /* No need to get completion as the entire packet is
1536                          * copied to WQ. Free the buf right away.
1537                          */
1538                         rte_pktmbuf_free_seg(buf);
1539                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1540                         /* Add pad in the next packet if any. */
1541                         inl_pad = (((uintptr_t)mpw.data.raw +
1542                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1543                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1544                                   (uintptr_t)mpw.data.raw;
1545                 } else {
1546                         /* No inline. Load a dseg of packet pointer. */
1547                         volatile rte_v128u32_t *dseg;
1548
1549                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1550                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1551                         assert(length == DATA_LEN(buf));
1552                         if (!tx_mlx5_wq_tailroom(txq,
1553                                         (void *)((uintptr_t)mpw.data.raw
1554                                                 + inl_pad)))
1555                                 dseg = (volatile void *)txq->wqes;
1556                         else
1557                                 dseg = (volatile void *)
1558                                         ((uintptr_t)mpw.data.raw +
1559                                          inl_pad);
1560                         (*txq->elts)[elts_head++ & elts_m] = buf;
1561                         addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1562                                                                  uintptr_t));
1563                         *dseg = (rte_v128u32_t) {
1564                                 rte_cpu_to_be_32(length),
1565                                 mlx5_tx_mb2mr(txq, buf),
1566                                 addr,
1567                                 addr >> 32,
1568                         };
1569                         mpw.data.raw = (volatile void *)(dseg + 1);
1570                         mpw.total_len += (inl_pad + sizeof(*dseg));
1571                         ++j;
1572                         ++mpw.pkts_n;
1573                         mpw_room -= (inl_pad + sizeof(*dseg));
1574                         inl_pad = 0;
1575                 }
1576 #ifdef MLX5_PMD_SOFT_COUNTERS
1577                 /* Increment sent bytes counter. */
1578                 txq->stats.obytes += length;
1579 #endif
1580                 ++i;
1581         } while (i < pkts_n);
1582         /* Take a shortcut if nothing must be sent. */
1583         if (unlikely(i == 0))
1584                 return 0;
1585         /* Check whether completion threshold has been reached. */
1586         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1587                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1588                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1589                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1590
1591                 /* A CQE slot must always be available. */
1592                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1593                 /* Request completion on last WQE. */
1594                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1595                 /* Save elts_head in unused "immediate" field of WQE. */
1596                 wqe->ctrl[3] = elts_head;
1597                 txq->elts_comp = 0;
1598                 txq->mpw_comp = txq->wqe_ci;
1599         } else {
1600                 txq->elts_comp += j;
1601         }
1602 #ifdef MLX5_PMD_SOFT_COUNTERS
1603         /* Increment sent packets counter. */
1604         txq->stats.opackets += i;
1605 #endif
1606         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1607                 mlx5_empw_close(txq, &mpw);
1608         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1609                 mlx5_mpw_close(txq, &mpw);
1610         /* Ring QP doorbell. */
1611         mlx5_tx_dbrec(txq, mpw.wqe);
1612         txq->elts_head = elts_head;
1613         return i;
1614 }
1615
1616 /**
1617  * Translate RX completion flags to packet type.
1618  *
1619  * @param[in] cqe
1620  *   Pointer to CQE.
1621  *
1622  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1623  *
1624  * @return
1625  *   Packet type for struct rte_mbuf.
1626  */
1627 static inline uint32_t
1628 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1629 {
1630         uint8_t idx;
1631         uint8_t pinfo = cqe->pkt_info;
1632         uint16_t ptype = cqe->hdr_type_etc;
1633
1634         /*
1635          * The index to the array should have:
1636          * bit[1:0] = l3_hdr_type
1637          * bit[4:2] = l4_hdr_type
1638          * bit[5] = ip_frag
1639          * bit[6] = tunneled
1640          * bit[7] = outer_l3_type
1641          */
1642         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1643         return mlx5_ptype_table[idx];
1644 }
1645
1646 /**
1647  * Get size of the next packet for a given CQE. For compressed CQEs, the
1648  * consumer index is updated only once all packets of the current one have
1649  * been processed.
1650  *
1651  * @param rxq
1652  *   Pointer to RX queue.
1653  * @param cqe
1654  *   CQE to process.
1655  * @param[out] rss_hash
1656  *   Packet RSS Hash result.
1657  *
1658  * @return
1659  *   Packet size in bytes (0 if there is none), -1 in case of completion
1660  *   with error.
1661  */
1662 static inline int
1663 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1664                  uint16_t cqe_cnt, uint32_t *rss_hash)
1665 {
1666         struct rxq_zip *zip = &rxq->zip;
1667         uint16_t cqe_n = cqe_cnt + 1;
1668         int len = 0;
1669         uint16_t idx, end;
1670
1671         /* Process compressed data in the CQE and mini arrays. */
1672         if (zip->ai) {
1673                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1674                         (volatile struct mlx5_mini_cqe8 (*)[8])
1675                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1676
1677                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1678                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1679                 if ((++zip->ai & 7) == 0) {
1680                         /* Invalidate consumed CQEs */
1681                         idx = zip->ca;
1682                         end = zip->na;
1683                         while (idx != end) {
1684                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1685                                         MLX5_CQE_INVALIDATE;
1686                                 ++idx;
1687                         }
1688                         /*
1689                          * Increment consumer index to skip the number of
1690                          * CQEs consumed. Hardware leaves holes in the CQ
1691                          * ring for software use.
1692                          */
1693                         zip->ca = zip->na;
1694                         zip->na += 8;
1695                 }
1696                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1697                         /* Invalidate the rest */
1698                         idx = zip->ca;
1699                         end = zip->cq_ci;
1700
1701                         while (idx != end) {
1702                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1703                                         MLX5_CQE_INVALIDATE;
1704                                 ++idx;
1705                         }
1706                         rxq->cq_ci = zip->cq_ci;
1707                         zip->ai = 0;
1708                 }
1709         /* No compressed data, get next CQE and verify if it is compressed. */
1710         } else {
1711                 int ret;
1712                 int8_t op_own;
1713
1714                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1715                 if (unlikely(ret == 1))
1716                         return 0;
1717                 ++rxq->cq_ci;
1718                 op_own = cqe->op_own;
1719                 rte_io_rmb();
1720                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1721                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1722                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1723                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1724                                                           cqe_cnt].pkt_info);
1725
1726                         /* Fix endianness. */
1727                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1728                         /*
1729                          * Current mini array position is the one returned by
1730                          * check_cqe64().
1731                          *
1732                          * If completion comprises several mini arrays, as a
1733                          * special case the second one is located 7 CQEs after
1734                          * the initial CQE instead of 8 for subsequent ones.
1735                          */
1736                         zip->ca = rxq->cq_ci;
1737                         zip->na = zip->ca + 7;
1738                         /* Compute the next non compressed CQE. */
1739                         --rxq->cq_ci;
1740                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1741                         /* Get packet size to return. */
1742                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1743                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1744                         zip->ai = 1;
1745                         /* Prefetch all the entries to be invalidated */
1746                         idx = zip->ca;
1747                         end = zip->cq_ci;
1748                         while (idx != end) {
1749                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1750                                 ++idx;
1751                         }
1752                 } else {
1753                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1754                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1755                 }
1756                 /* Error while receiving packet. */
1757                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1758                         return -1;
1759         }
1760         return len;
1761 }
1762
1763 /**
1764  * Translate RX completion flags to offload flags.
1765  *
1766  * @param[in] rxq
1767  *   Pointer to RX queue structure.
1768  * @param[in] cqe
1769  *   Pointer to CQE.
1770  *
1771  * @return
1772  *   Offload flags (ol_flags) for struct rte_mbuf.
1773  */
1774 static inline uint32_t
1775 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1776 {
1777         uint32_t ol_flags = 0;
1778         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1779
1780         ol_flags =
1781                 TRANSPOSE(flags,
1782                           MLX5_CQE_RX_L3_HDR_VALID,
1783                           PKT_RX_IP_CKSUM_GOOD) |
1784                 TRANSPOSE(flags,
1785                           MLX5_CQE_RX_L4_HDR_VALID,
1786                           PKT_RX_L4_CKSUM_GOOD);
1787         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1788                 ol_flags |=
1789                         TRANSPOSE(flags,
1790                                   MLX5_CQE_RX_L3_HDR_VALID,
1791                                   PKT_RX_IP_CKSUM_GOOD) |
1792                         TRANSPOSE(flags,
1793                                   MLX5_CQE_RX_L4_HDR_VALID,
1794                                   PKT_RX_L4_CKSUM_GOOD);
1795         return ol_flags;
1796 }
1797
1798 /**
1799  * DPDK callback for RX.
1800  *
1801  * @param dpdk_rxq
1802  *   Generic pointer to RX queue structure.
1803  * @param[out] pkts
1804  *   Array to store received packets.
1805  * @param pkts_n
1806  *   Maximum number of packets in array.
1807  *
1808  * @return
1809  *   Number of packets successfully received (<= pkts_n).
1810  */
1811 uint16_t
1812 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1813 {
1814         struct mlx5_rxq_data *rxq = dpdk_rxq;
1815         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1816         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1817         const unsigned int sges_n = rxq->sges_n;
1818         struct rte_mbuf *pkt = NULL;
1819         struct rte_mbuf *seg = NULL;
1820         volatile struct mlx5_cqe *cqe =
1821                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1822         unsigned int i = 0;
1823         unsigned int rq_ci = rxq->rq_ci << sges_n;
1824         int len = 0; /* keep its value across iterations. */
1825
1826         while (pkts_n) {
1827                 unsigned int idx = rq_ci & wqe_cnt;
1828                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1829                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1830                 uint32_t rss_hash_res = 0;
1831
1832                 if (pkt)
1833                         NEXT(seg) = rep;
1834                 seg = rep;
1835                 rte_prefetch0(seg);
1836                 rte_prefetch0(cqe);
1837                 rte_prefetch0(wqe);
1838                 rep = rte_mbuf_raw_alloc(rxq->mp);
1839                 if (unlikely(rep == NULL)) {
1840                         ++rxq->stats.rx_nombuf;
1841                         if (!pkt) {
1842                                 /*
1843                                  * no buffers before we even started,
1844                                  * bail out silently.
1845                                  */
1846                                 break;
1847                         }
1848                         while (pkt != seg) {
1849                                 assert(pkt != (*rxq->elts)[idx]);
1850                                 rep = NEXT(pkt);
1851                                 NEXT(pkt) = NULL;
1852                                 NB_SEGS(pkt) = 1;
1853                                 rte_mbuf_raw_free(pkt);
1854                                 pkt = rep;
1855                         }
1856                         break;
1857                 }
1858                 if (!pkt) {
1859                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1860                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1861                                                &rss_hash_res);
1862                         if (!len) {
1863                                 rte_mbuf_raw_free(rep);
1864                                 break;
1865                         }
1866                         if (unlikely(len == -1)) {
1867                                 /* RX error, packet is likely too large. */
1868                                 rte_mbuf_raw_free(rep);
1869                                 ++rxq->stats.idropped;
1870                                 goto skip;
1871                         }
1872                         pkt = seg;
1873                         assert(len >= (rxq->crc_present << 2));
1874                         /* Update packet information. */
1875                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1876                         pkt->ol_flags = 0;
1877                         if (rss_hash_res && rxq->rss_hash) {
1878                                 pkt->hash.rss = rss_hash_res;
1879                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1880                         }
1881                         if (rxq->mark &&
1882                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1883                                 pkt->ol_flags |= PKT_RX_FDIR;
1884                                 if (cqe->sop_drop_qpn !=
1885                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1886                                         uint32_t mark = cqe->sop_drop_qpn;
1887
1888                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1889                                         pkt->hash.fdir.hi =
1890                                                 mlx5_flow_mark_get(mark);
1891                                 }
1892                         }
1893                         if (rxq->csum | rxq->csum_l2tun)
1894                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1895                         if (rxq->vlan_strip &&
1896                             (cqe->hdr_type_etc &
1897                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1898                                 pkt->ol_flags |= PKT_RX_VLAN |
1899                                         PKT_RX_VLAN_STRIPPED;
1900                                 pkt->vlan_tci =
1901                                         rte_be_to_cpu_16(cqe->vlan_info);
1902                         }
1903                         if (rxq->hw_timestamp) {
1904                                 pkt->timestamp =
1905                                         rte_be_to_cpu_64(cqe->timestamp);
1906                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1907                         }
1908                         if (rxq->crc_present)
1909                                 len -= ETHER_CRC_LEN;
1910                         PKT_LEN(pkt) = len;
1911                 }
1912                 DATA_LEN(rep) = DATA_LEN(seg);
1913                 PKT_LEN(rep) = PKT_LEN(seg);
1914                 SET_DATA_OFF(rep, DATA_OFF(seg));
1915                 PORT(rep) = PORT(seg);
1916                 (*rxq->elts)[idx] = rep;
1917                 /*
1918                  * Fill NIC descriptor with the new buffer.  The lkey and size
1919                  * of the buffers are already known, only the buffer address
1920                  * changes.
1921                  */
1922                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1923                 if (len > DATA_LEN(seg)) {
1924                         len -= DATA_LEN(seg);
1925                         ++NB_SEGS(pkt);
1926                         ++rq_ci;
1927                         continue;
1928                 }
1929                 DATA_LEN(seg) = len;
1930 #ifdef MLX5_PMD_SOFT_COUNTERS
1931                 /* Increment bytes counter. */
1932                 rxq->stats.ibytes += PKT_LEN(pkt);
1933 #endif
1934                 /* Return packet. */
1935                 *(pkts++) = pkt;
1936                 pkt = NULL;
1937                 --pkts_n;
1938                 ++i;
1939 skip:
1940                 /* Align consumer index to the next stride. */
1941                 rq_ci >>= sges_n;
1942                 ++rq_ci;
1943                 rq_ci <<= sges_n;
1944         }
1945         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1946                 return 0;
1947         /* Update the consumer index. */
1948         rxq->rq_ci = rq_ci >> sges_n;
1949         rte_io_wmb();
1950         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1951         rte_io_wmb();
1952         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1953 #ifdef MLX5_PMD_SOFT_COUNTERS
1954         /* Increment packets counter. */
1955         rxq->stats.ipackets += i;
1956 #endif
1957         return i;
1958 }
1959
1960 /**
1961  * Dummy DPDK callback for TX.
1962  *
1963  * This function is used to temporarily replace the real callback during
1964  * unsafe control operations on the queue, or in case of error.
1965  *
1966  * @param dpdk_txq
1967  *   Generic pointer to TX queue structure.
1968  * @param[in] pkts
1969  *   Packets to transmit.
1970  * @param pkts_n
1971  *   Number of packets in array.
1972  *
1973  * @return
1974  *   Number of packets successfully transmitted (<= pkts_n).
1975  */
1976 uint16_t
1977 removed_tx_burst(void *dpdk_txq __rte_unused,
1978                  struct rte_mbuf **pkts __rte_unused,
1979                  uint16_t pkts_n __rte_unused)
1980 {
1981         return 0;
1982 }
1983
1984 /**
1985  * Dummy DPDK callback for RX.
1986  *
1987  * This function is used to temporarily replace the real callback during
1988  * unsafe control operations on the queue, or in case of error.
1989  *
1990  * @param dpdk_rxq
1991  *   Generic pointer to RX queue structure.
1992  * @param[out] pkts
1993  *   Array to store received packets.
1994  * @param pkts_n
1995  *   Maximum number of packets in array.
1996  *
1997  * @return
1998  *   Number of packets successfully received (<= pkts_n).
1999  */
2000 uint16_t
2001 removed_rx_burst(void *dpdk_txq __rte_unused,
2002                  struct rte_mbuf **pkts __rte_unused,
2003                  uint16_t pkts_n __rte_unused)
2004 {
2005         return 0;
2006 }
2007
2008 /*
2009  * Vectorized Rx/Tx routines are not compiled in when required vector
2010  * instructions are not supported on a target architecture. The following null
2011  * stubs are needed for linkage when those are not included outside of this file
2012  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2013  */
2014
2015 uint16_t __attribute__((weak))
2016 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2017                       struct rte_mbuf **pkts __rte_unused,
2018                       uint16_t pkts_n __rte_unused)
2019 {
2020         return 0;
2021 }
2022
2023 uint16_t __attribute__((weak))
2024 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2025                   struct rte_mbuf **pkts __rte_unused,
2026                   uint16_t pkts_n __rte_unused)
2027 {
2028         return 0;
2029 }
2030
2031 uint16_t __attribute__((weak))
2032 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2033                   struct rte_mbuf **pkts __rte_unused,
2034                   uint16_t pkts_n __rte_unused)
2035 {
2036         return 0;
2037 }
2038
2039 int __attribute__((weak))
2040 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2041 {
2042         return -ENOTSUP;
2043 }
2044
2045 int __attribute__((weak))
2046 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2047 {
2048         return -ENOTSUP;
2049 }
2050
2051 int __attribute__((weak))
2052 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2053 {
2054         return -ENOTSUP;
2055 }
2056
2057 int __attribute__((weak))
2058 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2059 {
2060         return -ENOTSUP;
2061 }