drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         /* UDP */
 118         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_UDP;
 120         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_UDP;
 122         /* Repeat with outer_l3_type being set. Just in case. */
 123         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_NONFRAG;
 125         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_NONFRAG;
 127         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_FRAG;
 129         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_FRAG;
 131         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_TCP;
 135         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_UDP;
 139         /* Tunneled - L3 */
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         /* Tunneled - UDP */
 179         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_UDP;
 182         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_UDP;
 185         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_UDP;
 188         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_UDP;
 191 }
 192
 193 /**
 194  * Return the size of tailroom of WQ.
 195  *
 196  * @param txq
 197  *   Pointer to TX queue structure.
 198  * @param addr
 199  *   Pointer to tail of WQ.
 200  *
 201  * @return
 202  *   Size of tailroom.
 203  */
 204 static inline size_t
 205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 206 {
 207         size_t tailroom;
 208         tailroom = (uintptr_t)(txq->wqes) +
 209                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 210                    (uintptr_t)addr;
 211         return tailroom;
 212 }
 213
 214 /**
 215  * Copy data to tailroom of circular queue.
 216  *
 217  * @param dst
 218  *   Pointer to destination.
 219  * @param src
 220  *   Pointer to source.
 221  * @param n
 222  *   Number of bytes to copy.
 223  * @param base
 224  *   Pointer to head of queue.
 225  * @param tailroom
 226  *   Size of tailroom from dst.
 227  *
 228  * @return
 229  *   Pointer after copied data.
 230  */
 231 static inline void *
 232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 233                 void *base, size_t tailroom)
 234 {
 235         void *ret;
 236
 237         if (n > tailroom) {
 238                 rte_memcpy(dst, src, tailroom);
 239                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 240                            n - tailroom);
 241                 ret = (uint8_t *)base + n - tailroom;
 242         } else {
 243                 rte_memcpy(dst, src, n);
 244                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 245         }
 246         return ret;
 247 }
 248
 249 /**
 250  * DPDK callback to check the status of a tx descriptor.
 251  *
 252  * @param tx_queue
 253  *   The tx queue.
 254  * @param[in] offset
 255  *   The index of the descriptor in the ring.
 256  *
 257  * @return
 258  *   The status of the tx descriptor.
 259  */
 260 int
 261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 262 {
 263         struct mlx5_txq_data *txq = tx_queue;
 264         uint16_t used;
 265
 266         mlx5_tx_complete(txq);
 267         used = txq->elts_head - txq->elts_tail;
 268         if (offset < used)
 269                 return RTE_ETH_TX_DESC_FULL;
 270         return RTE_ETH_TX_DESC_DONE;
 271 }
 272
 273 /**
 274  * DPDK callback to check the status of a rx descriptor.
 275  *
 276  * @param rx_queue
 277  *   The rx queue.
 278  * @param[in] offset
 279  *   The index of the descriptor in the ring.
 280  *
 281  * @return
 282  *   The status of the tx descriptor.
 283  */
 284 int
 285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 286 {
 287         struct mlx5_rxq_data *rxq = rx_queue;
 288         struct rxq_zip *zip = &rxq->zip;
 289         volatile struct mlx5_cqe *cqe;
 290         const unsigned int cqe_n = (1 << rxq->cqe_n);
 291         const unsigned int cqe_cnt = cqe_n - 1;
 292         unsigned int cq_ci;
 293         unsigned int used;
 294
 295         /* if we are processing a compressed cqe */
 296         if (zip->ai) {
 297                 used = zip->cqe_cnt - zip->ca;
 298                 cq_ci = zip->cq_ci;
 299         } else {
 300                 used = 0;
 301                 cq_ci = rxq->cq_ci;
 302         }
 303         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 304         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 305                 int8_t op_own;
 306                 unsigned int n;
 307
 308                 op_own = cqe->op_own;
 309                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 310                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 311                 else
 312                         n = 1;
 313                 cq_ci += n;
 314                 used += n;
 315                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 316         }
 317         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 318         if (offset < used)
 319                 return RTE_ETH_RX_DESC_DONE;
 320         return RTE_ETH_RX_DESC_AVAIL;
 321 }
 322
 323 /**
 324  * DPDK callback for TX.
 325  *
 326  * @param dpdk_txq
 327  *   Generic pointer to TX queue structure.
 328  * @param[in] pkts
 329  *   Packets to transmit.
 330  * @param pkts_n
 331  *   Number of packets in array.
 332  *
 333  * @return
 334  *   Number of packets successfully transmitted (<= pkts_n).
 335  */
 336 uint16_t
 337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 338 {
 339         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 340         uint16_t elts_head = txq->elts_head;
 341         const uint16_t elts_n = 1 << txq->elts_n;
 342         const uint16_t elts_m = elts_n - 1;
 343         unsigned int i = 0;
 344         unsigned int j = 0;
 345         unsigned int k = 0;
 346         uint16_t max_elts;
 347         unsigned int max_inline = txq->max_inline;
 348         const unsigned int inline_en = !!max_inline && txq->inline_en;
 349         uint16_t max_wqe;
 350         unsigned int comp;
 351         volatile struct mlx5_wqe_v *wqe = NULL;
 352         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 353         unsigned int segs_n = 0;
 354         struct rte_mbuf *buf = NULL;
 355         uint8_t *raw;
 356
 357         if (unlikely(!pkts_n))
 358                 return 0;
 359         /* Prefetch first packet cacheline. */
 360         rte_prefetch0(*pkts);
 361         /* Start processing. */
 362         mlx5_tx_complete(txq);
 363         max_elts = (elts_n - (elts_head - txq->elts_tail));
 364         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 365         if (unlikely(!max_wqe))
 366                 return 0;
 367         do {
 368                 volatile rte_v128u32_t *dseg = NULL;
 369                 uint32_t length;
 370                 unsigned int ds = 0;
 371                 unsigned int sg = 0; /* counter of additional segs attached. */
 372                 uintptr_t addr;
 373                 uint64_t naddr;
 374                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 375                 uint16_t tso_header_sz = 0;
 376                 uint16_t ehdr;
 377                 uint8_t cs_flags;
 378                 uint64_t tso = 0;
 379                 uint16_t tso_segsz = 0;
 380 #ifdef MLX5_PMD_SOFT_COUNTERS
 381                 uint32_t total_length = 0;
 382 #endif
 383
 384                 /* first_seg */
 385                 buf = *pkts;
 386                 segs_n = buf->nb_segs;
 387                 /*
 388                  * Make sure there is enough room to store this packet and
 389                  * that one ring entry remains unused.
 390                  */
 391                 assert(segs_n);
 392                 if (max_elts < segs_n)
 393                         break;
 394                 max_elts -= segs_n;
 395                 --segs_n;
 396                 if (unlikely(--max_wqe == 0))
 397                         break;
 398                 wqe = (volatile struct mlx5_wqe_v *)
 399                         tx_mlx5_wqe(txq, txq->wqe_ci);
 400                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 401                 if (pkts_n - i > 1)
 402                         rte_prefetch0(*(pkts + 1));
 403                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 404                 length = DATA_LEN(buf);
 405                 ehdr = (((uint8_t *)addr)[1] << 8) |
 406                        ((uint8_t *)addr)[0];
 407 #ifdef MLX5_PMD_SOFT_COUNTERS
 408                 total_length = length;
 409 #endif
 410                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 411                         txq->stats.oerrors++;
 412                         break;
 413                 }
 414                 /* Update element. */
 415                 (*txq->elts)[elts_head & elts_m] = buf;
 416                 /* Prefetch next buffer data. */
 417                 if (pkts_n - i > 1)
 418                         rte_prefetch0(
 419                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 420                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 421                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 422                 /* Replace the Ethernet type by the VLAN if necessary. */
 423                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 424                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 425                                                          buf->vlan_tci);
 426                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 427
 428                         addr += 2;
 429                         length -= 2;
 430                         /* Copy Destination and source mac address. */
 431                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 432                         /* Copy VLAN. */
 433                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 434                         /* Copy missing two bytes to end the DSeg. */
 435                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 436                                ((uint8_t *)addr) + len, 2);
 437                         addr += len + 2;
 438                         length -= (len + 2);
 439                 } else {
 440                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 441                                MLX5_WQE_DWORD_SIZE);
 442                         length -= pkt_inline_sz;
 443                         addr += pkt_inline_sz;
 444                 }
 445                 raw += MLX5_WQE_DWORD_SIZE;
 446                 if (txq->tso_en) {
 447                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 448                         if (tso) {
 449                                 uintptr_t end = (uintptr_t)
 450                                                 (((uintptr_t)txq->wqes) +
 451                                                 (1 << txq->wqe_n) *
 452                                                 MLX5_WQE_SIZE);
 453                                 unsigned int copy_b;
 454                                 uint8_t vlan_sz = (buf->ol_flags &
 455                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 456                                 const uint64_t is_tunneled =
 457                                                         buf->ol_flags &
 458                                                         (PKT_TX_TUNNEL_GRE |
 459                                                          PKT_TX_TUNNEL_VXLAN);
 460
 461                                 tso_header_sz = buf->l2_len + vlan_sz +
 462                                                 buf->l3_len + buf->l4_len;
 463                                 tso_segsz = buf->tso_segsz;
 464                                 if (unlikely(tso_segsz == 0)) {
 465                                         txq->stats.oerrors++;
 466                                         break;
 467                                 }
 468                                 if (is_tunneled && txq->tunnel_en) {
 469                                         tso_header_sz += buf->outer_l2_len +
 470                                                          buf->outer_l3_len;
 471                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 472                                 } else {
 473                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 474                                 }
 475                                 if (unlikely(tso_header_sz >
 476                                              MLX5_MAX_TSO_HEADER)) {
 477                                         txq->stats.oerrors++;
 478                                         break;
 479                                 }
 480                                 copy_b = tso_header_sz - pkt_inline_sz;
 481                                 /* First seg must contain all headers. */
 482                                 assert(copy_b <= length);
 483                                 if (copy_b &&
 484                                    ((end - (uintptr_t)raw) > copy_b)) {
 485                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 486                                                       1 + 3) / 4;
 487
 488                                         if (unlikely(max_wqe < n))
 489                                                 break;
 490                                         max_wqe -= n;
 491                                         rte_memcpy((void *)raw,
 492                                                    (void *)addr, copy_b);
 493                                         addr += copy_b;
 494                                         length -= copy_b;
 495                                         /* Include padding for TSO header. */
 496                                         copy_b = MLX5_WQE_DS(copy_b) *
 497                                                  MLX5_WQE_DWORD_SIZE;
 498                                         pkt_inline_sz += copy_b;
 499                                         raw += copy_b;
 500                                 } else {
 501                                         /* NOP WQE. */
 502                                         wqe->ctrl = (rte_v128u32_t){
 503                                                      rte_cpu_to_be_32(
 504                                                         txq->wqe_ci << 8),
 505                                                      rte_cpu_to_be_32(
 506                                                         txq->qp_num_8s | 1),
 507                                                      0,
 508                                                      0,
 509                                         };
 510                                         ds = 1;
 511 #ifdef MLX5_PMD_SOFT_COUNTERS
 512                                         total_length = 0;
 513 #endif
 514                                         k++;
 515                                         goto next_wqe;
 516                                 }
 517                         }
 518                 }
 519                 /* Inline if enough room. */
 520                 if (inline_en || tso) {
 521                         uint32_t inl;
 522                         uintptr_t end = (uintptr_t)
 523                                 (((uintptr_t)txq->wqes) +
 524                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 525                         unsigned int inline_room = max_inline *
 526                                                    RTE_CACHE_LINE_SIZE -
 527                                                    (pkt_inline_sz - 2) -
 528                                                    !!tso * sizeof(inl);
 529                         uintptr_t addr_end = (addr + inline_room) &
 530                                              ~(RTE_CACHE_LINE_SIZE - 1);
 531                         unsigned int copy_b = (addr_end > addr) ?
 532                                 RTE_MIN((addr_end - addr), length) :
 533                                 0;
 534
 535                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 536                                 /*
 537                                  * One Dseg remains in the current WQE.  To
 538                                  * keep the computation positive, it is
 539                                  * removed after the bytes to Dseg conversion.
 540                                  */
 541                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 542
 543                                 if (unlikely(max_wqe < n))
 544                                         break;
 545                                 max_wqe -= n;
 546                                 if (tso) {
 547                                         inl = rte_cpu_to_be_32(copy_b |
 548                                                                MLX5_INLINE_SEG);
 549                                         rte_memcpy((void *)raw,
 550                                                    (void *)&inl, sizeof(inl));
 551                                         raw += sizeof(inl);
 552                                         pkt_inline_sz += sizeof(inl);
 553                                 }
 554                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 555                                 addr += copy_b;
 556                                 length -= copy_b;
 557                                 pkt_inline_sz += copy_b;
 558                         }
 559                         /*
 560                          * 2 DWORDs consumed by the WQE header + ETH segment +
 561                          * the size of the inline part of the packet.
 562                          */
 563                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 564                         if (length > 0) {
 565                                 if (ds % (MLX5_WQE_SIZE /
 566                                           MLX5_WQE_DWORD_SIZE) == 0) {
 567                                         if (unlikely(--max_wqe == 0))
 568                                                 break;
 569                                         dseg = (volatile rte_v128u32_t *)
 570                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 571                                                            ds / 4);
 572                                 } else {
 573                                         dseg = (volatile rte_v128u32_t *)
 574                                                 ((uintptr_t)wqe +
 575                                                  (ds * MLX5_WQE_DWORD_SIZE));
 576                                 }
 577                                 goto use_dseg;
 578                         } else if (!segs_n) {
 579                                 goto next_pkt;
 580                         } else {
 581                                 /* dseg will be advance as part of next_seg */
 582                                 dseg = (volatile rte_v128u32_t *)
 583                                         ((uintptr_t)wqe +
 584                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 585                                 goto next_seg;
 586                         }
 587                 } else {
 588                         /*
 589                          * No inline has been done in the packet, only the
 590                          * Ethernet Header as been stored.
 591                          */
 592                         dseg = (volatile rte_v128u32_t *)
 593                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 594                         ds = 3;
 595 use_dseg:
 596                         /* Add the remaining packet as a simple ds. */
 597                         naddr = rte_cpu_to_be_64(addr);
 598                         *dseg = (rte_v128u32_t){
 599                                 rte_cpu_to_be_32(length),
 600                                 mlx5_tx_mb2mr(txq, buf),
 601                                 naddr,
 602                                 naddr >> 32,
 603                         };
 604                         ++ds;
 605                         if (!segs_n)
 606                                 goto next_pkt;
 607                 }
 608 next_seg:
 609                 assert(buf);
 610                 assert(ds);
 611                 assert(wqe);
 612                 /*
 613                  * Spill on next WQE when the current one does not have
 614                  * enough room left. Size of WQE must a be a multiple
 615                  * of data segment size.
 616                  */
 617                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 618                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 619                         if (unlikely(--max_wqe == 0))
 620                                 break;
 621                         dseg = (volatile rte_v128u32_t *)
 622                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 623                         rte_prefetch0(tx_mlx5_wqe(txq,
 624                                                   txq->wqe_ci + ds / 4 + 1));
 625                 } else {
 626                         ++dseg;
 627                 }
 628                 ++ds;
 629                 buf = buf->next;
 630                 assert(buf);
 631                 length = DATA_LEN(buf);
 632 #ifdef MLX5_PMD_SOFT_COUNTERS
 633                 total_length += length;
 634 #endif
 635                 /* Store segment information. */
 636                 naddr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 637                 *dseg = (rte_v128u32_t){
 638                         rte_cpu_to_be_32(length),
 639                         mlx5_tx_mb2mr(txq, buf),
 640                         naddr,
 641                         naddr >> 32,
 642                 };
 643                 (*txq->elts)[++elts_head & elts_m] = buf;
 644                 ++sg;
 645                 /* Advance counter only if all segs are successfully posted. */
 646                 if (sg < segs_n)
 647                         goto next_seg;
 648                 else
 649                         j += sg;
 650 next_pkt:
 651                 if (ds > MLX5_DSEG_MAX) {
 652                         txq->stats.oerrors++;
 653                         break;
 654                 }
 655                 ++elts_head;
 656                 ++pkts;
 657                 ++i;
 658                 /* Initialize known and common part of the WQE structure. */
 659                 if (tso) {
 660                         wqe->ctrl = (rte_v128u32_t){
 661                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 662                                                  MLX5_OPCODE_TSO),
 663                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 664                                 0,
 665                                 0,
 666                         };
 667                         wqe->eseg = (rte_v128u32_t){
 668                                 0,
 669                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 670                                 0,
 671                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 672                         };
 673                 } else {
 674                         wqe->ctrl = (rte_v128u32_t){
 675                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 676                                                  MLX5_OPCODE_SEND),
 677                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 678                                 0,
 679                                 0,
 680                         };
 681                         wqe->eseg = (rte_v128u32_t){
 682                                 0,
 683                                 cs_flags,
 684                                 0,
 685                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 686                         };
 687                 }
 688 next_wqe:
 689                 txq->wqe_ci += (ds + 3) / 4;
 690                 /* Save the last successful WQE for completion request */
 691                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 692 #ifdef MLX5_PMD_SOFT_COUNTERS
 693                 /* Increment sent bytes counter. */
 694                 txq->stats.obytes += total_length;
 695 #endif
 696         } while (i < pkts_n);
 697         /* Take a shortcut if nothing must be sent. */
 698         if (unlikely((i + k) == 0))
 699                 return 0;
 700         txq->elts_head += (i + j);
 701         /* Check whether completion threshold has been reached. */
 702         comp = txq->elts_comp + i + j + k;
 703         if (comp >= MLX5_TX_COMP_THRESH) {
 704                 /* Request completion on last WQE. */
 705                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 706                 /* Save elts_head in unused "immediate" field of WQE. */
 707                 last_wqe->ctrl3 = txq->elts_head;
 708                 txq->elts_comp = 0;
 709         } else {
 710                 txq->elts_comp = comp;
 711         }
 712 #ifdef MLX5_PMD_SOFT_COUNTERS
 713         /* Increment sent packets counter. */
 714         txq->stats.opackets += i;
 715 #endif
 716         /* Ring QP doorbell. */
 717         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 718         return i;
 719 }
 720
 721 /**
 722  * Open a MPW session.
 723  *
 724  * @param txq
 725  *   Pointer to TX queue structure.
 726  * @param mpw
 727  *   Pointer to MPW session structure.
 728  * @param length
 729  *   Packet length.
 730  */
 731 static inline void
 732 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 733 {
 734         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 735         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 736                 (volatile struct mlx5_wqe_data_seg (*)[])
 737                 tx_mlx5_wqe(txq, idx + 1);
 738
 739         mpw->state = MLX5_MPW_STATE_OPENED;
 740         mpw->pkts_n = 0;
 741         mpw->len = length;
 742         mpw->total_len = 0;
 743         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 744         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 745         mpw->wqe->eseg.inline_hdr_sz = 0;
 746         mpw->wqe->eseg.rsvd0 = 0;
 747         mpw->wqe->eseg.rsvd1 = 0;
 748         mpw->wqe->eseg.rsvd2 = 0;
 749         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 750                                              (txq->wqe_ci << 8) |
 751                                              MLX5_OPCODE_TSO);
 752         mpw->wqe->ctrl[2] = 0;
 753         mpw->wqe->ctrl[3] = 0;
 754         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 755                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 756         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 757                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 758         mpw->data.dseg[2] = &(*dseg)[0];
 759         mpw->data.dseg[3] = &(*dseg)[1];
 760         mpw->data.dseg[4] = &(*dseg)[2];
 761 }
 762
 763 /**
 764  * Close a MPW session.
 765  *
 766  * @param txq
 767  *   Pointer to TX queue structure.
 768  * @param mpw
 769  *   Pointer to MPW session structure.
 770  */
 771 static inline void
 772 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 773 {
 774         unsigned int num = mpw->pkts_n;
 775
 776         /*
 777          * Store size in multiple of 16 bytes. Control and Ethernet segments
 778          * count as 2.
 779          */
 780         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 781         mpw->state = MLX5_MPW_STATE_CLOSED;
 782         if (num < 3)
 783                 ++txq->wqe_ci;
 784         else
 785                 txq->wqe_ci += 2;
 786         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 787         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 788 }
 789
 790 /**
 791  * DPDK callback for TX with MPW support.
 792  *
 793  * @param dpdk_txq
 794  *   Generic pointer to TX queue structure.
 795  * @param[in] pkts
 796  *   Packets to transmit.
 797  * @param pkts_n
 798  *   Number of packets in array.
 799  *
 800  * @return
 801  *   Number of packets successfully transmitted (<= pkts_n).
 802  */
 803 uint16_t
 804 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 805 {
 806         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 807         uint16_t elts_head = txq->elts_head;
 808         const uint16_t elts_n = 1 << txq->elts_n;
 809         const uint16_t elts_m = elts_n - 1;
 810         unsigned int i = 0;
 811         unsigned int j = 0;
 812         uint16_t max_elts;
 813         uint16_t max_wqe;
 814         unsigned int comp;
 815         struct mlx5_mpw mpw = {
 816                 .state = MLX5_MPW_STATE_CLOSED,
 817         };
 818
 819         if (unlikely(!pkts_n))
 820                 return 0;
 821         /* Prefetch first packet cacheline. */
 822         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 823         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 824         /* Start processing. */
 825         mlx5_tx_complete(txq);
 826         max_elts = (elts_n - (elts_head - txq->elts_tail));
 827         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 828         if (unlikely(!max_wqe))
 829                 return 0;
 830         do {
 831                 struct rte_mbuf *buf = *(pkts++);
 832                 uint32_t length;
 833                 unsigned int segs_n = buf->nb_segs;
 834                 uint32_t cs_flags;
 835
 836                 /*
 837                  * Make sure there is enough room to store this packet and
 838                  * that one ring entry remains unused.
 839                  */
 840                 assert(segs_n);
 841                 if (max_elts < segs_n)
 842                         break;
 843                 /* Do not bother with large packets MPW cannot handle. */
 844                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 845                         txq->stats.oerrors++;
 846                         break;
 847                 }
 848                 max_elts -= segs_n;
 849                 --pkts_n;
 850                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 851                 /* Retrieve packet information. */
 852                 length = PKT_LEN(buf);
 853                 assert(length);
 854                 /* Start new session if packet differs. */
 855                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 856                     ((mpw.len != length) ||
 857                      (segs_n != 1) ||
 858                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 859                         mlx5_mpw_close(txq, &mpw);
 860                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 861                         /*
 862                          * Multi-Packet WQE consumes at most two WQE.
 863                          * mlx5_mpw_new() expects to be able to use such
 864                          * resources.
 865                          */
 866                         if (unlikely(max_wqe < 2))
 867                                 break;
 868                         max_wqe -= 2;
 869                         mlx5_mpw_new(txq, &mpw, length);
 870                         mpw.wqe->eseg.cs_flags = cs_flags;
 871                 }
 872                 /* Multi-segment packets must be alone in their MPW. */
 873                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 874 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 875                 length = 0;
 876 #endif
 877                 do {
 878                         volatile struct mlx5_wqe_data_seg *dseg;
 879                         uintptr_t addr;
 880
 881                         assert(buf);
 882                         (*txq->elts)[elts_head++ & elts_m] = buf;
 883                         dseg = mpw.data.dseg[mpw.pkts_n];
 884                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 885                         *dseg = (struct mlx5_wqe_data_seg){
 886                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 887                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 888                                 .addr = rte_cpu_to_be_64(addr),
 889                         };
 890 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 891                         length += DATA_LEN(buf);
 892 #endif
 893                         buf = buf->next;
 894                         ++mpw.pkts_n;
 895                         ++j;
 896                 } while (--segs_n);
 897                 assert(length == mpw.len);
 898                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 899                         mlx5_mpw_close(txq, &mpw);
 900 #ifdef MLX5_PMD_SOFT_COUNTERS
 901                 /* Increment sent bytes counter. */
 902                 txq->stats.obytes += length;
 903 #endif
 904                 ++i;
 905         } while (pkts_n);
 906         /* Take a shortcut if nothing must be sent. */
 907         if (unlikely(i == 0))
 908                 return 0;
 909         /* Check whether completion threshold has been reached. */
 910         /* "j" includes both packets and segments. */
 911         comp = txq->elts_comp + j;
 912         if (comp >= MLX5_TX_COMP_THRESH) {
 913                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 914
 915                 /* Request completion on last WQE. */
 916                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 917                 /* Save elts_head in unused "immediate" field of WQE. */
 918                 wqe->ctrl[3] = elts_head;
 919                 txq->elts_comp = 0;
 920         } else {
 921                 txq->elts_comp = comp;
 922         }
 923 #ifdef MLX5_PMD_SOFT_COUNTERS
 924         /* Increment sent packets counter. */
 925         txq->stats.opackets += i;
 926 #endif
 927         /* Ring QP doorbell. */
 928         if (mpw.state == MLX5_MPW_STATE_OPENED)
 929                 mlx5_mpw_close(txq, &mpw);
 930         mlx5_tx_dbrec(txq, mpw.wqe);
 931         txq->elts_head = elts_head;
 932         return i;
 933 }
 934
 935 /**
 936  * Open a MPW inline session.
 937  *
 938  * @param txq
 939  *   Pointer to TX queue structure.
 940  * @param mpw
 941  *   Pointer to MPW session structure.
 942  * @param length
 943  *   Packet length.
 944  */
 945 static inline void
 946 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 947                     uint32_t length)
 948 {
 949         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 950         struct mlx5_wqe_inl_small *inl;
 951
 952         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 953         mpw->pkts_n = 0;
 954         mpw->len = length;
 955         mpw->total_len = 0;
 956         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 957         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 958                                              (txq->wqe_ci << 8) |
 959                                              MLX5_OPCODE_TSO);
 960         mpw->wqe->ctrl[2] = 0;
 961         mpw->wqe->ctrl[3] = 0;
 962         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 963         mpw->wqe->eseg.inline_hdr_sz = 0;
 964         mpw->wqe->eseg.cs_flags = 0;
 965         mpw->wqe->eseg.rsvd0 = 0;
 966         mpw->wqe->eseg.rsvd1 = 0;
 967         mpw->wqe->eseg.rsvd2 = 0;
 968         inl = (struct mlx5_wqe_inl_small *)
 969                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 970         mpw->data.raw = (uint8_t *)&inl->raw;
 971 }
 972
 973 /**
 974  * Close a MPW inline session.
 975  *
 976  * @param txq
 977  *   Pointer to TX queue structure.
 978  * @param mpw
 979  *   Pointer to MPW session structure.
 980  */
 981 static inline void
 982 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 983 {
 984         unsigned int size;
 985         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 986                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 987
 988         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 989         /*
 990          * Store size in multiple of 16 bytes. Control and Ethernet segments
 991          * count as 2.
 992          */
 993         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
 994                                              MLX5_WQE_DS(size));
 995         mpw->state = MLX5_MPW_STATE_CLOSED;
 996         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
 997         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 998 }
 999
1000 /**
1001  * DPDK callback for TX with MPW inline support.
1002  *
1003  * @param dpdk_txq
1004  *   Generic pointer to TX queue structure.
1005  * @param[in] pkts
1006  *   Packets to transmit.
1007  * @param pkts_n
1008  *   Number of packets in array.
1009  *
1010  * @return
1011  *   Number of packets successfully transmitted (<= pkts_n).
1012  */
1013 uint16_t
1014 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1015                          uint16_t pkts_n)
1016 {
1017         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1018         uint16_t elts_head = txq->elts_head;
1019         const uint16_t elts_n = 1 << txq->elts_n;
1020         const uint16_t elts_m = elts_n - 1;
1021         unsigned int i = 0;
1022         unsigned int j = 0;
1023         uint16_t max_elts;
1024         uint16_t max_wqe;
1025         unsigned int comp;
1026         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1027         struct mlx5_mpw mpw = {
1028                 .state = MLX5_MPW_STATE_CLOSED,
1029         };
1030         /*
1031          * Compute the maximum number of WQE which can be consumed by inline
1032          * code.
1033          * - 2 DSEG for:
1034          *   - 1 control segment,
1035          *   - 1 Ethernet segment,
1036          * - N Dseg from the inline request.
1037          */
1038         const unsigned int wqe_inl_n =
1039                 ((2 * MLX5_WQE_DWORD_SIZE +
1040                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1041                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1042
1043         if (unlikely(!pkts_n))
1044                 return 0;
1045         /* Prefetch first packet cacheline. */
1046         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1047         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1048         /* Start processing. */
1049         mlx5_tx_complete(txq);
1050         max_elts = (elts_n - (elts_head - txq->elts_tail));
1051         do {
1052                 struct rte_mbuf *buf = *(pkts++);
1053                 uintptr_t addr;
1054                 uint32_t length;
1055                 unsigned int segs_n = buf->nb_segs;
1056                 uint8_t cs_flags;
1057
1058                 /*
1059                  * Make sure there is enough room to store this packet and
1060                  * that one ring entry remains unused.
1061                  */
1062                 assert(segs_n);
1063                 if (max_elts < segs_n)
1064                         break;
1065                 /* Do not bother with large packets MPW cannot handle. */
1066                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1067                         txq->stats.oerrors++;
1068                         break;
1069                 }
1070                 max_elts -= segs_n;
1071                 --pkts_n;
1072                 /*
1073                  * Compute max_wqe in case less WQE were consumed in previous
1074                  * iteration.
1075                  */
1076                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1077                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1078                 /* Retrieve packet information. */
1079                 length = PKT_LEN(buf);
1080                 /* Start new session if packet differs. */
1081                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1082                         if ((mpw.len != length) ||
1083                             (segs_n != 1) ||
1084                             (mpw.wqe->eseg.cs_flags != cs_flags))
1085                                 mlx5_mpw_close(txq, &mpw);
1086                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1087                         if ((mpw.len != length) ||
1088                             (segs_n != 1) ||
1089                             (length > inline_room) ||
1090                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1091                                 mlx5_mpw_inline_close(txq, &mpw);
1092                                 inline_room =
1093                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1094                         }
1095                 }
1096                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1097                         if ((segs_n != 1) ||
1098                             (length > inline_room)) {
1099                                 /*
1100                                  * Multi-Packet WQE consumes at most two WQE.
1101                                  * mlx5_mpw_new() expects to be able to use
1102                                  * such resources.
1103                                  */
1104                                 if (unlikely(max_wqe < 2))
1105                                         break;
1106                                 max_wqe -= 2;
1107                                 mlx5_mpw_new(txq, &mpw, length);
1108                                 mpw.wqe->eseg.cs_flags = cs_flags;
1109                         } else {
1110                                 if (unlikely(max_wqe < wqe_inl_n))
1111                                         break;
1112                                 max_wqe -= wqe_inl_n;
1113                                 mlx5_mpw_inline_new(txq, &mpw, length);
1114                                 mpw.wqe->eseg.cs_flags = cs_flags;
1115                         }
1116                 }
1117                 /* Multi-segment packets must be alone in their MPW. */
1118                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1119                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1120                         assert(inline_room ==
1121                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1122 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1123                         length = 0;
1124 #endif
1125                         do {
1126                                 volatile struct mlx5_wqe_data_seg *dseg;
1127
1128                                 assert(buf);
1129                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1130                                 dseg = mpw.data.dseg[mpw.pkts_n];
1131                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1132                                 *dseg = (struct mlx5_wqe_data_seg){
1133                                         .byte_count =
1134                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1135                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1136                                         .addr = rte_cpu_to_be_64(addr),
1137                                 };
1138 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1139                                 length += DATA_LEN(buf);
1140 #endif
1141                                 buf = buf->next;
1142                                 ++mpw.pkts_n;
1143                                 ++j;
1144                         } while (--segs_n);
1145                         assert(length == mpw.len);
1146                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1147                                 mlx5_mpw_close(txq, &mpw);
1148                 } else {
1149                         unsigned int max;
1150
1151                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1152                         assert(length <= inline_room);
1153                         assert(length == DATA_LEN(buf));
1154                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1155                         (*txq->elts)[elts_head++ & elts_m] = buf;
1156                         /* Maximum number of bytes before wrapping. */
1157                         max = ((((uintptr_t)(txq->wqes)) +
1158                                 (1 << txq->wqe_n) *
1159                                 MLX5_WQE_SIZE) -
1160                                (uintptr_t)mpw.data.raw);
1161                         if (length > max) {
1162                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1163                                            (void *)addr,
1164                                            max);
1165                                 mpw.data.raw = (volatile void *)txq->wqes;
1166                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1167                                            (void *)(addr + max),
1168                                            length - max);
1169                                 mpw.data.raw += length - max;
1170                         } else {
1171                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1172                                            (void *)addr,
1173                                            length);
1174
1175                                 if (length == max)
1176                                         mpw.data.raw =
1177                                                 (volatile void *)txq->wqes;
1178                                 else
1179                                         mpw.data.raw += length;
1180                         }
1181                         ++mpw.pkts_n;
1182                         mpw.total_len += length;
1183                         ++j;
1184                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1185                                 mlx5_mpw_inline_close(txq, &mpw);
1186                                 inline_room =
1187                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1188                         } else {
1189                                 inline_room -= length;
1190                         }
1191                 }
1192 #ifdef MLX5_PMD_SOFT_COUNTERS
1193                 /* Increment sent bytes counter. */
1194                 txq->stats.obytes += length;
1195 #endif
1196                 ++i;
1197         } while (pkts_n);
1198         /* Take a shortcut if nothing must be sent. */
1199         if (unlikely(i == 0))
1200                 return 0;
1201         /* Check whether completion threshold has been reached. */
1202         /* "j" includes both packets and segments. */
1203         comp = txq->elts_comp + j;
1204         if (comp >= MLX5_TX_COMP_THRESH) {
1205                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1206
1207                 /* Request completion on last WQE. */
1208                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1209                 /* Save elts_head in unused "immediate" field of WQE. */
1210                 wqe->ctrl[3] = elts_head;
1211                 txq->elts_comp = 0;
1212         } else {
1213                 txq->elts_comp = comp;
1214         }
1215 #ifdef MLX5_PMD_SOFT_COUNTERS
1216         /* Increment sent packets counter. */
1217         txq->stats.opackets += i;
1218 #endif
1219         /* Ring QP doorbell. */
1220         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1221                 mlx5_mpw_inline_close(txq, &mpw);
1222         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1223                 mlx5_mpw_close(txq, &mpw);
1224         mlx5_tx_dbrec(txq, mpw.wqe);
1225         txq->elts_head = elts_head;
1226         return i;
1227 }
1228
1229 /**
1230  * Open an Enhanced MPW session.
1231  *
1232  * @param txq
1233  *   Pointer to TX queue structure.
1234  * @param mpw
1235  *   Pointer to MPW session structure.
1236  * @param length
1237  *   Packet length.
1238  */
1239 static inline void
1240 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1241 {
1242         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1243
1244         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1245         mpw->pkts_n = 0;
1246         mpw->total_len = sizeof(struct mlx5_wqe);
1247         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1248         mpw->wqe->ctrl[0] =
1249                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1250                                  (txq->wqe_ci << 8) |
1251                                  MLX5_OPCODE_ENHANCED_MPSW);
1252         mpw->wqe->ctrl[2] = 0;
1253         mpw->wqe->ctrl[3] = 0;
1254         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1255         if (unlikely(padding)) {
1256                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1257
1258                 /* Pad the first 2 DWORDs with zero-length inline header. */
1259                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1260                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1261                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1262                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1263                 /* Start from the next WQEBB. */
1264                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1265         } else {
1266                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1267         }
1268 }
1269
1270 /**
1271  * Close an Enhanced MPW session.
1272  *
1273  * @param txq
1274  *   Pointer to TX queue structure.
1275  * @param mpw
1276  *   Pointer to MPW session structure.
1277  *
1278  * @return
1279  *   Number of consumed WQEs.
1280  */
1281 static inline uint16_t
1282 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1283 {
1284         uint16_t ret;
1285
1286         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1287          * count as 2.
1288          */
1289         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1290                                              MLX5_WQE_DS(mpw->total_len));
1291         mpw->state = MLX5_MPW_STATE_CLOSED;
1292         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1293         txq->wqe_ci += ret;
1294         return ret;
1295 }
1296
1297 /**
1298  * DPDK callback for TX with Enhanced MPW support.
1299  *
1300  * @param dpdk_txq
1301  *   Generic pointer to TX queue structure.
1302  * @param[in] pkts
1303  *   Packets to transmit.
1304  * @param pkts_n
1305  *   Number of packets in array.
1306  *
1307  * @return
1308  *   Number of packets successfully transmitted (<= pkts_n).
1309  */
1310 uint16_t
1311 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1312 {
1313         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1314         uint16_t elts_head = txq->elts_head;
1315         const uint16_t elts_n = 1 << txq->elts_n;
1316         const uint16_t elts_m = elts_n - 1;
1317         unsigned int i = 0;
1318         unsigned int j = 0;
1319         uint16_t max_elts;
1320         uint16_t max_wqe;
1321         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1322         unsigned int mpw_room = 0;
1323         unsigned int inl_pad = 0;
1324         uint32_t inl_hdr;
1325         struct mlx5_mpw mpw = {
1326                 .state = MLX5_MPW_STATE_CLOSED,
1327         };
1328
1329         if (unlikely(!pkts_n))
1330                 return 0;
1331         /* Start processing. */
1332         mlx5_tx_complete(txq);
1333         max_elts = (elts_n - (elts_head - txq->elts_tail));
1334         /* A CQE slot must always be available. */
1335         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1336         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1337         if (unlikely(!max_wqe))
1338                 return 0;
1339         do {
1340                 struct rte_mbuf *buf = *(pkts++);
1341                 uintptr_t addr;
1342                 uint64_t naddr;
1343                 unsigned int n;
1344                 unsigned int do_inline = 0; /* Whether inline is possible. */
1345                 uint32_t length;
1346                 unsigned int segs_n = buf->nb_segs;
1347                 uint8_t cs_flags;
1348
1349                 /*
1350                  * Make sure there is enough room to store this packet and
1351                  * that one ring entry remains unused.
1352                  */
1353                 assert(segs_n);
1354                 if (max_elts - j < segs_n)
1355                         break;
1356                 /* Do not bother with large packets MPW cannot handle. */
1357                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1358                         txq->stats.oerrors++;
1359                         break;
1360                 }
1361                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1362                 /* Retrieve packet information. */
1363                 length = PKT_LEN(buf);
1364                 /* Start new session if:
1365                  * - multi-segment packet
1366                  * - no space left even for a dseg
1367                  * - next packet can be inlined with a new WQE
1368                  * - cs_flag differs
1369                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1370                  * segmented packet.
1371                  */
1372                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1373                         if ((segs_n != 1) ||
1374                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1375                               mpw_room) ||
1376                             (length <= txq->inline_max_packet_sz &&
1377                              inl_pad + sizeof(inl_hdr) + length >
1378                               mpw_room) ||
1379                             (mpw.wqe->eseg.cs_flags != cs_flags))
1380                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1381                 }
1382                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1383                         if (unlikely(segs_n != 1)) {
1384                                 /* Fall back to legacy MPW.
1385                                  * A MPW session consumes 2 WQEs at most to
1386                                  * include MLX5_MPW_DSEG_MAX pointers.
1387                                  */
1388                                 if (unlikely(max_wqe < 2))
1389                                         break;
1390                                 mlx5_mpw_new(txq, &mpw, length);
1391                         } else {
1392                                 /* In Enhanced MPW, inline as much as the budget
1393                                  * is allowed. The remaining space is to be
1394                                  * filled with dsegs. If the title WQEBB isn't
1395                                  * padded, it will have 2 dsegs there.
1396                                  */
1397                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1398                                             (max_inline ? max_inline :
1399                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1400                                             MLX5_WQE_SIZE);
1401                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1402                                               mpw_room))
1403                                         break;
1404                                 /* Don't pad the title WQEBB to not waste WQ. */
1405                                 mlx5_empw_new(txq, &mpw, 0);
1406                                 mpw_room -= mpw.total_len;
1407                                 inl_pad = 0;
1408                                 do_inline =
1409                                         length <= txq->inline_max_packet_sz &&
1410                                         sizeof(inl_hdr) + length <= mpw_room &&
1411                                         !txq->mpw_hdr_dseg;
1412                         }
1413                         mpw.wqe->eseg.cs_flags = cs_flags;
1414                 } else {
1415                         /* Evaluate whether the next packet can be inlined.
1416                          * Inlininig is possible when:
1417                          * - length is less than configured value
1418                          * - length fits for remaining space
1419                          * - not required to fill the title WQEBB with dsegs
1420                          */
1421                         do_inline =
1422                                 length <= txq->inline_max_packet_sz &&
1423                                 inl_pad + sizeof(inl_hdr) + length <=
1424                                  mpw_room &&
1425                                 (!txq->mpw_hdr_dseg ||
1426                                  mpw.total_len >= MLX5_WQE_SIZE);
1427                 }
1428                 /* Multi-segment packets must be alone in their MPW. */
1429                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1430                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1431 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1432                         length = 0;
1433 #endif
1434                         do {
1435                                 volatile struct mlx5_wqe_data_seg *dseg;
1436
1437                                 assert(buf);
1438                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1439                                 dseg = mpw.data.dseg[mpw.pkts_n];
1440                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1441                                 *dseg = (struct mlx5_wqe_data_seg){
1442                                         .byte_count = rte_cpu_to_be_32(
1443                                                                 DATA_LEN(buf)),
1444                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1445                                         .addr = rte_cpu_to_be_64(addr),
1446                                 };
1447 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1448                                 length += DATA_LEN(buf);
1449 #endif
1450                                 buf = buf->next;
1451                                 ++j;
1452                                 ++mpw.pkts_n;
1453                         } while (--segs_n);
1454                         /* A multi-segmented packet takes one MPW session.
1455                          * TODO: Pack more multi-segmented packets if possible.
1456                          */
1457                         mlx5_mpw_close(txq, &mpw);
1458                         if (mpw.pkts_n < 3)
1459                                 max_wqe--;
1460                         else
1461                                 max_wqe -= 2;
1462                 } else if (do_inline) {
1463                         /* Inline packet into WQE. */
1464                         unsigned int max;
1465
1466                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1467                         assert(length == DATA_LEN(buf));
1468                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1469                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1470                         mpw.data.raw = (volatile void *)
1471                                 ((uintptr_t)mpw.data.raw + inl_pad);
1472                         max = tx_mlx5_wq_tailroom(txq,
1473                                         (void *)(uintptr_t)mpw.data.raw);
1474                         /* Copy inline header. */
1475                         mpw.data.raw = (volatile void *)
1476                                 mlx5_copy_to_wq(
1477                                           (void *)(uintptr_t)mpw.data.raw,
1478                                           &inl_hdr,
1479                                           sizeof(inl_hdr),
1480                                           (void *)(uintptr_t)txq->wqes,
1481                                           max);
1482                         max = tx_mlx5_wq_tailroom(txq,
1483                                         (void *)(uintptr_t)mpw.data.raw);
1484                         /* Copy packet data. */
1485                         mpw.data.raw = (volatile void *)
1486                                 mlx5_copy_to_wq(
1487                                           (void *)(uintptr_t)mpw.data.raw,
1488                                           (void *)addr,
1489                                           length,
1490                                           (void *)(uintptr_t)txq->wqes,
1491                                           max);
1492                         ++mpw.pkts_n;
1493                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1494                         /* No need to get completion as the entire packet is
1495                          * copied to WQ. Free the buf right away.
1496                          */
1497                         rte_pktmbuf_free_seg(buf);
1498                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1499                         /* Add pad in the next packet if any. */
1500                         inl_pad = (((uintptr_t)mpw.data.raw +
1501                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1502                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1503                                   (uintptr_t)mpw.data.raw;
1504                 } else {
1505                         /* No inline. Load a dseg of packet pointer. */
1506                         volatile rte_v128u32_t *dseg;
1507
1508                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1509                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1510                         assert(length == DATA_LEN(buf));
1511                         if (!tx_mlx5_wq_tailroom(txq,
1512                                         (void *)((uintptr_t)mpw.data.raw
1513                                                 + inl_pad)))
1514                                 dseg = (volatile void *)txq->wqes;
1515                         else
1516                                 dseg = (volatile void *)
1517                                         ((uintptr_t)mpw.data.raw +
1518                                          inl_pad);
1519                         (*txq->elts)[elts_head++ & elts_m] = buf;
1520                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1521                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1522                                 rte_prefetch2((void *)(addr +
1523                                                 n * RTE_CACHE_LINE_SIZE));
1524                         naddr = rte_cpu_to_be_64(addr);
1525                         *dseg = (rte_v128u32_t) {
1526                                 rte_cpu_to_be_32(length),
1527                                 mlx5_tx_mb2mr(txq, buf),
1528                                 naddr,
1529                                 naddr >> 32,
1530                         };
1531                         mpw.data.raw = (volatile void *)(dseg + 1);
1532                         mpw.total_len += (inl_pad + sizeof(*dseg));
1533                         ++j;
1534                         ++mpw.pkts_n;
1535                         mpw_room -= (inl_pad + sizeof(*dseg));
1536                         inl_pad = 0;
1537                 }
1538 #ifdef MLX5_PMD_SOFT_COUNTERS
1539                 /* Increment sent bytes counter. */
1540                 txq->stats.obytes += length;
1541 #endif
1542                 ++i;
1543         } while (i < pkts_n);
1544         /* Take a shortcut if nothing must be sent. */
1545         if (unlikely(i == 0))
1546                 return 0;
1547         /* Check whether completion threshold has been reached. */
1548         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1549                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1550                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1551                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1552
1553                 /* Request completion on last WQE. */
1554                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1555                 /* Save elts_head in unused "immediate" field of WQE. */
1556                 wqe->ctrl[3] = elts_head;
1557                 txq->elts_comp = 0;
1558                 txq->mpw_comp = txq->wqe_ci;
1559                 txq->cq_pi++;
1560         } else {
1561                 txq->elts_comp += j;
1562         }
1563 #ifdef MLX5_PMD_SOFT_COUNTERS
1564         /* Increment sent packets counter. */
1565         txq->stats.opackets += i;
1566 #endif
1567         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1568                 mlx5_empw_close(txq, &mpw);
1569         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1570                 mlx5_mpw_close(txq, &mpw);
1571         /* Ring QP doorbell. */
1572         mlx5_tx_dbrec(txq, mpw.wqe);
1573         txq->elts_head = elts_head;
1574         return i;
1575 }
1576
1577 /**
1578  * Translate RX completion flags to packet type.
1579  *
1580  * @param[in] cqe
1581  *   Pointer to CQE.
1582  *
1583  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1584  *
1585  * @return
1586  *   Packet type for struct rte_mbuf.
1587  */
1588 static inline uint32_t
1589 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1590 {
1591         uint8_t idx;
1592         uint8_t pinfo = cqe->pkt_info;
1593         uint16_t ptype = cqe->hdr_type_etc;
1594
1595         /*
1596          * The index to the array should have:
1597          * bit[1:0] = l3_hdr_type
1598          * bit[4:2] = l4_hdr_type
1599          * bit[5] = ip_frag
1600          * bit[6] = tunneled
1601          * bit[7] = outer_l3_type
1602          */
1603         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1604         return mlx5_ptype_table[idx];
1605 }
1606
1607 /**
1608  * Get size of the next packet for a given CQE. For compressed CQEs, the
1609  * consumer index is updated only once all packets of the current one have
1610  * been processed.
1611  *
1612  * @param rxq
1613  *   Pointer to RX queue.
1614  * @param cqe
1615  *   CQE to process.
1616  * @param[out] rss_hash
1617  *   Packet RSS Hash result.
1618  *
1619  * @return
1620  *   Packet size in bytes (0 if there is none), -1 in case of completion
1621  *   with error.
1622  */
1623 static inline int
1624 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1625                  uint16_t cqe_cnt, uint32_t *rss_hash)
1626 {
1627         struct rxq_zip *zip = &rxq->zip;
1628         uint16_t cqe_n = cqe_cnt + 1;
1629         int len = 0;
1630         uint16_t idx, end;
1631
1632         /* Process compressed data in the CQE and mini arrays. */
1633         if (zip->ai) {
1634                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1635                         (volatile struct mlx5_mini_cqe8 (*)[8])
1636                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1637
1638                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1639                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1640                 if ((++zip->ai & 7) == 0) {
1641                         /* Invalidate consumed CQEs */
1642                         idx = zip->ca;
1643                         end = zip->na;
1644                         while (idx != end) {
1645                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1646                                         MLX5_CQE_INVALIDATE;
1647                                 ++idx;
1648                         }
1649                         /*
1650                          * Increment consumer index to skip the number of
1651                          * CQEs consumed. Hardware leaves holes in the CQ
1652                          * ring for software use.
1653                          */
1654                         zip->ca = zip->na;
1655                         zip->na += 8;
1656                 }
1657                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1658                         /* Invalidate the rest */
1659                         idx = zip->ca;
1660                         end = zip->cq_ci;
1661
1662                         while (idx != end) {
1663                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1664                                         MLX5_CQE_INVALIDATE;
1665                                 ++idx;
1666                         }
1667                         rxq->cq_ci = zip->cq_ci;
1668                         zip->ai = 0;
1669                 }
1670         /* No compressed data, get next CQE and verify if it is compressed. */
1671         } else {
1672                 int ret;
1673                 int8_t op_own;
1674
1675                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1676                 if (unlikely(ret == 1))
1677                         return 0;
1678                 ++rxq->cq_ci;
1679                 op_own = cqe->op_own;
1680                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1681                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1682                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1683                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1684                                                           cqe_cnt].pkt_info);
1685
1686                         /* Fix endianness. */
1687                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1688                         /*
1689                          * Current mini array position is the one returned by
1690                          * check_cqe64().
1691                          *
1692                          * If completion comprises several mini arrays, as a
1693                          * special case the second one is located 7 CQEs after
1694                          * the initial CQE instead of 8 for subsequent ones.
1695                          */
1696                         zip->ca = rxq->cq_ci;
1697                         zip->na = zip->ca + 7;
1698                         /* Compute the next non compressed CQE. */
1699                         --rxq->cq_ci;
1700                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1701                         /* Get packet size to return. */
1702                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1703                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1704                         zip->ai = 1;
1705                         /* Prefetch all the entries to be invalidated */
1706                         idx = zip->ca;
1707                         end = zip->cq_ci;
1708                         while (idx != end) {
1709                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1710                                 ++idx;
1711                         }
1712                 } else {
1713                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1714                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1715                 }
1716                 /* Error while receiving packet. */
1717                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1718                         return -1;
1719         }
1720         return len;
1721 }
1722
1723 /**
1724  * Translate RX completion flags to offload flags.
1725  *
1726  * @param[in] rxq
1727  *   Pointer to RX queue structure.
1728  * @param[in] cqe
1729  *   Pointer to CQE.
1730  *
1731  * @return
1732  *   Offload flags (ol_flags) for struct rte_mbuf.
1733  */
1734 static inline uint32_t
1735 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1736 {
1737         uint32_t ol_flags = 0;
1738         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1739
1740         ol_flags =
1741                 TRANSPOSE(flags,
1742                           MLX5_CQE_RX_L3_HDR_VALID,
1743                           PKT_RX_IP_CKSUM_GOOD) |
1744                 TRANSPOSE(flags,
1745                           MLX5_CQE_RX_L4_HDR_VALID,
1746                           PKT_RX_L4_CKSUM_GOOD);
1747         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1748                 ol_flags |=
1749                         TRANSPOSE(flags,
1750                                   MLX5_CQE_RX_L3_HDR_VALID,
1751                                   PKT_RX_IP_CKSUM_GOOD) |
1752                         TRANSPOSE(flags,
1753                                   MLX5_CQE_RX_L4_HDR_VALID,
1754                                   PKT_RX_L4_CKSUM_GOOD);
1755         return ol_flags;
1756 }
1757
1758 /**
1759  * DPDK callback for RX.
1760  *
1761  * @param dpdk_rxq
1762  *   Generic pointer to RX queue structure.
1763  * @param[out] pkts
1764  *   Array to store received packets.
1765  * @param pkts_n
1766  *   Maximum number of packets in array.
1767  *
1768  * @return
1769  *   Number of packets successfully received (<= pkts_n).
1770  */
1771 uint16_t
1772 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1773 {
1774         struct mlx5_rxq_data *rxq = dpdk_rxq;
1775         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1776         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1777         const unsigned int sges_n = rxq->sges_n;
1778         struct rte_mbuf *pkt = NULL;
1779         struct rte_mbuf *seg = NULL;
1780         volatile struct mlx5_cqe *cqe =
1781                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1782         unsigned int i = 0;
1783         unsigned int rq_ci = rxq->rq_ci << sges_n;
1784         int len = 0; /* keep its value across iterations. */
1785
1786         while (pkts_n) {
1787                 unsigned int idx = rq_ci & wqe_cnt;
1788                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1789                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1790                 uint32_t rss_hash_res = 0;
1791
1792                 if (pkt)
1793                         NEXT(seg) = rep;
1794                 seg = rep;
1795                 rte_prefetch0(seg);
1796                 rte_prefetch0(cqe);
1797                 rte_prefetch0(wqe);
1798                 rep = rte_mbuf_raw_alloc(rxq->mp);
1799                 if (unlikely(rep == NULL)) {
1800                         ++rxq->stats.rx_nombuf;
1801                         if (!pkt) {
1802                                 /*
1803                                  * no buffers before we even started,
1804                                  * bail out silently.
1805                                  */
1806                                 break;
1807                         }
1808                         while (pkt != seg) {
1809                                 assert(pkt != (*rxq->elts)[idx]);
1810                                 rep = NEXT(pkt);
1811                                 NEXT(pkt) = NULL;
1812                                 NB_SEGS(pkt) = 1;
1813                                 rte_mbuf_raw_free(pkt);
1814                                 pkt = rep;
1815                         }
1816                         break;
1817                 }
1818                 if (!pkt) {
1819                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1820                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1821                                                &rss_hash_res);
1822                         if (!len) {
1823                                 rte_mbuf_raw_free(rep);
1824                                 break;
1825                         }
1826                         if (unlikely(len == -1)) {
1827                                 /* RX error, packet is likely too large. */
1828                                 rte_mbuf_raw_free(rep);
1829                                 ++rxq->stats.idropped;
1830                                 goto skip;
1831                         }
1832                         pkt = seg;
1833                         assert(len >= (rxq->crc_present << 2));
1834                         /* Update packet information. */
1835                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1836                         pkt->ol_flags = 0;
1837                         if (rss_hash_res && rxq->rss_hash) {
1838                                 pkt->hash.rss = rss_hash_res;
1839                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1840                         }
1841                         if (rxq->mark &&
1842                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1843                                 pkt->ol_flags |= PKT_RX_FDIR;
1844                                 if (cqe->sop_drop_qpn !=
1845                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1846                                         uint32_t mark = cqe->sop_drop_qpn;
1847
1848                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1849                                         pkt->hash.fdir.hi =
1850                                                 mlx5_flow_mark_get(mark);
1851                                 }
1852                         }
1853                         if (rxq->csum | rxq->csum_l2tun)
1854                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1855                         if (rxq->vlan_strip &&
1856                             (cqe->hdr_type_etc &
1857                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1858                                 pkt->ol_flags |= PKT_RX_VLAN |
1859                                         PKT_RX_VLAN_STRIPPED;
1860                                 pkt->vlan_tci =
1861                                         rte_be_to_cpu_16(cqe->vlan_info);
1862                         }
1863                         if (rxq->hw_timestamp) {
1864                                 pkt->timestamp =
1865                                         rte_be_to_cpu_64(cqe->timestamp);
1866                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1867                         }
1868                         if (rxq->crc_present)
1869                                 len -= ETHER_CRC_LEN;
1870                         PKT_LEN(pkt) = len;
1871                 }
1872                 DATA_LEN(rep) = DATA_LEN(seg);
1873                 PKT_LEN(rep) = PKT_LEN(seg);
1874                 SET_DATA_OFF(rep, DATA_OFF(seg));
1875                 PORT(rep) = PORT(seg);
1876                 (*rxq->elts)[idx] = rep;
1877                 /*
1878                  * Fill NIC descriptor with the new buffer.  The lkey and size
1879                  * of the buffers are already known, only the buffer address
1880                  * changes.
1881                  */
1882                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1883                 if (len > DATA_LEN(seg)) {
1884                         len -= DATA_LEN(seg);
1885                         ++NB_SEGS(pkt);
1886                         ++rq_ci;
1887                         continue;
1888                 }
1889                 DATA_LEN(seg) = len;
1890 #ifdef MLX5_PMD_SOFT_COUNTERS
1891                 /* Increment bytes counter. */
1892                 rxq->stats.ibytes += PKT_LEN(pkt);
1893 #endif
1894                 /* Return packet. */
1895                 *(pkts++) = pkt;
1896                 pkt = NULL;
1897                 --pkts_n;
1898                 ++i;
1899 skip:
1900                 /* Align consumer index to the next stride. */
1901                 rq_ci >>= sges_n;
1902                 ++rq_ci;
1903                 rq_ci <<= sges_n;
1904         }
1905         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1906                 return 0;
1907         /* Update the consumer index. */
1908         rxq->rq_ci = rq_ci >> sges_n;
1909         rte_io_wmb();
1910         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1911         rte_io_wmb();
1912         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914         /* Increment packets counter. */
1915         rxq->stats.ipackets += i;
1916 #endif
1917         return i;
1918 }
1919
1920 /**
1921  * Dummy DPDK callback for TX.
1922  *
1923  * This function is used to temporarily replace the real callback during
1924  * unsafe control operations on the queue, or in case of error.
1925  *
1926  * @param dpdk_txq
1927  *   Generic pointer to TX queue structure.
1928  * @param[in] pkts
1929  *   Packets to transmit.
1930  * @param pkts_n
1931  *   Number of packets in array.
1932  *
1933  * @return
1934  *   Number of packets successfully transmitted (<= pkts_n).
1935  */
1936 uint16_t
1937 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1938 {
1939         (void)dpdk_txq;
1940         (void)pkts;
1941         (void)pkts_n;
1942         return 0;
1943 }
1944
1945 /**
1946  * Dummy DPDK callback for RX.
1947  *
1948  * This function is used to temporarily replace the real callback during
1949  * unsafe control operations on the queue, or in case of error.
1950  *
1951  * @param dpdk_rxq
1952  *   Generic pointer to RX queue structure.
1953  * @param[out] pkts
1954  *   Array to store received packets.
1955  * @param pkts_n
1956  *   Maximum number of packets in array.
1957  *
1958  * @return
1959  *   Number of packets successfully received (<= pkts_n).
1960  */
1961 uint16_t
1962 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1963 {
1964         (void)dpdk_rxq;
1965         (void)pkts;
1966         (void)pkts_n;
1967         return 0;
1968 }
1969
1970 /*
1971  * Vectorized Rx/Tx routines are not compiled in when required vector
1972  * instructions are not supported on a target architecture. The following null
1973  * stubs are needed for linkage when those are not included outside of this file
1974  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1975  */
1976
1977 uint16_t __attribute__((weak))
1978 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1979 {
1980         (void)dpdk_txq;
1981         (void)pkts;
1982         (void)pkts_n;
1983         return 0;
1984 }
1985
1986 uint16_t __attribute__((weak))
1987 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1988 {
1989         (void)dpdk_txq;
1990         (void)pkts;
1991         (void)pkts_n;
1992         return 0;
1993 }
1994
1995 uint16_t __attribute__((weak))
1996 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1997 {
1998         (void)dpdk_rxq;
1999         (void)pkts;
2000         (void)pkts_n;
2001         return 0;
2002 }
2003
2004 int __attribute__((weak))
2005 priv_check_raw_vec_tx_support(struct priv *priv)
2006 {
2007         (void)priv;
2008         return -ENOTSUP;
2009 }
2010
2011 int __attribute__((weak))
2012 priv_check_vec_tx_support(struct priv *priv)
2013 {
2014         (void)priv;
2015         return -ENOTSUP;
2016 }
2017
2018 int __attribute__((weak))
2019 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2020 {
2021         (void)rxq;
2022         return -ENOTSUP;
2023 }
2024
2025 int __attribute__((weak))
2026 priv_check_vec_rx_support(struct priv *priv)
2027 {
2028         (void)priv;
2029         return -ENOTSUP;
2030 }