drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  45
  46 static __rte_always_inline void
  47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  48                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  49
  50 static __rte_always_inline void
  51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  52
  53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  54         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  55 };
  56
  57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  59
  60 /**
  61  * Build a table to translate Rx completion flags to packet type.
  62  *
  63  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  64  */
  65 void
  66 mlx5_set_ptype_table(void)
  67 {
  68         unsigned int i;
  69         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  70
  71         /* Last entry must not be overwritten, reserved for errored packet. */
  72         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  73                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  74         /*
  75          * The index to the array should have:
  76          * bit[1:0] = l3_hdr_type
  77          * bit[4:2] = l4_hdr_type
  78          * bit[5] = ip_frag
  79          * bit[6] = tunneled
  80          * bit[7] = outer_l3_type
  81          */
  82         /* L2 */
  83         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  84         /* L3 */
  85         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_NONFRAG;
  87         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_NONFRAG;
  89         /* Fragmented */
  90         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  91                      RTE_PTYPE_L4_FRAG;
  92         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG;
  94         /* TCP */
  95         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  96                      RTE_PTYPE_L4_TCP;
  97         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP;
  99         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP;
 101         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP;
 103         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_TCP;
 105         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_TCP;
 107         /* UDP */
 108         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_UDP;
 110         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_UDP;
 112         /* Repeat with outer_l3_type being set. Just in case. */
 113         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_NONFRAG;
 115         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_NONFRAG;
 117         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_FRAG;
 119         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_FRAG;
 121         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_TCP;
 125         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_TCP;
 127         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_TCP;
 129         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_TCP;
 131         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_UDP;
 135         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         /* Tunneled - L3 */
 138         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L4_TCP;
 196         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 197                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L4_TCP;
 199         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L4_TCP;
 202         /* Tunneled - UDP */
 203         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_UDP;
 209         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_UDP;
 212         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 213                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L4_UDP;
 215 }
 216
 217 /**
 218  * Build a table to translate packet to checksum type of Verbs.
 219  */
 220 void
 221 mlx5_set_cksum_table(void)
 222 {
 223         unsigned int i;
 224         uint8_t v;
 225
 226         /*
 227          * The index should have:
 228          * bit[0] = PKT_TX_TCP_SEG
 229          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 230          * bit[4] = PKT_TX_IP_CKSUM
 231          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 232          * bit[9] = tunnel
 233          */
 234         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 235                 v = 0;
 236                 if (i & (1 << 9)) {
 237                         /* Tunneled packet. */
 238                         if (i & (1 << 8)) /* Outer IP. */
 239                                 v |= MLX5_ETH_WQE_L3_CSUM;
 240                         if (i & (1 << 4)) /* Inner IP. */
 241                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 242                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 243                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 244                 } else {
 245                         /* No tunnel. */
 246                         if (i & (1 << 4)) /* IP. */
 247                                 v |= MLX5_ETH_WQE_L3_CSUM;
 248                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 249                                 v |= MLX5_ETH_WQE_L4_CSUM;
 250                 }
 251                 mlx5_cksum_table[i] = v;
 252         }
 253 }
 254
 255 /**
 256  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 257  */
 258 void
 259 mlx5_set_swp_types_table(void)
 260 {
 261         unsigned int i;
 262         uint8_t v;
 263
 264         /*
 265          * The index should have:
 266          * bit[0:1] = PKT_TX_L4_MASK
 267          * bit[4] = PKT_TX_IPV6
 268          * bit[8] = PKT_TX_OUTER_IPV6
 269          * bit[9] = PKT_TX_OUTER_UDP
 270          */
 271         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 272                 v = 0;
 273                 if (i & (1 << 8))
 274                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 275                 if (i & (1 << 9))
 276                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 277                 if (i & (1 << 4))
 278                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 279                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 280                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 281                 mlx5_swp_types_table[i] = v;
 282         }
 283 }
 284
 285 /**
 286  * Return the size of tailroom of WQ.
 287  *
 288  * @param txq
 289  *   Pointer to TX queue structure.
 290  * @param addr
 291  *   Pointer to tail of WQ.
 292  *
 293  * @return
 294  *   Size of tailroom.
 295  */
 296 static inline size_t
 297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 298 {
 299         size_t tailroom;
 300         tailroom = (uintptr_t)(txq->wqes) +
 301                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 302                    (uintptr_t)addr;
 303         return tailroom;
 304 }
 305
 306 /**
 307  * Copy data to tailroom of circular queue.
 308  *
 309  * @param dst
 310  *   Pointer to destination.
 311  * @param src
 312  *   Pointer to source.
 313  * @param n
 314  *   Number of bytes to copy.
 315  * @param base
 316  *   Pointer to head of queue.
 317  * @param tailroom
 318  *   Size of tailroom from dst.
 319  *
 320  * @return
 321  *   Pointer after copied data.
 322  */
 323 static inline void *
 324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 325                 void *base, size_t tailroom)
 326 {
 327         void *ret;
 328
 329         if (n > tailroom) {
 330                 rte_memcpy(dst, src, tailroom);
 331                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 332                            n - tailroom);
 333                 ret = (uint8_t *)base + n - tailroom;
 334         } else {
 335                 rte_memcpy(dst, src, n);
 336                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 337         }
 338         return ret;
 339 }
 340
 341 /**
 342  * Inline TSO headers into WQE.
 343  *
 344  * @return
 345  *   0 on success, negative errno value on failure.
 346  */
 347 static int
 348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 349            uint32_t *length,
 350            uintptr_t *addr,
 351            uint16_t *pkt_inline_sz,
 352            uint8_t **raw,
 353            uint16_t *max_wqe,
 354            uint16_t *tso_segsz,
 355            uint16_t *tso_header_sz)
 356 {
 357         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 358                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 359         unsigned int copy_b;
 360         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 361         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 362                                  PKT_TX_TUNNEL_MASK);
 363         uint16_t n_wqe;
 364
 365         *tso_segsz = buf->tso_segsz;
 366         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 367         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 368                 txq->stats.oerrors++;
 369                 return -EINVAL;
 370         }
 371         if (tunneled)
 372                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 373         /* First seg must contain all TSO headers. */
 374         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 375                      *tso_header_sz > DATA_LEN(buf)) {
 376                 txq->stats.oerrors++;
 377                 return -EINVAL;
 378         }
 379         copy_b = *tso_header_sz - *pkt_inline_sz;
 380         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 381                 return -EAGAIN;
 382         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 383         if (unlikely(*max_wqe < n_wqe))
 384                 return -EINVAL;
 385         *max_wqe -= n_wqe;
 386         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 387         *length -= copy_b;
 388         *addr += copy_b;
 389         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 390         *pkt_inline_sz += copy_b;
 391         *raw += copy_b;
 392         return 0;
 393 }
 394
 395 /**
 396  * DPDK callback to check the status of a tx descriptor.
 397  *
 398  * @param tx_queue
 399  *   The tx queue.
 400  * @param[in] offset
 401  *   The index of the descriptor in the ring.
 402  *
 403  * @return
 404  *   The status of the tx descriptor.
 405  */
 406 int
 407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 408 {
 409         struct mlx5_txq_data *txq = tx_queue;
 410         uint16_t used;
 411
 412         mlx5_tx_complete(txq);
 413         used = txq->elts_head - txq->elts_tail;
 414         if (offset < used)
 415                 return RTE_ETH_TX_DESC_FULL;
 416         return RTE_ETH_TX_DESC_DONE;
 417 }
 418
 419 /**
 420  * Internal function to compute the number of used descriptors in an RX queue
 421  *
 422  * @param rxq
 423  *   The Rx queue.
 424  *
 425  * @return
 426  *   The number of used rx descriptor.
 427  */
 428 static uint32_t
 429 rx_queue_count(struct mlx5_rxq_data *rxq)
 430 {
 431         struct rxq_zip *zip = &rxq->zip;
 432         volatile struct mlx5_cqe *cqe;
 433         const unsigned int cqe_n = (1 << rxq->cqe_n);
 434         const unsigned int cqe_cnt = cqe_n - 1;
 435         unsigned int cq_ci;
 436         unsigned int used;
 437
 438         /* if we are processing a compressed cqe */
 439         if (zip->ai) {
 440                 used = zip->cqe_cnt - zip->ca;
 441                 cq_ci = zip->cq_ci;
 442         } else {
 443                 used = 0;
 444                 cq_ci = rxq->cq_ci;
 445         }
 446         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 447         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 448                 int8_t op_own;
 449                 unsigned int n;
 450
 451                 op_own = cqe->op_own;
 452                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 453                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 454                 else
 455                         n = 1;
 456                 cq_ci += n;
 457                 used += n;
 458                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 459         }
 460         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 461         return used;
 462 }
 463
 464 /**
 465  * DPDK callback to check the status of a rx descriptor.
 466  *
 467  * @param rx_queue
 468  *   The Rx queue.
 469  * @param[in] offset
 470  *   The index of the descriptor in the ring.
 471  *
 472  * @return
 473  *   The status of the tx descriptor.
 474  */
 475 int
 476 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 477 {
 478         struct mlx5_rxq_data *rxq = rx_queue;
 479         struct mlx5_rxq_ctrl *rxq_ctrl =
 480                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 481         struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
 482
 483         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 484                 rte_errno = ENOTSUP;
 485                 return -rte_errno;
 486         }
 487         if (offset >= (1 << rxq->elts_n)) {
 488                 rte_errno = EINVAL;
 489                 return -rte_errno;
 490         }
 491         if (offset < rx_queue_count(rxq))
 492                 return RTE_ETH_RX_DESC_DONE;
 493         return RTE_ETH_RX_DESC_AVAIL;
 494 }
 495
 496 /**
 497  * DPDK callback to get the number of used descriptors in a RX queue
 498  *
 499  * @param dev
 500  *   Pointer to the device structure.
 501  *
 502  * @param rx_queue_id
 503  *   The Rx queue.
 504  *
 505  * @return
 506  *   The number of used rx descriptor.
 507  *   -EINVAL if the queue is invalid
 508  */
 509 uint32_t
 510 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 511 {
 512         struct priv *priv = dev->data->dev_private;
 513         struct mlx5_rxq_data *rxq;
 514
 515         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 516                 rte_errno = ENOTSUP;
 517                 return -rte_errno;
 518         }
 519         rxq = (*priv->rxqs)[rx_queue_id];
 520         if (!rxq) {
 521                 rte_errno = EINVAL;
 522                 return -rte_errno;
 523         }
 524         return rx_queue_count(rxq);
 525 }
 526
 527 /**
 528  * DPDK callback for TX.
 529  *
 530  * @param dpdk_txq
 531  *   Generic pointer to TX queue structure.
 532  * @param[in] pkts
 533  *   Packets to transmit.
 534  * @param pkts_n
 535  *   Number of packets in array.
 536  *
 537  * @return
 538  *   Number of packets successfully transmitted (<= pkts_n).
 539  */
 540 uint16_t
 541 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 542 {
 543         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 544         uint16_t elts_head = txq->elts_head;
 545         const uint16_t elts_n = 1 << txq->elts_n;
 546         const uint16_t elts_m = elts_n - 1;
 547         unsigned int i = 0;
 548         unsigned int j = 0;
 549         unsigned int k = 0;
 550         uint16_t max_elts;
 551         uint16_t max_wqe;
 552         unsigned int comp;
 553         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 554         unsigned int segs_n = 0;
 555         const unsigned int max_inline = txq->max_inline;
 556         uint64_t addr_64;
 557
 558         if (unlikely(!pkts_n))
 559                 return 0;
 560         /* Prefetch first packet cacheline. */
 561         rte_prefetch0(*pkts);
 562         /* Start processing. */
 563         mlx5_tx_complete(txq);
 564         max_elts = (elts_n - (elts_head - txq->elts_tail));
 565         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 566         if (unlikely(!max_wqe))
 567                 return 0;
 568         do {
 569                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 570                 uint8_t *raw;
 571                 volatile struct mlx5_wqe_v *wqe = NULL;
 572                 volatile rte_v128u32_t *dseg = NULL;
 573                 uint32_t length;
 574                 unsigned int ds = 0;
 575                 unsigned int sg = 0; /* counter of additional segs attached. */
 576                 uintptr_t addr;
 577                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 578                 uint16_t tso_header_sz = 0;
 579                 uint16_t ehdr;
 580                 uint8_t cs_flags;
 581                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 582                 uint32_t swp_offsets = 0;
 583                 uint8_t swp_types = 0;
 584                 rte_be32_t metadata;
 585                 uint16_t tso_segsz = 0;
 586 #ifdef MLX5_PMD_SOFT_COUNTERS
 587                 uint32_t total_length = 0;
 588 #endif
 589                 int ret;
 590
 591                 segs_n = buf->nb_segs;
 592                 /*
 593                  * Make sure there is enough room to store this packet and
 594                  * that one ring entry remains unused.
 595                  */
 596                 assert(segs_n);
 597                 if (max_elts < segs_n)
 598                         break;
 599                 max_elts -= segs_n;
 600                 sg = --segs_n;
 601                 if (unlikely(--max_wqe == 0))
 602                         break;
 603                 wqe = (volatile struct mlx5_wqe_v *)
 604                         tx_mlx5_wqe(txq, txq->wqe_ci);
 605                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 606                 if (pkts_n - i > 1)
 607                         rte_prefetch0(*(pkts + 1));
 608                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 609                 length = DATA_LEN(buf);
 610                 ehdr = (((uint8_t *)addr)[1] << 8) |
 611                        ((uint8_t *)addr)[0];
 612 #ifdef MLX5_PMD_SOFT_COUNTERS
 613                 total_length = length;
 614 #endif
 615                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 616                         txq->stats.oerrors++;
 617                         break;
 618                 }
 619                 /* Update element. */
 620                 (*txq->elts)[elts_head & elts_m] = buf;
 621                 /* Prefetch next buffer data. */
 622                 if (pkts_n - i > 1)
 623                         rte_prefetch0(
 624                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 625                 cs_flags = txq_ol_cksum_to_cs(buf);
 626                 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
 627                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 628                 /* Copy metadata from mbuf if valid */
 629                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
 630                                                              0;
 631                 /* Replace the Ethernet type by the VLAN if necessary. */
 632                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 633                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 634                                                          buf->vlan_tci);
 635                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 636
 637                         addr += 2;
 638                         length -= 2;
 639                         /* Copy Destination and source mac address. */
 640                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 641                         /* Copy VLAN. */
 642                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 643                         /* Copy missing two bytes to end the DSeg. */
 644                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 645                                ((uint8_t *)addr) + len, 2);
 646                         addr += len + 2;
 647                         length -= (len + 2);
 648                 } else {
 649                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 650                                MLX5_WQE_DWORD_SIZE);
 651                         length -= pkt_inline_sz;
 652                         addr += pkt_inline_sz;
 653                 }
 654                 raw += MLX5_WQE_DWORD_SIZE;
 655                 if (tso) {
 656                         ret = inline_tso(txq, buf, &length,
 657                                          &addr, &pkt_inline_sz,
 658                                          &raw, &max_wqe,
 659                                          &tso_segsz, &tso_header_sz);
 660                         if (ret == -EINVAL) {
 661                                 break;
 662                         } else if (ret == -EAGAIN) {
 663                                 /* NOP WQE. */
 664                                 wqe->ctrl = (rte_v128u32_t){
 665                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 666                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 667                                         0,
 668                                         0,
 669                                 };
 670                                 ds = 1;
 671 #ifdef MLX5_PMD_SOFT_COUNTERS
 672                                 total_length = 0;
 673 #endif
 674                                 k++;
 675                                 goto next_wqe;
 676                         }
 677                 }
 678                 /* Inline if enough room. */
 679                 if (max_inline || tso) {
 680                         uint32_t inl = 0;
 681                         uintptr_t end = (uintptr_t)
 682                                 (((uintptr_t)txq->wqes) +
 683                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 684                         unsigned int inline_room = max_inline *
 685                                                    RTE_CACHE_LINE_SIZE -
 686                                                    (pkt_inline_sz - 2) -
 687                                                    !!tso * sizeof(inl);
 688                         uintptr_t addr_end;
 689                         unsigned int copy_b;
 690
 691 pkt_inline:
 692                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 693                                                    RTE_CACHE_LINE_SIZE);
 694                         copy_b = (addr_end > addr) ?
 695                                  RTE_MIN((addr_end - addr), length) : 0;
 696                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 697                                 /*
 698                                  * One Dseg remains in the current WQE.  To
 699                                  * keep the computation positive, it is
 700                                  * removed after the bytes to Dseg conversion.
 701                                  */
 702                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 703
 704                                 if (unlikely(max_wqe < n))
 705                                         break;
 706                                 max_wqe -= n;
 707                                 if (tso) {
 708                                         assert(inl == 0);
 709                                         inl = rte_cpu_to_be_32(copy_b |
 710                                                                MLX5_INLINE_SEG);
 711                                         rte_memcpy((void *)raw,
 712                                                    (void *)&inl, sizeof(inl));
 713                                         raw += sizeof(inl);
 714                                         pkt_inline_sz += sizeof(inl);
 715                                 }
 716                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 717                                 addr += copy_b;
 718                                 length -= copy_b;
 719                                 pkt_inline_sz += copy_b;
 720                         }
 721                         /*
 722                          * 2 DWORDs consumed by the WQE header + ETH segment +
 723                          * the size of the inline part of the packet.
 724                          */
 725                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 726                         if (length > 0) {
 727                                 if (ds % (MLX5_WQE_SIZE /
 728                                           MLX5_WQE_DWORD_SIZE) == 0) {
 729                                         if (unlikely(--max_wqe == 0))
 730                                                 break;
 731                                         dseg = (volatile rte_v128u32_t *)
 732                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 733                                                            ds / 4);
 734                                 } else {
 735                                         dseg = (volatile rte_v128u32_t *)
 736                                                 ((uintptr_t)wqe +
 737                                                  (ds * MLX5_WQE_DWORD_SIZE));
 738                                 }
 739                                 goto use_dseg;
 740                         } else if (!segs_n) {
 741                                 goto next_pkt;
 742                         } else {
 743                                 /*
 744                                  * Further inline the next segment only for
 745                                  * non-TSO packets.
 746                                  */
 747                                 if (!tso) {
 748                                         raw += copy_b;
 749                                         inline_room -= copy_b;
 750                                 } else {
 751                                         inline_room = 0;
 752                                 }
 753                                 /* Move to the next segment. */
 754                                 --segs_n;
 755                                 buf = buf->next;
 756                                 assert(buf);
 757                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 758                                 length = DATA_LEN(buf);
 759 #ifdef MLX5_PMD_SOFT_COUNTERS
 760                                 total_length += length;
 761 #endif
 762                                 (*txq->elts)[++elts_head & elts_m] = buf;
 763                                 goto pkt_inline;
 764                         }
 765                 } else {
 766                         /*
 767                          * No inline has been done in the packet, only the
 768                          * Ethernet Header as been stored.
 769                          */
 770                         dseg = (volatile rte_v128u32_t *)
 771                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 772                         ds = 3;
 773 use_dseg:
 774                         /* Add the remaining packet as a simple ds. */
 775                         addr_64 = rte_cpu_to_be_64(addr);
 776                         *dseg = (rte_v128u32_t){
 777                                 rte_cpu_to_be_32(length),
 778                                 mlx5_tx_mb2mr(txq, buf),
 779                                 addr_64,
 780                                 addr_64 >> 32,
 781                         };
 782                         ++ds;
 783                         if (!segs_n)
 784                                 goto next_pkt;
 785                 }
 786 next_seg:
 787                 assert(buf);
 788                 assert(ds);
 789                 assert(wqe);
 790                 /*
 791                  * Spill on next WQE when the current one does not have
 792                  * enough room left. Size of WQE must a be a multiple
 793                  * of data segment size.
 794                  */
 795                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 796                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 797                         if (unlikely(--max_wqe == 0))
 798                                 break;
 799                         dseg = (volatile rte_v128u32_t *)
 800                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 801                         rte_prefetch0(tx_mlx5_wqe(txq,
 802                                                   txq->wqe_ci + ds / 4 + 1));
 803                 } else {
 804                         ++dseg;
 805                 }
 806                 ++ds;
 807                 buf = buf->next;
 808                 assert(buf);
 809                 length = DATA_LEN(buf);
 810 #ifdef MLX5_PMD_SOFT_COUNTERS
 811                 total_length += length;
 812 #endif
 813                 /* Store segment information. */
 814                 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 815                 *dseg = (rte_v128u32_t){
 816                         rte_cpu_to_be_32(length),
 817                         mlx5_tx_mb2mr(txq, buf),
 818                         addr_64,
 819                         addr_64 >> 32,
 820                 };
 821                 (*txq->elts)[++elts_head & elts_m] = buf;
 822                 if (--segs_n)
 823                         goto next_seg;
 824 next_pkt:
 825                 if (ds > MLX5_DSEG_MAX) {
 826                         txq->stats.oerrors++;
 827                         break;
 828                 }
 829                 ++elts_head;
 830                 ++pkts;
 831                 ++i;
 832                 j += sg;
 833                 /* Initialize known and common part of the WQE structure. */
 834                 if (tso) {
 835                         wqe->ctrl = (rte_v128u32_t){
 836                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 837                                                  MLX5_OPCODE_TSO),
 838                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 839                                 0,
 840                                 0,
 841                         };
 842                         wqe->eseg = (rte_v128u32_t){
 843                                 swp_offsets,
 844                                 cs_flags | (swp_types << 8) |
 845                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 846                                 metadata,
 847                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 848                         };
 849                 } else {
 850                         wqe->ctrl = (rte_v128u32_t){
 851                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 852                                                  MLX5_OPCODE_SEND),
 853                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 854                                 0,
 855                                 0,
 856                         };
 857                         wqe->eseg = (rte_v128u32_t){
 858                                 swp_offsets,
 859                                 cs_flags | (swp_types << 8),
 860                                 metadata,
 861                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 862                         };
 863                 }
 864 next_wqe:
 865                 txq->wqe_ci += (ds + 3) / 4;
 866                 /* Save the last successful WQE for completion request */
 867                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 868 #ifdef MLX5_PMD_SOFT_COUNTERS
 869                 /* Increment sent bytes counter. */
 870                 txq->stats.obytes += total_length;
 871 #endif
 872         } while (i < pkts_n);
 873         /* Take a shortcut if nothing must be sent. */
 874         if (unlikely((i + k) == 0))
 875                 return 0;
 876         txq->elts_head += (i + j);
 877         /* Check whether completion threshold has been reached. */
 878         comp = txq->elts_comp + i + j + k;
 879         if (comp >= MLX5_TX_COMP_THRESH) {
 880                 /* A CQE slot must always be available. */
 881                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
 882                 /* Request completion on last WQE. */
 883                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 884                 /* Save elts_head in unused "immediate" field of WQE. */
 885                 last_wqe->ctrl3 = txq->elts_head;
 886                 txq->elts_comp = 0;
 887         } else {
 888                 txq->elts_comp = comp;
 889         }
 890 #ifdef MLX5_PMD_SOFT_COUNTERS
 891         /* Increment sent packets counter. */
 892         txq->stats.opackets += i;
 893 #endif
 894         /* Ring QP doorbell. */
 895         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 896         return i;
 897 }
 898
 899 /**
 900  * Open a MPW session.
 901  *
 902  * @param txq
 903  *   Pointer to TX queue structure.
 904  * @param mpw
 905  *   Pointer to MPW session structure.
 906  * @param length
 907  *   Packet length.
 908  */
 909 static inline void
 910 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 911 {
 912         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 913         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 914                 (volatile struct mlx5_wqe_data_seg (*)[])
 915                 tx_mlx5_wqe(txq, idx + 1);
 916
 917         mpw->state = MLX5_MPW_STATE_OPENED;
 918         mpw->pkts_n = 0;
 919         mpw->len = length;
 920         mpw->total_len = 0;
 921         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 922         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 923         mpw->wqe->eseg.inline_hdr_sz = 0;
 924         mpw->wqe->eseg.rsvd0 = 0;
 925         mpw->wqe->eseg.rsvd1 = 0;
 926         mpw->wqe->eseg.flow_table_metadata = 0;
 927         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 928                                              (txq->wqe_ci << 8) |
 929                                              MLX5_OPCODE_TSO);
 930         mpw->wqe->ctrl[2] = 0;
 931         mpw->wqe->ctrl[3] = 0;
 932         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 933                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 934         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 935                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 936         mpw->data.dseg[2] = &(*dseg)[0];
 937         mpw->data.dseg[3] = &(*dseg)[1];
 938         mpw->data.dseg[4] = &(*dseg)[2];
 939 }
 940
 941 /**
 942  * Close a MPW session.
 943  *
 944  * @param txq
 945  *   Pointer to TX queue structure.
 946  * @param mpw
 947  *   Pointer to MPW session structure.
 948  */
 949 static inline void
 950 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 951 {
 952         unsigned int num = mpw->pkts_n;
 953
 954         /*
 955          * Store size in multiple of 16 bytes. Control and Ethernet segments
 956          * count as 2.
 957          */
 958         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 959         mpw->state = MLX5_MPW_STATE_CLOSED;
 960         if (num < 3)
 961                 ++txq->wqe_ci;
 962         else
 963                 txq->wqe_ci += 2;
 964         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 965         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 966 }
 967
 968 /**
 969  * DPDK callback for TX with MPW support.
 970  *
 971  * @param dpdk_txq
 972  *   Generic pointer to TX queue structure.
 973  * @param[in] pkts
 974  *   Packets to transmit.
 975  * @param pkts_n
 976  *   Number of packets in array.
 977  *
 978  * @return
 979  *   Number of packets successfully transmitted (<= pkts_n).
 980  */
 981 uint16_t
 982 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 983 {
 984         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 985         uint16_t elts_head = txq->elts_head;
 986         const uint16_t elts_n = 1 << txq->elts_n;
 987         const uint16_t elts_m = elts_n - 1;
 988         unsigned int i = 0;
 989         unsigned int j = 0;
 990         uint16_t max_elts;
 991         uint16_t max_wqe;
 992         unsigned int comp;
 993         struct mlx5_mpw mpw = {
 994                 .state = MLX5_MPW_STATE_CLOSED,
 995         };
 996
 997         if (unlikely(!pkts_n))
 998                 return 0;
 999         /* Prefetch first packet cacheline. */
1000         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1001         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1002         /* Start processing. */
1003         mlx5_tx_complete(txq);
1004         max_elts = (elts_n - (elts_head - txq->elts_tail));
1005         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1006         if (unlikely(!max_wqe))
1007                 return 0;
1008         do {
1009                 struct rte_mbuf *buf = *(pkts++);
1010                 uint32_t length;
1011                 unsigned int segs_n = buf->nb_segs;
1012                 uint32_t cs_flags;
1013                 rte_be32_t metadata;
1014
1015                 /*
1016                  * Make sure there is enough room to store this packet and
1017                  * that one ring entry remains unused.
1018                  */
1019                 assert(segs_n);
1020                 if (max_elts < segs_n)
1021                         break;
1022                 /* Do not bother with large packets MPW cannot handle. */
1023                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1024                         txq->stats.oerrors++;
1025                         break;
1026                 }
1027                 max_elts -= segs_n;
1028                 --pkts_n;
1029                 cs_flags = txq_ol_cksum_to_cs(buf);
1030                 /* Copy metadata from mbuf if valid */
1031                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1032                                                              0;
1033                 /* Retrieve packet information. */
1034                 length = PKT_LEN(buf);
1035                 assert(length);
1036                 /* Start new session if packet differs. */
1037                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1038                     ((mpw.len != length) ||
1039                      (segs_n != 1) ||
1040                      (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1041                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1042                         mlx5_mpw_close(txq, &mpw);
1043                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1044                         /*
1045                          * Multi-Packet WQE consumes at most two WQE.
1046                          * mlx5_mpw_new() expects to be able to use such
1047                          * resources.
1048                          */
1049                         if (unlikely(max_wqe < 2))
1050                                 break;
1051                         max_wqe -= 2;
1052                         mlx5_mpw_new(txq, &mpw, length);
1053                         mpw.wqe->eseg.cs_flags = cs_flags;
1054                         mpw.wqe->eseg.flow_table_metadata = metadata;
1055                 }
1056                 /* Multi-segment packets must be alone in their MPW. */
1057                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1058 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1059                 length = 0;
1060 #endif
1061                 do {
1062                         volatile struct mlx5_wqe_data_seg *dseg;
1063                         uintptr_t addr;
1064
1065                         assert(buf);
1066                         (*txq->elts)[elts_head++ & elts_m] = buf;
1067                         dseg = mpw.data.dseg[mpw.pkts_n];
1068                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1069                         *dseg = (struct mlx5_wqe_data_seg){
1070                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1071                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1072                                 .addr = rte_cpu_to_be_64(addr),
1073                         };
1074 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1075                         length += DATA_LEN(buf);
1076 #endif
1077                         buf = buf->next;
1078                         ++mpw.pkts_n;
1079                         ++j;
1080                 } while (--segs_n);
1081                 assert(length == mpw.len);
1082                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1083                         mlx5_mpw_close(txq, &mpw);
1084 #ifdef MLX5_PMD_SOFT_COUNTERS
1085                 /* Increment sent bytes counter. */
1086                 txq->stats.obytes += length;
1087 #endif
1088                 ++i;
1089         } while (pkts_n);
1090         /* Take a shortcut if nothing must be sent. */
1091         if (unlikely(i == 0))
1092                 return 0;
1093         /* Check whether completion threshold has been reached. */
1094         /* "j" includes both packets and segments. */
1095         comp = txq->elts_comp + j;
1096         if (comp >= MLX5_TX_COMP_THRESH) {
1097                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1098
1099                 /* A CQE slot must always be available. */
1100                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1101                 /* Request completion on last WQE. */
1102                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1103                 /* Save elts_head in unused "immediate" field of WQE. */
1104                 wqe->ctrl[3] = elts_head;
1105                 txq->elts_comp = 0;
1106         } else {
1107                 txq->elts_comp = comp;
1108         }
1109 #ifdef MLX5_PMD_SOFT_COUNTERS
1110         /* Increment sent packets counter. */
1111         txq->stats.opackets += i;
1112 #endif
1113         /* Ring QP doorbell. */
1114         if (mpw.state == MLX5_MPW_STATE_OPENED)
1115                 mlx5_mpw_close(txq, &mpw);
1116         mlx5_tx_dbrec(txq, mpw.wqe);
1117         txq->elts_head = elts_head;
1118         return i;
1119 }
1120
1121 /**
1122  * Open a MPW inline session.
1123  *
1124  * @param txq
1125  *   Pointer to TX queue structure.
1126  * @param mpw
1127  *   Pointer to MPW session structure.
1128  * @param length
1129  *   Packet length.
1130  */
1131 static inline void
1132 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1133                     uint32_t length)
1134 {
1135         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1136         struct mlx5_wqe_inl_small *inl;
1137
1138         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1139         mpw->pkts_n = 0;
1140         mpw->len = length;
1141         mpw->total_len = 0;
1142         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1143         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1144                                              (txq->wqe_ci << 8) |
1145                                              MLX5_OPCODE_TSO);
1146         mpw->wqe->ctrl[2] = 0;
1147         mpw->wqe->ctrl[3] = 0;
1148         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1149         mpw->wqe->eseg.inline_hdr_sz = 0;
1150         mpw->wqe->eseg.cs_flags = 0;
1151         mpw->wqe->eseg.rsvd0 = 0;
1152         mpw->wqe->eseg.rsvd1 = 0;
1153         mpw->wqe->eseg.flow_table_metadata = 0;
1154         inl = (struct mlx5_wqe_inl_small *)
1155                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1156         mpw->data.raw = (uint8_t *)&inl->raw;
1157 }
1158
1159 /**
1160  * Close a MPW inline session.
1161  *
1162  * @param txq
1163  *   Pointer to TX queue structure.
1164  * @param mpw
1165  *   Pointer to MPW session structure.
1166  */
1167 static inline void
1168 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1169 {
1170         unsigned int size;
1171         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1172                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1173
1174         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1175         /*
1176          * Store size in multiple of 16 bytes. Control and Ethernet segments
1177          * count as 2.
1178          */
1179         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1180                                              MLX5_WQE_DS(size));
1181         mpw->state = MLX5_MPW_STATE_CLOSED;
1182         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1183         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1184 }
1185
1186 /**
1187  * DPDK callback for TX with MPW inline support.
1188  *
1189  * @param dpdk_txq
1190  *   Generic pointer to TX queue structure.
1191  * @param[in] pkts
1192  *   Packets to transmit.
1193  * @param pkts_n
1194  *   Number of packets in array.
1195  *
1196  * @return
1197  *   Number of packets successfully transmitted (<= pkts_n).
1198  */
1199 uint16_t
1200 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1201                          uint16_t pkts_n)
1202 {
1203         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1204         uint16_t elts_head = txq->elts_head;
1205         const uint16_t elts_n = 1 << txq->elts_n;
1206         const uint16_t elts_m = elts_n - 1;
1207         unsigned int i = 0;
1208         unsigned int j = 0;
1209         uint16_t max_elts;
1210         uint16_t max_wqe;
1211         unsigned int comp;
1212         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1213         struct mlx5_mpw mpw = {
1214                 .state = MLX5_MPW_STATE_CLOSED,
1215         };
1216         /*
1217          * Compute the maximum number of WQE which can be consumed by inline
1218          * code.
1219          * - 2 DSEG for:
1220          *   - 1 control segment,
1221          *   - 1 Ethernet segment,
1222          * - N Dseg from the inline request.
1223          */
1224         const unsigned int wqe_inl_n =
1225                 ((2 * MLX5_WQE_DWORD_SIZE +
1226                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1227                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1228
1229         if (unlikely(!pkts_n))
1230                 return 0;
1231         /* Prefetch first packet cacheline. */
1232         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1233         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1234         /* Start processing. */
1235         mlx5_tx_complete(txq);
1236         max_elts = (elts_n - (elts_head - txq->elts_tail));
1237         do {
1238                 struct rte_mbuf *buf = *(pkts++);
1239                 uintptr_t addr;
1240                 uint32_t length;
1241                 unsigned int segs_n = buf->nb_segs;
1242                 uint8_t cs_flags;
1243                 rte_be32_t metadata;
1244
1245                 /*
1246                  * Make sure there is enough room to store this packet and
1247                  * that one ring entry remains unused.
1248                  */
1249                 assert(segs_n);
1250                 if (max_elts < segs_n)
1251                         break;
1252                 /* Do not bother with large packets MPW cannot handle. */
1253                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1254                         txq->stats.oerrors++;
1255                         break;
1256                 }
1257                 max_elts -= segs_n;
1258                 --pkts_n;
1259                 /*
1260                  * Compute max_wqe in case less WQE were consumed in previous
1261                  * iteration.
1262                  */
1263                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1264                 cs_flags = txq_ol_cksum_to_cs(buf);
1265                 /* Copy metadata from mbuf if valid */
1266                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1267                                                              0;
1268                 /* Retrieve packet information. */
1269                 length = PKT_LEN(buf);
1270                 /* Start new session if packet differs. */
1271                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1272                         if ((mpw.len != length) ||
1273                             (segs_n != 1) ||
1274                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1275                             (mpw.wqe->eseg.cs_flags != cs_flags))
1276                                 mlx5_mpw_close(txq, &mpw);
1277                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1278                         if ((mpw.len != length) ||
1279                             (segs_n != 1) ||
1280                             (length > inline_room) ||
1281                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1282                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1283                                 mlx5_mpw_inline_close(txq, &mpw);
1284                                 inline_room =
1285                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1286                         }
1287                 }
1288                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1289                         if ((segs_n != 1) ||
1290                             (length > inline_room)) {
1291                                 /*
1292                                  * Multi-Packet WQE consumes at most two WQE.
1293                                  * mlx5_mpw_new() expects to be able to use
1294                                  * such resources.
1295                                  */
1296                                 if (unlikely(max_wqe < 2))
1297                                         break;
1298                                 max_wqe -= 2;
1299                                 mlx5_mpw_new(txq, &mpw, length);
1300                                 mpw.wqe->eseg.cs_flags = cs_flags;
1301                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1302                         } else {
1303                                 if (unlikely(max_wqe < wqe_inl_n))
1304                                         break;
1305                                 max_wqe -= wqe_inl_n;
1306                                 mlx5_mpw_inline_new(txq, &mpw, length);
1307                                 mpw.wqe->eseg.cs_flags = cs_flags;
1308                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1309                         }
1310                 }
1311                 /* Multi-segment packets must be alone in their MPW. */
1312                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1313                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1314                         assert(inline_room ==
1315                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1316 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1317                         length = 0;
1318 #endif
1319                         do {
1320                                 volatile struct mlx5_wqe_data_seg *dseg;
1321
1322                                 assert(buf);
1323                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1324                                 dseg = mpw.data.dseg[mpw.pkts_n];
1325                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1326                                 *dseg = (struct mlx5_wqe_data_seg){
1327                                         .byte_count =
1328                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1329                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1330                                         .addr = rte_cpu_to_be_64(addr),
1331                                 };
1332 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1333                                 length += DATA_LEN(buf);
1334 #endif
1335                                 buf = buf->next;
1336                                 ++mpw.pkts_n;
1337                                 ++j;
1338                         } while (--segs_n);
1339                         assert(length == mpw.len);
1340                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1341                                 mlx5_mpw_close(txq, &mpw);
1342                 } else {
1343                         unsigned int max;
1344
1345                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1346                         assert(length <= inline_room);
1347                         assert(length == DATA_LEN(buf));
1348                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1349                         (*txq->elts)[elts_head++ & elts_m] = buf;
1350                         /* Maximum number of bytes before wrapping. */
1351                         max = ((((uintptr_t)(txq->wqes)) +
1352                                 (1 << txq->wqe_n) *
1353                                 MLX5_WQE_SIZE) -
1354                                (uintptr_t)mpw.data.raw);
1355                         if (length > max) {
1356                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1357                                            (void *)addr,
1358                                            max);
1359                                 mpw.data.raw = (volatile void *)txq->wqes;
1360                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1361                                            (void *)(addr + max),
1362                                            length - max);
1363                                 mpw.data.raw += length - max;
1364                         } else {
1365                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1366                                            (void *)addr,
1367                                            length);
1368
1369                                 if (length == max)
1370                                         mpw.data.raw =
1371                                                 (volatile void *)txq->wqes;
1372                                 else
1373                                         mpw.data.raw += length;
1374                         }
1375                         ++mpw.pkts_n;
1376                         mpw.total_len += length;
1377                         ++j;
1378                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1379                                 mlx5_mpw_inline_close(txq, &mpw);
1380                                 inline_room =
1381                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1382                         } else {
1383                                 inline_room -= length;
1384                         }
1385                 }
1386 #ifdef MLX5_PMD_SOFT_COUNTERS
1387                 /* Increment sent bytes counter. */
1388                 txq->stats.obytes += length;
1389 #endif
1390                 ++i;
1391         } while (pkts_n);
1392         /* Take a shortcut if nothing must be sent. */
1393         if (unlikely(i == 0))
1394                 return 0;
1395         /* Check whether completion threshold has been reached. */
1396         /* "j" includes both packets and segments. */
1397         comp = txq->elts_comp + j;
1398         if (comp >= MLX5_TX_COMP_THRESH) {
1399                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1400
1401                 /* A CQE slot must always be available. */
1402                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1403                 /* Request completion on last WQE. */
1404                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1405                 /* Save elts_head in unused "immediate" field of WQE. */
1406                 wqe->ctrl[3] = elts_head;
1407                 txq->elts_comp = 0;
1408         } else {
1409                 txq->elts_comp = comp;
1410         }
1411 #ifdef MLX5_PMD_SOFT_COUNTERS
1412         /* Increment sent packets counter. */
1413         txq->stats.opackets += i;
1414 #endif
1415         /* Ring QP doorbell. */
1416         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1417                 mlx5_mpw_inline_close(txq, &mpw);
1418         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1419                 mlx5_mpw_close(txq, &mpw);
1420         mlx5_tx_dbrec(txq, mpw.wqe);
1421         txq->elts_head = elts_head;
1422         return i;
1423 }
1424
1425 /**
1426  * Open an Enhanced MPW session.
1427  *
1428  * @param txq
1429  *   Pointer to TX queue structure.
1430  * @param mpw
1431  *   Pointer to MPW session structure.
1432  * @param length
1433  *   Packet length.
1434  */
1435 static inline void
1436 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1437 {
1438         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1439
1440         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1441         mpw->pkts_n = 0;
1442         mpw->total_len = sizeof(struct mlx5_wqe);
1443         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1444         mpw->wqe->ctrl[0] =
1445                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1446                                  (txq->wqe_ci << 8) |
1447                                  MLX5_OPCODE_ENHANCED_MPSW);
1448         mpw->wqe->ctrl[2] = 0;
1449         mpw->wqe->ctrl[3] = 0;
1450         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1451         if (unlikely(padding)) {
1452                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1453
1454                 /* Pad the first 2 DWORDs with zero-length inline header. */
1455                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1456                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1457                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1458                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1459                 /* Start from the next WQEBB. */
1460                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1461         } else {
1462                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1463         }
1464 }
1465
1466 /**
1467  * Close an Enhanced MPW session.
1468  *
1469  * @param txq
1470  *   Pointer to TX queue structure.
1471  * @param mpw
1472  *   Pointer to MPW session structure.
1473  *
1474  * @return
1475  *   Number of consumed WQEs.
1476  */
1477 static inline uint16_t
1478 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1479 {
1480         uint16_t ret;
1481
1482         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1483          * count as 2.
1484          */
1485         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1486                                              MLX5_WQE_DS(mpw->total_len));
1487         mpw->state = MLX5_MPW_STATE_CLOSED;
1488         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1489         txq->wqe_ci += ret;
1490         return ret;
1491 }
1492
1493 /**
1494  * TX with Enhanced MPW support.
1495  *
1496  * @param txq
1497  *   Pointer to TX queue structure.
1498  * @param[in] pkts
1499  *   Packets to transmit.
1500  * @param pkts_n
1501  *   Number of packets in array.
1502  *
1503  * @return
1504  *   Number of packets successfully transmitted (<= pkts_n).
1505  */
1506 static inline uint16_t
1507 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1508                uint16_t pkts_n)
1509 {
1510         uint16_t elts_head = txq->elts_head;
1511         const uint16_t elts_n = 1 << txq->elts_n;
1512         const uint16_t elts_m = elts_n - 1;
1513         unsigned int i = 0;
1514         unsigned int j = 0;
1515         uint16_t max_elts;
1516         uint16_t max_wqe;
1517         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1518         unsigned int mpw_room = 0;
1519         unsigned int inl_pad = 0;
1520         uint32_t inl_hdr;
1521         uint64_t addr_64;
1522         struct mlx5_mpw mpw = {
1523                 .state = MLX5_MPW_STATE_CLOSED,
1524         };
1525
1526         if (unlikely(!pkts_n))
1527                 return 0;
1528         /* Start processing. */
1529         mlx5_tx_complete(txq);
1530         max_elts = (elts_n - (elts_head - txq->elts_tail));
1531         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1532         if (unlikely(!max_wqe))
1533                 return 0;
1534         do {
1535                 struct rte_mbuf *buf = *(pkts++);
1536                 uintptr_t addr;
1537                 unsigned int do_inline = 0; /* Whether inline is possible. */
1538                 uint32_t length;
1539                 uint8_t cs_flags;
1540                 rte_be32_t metadata;
1541
1542                 /* Multi-segmented packet is handled in slow-path outside. */
1543                 assert(NB_SEGS(buf) == 1);
1544                 /* Make sure there is enough room to store this packet. */
1545                 if (max_elts - j == 0)
1546                         break;
1547                 cs_flags = txq_ol_cksum_to_cs(buf);
1548                 /* Copy metadata from mbuf if valid */
1549                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1550                                                              0;
1551                 /* Retrieve packet information. */
1552                 length = PKT_LEN(buf);
1553                 /* Start new session if:
1554                  * - multi-segment packet
1555                  * - no space left even for a dseg
1556                  * - next packet can be inlined with a new WQE
1557                  * - cs_flag differs
1558                  */
1559                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1560                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1561                              mpw_room) ||
1562                             (length <= txq->inline_max_packet_sz &&
1563                              inl_pad + sizeof(inl_hdr) + length >
1564                              mpw_room) ||
1565                              (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1566                             (mpw.wqe->eseg.cs_flags != cs_flags))
1567                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1568                 }
1569                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1570                         /* In Enhanced MPW, inline as much as the budget is
1571                          * allowed. The remaining space is to be filled with
1572                          * dsegs. If the title WQEBB isn't padded, it will have
1573                          * 2 dsegs there.
1574                          */
1575                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1576                                            (max_inline ? max_inline :
1577                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1578                                            MLX5_WQE_SIZE);
1579                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1580                                 break;
1581                         /* Don't pad the title WQEBB to not waste WQ. */
1582                         mlx5_empw_new(txq, &mpw, 0);
1583                         mpw_room -= mpw.total_len;
1584                         inl_pad = 0;
1585                         do_inline = length <= txq->inline_max_packet_sz &&
1586                                     sizeof(inl_hdr) + length <= mpw_room &&
1587                                     !txq->mpw_hdr_dseg;
1588                         mpw.wqe->eseg.cs_flags = cs_flags;
1589                         mpw.wqe->eseg.flow_table_metadata = metadata;
1590                 } else {
1591                         /* Evaluate whether the next packet can be inlined.
1592                          * Inlininig is possible when:
1593                          * - length is less than configured value
1594                          * - length fits for remaining space
1595                          * - not required to fill the title WQEBB with dsegs
1596                          */
1597                         do_inline =
1598                                 length <= txq->inline_max_packet_sz &&
1599                                 inl_pad + sizeof(inl_hdr) + length <=
1600                                  mpw_room &&
1601                                 (!txq->mpw_hdr_dseg ||
1602                                  mpw.total_len >= MLX5_WQE_SIZE);
1603                 }
1604                 if (max_inline && do_inline) {
1605                         /* Inline packet into WQE. */
1606                         unsigned int max;
1607
1608                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1609                         assert(length == DATA_LEN(buf));
1610                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1611                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1612                         mpw.data.raw = (volatile void *)
1613                                 ((uintptr_t)mpw.data.raw + inl_pad);
1614                         max = tx_mlx5_wq_tailroom(txq,
1615                                         (void *)(uintptr_t)mpw.data.raw);
1616                         /* Copy inline header. */
1617                         mpw.data.raw = (volatile void *)
1618                                 mlx5_copy_to_wq(
1619                                           (void *)(uintptr_t)mpw.data.raw,
1620                                           &inl_hdr,
1621                                           sizeof(inl_hdr),
1622                                           (void *)(uintptr_t)txq->wqes,
1623                                           max);
1624                         max = tx_mlx5_wq_tailroom(txq,
1625                                         (void *)(uintptr_t)mpw.data.raw);
1626                         /* Copy packet data. */
1627                         mpw.data.raw = (volatile void *)
1628                                 mlx5_copy_to_wq(
1629                                           (void *)(uintptr_t)mpw.data.raw,
1630                                           (void *)addr,
1631                                           length,
1632                                           (void *)(uintptr_t)txq->wqes,
1633                                           max);
1634                         ++mpw.pkts_n;
1635                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1636                         /* No need to get completion as the entire packet is
1637                          * copied to WQ. Free the buf right away.
1638                          */
1639                         rte_pktmbuf_free_seg(buf);
1640                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1641                         /* Add pad in the next packet if any. */
1642                         inl_pad = (((uintptr_t)mpw.data.raw +
1643                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1644                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1645                                   (uintptr_t)mpw.data.raw;
1646                 } else {
1647                         /* No inline. Load a dseg of packet pointer. */
1648                         volatile rte_v128u32_t *dseg;
1649
1650                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1651                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1652                         assert(length == DATA_LEN(buf));
1653                         if (!tx_mlx5_wq_tailroom(txq,
1654                                         (void *)((uintptr_t)mpw.data.raw
1655                                                 + inl_pad)))
1656                                 dseg = (volatile void *)txq->wqes;
1657                         else
1658                                 dseg = (volatile void *)
1659                                         ((uintptr_t)mpw.data.raw +
1660                                          inl_pad);
1661                         (*txq->elts)[elts_head++ & elts_m] = buf;
1662                         addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1663                                                                     uintptr_t));
1664                         *dseg = (rte_v128u32_t) {
1665                                 rte_cpu_to_be_32(length),
1666                                 mlx5_tx_mb2mr(txq, buf),
1667                                 addr_64,
1668                                 addr_64 >> 32,
1669                         };
1670                         mpw.data.raw = (volatile void *)(dseg + 1);
1671                         mpw.total_len += (inl_pad + sizeof(*dseg));
1672                         ++j;
1673                         ++mpw.pkts_n;
1674                         mpw_room -= (inl_pad + sizeof(*dseg));
1675                         inl_pad = 0;
1676                 }
1677 #ifdef MLX5_PMD_SOFT_COUNTERS
1678                 /* Increment sent bytes counter. */
1679                 txq->stats.obytes += length;
1680 #endif
1681                 ++i;
1682         } while (i < pkts_n);
1683         /* Take a shortcut if nothing must be sent. */
1684         if (unlikely(i == 0))
1685                 return 0;
1686         /* Check whether completion threshold has been reached. */
1687         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1688                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1689                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1690                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1691
1692                 /* A CQE slot must always be available. */
1693                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1694                 /* Request completion on last WQE. */
1695                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1696                 /* Save elts_head in unused "immediate" field of WQE. */
1697                 wqe->ctrl[3] = elts_head;
1698                 txq->elts_comp = 0;
1699                 txq->mpw_comp = txq->wqe_ci;
1700         } else {
1701                 txq->elts_comp += j;
1702         }
1703 #ifdef MLX5_PMD_SOFT_COUNTERS
1704         /* Increment sent packets counter. */
1705         txq->stats.opackets += i;
1706 #endif
1707         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1708                 mlx5_empw_close(txq, &mpw);
1709         /* Ring QP doorbell. */
1710         mlx5_tx_dbrec(txq, mpw.wqe);
1711         txq->elts_head = elts_head;
1712         return i;
1713 }
1714
1715 /**
1716  * DPDK callback for TX with Enhanced MPW support.
1717  *
1718  * @param dpdk_txq
1719  *   Generic pointer to TX queue structure.
1720  * @param[in] pkts
1721  *   Packets to transmit.
1722  * @param pkts_n
1723  *   Number of packets in array.
1724  *
1725  * @return
1726  *   Number of packets successfully transmitted (<= pkts_n).
1727  */
1728 uint16_t
1729 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1730 {
1731         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1732         uint16_t nb_tx = 0;
1733
1734         while (pkts_n > nb_tx) {
1735                 uint16_t n;
1736                 uint16_t ret;
1737
1738                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1739                 if (n) {
1740                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1741                         if (!ret)
1742                                 break;
1743                         nb_tx += ret;
1744                 }
1745                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1746                 if (n) {
1747                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1748                         if (!ret)
1749                                 break;
1750                         nb_tx += ret;
1751                 }
1752         }
1753         return nb_tx;
1754 }
1755
1756 /**
1757  * Translate RX completion flags to packet type.
1758  *
1759  * @param[in] rxq
1760  *   Pointer to RX queue structure.
1761  * @param[in] cqe
1762  *   Pointer to CQE.
1763  *
1764  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1765  *
1766  * @return
1767  *   Packet type for struct rte_mbuf.
1768  */
1769 static inline uint32_t
1770 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1771 {
1772         uint8_t idx;
1773         uint8_t pinfo = cqe->pkt_info;
1774         uint16_t ptype = cqe->hdr_type_etc;
1775
1776         /*
1777          * The index to the array should have:
1778          * bit[1:0] = l3_hdr_type
1779          * bit[4:2] = l4_hdr_type
1780          * bit[5] = ip_frag
1781          * bit[6] = tunneled
1782          * bit[7] = outer_l3_type
1783          */
1784         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1785         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1786 }
1787
1788 /**
1789  * Get size of the next packet for a given CQE. For compressed CQEs, the
1790  * consumer index is updated only once all packets of the current one have
1791  * been processed.
1792  *
1793  * @param rxq
1794  *   Pointer to RX queue.
1795  * @param cqe
1796  *   CQE to process.
1797  * @param[out] mcqe
1798  *   Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1799  *   written.
1800  *
1801  * @return
1802  *   Packet size in bytes (0 if there is none), -1 in case of completion
1803  *   with error.
1804  */
1805 static inline int
1806 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1807                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1808 {
1809         struct rxq_zip *zip = &rxq->zip;
1810         uint16_t cqe_n = cqe_cnt + 1;
1811         int len = 0;
1812         uint16_t idx, end;
1813
1814         /* Process compressed data in the CQE and mini arrays. */
1815         if (zip->ai) {
1816                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1817                         (volatile struct mlx5_mini_cqe8 (*)[8])
1818                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1819
1820                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1821                 *mcqe = &(*mc)[zip->ai & 7];
1822                 if ((++zip->ai & 7) == 0) {
1823                         /* Invalidate consumed CQEs */
1824                         idx = zip->ca;
1825                         end = zip->na;
1826                         while (idx != end) {
1827                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1828                                         MLX5_CQE_INVALIDATE;
1829                                 ++idx;
1830                         }
1831                         /*
1832                          * Increment consumer index to skip the number of
1833                          * CQEs consumed. Hardware leaves holes in the CQ
1834                          * ring for software use.
1835                          */
1836                         zip->ca = zip->na;
1837                         zip->na += 8;
1838                 }
1839                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1840                         /* Invalidate the rest */
1841                         idx = zip->ca;
1842                         end = zip->cq_ci;
1843
1844                         while (idx != end) {
1845                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1846                                         MLX5_CQE_INVALIDATE;
1847                                 ++idx;
1848                         }
1849                         rxq->cq_ci = zip->cq_ci;
1850                         zip->ai = 0;
1851                 }
1852         /* No compressed data, get next CQE and verify if it is compressed. */
1853         } else {
1854                 int ret;
1855                 int8_t op_own;
1856
1857                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1858                 if (unlikely(ret == 1))
1859                         return 0;
1860                 ++rxq->cq_ci;
1861                 op_own = cqe->op_own;
1862                 rte_cio_rmb();
1863                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1864                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1865                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1866                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1867                                                           cqe_cnt].pkt_info);
1868
1869                         /* Fix endianness. */
1870                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1871                         /*
1872                          * Current mini array position is the one returned by
1873                          * check_cqe64().
1874                          *
1875                          * If completion comprises several mini arrays, as a
1876                          * special case the second one is located 7 CQEs after
1877                          * the initial CQE instead of 8 for subsequent ones.
1878                          */
1879                         zip->ca = rxq->cq_ci;
1880                         zip->na = zip->ca + 7;
1881                         /* Compute the next non compressed CQE. */
1882                         --rxq->cq_ci;
1883                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1884                         /* Get packet size to return. */
1885                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1886                         *mcqe = &(*mc)[0];
1887                         zip->ai = 1;
1888                         /* Prefetch all the entries to be invalidated */
1889                         idx = zip->ca;
1890                         end = zip->cq_ci;
1891                         while (idx != end) {
1892                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1893                                 ++idx;
1894                         }
1895                 } else {
1896                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1897                 }
1898                 /* Error while receiving packet. */
1899                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1900                         return -1;
1901         }
1902         return len;
1903 }
1904
1905 /**
1906  * Translate RX completion flags to offload flags.
1907  *
1908  * @param[in] cqe
1909  *   Pointer to CQE.
1910  *
1911  * @return
1912  *   Offload flags (ol_flags) for struct rte_mbuf.
1913  */
1914 static inline uint32_t
1915 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1916 {
1917         uint32_t ol_flags = 0;
1918         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1919
1920         ol_flags =
1921                 TRANSPOSE(flags,
1922                           MLX5_CQE_RX_L3_HDR_VALID,
1923                           PKT_RX_IP_CKSUM_GOOD) |
1924                 TRANSPOSE(flags,
1925                           MLX5_CQE_RX_L4_HDR_VALID,
1926                           PKT_RX_L4_CKSUM_GOOD);
1927         return ol_flags;
1928 }
1929
1930 /**
1931  * Fill in mbuf fields from RX completion flags.
1932  * Note that pkt->ol_flags should be initialized outside of this function.
1933  *
1934  * @param rxq
1935  *   Pointer to RX queue.
1936  * @param pkt
1937  *   mbuf to fill.
1938  * @param cqe
1939  *   CQE to process.
1940  * @param rss_hash_res
1941  *   Packet RSS Hash result.
1942  */
1943 static inline void
1944 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1945                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1946 {
1947         /* Update packet information. */
1948         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1949         if (rss_hash_res && rxq->rss_hash) {
1950                 pkt->hash.rss = rss_hash_res;
1951                 pkt->ol_flags |= PKT_RX_RSS_HASH;
1952         }
1953         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1954                 pkt->ol_flags |= PKT_RX_FDIR;
1955                 if (cqe->sop_drop_qpn !=
1956                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1957                         uint32_t mark = cqe->sop_drop_qpn;
1958
1959                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1960                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1961                 }
1962         }
1963         if (rxq->csum)
1964                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1965         if (rxq->vlan_strip &&
1966             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1967                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1968                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1969         }
1970         if (rxq->hw_timestamp) {
1971                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1972                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1973         }
1974 }
1975
1976 /**
1977  * DPDK callback for RX.
1978  *
1979  * @param dpdk_rxq
1980  *   Generic pointer to RX queue structure.
1981  * @param[out] pkts
1982  *   Array to store received packets.
1983  * @param pkts_n
1984  *   Maximum number of packets in array.
1985  *
1986  * @return
1987  *   Number of packets successfully received (<= pkts_n).
1988  */
1989 uint16_t
1990 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1991 {
1992         struct mlx5_rxq_data *rxq = dpdk_rxq;
1993         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1994         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1995         const unsigned int sges_n = rxq->sges_n;
1996         struct rte_mbuf *pkt = NULL;
1997         struct rte_mbuf *seg = NULL;
1998         volatile struct mlx5_cqe *cqe =
1999                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2000         unsigned int i = 0;
2001         unsigned int rq_ci = rxq->rq_ci << sges_n;
2002         int len = 0; /* keep its value across iterations. */
2003
2004         while (pkts_n) {
2005                 unsigned int idx = rq_ci & wqe_cnt;
2006                 volatile struct mlx5_wqe_data_seg *wqe =
2007                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2008                 struct rte_mbuf *rep = (*rxq->elts)[idx];
2009                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2010                 uint32_t rss_hash_res;
2011
2012                 if (pkt)
2013                         NEXT(seg) = rep;
2014                 seg = rep;
2015                 rte_prefetch0(seg);
2016                 rte_prefetch0(cqe);
2017                 rte_prefetch0(wqe);
2018                 rep = rte_mbuf_raw_alloc(rxq->mp);
2019                 if (unlikely(rep == NULL)) {
2020                         ++rxq->stats.rx_nombuf;
2021                         if (!pkt) {
2022                                 /*
2023                                  * no buffers before we even started,
2024                                  * bail out silently.
2025                                  */
2026                                 break;
2027                         }
2028                         while (pkt != seg) {
2029                                 assert(pkt != (*rxq->elts)[idx]);
2030                                 rep = NEXT(pkt);
2031                                 NEXT(pkt) = NULL;
2032                                 NB_SEGS(pkt) = 1;
2033                                 rte_mbuf_raw_free(pkt);
2034                                 pkt = rep;
2035                         }
2036                         break;
2037                 }
2038                 if (!pkt) {
2039                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2040                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2041                         if (!len) {
2042                                 rte_mbuf_raw_free(rep);
2043                                 break;
2044                         }
2045                         if (unlikely(len == -1)) {
2046                                 /* RX error, packet is likely too large. */
2047                                 rte_mbuf_raw_free(rep);
2048                                 ++rxq->stats.idropped;
2049                                 goto skip;
2050                         }
2051                         pkt = seg;
2052                         assert(len >= (rxq->crc_present << 2));
2053                         pkt->ol_flags = 0;
2054                         /* If compressed, take hash result from mini-CQE. */
2055                         rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2056                                                         cqe->rx_hash_res :
2057                                                         mcqe->rx_hash_result);
2058                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2059                         if (rxq->crc_present)
2060                                 len -= ETHER_CRC_LEN;
2061                         PKT_LEN(pkt) = len;
2062                 }
2063                 DATA_LEN(rep) = DATA_LEN(seg);
2064                 PKT_LEN(rep) = PKT_LEN(seg);
2065                 SET_DATA_OFF(rep, DATA_OFF(seg));
2066                 PORT(rep) = PORT(seg);
2067                 (*rxq->elts)[idx] = rep;
2068                 /*
2069                  * Fill NIC descriptor with the new buffer.  The lkey and size
2070                  * of the buffers are already known, only the buffer address
2071                  * changes.
2072                  */
2073                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2074                 /* If there's only one MR, no need to replace LKey in WQE. */
2075                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2076                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2077                 if (len > DATA_LEN(seg)) {
2078                         len -= DATA_LEN(seg);
2079                         ++NB_SEGS(pkt);
2080                         ++rq_ci;
2081                         continue;
2082                 }
2083                 DATA_LEN(seg) = len;
2084 #ifdef MLX5_PMD_SOFT_COUNTERS
2085                 /* Increment bytes counter. */
2086                 rxq->stats.ibytes += PKT_LEN(pkt);
2087 #endif
2088                 /* Return packet. */
2089                 *(pkts++) = pkt;
2090                 pkt = NULL;
2091                 --pkts_n;
2092                 ++i;
2093 skip:
2094                 /* Align consumer index to the next stride. */
2095                 rq_ci >>= sges_n;
2096                 ++rq_ci;
2097                 rq_ci <<= sges_n;
2098         }
2099         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2100                 return 0;
2101         /* Update the consumer index. */
2102         rxq->rq_ci = rq_ci >> sges_n;
2103         rte_cio_wmb();
2104         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2105         rte_cio_wmb();
2106         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2107 #ifdef MLX5_PMD_SOFT_COUNTERS
2108         /* Increment packets counter. */
2109         rxq->stats.ipackets += i;
2110 #endif
2111         return i;
2112 }
2113
2114 void
2115 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2116 {
2117         struct mlx5_mprq_buf *buf = opaque;
2118
2119         if (rte_atomic16_read(&buf->refcnt) == 1) {
2120                 rte_mempool_put(buf->mp, buf);
2121         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2122                 rte_atomic16_set(&buf->refcnt, 1);
2123                 rte_mempool_put(buf->mp, buf);
2124         }
2125 }
2126
2127 void
2128 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2129 {
2130         mlx5_mprq_buf_free_cb(NULL, buf);
2131 }
2132
2133 static inline void
2134 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2135 {
2136         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2137         volatile struct mlx5_wqe_data_seg *wqe =
2138                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2139         void *addr;
2140
2141         assert(rep != NULL);
2142         /* Replace MPRQ buf. */
2143         (*rxq->mprq_bufs)[rq_idx] = rep;
2144         /* Replace WQE. */
2145         addr = mlx5_mprq_buf_addr(rep);
2146         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2147         /* If there's only one MR, no need to replace LKey in WQE. */
2148         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2149                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2150         /* Stash a mbuf for next replacement. */
2151         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2152                 rxq->mprq_repl = rep;
2153         else
2154                 rxq->mprq_repl = NULL;
2155 }
2156
2157 /**
2158  * DPDK callback for RX with Multi-Packet RQ support.
2159  *
2160  * @param dpdk_rxq
2161  *   Generic pointer to RX queue structure.
2162  * @param[out] pkts
2163  *   Array to store received packets.
2164  * @param pkts_n
2165  *   Maximum number of packets in array.
2166  *
2167  * @return
2168  *   Number of packets successfully received (<= pkts_n).
2169  */
2170 uint16_t
2171 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2172 {
2173         struct mlx5_rxq_data *rxq = dpdk_rxq;
2174         const unsigned int strd_n = 1 << rxq->strd_num_n;
2175         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2176         const unsigned int strd_shift =
2177                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2178         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2179         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2180         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2181         unsigned int i = 0;
2182         uint32_t rq_ci = rxq->rq_ci;
2183         uint16_t consumed_strd = rxq->consumed_strd;
2184         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2185
2186         while (i < pkts_n) {
2187                 struct rte_mbuf *pkt;
2188                 void *addr;
2189                 int ret;
2190                 unsigned int len;
2191                 uint16_t strd_cnt;
2192                 uint16_t strd_idx;
2193                 uint32_t offset;
2194                 uint32_t byte_cnt;
2195                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2196                 uint32_t rss_hash_res = 0;
2197
2198                 if (consumed_strd == strd_n) {
2199                         /* Replace WQE only if the buffer is still in use. */
2200                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2201                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2202                                 /* Release the old buffer. */
2203                                 mlx5_mprq_buf_free(buf);
2204                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2205                                 struct mlx5_mprq_buf *rep;
2206
2207                                 /*
2208                                  * Currently, the MPRQ mempool is out of buffer
2209                                  * and doing memcpy regardless of the size of Rx
2210                                  * packet. Retry allocation to get back to
2211                                  * normal.
2212                                  */
2213                                 if (!rte_mempool_get(rxq->mprq_mp,
2214                                                      (void **)&rep))
2215                                         rxq->mprq_repl = rep;
2216                         }
2217                         /* Advance to the next WQE. */
2218                         consumed_strd = 0;
2219                         ++rq_ci;
2220                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2221                 }
2222                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2223                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2224                 if (!ret)
2225                         break;
2226                 if (unlikely(ret == -1)) {
2227                         /* RX error, packet is likely too large. */
2228                         ++rxq->stats.idropped;
2229                         continue;
2230                 }
2231                 byte_cnt = ret;
2232                 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2233                            MLX5_MPRQ_STRIDE_NUM_SHIFT;
2234                 assert(strd_cnt);
2235                 consumed_strd += strd_cnt;
2236                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2237                         continue;
2238                 if (mcqe == NULL) {
2239                         rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2240                         strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2241                 } else {
2242                         /* mini-CQE for MPRQ doesn't have hash result. */
2243                         strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2244                 }
2245                 assert(strd_idx < strd_n);
2246                 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2247                 /*
2248                  * Currently configured to receive a packet per a stride. But if
2249                  * MTU is adjusted through kernel interface, device could
2250                  * consume multiple strides without raising an error. In this
2251                  * case, the packet should be dropped because it is bigger than
2252                  * the max_rx_pkt_len.
2253                  */
2254                 if (unlikely(strd_cnt > 1)) {
2255                         ++rxq->stats.idropped;
2256                         continue;
2257                 }
2258                 pkt = rte_pktmbuf_alloc(rxq->mp);
2259                 if (unlikely(pkt == NULL)) {
2260                         ++rxq->stats.rx_nombuf;
2261                         break;
2262                 }
2263                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2264                 assert((int)len >= (rxq->crc_present << 2));
2265                 if (rxq->crc_present)
2266                         len -= ETHER_CRC_LEN;
2267                 offset = strd_idx * strd_sz + strd_shift;
2268                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2269                 /* Initialize the offload flag. */
2270                 pkt->ol_flags = 0;
2271                 /*
2272                  * Memcpy packets to the target mbuf if:
2273                  * - The size of packet is smaller than mprq_max_memcpy_len.
2274                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2275                  */
2276                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2277                         /*
2278                          * When memcpy'ing packet due to out-of-buffer, the
2279                          * packet must be smaller than the target mbuf.
2280                          */
2281                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2282                                 rte_pktmbuf_free_seg(pkt);
2283                                 ++rxq->stats.idropped;
2284                                 continue;
2285                         }
2286                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2287                 } else {
2288                         rte_iova_t buf_iova;
2289                         struct rte_mbuf_ext_shared_info *shinfo;
2290                         uint16_t buf_len = strd_cnt * strd_sz;
2291
2292                         /* Increment the refcnt of the whole chunk. */
2293                         rte_atomic16_add_return(&buf->refcnt, 1);
2294                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2295                                strd_n + 1);
2296                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2297                         /*
2298                          * MLX5 device doesn't use iova but it is necessary in a
2299                          * case where the Rx packet is transmitted via a
2300                          * different PMD.
2301                          */
2302                         buf_iova = rte_mempool_virt2iova(buf) +
2303                                    RTE_PTR_DIFF(addr, buf);
2304                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2305                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2306                         /*
2307                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2308                          * attaching the stride to mbuf and more offload flags
2309                          * will be added below by calling rxq_cq_to_mbuf().
2310                          * Other fields will be overwritten.
2311                          */
2312                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2313                                                   shinfo);
2314                         rte_pktmbuf_reset_headroom(pkt);
2315                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2316                         /*
2317                          * Prevent potential overflow due to MTU change through
2318                          * kernel interface.
2319                          */
2320                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2321                                 rte_pktmbuf_free_seg(pkt);
2322                                 ++rxq->stats.idropped;
2323                                 continue;
2324                         }
2325                 }
2326                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2327                 PKT_LEN(pkt) = len;
2328                 DATA_LEN(pkt) = len;
2329                 PORT(pkt) = rxq->port_id;
2330 #ifdef MLX5_PMD_SOFT_COUNTERS
2331                 /* Increment bytes counter. */
2332                 rxq->stats.ibytes += PKT_LEN(pkt);
2333 #endif
2334                 /* Return packet. */
2335                 *(pkts++) = pkt;
2336                 ++i;
2337         }
2338         /* Update the consumer indexes. */
2339         rxq->consumed_strd = consumed_strd;
2340         rte_cio_wmb();
2341         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2342         if (rq_ci != rxq->rq_ci) {
2343                 rxq->rq_ci = rq_ci;
2344                 rte_cio_wmb();
2345                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2346         }
2347 #ifdef MLX5_PMD_SOFT_COUNTERS
2348         /* Increment packets counter. */
2349         rxq->stats.ipackets += i;
2350 #endif
2351         return i;
2352 }
2353
2354 /**
2355  * Dummy DPDK callback for TX.
2356  *
2357  * This function is used to temporarily replace the real callback during
2358  * unsafe control operations on the queue, or in case of error.
2359  *
2360  * @param dpdk_txq
2361  *   Generic pointer to TX queue structure.
2362  * @param[in] pkts
2363  *   Packets to transmit.
2364  * @param pkts_n
2365  *   Number of packets in array.
2366  *
2367  * @return
2368  *   Number of packets successfully transmitted (<= pkts_n).
2369  */
2370 uint16_t
2371 removed_tx_burst(void *dpdk_txq __rte_unused,
2372                  struct rte_mbuf **pkts __rte_unused,
2373                  uint16_t pkts_n __rte_unused)
2374 {
2375         return 0;
2376 }
2377
2378 /**
2379  * Dummy DPDK callback for RX.
2380  *
2381  * This function is used to temporarily replace the real callback during
2382  * unsafe control operations on the queue, or in case of error.
2383  *
2384  * @param dpdk_rxq
2385  *   Generic pointer to RX queue structure.
2386  * @param[out] pkts
2387  *   Array to store received packets.
2388  * @param pkts_n
2389  *   Maximum number of packets in array.
2390  *
2391  * @return
2392  *   Number of packets successfully received (<= pkts_n).
2393  */
2394 uint16_t
2395 removed_rx_burst(void *dpdk_txq __rte_unused,
2396                  struct rte_mbuf **pkts __rte_unused,
2397                  uint16_t pkts_n __rte_unused)
2398 {
2399         return 0;
2400 }
2401
2402 /*
2403  * Vectorized Rx/Tx routines are not compiled in when required vector
2404  * instructions are not supported on a target architecture. The following null
2405  * stubs are needed for linkage when those are not included outside of this file
2406  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2407  */
2408
2409 __rte_weak uint16_t
2410 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2411                       struct rte_mbuf **pkts __rte_unused,
2412                       uint16_t pkts_n __rte_unused)
2413 {
2414         return 0;
2415 }
2416
2417 __rte_weak uint16_t
2418 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2419                   struct rte_mbuf **pkts __rte_unused,
2420                   uint16_t pkts_n __rte_unused)
2421 {
2422         return 0;
2423 }
2424
2425 __rte_weak uint16_t
2426 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2427                   struct rte_mbuf **pkts __rte_unused,
2428                   uint16_t pkts_n __rte_unused)
2429 {
2430         return 0;
2431 }
2432
2433 __rte_weak int
2434 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2435 {
2436         return -ENOTSUP;
2437 }
2438
2439 __rte_weak int
2440 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2441 {
2442         return -ENOTSUP;
2443 }
2444
2445 __rte_weak int
2446 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2447 {
2448         return -ENOTSUP;
2449 }
2450
2451 __rte_weak int
2452 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2453 {
2454         return -ENOTSUP;
2455 }