drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Return the size of tailroom of WQ.
 199  *
 200  * @param txq
 201  *   Pointer to TX queue structure.
 202  * @param addr
 203  *   Pointer to tail of WQ.
 204  *
 205  * @return
 206  *   Size of tailroom.
 207  */
 208 static inline size_t
 209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 210 {
 211         size_t tailroom;
 212         tailroom = (uintptr_t)(txq->wqes) +
 213                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 214                    (uintptr_t)addr;
 215         return tailroom;
 216 }
 217
 218 /**
 219  * Copy data to tailroom of circular queue.
 220  *
 221  * @param dst
 222  *   Pointer to destination.
 223  * @param src
 224  *   Pointer to source.
 225  * @param n
 226  *   Number of bytes to copy.
 227  * @param base
 228  *   Pointer to head of queue.
 229  * @param tailroom
 230  *   Size of tailroom from dst.
 231  *
 232  * @return
 233  *   Pointer after copied data.
 234  */
 235 static inline void *
 236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 237                 void *base, size_t tailroom)
 238 {
 239         void *ret;
 240
 241         if (n > tailroom) {
 242                 rte_memcpy(dst, src, tailroom);
 243                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 244                            n - tailroom);
 245                 ret = (uint8_t *)base + n - tailroom;
 246         } else {
 247                 rte_memcpy(dst, src, n);
 248                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 249         }
 250         return ret;
 251 }
 252
 253 /**
 254  * Manage TX completions.
 255  *
 256  * When sending a burst, mlx5_tx_burst() posts several WRs.
 257  *
 258  * @param txq
 259  *   Pointer to TX queue structure.
 260  */
 261 static inline void
 262 txq_complete(struct txq *txq)
 263 {
 264         const unsigned int elts_n = 1 << txq->elts_n;
 265         const unsigned int cqe_n = 1 << txq->cqe_n;
 266         const unsigned int cqe_cnt = cqe_n - 1;
 267         uint16_t elts_free = txq->elts_tail;
 268         uint16_t elts_tail;
 269         uint16_t cq_ci = txq->cq_ci;
 270         volatile struct mlx5_cqe *cqe = NULL;
 271         volatile struct mlx5_wqe_ctrl *ctrl;
 272
 273         do {
 274                 volatile struct mlx5_cqe *tmp;
 275
 276                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 277                 if (check_cqe(tmp, cqe_n, cq_ci))
 278                         break;
 279                 cqe = tmp;
 280 #ifndef NDEBUG
 281                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 282                         if (!check_cqe_seen(cqe))
 283                                 ERROR("unexpected compressed CQE, TX stopped");
 284                         return;
 285                 }
 286                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 287                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 288                         if (!check_cqe_seen(cqe))
 289                                 ERROR("unexpected error CQE, TX stopped");
 290                         return;
 291                 }
 292 #endif /* NDEBUG */
 293                 ++cq_ci;
 294         } while (1);
 295         if (unlikely(cqe == NULL))
 296                 return;
 297         txq->wqe_pi = ntohs(cqe->wqe_counter);
 298         ctrl = (volatile struct mlx5_wqe_ctrl *)
 299                 tx_mlx5_wqe(txq, txq->wqe_pi);
 300         elts_tail = ctrl->ctrl3;
 301         assert(elts_tail < (1 << txq->wqe_n));
 302         /* Free buffers. */
 303         while (elts_free != elts_tail) {
 304                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 305                 unsigned int elts_free_next =
 306                         (elts_free + 1) & (elts_n - 1);
 307                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 308
 309 #ifndef NDEBUG
 310                 /* Poisoning. */
 311                 memset(&(*txq->elts)[elts_free],
 312                        0x66,
 313                        sizeof((*txq->elts)[elts_free]));
 314 #endif
 315                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 316                 /* Only one segment needs to be freed. */
 317                 rte_pktmbuf_free_seg(elt);
 318                 elts_free = elts_free_next;
 319         }
 320         txq->cq_ci = cq_ci;
 321         txq->elts_tail = elts_tail;
 322         /* Update the consumer index. */
 323         rte_wmb();
 324         *txq->cq_db = htonl(cq_ci);
 325 }
 326
 327 /**
 328  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 329  * the cloned mbuf is allocated is returned instead.
 330  *
 331  * @param buf
 332  *   Pointer to mbuf.
 333  *
 334  * @return
 335  *   Memory pool where data is located for given mbuf.
 336  */
 337 static struct rte_mempool *
 338 txq_mb2mp(struct rte_mbuf *buf)
 339 {
 340         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 341                 return rte_mbuf_from_indirect(buf)->pool;
 342         return buf->pool;
 343 }
 344
 345 /**
 346  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 347  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 348  * remove an entry first.
 349  *
 350  * @param txq
 351  *   Pointer to TX queue structure.
 352  * @param[in] mp
 353  *   Memory Pool for which a Memory Region lkey must be returned.
 354  *
 355  * @return
 356  *   mr->lkey on success, (uint32_t)-1 on failure.
 357  */
 358 static inline uint32_t
 359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 360 {
 361         unsigned int i;
 362         uint32_t lkey = (uint32_t)-1;
 363
 364         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 365                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 366                         /* Unknown MP, add a new MR for it. */
 367                         break;
 368                 }
 369                 if (txq->mp2mr[i].mp == mp) {
 370                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 371                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 372                                txq->mp2mr[i].lkey);
 373                         lkey = txq->mp2mr[i].lkey;
 374                         break;
 375                 }
 376         }
 377         if (unlikely(lkey == (uint32_t)-1))
 378                 lkey = txq_mp2mr_reg(txq, mp, i);
 379         return lkey;
 380 }
 381
 382 /**
 383  * Ring TX queue doorbell.
 384  *
 385  * @param txq
 386  *   Pointer to TX queue structure.
 387  * @param wqe
 388  *   Pointer to the last WQE posted in the NIC.
 389  */
 390 static inline void
 391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 392 {
 393         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 394         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 395
 396         rte_wmb();
 397         *txq->qp_db = htonl(txq->wqe_ci);
 398         /* Ensure ordering between DB record and BF copy. */
 399         rte_wmb();
 400         *dst = *src;
 401 }
 402
 403 /**
 404  * DPDK callback to check the status of a tx descriptor.
 405  *
 406  * @param tx_queue
 407  *   The tx queue.
 408  * @param[in] offset
 409  *   The index of the descriptor in the ring.
 410  *
 411  * @return
 412  *   The status of the tx descriptor.
 413  */
 414 int
 415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 416 {
 417         struct txq *txq = tx_queue;
 418         const unsigned int elts_n = 1 << txq->elts_n;
 419         const unsigned int elts_cnt = elts_n - 1;
 420         unsigned int used;
 421
 422         txq_complete(txq);
 423         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 424         if (offset < used)
 425                 return RTE_ETH_TX_DESC_FULL;
 426         return RTE_ETH_TX_DESC_DONE;
 427 }
 428
 429 /**
 430  * DPDK callback to check the status of a rx descriptor.
 431  *
 432  * @param rx_queue
 433  *   The rx queue.
 434  * @param[in] offset
 435  *   The index of the descriptor in the ring.
 436  *
 437  * @return
 438  *   The status of the tx descriptor.
 439  */
 440 int
 441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 442 {
 443         struct rxq *rxq = rx_queue;
 444         struct rxq_zip *zip = &rxq->zip;
 445         volatile struct mlx5_cqe *cqe;
 446         const unsigned int cqe_n = (1 << rxq->cqe_n);
 447         const unsigned int cqe_cnt = cqe_n - 1;
 448         unsigned int cq_ci;
 449         unsigned int used;
 450
 451         /* if we are processing a compressed cqe */
 452         if (zip->ai) {
 453                 used = zip->cqe_cnt - zip->ca;
 454                 cq_ci = zip->cq_ci;
 455         } else {
 456                 used = 0;
 457                 cq_ci = rxq->cq_ci;
 458         }
 459         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 461                 int8_t op_own;
 462                 unsigned int n;
 463
 464                 op_own = cqe->op_own;
 465                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 466                         n = ntohl(cqe->byte_cnt);
 467                 else
 468                         n = 1;
 469                 cq_ci += n;
 470                 used += n;
 471                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 472         }
 473         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 474         if (offset < used)
 475                 return RTE_ETH_RX_DESC_DONE;
 476         return RTE_ETH_RX_DESC_AVAIL;
 477 }
 478
 479 /**
 480  * DPDK callback for TX.
 481  *
 482  * @param dpdk_txq
 483  *   Generic pointer to TX queue structure.
 484  * @param[in] pkts
 485  *   Packets to transmit.
 486  * @param pkts_n
 487  *   Number of packets in array.
 488  *
 489  * @return
 490  *   Number of packets successfully transmitted (<= pkts_n).
 491  */
 492 uint16_t
 493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 494 {
 495         struct txq *txq = (struct txq *)dpdk_txq;
 496         uint16_t elts_head = txq->elts_head;
 497         const unsigned int elts_n = 1 << txq->elts_n;
 498         unsigned int i = 0;
 499         unsigned int j = 0;
 500         unsigned int k = 0;
 501         unsigned int max;
 502         unsigned int max_inline = txq->max_inline;
 503         const unsigned int inline_en = !!max_inline && txq->inline_en;
 504         uint16_t max_wqe;
 505         unsigned int comp;
 506         volatile struct mlx5_wqe_v *wqe = NULL;
 507         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 508         unsigned int segs_n = 0;
 509         struct rte_mbuf *buf = NULL;
 510         uint8_t *raw;
 511
 512         if (unlikely(!pkts_n))
 513                 return 0;
 514         /* Prefetch first packet cacheline. */
 515         rte_prefetch0(*pkts);
 516         /* Start processing. */
 517         txq_complete(txq);
 518         max = (elts_n - (elts_head - txq->elts_tail));
 519         if (max > elts_n)
 520                 max -= elts_n;
 521         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 522         if (unlikely(!max_wqe))
 523                 return 0;
 524         do {
 525                 volatile rte_v128u32_t *dseg = NULL;
 526                 uint32_t length;
 527                 unsigned int ds = 0;
 528                 unsigned int sg = 0; /* counter of additional segs attached. */
 529                 uintptr_t addr;
 530                 uint64_t naddr;
 531                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 532                 uint16_t tso_header_sz = 0;
 533                 uint16_t ehdr;
 534                 uint8_t cs_flags = 0;
 535                 uint64_t tso = 0;
 536                 uint16_t tso_segsz = 0;
 537 #ifdef MLX5_PMD_SOFT_COUNTERS
 538                 uint32_t total_length = 0;
 539 #endif
 540
 541                 /* first_seg */
 542                 buf = *pkts;
 543                 segs_n = buf->nb_segs;
 544                 /*
 545                  * Make sure there is enough room to store this packet and
 546                  * that one ring entry remains unused.
 547                  */
 548                 assert(segs_n);
 549                 if (max < segs_n + 1)
 550                         break;
 551                 max -= segs_n;
 552                 --segs_n;
 553                 if (unlikely(--max_wqe == 0))
 554                         break;
 555                 wqe = (volatile struct mlx5_wqe_v *)
 556                         tx_mlx5_wqe(txq, txq->wqe_ci);
 557                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 558                 if (pkts_n - i > 1)
 559                         rte_prefetch0(*(pkts + 1));
 560                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 561                 length = DATA_LEN(buf);
 562                 ehdr = (((uint8_t *)addr)[1] << 8) |
 563                        ((uint8_t *)addr)[0];
 564 #ifdef MLX5_PMD_SOFT_COUNTERS
 565                 total_length = length;
 566 #endif
 567                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 568                         break;
 569                 /* Update element. */
 570                 (*txq->elts)[elts_head] = buf;
 571                 /* Prefetch next buffer data. */
 572                 if (pkts_n - i > 1)
 573                         rte_prefetch0(
 574                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 575                 /* Should we enable HW CKSUM offload */
 576                 if (buf->ol_flags &
 577                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 578                         const uint64_t is_tunneled = buf->ol_flags &
 579                                                      (PKT_TX_TUNNEL_GRE |
 580                                                       PKT_TX_TUNNEL_VXLAN);
 581
 582                         if (is_tunneled && txq->tunnel_en) {
 583                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 584                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 585                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 586                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 587                         } else {
 588                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 589                                            MLX5_ETH_WQE_L4_CSUM;
 590                         }
 591                 }
 592                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 593                 /* Replace the Ethernet type by the VLAN if necessary. */
 594                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 595                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 596                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 597
 598                         addr += 2;
 599                         length -= 2;
 600                         /* Copy Destination and source mac address. */
 601                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 602                         /* Copy VLAN. */
 603                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 604                         /* Copy missing two bytes to end the DSeg. */
 605                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 606                                ((uint8_t *)addr) + len, 2);
 607                         addr += len + 2;
 608                         length -= (len + 2);
 609                 } else {
 610                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 611                                MLX5_WQE_DWORD_SIZE);
 612                         length -= pkt_inline_sz;
 613                         addr += pkt_inline_sz;
 614                 }
 615                 if (txq->tso_en) {
 616                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 617                         if (tso) {
 618                                 uintptr_t end = (uintptr_t)
 619                                                 (((uintptr_t)txq->wqes) +
 620                                                 (1 << txq->wqe_n) *
 621                                                 MLX5_WQE_SIZE);
 622                                 unsigned int copy_b;
 623                                 uint8_t vlan_sz = (buf->ol_flags &
 624                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 625                                 const uint64_t is_tunneled =
 626                                                         buf->ol_flags &
 627                                                         (PKT_TX_TUNNEL_GRE |
 628                                                          PKT_TX_TUNNEL_VXLAN);
 629
 630                                 tso_header_sz = buf->l2_len + vlan_sz +
 631                                                 buf->l3_len + buf->l4_len;
 632                                 tso_segsz = buf->tso_segsz;
 633
 634                                 if (is_tunneled && txq->tunnel_en) {
 635                                         tso_header_sz += buf->outer_l2_len +
 636                                                          buf->outer_l3_len;
 637                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 638                                 } else {
 639                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 640                                 }
 641                                 if (unlikely(tso_header_sz >
 642                                              MLX5_MAX_TSO_HEADER))
 643                                         break;
 644                                 copy_b = tso_header_sz - pkt_inline_sz;
 645                                 /* First seg must contain all headers. */
 646                                 assert(copy_b <= length);
 647                                 raw += MLX5_WQE_DWORD_SIZE;
 648                                 if (copy_b &&
 649                                    ((end - (uintptr_t)raw) > copy_b)) {
 650                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 651                                                       1 + 3) / 4;
 652
 653                                         if (unlikely(max_wqe < n))
 654                                                 break;
 655                                         max_wqe -= n;
 656                                         rte_memcpy((void *)raw,
 657                                                    (void *)addr, copy_b);
 658                                         addr += copy_b;
 659                                         length -= copy_b;
 660                                         pkt_inline_sz += copy_b;
 661                                         /*
 662                                          * Another DWORD will be added
 663                                          * in the inline part.
 664                                          */
 665                                         raw += MLX5_WQE_DS(copy_b) *
 666                                                MLX5_WQE_DWORD_SIZE -
 667                                                MLX5_WQE_DWORD_SIZE;
 668                                 } else {
 669                                         /* NOP WQE. */
 670                                         wqe->ctrl = (rte_v128u32_t){
 671                                                      htonl(txq->wqe_ci << 8),
 672                                                      htonl(txq->qp_num_8s | 1),
 673                                                      0,
 674                                                      0,
 675                                         };
 676                                         ds = 1;
 677                                         total_length = 0;
 678                                         k++;
 679                                         goto next_wqe;
 680                                 }
 681                         }
 682                 }
 683                 /* Inline if enough room. */
 684                 if (inline_en || tso) {
 685                         uintptr_t end = (uintptr_t)
 686                                 (((uintptr_t)txq->wqes) +
 687                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 688                         unsigned int inline_room = max_inline *
 689                                                    RTE_CACHE_LINE_SIZE -
 690                                                    (pkt_inline_sz - 2);
 691                         uintptr_t addr_end = (addr + inline_room) &
 692                                              ~(RTE_CACHE_LINE_SIZE - 1);
 693                         unsigned int copy_b = (addr_end > addr) ?
 694                                 RTE_MIN((addr_end - addr), length) :
 695                                 0;
 696
 697                         raw += MLX5_WQE_DWORD_SIZE;
 698                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 699                                 /*
 700                                  * One Dseg remains in the current WQE.  To
 701                                  * keep the computation positive, it is
 702                                  * removed after the bytes to Dseg conversion.
 703                                  */
 704                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 705
 706                                 if (unlikely(max_wqe < n))
 707                                         break;
 708                                 max_wqe -= n;
 709                                 if (tso) {
 710                                         uint32_t inl =
 711                                                 htonl(copy_b | MLX5_INLINE_SEG);
 712
 713                                         pkt_inline_sz =
 714                                                 MLX5_WQE_DS(tso_header_sz) *
 715                                                 MLX5_WQE_DWORD_SIZE;
 716                                         rte_memcpy((void *)raw,
 717                                                    (void *)&inl, sizeof(inl));
 718                                         raw += sizeof(inl);
 719                                         pkt_inline_sz += sizeof(inl);
 720                                 }
 721                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 722                                 addr += copy_b;
 723                                 length -= copy_b;
 724                                 pkt_inline_sz += copy_b;
 725                         }
 726                         /*
 727                          * 2 DWORDs consumed by the WQE header + ETH segment +
 728                          * the size of the inline part of the packet.
 729                          */
 730                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 731                         if (length > 0) {
 732                                 if (ds % (MLX5_WQE_SIZE /
 733                                           MLX5_WQE_DWORD_SIZE) == 0) {
 734                                         if (unlikely(--max_wqe == 0))
 735                                                 break;
 736                                         dseg = (volatile rte_v128u32_t *)
 737                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 738                                                            ds / 4);
 739                                 } else {
 740                                         dseg = (volatile rte_v128u32_t *)
 741                                                 ((uintptr_t)wqe +
 742                                                  (ds * MLX5_WQE_DWORD_SIZE));
 743                                 }
 744                                 goto use_dseg;
 745                         } else if (!segs_n) {
 746                                 goto next_pkt;
 747                         } else {
 748                                 /* dseg will be advance as part of next_seg */
 749                                 dseg = (volatile rte_v128u32_t *)
 750                                         ((uintptr_t)wqe +
 751                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 752                                 goto next_seg;
 753                         }
 754                 } else {
 755                         /*
 756                          * No inline has been done in the packet, only the
 757                          * Ethernet Header as been stored.
 758                          */
 759                         dseg = (volatile rte_v128u32_t *)
 760                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 761                         ds = 3;
 762 use_dseg:
 763                         /* Add the remaining packet as a simple ds. */
 764                         naddr = htonll(addr);
 765                         *dseg = (rte_v128u32_t){
 766                                 htonl(length),
 767                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 768                                 naddr,
 769                                 naddr >> 32,
 770                         };
 771                         ++ds;
 772                         if (!segs_n)
 773                                 goto next_pkt;
 774                 }
 775 next_seg:
 776                 assert(buf);
 777                 assert(ds);
 778                 assert(wqe);
 779                 /*
 780                  * Spill on next WQE when the current one does not have
 781                  * enough room left. Size of WQE must a be a multiple
 782                  * of data segment size.
 783                  */
 784                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 785                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 786                         if (unlikely(--max_wqe == 0))
 787                                 break;
 788                         dseg = (volatile rte_v128u32_t *)
 789                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 790                         rte_prefetch0(tx_mlx5_wqe(txq,
 791                                                   txq->wqe_ci + ds / 4 + 1));
 792                 } else {
 793                         ++dseg;
 794                 }
 795                 ++ds;
 796                 buf = buf->next;
 797                 assert(buf);
 798                 length = DATA_LEN(buf);
 799 #ifdef MLX5_PMD_SOFT_COUNTERS
 800                 total_length += length;
 801 #endif
 802                 /* Store segment information. */
 803                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 804                 *dseg = (rte_v128u32_t){
 805                         htonl(length),
 806                         txq_mp2mr(txq, txq_mb2mp(buf)),
 807                         naddr,
 808                         naddr >> 32,
 809                 };
 810                 elts_head = (elts_head + 1) & (elts_n - 1);
 811                 (*txq->elts)[elts_head] = buf;
 812                 ++sg;
 813                 /* Advance counter only if all segs are successfully posted. */
 814                 if (sg < segs_n)
 815                         goto next_seg;
 816                 else
 817                         j += sg;
 818 next_pkt:
 819                 elts_head = (elts_head + 1) & (elts_n - 1);
 820                 ++pkts;
 821                 ++i;
 822                 /* Initialize known and common part of the WQE structure. */
 823                 if (tso) {
 824                         wqe->ctrl = (rte_v128u32_t){
 825                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 826                                 htonl(txq->qp_num_8s | ds),
 827                                 0,
 828                                 0,
 829                         };
 830                         wqe->eseg = (rte_v128u32_t){
 831                                 0,
 832                                 cs_flags | (htons(tso_segsz) << 16),
 833                                 0,
 834                                 (ehdr << 16) | htons(tso_header_sz),
 835                         };
 836                 } else {
 837                         wqe->ctrl = (rte_v128u32_t){
 838                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 839                                 htonl(txq->qp_num_8s | ds),
 840                                 0,
 841                                 0,
 842                         };
 843                         wqe->eseg = (rte_v128u32_t){
 844                                 0,
 845                                 cs_flags,
 846                                 0,
 847                                 (ehdr << 16) | htons(pkt_inline_sz),
 848                         };
 849                 }
 850 next_wqe:
 851                 txq->wqe_ci += (ds + 3) / 4;
 852                 /* Save the last successful WQE for completion request */
 853                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 854 #ifdef MLX5_PMD_SOFT_COUNTERS
 855                 /* Increment sent bytes counter. */
 856                 txq->stats.obytes += total_length;
 857 #endif
 858         } while (i < pkts_n);
 859         /* Take a shortcut if nothing must be sent. */
 860         if (unlikely((i + k) == 0))
 861                 return 0;
 862         txq->elts_head = (txq->elts_head + i + j) & (elts_n - 1);
 863         /* Check whether completion threshold has been reached. */
 864         comp = txq->elts_comp + i + j + k;
 865         if (comp >= MLX5_TX_COMP_THRESH) {
 866                 /* Request completion on last WQE. */
 867                 last_wqe->ctrl2 = htonl(8);
 868                 /* Save elts_head in unused "immediate" field of WQE. */
 869                 last_wqe->ctrl3 = txq->elts_head;
 870                 txq->elts_comp = 0;
 871         } else {
 872                 txq->elts_comp = comp;
 873         }
 874 #ifdef MLX5_PMD_SOFT_COUNTERS
 875         /* Increment sent packets counter. */
 876         txq->stats.opackets += i;
 877 #endif
 878         /* Ring QP doorbell. */
 879         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 880         return i;
 881 }
 882
 883 /**
 884  * Open a MPW session.
 885  *
 886  * @param txq
 887  *   Pointer to TX queue structure.
 888  * @param mpw
 889  *   Pointer to MPW session structure.
 890  * @param length
 891  *   Packet length.
 892  */
 893 static inline void
 894 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 895 {
 896         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 897         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 898                 (volatile struct mlx5_wqe_data_seg (*)[])
 899                 tx_mlx5_wqe(txq, idx + 1);
 900
 901         mpw->state = MLX5_MPW_STATE_OPENED;
 902         mpw->pkts_n = 0;
 903         mpw->len = length;
 904         mpw->total_len = 0;
 905         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 906         mpw->wqe->eseg.mss = htons(length);
 907         mpw->wqe->eseg.inline_hdr_sz = 0;
 908         mpw->wqe->eseg.rsvd0 = 0;
 909         mpw->wqe->eseg.rsvd1 = 0;
 910         mpw->wqe->eseg.rsvd2 = 0;
 911         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 912                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 913         mpw->wqe->ctrl[2] = 0;
 914         mpw->wqe->ctrl[3] = 0;
 915         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 916                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 917         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 918                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 919         mpw->data.dseg[2] = &(*dseg)[0];
 920         mpw->data.dseg[3] = &(*dseg)[1];
 921         mpw->data.dseg[4] = &(*dseg)[2];
 922 }
 923
 924 /**
 925  * Close a MPW session.
 926  *
 927  * @param txq
 928  *   Pointer to TX queue structure.
 929  * @param mpw
 930  *   Pointer to MPW session structure.
 931  */
 932 static inline void
 933 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 934 {
 935         unsigned int num = mpw->pkts_n;
 936
 937         /*
 938          * Store size in multiple of 16 bytes. Control and Ethernet segments
 939          * count as 2.
 940          */
 941         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 942         mpw->state = MLX5_MPW_STATE_CLOSED;
 943         if (num < 3)
 944                 ++txq->wqe_ci;
 945         else
 946                 txq->wqe_ci += 2;
 947         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 948         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 949 }
 950
 951 /**
 952  * DPDK callback for TX with MPW support.
 953  *
 954  * @param dpdk_txq
 955  *   Generic pointer to TX queue structure.
 956  * @param[in] pkts
 957  *   Packets to transmit.
 958  * @param pkts_n
 959  *   Number of packets in array.
 960  *
 961  * @return
 962  *   Number of packets successfully transmitted (<= pkts_n).
 963  */
 964 uint16_t
 965 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 966 {
 967         struct txq *txq = (struct txq *)dpdk_txq;
 968         uint16_t elts_head = txq->elts_head;
 969         const unsigned int elts_n = 1 << txq->elts_n;
 970         unsigned int i = 0;
 971         unsigned int j = 0;
 972         unsigned int max;
 973         uint16_t max_wqe;
 974         unsigned int comp;
 975         struct mlx5_mpw mpw = {
 976                 .state = MLX5_MPW_STATE_CLOSED,
 977         };
 978
 979         if (unlikely(!pkts_n))
 980                 return 0;
 981         /* Prefetch first packet cacheline. */
 982         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 983         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 984         /* Start processing. */
 985         txq_complete(txq);
 986         max = (elts_n - (elts_head - txq->elts_tail));
 987         if (max > elts_n)
 988                 max -= elts_n;
 989         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 990         if (unlikely(!max_wqe))
 991                 return 0;
 992         do {
 993                 struct rte_mbuf *buf = *(pkts++);
 994                 unsigned int elts_head_next;
 995                 uint32_t length;
 996                 unsigned int segs_n = buf->nb_segs;
 997                 uint32_t cs_flags = 0;
 998
 999                 /*
1000                  * Make sure there is enough room to store this packet and
1001                  * that one ring entry remains unused.
1002                  */
1003                 assert(segs_n);
1004                 if (max < segs_n + 1)
1005                         break;
1006                 /* Do not bother with large packets MPW cannot handle. */
1007                 if (segs_n > MLX5_MPW_DSEG_MAX)
1008                         break;
1009                 max -= segs_n;
1010                 --pkts_n;
1011                 /* Should we enable HW CKSUM offload */
1012                 if (buf->ol_flags &
1013                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1014                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1015                 /* Retrieve packet information. */
1016                 length = PKT_LEN(buf);
1017                 assert(length);
1018                 /* Start new session if packet differs. */
1019                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1020                     ((mpw.len != length) ||
1021                      (segs_n != 1) ||
1022                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1023                         mlx5_mpw_close(txq, &mpw);
1024                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1025                         /*
1026                          * Multi-Packet WQE consumes at most two WQE.
1027                          * mlx5_mpw_new() expects to be able to use such
1028                          * resources.
1029                          */
1030                         if (unlikely(max_wqe < 2))
1031                                 break;
1032                         max_wqe -= 2;
1033                         mlx5_mpw_new(txq, &mpw, length);
1034                         mpw.wqe->eseg.cs_flags = cs_flags;
1035                 }
1036                 /* Multi-segment packets must be alone in their MPW. */
1037                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1038 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1039                 length = 0;
1040 #endif
1041                 do {
1042                         volatile struct mlx5_wqe_data_seg *dseg;
1043                         uintptr_t addr;
1044
1045                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1046                         assert(buf);
1047                         (*txq->elts)[elts_head] = buf;
1048                         dseg = mpw.data.dseg[mpw.pkts_n];
1049                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1050                         *dseg = (struct mlx5_wqe_data_seg){
1051                                 .byte_count = htonl(DATA_LEN(buf)),
1052                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1053                                 .addr = htonll(addr),
1054                         };
1055                         elts_head = elts_head_next;
1056 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1057                         length += DATA_LEN(buf);
1058 #endif
1059                         buf = buf->next;
1060                         ++mpw.pkts_n;
1061                         ++j;
1062                 } while (--segs_n);
1063                 assert(length == mpw.len);
1064                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1065                         mlx5_mpw_close(txq, &mpw);
1066                 elts_head = elts_head_next;
1067 #ifdef MLX5_PMD_SOFT_COUNTERS
1068                 /* Increment sent bytes counter. */
1069                 txq->stats.obytes += length;
1070 #endif
1071                 ++i;
1072         } while (pkts_n);
1073         /* Take a shortcut if nothing must be sent. */
1074         if (unlikely(i == 0))
1075                 return 0;
1076         /* Check whether completion threshold has been reached. */
1077         /* "j" includes both packets and segments. */
1078         comp = txq->elts_comp + j;
1079         if (comp >= MLX5_TX_COMP_THRESH) {
1080                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1081
1082                 /* Request completion on last WQE. */
1083                 wqe->ctrl[2] = htonl(8);
1084                 /* Save elts_head in unused "immediate" field of WQE. */
1085                 wqe->ctrl[3] = elts_head;
1086                 txq->elts_comp = 0;
1087         } else {
1088                 txq->elts_comp = comp;
1089         }
1090 #ifdef MLX5_PMD_SOFT_COUNTERS
1091         /* Increment sent packets counter. */
1092         txq->stats.opackets += i;
1093 #endif
1094         /* Ring QP doorbell. */
1095         if (mpw.state == MLX5_MPW_STATE_OPENED)
1096                 mlx5_mpw_close(txq, &mpw);
1097         mlx5_tx_dbrec(txq, mpw.wqe);
1098         txq->elts_head = elts_head;
1099         return i;
1100 }
1101
1102 /**
1103  * Open a MPW inline session.
1104  *
1105  * @param txq
1106  *   Pointer to TX queue structure.
1107  * @param mpw
1108  *   Pointer to MPW session structure.
1109  * @param length
1110  *   Packet length.
1111  */
1112 static inline void
1113 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1114 {
1115         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1116         struct mlx5_wqe_inl_small *inl;
1117
1118         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1119         mpw->pkts_n = 0;
1120         mpw->len = length;
1121         mpw->total_len = 0;
1122         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1123         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1124                                   (txq->wqe_ci << 8) |
1125                                   MLX5_OPCODE_TSO);
1126         mpw->wqe->ctrl[2] = 0;
1127         mpw->wqe->ctrl[3] = 0;
1128         mpw->wqe->eseg.mss = htons(length);
1129         mpw->wqe->eseg.inline_hdr_sz = 0;
1130         mpw->wqe->eseg.cs_flags = 0;
1131         mpw->wqe->eseg.rsvd0 = 0;
1132         mpw->wqe->eseg.rsvd1 = 0;
1133         mpw->wqe->eseg.rsvd2 = 0;
1134         inl = (struct mlx5_wqe_inl_small *)
1135                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1136         mpw->data.raw = (uint8_t *)&inl->raw;
1137 }
1138
1139 /**
1140  * Close a MPW inline session.
1141  *
1142  * @param txq
1143  *   Pointer to TX queue structure.
1144  * @param mpw
1145  *   Pointer to MPW session structure.
1146  */
1147 static inline void
1148 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1149 {
1150         unsigned int size;
1151         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1152                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1153
1154         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1155         /*
1156          * Store size in multiple of 16 bytes. Control and Ethernet segments
1157          * count as 2.
1158          */
1159         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1160         mpw->state = MLX5_MPW_STATE_CLOSED;
1161         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1162         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1163 }
1164
1165 /**
1166  * DPDK callback for TX with MPW inline support.
1167  *
1168  * @param dpdk_txq
1169  *   Generic pointer to TX queue structure.
1170  * @param[in] pkts
1171  *   Packets to transmit.
1172  * @param pkts_n
1173  *   Number of packets in array.
1174  *
1175  * @return
1176  *   Number of packets successfully transmitted (<= pkts_n).
1177  */
1178 uint16_t
1179 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1180                          uint16_t pkts_n)
1181 {
1182         struct txq *txq = (struct txq *)dpdk_txq;
1183         uint16_t elts_head = txq->elts_head;
1184         const unsigned int elts_n = 1 << txq->elts_n;
1185         unsigned int i = 0;
1186         unsigned int j = 0;
1187         unsigned int max;
1188         uint16_t max_wqe;
1189         unsigned int comp;
1190         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1191         struct mlx5_mpw mpw = {
1192                 .state = MLX5_MPW_STATE_CLOSED,
1193         };
1194         /*
1195          * Compute the maximum number of WQE which can be consumed by inline
1196          * code.
1197          * - 2 DSEG for:
1198          *   - 1 control segment,
1199          *   - 1 Ethernet segment,
1200          * - N Dseg from the inline request.
1201          */
1202         const unsigned int wqe_inl_n =
1203                 ((2 * MLX5_WQE_DWORD_SIZE +
1204                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1205                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1206
1207         if (unlikely(!pkts_n))
1208                 return 0;
1209         /* Prefetch first packet cacheline. */
1210         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1211         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1212         /* Start processing. */
1213         txq_complete(txq);
1214         max = (elts_n - (elts_head - txq->elts_tail));
1215         if (max > elts_n)
1216                 max -= elts_n;
1217         do {
1218                 struct rte_mbuf *buf = *(pkts++);
1219                 unsigned int elts_head_next;
1220                 uintptr_t addr;
1221                 uint32_t length;
1222                 unsigned int segs_n = buf->nb_segs;
1223                 uint32_t cs_flags = 0;
1224
1225                 /*
1226                  * Make sure there is enough room to store this packet and
1227                  * that one ring entry remains unused.
1228                  */
1229                 assert(segs_n);
1230                 if (max < segs_n + 1)
1231                         break;
1232                 /* Do not bother with large packets MPW cannot handle. */
1233                 if (segs_n > MLX5_MPW_DSEG_MAX)
1234                         break;
1235                 max -= segs_n;
1236                 --pkts_n;
1237                 /*
1238                  * Compute max_wqe in case less WQE were consumed in previous
1239                  * iteration.
1240                  */
1241                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1242                 /* Should we enable HW CKSUM offload */
1243                 if (buf->ol_flags &
1244                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1245                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1246                 /* Retrieve packet information. */
1247                 length = PKT_LEN(buf);
1248                 /* Start new session if packet differs. */
1249                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1250                         if ((mpw.len != length) ||
1251                             (segs_n != 1) ||
1252                             (mpw.wqe->eseg.cs_flags != cs_flags))
1253                                 mlx5_mpw_close(txq, &mpw);
1254                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1255                         if ((mpw.len != length) ||
1256                             (segs_n != 1) ||
1257                             (length > inline_room) ||
1258                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1259                                 mlx5_mpw_inline_close(txq, &mpw);
1260                                 inline_room =
1261                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1262                         }
1263                 }
1264                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1265                         if ((segs_n != 1) ||
1266                             (length > inline_room)) {
1267                                 /*
1268                                  * Multi-Packet WQE consumes at most two WQE.
1269                                  * mlx5_mpw_new() expects to be able to use
1270                                  * such resources.
1271                                  */
1272                                 if (unlikely(max_wqe < 2))
1273                                         break;
1274                                 max_wqe -= 2;
1275                                 mlx5_mpw_new(txq, &mpw, length);
1276                                 mpw.wqe->eseg.cs_flags = cs_flags;
1277                         } else {
1278                                 if (unlikely(max_wqe < wqe_inl_n))
1279                                         break;
1280                                 max_wqe -= wqe_inl_n;
1281                                 mlx5_mpw_inline_new(txq, &mpw, length);
1282                                 mpw.wqe->eseg.cs_flags = cs_flags;
1283                         }
1284                 }
1285                 /* Multi-segment packets must be alone in their MPW. */
1286                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1287                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1288                         assert(inline_room ==
1289                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1290 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1291                         length = 0;
1292 #endif
1293                         do {
1294                                 volatile struct mlx5_wqe_data_seg *dseg;
1295
1296                                 elts_head_next =
1297                                         (elts_head + 1) & (elts_n - 1);
1298                                 assert(buf);
1299                                 (*txq->elts)[elts_head] = buf;
1300                                 dseg = mpw.data.dseg[mpw.pkts_n];
1301                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1302                                 *dseg = (struct mlx5_wqe_data_seg){
1303                                         .byte_count = htonl(DATA_LEN(buf)),
1304                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1305                                         .addr = htonll(addr),
1306                                 };
1307                                 elts_head = elts_head_next;
1308 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1309                                 length += DATA_LEN(buf);
1310 #endif
1311                                 buf = buf->next;
1312                                 ++mpw.pkts_n;
1313                                 ++j;
1314                         } while (--segs_n);
1315                         assert(length == mpw.len);
1316                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1317                                 mlx5_mpw_close(txq, &mpw);
1318                 } else {
1319                         unsigned int max;
1320
1321                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1322                         assert(length <= inline_room);
1323                         assert(length == DATA_LEN(buf));
1324                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1325                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1326                         (*txq->elts)[elts_head] = buf;
1327                         /* Maximum number of bytes before wrapping. */
1328                         max = ((((uintptr_t)(txq->wqes)) +
1329                                 (1 << txq->wqe_n) *
1330                                 MLX5_WQE_SIZE) -
1331                                (uintptr_t)mpw.data.raw);
1332                         if (length > max) {
1333                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1334                                            (void *)addr,
1335                                            max);
1336                                 mpw.data.raw = (volatile void *)txq->wqes;
1337                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1338                                            (void *)(addr + max),
1339                                            length - max);
1340                                 mpw.data.raw += length - max;
1341                         } else {
1342                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1343                                            (void *)addr,
1344                                            length);
1345
1346                                 if (length == max)
1347                                         mpw.data.raw =
1348                                                 (volatile void *)txq->wqes;
1349                                 else
1350                                         mpw.data.raw += length;
1351                         }
1352                         ++mpw.pkts_n;
1353                         mpw.total_len += length;
1354                         ++j;
1355                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1356                                 mlx5_mpw_inline_close(txq, &mpw);
1357                                 inline_room =
1358                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1359                         } else {
1360                                 inline_room -= length;
1361                         }
1362                 }
1363                 elts_head = elts_head_next;
1364 #ifdef MLX5_PMD_SOFT_COUNTERS
1365                 /* Increment sent bytes counter. */
1366                 txq->stats.obytes += length;
1367 #endif
1368                 ++i;
1369         } while (pkts_n);
1370         /* Take a shortcut if nothing must be sent. */
1371         if (unlikely(i == 0))
1372                 return 0;
1373         /* Check whether completion threshold has been reached. */
1374         /* "j" includes both packets and segments. */
1375         comp = txq->elts_comp + j;
1376         if (comp >= MLX5_TX_COMP_THRESH) {
1377                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1378
1379                 /* Request completion on last WQE. */
1380                 wqe->ctrl[2] = htonl(8);
1381                 /* Save elts_head in unused "immediate" field of WQE. */
1382                 wqe->ctrl[3] = elts_head;
1383                 txq->elts_comp = 0;
1384         } else {
1385                 txq->elts_comp = comp;
1386         }
1387 #ifdef MLX5_PMD_SOFT_COUNTERS
1388         /* Increment sent packets counter. */
1389         txq->stats.opackets += i;
1390 #endif
1391         /* Ring QP doorbell. */
1392         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1393                 mlx5_mpw_inline_close(txq, &mpw);
1394         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1395                 mlx5_mpw_close(txq, &mpw);
1396         mlx5_tx_dbrec(txq, mpw.wqe);
1397         txq->elts_head = elts_head;
1398         return i;
1399 }
1400
1401 /**
1402  * Open an Enhanced MPW session.
1403  *
1404  * @param txq
1405  *   Pointer to TX queue structure.
1406  * @param mpw
1407  *   Pointer to MPW session structure.
1408  * @param length
1409  *   Packet length.
1410  */
1411 static inline void
1412 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1413 {
1414         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1415
1416         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1417         mpw->pkts_n = 0;
1418         mpw->total_len = sizeof(struct mlx5_wqe);
1419         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1420         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1421                                   (txq->wqe_ci << 8) |
1422                                   MLX5_OPCODE_ENHANCED_MPSW);
1423         mpw->wqe->ctrl[2] = 0;
1424         mpw->wqe->ctrl[3] = 0;
1425         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1426         if (unlikely(padding)) {
1427                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1428
1429                 /* Pad the first 2 DWORDs with zero-length inline header. */
1430                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1431                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1432                         htonl(MLX5_INLINE_SEG);
1433                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1434                 /* Start from the next WQEBB. */
1435                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1436         } else {
1437                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1438         }
1439 }
1440
1441 /**
1442  * Close an Enhanced MPW session.
1443  *
1444  * @param txq
1445  *   Pointer to TX queue structure.
1446  * @param mpw
1447  *   Pointer to MPW session structure.
1448  *
1449  * @return
1450  *   Number of consumed WQEs.
1451  */
1452 static inline uint16_t
1453 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1454 {
1455         uint16_t ret;
1456
1457         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1458          * count as 2.
1459          */
1460         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1461         mpw->state = MLX5_MPW_STATE_CLOSED;
1462         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1463         txq->wqe_ci += ret;
1464         return ret;
1465 }
1466
1467 /**
1468  * DPDK callback for TX with Enhanced MPW support.
1469  *
1470  * @param dpdk_txq
1471  *   Generic pointer to TX queue structure.
1472  * @param[in] pkts
1473  *   Packets to transmit.
1474  * @param pkts_n
1475  *   Number of packets in array.
1476  *
1477  * @return
1478  *   Number of packets successfully transmitted (<= pkts_n).
1479  */
1480 uint16_t
1481 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1482 {
1483         struct txq *txq = (struct txq *)dpdk_txq;
1484         uint16_t elts_head = txq->elts_head;
1485         const unsigned int elts_n = 1 << txq->elts_n;
1486         unsigned int i = 0;
1487         unsigned int j = 0;
1488         unsigned int max_elts;
1489         uint16_t max_wqe;
1490         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1491         unsigned int mpw_room = 0;
1492         unsigned int inl_pad = 0;
1493         uint32_t inl_hdr;
1494         struct mlx5_mpw mpw = {
1495                 .state = MLX5_MPW_STATE_CLOSED,
1496         };
1497
1498         if (unlikely(!pkts_n))
1499                 return 0;
1500         /* Start processing. */
1501         txq_complete(txq);
1502         max_elts = (elts_n - (elts_head - txq->elts_tail));
1503         if (max_elts > elts_n)
1504                 max_elts -= elts_n;
1505         /* A CQE slot must always be available. */
1506         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1507         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1508         if (unlikely(!max_wqe))
1509                 return 0;
1510         do {
1511                 struct rte_mbuf *buf = *(pkts++);
1512                 unsigned int elts_head_next;
1513                 uintptr_t addr;
1514                 uint64_t naddr;
1515                 unsigned int n;
1516                 unsigned int do_inline = 0; /* Whether inline is possible. */
1517                 uint32_t length;
1518                 unsigned int segs_n = buf->nb_segs;
1519                 uint32_t cs_flags = 0;
1520
1521                 /*
1522                  * Make sure there is enough room to store this packet and
1523                  * that one ring entry remains unused.
1524                  */
1525                 assert(segs_n);
1526                 if (max_elts - j < segs_n + 1)
1527                         break;
1528                 /* Do not bother with large packets MPW cannot handle. */
1529                 if (segs_n > MLX5_MPW_DSEG_MAX)
1530                         break;
1531                 /* Should we enable HW CKSUM offload. */
1532                 if (buf->ol_flags &
1533                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1534                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1535                 /* Retrieve packet information. */
1536                 length = PKT_LEN(buf);
1537                 /* Start new session if:
1538                  * - multi-segment packet
1539                  * - no space left even for a dseg
1540                  * - next packet can be inlined with a new WQE
1541                  * - cs_flag differs
1542                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1543                  * segmented packet.
1544                  */
1545                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1546                         if ((segs_n != 1) ||
1547                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1548                               mpw_room) ||
1549                             (length <= txq->inline_max_packet_sz &&
1550                              inl_pad + sizeof(inl_hdr) + length >
1551                               mpw_room) ||
1552                             (mpw.wqe->eseg.cs_flags != cs_flags))
1553                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1554                 }
1555                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1556                         if (unlikely(segs_n != 1)) {
1557                                 /* Fall back to legacy MPW.
1558                                  * A MPW session consumes 2 WQEs at most to
1559                                  * include MLX5_MPW_DSEG_MAX pointers.
1560                                  */
1561                                 if (unlikely(max_wqe < 2))
1562                                         break;
1563                                 mlx5_mpw_new(txq, &mpw, length);
1564                         } else {
1565                                 /* In Enhanced MPW, inline as much as the budget
1566                                  * is allowed. The remaining space is to be
1567                                  * filled with dsegs. If the title WQEBB isn't
1568                                  * padded, it will have 2 dsegs there.
1569                                  */
1570                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1571                                             (max_inline ? max_inline :
1572                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1573                                             MLX5_WQE_SIZE);
1574                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1575                                               mpw_room))
1576                                         break;
1577                                 /* Don't pad the title WQEBB to not waste WQ. */
1578                                 mlx5_empw_new(txq, &mpw, 0);
1579                                 mpw_room -= mpw.total_len;
1580                                 inl_pad = 0;
1581                                 do_inline =
1582                                         length <= txq->inline_max_packet_sz &&
1583                                         sizeof(inl_hdr) + length <= mpw_room &&
1584                                         !txq->mpw_hdr_dseg;
1585                         }
1586                         mpw.wqe->eseg.cs_flags = cs_flags;
1587                 } else {
1588                         /* Evaluate whether the next packet can be inlined.
1589                          * Inlininig is possible when:
1590                          * - length is less than configured value
1591                          * - length fits for remaining space
1592                          * - not required to fill the title WQEBB with dsegs
1593                          */
1594                         do_inline =
1595                                 length <= txq->inline_max_packet_sz &&
1596                                 inl_pad + sizeof(inl_hdr) + length <=
1597                                  mpw_room &&
1598                                 (!txq->mpw_hdr_dseg ||
1599                                  mpw.total_len >= MLX5_WQE_SIZE);
1600                 }
1601                 /* Multi-segment packets must be alone in their MPW. */
1602                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1603                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1604 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1605                         length = 0;
1606 #endif
1607                         do {
1608                                 volatile struct mlx5_wqe_data_seg *dseg;
1609
1610                                 elts_head_next =
1611                                         (elts_head + 1) & (elts_n - 1);
1612                                 assert(buf);
1613                                 (*txq->elts)[elts_head] = buf;
1614                                 dseg = mpw.data.dseg[mpw.pkts_n];
1615                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1616                                 *dseg = (struct mlx5_wqe_data_seg){
1617                                         .byte_count = htonl(DATA_LEN(buf)),
1618                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1619                                         .addr = htonll(addr),
1620                                 };
1621                                 elts_head = elts_head_next;
1622 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1623                                 length += DATA_LEN(buf);
1624 #endif
1625                                 buf = buf->next;
1626                                 ++j;
1627                                 ++mpw.pkts_n;
1628                         } while (--segs_n);
1629                         /* A multi-segmented packet takes one MPW session.
1630                          * TODO: Pack more multi-segmented packets if possible.
1631                          */
1632                         mlx5_mpw_close(txq, &mpw);
1633                         if (mpw.pkts_n < 3)
1634                                 max_wqe--;
1635                         else
1636                                 max_wqe -= 2;
1637                 } else if (do_inline) {
1638                         /* Inline packet into WQE. */
1639                         unsigned int max;
1640
1641                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1642                         assert(length == DATA_LEN(buf));
1643                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1644                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1645                         mpw.data.raw = (volatile void *)
1646                                 ((uintptr_t)mpw.data.raw + inl_pad);
1647                         max = tx_mlx5_wq_tailroom(txq,
1648                                         (void *)(uintptr_t)mpw.data.raw);
1649                         /* Copy inline header. */
1650                         mpw.data.raw = (volatile void *)
1651                                 mlx5_copy_to_wq(
1652                                           (void *)(uintptr_t)mpw.data.raw,
1653                                           &inl_hdr,
1654                                           sizeof(inl_hdr),
1655                                           (void *)(uintptr_t)txq->wqes,
1656                                           max);
1657                         max = tx_mlx5_wq_tailroom(txq,
1658                                         (void *)(uintptr_t)mpw.data.raw);
1659                         /* Copy packet data. */
1660                         mpw.data.raw = (volatile void *)
1661                                 mlx5_copy_to_wq(
1662                                           (void *)(uintptr_t)mpw.data.raw,
1663                                           (void *)addr,
1664                                           length,
1665                                           (void *)(uintptr_t)txq->wqes,
1666                                           max);
1667                         ++mpw.pkts_n;
1668                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1669                         /* No need to get completion as the entire packet is
1670                          * copied to WQ. Free the buf right away.
1671                          */
1672                         elts_head_next = elts_head;
1673                         rte_pktmbuf_free_seg(buf);
1674                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1675                         /* Add pad in the next packet if any. */
1676                         inl_pad = (((uintptr_t)mpw.data.raw +
1677                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1678                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1679                                   (uintptr_t)mpw.data.raw;
1680                 } else {
1681                         /* No inline. Load a dseg of packet pointer. */
1682                         volatile rte_v128u32_t *dseg;
1683
1684                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1685                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1686                         assert(length == DATA_LEN(buf));
1687                         if (!tx_mlx5_wq_tailroom(txq,
1688                                         (void *)((uintptr_t)mpw.data.raw
1689                                                 + inl_pad)))
1690                                 dseg = (volatile void *)txq->wqes;
1691                         else
1692                                 dseg = (volatile void *)
1693                                         ((uintptr_t)mpw.data.raw +
1694                                          inl_pad);
1695                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1696                         (*txq->elts)[elts_head] = buf;
1697                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1698                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1699                                 rte_prefetch2((void *)(addr +
1700                                                 n * RTE_CACHE_LINE_SIZE));
1701                         naddr = htonll(addr);
1702                         *dseg = (rte_v128u32_t) {
1703                                 htonl(length),
1704                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1705                                 naddr,
1706                                 naddr >> 32,
1707                         };
1708                         mpw.data.raw = (volatile void *)(dseg + 1);
1709                         mpw.total_len += (inl_pad + sizeof(*dseg));
1710                         ++j;
1711                         ++mpw.pkts_n;
1712                         mpw_room -= (inl_pad + sizeof(*dseg));
1713                         inl_pad = 0;
1714                 }
1715                 elts_head = elts_head_next;
1716 #ifdef MLX5_PMD_SOFT_COUNTERS
1717                 /* Increment sent bytes counter. */
1718                 txq->stats.obytes += length;
1719 #endif
1720                 ++i;
1721         } while (i < pkts_n);
1722         /* Take a shortcut if nothing must be sent. */
1723         if (unlikely(i == 0))
1724                 return 0;
1725         /* Check whether completion threshold has been reached. */
1726         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1727                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1728                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1729                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1730
1731                 /* Request completion on last WQE. */
1732                 wqe->ctrl[2] = htonl(8);
1733                 /* Save elts_head in unused "immediate" field of WQE. */
1734                 wqe->ctrl[3] = elts_head;
1735                 txq->elts_comp = 0;
1736                 txq->mpw_comp = txq->wqe_ci;
1737                 txq->cq_pi++;
1738         } else {
1739                 txq->elts_comp += j;
1740         }
1741 #ifdef MLX5_PMD_SOFT_COUNTERS
1742         /* Increment sent packets counter. */
1743         txq->stats.opackets += i;
1744 #endif
1745         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1746                 mlx5_empw_close(txq, &mpw);
1747         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1748                 mlx5_mpw_close(txq, &mpw);
1749         /* Ring QP doorbell. */
1750         mlx5_tx_dbrec(txq, mpw.wqe);
1751         txq->elts_head = elts_head;
1752         return i;
1753 }
1754
1755 /**
1756  * Translate RX completion flags to packet type.
1757  *
1758  * @param[in] cqe
1759  *   Pointer to CQE.
1760  *
1761  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1762  *
1763  * @return
1764  *   Packet type for struct rte_mbuf.
1765  */
1766 static inline uint32_t
1767 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1768 {
1769         uint32_t pkt_type;
1770         uint16_t flags = ntohs(cqe->hdr_type_etc);
1771
1772         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1773                 pkt_type =
1774                         TRANSPOSE(flags,
1775                                   MLX5_CQE_RX_IPV4_PACKET,
1776                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1777                         TRANSPOSE(flags,
1778                                   MLX5_CQE_RX_IPV6_PACKET,
1779                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1780                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1781                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1782                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1783         } else {
1784                 pkt_type =
1785                         TRANSPOSE(flags,
1786                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1787                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1788                         TRANSPOSE(flags,
1789                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1790                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1791         }
1792         return pkt_type;
1793 }
1794
1795 /**
1796  * Get size of the next packet for a given CQE. For compressed CQEs, the
1797  * consumer index is updated only once all packets of the current one have
1798  * been processed.
1799  *
1800  * @param rxq
1801  *   Pointer to RX queue.
1802  * @param cqe
1803  *   CQE to process.
1804  * @param[out] rss_hash
1805  *   Packet RSS Hash result.
1806  *
1807  * @return
1808  *   Packet size in bytes (0 if there is none), -1 in case of completion
1809  *   with error.
1810  */
1811 static inline int
1812 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1813                  uint16_t cqe_cnt, uint32_t *rss_hash)
1814 {
1815         struct rxq_zip *zip = &rxq->zip;
1816         uint16_t cqe_n = cqe_cnt + 1;
1817         int len = 0;
1818         uint16_t idx, end;
1819
1820         /* Process compressed data in the CQE and mini arrays. */
1821         if (zip->ai) {
1822                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1823                         (volatile struct mlx5_mini_cqe8 (*)[8])
1824                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1825
1826                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1827                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1828                 if ((++zip->ai & 7) == 0) {
1829                         /* Invalidate consumed CQEs */
1830                         idx = zip->ca;
1831                         end = zip->na;
1832                         while (idx != end) {
1833                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1834                                         MLX5_CQE_INVALIDATE;
1835                                 ++idx;
1836                         }
1837                         /*
1838                          * Increment consumer index to skip the number of
1839                          * CQEs consumed. Hardware leaves holes in the CQ
1840                          * ring for software use.
1841                          */
1842                         zip->ca = zip->na;
1843                         zip->na += 8;
1844                 }
1845                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1846                         /* Invalidate the rest */
1847                         idx = zip->ca;
1848                         end = zip->cq_ci;
1849
1850                         while (idx != end) {
1851                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1852                                         MLX5_CQE_INVALIDATE;
1853                                 ++idx;
1854                         }
1855                         rxq->cq_ci = zip->cq_ci;
1856                         zip->ai = 0;
1857                 }
1858         /* No compressed data, get next CQE and verify if it is compressed. */
1859         } else {
1860                 int ret;
1861                 int8_t op_own;
1862
1863                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1864                 if (unlikely(ret == 1))
1865                         return 0;
1866                 ++rxq->cq_ci;
1867                 op_own = cqe->op_own;
1868                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1869                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1870                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1871                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1872                                                           cqe_cnt]);
1873
1874                         /* Fix endianness. */
1875                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1876                         /*
1877                          * Current mini array position is the one returned by
1878                          * check_cqe64().
1879                          *
1880                          * If completion comprises several mini arrays, as a
1881                          * special case the second one is located 7 CQEs after
1882                          * the initial CQE instead of 8 for subsequent ones.
1883                          */
1884                         zip->ca = rxq->cq_ci;
1885                         zip->na = zip->ca + 7;
1886                         /* Compute the next non compressed CQE. */
1887                         --rxq->cq_ci;
1888                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1889                         /* Get packet size to return. */
1890                         len = ntohl((*mc)[0].byte_cnt);
1891                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1892                         zip->ai = 1;
1893                         /* Prefetch all the entries to be invalidated */
1894                         idx = zip->ca;
1895                         end = zip->cq_ci;
1896                         while (idx != end) {
1897                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1898                                 ++idx;
1899                         }
1900                 } else {
1901                         len = ntohl(cqe->byte_cnt);
1902                         *rss_hash = ntohl(cqe->rx_hash_res);
1903                 }
1904                 /* Error while receiving packet. */
1905                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1906                         return -1;
1907         }
1908         return len;
1909 }
1910
1911 /**
1912  * Translate RX completion flags to offload flags.
1913  *
1914  * @param[in] rxq
1915  *   Pointer to RX queue structure.
1916  * @param[in] cqe
1917  *   Pointer to CQE.
1918  *
1919  * @return
1920  *   Offload flags (ol_flags) for struct rte_mbuf.
1921  */
1922 static inline uint32_t
1923 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1924 {
1925         uint32_t ol_flags = 0;
1926         uint16_t flags = ntohs(cqe->hdr_type_etc);
1927
1928         ol_flags =
1929                 TRANSPOSE(flags,
1930                           MLX5_CQE_RX_L3_HDR_VALID,
1931                           PKT_RX_IP_CKSUM_GOOD) |
1932                 TRANSPOSE(flags,
1933                           MLX5_CQE_RX_L4_HDR_VALID,
1934                           PKT_RX_L4_CKSUM_GOOD);
1935         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1936                 ol_flags |=
1937                         TRANSPOSE(flags,
1938                                   MLX5_CQE_RX_L3_HDR_VALID,
1939                                   PKT_RX_IP_CKSUM_GOOD) |
1940                         TRANSPOSE(flags,
1941                                   MLX5_CQE_RX_L4_HDR_VALID,
1942                                   PKT_RX_L4_CKSUM_GOOD);
1943         return ol_flags;
1944 }
1945
1946 /**
1947  * DPDK callback for RX.
1948  *
1949  * @param dpdk_rxq
1950  *   Generic pointer to RX queue structure.
1951  * @param[out] pkts
1952  *   Array to store received packets.
1953  * @param pkts_n
1954  *   Maximum number of packets in array.
1955  *
1956  * @return
1957  *   Number of packets successfully received (<= pkts_n).
1958  */
1959 uint16_t
1960 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1961 {
1962         struct rxq *rxq = dpdk_rxq;
1963         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1964         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1965         const unsigned int sges_n = rxq->sges_n;
1966         struct rte_mbuf *pkt = NULL;
1967         struct rte_mbuf *seg = NULL;
1968         volatile struct mlx5_cqe *cqe =
1969                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1970         unsigned int i = 0;
1971         unsigned int rq_ci = rxq->rq_ci << sges_n;
1972         int len = 0; /* keep its value across iterations. */
1973
1974         while (pkts_n) {
1975                 unsigned int idx = rq_ci & wqe_cnt;
1976                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1977                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1978                 uint32_t rss_hash_res = 0;
1979
1980                 if (pkt)
1981                         NEXT(seg) = rep;
1982                 seg = rep;
1983                 rte_prefetch0(seg);
1984                 rte_prefetch0(cqe);
1985                 rte_prefetch0(wqe);
1986                 rep = rte_mbuf_raw_alloc(rxq->mp);
1987                 if (unlikely(rep == NULL)) {
1988                         ++rxq->stats.rx_nombuf;
1989                         if (!pkt) {
1990                                 /*
1991                                  * no buffers before we even started,
1992                                  * bail out silently.
1993                                  */
1994                                 break;
1995                         }
1996                         while (pkt != seg) {
1997                                 assert(pkt != (*rxq->elts)[idx]);
1998                                 rep = NEXT(pkt);
1999                                 NEXT(pkt) = NULL;
2000                                 NB_SEGS(pkt) = 1;
2001                                 rte_mbuf_raw_free(pkt);
2002                                 pkt = rep;
2003                         }
2004                         break;
2005                 }
2006                 if (!pkt) {
2007                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2008                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2009                                                &rss_hash_res);
2010                         if (!len) {
2011                                 rte_mbuf_raw_free(rep);
2012                                 break;
2013                         }
2014                         if (unlikely(len == -1)) {
2015                                 /* RX error, packet is likely too large. */
2016                                 rte_mbuf_raw_free(rep);
2017                                 ++rxq->stats.idropped;
2018                                 goto skip;
2019                         }
2020                         pkt = seg;
2021                         assert(len >= (rxq->crc_present << 2));
2022                         /* Update packet information. */
2023                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2024                         pkt->ol_flags = 0;
2025                         if (rss_hash_res && rxq->rss_hash) {
2026                                 pkt->hash.rss = rss_hash_res;
2027                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2028                         }
2029                         if (rxq->mark &&
2030                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2031                                 pkt->ol_flags |= PKT_RX_FDIR;
2032                                 if (cqe->sop_drop_qpn !=
2033                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2034                                         uint32_t mark = cqe->sop_drop_qpn;
2035
2036                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2037                                         pkt->hash.fdir.hi =
2038                                                 mlx5_flow_mark_get(mark);
2039                                 }
2040                         }
2041                         if (rxq->csum | rxq->csum_l2tun)
2042                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2043                         if (rxq->vlan_strip &&
2044                             (cqe->hdr_type_etc &
2045                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2046                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2047                                         PKT_RX_VLAN_STRIPPED;
2048                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2049                         }
2050                         if (rxq->crc_present)
2051                                 len -= ETHER_CRC_LEN;
2052                         PKT_LEN(pkt) = len;
2053                 }
2054                 DATA_LEN(rep) = DATA_LEN(seg);
2055                 PKT_LEN(rep) = PKT_LEN(seg);
2056                 SET_DATA_OFF(rep, DATA_OFF(seg));
2057                 NB_SEGS(rep) = NB_SEGS(seg);
2058                 PORT(rep) = PORT(seg);
2059                 NEXT(rep) = NULL;
2060                 (*rxq->elts)[idx] = rep;
2061                 /*
2062                  * Fill NIC descriptor with the new buffer.  The lkey and size
2063                  * of the buffers are already known, only the buffer address
2064                  * changes.
2065                  */
2066                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2067                 if (len > DATA_LEN(seg)) {
2068                         len -= DATA_LEN(seg);
2069                         ++NB_SEGS(pkt);
2070                         ++rq_ci;
2071                         continue;
2072                 }
2073                 DATA_LEN(seg) = len;
2074 #ifdef MLX5_PMD_SOFT_COUNTERS
2075                 /* Increment bytes counter. */
2076                 rxq->stats.ibytes += PKT_LEN(pkt);
2077 #endif
2078                 /* Return packet. */
2079                 *(pkts++) = pkt;
2080                 pkt = NULL;
2081                 --pkts_n;
2082                 ++i;
2083 skip:
2084                 /* Align consumer index to the next stride. */
2085                 rq_ci >>= sges_n;
2086                 ++rq_ci;
2087                 rq_ci <<= sges_n;
2088         }
2089         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2090                 return 0;
2091         /* Update the consumer index. */
2092         rxq->rq_ci = rq_ci >> sges_n;
2093         rte_wmb();
2094         *rxq->cq_db = htonl(rxq->cq_ci);
2095         rte_wmb();
2096         *rxq->rq_db = htonl(rxq->rq_ci);
2097 #ifdef MLX5_PMD_SOFT_COUNTERS
2098         /* Increment packets counter. */
2099         rxq->stats.ipackets += i;
2100 #endif
2101         return i;
2102 }
2103
2104 /**
2105  * Dummy DPDK callback for TX.
2106  *
2107  * This function is used to temporarily replace the real callback during
2108  * unsafe control operations on the queue, or in case of error.
2109  *
2110  * @param dpdk_txq
2111  *   Generic pointer to TX queue structure.
2112  * @param[in] pkts
2113  *   Packets to transmit.
2114  * @param pkts_n
2115  *   Number of packets in array.
2116  *
2117  * @return
2118  *   Number of packets successfully transmitted (<= pkts_n).
2119  */
2120 uint16_t
2121 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2122 {
2123         (void)dpdk_txq;
2124         (void)pkts;
2125         (void)pkts_n;
2126         return 0;
2127 }
2128
2129 /**
2130  * Dummy DPDK callback for RX.
2131  *
2132  * This function is used to temporarily replace the real callback during
2133  * unsafe control operations on the queue, or in case of error.
2134  *
2135  * @param dpdk_rxq
2136  *   Generic pointer to RX queue structure.
2137  * @param[out] pkts
2138  *   Array to store received packets.
2139  * @param pkts_n
2140  *   Maximum number of packets in array.
2141  *
2142  * @return
2143  *   Number of packets successfully received (<= pkts_n).
2144  */
2145 uint16_t
2146 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2147 {
2148         (void)dpdk_rxq;
2149         (void)pkts;
2150         (void)pkts_n;
2151         return 0;
2152 }