drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Return the size of tailroom of WQ.
 199  *
 200  * @param txq
 201  *   Pointer to TX queue structure.
 202  * @param addr
 203  *   Pointer to tail of WQ.
 204  *
 205  * @return
 206  *   Size of tailroom.
 207  */
 208 static inline size_t
 209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 210 {
 211         size_t tailroom;
 212         tailroom = (uintptr_t)(txq->wqes) +
 213                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 214                    (uintptr_t)addr;
 215         return tailroom;
 216 }
 217
 218 /**
 219  * Copy data to tailroom of circular queue.
 220  *
 221  * @param dst
 222  *   Pointer to destination.
 223  * @param src
 224  *   Pointer to source.
 225  * @param n
 226  *   Number of bytes to copy.
 227  * @param base
 228  *   Pointer to head of queue.
 229  * @param tailroom
 230  *   Size of tailroom from dst.
 231  *
 232  * @return
 233  *   Pointer after copied data.
 234  */
 235 static inline void *
 236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 237                 void *base, size_t tailroom)
 238 {
 239         void *ret;
 240
 241         if (n > tailroom) {
 242                 rte_memcpy(dst, src, tailroom);
 243                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 244                            n - tailroom);
 245                 ret = (uint8_t *)base + n - tailroom;
 246         } else {
 247                 rte_memcpy(dst, src, n);
 248                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 249         }
 250         return ret;
 251 }
 252
 253 /**
 254  * Manage TX completions.
 255  *
 256  * When sending a burst, mlx5_tx_burst() posts several WRs.
 257  *
 258  * @param txq
 259  *   Pointer to TX queue structure.
 260  */
 261 static inline void
 262 txq_complete(struct txq *txq)
 263 {
 264         const unsigned int elts_n = 1 << txq->elts_n;
 265         const unsigned int cqe_n = 1 << txq->cqe_n;
 266         const unsigned int cqe_cnt = cqe_n - 1;
 267         uint16_t elts_free = txq->elts_tail;
 268         uint16_t elts_tail;
 269         uint16_t cq_ci = txq->cq_ci;
 270         volatile struct mlx5_cqe *cqe = NULL;
 271         volatile struct mlx5_wqe_ctrl *ctrl;
 272
 273         do {
 274                 volatile struct mlx5_cqe *tmp;
 275
 276                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 277                 if (check_cqe(tmp, cqe_n, cq_ci))
 278                         break;
 279                 cqe = tmp;
 280 #ifndef NDEBUG
 281                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 282                         if (!check_cqe_seen(cqe))
 283                                 ERROR("unexpected compressed CQE, TX stopped");
 284                         return;
 285                 }
 286                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 287                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 288                         if (!check_cqe_seen(cqe))
 289                                 ERROR("unexpected error CQE, TX stopped");
 290                         return;
 291                 }
 292 #endif /* NDEBUG */
 293                 ++cq_ci;
 294         } while (1);
 295         if (unlikely(cqe == NULL))
 296                 return;
 297         txq->wqe_pi = ntohs(cqe->wqe_counter);
 298         ctrl = (volatile struct mlx5_wqe_ctrl *)
 299                 tx_mlx5_wqe(txq, txq->wqe_pi);
 300         elts_tail = ctrl->ctrl3;
 301         assert(elts_tail < (1 << txq->wqe_n));
 302         /* Free buffers. */
 303         while (elts_free != elts_tail) {
 304                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 305                 unsigned int elts_free_next =
 306                         (elts_free + 1) & (elts_n - 1);
 307                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 308
 309 #ifndef NDEBUG
 310                 /* Poisoning. */
 311                 memset(&(*txq->elts)[elts_free],
 312                        0x66,
 313                        sizeof((*txq->elts)[elts_free]));
 314 #endif
 315                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 316                 /* Only one segment needs to be freed. */
 317                 rte_pktmbuf_free_seg(elt);
 318                 elts_free = elts_free_next;
 319         }
 320         txq->cq_ci = cq_ci;
 321         txq->elts_tail = elts_tail;
 322         /* Update the consumer index. */
 323         rte_wmb();
 324         *txq->cq_db = htonl(cq_ci);
 325 }
 326
 327 /**
 328  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 329  * the cloned mbuf is allocated is returned instead.
 330  *
 331  * @param buf
 332  *   Pointer to mbuf.
 333  *
 334  * @return
 335  *   Memory pool where data is located for given mbuf.
 336  */
 337 static struct rte_mempool *
 338 txq_mb2mp(struct rte_mbuf *buf)
 339 {
 340         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 341                 return rte_mbuf_from_indirect(buf)->pool;
 342         return buf->pool;
 343 }
 344
 345 /**
 346  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 347  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 348  * remove an entry first.
 349  *
 350  * @param txq
 351  *   Pointer to TX queue structure.
 352  * @param[in] mp
 353  *   Memory Pool for which a Memory Region lkey must be returned.
 354  *
 355  * @return
 356  *   mr->lkey on success, (uint32_t)-1 on failure.
 357  */
 358 static inline uint32_t
 359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 360 {
 361         unsigned int i;
 362         uint32_t lkey = (uint32_t)-1;
 363
 364         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 365                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 366                         /* Unknown MP, add a new MR for it. */
 367                         break;
 368                 }
 369                 if (txq->mp2mr[i].mp == mp) {
 370                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 371                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 372                                txq->mp2mr[i].lkey);
 373                         lkey = txq->mp2mr[i].lkey;
 374                         break;
 375                 }
 376         }
 377         if (unlikely(lkey == (uint32_t)-1))
 378                 lkey = txq_mp2mr_reg(txq, mp, i);
 379         return lkey;
 380 }
 381
 382 /**
 383  * Ring TX queue doorbell.
 384  *
 385  * @param txq
 386  *   Pointer to TX queue structure.
 387  * @param wqe
 388  *   Pointer to the last WQE posted in the NIC.
 389  */
 390 static inline void
 391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 392 {
 393         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 394         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 395
 396         rte_wmb();
 397         *txq->qp_db = htonl(txq->wqe_ci);
 398         /* Ensure ordering between DB record and BF copy. */
 399         rte_wmb();
 400         *dst = *src;
 401 }
 402
 403 /**
 404  * DPDK callback to check the status of a tx descriptor.
 405  *
 406  * @param tx_queue
 407  *   The tx queue.
 408  * @param[in] offset
 409  *   The index of the descriptor in the ring.
 410  *
 411  * @return
 412  *   The status of the tx descriptor.
 413  */
 414 int
 415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 416 {
 417         struct txq *txq = tx_queue;
 418         const unsigned int elts_n = 1 << txq->elts_n;
 419         const unsigned int elts_cnt = elts_n - 1;
 420         unsigned int used;
 421
 422         txq_complete(txq);
 423         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 424         if (offset < used)
 425                 return RTE_ETH_TX_DESC_FULL;
 426         return RTE_ETH_TX_DESC_DONE;
 427 }
 428
 429 /**
 430  * DPDK callback to check the status of a rx descriptor.
 431  *
 432  * @param rx_queue
 433  *   The rx queue.
 434  * @param[in] offset
 435  *   The index of the descriptor in the ring.
 436  *
 437  * @return
 438  *   The status of the tx descriptor.
 439  */
 440 int
 441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 442 {
 443         struct rxq *rxq = rx_queue;
 444         struct rxq_zip *zip = &rxq->zip;
 445         volatile struct mlx5_cqe *cqe;
 446         const unsigned int cqe_n = (1 << rxq->cqe_n);
 447         const unsigned int cqe_cnt = cqe_n - 1;
 448         unsigned int cq_ci;
 449         unsigned int used;
 450
 451         /* if we are processing a compressed cqe */
 452         if (zip->ai) {
 453                 used = zip->cqe_cnt - zip->ca;
 454                 cq_ci = zip->cq_ci;
 455         } else {
 456                 used = 0;
 457                 cq_ci = rxq->cq_ci;
 458         }
 459         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 461                 int8_t op_own;
 462                 unsigned int n;
 463
 464                 op_own = cqe->op_own;
 465                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 466                         n = ntohl(cqe->byte_cnt);
 467                 else
 468                         n = 1;
 469                 cq_ci += n;
 470                 used += n;
 471                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 472         }
 473         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 474         if (offset < used)
 475                 return RTE_ETH_RX_DESC_DONE;
 476         return RTE_ETH_RX_DESC_AVAIL;
 477 }
 478
 479 /**
 480  * DPDK callback for TX.
 481  *
 482  * @param dpdk_txq
 483  *   Generic pointer to TX queue structure.
 484  * @param[in] pkts
 485  *   Packets to transmit.
 486  * @param pkts_n
 487  *   Number of packets in array.
 488  *
 489  * @return
 490  *   Number of packets successfully transmitted (<= pkts_n).
 491  */
 492 uint16_t
 493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 494 {
 495         struct txq *txq = (struct txq *)dpdk_txq;
 496         uint16_t elts_head = txq->elts_head;
 497         const unsigned int elts_n = 1 << txq->elts_n;
 498         unsigned int i = 0;
 499         unsigned int j = 0;
 500         unsigned int k = 0;
 501         unsigned int max;
 502         unsigned int max_inline = txq->max_inline;
 503         const unsigned int inline_en = !!max_inline && txq->inline_en;
 504         uint16_t max_wqe;
 505         unsigned int comp;
 506         volatile struct mlx5_wqe_v *wqe = NULL;
 507         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 508         unsigned int segs_n = 0;
 509         struct rte_mbuf *buf = NULL;
 510         uint8_t *raw;
 511
 512         if (unlikely(!pkts_n))
 513                 return 0;
 514         /* Prefetch first packet cacheline. */
 515         rte_prefetch0(*pkts);
 516         /* Start processing. */
 517         txq_complete(txq);
 518         max = (elts_n - (elts_head - txq->elts_tail));
 519         if (max > elts_n)
 520                 max -= elts_n;
 521         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 522         if (unlikely(!max_wqe))
 523                 return 0;
 524         do {
 525                 volatile rte_v128u32_t *dseg = NULL;
 526                 uint32_t length;
 527                 unsigned int ds = 0;
 528                 unsigned int sg = 0; /* counter of additional segs attached. */
 529                 uintptr_t addr;
 530                 uint64_t naddr;
 531                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 532                 uint16_t tso_header_sz = 0;
 533                 uint16_t ehdr;
 534                 uint8_t cs_flags = 0;
 535                 uint64_t tso = 0;
 536 #ifdef MLX5_PMD_SOFT_COUNTERS
 537                 uint32_t total_length = 0;
 538 #endif
 539
 540                 /* first_seg */
 541                 buf = *pkts;
 542                 segs_n = buf->nb_segs;
 543                 /*
 544                  * Make sure there is enough room to store this packet and
 545                  * that one ring entry remains unused.
 546                  */
 547                 assert(segs_n);
 548                 if (max < segs_n + 1)
 549                         break;
 550                 max -= segs_n;
 551                 --segs_n;
 552                 if (unlikely(--max_wqe == 0))
 553                         break;
 554                 wqe = (volatile struct mlx5_wqe_v *)
 555                         tx_mlx5_wqe(txq, txq->wqe_ci);
 556                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 557                 if (pkts_n - i > 1)
 558                         rte_prefetch0(*(pkts + 1));
 559                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 560                 length = DATA_LEN(buf);
 561                 ehdr = (((uint8_t *)addr)[1] << 8) |
 562                        ((uint8_t *)addr)[0];
 563 #ifdef MLX5_PMD_SOFT_COUNTERS
 564                 total_length = length;
 565 #endif
 566                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 567                         break;
 568                 /* Update element. */
 569                 (*txq->elts)[elts_head] = buf;
 570                 /* Prefetch next buffer data. */
 571                 if (pkts_n - i > 1)
 572                         rte_prefetch0(
 573                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 574                 /* Should we enable HW CKSUM offload */
 575                 if (buf->ol_flags &
 576                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 577                         const uint64_t is_tunneled = buf->ol_flags &
 578                                                      (PKT_TX_TUNNEL_GRE |
 579                                                       PKT_TX_TUNNEL_VXLAN);
 580
 581                         if (is_tunneled && txq->tunnel_en) {
 582                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 583                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 584                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 585                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 586                         } else {
 587                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 588                                            MLX5_ETH_WQE_L4_CSUM;
 589                         }
 590                 }
 591                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 592                 /* Replace the Ethernet type by the VLAN if necessary. */
 593                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 594                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 595                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 596
 597                         addr += 2;
 598                         length -= 2;
 599                         /* Copy Destination and source mac address. */
 600                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 601                         /* Copy VLAN. */
 602                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 603                         /* Copy missing two bytes to end the DSeg. */
 604                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 605                                ((uint8_t *)addr) + len, 2);
 606                         addr += len + 2;
 607                         length -= (len + 2);
 608                 } else {
 609                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 610                                MLX5_WQE_DWORD_SIZE);
 611                         length -= pkt_inline_sz;
 612                         addr += pkt_inline_sz;
 613                 }
 614                 if (txq->tso_en) {
 615                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 616                         if (tso) {
 617                                 uintptr_t end = (uintptr_t)
 618                                                 (((uintptr_t)txq->wqes) +
 619                                                 (1 << txq->wqe_n) *
 620                                                 MLX5_WQE_SIZE);
 621                                 unsigned int copy_b;
 622                                 uint8_t vlan_sz = (buf->ol_flags &
 623                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 624                                 const uint64_t is_tunneled =
 625                                                         buf->ol_flags &
 626                                                         (PKT_TX_TUNNEL_GRE |
 627                                                          PKT_TX_TUNNEL_VXLAN);
 628
 629                                 tso_header_sz = buf->l2_len + vlan_sz +
 630                                                 buf->l3_len + buf->l4_len;
 631
 632                                 if (is_tunneled && txq->tunnel_en) {
 633                                         tso_header_sz += buf->outer_l2_len +
 634                                                          buf->outer_l3_len;
 635                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 636                                 } else {
 637                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 638                                 }
 639                                 if (unlikely(tso_header_sz >
 640                                              MLX5_MAX_TSO_HEADER))
 641                                         break;
 642                                 copy_b = tso_header_sz - pkt_inline_sz;
 643                                 /* First seg must contain all headers. */
 644                                 assert(copy_b <= length);
 645                                 raw += MLX5_WQE_DWORD_SIZE;
 646                                 if (copy_b &&
 647                                    ((end - (uintptr_t)raw) > copy_b)) {
 648                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 649                                                       1 + 3) / 4;
 650
 651                                         if (unlikely(max_wqe < n))
 652                                                 break;
 653                                         max_wqe -= n;
 654                                         rte_memcpy((void *)raw,
 655                                                    (void *)addr, copy_b);
 656                                         addr += copy_b;
 657                                         length -= copy_b;
 658                                         pkt_inline_sz += copy_b;
 659                                         /*
 660                                          * Another DWORD will be added
 661                                          * in the inline part.
 662                                          */
 663                                         raw += MLX5_WQE_DS(copy_b) *
 664                                                MLX5_WQE_DWORD_SIZE -
 665                                                MLX5_WQE_DWORD_SIZE;
 666                                 } else {
 667                                         /* NOP WQE. */
 668                                         wqe->ctrl = (rte_v128u32_t){
 669                                                      htonl(txq->wqe_ci << 8),
 670                                                      htonl(txq->qp_num_8s | 1),
 671                                                      0,
 672                                                      0,
 673                                         };
 674                                         ds = 1;
 675                                         total_length = 0;
 676                                         k++;
 677                                         goto next_wqe;
 678                                 }
 679                         }
 680                 }
 681                 /* Inline if enough room. */
 682                 if (inline_en || tso) {
 683                         uintptr_t end = (uintptr_t)
 684                                 (((uintptr_t)txq->wqes) +
 685                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 686                         unsigned int inline_room = max_inline *
 687                                                    RTE_CACHE_LINE_SIZE -
 688                                                    (pkt_inline_sz - 2);
 689                         uintptr_t addr_end = (addr + inline_room) &
 690                                              ~(RTE_CACHE_LINE_SIZE - 1);
 691                         unsigned int copy_b = (addr_end > addr) ?
 692                                 RTE_MIN((addr_end - addr), length) :
 693                                 0;
 694
 695                         raw += MLX5_WQE_DWORD_SIZE;
 696                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 697                                 /*
 698                                  * One Dseg remains in the current WQE.  To
 699                                  * keep the computation positive, it is
 700                                  * removed after the bytes to Dseg conversion.
 701                                  */
 702                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 703
 704                                 if (unlikely(max_wqe < n))
 705                                         break;
 706                                 max_wqe -= n;
 707                                 if (tso) {
 708                                         uint32_t inl =
 709                                                 htonl(copy_b | MLX5_INLINE_SEG);
 710
 711                                         pkt_inline_sz =
 712                                                 MLX5_WQE_DS(tso_header_sz) *
 713                                                 MLX5_WQE_DWORD_SIZE;
 714                                         rte_memcpy((void *)raw,
 715                                                    (void *)&inl, sizeof(inl));
 716                                         raw += sizeof(inl);
 717                                         pkt_inline_sz += sizeof(inl);
 718                                 }
 719                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 720                                 addr += copy_b;
 721                                 length -= copy_b;
 722                                 pkt_inline_sz += copy_b;
 723                         }
 724                         /*
 725                          * 2 DWORDs consumed by the WQE header + ETH segment +
 726                          * the size of the inline part of the packet.
 727                          */
 728                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 729                         if (length > 0) {
 730                                 if (ds % (MLX5_WQE_SIZE /
 731                                           MLX5_WQE_DWORD_SIZE) == 0) {
 732                                         if (unlikely(--max_wqe == 0))
 733                                                 break;
 734                                         dseg = (volatile rte_v128u32_t *)
 735                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 736                                                            ds / 4);
 737                                 } else {
 738                                         dseg = (volatile rte_v128u32_t *)
 739                                                 ((uintptr_t)wqe +
 740                                                  (ds * MLX5_WQE_DWORD_SIZE));
 741                                 }
 742                                 goto use_dseg;
 743                         } else if (!segs_n) {
 744                                 goto next_pkt;
 745                         } else {
 746                                 /* dseg will be advance as part of next_seg */
 747                                 dseg = (volatile rte_v128u32_t *)
 748                                         ((uintptr_t)wqe +
 749                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 750                                 goto next_seg;
 751                         }
 752                 } else {
 753                         /*
 754                          * No inline has been done in the packet, only the
 755                          * Ethernet Header as been stored.
 756                          */
 757                         dseg = (volatile rte_v128u32_t *)
 758                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 759                         ds = 3;
 760 use_dseg:
 761                         /* Add the remaining packet as a simple ds. */
 762                         naddr = htonll(addr);
 763                         *dseg = (rte_v128u32_t){
 764                                 htonl(length),
 765                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 766                                 naddr,
 767                                 naddr >> 32,
 768                         };
 769                         ++ds;
 770                         if (!segs_n)
 771                                 goto next_pkt;
 772                 }
 773 next_seg:
 774                 assert(buf);
 775                 assert(ds);
 776                 assert(wqe);
 777                 /*
 778                  * Spill on next WQE when the current one does not have
 779                  * enough room left. Size of WQE must a be a multiple
 780                  * of data segment size.
 781                  */
 782                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 783                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 784                         if (unlikely(--max_wqe == 0))
 785                                 break;
 786                         dseg = (volatile rte_v128u32_t *)
 787                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 788                         rte_prefetch0(tx_mlx5_wqe(txq,
 789                                                   txq->wqe_ci + ds / 4 + 1));
 790                 } else {
 791                         ++dseg;
 792                 }
 793                 ++ds;
 794                 buf = buf->next;
 795                 assert(buf);
 796                 length = DATA_LEN(buf);
 797 #ifdef MLX5_PMD_SOFT_COUNTERS
 798                 total_length += length;
 799 #endif
 800                 /* Store segment information. */
 801                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 802                 *dseg = (rte_v128u32_t){
 803                         htonl(length),
 804                         txq_mp2mr(txq, txq_mb2mp(buf)),
 805                         naddr,
 806                         naddr >> 32,
 807                 };
 808                 elts_head = (elts_head + 1) & (elts_n - 1);
 809                 (*txq->elts)[elts_head] = buf;
 810                 ++sg;
 811                 /* Advance counter only if all segs are successfully posted. */
 812                 if (sg < segs_n)
 813                         goto next_seg;
 814                 else
 815                         j += sg;
 816 next_pkt:
 817                 elts_head = (elts_head + 1) & (elts_n - 1);
 818                 ++pkts;
 819                 ++i;
 820                 /* Initialize known and common part of the WQE structure. */
 821                 if (tso) {
 822                         wqe->ctrl = (rte_v128u32_t){
 823                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 824                                 htonl(txq->qp_num_8s | ds),
 825                                 0,
 826                                 0,
 827                         };
 828                         wqe->eseg = (rte_v128u32_t){
 829                                 0,
 830                                 cs_flags | (htons(buf->tso_segsz) << 16),
 831                                 0,
 832                                 (ehdr << 16) | htons(tso_header_sz),
 833                         };
 834                 } else {
 835                         wqe->ctrl = (rte_v128u32_t){
 836                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 837                                 htonl(txq->qp_num_8s | ds),
 838                                 0,
 839                                 0,
 840                         };
 841                         wqe->eseg = (rte_v128u32_t){
 842                                 0,
 843                                 cs_flags,
 844                                 0,
 845                                 (ehdr << 16) | htons(pkt_inline_sz),
 846                         };
 847                 }
 848 next_wqe:
 849                 txq->wqe_ci += (ds + 3) / 4;
 850                 /* Save the last successful WQE for completion request */
 851                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 852 #ifdef MLX5_PMD_SOFT_COUNTERS
 853                 /* Increment sent bytes counter. */
 854                 txq->stats.obytes += total_length;
 855 #endif
 856         } while (i < pkts_n);
 857         /* Take a shortcut if nothing must be sent. */
 858         if (unlikely((i + k) == 0))
 859                 return 0;
 860         txq->elts_head = (txq->elts_head + i + j) & (elts_n - 1);
 861         /* Check whether completion threshold has been reached. */
 862         comp = txq->elts_comp + i + j + k;
 863         if (comp >= MLX5_TX_COMP_THRESH) {
 864                 /* Request completion on last WQE. */
 865                 last_wqe->ctrl2 = htonl(8);
 866                 /* Save elts_head in unused "immediate" field of WQE. */
 867                 last_wqe->ctrl3 = txq->elts_head;
 868                 txq->elts_comp = 0;
 869         } else {
 870                 txq->elts_comp = comp;
 871         }
 872 #ifdef MLX5_PMD_SOFT_COUNTERS
 873         /* Increment sent packets counter. */
 874         txq->stats.opackets += i;
 875 #endif
 876         /* Ring QP doorbell. */
 877         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 878         return i;
 879 }
 880
 881 /**
 882  * Open a MPW session.
 883  *
 884  * @param txq
 885  *   Pointer to TX queue structure.
 886  * @param mpw
 887  *   Pointer to MPW session structure.
 888  * @param length
 889  *   Packet length.
 890  */
 891 static inline void
 892 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 893 {
 894         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 895         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 896                 (volatile struct mlx5_wqe_data_seg (*)[])
 897                 tx_mlx5_wqe(txq, idx + 1);
 898
 899         mpw->state = MLX5_MPW_STATE_OPENED;
 900         mpw->pkts_n = 0;
 901         mpw->len = length;
 902         mpw->total_len = 0;
 903         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 904         mpw->wqe->eseg.mss = htons(length);
 905         mpw->wqe->eseg.inline_hdr_sz = 0;
 906         mpw->wqe->eseg.rsvd0 = 0;
 907         mpw->wqe->eseg.rsvd1 = 0;
 908         mpw->wqe->eseg.rsvd2 = 0;
 909         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 910                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 911         mpw->wqe->ctrl[2] = 0;
 912         mpw->wqe->ctrl[3] = 0;
 913         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 914                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 915         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 916                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 917         mpw->data.dseg[2] = &(*dseg)[0];
 918         mpw->data.dseg[3] = &(*dseg)[1];
 919         mpw->data.dseg[4] = &(*dseg)[2];
 920 }
 921
 922 /**
 923  * Close a MPW session.
 924  *
 925  * @param txq
 926  *   Pointer to TX queue structure.
 927  * @param mpw
 928  *   Pointer to MPW session structure.
 929  */
 930 static inline void
 931 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 932 {
 933         unsigned int num = mpw->pkts_n;
 934
 935         /*
 936          * Store size in multiple of 16 bytes. Control and Ethernet segments
 937          * count as 2.
 938          */
 939         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 940         mpw->state = MLX5_MPW_STATE_CLOSED;
 941         if (num < 3)
 942                 ++txq->wqe_ci;
 943         else
 944                 txq->wqe_ci += 2;
 945         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 946         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 947 }
 948
 949 /**
 950  * DPDK callback for TX with MPW support.
 951  *
 952  * @param dpdk_txq
 953  *   Generic pointer to TX queue structure.
 954  * @param[in] pkts
 955  *   Packets to transmit.
 956  * @param pkts_n
 957  *   Number of packets in array.
 958  *
 959  * @return
 960  *   Number of packets successfully transmitted (<= pkts_n).
 961  */
 962 uint16_t
 963 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 964 {
 965         struct txq *txq = (struct txq *)dpdk_txq;
 966         uint16_t elts_head = txq->elts_head;
 967         const unsigned int elts_n = 1 << txq->elts_n;
 968         unsigned int i = 0;
 969         unsigned int j = 0;
 970         unsigned int max;
 971         uint16_t max_wqe;
 972         unsigned int comp;
 973         struct mlx5_mpw mpw = {
 974                 .state = MLX5_MPW_STATE_CLOSED,
 975         };
 976
 977         if (unlikely(!pkts_n))
 978                 return 0;
 979         /* Prefetch first packet cacheline. */
 980         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 981         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 982         /* Start processing. */
 983         txq_complete(txq);
 984         max = (elts_n - (elts_head - txq->elts_tail));
 985         if (max > elts_n)
 986                 max -= elts_n;
 987         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 988         if (unlikely(!max_wqe))
 989                 return 0;
 990         do {
 991                 struct rte_mbuf *buf = *(pkts++);
 992                 unsigned int elts_head_next;
 993                 uint32_t length;
 994                 unsigned int segs_n = buf->nb_segs;
 995                 uint32_t cs_flags = 0;
 996
 997                 /*
 998                  * Make sure there is enough room to store this packet and
 999                  * that one ring entry remains unused.
1000                  */
1001                 assert(segs_n);
1002                 if (max < segs_n + 1)
1003                         break;
1004                 /* Do not bother with large packets MPW cannot handle. */
1005                 if (segs_n > MLX5_MPW_DSEG_MAX)
1006                         break;
1007                 max -= segs_n;
1008                 --pkts_n;
1009                 /* Should we enable HW CKSUM offload */
1010                 if (buf->ol_flags &
1011                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1012                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1013                 /* Retrieve packet information. */
1014                 length = PKT_LEN(buf);
1015                 assert(length);
1016                 /* Start new session if packet differs. */
1017                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1018                     ((mpw.len != length) ||
1019                      (segs_n != 1) ||
1020                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1021                         mlx5_mpw_close(txq, &mpw);
1022                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1023                         /*
1024                          * Multi-Packet WQE consumes at most two WQE.
1025                          * mlx5_mpw_new() expects to be able to use such
1026                          * resources.
1027                          */
1028                         if (unlikely(max_wqe < 2))
1029                                 break;
1030                         max_wqe -= 2;
1031                         mlx5_mpw_new(txq, &mpw, length);
1032                         mpw.wqe->eseg.cs_flags = cs_flags;
1033                 }
1034                 /* Multi-segment packets must be alone in their MPW. */
1035                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1036 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1037                 length = 0;
1038 #endif
1039                 do {
1040                         volatile struct mlx5_wqe_data_seg *dseg;
1041                         uintptr_t addr;
1042
1043                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1044                         assert(buf);
1045                         (*txq->elts)[elts_head] = buf;
1046                         dseg = mpw.data.dseg[mpw.pkts_n];
1047                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1048                         *dseg = (struct mlx5_wqe_data_seg){
1049                                 .byte_count = htonl(DATA_LEN(buf)),
1050                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1051                                 .addr = htonll(addr),
1052                         };
1053                         elts_head = elts_head_next;
1054 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1055                         length += DATA_LEN(buf);
1056 #endif
1057                         buf = buf->next;
1058                         ++mpw.pkts_n;
1059                         ++j;
1060                 } while (--segs_n);
1061                 assert(length == mpw.len);
1062                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1063                         mlx5_mpw_close(txq, &mpw);
1064                 elts_head = elts_head_next;
1065 #ifdef MLX5_PMD_SOFT_COUNTERS
1066                 /* Increment sent bytes counter. */
1067                 txq->stats.obytes += length;
1068 #endif
1069                 ++i;
1070         } while (pkts_n);
1071         /* Take a shortcut if nothing must be sent. */
1072         if (unlikely(i == 0))
1073                 return 0;
1074         /* Check whether completion threshold has been reached. */
1075         /* "j" includes both packets and segments. */
1076         comp = txq->elts_comp + j;
1077         if (comp >= MLX5_TX_COMP_THRESH) {
1078                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1079
1080                 /* Request completion on last WQE. */
1081                 wqe->ctrl[2] = htonl(8);
1082                 /* Save elts_head in unused "immediate" field of WQE. */
1083                 wqe->ctrl[3] = elts_head;
1084                 txq->elts_comp = 0;
1085         } else {
1086                 txq->elts_comp = comp;
1087         }
1088 #ifdef MLX5_PMD_SOFT_COUNTERS
1089         /* Increment sent packets counter. */
1090         txq->stats.opackets += i;
1091 #endif
1092         /* Ring QP doorbell. */
1093         if (mpw.state == MLX5_MPW_STATE_OPENED)
1094                 mlx5_mpw_close(txq, &mpw);
1095         mlx5_tx_dbrec(txq, mpw.wqe);
1096         txq->elts_head = elts_head;
1097         return i;
1098 }
1099
1100 /**
1101  * Open a MPW inline session.
1102  *
1103  * @param txq
1104  *   Pointer to TX queue structure.
1105  * @param mpw
1106  *   Pointer to MPW session structure.
1107  * @param length
1108  *   Packet length.
1109  */
1110 static inline void
1111 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1112 {
1113         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1114         struct mlx5_wqe_inl_small *inl;
1115
1116         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1117         mpw->pkts_n = 0;
1118         mpw->len = length;
1119         mpw->total_len = 0;
1120         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1121         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1122                                   (txq->wqe_ci << 8) |
1123                                   MLX5_OPCODE_TSO);
1124         mpw->wqe->ctrl[2] = 0;
1125         mpw->wqe->ctrl[3] = 0;
1126         mpw->wqe->eseg.mss = htons(length);
1127         mpw->wqe->eseg.inline_hdr_sz = 0;
1128         mpw->wqe->eseg.cs_flags = 0;
1129         mpw->wqe->eseg.rsvd0 = 0;
1130         mpw->wqe->eseg.rsvd1 = 0;
1131         mpw->wqe->eseg.rsvd2 = 0;
1132         inl = (struct mlx5_wqe_inl_small *)
1133                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1134         mpw->data.raw = (uint8_t *)&inl->raw;
1135 }
1136
1137 /**
1138  * Close a MPW inline session.
1139  *
1140  * @param txq
1141  *   Pointer to TX queue structure.
1142  * @param mpw
1143  *   Pointer to MPW session structure.
1144  */
1145 static inline void
1146 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1147 {
1148         unsigned int size;
1149         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1150                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1151
1152         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1153         /*
1154          * Store size in multiple of 16 bytes. Control and Ethernet segments
1155          * count as 2.
1156          */
1157         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1158         mpw->state = MLX5_MPW_STATE_CLOSED;
1159         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1160         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1161 }
1162
1163 /**
1164  * DPDK callback for TX with MPW inline support.
1165  *
1166  * @param dpdk_txq
1167  *   Generic pointer to TX queue structure.
1168  * @param[in] pkts
1169  *   Packets to transmit.
1170  * @param pkts_n
1171  *   Number of packets in array.
1172  *
1173  * @return
1174  *   Number of packets successfully transmitted (<= pkts_n).
1175  */
1176 uint16_t
1177 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1178                          uint16_t pkts_n)
1179 {
1180         struct txq *txq = (struct txq *)dpdk_txq;
1181         uint16_t elts_head = txq->elts_head;
1182         const unsigned int elts_n = 1 << txq->elts_n;
1183         unsigned int i = 0;
1184         unsigned int j = 0;
1185         unsigned int max;
1186         uint16_t max_wqe;
1187         unsigned int comp;
1188         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1189         struct mlx5_mpw mpw = {
1190                 .state = MLX5_MPW_STATE_CLOSED,
1191         };
1192         /*
1193          * Compute the maximum number of WQE which can be consumed by inline
1194          * code.
1195          * - 2 DSEG for:
1196          *   - 1 control segment,
1197          *   - 1 Ethernet segment,
1198          * - N Dseg from the inline request.
1199          */
1200         const unsigned int wqe_inl_n =
1201                 ((2 * MLX5_WQE_DWORD_SIZE +
1202                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1203                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1204
1205         if (unlikely(!pkts_n))
1206                 return 0;
1207         /* Prefetch first packet cacheline. */
1208         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1209         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1210         /* Start processing. */
1211         txq_complete(txq);
1212         max = (elts_n - (elts_head - txq->elts_tail));
1213         if (max > elts_n)
1214                 max -= elts_n;
1215         do {
1216                 struct rte_mbuf *buf = *(pkts++);
1217                 unsigned int elts_head_next;
1218                 uintptr_t addr;
1219                 uint32_t length;
1220                 unsigned int segs_n = buf->nb_segs;
1221                 uint32_t cs_flags = 0;
1222
1223                 /*
1224                  * Make sure there is enough room to store this packet and
1225                  * that one ring entry remains unused.
1226                  */
1227                 assert(segs_n);
1228                 if (max < segs_n + 1)
1229                         break;
1230                 /* Do not bother with large packets MPW cannot handle. */
1231                 if (segs_n > MLX5_MPW_DSEG_MAX)
1232                         break;
1233                 max -= segs_n;
1234                 --pkts_n;
1235                 /*
1236                  * Compute max_wqe in case less WQE were consumed in previous
1237                  * iteration.
1238                  */
1239                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1240                 /* Should we enable HW CKSUM offload */
1241                 if (buf->ol_flags &
1242                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1243                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1244                 /* Retrieve packet information. */
1245                 length = PKT_LEN(buf);
1246                 /* Start new session if packet differs. */
1247                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1248                         if ((mpw.len != length) ||
1249                             (segs_n != 1) ||
1250                             (mpw.wqe->eseg.cs_flags != cs_flags))
1251                                 mlx5_mpw_close(txq, &mpw);
1252                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1253                         if ((mpw.len != length) ||
1254                             (segs_n != 1) ||
1255                             (length > inline_room) ||
1256                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1257                                 mlx5_mpw_inline_close(txq, &mpw);
1258                                 inline_room =
1259                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1260                         }
1261                 }
1262                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1263                         if ((segs_n != 1) ||
1264                             (length > inline_room)) {
1265                                 /*
1266                                  * Multi-Packet WQE consumes at most two WQE.
1267                                  * mlx5_mpw_new() expects to be able to use
1268                                  * such resources.
1269                                  */
1270                                 if (unlikely(max_wqe < 2))
1271                                         break;
1272                                 max_wqe -= 2;
1273                                 mlx5_mpw_new(txq, &mpw, length);
1274                                 mpw.wqe->eseg.cs_flags = cs_flags;
1275                         } else {
1276                                 if (unlikely(max_wqe < wqe_inl_n))
1277                                         break;
1278                                 max_wqe -= wqe_inl_n;
1279                                 mlx5_mpw_inline_new(txq, &mpw, length);
1280                                 mpw.wqe->eseg.cs_flags = cs_flags;
1281                         }
1282                 }
1283                 /* Multi-segment packets must be alone in their MPW. */
1284                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1285                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1286                         assert(inline_room ==
1287                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1288 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1289                         length = 0;
1290 #endif
1291                         do {
1292                                 volatile struct mlx5_wqe_data_seg *dseg;
1293
1294                                 elts_head_next =
1295                                         (elts_head + 1) & (elts_n - 1);
1296                                 assert(buf);
1297                                 (*txq->elts)[elts_head] = buf;
1298                                 dseg = mpw.data.dseg[mpw.pkts_n];
1299                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1300                                 *dseg = (struct mlx5_wqe_data_seg){
1301                                         .byte_count = htonl(DATA_LEN(buf)),
1302                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1303                                         .addr = htonll(addr),
1304                                 };
1305                                 elts_head = elts_head_next;
1306 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1307                                 length += DATA_LEN(buf);
1308 #endif
1309                                 buf = buf->next;
1310                                 ++mpw.pkts_n;
1311                                 ++j;
1312                         } while (--segs_n);
1313                         assert(length == mpw.len);
1314                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1315                                 mlx5_mpw_close(txq, &mpw);
1316                 } else {
1317                         unsigned int max;
1318
1319                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1320                         assert(length <= inline_room);
1321                         assert(length == DATA_LEN(buf));
1322                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1323                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1324                         (*txq->elts)[elts_head] = buf;
1325                         /* Maximum number of bytes before wrapping. */
1326                         max = ((((uintptr_t)(txq->wqes)) +
1327                                 (1 << txq->wqe_n) *
1328                                 MLX5_WQE_SIZE) -
1329                                (uintptr_t)mpw.data.raw);
1330                         if (length > max) {
1331                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1332                                            (void *)addr,
1333                                            max);
1334                                 mpw.data.raw = (volatile void *)txq->wqes;
1335                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1336                                            (void *)(addr + max),
1337                                            length - max);
1338                                 mpw.data.raw += length - max;
1339                         } else {
1340                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1341                                            (void *)addr,
1342                                            length);
1343
1344                                 if (length == max)
1345                                         mpw.data.raw =
1346                                                 (volatile void *)txq->wqes;
1347                                 else
1348                                         mpw.data.raw += length;
1349                         }
1350                         ++mpw.pkts_n;
1351                         mpw.total_len += length;
1352                         ++j;
1353                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1354                                 mlx5_mpw_inline_close(txq, &mpw);
1355                                 inline_room =
1356                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1357                         } else {
1358                                 inline_room -= length;
1359                         }
1360                 }
1361                 elts_head = elts_head_next;
1362 #ifdef MLX5_PMD_SOFT_COUNTERS
1363                 /* Increment sent bytes counter. */
1364                 txq->stats.obytes += length;
1365 #endif
1366                 ++i;
1367         } while (pkts_n);
1368         /* Take a shortcut if nothing must be sent. */
1369         if (unlikely(i == 0))
1370                 return 0;
1371         /* Check whether completion threshold has been reached. */
1372         /* "j" includes both packets and segments. */
1373         comp = txq->elts_comp + j;
1374         if (comp >= MLX5_TX_COMP_THRESH) {
1375                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1376
1377                 /* Request completion on last WQE. */
1378                 wqe->ctrl[2] = htonl(8);
1379                 /* Save elts_head in unused "immediate" field of WQE. */
1380                 wqe->ctrl[3] = elts_head;
1381                 txq->elts_comp = 0;
1382         } else {
1383                 txq->elts_comp = comp;
1384         }
1385 #ifdef MLX5_PMD_SOFT_COUNTERS
1386         /* Increment sent packets counter. */
1387         txq->stats.opackets += i;
1388 #endif
1389         /* Ring QP doorbell. */
1390         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1391                 mlx5_mpw_inline_close(txq, &mpw);
1392         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1393                 mlx5_mpw_close(txq, &mpw);
1394         mlx5_tx_dbrec(txq, mpw.wqe);
1395         txq->elts_head = elts_head;
1396         return i;
1397 }
1398
1399 /**
1400  * Open an Enhanced MPW session.
1401  *
1402  * @param txq
1403  *   Pointer to TX queue structure.
1404  * @param mpw
1405  *   Pointer to MPW session structure.
1406  * @param length
1407  *   Packet length.
1408  */
1409 static inline void
1410 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1411 {
1412         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1413
1414         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1415         mpw->pkts_n = 0;
1416         mpw->total_len = sizeof(struct mlx5_wqe);
1417         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1418         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1419                                   (txq->wqe_ci << 8) |
1420                                   MLX5_OPCODE_ENHANCED_MPSW);
1421         mpw->wqe->ctrl[2] = 0;
1422         mpw->wqe->ctrl[3] = 0;
1423         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1424         if (unlikely(padding)) {
1425                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1426
1427                 /* Pad the first 2 DWORDs with zero-length inline header. */
1428                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1429                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1430                         htonl(MLX5_INLINE_SEG);
1431                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1432                 /* Start from the next WQEBB. */
1433                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1434         } else {
1435                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1436         }
1437 }
1438
1439 /**
1440  * Close an Enhanced MPW session.
1441  *
1442  * @param txq
1443  *   Pointer to TX queue structure.
1444  * @param mpw
1445  *   Pointer to MPW session structure.
1446  *
1447  * @return
1448  *   Number of consumed WQEs.
1449  */
1450 static inline uint16_t
1451 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1452 {
1453         uint16_t ret;
1454
1455         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1456          * count as 2.
1457          */
1458         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1459         mpw->state = MLX5_MPW_STATE_CLOSED;
1460         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1461         txq->wqe_ci += ret;
1462         return ret;
1463 }
1464
1465 /**
1466  * DPDK callback for TX with Enhanced MPW support.
1467  *
1468  * @param dpdk_txq
1469  *   Generic pointer to TX queue structure.
1470  * @param[in] pkts
1471  *   Packets to transmit.
1472  * @param pkts_n
1473  *   Number of packets in array.
1474  *
1475  * @return
1476  *   Number of packets successfully transmitted (<= pkts_n).
1477  */
1478 uint16_t
1479 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1480 {
1481         struct txq *txq = (struct txq *)dpdk_txq;
1482         uint16_t elts_head = txq->elts_head;
1483         const unsigned int elts_n = 1 << txq->elts_n;
1484         unsigned int i = 0;
1485         unsigned int j = 0;
1486         unsigned int max_elts;
1487         uint16_t max_wqe;
1488         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1489         unsigned int mpw_room = 0;
1490         unsigned int inl_pad = 0;
1491         uint32_t inl_hdr;
1492         struct mlx5_mpw mpw = {
1493                 .state = MLX5_MPW_STATE_CLOSED,
1494         };
1495
1496         if (unlikely(!pkts_n))
1497                 return 0;
1498         /* Start processing. */
1499         txq_complete(txq);
1500         max_elts = (elts_n - (elts_head - txq->elts_tail));
1501         if (max_elts > elts_n)
1502                 max_elts -= elts_n;
1503         /* A CQE slot must always be available. */
1504         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1505         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1506         if (unlikely(!max_wqe))
1507                 return 0;
1508         do {
1509                 struct rte_mbuf *buf = *(pkts++);
1510                 unsigned int elts_head_next;
1511                 uintptr_t addr;
1512                 uint64_t naddr;
1513                 unsigned int n;
1514                 unsigned int do_inline = 0; /* Whether inline is possible. */
1515                 uint32_t length;
1516                 unsigned int segs_n = buf->nb_segs;
1517                 uint32_t cs_flags = 0;
1518
1519                 /*
1520                  * Make sure there is enough room to store this packet and
1521                  * that one ring entry remains unused.
1522                  */
1523                 assert(segs_n);
1524                 if (max_elts - j < segs_n + 1)
1525                         break;
1526                 /* Do not bother with large packets MPW cannot handle. */
1527                 if (segs_n > MLX5_MPW_DSEG_MAX)
1528                         break;
1529                 /* Should we enable HW CKSUM offload. */
1530                 if (buf->ol_flags &
1531                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1532                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1533                 /* Retrieve packet information. */
1534                 length = PKT_LEN(buf);
1535                 /* Start new session if:
1536                  * - multi-segment packet
1537                  * - no space left even for a dseg
1538                  * - next packet can be inlined with a new WQE
1539                  * - cs_flag differs
1540                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1541                  * segmented packet.
1542                  */
1543                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1544                         if ((segs_n != 1) ||
1545                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1546                               mpw_room) ||
1547                             (length <= txq->inline_max_packet_sz &&
1548                              inl_pad + sizeof(inl_hdr) + length >
1549                               mpw_room) ||
1550                             (mpw.wqe->eseg.cs_flags != cs_flags))
1551                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1552                 }
1553                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1554                         if (unlikely(segs_n != 1)) {
1555                                 /* Fall back to legacy MPW.
1556                                  * A MPW session consumes 2 WQEs at most to
1557                                  * include MLX5_MPW_DSEG_MAX pointers.
1558                                  */
1559                                 if (unlikely(max_wqe < 2))
1560                                         break;
1561                                 mlx5_mpw_new(txq, &mpw, length);
1562                         } else {
1563                                 /* In Enhanced MPW, inline as much as the budget
1564                                  * is allowed. The remaining space is to be
1565                                  * filled with dsegs. If the title WQEBB isn't
1566                                  * padded, it will have 2 dsegs there.
1567                                  */
1568                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1569                                             (max_inline ? max_inline :
1570                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1571                                             MLX5_WQE_SIZE);
1572                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1573                                               mpw_room))
1574                                         break;
1575                                 /* Don't pad the title WQEBB to not waste WQ. */
1576                                 mlx5_empw_new(txq, &mpw, 0);
1577                                 mpw_room -= mpw.total_len;
1578                                 inl_pad = 0;
1579                                 do_inline =
1580                                         length <= txq->inline_max_packet_sz &&
1581                                         sizeof(inl_hdr) + length <= mpw_room &&
1582                                         !txq->mpw_hdr_dseg;
1583                         }
1584                         mpw.wqe->eseg.cs_flags = cs_flags;
1585                 } else {
1586                         /* Evaluate whether the next packet can be inlined.
1587                          * Inlininig is possible when:
1588                          * - length is less than configured value
1589                          * - length fits for remaining space
1590                          * - not required to fill the title WQEBB with dsegs
1591                          */
1592                         do_inline =
1593                                 length <= txq->inline_max_packet_sz &&
1594                                 inl_pad + sizeof(inl_hdr) + length <=
1595                                  mpw_room &&
1596                                 (!txq->mpw_hdr_dseg ||
1597                                  mpw.total_len >= MLX5_WQE_SIZE);
1598                 }
1599                 /* Multi-segment packets must be alone in their MPW. */
1600                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1601                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1602 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1603                         length = 0;
1604 #endif
1605                         do {
1606                                 volatile struct mlx5_wqe_data_seg *dseg;
1607
1608                                 elts_head_next =
1609                                         (elts_head + 1) & (elts_n - 1);
1610                                 assert(buf);
1611                                 (*txq->elts)[elts_head] = buf;
1612                                 dseg = mpw.data.dseg[mpw.pkts_n];
1613                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1614                                 *dseg = (struct mlx5_wqe_data_seg){
1615                                         .byte_count = htonl(DATA_LEN(buf)),
1616                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1617                                         .addr = htonll(addr),
1618                                 };
1619                                 elts_head = elts_head_next;
1620 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1621                                 length += DATA_LEN(buf);
1622 #endif
1623                                 buf = buf->next;
1624                                 ++j;
1625                                 ++mpw.pkts_n;
1626                         } while (--segs_n);
1627                         /* A multi-segmented packet takes one MPW session.
1628                          * TODO: Pack more multi-segmented packets if possible.
1629                          */
1630                         mlx5_mpw_close(txq, &mpw);
1631                         if (mpw.pkts_n < 3)
1632                                 max_wqe--;
1633                         else
1634                                 max_wqe -= 2;
1635                 } else if (do_inline) {
1636                         /* Inline packet into WQE. */
1637                         unsigned int max;
1638
1639                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1640                         assert(length == DATA_LEN(buf));
1641                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1642                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1643                         mpw.data.raw = (volatile void *)
1644                                 ((uintptr_t)mpw.data.raw + inl_pad);
1645                         max = tx_mlx5_wq_tailroom(txq,
1646                                         (void *)(uintptr_t)mpw.data.raw);
1647                         /* Copy inline header. */
1648                         mpw.data.raw = (volatile void *)
1649                                 mlx5_copy_to_wq(
1650                                           (void *)(uintptr_t)mpw.data.raw,
1651                                           &inl_hdr,
1652                                           sizeof(inl_hdr),
1653                                           (void *)(uintptr_t)txq->wqes,
1654                                           max);
1655                         max = tx_mlx5_wq_tailroom(txq,
1656                                         (void *)(uintptr_t)mpw.data.raw);
1657                         /* Copy packet data. */
1658                         mpw.data.raw = (volatile void *)
1659                                 mlx5_copy_to_wq(
1660                                           (void *)(uintptr_t)mpw.data.raw,
1661                                           (void *)addr,
1662                                           length,
1663                                           (void *)(uintptr_t)txq->wqes,
1664                                           max);
1665                         ++mpw.pkts_n;
1666                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1667                         /* No need to get completion as the entire packet is
1668                          * copied to WQ. Free the buf right away.
1669                          */
1670                         elts_head_next = elts_head;
1671                         rte_pktmbuf_free_seg(buf);
1672                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1673                         /* Add pad in the next packet if any. */
1674                         inl_pad = (((uintptr_t)mpw.data.raw +
1675                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1676                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1677                                   (uintptr_t)mpw.data.raw;
1678                 } else {
1679                         /* No inline. Load a dseg of packet pointer. */
1680                         volatile rte_v128u32_t *dseg;
1681
1682                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1683                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1684                         assert(length == DATA_LEN(buf));
1685                         if (!tx_mlx5_wq_tailroom(txq,
1686                                         (void *)((uintptr_t)mpw.data.raw
1687                                                 + inl_pad)))
1688                                 dseg = (volatile void *)txq->wqes;
1689                         else
1690                                 dseg = (volatile void *)
1691                                         ((uintptr_t)mpw.data.raw +
1692                                          inl_pad);
1693                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1694                         (*txq->elts)[elts_head] = buf;
1695                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1696                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1697                                 rte_prefetch2((void *)(addr +
1698                                                 n * RTE_CACHE_LINE_SIZE));
1699                         naddr = htonll(addr);
1700                         *dseg = (rte_v128u32_t) {
1701                                 htonl(length),
1702                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1703                                 naddr,
1704                                 naddr >> 32,
1705                         };
1706                         mpw.data.raw = (volatile void *)(dseg + 1);
1707                         mpw.total_len += (inl_pad + sizeof(*dseg));
1708                         ++j;
1709                         ++mpw.pkts_n;
1710                         mpw_room -= (inl_pad + sizeof(*dseg));
1711                         inl_pad = 0;
1712                 }
1713                 elts_head = elts_head_next;
1714 #ifdef MLX5_PMD_SOFT_COUNTERS
1715                 /* Increment sent bytes counter. */
1716                 txq->stats.obytes += length;
1717 #endif
1718                 ++i;
1719         } while (i < pkts_n);
1720         /* Take a shortcut if nothing must be sent. */
1721         if (unlikely(i == 0))
1722                 return 0;
1723         /* Check whether completion threshold has been reached. */
1724         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1725                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1726                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1727                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1728
1729                 /* Request completion on last WQE. */
1730                 wqe->ctrl[2] = htonl(8);
1731                 /* Save elts_head in unused "immediate" field of WQE. */
1732                 wqe->ctrl[3] = elts_head;
1733                 txq->elts_comp = 0;
1734                 txq->mpw_comp = txq->wqe_ci;
1735                 txq->cq_pi++;
1736         } else {
1737                 txq->elts_comp += j;
1738         }
1739 #ifdef MLX5_PMD_SOFT_COUNTERS
1740         /* Increment sent packets counter. */
1741         txq->stats.opackets += i;
1742 #endif
1743         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1744                 mlx5_empw_close(txq, &mpw);
1745         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1746                 mlx5_mpw_close(txq, &mpw);
1747         /* Ring QP doorbell. */
1748         mlx5_tx_dbrec(txq, mpw.wqe);
1749         txq->elts_head = elts_head;
1750         return i;
1751 }
1752
1753 /**
1754  * Translate RX completion flags to packet type.
1755  *
1756  * @param[in] cqe
1757  *   Pointer to CQE.
1758  *
1759  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1760  *
1761  * @return
1762  *   Packet type for struct rte_mbuf.
1763  */
1764 static inline uint32_t
1765 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1766 {
1767         uint32_t pkt_type;
1768         uint16_t flags = ntohs(cqe->hdr_type_etc);
1769
1770         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1771                 pkt_type =
1772                         TRANSPOSE(flags,
1773                                   MLX5_CQE_RX_IPV4_PACKET,
1774                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1775                         TRANSPOSE(flags,
1776                                   MLX5_CQE_RX_IPV6_PACKET,
1777                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1778                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1779                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1780                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1781         } else {
1782                 pkt_type =
1783                         TRANSPOSE(flags,
1784                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1785                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1786                         TRANSPOSE(flags,
1787                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1788                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1789         }
1790         return pkt_type;
1791 }
1792
1793 /**
1794  * Get size of the next packet for a given CQE. For compressed CQEs, the
1795  * consumer index is updated only once all packets of the current one have
1796  * been processed.
1797  *
1798  * @param rxq
1799  *   Pointer to RX queue.
1800  * @param cqe
1801  *   CQE to process.
1802  * @param[out] rss_hash
1803  *   Packet RSS Hash result.
1804  *
1805  * @return
1806  *   Packet size in bytes (0 if there is none), -1 in case of completion
1807  *   with error.
1808  */
1809 static inline int
1810 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1811                  uint16_t cqe_cnt, uint32_t *rss_hash)
1812 {
1813         struct rxq_zip *zip = &rxq->zip;
1814         uint16_t cqe_n = cqe_cnt + 1;
1815         int len = 0;
1816         uint16_t idx, end;
1817
1818         /* Process compressed data in the CQE and mini arrays. */
1819         if (zip->ai) {
1820                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1821                         (volatile struct mlx5_mini_cqe8 (*)[8])
1822                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1823
1824                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1825                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1826                 if ((++zip->ai & 7) == 0) {
1827                         /* Invalidate consumed CQEs */
1828                         idx = zip->ca;
1829                         end = zip->na;
1830                         while (idx != end) {
1831                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1832                                         MLX5_CQE_INVALIDATE;
1833                                 ++idx;
1834                         }
1835                         /*
1836                          * Increment consumer index to skip the number of
1837                          * CQEs consumed. Hardware leaves holes in the CQ
1838                          * ring for software use.
1839                          */
1840                         zip->ca = zip->na;
1841                         zip->na += 8;
1842                 }
1843                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1844                         /* Invalidate the rest */
1845                         idx = zip->ca;
1846                         end = zip->cq_ci;
1847
1848                         while (idx != end) {
1849                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1850                                         MLX5_CQE_INVALIDATE;
1851                                 ++idx;
1852                         }
1853                         rxq->cq_ci = zip->cq_ci;
1854                         zip->ai = 0;
1855                 }
1856         /* No compressed data, get next CQE and verify if it is compressed. */
1857         } else {
1858                 int ret;
1859                 int8_t op_own;
1860
1861                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1862                 if (unlikely(ret == 1))
1863                         return 0;
1864                 ++rxq->cq_ci;
1865                 op_own = cqe->op_own;
1866                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1867                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1868                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1869                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1870                                                           cqe_cnt]);
1871
1872                         /* Fix endianness. */
1873                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1874                         /*
1875                          * Current mini array position is the one returned by
1876                          * check_cqe64().
1877                          *
1878                          * If completion comprises several mini arrays, as a
1879                          * special case the second one is located 7 CQEs after
1880                          * the initial CQE instead of 8 for subsequent ones.
1881                          */
1882                         zip->ca = rxq->cq_ci;
1883                         zip->na = zip->ca + 7;
1884                         /* Compute the next non compressed CQE. */
1885                         --rxq->cq_ci;
1886                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1887                         /* Get packet size to return. */
1888                         len = ntohl((*mc)[0].byte_cnt);
1889                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1890                         zip->ai = 1;
1891                         /* Prefetch all the entries to be invalidated */
1892                         idx = zip->ca;
1893                         end = zip->cq_ci;
1894                         while (idx != end) {
1895                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1896                                 ++idx;
1897                         }
1898                 } else {
1899                         len = ntohl(cqe->byte_cnt);
1900                         *rss_hash = ntohl(cqe->rx_hash_res);
1901                 }
1902                 /* Error while receiving packet. */
1903                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1904                         return -1;
1905         }
1906         return len;
1907 }
1908
1909 /**
1910  * Translate RX completion flags to offload flags.
1911  *
1912  * @param[in] rxq
1913  *   Pointer to RX queue structure.
1914  * @param[in] cqe
1915  *   Pointer to CQE.
1916  *
1917  * @return
1918  *   Offload flags (ol_flags) for struct rte_mbuf.
1919  */
1920 static inline uint32_t
1921 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1922 {
1923         uint32_t ol_flags = 0;
1924         uint16_t flags = ntohs(cqe->hdr_type_etc);
1925
1926         ol_flags =
1927                 TRANSPOSE(flags,
1928                           MLX5_CQE_RX_L3_HDR_VALID,
1929                           PKT_RX_IP_CKSUM_GOOD) |
1930                 TRANSPOSE(flags,
1931                           MLX5_CQE_RX_L4_HDR_VALID,
1932                           PKT_RX_L4_CKSUM_GOOD);
1933         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1934                 ol_flags |=
1935                         TRANSPOSE(flags,
1936                                   MLX5_CQE_RX_L3_HDR_VALID,
1937                                   PKT_RX_IP_CKSUM_GOOD) |
1938                         TRANSPOSE(flags,
1939                                   MLX5_CQE_RX_L4_HDR_VALID,
1940                                   PKT_RX_L4_CKSUM_GOOD);
1941         return ol_flags;
1942 }
1943
1944 /**
1945  * DPDK callback for RX.
1946  *
1947  * @param dpdk_rxq
1948  *   Generic pointer to RX queue structure.
1949  * @param[out] pkts
1950  *   Array to store received packets.
1951  * @param pkts_n
1952  *   Maximum number of packets in array.
1953  *
1954  * @return
1955  *   Number of packets successfully received (<= pkts_n).
1956  */
1957 uint16_t
1958 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1959 {
1960         struct rxq *rxq = dpdk_rxq;
1961         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1962         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1963         const unsigned int sges_n = rxq->sges_n;
1964         struct rte_mbuf *pkt = NULL;
1965         struct rte_mbuf *seg = NULL;
1966         volatile struct mlx5_cqe *cqe =
1967                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1968         unsigned int i = 0;
1969         unsigned int rq_ci = rxq->rq_ci << sges_n;
1970         int len = 0; /* keep its value across iterations. */
1971
1972         while (pkts_n) {
1973                 unsigned int idx = rq_ci & wqe_cnt;
1974                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1975                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1976                 uint32_t rss_hash_res = 0;
1977
1978                 if (pkt)
1979                         NEXT(seg) = rep;
1980                 seg = rep;
1981                 rte_prefetch0(seg);
1982                 rte_prefetch0(cqe);
1983                 rte_prefetch0(wqe);
1984                 rep = rte_mbuf_raw_alloc(rxq->mp);
1985                 if (unlikely(rep == NULL)) {
1986                         ++rxq->stats.rx_nombuf;
1987                         if (!pkt) {
1988                                 /*
1989                                  * no buffers before we even started,
1990                                  * bail out silently.
1991                                  */
1992                                 break;
1993                         }
1994                         while (pkt != seg) {
1995                                 assert(pkt != (*rxq->elts)[idx]);
1996                                 rep = NEXT(pkt);
1997                                 NEXT(pkt) = NULL;
1998                                 NB_SEGS(pkt) = 1;
1999                                 rte_mbuf_raw_free(pkt);
2000                                 pkt = rep;
2001                         }
2002                         break;
2003                 }
2004                 if (!pkt) {
2005                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2006                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2007                                                &rss_hash_res);
2008                         if (!len) {
2009                                 rte_mbuf_raw_free(rep);
2010                                 break;
2011                         }
2012                         if (unlikely(len == -1)) {
2013                                 /* RX error, packet is likely too large. */
2014                                 rte_mbuf_raw_free(rep);
2015                                 ++rxq->stats.idropped;
2016                                 goto skip;
2017                         }
2018                         pkt = seg;
2019                         assert(len >= (rxq->crc_present << 2));
2020                         /* Update packet information. */
2021                         pkt->packet_type = 0;
2022                         pkt->ol_flags = 0;
2023                         if (rss_hash_res && rxq->rss_hash) {
2024                                 pkt->hash.rss = rss_hash_res;
2025                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2026                         }
2027                         if (rxq->mark &&
2028                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2029                                 pkt->ol_flags |= PKT_RX_FDIR;
2030                                 if (cqe->sop_drop_qpn !=
2031                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2032                                         uint32_t mark = cqe->sop_drop_qpn;
2033
2034                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2035                                         pkt->hash.fdir.hi =
2036                                                 mlx5_flow_mark_get(mark);
2037                                 }
2038                         }
2039                         if (rxq->csum | rxq->csum_l2tun) {
2040                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2041                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2042                         }
2043                         if (rxq->vlan_strip &&
2044                             (cqe->hdr_type_etc &
2045                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2046                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2047                                         PKT_RX_VLAN_STRIPPED;
2048                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2049                         }
2050                         if (rxq->crc_present)
2051                                 len -= ETHER_CRC_LEN;
2052                         PKT_LEN(pkt) = len;
2053                 }
2054                 DATA_LEN(rep) = DATA_LEN(seg);
2055                 PKT_LEN(rep) = PKT_LEN(seg);
2056                 SET_DATA_OFF(rep, DATA_OFF(seg));
2057                 NB_SEGS(rep) = NB_SEGS(seg);
2058                 PORT(rep) = PORT(seg);
2059                 NEXT(rep) = NULL;
2060                 (*rxq->elts)[idx] = rep;
2061                 /*
2062                  * Fill NIC descriptor with the new buffer.  The lkey and size
2063                  * of the buffers are already known, only the buffer address
2064                  * changes.
2065                  */
2066                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2067                 if (len > DATA_LEN(seg)) {
2068                         len -= DATA_LEN(seg);
2069                         ++NB_SEGS(pkt);
2070                         ++rq_ci;
2071                         continue;
2072                 }
2073                 DATA_LEN(seg) = len;
2074 #ifdef MLX5_PMD_SOFT_COUNTERS
2075                 /* Increment bytes counter. */
2076                 rxq->stats.ibytes += PKT_LEN(pkt);
2077 #endif
2078                 /* Return packet. */
2079                 *(pkts++) = pkt;
2080                 pkt = NULL;
2081                 --pkts_n;
2082                 ++i;
2083 skip:
2084                 /* Align consumer index to the next stride. */
2085                 rq_ci >>= sges_n;
2086                 ++rq_ci;
2087                 rq_ci <<= sges_n;
2088         }
2089         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2090                 return 0;
2091         /* Update the consumer index. */
2092         rxq->rq_ci = rq_ci >> sges_n;
2093         rte_wmb();
2094         *rxq->cq_db = htonl(rxq->cq_ci);
2095         rte_wmb();
2096         *rxq->rq_db = htonl(rxq->rq_ci);
2097 #ifdef MLX5_PMD_SOFT_COUNTERS
2098         /* Increment packets counter. */
2099         rxq->stats.ipackets += i;
2100 #endif
2101         return i;
2102 }
2103
2104 /**
2105  * Dummy DPDK callback for TX.
2106  *
2107  * This function is used to temporarily replace the real callback during
2108  * unsafe control operations on the queue, or in case of error.
2109  *
2110  * @param dpdk_txq
2111  *   Generic pointer to TX queue structure.
2112  * @param[in] pkts
2113  *   Packets to transmit.
2114  * @param pkts_n
2115  *   Number of packets in array.
2116  *
2117  * @return
2118  *   Number of packets successfully transmitted (<= pkts_n).
2119  */
2120 uint16_t
2121 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2122 {
2123         (void)dpdk_txq;
2124         (void)pkts;
2125         (void)pkts_n;
2126         return 0;
2127 }
2128
2129 /**
2130  * Dummy DPDK callback for RX.
2131  *
2132  * This function is used to temporarily replace the real callback during
2133  * unsafe control operations on the queue, or in case of error.
2134  *
2135  * @param dpdk_rxq
2136  *   Generic pointer to RX queue structure.
2137  * @param[out] pkts
2138  *   Array to store received packets.
2139  * @param pkts_n
2140  *   Maximum number of packets in array.
2141  *
2142  * @return
2143  *   Number of packets successfully received (<= pkts_n).
2144  */
2145 uint16_t
2146 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2147 {
2148         (void)dpdk_rxq;
2149         (void)pkts;
2150         (void)pkts_n;
2151         return 0;
2152 }
2153
2154 /**
2155  * DPDK callback for rx queue interrupt enable.
2156  *
2157  * @param dev
2158  *   Pointer to Ethernet device structure.
2159  * @param rx_queue_id
2160  *   RX queue number
2161  *
2162  * @return
2163  *   0 on success, negative on failure.
2164  */
2165 int
2166 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2167 {
2168 #ifdef HAVE_UPDATE_CQ_CI
2169         struct priv *priv = mlx5_get_priv(dev);
2170         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2171         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2172         struct ibv_cq *cq = rxq_ctrl->cq;
2173         uint16_t ci = rxq->cq_ci;
2174         int ret = 0;
2175
2176         ibv_mlx5_exp_update_cq_ci(cq, ci);
2177         ret = ibv_req_notify_cq(cq, 0);
2178 #else
2179         int ret = -1;
2180         (void)dev;
2181         (void)rx_queue_id;
2182 #endif
2183         if (ret)
2184                 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2185         return ret;
2186 }
2187
2188 /**
2189  * DPDK callback for rx queue interrupt disable.
2190  *
2191  * @param dev
2192  *   Pointer to Ethernet device structure.
2193  * @param rx_queue_id
2194  *   RX queue number
2195  *
2196  * @return
2197  *   0 on success, negative on failure.
2198  */
2199 int
2200 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2201 {
2202 #ifdef HAVE_UPDATE_CQ_CI
2203         struct priv *priv = mlx5_get_priv(dev);
2204         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2205         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2206         struct ibv_cq *cq = rxq_ctrl->cq;
2207         struct ibv_cq *ev_cq;
2208         void *ev_ctx;
2209         int ret = 0;
2210
2211         ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2212         if (ret || ev_cq != cq)
2213                 ret = -1;
2214         else
2215                 ibv_ack_cq_events(cq, 1);
2216 #else
2217         int ret = -1;
2218         (void)dev;
2219         (void)rx_queue_id;
2220 #endif
2221         if (ret)
2222                 WARN("unable to disable interrupt on rx queue %d",
2223                      rx_queue_id);
2224         return ret;
2225 }