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34 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
35 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
44 #include <rte_mempool.h>
45 #include <rte_prefetch.h>
48 #include "mlx5_utils.h"
49 #include "mlx5_rxtx.h"
50 #include "mlx5_rxtx_vec.h"
51 #include "mlx5_autoconf.h"
52 #include "mlx5_defs.h"
55 #pragma GCC diagnostic ignored "-Wcast-qual"
58 * Fill in buffer descriptors in a multi-packet send descriptor.
61 * Pointer to TX queue structure.
63 * Pointer to buffer descriptor to be written.
65 * Pointer to array of packets to be sent.
67 * Number of packets to be filled.
70 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
71 struct rte_mbuf **pkts, unsigned int n)
75 const uint8x16_t dseg_shuf_m = {
76 3, 2, 1, 0, /* length, bswap32 */
77 4, 5, 6, 7, /* lkey */
78 15, 14, 13, 12, /* addr, bswap64 */
81 #ifdef MLX5_PMD_SOFT_COUNTERS
85 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
87 struct rte_mbuf *pkt = pkts[pos];
89 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
90 desc = vreinterpretq_u8_u32((uint32x4_t) {
92 mlx5_tx_mb2mr(txq, pkt),
95 desc = vqtbl1q_u8(desc, dseg_shuf_m);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
98 tx_byte += DATA_LEN(pkt);
101 #ifdef MLX5_PMD_SOFT_COUNTERS
102 txq->stats.obytes += tx_byte;
107 * Send multi-segmented packets until it encounters a single segment packet in
111 * Pointer to TX queue structure.
113 * Pointer to array of packets to be sent.
115 * Number of packets to be sent.
118 * Number of packets successfully transmitted (<= pkts_n).
121 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
124 uint16_t elts_head = txq->elts_head;
125 const uint16_t elts_n = 1 << txq->elts_n;
126 const uint16_t elts_m = elts_n - 1;
127 const uint16_t wq_n = 1 << txq->wqe_n;
128 const uint16_t wq_mask = wq_n - 1;
129 const unsigned int nb_dword_per_wqebb =
130 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
131 const unsigned int nb_dword_in_hdr =
132 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
134 volatile struct mlx5_wqe *wqe = NULL;
136 assert(elts_n > pkts_n);
137 mlx5_tx_complete(txq);
138 if (unlikely(!pkts_n))
140 for (n = 0; n < pkts_n; ++n) {
141 struct rte_mbuf *buf = pkts[n];
142 unsigned int segs_n = buf->nb_segs;
143 unsigned int ds = nb_dword_in_hdr;
144 unsigned int len = PKT_LEN(buf);
145 uint16_t wqe_ci = txq->wqe_ci;
146 const uint8x16_t ctrl_shuf_m = {
147 3, 2, 1, 0, /* bswap32 */
148 7, 6, 5, 4, /* bswap32 */
149 11, 10, 9, 8, /* bswap32 */
160 max_elts = elts_n - (elts_head - txq->elts_tail);
161 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
163 * A MPW session consumes 2 WQEs at most to
164 * include MLX5_MPW_DSEG_MAX pointers.
167 max_elts < segs_n || max_wqe < 2)
169 wqe = &((volatile struct mlx5_wqe64 *)
170 txq->wqes)[wqe_ci & wq_mask].hdr;
171 cs_flags = txq_ol_cksum_to_cs(txq, buf);
172 /* Title WQEBB pointer. */
173 t_wqe = (uint8x16_t *)wqe;
174 dseg = (uint8_t *)(wqe + 1);
176 if (!(ds++ % nb_dword_per_wqebb)) {
178 &((volatile struct mlx5_wqe64 *)
179 txq->wqes)[++wqe_ci & wq_mask];
181 txq_wr_dseg_v(txq, dseg, &buf, 1);
182 dseg += MLX5_WQE_DWORD_SIZE;
183 (*txq->elts)[elts_head++ & elts_m] = buf;
187 /* Fill CTRL in the header. */
188 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
189 MLX5_OPC_MOD_MPW << 24 |
190 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
191 txq->qp_num_8s | ds, 0, 0});
192 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
193 vst1q_u8((void *)t_wqe, ctrl);
194 /* Fill ESEG in the header. */
195 vst1q_u16((void *)(t_wqe + 1),
196 ((uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len),
198 txq->wqe_ci = wqe_ci;
202 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
203 txq->elts_head = elts_head;
204 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
205 wqe->ctrl[2] = rte_cpu_to_be_32(8);
206 wqe->ctrl[3] = txq->elts_head;
210 #ifdef MLX5_PMD_SOFT_COUNTERS
211 txq->stats.opackets += n;
213 mlx5_tx_dbrec(txq, wqe);
218 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
219 * it returns to make it processed by txq_scatter_v(). All the packets in
220 * the pkts list should be single segment packets having same offload flags.
221 * This must be checked by txq_check_multiseg() and txq_calc_offload().
224 * Pointer to TX queue structure.
226 * Pointer to array of packets to be sent.
228 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
230 * Checksum offload flags to be written in the descriptor.
233 * Number of packets successfully transmitted (<= pkts_n).
235 static inline uint16_t
236 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
239 struct rte_mbuf **elts;
240 uint16_t elts_head = txq->elts_head;
241 const uint16_t elts_n = 1 << txq->elts_n;
242 const uint16_t elts_m = elts_n - 1;
243 const unsigned int nb_dword_per_wqebb =
244 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
245 const unsigned int nb_dword_in_hdr =
246 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
251 uint32_t comp_req = 0;
252 const uint16_t wq_n = 1 << txq->wqe_n;
253 const uint16_t wq_mask = wq_n - 1;
254 uint16_t wq_idx = txq->wqe_ci & wq_mask;
255 volatile struct mlx5_wqe64 *wq =
256 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
257 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
258 const uint8x16_t ctrl_shuf_m = {
259 3, 2, 1, 0, /* bswap32 */
260 7, 6, 5, 4, /* bswap32 */
261 11, 10, 9, 8, /* bswap32 */
268 /* Make sure all packets can fit into a single WQE. */
269 assert(elts_n > pkts_n);
270 mlx5_tx_complete(txq);
271 max_elts = (elts_n - (elts_head - txq->elts_tail));
272 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
273 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
274 if (unlikely(!pkts_n))
276 elts = &(*txq->elts)[elts_head & elts_m];
277 /* Loop for available tailroom first. */
278 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
279 for (pos = 0; pos < (n & -2); pos += 2)
280 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
282 elts[pos] = pkts[pos];
283 /* Check if it crosses the end of the queue. */
284 if (unlikely(n < pkts_n)) {
285 elts = &(*txq->elts)[0];
286 for (pos = 0; pos < pkts_n - n; ++pos)
287 elts[pos] = pkts[n + pos];
289 txq->elts_head += pkts_n;
290 /* Save title WQEBB pointer. */
291 t_wqe = (uint8x16_t *)wqe;
292 dseg = (uint8_t *)(wqe + 1);
293 /* Calculate the number of entries to the end. */
295 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
298 txq_wr_dseg_v(txq, dseg, pkts, n);
299 /* Check if it crosses the end of the queue. */
301 dseg = (uint8_t *)txq->wqes;
302 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
304 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
305 txq->elts_comp += pkts_n;
307 /* Request a completion. */
312 /* Fill CTRL in the header. */
313 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
314 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
315 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
316 txq->qp_num_8s | (pkts_n + 2),
319 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
320 vst1q_u8((void *)t_wqe, ctrl);
321 /* Fill ESEG in the header. */
322 vst1q_u8((void *)(t_wqe + 1),
323 ((uint8x16_t) { 0, 0, 0, 0,
327 #ifdef MLX5_PMD_SOFT_COUNTERS
328 txq->stats.opackets += pkts_n;
330 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
332 /* Ring QP doorbell. */
333 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
338 * Store free buffers to RX SW ring.
341 * Pointer to RX queue structure.
343 * Pointer to array of packets to be stored.
345 * Number of packets to be stored.
348 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
350 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
351 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
355 for (pos = 0; pos < p; pos += 2) {
358 mbp = vld1q_u64((void *)&elts[pos]);
359 vst1q_u64((void *)&pkts[pos], mbp);
362 pkts[pos] = elts[pos];
366 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
367 * extracted from the title completion descriptor.
370 * Pointer to RX queue structure.
372 * Pointer to completion array having a compressed completion at first.
374 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
375 * the title completion descriptor to be copied to the rest of mbufs.
378 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
379 struct rte_mbuf **elts)
381 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
382 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
385 unsigned int inv = 0;
386 /* Mask to shuffle from extracted mini CQE to mbuf. */
387 const uint8x16_t mcqe_shuf_m1 = {
388 -1, -1, -1, -1, /* skip packet_type */
389 7, 6, -1, -1, /* pkt_len, bswap16 */
390 7, 6, /* data_len, bswap16 */
391 -1, -1, /* skip vlan_tci */
392 3, 2, 1, 0 /* hash.rss, bswap32 */
394 const uint8x16_t mcqe_shuf_m2 = {
395 -1, -1, -1, -1, /* skip packet_type */
396 15, 14, -1, -1, /* pkt_len, bswap16 */
397 15, 14, /* data_len, bswap16 */
398 -1, -1, /* skip vlan_tci */
399 11, 10, 9, 8 /* hash.rss, bswap32 */
401 /* Restore the compressed count. Must be 16 bits. */
402 const uint16_t mcqe_n = t_pkt->data_len +
403 (rxq->crc_present * ETHER_CRC_LEN);
404 const uint64x2_t rearm =
405 vld1q_u64((void *)&t_pkt->rearm_data);
406 const uint32x4_t rxdf_mask = {
407 0xffffffff, /* packet_type */
408 0, /* skip pkt_len */
409 0xffff0000, /* vlan_tci, skip data_len */
410 0, /* skip hash.rss */
412 const uint8x16_t rxdf =
413 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
414 vreinterpretq_u8_u32(rxdf_mask));
415 const uint16x8_t crc_adj = {
417 rxq->crc_present * ETHER_CRC_LEN, 0,
418 rxq->crc_present * ETHER_CRC_LEN, 0,
421 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
422 #ifdef MLX5_PMD_SOFT_COUNTERS
423 uint32_t rcvd_byte = 0;
425 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
426 const uint8x8_t len_shuf_m = {
428 15, 14, /* 2nd mCQE */
429 23, 22, /* 3rd mCQE */
430 31, 30 /* 4th mCQE */
434 * A. load mCQEs into a 128bit register.
435 * B. store rearm data to mbuf.
436 * C. combine data from mCQEs with rx_descriptor_fields1.
437 * D. store rx_descriptor_fields1.
438 * E. store flow tag (rte_flow mark).
440 for (pos = 0; pos < mcqe_n; ) {
441 uint8_t *p = (void *)&mcq[pos % 8];
442 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
443 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
444 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
445 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
447 #ifdef MLX5_PMD_SOFT_COUNTERS
448 uint16x4_t invalid_mask =
449 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
450 -1UL << ((mcqe_n - pos) *
451 sizeof(uint16_t) * 8) : 0);
454 if (!(pos & 0x7) && pos + 8 < mcqe_n)
455 rte_prefetch0((void *)(cq + pos + 8));
457 /* A.1 load mCQEs into a 128bit register. */
458 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
459 /* B.1 store rearm data to mbuf. */
460 "st1 {%[rearm].2d}, [%[e0]] \n\t"
461 "add %[e0], %[e0], #16 \n\t"
462 "st1 {%[rearm].2d}, [%[e1]] \n\t"
463 "add %[e1], %[e1], #16 \n\t"
464 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
465 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
466 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
467 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
468 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
469 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
470 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
471 /* D.1 store rx_descriptor_fields1. */
472 "st1 {v18.2d}, [%[e0]] \n\t"
473 "st1 {v19.2d}, [%[e1]] \n\t"
474 /* B.1 store rearm data to mbuf. */
475 "st1 {%[rearm].2d}, [%[e2]] \n\t"
476 "add %[e2], %[e2], #16 \n\t"
477 "st1 {%[rearm].2d}, [%[e3]] \n\t"
478 "add %[e3], %[e3], #16 \n\t"
479 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
480 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
481 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
482 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
483 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
484 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
485 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
486 /* D.1 store rx_descriptor_fields1. */
487 "st1 {v18.2d}, [%[e2]] \n\t"
488 "st1 {v19.2d}, [%[e3]] \n\t"
489 #ifdef MLX5_PMD_SOFT_COUNTERS
490 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
492 :[byte_cnt]"=&w"(byte_cnt)
496 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
497 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
498 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
499 [crc_adj]"w"(crc_adj),
500 [len_shuf_m]"w"(len_shuf_m)
501 :"memory", "v16", "v17", "v18", "v19");
502 #ifdef MLX5_PMD_SOFT_COUNTERS
503 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
504 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
507 /* E.1 store flow tag (rte_flow mark). */
508 elts[pos]->hash.fdir.hi = flow_tag;
509 elts[pos + 1]->hash.fdir.hi = flow_tag;
510 elts[pos + 2]->hash.fdir.hi = flow_tag;
511 elts[pos + 3]->hash.fdir.hi = flow_tag;
513 pos += MLX5_VPMD_DESCS_PER_LOOP;
514 /* Move to next CQE and invalidate consumed CQEs. */
515 if (!(pos & 0x7) && pos < mcqe_n) {
516 mcq = (void *)&(cq + pos)->pkt_info;
517 for (i = 0; i < 8; ++i)
518 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
521 /* Invalidate the rest of CQEs. */
522 for (; inv < mcqe_n; ++inv)
523 cq[inv].op_own = MLX5_CQE_INVALIDATE;
524 #ifdef MLX5_PMD_SOFT_COUNTERS
525 rxq->stats.ipackets += mcqe_n;
526 rxq->stats.ibytes += rcvd_byte;
528 rxq->cq_ci += mcqe_n;
532 * Calculate packet type and offload flag for mbuf and store it.
535 * Pointer to RX queue structure.
537 * Array of four 4bytes packet type info extracted from the original
538 * completion descriptor.
540 * Array of four 4bytes flow ID extracted from the original completion
543 * Opcode vector having responder error status. Each field is 4B.
545 * Pointer to array of packets to be filled.
548 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
549 uint32x4_t ptype_info, uint32x4_t flow_tag,
550 uint16x4_t op_err, struct rte_mbuf **pkts)
553 uint32x4_t pinfo, cv_flags;
554 uint32x4_t ol_flags =
555 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
556 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
557 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
558 const uint8x16_t cv_flag_sel = {
560 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
561 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
563 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
565 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
566 0, 0, 0, 0, 0, 0, 0, 0, 0
568 const uint32x4_t cv_mask =
569 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
570 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
571 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
572 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
573 uint64x2_t rearm0, rearm1, rearm2, rearm3;
576 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
577 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
578 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
579 uint32x4_t invalid_mask;
581 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
582 invalid_mask = vceqzq_u32(flow_tag);
583 ol_flags = vorrq_u32(ol_flags,
584 vbicq_u32(fdir_flags, invalid_mask));
585 /* Mask out invalid entries. */
586 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
587 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
588 ol_flags = vorrq_u32(ol_flags,
589 vbicq_u32(fdir_id_flags,
590 vceqq_u32(flow_tag, ft_def)));
593 * ptype_info has the following:
597 * bit[11:10] = l3_hdr_type
598 * bit[14:12] = l4_hdr_type
601 * bit[17] = outer_l3_type
603 ptype = vshrn_n_u32(ptype_info, 10);
604 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
605 ptype = vorr_u16(ptype, op_err);
606 pkts[0]->packet_type =
607 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 6)];
608 pkts[1]->packet_type =
609 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 4)];
610 pkts[2]->packet_type =
611 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 2)];
612 pkts[3]->packet_type =
613 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 0)];
614 /* Fill flags for checksum and VLAN. */
615 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
616 pinfo = vreinterpretq_u32_u8(
617 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
618 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
619 cv_flags = vshlq_n_u32(pinfo, 9);
620 cv_flags = vorrq_u32(pinfo, cv_flags);
621 /* Move back flags to start from byte[0]. */
622 cv_flags = vshrq_n_u32(cv_flags, 8);
623 /* Mask out garbage bits. */
624 cv_flags = vandq_u32(cv_flags, cv_mask);
625 /* Merge to ol_flags. */
626 ol_flags = vorrq_u32(ol_flags, cv_flags);
627 /* Merge mbuf_init and ol_flags, and store. */
628 rearm0 = vcombine_u64(mbuf_init,
629 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
631 rearm1 = vcombine_u64(mbuf_init,
632 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
633 ol_flags)), r32_mask));
634 rearm2 = vcombine_u64(mbuf_init,
635 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
637 rearm3 = vcombine_u64(mbuf_init,
638 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
639 ol_flags)), r32_mask));
640 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
641 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
642 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
643 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
647 * Receive burst of packets. An errored completion also consumes a mbuf, but the
648 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
649 * before returning to application.
652 * Pointer to RX queue structure.
654 * Array to store received packets.
656 * Maximum number of packets in array.
658 * Pointer to a flag. Set non-zero value if pkts array has at least one error
662 * Number of packets received including errors (<= pkts_n).
664 static inline uint16_t
665 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
668 const uint16_t q_n = 1 << rxq->cqe_n;
669 const uint16_t q_mask = q_n - 1;
670 volatile struct mlx5_cqe *cq;
671 struct rte_mbuf **elts;
675 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
676 uint16_t nocmp_n = 0;
677 uint16_t rcvd_pkt = 0;
678 unsigned int cq_idx = rxq->cq_ci & q_mask;
679 unsigned int elts_idx;
680 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
681 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
682 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
683 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
684 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
685 #ifdef MLX5_PMD_SOFT_COUNTERS
686 uint32_t rcvd_byte = 0;
688 /* Mask to generate 16B length vector. */
689 const uint8x8_t len_shuf_m = {
690 52, 53, /* 4th CQE */
691 36, 37, /* 3rd CQE */
692 20, 21, /* 2nd CQE */
695 /* Mask to extract 16B data from a 64B CQE. */
696 const uint8x16_t cqe_shuf_m = {
697 28, 29, /* hdr_type_etc */
700 47, 46, /* byte_cnt, bswap16 */
701 31, 30, /* vlan_info, bswap16 */
702 15, 14, 13, 12, /* rx_hash_res, bswap32 */
703 57, 58, 59, /* flow_tag */
706 /* Mask to generate 16B data for mbuf. */
707 const uint8x16_t mb_shuf_m = {
708 4, 5, -1, -1, /* pkt_len */
711 8, 9, 10, 11, /* hash.rss */
712 12, 13, 14, -1 /* hash.fdir.hi */
714 /* Mask to generate 16B owner vector. */
715 const uint8x8_t owner_shuf_m = {
716 63, -1, /* 4th CQE */
717 47, -1, /* 3rd CQE */
718 31, -1, /* 2nd CQE */
721 /* Mask to generate a vector having packet_type/ol_flags. */
722 const uint8x16_t ptype_shuf_m = {
723 48, 49, 50, -1, /* 4th CQE */
724 32, 33, 34, -1, /* 3rd CQE */
725 16, 17, 18, -1, /* 2nd CQE */
726 0, 1, 2, -1 /* 1st CQE */
728 /* Mask to generate a vector having flow tags. */
729 const uint8x16_t ftag_shuf_m = {
730 60, 61, 62, -1, /* 4th CQE */
731 44, 45, 46, -1, /* 3rd CQE */
732 28, 29, 30, -1, /* 2nd CQE */
733 12, 13, 14, -1 /* 1st CQE */
735 const uint16x8_t crc_adj = {
736 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0
738 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
740 assert(rxq->sges_n == 0);
741 assert(rxq->cqe_n == rxq->elts_n);
742 cq = &(*rxq->cqes)[cq_idx];
743 rte_prefetch_non_temporal(cq);
744 rte_prefetch_non_temporal(cq + 1);
745 rte_prefetch_non_temporal(cq + 2);
746 rte_prefetch_non_temporal(cq + 3);
747 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
750 * rq_ci >= cq_ci >= rq_pi
751 * Definition of indexes:
752 * rq_ci - cq_ci := # of buffers owned by HW (posted).
753 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
754 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
756 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
757 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
758 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
759 /* See if there're unreturned mbufs from compressed CQE. */
760 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
762 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
763 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
764 rxq->rq_pi += rcvd_pkt;
767 elts_idx = rxq->rq_pi & q_mask;
768 elts = &(*rxq->elts)[elts_idx];
769 /* Not to overflow pkts array. */
770 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
771 /* Not to cross queue end. */
772 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
775 /* At this point, there shouldn't be any remained packets. */
776 assert(rxq->rq_pi == rxq->cq_ci);
778 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
779 * there's no instruction to count trailing zeros. __builtin_clzl() is
782 * A. copy 4 mbuf pointers from elts ring to returing pkts.
783 * B. load 64B CQE and extract necessary fields
784 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
785 * following structure:
787 * uint16_t hdr_type_etc;
791 * uint16_t vlan_info;
792 * uint32_t rx_has_res;
793 * uint8_t flow_tag[3];
798 * E. find compressed CQE.
802 pos += MLX5_VPMD_DESCS_PER_LOOP) {
804 uint16x4_t opcode, owner_mask, invalid_mask;
805 uint16x4_t comp_mask;
808 uint32x4_t ptype_info, flow_tag;
809 register uint64x2_t c0, c1, c2, c3;
810 uint8_t *p0, *p1, *p2, *p3;
811 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
812 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
813 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
814 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
815 void *elts_p = (void *)&elts[pos];
816 void *pkts_p = (void *)&pkts[pos];
818 /* A.0 do not cross the end of CQ. */
819 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
820 -1UL >> ((pkts_n - pos) *
821 sizeof(uint16_t) * 8) : 0);
822 p0 = (void *)&cq[pos].pkt_info;
823 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
824 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
825 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
826 /* B.0 (CQE 3) load a block having op_own. */
827 c3 = vld1q_u64((uint64_t *)(p3 + 48));
828 /* B.0 (CQE 2) load a block having op_own. */
829 c2 = vld1q_u64((uint64_t *)(p2 + 48));
830 /* B.0 (CQE 1) load a block having op_own. */
831 c1 = vld1q_u64((uint64_t *)(p1 + 48));
832 /* B.0 (CQE 0) load a block having op_own. */
833 c0 = vld1q_u64((uint64_t *)(p0 + 48));
834 /* Synchronize for loading the rest of blocks. */
836 /* Prefetch next 4 CQEs. */
837 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
838 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
839 rte_prefetch_non_temporal(&cq[next]);
840 rte_prefetch_non_temporal(&cq[next + 1]);
841 rte_prefetch_non_temporal(&cq[next + 2]);
842 rte_prefetch_non_temporal(&cq[next + 3]);
845 /* B.1 (CQE 3) load the rest of blocks. */
846 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
847 /* B.2 (CQE 3) move the block having op_own. */
848 "mov v19.16b, %[c3].16b \n\t"
849 /* B.3 (CQE 3) extract 16B fields. */
850 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
851 /* B.1 (CQE 2) load the rest of blocks. */
852 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
853 /* B.4 (CQE 3) adjust CRC length. */
854 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
855 /* C.1 (CQE 3) generate final structure for mbuf. */
856 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
857 /* B.2 (CQE 2) move the block having op_own. */
858 "mov v19.16b, %[c2].16b \n\t"
859 /* B.3 (CQE 2) extract 16B fields. */
860 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
861 /* B.1 (CQE 1) load the rest of blocks. */
862 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
863 /* B.4 (CQE 2) adjust CRC length. */
864 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
865 /* C.1 (CQE 2) generate final structure for mbuf. */
866 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
867 /* B.2 (CQE 1) move the block having op_own. */
868 "mov v19.16b, %[c1].16b \n\t"
869 /* B.3 (CQE 1) extract 16B fields. */
870 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
871 /* B.1 (CQE 0) load the rest of blocks. */
872 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
873 /* B.4 (CQE 1) adjust CRC length. */
874 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
875 /* C.1 (CQE 1) generate final structure for mbuf. */
876 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
877 /* B.2 (CQE 0) move the block having op_own. */
878 "mov v19.16b, %[c0].16b \n\t"
879 /* A.1 load mbuf pointers. */
880 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
881 /* B.3 (CQE 0) extract 16B fields. */
882 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
883 /* B.4 (CQE 0) adjust CRC length. */
884 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
885 /* D.1 extract op_own byte. */
886 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
887 /* C.2 (CQE 3) adjust flow mark. */
888 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
889 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
890 "st1 {v15.2d}, [%[e3]] \n\t"
891 /* C.2 (CQE 2) adjust flow mark. */
892 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
893 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
894 "st1 {v14.2d}, [%[e2]] \n\t"
895 /* C.1 (CQE 0) generate final structure for mbuf. */
896 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
897 /* C.2 (CQE 1) adjust flow mark. */
898 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
899 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
900 "st1 {v13.2d}, [%[e1]] \n\t"
901 #ifdef MLX5_PMD_SOFT_COUNTERS
902 /* Extract byte_cnt. */
903 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
905 /* Extract ptype_info. */
906 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
907 /* Extract flow_tag. */
908 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
909 /* A.2 copy mbuf pointers. */
910 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
911 /* C.2 (CQE 0) adjust flow mark. */
912 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
913 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
914 "st1 {v12.2d}, [%[e0]] \n\t"
915 :[op_own]"=&w"(op_own),
916 [byte_cnt]"=&w"(byte_cnt),
917 [ptype_info]"=&w"(ptype_info),
918 [flow_tag]"=&w"(flow_tag)
919 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
920 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
921 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
924 [cqe_shuf_m]"w"(cqe_shuf_m),
925 [mb_shuf_m]"w"(mb_shuf_m),
926 [owner_shuf_m]"w"(owner_shuf_m),
927 [len_shuf_m]"w"(len_shuf_m),
928 [ptype_shuf_m]"w"(ptype_shuf_m),
929 [ftag_shuf_m]"w"(ftag_shuf_m),
930 [crc_adj]"w"(crc_adj),
931 [flow_mark_adj]"w"(flow_mark_adj)
933 "v12", "v13", "v14", "v15",
934 "v16", "v17", "v18", "v19",
935 "v20", "v21", "v22", "v23",
937 /* D.2 flip owner bit to mark CQEs from last round. */
938 owner_mask = vand_u16(op_own, owner_check);
939 owner_mask = vceq_u16(owner_mask, ownership);
940 /* D.3 get mask for invalidated CQEs. */
941 opcode = vand_u16(op_own, opcode_check);
942 invalid_mask = vceq_u16(opcode_check, opcode);
943 /* E.1 find compressed CQE format. */
944 comp_mask = vand_u16(op_own, format_check);
945 comp_mask = vceq_u16(comp_mask, format_check);
946 /* D.4 mask out beyond boundary. */
947 invalid_mask = vorr_u16(invalid_mask, mask);
948 /* D.5 merge invalid_mask with invalid owner. */
949 invalid_mask = vorr_u16(invalid_mask, owner_mask);
950 /* E.2 mask out invalid entries. */
951 comp_mask = vbic_u16(comp_mask, invalid_mask);
952 /* E.3 get the first compressed CQE. */
953 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
955 (sizeof(uint16_t) * 8);
956 /* D.6 mask out entries after the compressed CQE. */
957 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
958 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
960 invalid_mask = vorr_u16(invalid_mask, mask);
961 /* D.7 count non-compressed valid CQEs. */
962 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
963 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
965 /* D.2 get the final invalid mask. */
966 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
967 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
968 invalid_mask = vorr_u16(invalid_mask, mask);
969 /* D.3 check error in opcode. */
970 opcode = vceq_u16(resp_err_check, opcode);
971 opcode = vbic_u16(opcode, invalid_mask);
972 /* D.4 mark if any error is set */
973 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
974 /* C.4 fill in mbuf - rearm_data and packet_type. */
975 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
977 if (rxq->hw_timestamp) {
978 elts[pos]->timestamp =
980 container_of(p0, struct mlx5_cqe,
981 pkt_info)->timestamp);
982 elts[pos + 1]->timestamp =
984 container_of(p1, struct mlx5_cqe,
985 pkt_info)->timestamp);
986 elts[pos + 2]->timestamp =
988 container_of(p2, struct mlx5_cqe,
989 pkt_info)->timestamp);
990 elts[pos + 3]->timestamp =
992 container_of(p3, struct mlx5_cqe,
993 pkt_info)->timestamp);
995 #ifdef MLX5_PMD_SOFT_COUNTERS
996 /* Add up received bytes count. */
997 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
998 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
1001 * Break the loop unless more valid CQE is expected, or if
1002 * there's a compressed CQE.
1004 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1007 /* If no new CQE seen, return without updating cq_db. */
1008 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1010 /* Update the consumer indexes for non-compressed CQEs. */
1011 assert(nocmp_n <= pkts_n);
1012 rxq->cq_ci += nocmp_n;
1013 rxq->rq_pi += nocmp_n;
1014 rcvd_pkt += nocmp_n;
1015 #ifdef MLX5_PMD_SOFT_COUNTERS
1016 rxq->stats.ipackets += nocmp_n;
1017 rxq->stats.ibytes += rcvd_byte;
1019 /* Decompress the last CQE if compressed. */
1020 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1021 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1022 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1023 /* Return more packets if needed. */
1024 if (nocmp_n < pkts_n) {
1025 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1027 n = RTE_MIN(n, pkts_n - nocmp_n);
1028 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1033 rte_compiler_barrier();
1034 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1038 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */