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5 * Copyright 2017 Mellanox.
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34 #ifndef RTE_PMD_MLX5_RXTX_VEC_NEON_H_
35 #define RTE_PMD_MLX5_RXTX_VEC_NEON_H_
44 #include <rte_mempool.h>
45 #include <rte_prefetch.h>
48 #include "mlx5_utils.h"
49 #include "mlx5_rxtx.h"
50 #include "mlx5_rxtx_vec.h"
51 #include "mlx5_autoconf.h"
52 #include "mlx5_defs.h"
55 #pragma GCC diagnostic ignored "-Wcast-qual"
58 * Fill in buffer descriptors in a multi-packet send descriptor.
61 * Pointer to TX queue structure.
63 * Pointer to buffer descriptor to be written.
65 * Pointer to array of packets to be sent.
67 * Number of packets to be filled.
70 txq_wr_dseg_v(struct mlx5_txq_data *txq, uint8_t *dseg,
71 struct rte_mbuf **pkts, unsigned int n)
75 const uint8x16_t dseg_shuf_m = {
76 3, 2, 1, 0, /* length, bswap32 */
77 4, 5, 6, 7, /* lkey */
78 15, 14, 13, 12, /* addr, bswap64 */
81 #ifdef MLX5_PMD_SOFT_COUNTERS
85 for (pos = 0; pos < n; ++pos, dseg += MLX5_WQE_DWORD_SIZE) {
87 struct rte_mbuf *pkt = pkts[pos];
89 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
90 desc = vreinterpretq_u8_u32((uint32x4_t) {
92 mlx5_tx_mb2mr(txq, pkt),
95 desc = vqtbl1q_u8(desc, dseg_shuf_m);
97 #ifdef MLX5_PMD_SOFT_COUNTERS
98 tx_byte += DATA_LEN(pkt);
101 #ifdef MLX5_PMD_SOFT_COUNTERS
102 txq->stats.obytes += tx_byte;
107 * Send multi-segmented packets until it encounters a single segment packet in
111 * Pointer to TX queue structure.
113 * Pointer to array of packets to be sent.
115 * Number of packets to be sent.
118 * Number of packets successfully transmitted (<= pkts_n).
121 txq_scatter_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
124 uint16_t elts_head = txq->elts_head;
125 const uint16_t elts_n = 1 << txq->elts_n;
126 const uint16_t elts_m = elts_n - 1;
127 const uint16_t wq_n = 1 << txq->wqe_n;
128 const uint16_t wq_mask = wq_n - 1;
129 const unsigned int nb_dword_per_wqebb =
130 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
131 const unsigned int nb_dword_in_hdr =
132 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
134 volatile struct mlx5_wqe *wqe = NULL;
136 assert(elts_n > pkts_n);
137 mlx5_tx_complete(txq);
138 if (unlikely(!pkts_n))
140 for (n = 0; n < pkts_n; ++n) {
141 struct rte_mbuf *buf = pkts[n];
142 unsigned int segs_n = buf->nb_segs;
143 unsigned int ds = nb_dword_in_hdr;
144 unsigned int len = PKT_LEN(buf);
145 uint16_t wqe_ci = txq->wqe_ci;
146 const uint8x16_t ctrl_shuf_m = {
147 3, 2, 1, 0, /* bswap32 */
148 7, 6, 5, 4, /* bswap32 */
149 11, 10, 9, 8, /* bswap32 */
160 max_elts = elts_n - (elts_head - txq->elts_tail);
161 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
163 * A MPW session consumes 2 WQEs at most to
164 * include MLX5_MPW_DSEG_MAX pointers.
167 max_elts < segs_n || max_wqe < 2)
169 wqe = &((volatile struct mlx5_wqe64 *)
170 txq->wqes)[wqe_ci & wq_mask].hdr;
171 cs_flags = txq_ol_cksum_to_cs(txq, buf);
172 /* Title WQEBB pointer. */
173 t_wqe = (uint8x16_t *)wqe;
174 dseg = (uint8_t *)(wqe + 1);
176 if (!(ds++ % nb_dword_per_wqebb)) {
178 &((volatile struct mlx5_wqe64 *)
179 txq->wqes)[++wqe_ci & wq_mask];
181 txq_wr_dseg_v(txq, dseg, &buf, 1);
182 dseg += MLX5_WQE_DWORD_SIZE;
183 (*txq->elts)[elts_head++ & elts_m] = buf;
187 /* Fill CTRL in the header. */
188 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
189 MLX5_OPC_MOD_MPW << 24 |
190 txq->wqe_ci << 8 | MLX5_OPCODE_TSO,
191 txq->qp_num_8s | ds, 0, 0});
192 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
193 vst1q_u8((void *)t_wqe, ctrl);
194 /* Fill ESEG in the header. */
195 vst1q_u16((void *)(t_wqe + 1),
196 ((uint16x8_t) { 0, 0, cs_flags, rte_cpu_to_be_16(len),
198 txq->wqe_ci = wqe_ci;
202 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
203 txq->elts_head = elts_head;
204 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
205 /* A CQE slot must always be available. */
206 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
207 wqe->ctrl[2] = rte_cpu_to_be_32(8);
208 wqe->ctrl[3] = txq->elts_head;
211 #ifdef MLX5_PMD_SOFT_COUNTERS
212 txq->stats.opackets += n;
214 mlx5_tx_dbrec(txq, wqe);
219 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
220 * it returns to make it processed by txq_scatter_v(). All the packets in
221 * the pkts list should be single segment packets having same offload flags.
222 * This must be checked by txq_check_multiseg() and txq_calc_offload().
225 * Pointer to TX queue structure.
227 * Pointer to array of packets to be sent.
229 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
231 * Checksum offload flags to be written in the descriptor.
234 * Number of packets successfully transmitted (<= pkts_n).
236 static inline uint16_t
237 txq_burst_v(struct mlx5_txq_data *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
240 struct rte_mbuf **elts;
241 uint16_t elts_head = txq->elts_head;
242 const uint16_t elts_n = 1 << txq->elts_n;
243 const uint16_t elts_m = elts_n - 1;
244 const unsigned int nb_dword_per_wqebb =
245 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
246 const unsigned int nb_dword_in_hdr =
247 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
252 uint32_t comp_req = 0;
253 const uint16_t wq_n = 1 << txq->wqe_n;
254 const uint16_t wq_mask = wq_n - 1;
255 uint16_t wq_idx = txq->wqe_ci & wq_mask;
256 volatile struct mlx5_wqe64 *wq =
257 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
258 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
259 const uint8x16_t ctrl_shuf_m = {
260 3, 2, 1, 0, /* bswap32 */
261 7, 6, 5, 4, /* bswap32 */
262 11, 10, 9, 8, /* bswap32 */
269 /* Make sure all packets can fit into a single WQE. */
270 assert(elts_n > pkts_n);
271 mlx5_tx_complete(txq);
272 max_elts = (elts_n - (elts_head - txq->elts_tail));
273 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
274 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
275 if (unlikely(!pkts_n))
277 elts = &(*txq->elts)[elts_head & elts_m];
278 /* Loop for available tailroom first. */
279 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
280 for (pos = 0; pos < (n & -2); pos += 2)
281 vst1q_u64((void *)&elts[pos], vld1q_u64((void *)&pkts[pos]));
283 elts[pos] = pkts[pos];
284 /* Check if it crosses the end of the queue. */
285 if (unlikely(n < pkts_n)) {
286 elts = &(*txq->elts)[0];
287 for (pos = 0; pos < pkts_n - n; ++pos)
288 elts[pos] = pkts[n + pos];
290 txq->elts_head += pkts_n;
291 /* Save title WQEBB pointer. */
292 t_wqe = (uint8x16_t *)wqe;
293 dseg = (uint8_t *)(wqe + 1);
294 /* Calculate the number of entries to the end. */
296 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
299 txq_wr_dseg_v(txq, dseg, pkts, n);
300 /* Check if it crosses the end of the queue. */
302 dseg = (uint8_t *)txq->wqes;
303 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
305 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
306 txq->elts_comp += pkts_n;
308 /* A CQE slot must always be available. */
309 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
310 /* Request a completion. */
314 /* Fill CTRL in the header. */
315 ctrl = vreinterpretq_u8_u32((uint32x4_t) {
316 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
317 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW,
318 txq->qp_num_8s | (pkts_n + 2),
321 ctrl = vqtbl1q_u8(ctrl, ctrl_shuf_m);
322 vst1q_u8((void *)t_wqe, ctrl);
323 /* Fill ESEG in the header. */
324 vst1q_u8((void *)(t_wqe + 1),
325 ((uint8x16_t) { 0, 0, 0, 0,
329 #ifdef MLX5_PMD_SOFT_COUNTERS
330 txq->stats.opackets += pkts_n;
332 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
334 /* Ring QP doorbell. */
335 mlx5_tx_dbrec_cond_wmb(txq, wqe, pkts_n < MLX5_VPMD_TX_MAX_BURST);
340 * Store free buffers to RX SW ring.
343 * Pointer to RX queue structure.
345 * Pointer to array of packets to be stored.
347 * Number of packets to be stored.
350 rxq_copy_mbuf_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t n)
352 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
353 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
357 for (pos = 0; pos < p; pos += 2) {
360 mbp = vld1q_u64((void *)&elts[pos]);
361 vst1q_u64((void *)&pkts[pos], mbp);
364 pkts[pos] = elts[pos];
368 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
369 * extracted from the title completion descriptor.
372 * Pointer to RX queue structure.
374 * Pointer to completion array having a compressed completion at first.
376 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
377 * the title completion descriptor to be copied to the rest of mbufs.
380 rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
381 struct rte_mbuf **elts)
383 volatile struct mlx5_mini_cqe8 *mcq = (void *)&(cq + 1)->pkt_info;
384 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
387 unsigned int inv = 0;
388 /* Mask to shuffle from extracted mini CQE to mbuf. */
389 const uint8x16_t mcqe_shuf_m1 = {
390 -1, -1, -1, -1, /* skip packet_type */
391 7, 6, -1, -1, /* pkt_len, bswap16 */
392 7, 6, /* data_len, bswap16 */
393 -1, -1, /* skip vlan_tci */
394 3, 2, 1, 0 /* hash.rss, bswap32 */
396 const uint8x16_t mcqe_shuf_m2 = {
397 -1, -1, -1, -1, /* skip packet_type */
398 15, 14, -1, -1, /* pkt_len, bswap16 */
399 15, 14, /* data_len, bswap16 */
400 -1, -1, /* skip vlan_tci */
401 11, 10, 9, 8 /* hash.rss, bswap32 */
403 /* Restore the compressed count. Must be 16 bits. */
404 const uint16_t mcqe_n = t_pkt->data_len +
405 (rxq->crc_present * ETHER_CRC_LEN);
406 const uint64x2_t rearm =
407 vld1q_u64((void *)&t_pkt->rearm_data);
408 const uint32x4_t rxdf_mask = {
409 0xffffffff, /* packet_type */
410 0, /* skip pkt_len */
411 0xffff0000, /* vlan_tci, skip data_len */
412 0, /* skip hash.rss */
414 const uint8x16_t rxdf =
415 vandq_u8(vld1q_u8((void *)&t_pkt->rx_descriptor_fields1),
416 vreinterpretq_u8_u32(rxdf_mask));
417 const uint16x8_t crc_adj = {
419 rxq->crc_present * ETHER_CRC_LEN, 0,
420 rxq->crc_present * ETHER_CRC_LEN, 0,
423 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
424 #ifdef MLX5_PMD_SOFT_COUNTERS
425 uint32_t rcvd_byte = 0;
427 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
428 const uint8x8_t len_shuf_m = {
430 15, 14, /* 2nd mCQE */
431 23, 22, /* 3rd mCQE */
432 31, 30 /* 4th mCQE */
436 * A. load mCQEs into a 128bit register.
437 * B. store rearm data to mbuf.
438 * C. combine data from mCQEs with rx_descriptor_fields1.
439 * D. store rx_descriptor_fields1.
440 * E. store flow tag (rte_flow mark).
442 for (pos = 0; pos < mcqe_n; ) {
443 uint8_t *p = (void *)&mcq[pos % 8];
444 uint8_t *e0 = (void *)&elts[pos]->rearm_data;
445 uint8_t *e1 = (void *)&elts[pos + 1]->rearm_data;
446 uint8_t *e2 = (void *)&elts[pos + 2]->rearm_data;
447 uint8_t *e3 = (void *)&elts[pos + 3]->rearm_data;
449 #ifdef MLX5_PMD_SOFT_COUNTERS
450 uint16x4_t invalid_mask =
451 vcreate_u16(mcqe_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
452 -1UL << ((mcqe_n - pos) *
453 sizeof(uint16_t) * 8) : 0);
456 if (!(pos & 0x7) && pos + 8 < mcqe_n)
457 rte_prefetch0((void *)(cq + pos + 8));
459 /* A.1 load mCQEs into a 128bit register. */
460 "ld1 {v16.16b - v17.16b}, [%[mcq]] \n\t"
461 /* B.1 store rearm data to mbuf. */
462 "st1 {%[rearm].2d}, [%[e0]] \n\t"
463 "add %[e0], %[e0], #16 \n\t"
464 "st1 {%[rearm].2d}, [%[e1]] \n\t"
465 "add %[e1], %[e1], #16 \n\t"
466 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
467 "tbl v18.16b, {v16.16b}, %[mcqe_shuf_m1].16b \n\t"
468 "tbl v19.16b, {v16.16b}, %[mcqe_shuf_m2].16b \n\t"
469 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
470 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
471 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
472 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
473 /* D.1 store rx_descriptor_fields1. */
474 "st1 {v18.2d}, [%[e0]] \n\t"
475 "st1 {v19.2d}, [%[e1]] \n\t"
476 /* B.1 store rearm data to mbuf. */
477 "st1 {%[rearm].2d}, [%[e2]] \n\t"
478 "add %[e2], %[e2], #16 \n\t"
479 "st1 {%[rearm].2d}, [%[e3]] \n\t"
480 "add %[e3], %[e3], #16 \n\t"
481 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
482 "tbl v18.16b, {v17.16b}, %[mcqe_shuf_m1].16b \n\t"
483 "tbl v19.16b, {v17.16b}, %[mcqe_shuf_m2].16b \n\t"
484 "sub v18.8h, v18.8h, %[crc_adj].8h \n\t"
485 "sub v19.8h, v19.8h, %[crc_adj].8h \n\t"
486 "orr v18.16b, v18.16b, %[rxdf].16b \n\t"
487 "orr v19.16b, v19.16b, %[rxdf].16b \n\t"
488 /* D.1 store rx_descriptor_fields1. */
489 "st1 {v18.2d}, [%[e2]] \n\t"
490 "st1 {v19.2d}, [%[e3]] \n\t"
491 #ifdef MLX5_PMD_SOFT_COUNTERS
492 "tbl %[byte_cnt].8b, {v16.16b - v17.16b}, %[len_shuf_m].8b \n\t"
494 :[byte_cnt]"=&w"(byte_cnt)
498 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
499 [mcqe_shuf_m1]"w"(mcqe_shuf_m1),
500 [mcqe_shuf_m2]"w"(mcqe_shuf_m2),
501 [crc_adj]"w"(crc_adj),
502 [len_shuf_m]"w"(len_shuf_m)
503 :"memory", "v16", "v17", "v18", "v19");
504 #ifdef MLX5_PMD_SOFT_COUNTERS
505 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
506 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
509 /* E.1 store flow tag (rte_flow mark). */
510 elts[pos]->hash.fdir.hi = flow_tag;
511 elts[pos + 1]->hash.fdir.hi = flow_tag;
512 elts[pos + 2]->hash.fdir.hi = flow_tag;
513 elts[pos + 3]->hash.fdir.hi = flow_tag;
515 pos += MLX5_VPMD_DESCS_PER_LOOP;
516 /* Move to next CQE and invalidate consumed CQEs. */
517 if (!(pos & 0x7) && pos < mcqe_n) {
518 mcq = (void *)&(cq + pos)->pkt_info;
519 for (i = 0; i < 8; ++i)
520 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
523 /* Invalidate the rest of CQEs. */
524 for (; inv < mcqe_n; ++inv)
525 cq[inv].op_own = MLX5_CQE_INVALIDATE;
526 #ifdef MLX5_PMD_SOFT_COUNTERS
527 rxq->stats.ipackets += mcqe_n;
528 rxq->stats.ibytes += rcvd_byte;
530 rxq->cq_ci += mcqe_n;
534 * Calculate packet type and offload flag for mbuf and store it.
537 * Pointer to RX queue structure.
539 * Array of four 4bytes packet type info extracted from the original
540 * completion descriptor.
542 * Array of four 4bytes flow ID extracted from the original completion
545 * Opcode vector having responder error status. Each field is 4B.
547 * Pointer to array of packets to be filled.
550 rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
551 uint32x4_t ptype_info, uint32x4_t flow_tag,
552 uint16x4_t op_err, struct rte_mbuf **pkts)
555 uint32x4_t pinfo, cv_flags;
556 uint32x4_t ol_flags =
557 vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
558 rxq->hw_timestamp * PKT_RX_TIMESTAMP);
559 const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
560 const uint8x16_t cv_flag_sel = {
562 (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
563 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
565 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
567 (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
568 0, 0, 0, 0, 0, 0, 0, 0, 0
570 const uint32x4_t cv_mask =
571 vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
572 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
573 const uint64x1_t mbuf_init = vld1_u64(&rxq->mbuf_initializer);
574 const uint64x1_t r32_mask = vcreate_u64(0xffffffff);
575 uint64x2_t rearm0, rearm1, rearm2, rearm3;
578 const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
579 const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
580 uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
581 uint32x4_t invalid_mask;
583 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
584 invalid_mask = vceqzq_u32(flow_tag);
585 ol_flags = vorrq_u32(ol_flags,
586 vbicq_u32(fdir_flags, invalid_mask));
587 /* Mask out invalid entries. */
588 fdir_id_flags = vbicq_u32(fdir_id_flags, invalid_mask);
589 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
590 ol_flags = vorrq_u32(ol_flags,
591 vbicq_u32(fdir_id_flags,
592 vceqq_u32(flow_tag, ft_def)));
595 * ptype_info has the following:
599 * bit[11:10] = l3_hdr_type
600 * bit[14:12] = l4_hdr_type
603 * bit[17] = outer_l3_type
605 ptype = vshrn_n_u32(ptype_info, 10);
606 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
607 ptype = vorr_u16(ptype, op_err);
608 pkts[0]->packet_type =
609 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 6)];
610 pkts[1]->packet_type =
611 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 4)];
612 pkts[2]->packet_type =
613 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 2)];
614 pkts[3]->packet_type =
615 mlx5_ptype_table[vget_lane_u8(vreinterpret_u8_u16(ptype), 0)];
616 /* Fill flags for checksum and VLAN. */
617 pinfo = vandq_u32(ptype_info, ptype_ol_mask);
618 pinfo = vreinterpretq_u32_u8(
619 vqtbl1q_u8(cv_flag_sel, vreinterpretq_u8_u32(pinfo)));
620 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
621 cv_flags = vshlq_n_u32(pinfo, 9);
622 cv_flags = vorrq_u32(pinfo, cv_flags);
623 /* Move back flags to start from byte[0]. */
624 cv_flags = vshrq_n_u32(cv_flags, 8);
625 /* Mask out garbage bits. */
626 cv_flags = vandq_u32(cv_flags, cv_mask);
627 /* Merge to ol_flags. */
628 ol_flags = vorrq_u32(ol_flags, cv_flags);
629 /* Merge mbuf_init and ol_flags, and store. */
630 rearm0 = vcombine_u64(mbuf_init,
631 vshr_n_u64(vget_high_u64(vreinterpretq_u64_u32(
633 rearm1 = vcombine_u64(mbuf_init,
634 vand_u64(vget_high_u64(vreinterpretq_u64_u32(
635 ol_flags)), r32_mask));
636 rearm2 = vcombine_u64(mbuf_init,
637 vshr_n_u64(vget_low_u64(vreinterpretq_u64_u32(
639 rearm3 = vcombine_u64(mbuf_init,
640 vand_u64(vget_low_u64(vreinterpretq_u64_u32(
641 ol_flags)), r32_mask));
642 vst1q_u64((void *)&pkts[0]->rearm_data, rearm0);
643 vst1q_u64((void *)&pkts[1]->rearm_data, rearm1);
644 vst1q_u64((void *)&pkts[2]->rearm_data, rearm2);
645 vst1q_u64((void *)&pkts[3]->rearm_data, rearm3);
649 * Receive burst of packets. An errored completion also consumes a mbuf, but the
650 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
651 * before returning to application.
654 * Pointer to RX queue structure.
656 * Array to store received packets.
658 * Maximum number of packets in array.
660 * Pointer to a flag. Set non-zero value if pkts array has at least one error
664 * Number of packets received including errors (<= pkts_n).
666 static inline uint16_t
667 rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
670 const uint16_t q_n = 1 << rxq->cqe_n;
671 const uint16_t q_mask = q_n - 1;
672 volatile struct mlx5_cqe *cq;
673 struct rte_mbuf **elts;
677 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
678 uint16_t nocmp_n = 0;
679 uint16_t rcvd_pkt = 0;
680 unsigned int cq_idx = rxq->cq_ci & q_mask;
681 unsigned int elts_idx;
682 const uint16x4_t ownership = vdup_n_u16(!(rxq->cq_ci & (q_mask + 1)));
683 const uint16x4_t owner_check = vcreate_u16(0x0001000100010001);
684 const uint16x4_t opcode_check = vcreate_u16(0x00f000f000f000f0);
685 const uint16x4_t format_check = vcreate_u16(0x000c000c000c000c);
686 const uint16x4_t resp_err_check = vcreate_u16(0x00e000e000e000e0);
687 #ifdef MLX5_PMD_SOFT_COUNTERS
688 uint32_t rcvd_byte = 0;
690 /* Mask to generate 16B length vector. */
691 const uint8x8_t len_shuf_m = {
692 52, 53, /* 4th CQE */
693 36, 37, /* 3rd CQE */
694 20, 21, /* 2nd CQE */
697 /* Mask to extract 16B data from a 64B CQE. */
698 const uint8x16_t cqe_shuf_m = {
699 28, 29, /* hdr_type_etc */
702 47, 46, /* byte_cnt, bswap16 */
703 31, 30, /* vlan_info, bswap16 */
704 15, 14, 13, 12, /* rx_hash_res, bswap32 */
705 57, 58, 59, /* flow_tag */
708 /* Mask to generate 16B data for mbuf. */
709 const uint8x16_t mb_shuf_m = {
710 4, 5, -1, -1, /* pkt_len */
713 8, 9, 10, 11, /* hash.rss */
714 12, 13, 14, -1 /* hash.fdir.hi */
716 /* Mask to generate 16B owner vector. */
717 const uint8x8_t owner_shuf_m = {
718 63, -1, /* 4th CQE */
719 47, -1, /* 3rd CQE */
720 31, -1, /* 2nd CQE */
723 /* Mask to generate a vector having packet_type/ol_flags. */
724 const uint8x16_t ptype_shuf_m = {
725 48, 49, 50, -1, /* 4th CQE */
726 32, 33, 34, -1, /* 3rd CQE */
727 16, 17, 18, -1, /* 2nd CQE */
728 0, 1, 2, -1 /* 1st CQE */
730 /* Mask to generate a vector having flow tags. */
731 const uint8x16_t ftag_shuf_m = {
732 60, 61, 62, -1, /* 4th CQE */
733 44, 45, 46, -1, /* 3rd CQE */
734 28, 29, 30, -1, /* 2nd CQE */
735 12, 13, 14, -1 /* 1st CQE */
737 const uint16x8_t crc_adj = {
738 0, 0, rxq->crc_present * ETHER_CRC_LEN, 0, 0, 0, 0, 0
740 const uint32x4_t flow_mark_adj = { 0, 0, 0, rxq->mark * (-1) };
742 assert(rxq->sges_n == 0);
743 assert(rxq->cqe_n == rxq->elts_n);
744 cq = &(*rxq->cqes)[cq_idx];
745 rte_prefetch_non_temporal(cq);
746 rte_prefetch_non_temporal(cq + 1);
747 rte_prefetch_non_temporal(cq + 2);
748 rte_prefetch_non_temporal(cq + 3);
749 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
752 * rq_ci >= cq_ci >= rq_pi
753 * Definition of indexes:
754 * rq_ci - cq_ci := # of buffers owned by HW (posted).
755 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
756 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
758 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
759 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(q_n))
760 mlx5_rx_replenish_bulk_mbuf(rxq, repl_n);
761 /* See if there're unreturned mbufs from compressed CQE. */
762 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
764 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
765 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
766 rxq->rq_pi += rcvd_pkt;
769 elts_idx = rxq->rq_pi & q_mask;
770 elts = &(*rxq->elts)[elts_idx];
771 /* Not to overflow pkts array. */
772 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
773 /* Not to cross queue end. */
774 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
777 /* At this point, there shouldn't be any remained packets. */
778 assert(rxq->rq_pi == rxq->cq_ci);
780 * Note that vectors have reverse order - {v3, v2, v1, v0}, because
781 * there's no instruction to count trailing zeros. __builtin_clzl() is
784 * A. copy 4 mbuf pointers from elts ring to returing pkts.
785 * B. load 64B CQE and extract necessary fields
786 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
787 * following structure:
789 * uint16_t hdr_type_etc;
793 * uint16_t vlan_info;
794 * uint32_t rx_has_res;
795 * uint8_t flow_tag[3];
800 * E. find compressed CQE.
804 pos += MLX5_VPMD_DESCS_PER_LOOP) {
806 uint16x4_t opcode, owner_mask, invalid_mask;
807 uint16x4_t comp_mask;
810 uint32x4_t ptype_info, flow_tag;
811 register uint64x2_t c0, c1, c2, c3;
812 uint8_t *p0, *p1, *p2, *p3;
813 uint8_t *e0 = (void *)&elts[pos]->pkt_len;
814 uint8_t *e1 = (void *)&elts[pos + 1]->pkt_len;
815 uint8_t *e2 = (void *)&elts[pos + 2]->pkt_len;
816 uint8_t *e3 = (void *)&elts[pos + 3]->pkt_len;
817 void *elts_p = (void *)&elts[pos];
818 void *pkts_p = (void *)&pkts[pos];
820 /* A.0 do not cross the end of CQ. */
821 mask = vcreate_u16(pkts_n - pos < MLX5_VPMD_DESCS_PER_LOOP ?
822 -1UL >> ((pkts_n - pos) *
823 sizeof(uint16_t) * 8) : 0);
824 p0 = (void *)&cq[pos].pkt_info;
825 p1 = p0 + (pkts_n - pos > 1) * sizeof(struct mlx5_cqe);
826 p2 = p1 + (pkts_n - pos > 2) * sizeof(struct mlx5_cqe);
827 p3 = p2 + (pkts_n - pos > 3) * sizeof(struct mlx5_cqe);
828 /* B.0 (CQE 3) load a block having op_own. */
829 c3 = vld1q_u64((uint64_t *)(p3 + 48));
830 /* B.0 (CQE 2) load a block having op_own. */
831 c2 = vld1q_u64((uint64_t *)(p2 + 48));
832 /* B.0 (CQE 1) load a block having op_own. */
833 c1 = vld1q_u64((uint64_t *)(p1 + 48));
834 /* B.0 (CQE 0) load a block having op_own. */
835 c0 = vld1q_u64((uint64_t *)(p0 + 48));
836 /* Synchronize for loading the rest of blocks. */
838 /* Prefetch next 4 CQEs. */
839 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
840 unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
841 rte_prefetch_non_temporal(&cq[next]);
842 rte_prefetch_non_temporal(&cq[next + 1]);
843 rte_prefetch_non_temporal(&cq[next + 2]);
844 rte_prefetch_non_temporal(&cq[next + 3]);
847 /* B.1 (CQE 3) load the rest of blocks. */
848 "ld1 {v16.16b - v18.16b}, [%[p3]] \n\t"
849 /* B.2 (CQE 3) move the block having op_own. */
850 "mov v19.16b, %[c3].16b \n\t"
851 /* B.3 (CQE 3) extract 16B fields. */
852 "tbl v23.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
853 /* B.1 (CQE 2) load the rest of blocks. */
854 "ld1 {v16.16b - v18.16b}, [%[p2]] \n\t"
855 /* B.4 (CQE 3) adjust CRC length. */
856 "sub v23.8h, v23.8h, %[crc_adj].8h \n\t"
857 /* C.1 (CQE 3) generate final structure for mbuf. */
858 "tbl v15.16b, {v23.16b}, %[mb_shuf_m].16b \n\t"
859 /* B.2 (CQE 2) move the block having op_own. */
860 "mov v19.16b, %[c2].16b \n\t"
861 /* B.3 (CQE 2) extract 16B fields. */
862 "tbl v22.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
863 /* B.1 (CQE 1) load the rest of blocks. */
864 "ld1 {v16.16b - v18.16b}, [%[p1]] \n\t"
865 /* B.4 (CQE 2) adjust CRC length. */
866 "sub v22.8h, v22.8h, %[crc_adj].8h \n\t"
867 /* C.1 (CQE 2) generate final structure for mbuf. */
868 "tbl v14.16b, {v22.16b}, %[mb_shuf_m].16b \n\t"
869 /* B.2 (CQE 1) move the block having op_own. */
870 "mov v19.16b, %[c1].16b \n\t"
871 /* B.3 (CQE 1) extract 16B fields. */
872 "tbl v21.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
873 /* B.1 (CQE 0) load the rest of blocks. */
874 "ld1 {v16.16b - v18.16b}, [%[p0]] \n\t"
875 /* B.4 (CQE 1) adjust CRC length. */
876 "sub v21.8h, v21.8h, %[crc_adj].8h \n\t"
877 /* C.1 (CQE 1) generate final structure for mbuf. */
878 "tbl v13.16b, {v21.16b}, %[mb_shuf_m].16b \n\t"
879 /* B.2 (CQE 0) move the block having op_own. */
880 "mov v19.16b, %[c0].16b \n\t"
881 /* A.1 load mbuf pointers. */
882 "ld1 {v24.2d - v25.2d}, [%[elts_p]] \n\t"
883 /* B.3 (CQE 0) extract 16B fields. */
884 "tbl v20.16b, {v16.16b - v19.16b}, %[cqe_shuf_m].16b \n\t"
885 /* B.4 (CQE 0) adjust CRC length. */
886 "sub v20.8h, v20.8h, %[crc_adj].8h \n\t"
887 /* D.1 extract op_own byte. */
888 "tbl %[op_own].8b, {v20.16b - v23.16b}, %[owner_shuf_m].8b \n\t"
889 /* C.2 (CQE 3) adjust flow mark. */
890 "add v15.4s, v15.4s, %[flow_mark_adj].4s \n\t"
891 /* C.3 (CQE 3) fill in mbuf - rx_descriptor_fields1. */
892 "st1 {v15.2d}, [%[e3]] \n\t"
893 /* C.2 (CQE 2) adjust flow mark. */
894 "add v14.4s, v14.4s, %[flow_mark_adj].4s \n\t"
895 /* C.3 (CQE 2) fill in mbuf - rx_descriptor_fields1. */
896 "st1 {v14.2d}, [%[e2]] \n\t"
897 /* C.1 (CQE 0) generate final structure for mbuf. */
898 "tbl v12.16b, {v20.16b}, %[mb_shuf_m].16b \n\t"
899 /* C.2 (CQE 1) adjust flow mark. */
900 "add v13.4s, v13.4s, %[flow_mark_adj].4s \n\t"
901 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
902 "st1 {v13.2d}, [%[e1]] \n\t"
903 #ifdef MLX5_PMD_SOFT_COUNTERS
904 /* Extract byte_cnt. */
905 "tbl %[byte_cnt].8b, {v20.16b - v23.16b}, %[len_shuf_m].8b \n\t"
907 /* Extract ptype_info. */
908 "tbl %[ptype_info].16b, {v20.16b - v23.16b}, %[ptype_shuf_m].16b \n\t"
909 /* Extract flow_tag. */
910 "tbl %[flow_tag].16b, {v20.16b - v23.16b}, %[ftag_shuf_m].16b \n\t"
911 /* A.2 copy mbuf pointers. */
912 "st1 {v24.2d - v25.2d}, [%[pkts_p]] \n\t"
913 /* C.2 (CQE 0) adjust flow mark. */
914 "add v12.4s, v12.4s, %[flow_mark_adj].4s \n\t"
915 /* C.3 (CQE 1) fill in mbuf - rx_descriptor_fields1. */
916 "st1 {v12.2d}, [%[e0]] \n\t"
917 :[op_own]"=&w"(op_own),
918 [byte_cnt]"=&w"(byte_cnt),
919 [ptype_info]"=&w"(ptype_info),
920 [flow_tag]"=&w"(flow_tag)
921 :[p3]"r"(p3), [p2]"r"(p2), [p1]"r"(p1), [p0]"r"(p0),
922 [e3]"r"(e3), [e2]"r"(e2), [e1]"r"(e1), [e0]"r"(e0),
923 [c3]"w"(c3), [c2]"w"(c2), [c1]"w"(c1), [c0]"w"(c0),
926 [cqe_shuf_m]"w"(cqe_shuf_m),
927 [mb_shuf_m]"w"(mb_shuf_m),
928 [owner_shuf_m]"w"(owner_shuf_m),
929 [len_shuf_m]"w"(len_shuf_m),
930 [ptype_shuf_m]"w"(ptype_shuf_m),
931 [ftag_shuf_m]"w"(ftag_shuf_m),
932 [crc_adj]"w"(crc_adj),
933 [flow_mark_adj]"w"(flow_mark_adj)
935 "v12", "v13", "v14", "v15",
936 "v16", "v17", "v18", "v19",
937 "v20", "v21", "v22", "v23",
939 /* D.2 flip owner bit to mark CQEs from last round. */
940 owner_mask = vand_u16(op_own, owner_check);
941 owner_mask = vceq_u16(owner_mask, ownership);
942 /* D.3 get mask for invalidated CQEs. */
943 opcode = vand_u16(op_own, opcode_check);
944 invalid_mask = vceq_u16(opcode_check, opcode);
945 /* E.1 find compressed CQE format. */
946 comp_mask = vand_u16(op_own, format_check);
947 comp_mask = vceq_u16(comp_mask, format_check);
948 /* D.4 mask out beyond boundary. */
949 invalid_mask = vorr_u16(invalid_mask, mask);
950 /* D.5 merge invalid_mask with invalid owner. */
951 invalid_mask = vorr_u16(invalid_mask, owner_mask);
952 /* E.2 mask out invalid entries. */
953 comp_mask = vbic_u16(comp_mask, invalid_mask);
954 /* E.3 get the first compressed CQE. */
955 comp_idx = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
957 (sizeof(uint16_t) * 8);
958 /* D.6 mask out entries after the compressed CQE. */
959 mask = vcreate_u16(comp_idx < MLX5_VPMD_DESCS_PER_LOOP ?
960 -1UL >> (comp_idx * sizeof(uint16_t) * 8) :
962 invalid_mask = vorr_u16(invalid_mask, mask);
963 /* D.7 count non-compressed valid CQEs. */
964 n = __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16(
965 invalid_mask), 0)) / (sizeof(uint16_t) * 8);
967 /* D.2 get the final invalid mask. */
968 mask = vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ?
969 -1UL >> (n * sizeof(uint16_t) * 8) : 0);
970 invalid_mask = vorr_u16(invalid_mask, mask);
971 /* D.3 check error in opcode. */
972 opcode = vceq_u16(resp_err_check, opcode);
973 opcode = vbic_u16(opcode, invalid_mask);
974 /* D.4 mark if any error is set */
975 *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
976 /* C.4 fill in mbuf - rearm_data and packet_type. */
977 rxq_cq_to_ptype_oflags_v(rxq, ptype_info, flow_tag,
979 if (rxq->hw_timestamp) {
980 elts[pos]->timestamp =
982 container_of(p0, struct mlx5_cqe,
983 pkt_info)->timestamp);
984 elts[pos + 1]->timestamp =
986 container_of(p1, struct mlx5_cqe,
987 pkt_info)->timestamp);
988 elts[pos + 2]->timestamp =
990 container_of(p2, struct mlx5_cqe,
991 pkt_info)->timestamp);
992 elts[pos + 3]->timestamp =
994 container_of(p3, struct mlx5_cqe,
995 pkt_info)->timestamp);
997 #ifdef MLX5_PMD_SOFT_COUNTERS
998 /* Add up received bytes count. */
999 byte_cnt = vbic_u16(byte_cnt, invalid_mask);
1000 rcvd_byte += vget_lane_u64(vpaddl_u32(vpaddl_u16(byte_cnt)), 0);
1003 * Break the loop unless more valid CQE is expected, or if
1004 * there's a compressed CQE.
1006 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1009 /* If no new CQE seen, return without updating cq_db. */
1010 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1012 /* Update the consumer indexes for non-compressed CQEs. */
1013 assert(nocmp_n <= pkts_n);
1014 rxq->cq_ci += nocmp_n;
1015 rxq->rq_pi += nocmp_n;
1016 rcvd_pkt += nocmp_n;
1017 #ifdef MLX5_PMD_SOFT_COUNTERS
1018 rxq->stats.ipackets += nocmp_n;
1019 rxq->stats.ibytes += rcvd_byte;
1021 /* Decompress the last CQE if compressed. */
1022 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1023 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1024 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1025 /* Return more packets if needed. */
1026 if (nocmp_n < pkts_n) {
1027 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1029 n = RTE_MIN(n, pkts_n - nocmp_n);
1030 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1035 rte_compiler_barrier();
1036 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1040 #endif /* RTE_PMD_MLX5_RXTX_VEC_NEON_H_ */