drivers/net/mrvl/mrvl_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Marvell International Ltd.
   5  *   Copyright(c) 2017 Semihalf.
   6  *   All rights reserved.
   7  *
   8  *   Redistribution and use in source and binary forms, with or without
   9  *   modification, are permitted provided that the following conditions
  10  *   are met:
  11  *
  12  *     * Redistributions of source code must retain the above copyright
  13  *       notice, this list of conditions and the following disclaimer.
  14  *     * Redistributions in binary form must reproduce the above copyright
  15  *       notice, this list of conditions and the following disclaimer in
  16  *       the documentation and/or other materials provided with the
  17  *       distribution.
  18  *     * Neither the name of Semihalf nor the names of its
  19  *       contributors may be used to endorse or promote products derived
  20  *       from this software without specific prior written permission.
  21  *
  22  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_log.h>
  38 #include <rte_malloc.h>
  39 #include <rte_bus_vdev.h>
  40
  41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  42  * we'll declare only one version.
  43  *
  44  * Note that it is not used in this PMD anyway.
  45  */
  46 #ifdef container_of
  47 #undef container_of
  48 #endif
  49
  50 #include <fcntl.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/sockios.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <sys/ioctl.h>
  56 #include <sys/socket.h>
  57 #include <sys/stat.h>
  58 #include <sys/types.h>
  59
  60 #include "mrvl_ethdev.h"
  61 #include "mrvl_qos.h"
  62
  63 /* bitmask with reserved hifs */
  64 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  65 /* bitmask with reserved bpools */
  66 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  67 /* bitmask with reserved kernel RSS tables */
  68 #define MRVL_MUSDK_RSS_RESERVED 0x01
  69 /* maximum number of available hifs */
  70 #define MRVL_MUSDK_HIFS_MAX 9
  71
  72 /* prefetch shift */
  73 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  74
  75 /* TCAM has 25 entries reserved for uc/mc filter entries */
  76 #define MRVL_MAC_ADDRS_MAX 25
  77 #define MRVL_MATCH_LEN 16
  78 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  79 /* Maximum allowable packet size */
  80 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  81
  82 #define MRVL_IFACE_NAME_ARG "iface"
  83 #define MRVL_CFG_ARG "cfg"
  84
  85 #define MRVL_BURST_SIZE 64
  86
  87 #define MRVL_ARP_LENGTH 28
  88
  89 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  90
  91 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  92 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  93
  94 /* Memory size (in bytes) for MUSDK dma buffers */
  95 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
  96
  97 /** Port Rx offload capabilities */
  98 #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \
  99                           DEV_RX_OFFLOAD_JUMBO_FRAME | \
 100                           DEV_RX_OFFLOAD_CRC_STRIP | \
 101                           DEV_RX_OFFLOAD_CHECKSUM)
 102
 103 /** Port Tx offloads capabilities */
 104 #define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \
 105                           DEV_TX_OFFLOAD_UDP_CKSUM | \
 106                           DEV_TX_OFFLOAD_TCP_CKSUM)
 107
 108 static const char * const valid_args[] = {
 109         MRVL_IFACE_NAME_ARG,
 110         MRVL_CFG_ARG,
 111         NULL
 112 };
 113
 114 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 115 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 116 static int used_bpools[PP2_NUM_PKT_PROC] = {
 117         MRVL_MUSDK_BPOOLS_RESERVED,
 118         MRVL_MUSDK_BPOOLS_RESERVED
 119 };
 120
 121 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
 122 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
 123 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 124
 125 struct mrvl_ifnames {
 126         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
 127         int idx;
 128 };
 129
 130 /*
 131  * To use buffer harvesting based on loopback port shadow queue structure
 132  * was introduced for buffers information bookkeeping.
 133  *
 134  * Before sending the packet, related buffer information (pp2_buff_inf) is
 135  * stored in shadow queue. After packet is transmitted no longer used
 136  * packet buffer is released back to it's original hardware pool,
 137  * on condition it originated from interface.
 138  * In case it  was generated by application itself i.e: mbuf->port field is
 139  * 0xff then its released to software mempool.
 140  */
 141 struct mrvl_shadow_txq {
 142         int head;           /* write index - used when sending buffers */
 143         int tail;           /* read index - used when releasing buffers */
 144         u16 size;           /* queue occupied size */
 145         u16 num_to_release; /* number of buffers sent, that can be released */
 146         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 147 };
 148
 149 struct mrvl_rxq {
 150         struct mrvl_priv *priv;
 151         struct rte_mempool *mp;
 152         int queue_id;
 153         int port_id;
 154         int cksum_enabled;
 155         uint64_t bytes_recv;
 156         uint64_t drop_mac;
 157 };
 158
 159 struct mrvl_txq {
 160         struct mrvl_priv *priv;
 161         int queue_id;
 162         int port_id;
 163         uint64_t bytes_sent;
 164         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 165 };
 166
 167 static int mrvl_lcore_first;
 168 static int mrvl_lcore_last;
 169 static int mrvl_dev_num;
 170
 171 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 172 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 173                         struct pp2_hif *hif, unsigned int core_id,
 174                         struct mrvl_shadow_txq *sq, int qid, int force);
 175
 176 static inline int
 177 mrvl_get_bpool_size(int pp2_id, int pool_id)
 178 {
 179         int i;
 180         int size = 0;
 181
 182         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 183                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 184
 185         return size;
 186 }
 187
 188 static inline int
 189 mrvl_reserve_bit(int *bitmap, int max)
 190 {
 191         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 192
 193         if (n >= max)
 194                 return -1;
 195
 196         *bitmap |= 1 << n;
 197
 198         return n;
 199 }
 200
 201 static int
 202 mrvl_init_hif(int core_id)
 203 {
 204         struct pp2_hif_params params;
 205         char match[MRVL_MATCH_LEN];
 206         int ret;
 207
 208         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 209         if (ret < 0) {
 210                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 211                 return ret;
 212         }
 213
 214         snprintf(match, sizeof(match), "hif-%d", ret);
 215         memset(&params, 0, sizeof(params));
 216         params.match = match;
 217         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 218         ret = pp2_hif_init(&params, &hifs[core_id]);
 219         if (ret) {
 220                 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
 221                 return ret;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static inline struct pp2_hif*
 228 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 229 {
 230         int ret;
 231
 232         if (likely(hifs[core_id] != NULL))
 233                 return hifs[core_id];
 234
 235         rte_spinlock_lock(&priv->lock);
 236
 237         ret = mrvl_init_hif(core_id);
 238         if (ret < 0) {
 239                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 240                 goto out;
 241         }
 242
 243         if (core_id < mrvl_lcore_first)
 244                 mrvl_lcore_first = core_id;
 245
 246         if (core_id > mrvl_lcore_last)
 247                 mrvl_lcore_last = core_id;
 248 out:
 249         rte_spinlock_unlock(&priv->lock);
 250
 251         return hifs[core_id];
 252 }
 253
 254 /**
 255  * Configure rss based on dpdk rss configuration.
 256  *
 257  * @param priv
 258  *   Pointer to private structure.
 259  * @param rss_conf
 260  *   Pointer to RSS configuration.
 261  *
 262  * @return
 263  *   0 on success, negative error value otherwise.
 264  */
 265 static int
 266 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 267 {
 268         if (rss_conf->rss_key)
 269                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 270
 271         if (rss_conf->rss_hf == 0) {
 272                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 273         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 274                 priv->ppio_params.inqs_params.hash_type =
 275                         PP2_PPIO_HASH_T_2_TUPLE;
 276         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 277                 priv->ppio_params.inqs_params.hash_type =
 278                         PP2_PPIO_HASH_T_5_TUPLE;
 279                 priv->rss_hf_tcp = 1;
 280         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 281                 priv->ppio_params.inqs_params.hash_type =
 282                         PP2_PPIO_HASH_T_5_TUPLE;
 283                 priv->rss_hf_tcp = 0;
 284         } else {
 285                 return -EINVAL;
 286         }
 287
 288         return 0;
 289 }
 290
 291 /**
 292  * Ethernet device configuration.
 293  *
 294  * Prepare the driver for a given number of TX and RX queues and
 295  * configure RSS.
 296  *
 297  * @param dev
 298  *   Pointer to Ethernet device structure.
 299  *
 300  * @return
 301  *   0 on success, negative error value otherwise.
 302  */
 303 static int
 304 mrvl_dev_configure(struct rte_eth_dev *dev)
 305 {
 306         struct mrvl_priv *priv = dev->data->dev_private;
 307         int ret;
 308
 309         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 310             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 311                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 312                         dev->data->dev_conf.rxmode.mq_mode);
 313                 return -EINVAL;
 314         }
 315
 316         if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
 317                 RTE_LOG(INFO, PMD,
 318                         "L2 CRC stripping is always enabled in hw\n");
 319                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
 320         }
 321
 322         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 323                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 324                 return -EINVAL;
 325         }
 326
 327         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 328                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 329                 return -EINVAL;
 330         }
 331
 332         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) {
 333                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 334                 return -EINVAL;
 335         }
 336
 337         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 338                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 339                 return -EINVAL;
 340         }
 341
 342         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 343                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 344                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 345
 346         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 347                                   dev->data->nb_rx_queues);
 348         if (ret < 0)
 349                 return ret;
 350
 351         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 352         priv->ppio_params.maintain_stats = 1;
 353         priv->nb_rx_queues = dev->data->nb_rx_queues;
 354
 355         if (dev->data->nb_rx_queues == 1 &&
 356             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 357                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 358                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 359
 360                 return 0;
 361         }
 362
 363         return mrvl_configure_rss(priv,
 364                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 365 }
 366
 367 /**
 368  * DPDK callback to change the MTU.
 369  *
 370  * Setting the MTU affects hardware MRU (packets larger than the MRU
 371  * will be dropped).
 372  *
 373  * @param dev
 374  *   Pointer to Ethernet device structure.
 375  * @param mtu
 376  *   New MTU.
 377  *
 378  * @return
 379  *   0 on success, negative error value otherwise.
 380  */
 381 static int
 382 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 383 {
 384         struct mrvl_priv *priv = dev->data->dev_private;
 385         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 386         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 387         int ret;
 388
 389         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 390                 return -EINVAL;
 391
 392         if (!priv->ppio)
 393                 return 0;
 394
 395         ret = pp2_ppio_set_mru(priv->ppio, mru);
 396         if (ret)
 397                 return ret;
 398
 399         return pp2_ppio_set_mtu(priv->ppio, mtu);
 400 }
 401
 402 /**
 403  * DPDK callback to bring the link up.
 404  *
 405  * @param dev
 406  *   Pointer to Ethernet device structure.
 407  *
 408  * @return
 409  *   0 on success, negative error value otherwise.
 410  */
 411 static int
 412 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 413 {
 414         struct mrvl_priv *priv = dev->data->dev_private;
 415         int ret;
 416
 417         if (!priv->ppio)
 418                 return -EPERM;
 419
 420         ret = pp2_ppio_enable(priv->ppio);
 421         if (ret)
 422                 return ret;
 423
 424         /*
 425          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 426          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 427          * PP2_TRAFFIC_INGRESS_EGRESS.
 428          *
 429          * Set mtu to default DPDK value here.
 430          */
 431         ret = mrvl_mtu_set(dev, dev->data->mtu);
 432         if (ret)
 433                 pp2_ppio_disable(priv->ppio);
 434
 435         return ret;
 436 }
 437
 438 /**
 439  * DPDK callback to bring the link down.
 440  *
 441  * @param dev
 442  *   Pointer to Ethernet device structure.
 443  *
 444  * @return
 445  *   0 on success, negative error value otherwise.
 446  */
 447 static int
 448 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 449 {
 450         struct mrvl_priv *priv = dev->data->dev_private;
 451
 452         if (!priv->ppio)
 453                 return -EPERM;
 454
 455         return pp2_ppio_disable(priv->ppio);
 456 }
 457
 458 /**
 459  * DPDK callback to start the device.
 460  *
 461  * @param dev
 462  *   Pointer to Ethernet device structure.
 463  *
 464  * @return
 465  *   0 on success, negative errno value on failure.
 466  */
 467 static int
 468 mrvl_dev_start(struct rte_eth_dev *dev)
 469 {
 470         struct mrvl_priv *priv = dev->data->dev_private;
 471         char match[MRVL_MATCH_LEN];
 472         int ret = 0, def_init_size;
 473
 474         snprintf(match, sizeof(match), "ppio-%d:%d",
 475                  priv->pp_id, priv->ppio_id);
 476         priv->ppio_params.match = match;
 477
 478         /*
 479          * Calculate the minimum bpool size for refill feature as follows:
 480          * 2 default burst sizes multiply by number of rx queues.
 481          * If the bpool size will be below this value, new buffers will
 482          * be added to the pool.
 483          */
 484         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 485
 486         /* In case initial bpool size configured in queues setup is
 487          * smaller than minimum size add more buffers
 488          */
 489         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 490         if (priv->bpool_init_size < def_init_size) {
 491                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 492
 493                 priv->bpool_init_size += buffs_to_add;
 494                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 495                 if (ret)
 496                         RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
 497         }
 498
 499         /*
 500          * Calculate the maximum bpool size for refill feature as follows:
 501          * maximum number of descriptors in rx queue multiply by number
 502          * of rx queues plus minimum bpool size.
 503          * In case the bpool size will exceed this value, superfluous buffers
 504          * will be removed
 505          */
 506         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 507                                 priv->bpool_min_size;
 508
 509         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 510         if (ret) {
 511                 RTE_LOG(ERR, PMD, "Failed to init ppio\n");
 512                 return ret;
 513         }
 514
 515         /*
 516          * In case there are some some stale uc/mc mac addresses flush them
 517          * here. It cannot be done during mrvl_dev_close() as port information
 518          * is already gone at that point (due to pp2_ppio_deinit() in
 519          * mrvl_dev_stop()).
 520          */
 521         if (!priv->uc_mc_flushed) {
 522                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 523                 if (ret) {
 524                         RTE_LOG(ERR, PMD,
 525                                 "Failed to flush uc/mc filter list\n");
 526                         goto out;
 527                 }
 528                 priv->uc_mc_flushed = 1;
 529         }
 530
 531         if (!priv->vlan_flushed) {
 532                 ret = pp2_ppio_flush_vlan(priv->ppio);
 533                 if (ret) {
 534                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 535                         /*
 536                          * TODO
 537                          * once pp2_ppio_flush_vlan() is supported jump to out
 538                          * goto out;
 539                          */
 540                 }
 541                 priv->vlan_flushed = 1;
 542         }
 543
 544         /* For default QoS config, don't start classifier. */
 545         if (mrvl_qos_cfg) {
 546                 ret = mrvl_start_qos_mapping(priv);
 547                 if (ret) {
 548                         RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n");
 549                         goto out;
 550                 }
 551         }
 552
 553         ret = mrvl_dev_set_link_up(dev);
 554         if (ret) {
 555                 RTE_LOG(ERR, PMD, "Failed to set link up\n");
 556                 goto out;
 557         }
 558
 559         return 0;
 560 out:
 561         RTE_LOG(ERR, PMD, "Failed to start device\n");
 562         pp2_ppio_deinit(priv->ppio);
 563         return ret;
 564 }
 565
 566 /**
 567  * Flush receive queues.
 568  *
 569  * @param dev
 570  *   Pointer to Ethernet device structure.
 571  */
 572 static void
 573 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 574 {
 575         int i;
 576
 577         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 578         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 579                 int ret, num;
 580
 581                 do {
 582                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 583                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 584
 585                         num = MRVL_PP2_RXD_MAX;
 586                         ret = pp2_ppio_recv(q->priv->ppio,
 587                                             q->priv->rxq_map[q->queue_id].tc,
 588                                             q->priv->rxq_map[q->queue_id].inq,
 589                                             descs, (uint16_t *)&num);
 590                 } while (ret == 0 && num);
 591         }
 592 }
 593
 594 /**
 595  * Flush transmit shadow queues.
 596  *
 597  * @param dev
 598  *   Pointer to Ethernet device structure.
 599  */
 600 static void
 601 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 602 {
 603         int i, j;
 604         struct mrvl_txq *txq;
 605
 606         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 607         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 608                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 609
 610                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 611                         struct mrvl_shadow_txq *sq;
 612
 613                         if (!hifs[j])
 614                                 continue;
 615
 616                         sq = &txq->shadow_txqs[j];
 617                         mrvl_free_sent_buffers(txq->priv->ppio,
 618                                 hifs[j], j, sq, txq->queue_id, 1);
 619                         while (sq->tail != sq->head) {
 620                                 uint64_t addr = cookie_addr_high |
 621                                         sq->ent[sq->tail].buff.cookie;
 622                                 rte_pktmbuf_free(
 623                                         (struct rte_mbuf *)addr);
 624                                 sq->tail = (sq->tail + 1) &
 625                                             MRVL_PP2_TX_SHADOWQ_MASK;
 626                         }
 627                         memset(sq, 0, sizeof(*sq));
 628                 }
 629         }
 630 }
 631
 632 /**
 633  * Flush hardware bpool (buffer-pool).
 634  *
 635  * @param dev
 636  *   Pointer to Ethernet device structure.
 637  */
 638 static void
 639 mrvl_flush_bpool(struct rte_eth_dev *dev)
 640 {
 641         struct mrvl_priv *priv = dev->data->dev_private;
 642         struct pp2_hif *hif;
 643         uint32_t num;
 644         int ret;
 645         unsigned int core_id = rte_lcore_id();
 646
 647         if (core_id == LCORE_ID_ANY)
 648                 core_id = 0;
 649
 650         hif = mrvl_get_hif(priv, core_id);
 651
 652         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 653         if (ret) {
 654                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 655                 return;
 656         }
 657
 658         while (num--) {
 659                 struct pp2_buff_inf inf;
 660                 uint64_t addr;
 661
 662                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 663                 if (ret)
 664                         break;
 665
 666                 addr = cookie_addr_high | inf.cookie;
 667                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 668         }
 669 }
 670
 671 /**
 672  * DPDK callback to stop the device.
 673  *
 674  * @param dev
 675  *   Pointer to Ethernet device structure.
 676  */
 677 static void
 678 mrvl_dev_stop(struct rte_eth_dev *dev)
 679 {
 680         struct mrvl_priv *priv = dev->data->dev_private;
 681
 682         mrvl_dev_set_link_down(dev);
 683         mrvl_flush_rx_queues(dev);
 684         mrvl_flush_tx_shadow_queues(dev);
 685         if (priv->qos_tbl) {
 686                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 687                 priv->qos_tbl = NULL;
 688         }
 689         pp2_ppio_deinit(priv->ppio);
 690         priv->ppio = NULL;
 691 }
 692
 693 /**
 694  * DPDK callback to close the device.
 695  *
 696  * @param dev
 697  *   Pointer to Ethernet device structure.
 698  */
 699 static void
 700 mrvl_dev_close(struct rte_eth_dev *dev)
 701 {
 702         struct mrvl_priv *priv = dev->data->dev_private;
 703         size_t i;
 704
 705         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 706                 struct pp2_ppio_tc_params *tc_params =
 707                         &priv->ppio_params.inqs_params.tcs_params[i];
 708
 709                 if (tc_params->inqs_params) {
 710                         rte_free(tc_params->inqs_params);
 711                         tc_params->inqs_params = NULL;
 712                 }
 713         }
 714
 715         mrvl_flush_bpool(dev);
 716 }
 717
 718 /**
 719  * DPDK callback to retrieve physical link information.
 720  *
 721  * @param dev
 722  *   Pointer to Ethernet device structure.
 723  * @param wait_to_complete
 724  *   Wait for request completion (ignored).
 725  *
 726  * @return
 727  *   0 on success, negative error value otherwise.
 728  */
 729 static int
 730 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 731 {
 732         /*
 733          * TODO
 734          * once MUSDK provides necessary API use it here
 735          */
 736         struct mrvl_priv *priv = dev->data->dev_private;
 737         struct ethtool_cmd edata;
 738         struct ifreq req;
 739         int ret, fd, link_up;
 740
 741         if (!priv->ppio)
 742                 return -EPERM;
 743
 744         edata.cmd = ETHTOOL_GSET;
 745
 746         strcpy(req.ifr_name, dev->data->name);
 747         req.ifr_data = (void *)&edata;
 748
 749         fd = socket(AF_INET, SOCK_DGRAM, 0);
 750         if (fd == -1)
 751                 return -EFAULT;
 752
 753         ret = ioctl(fd, SIOCETHTOOL, &req);
 754         if (ret == -1) {
 755                 close(fd);
 756                 return -EFAULT;
 757         }
 758
 759         close(fd);
 760
 761         switch (ethtool_cmd_speed(&edata)) {
 762         case SPEED_10:
 763                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 764                 break;
 765         case SPEED_100:
 766                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 767                 break;
 768         case SPEED_1000:
 769                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 770                 break;
 771         case SPEED_10000:
 772                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 773                 break;
 774         default:
 775                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 776         }
 777
 778         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 779                                                          ETH_LINK_HALF_DUPLEX;
 780         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 781                                                            ETH_LINK_FIXED;
 782         pp2_ppio_get_link_state(priv->ppio, &link_up);
 783         dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
 784
 785         return 0;
 786 }
 787
 788 /**
 789  * DPDK callback to enable promiscuous mode.
 790  *
 791  * @param dev
 792  *   Pointer to Ethernet device structure.
 793  */
 794 static void
 795 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 796 {
 797         struct mrvl_priv *priv = dev->data->dev_private;
 798         int ret;
 799
 800         if (!priv->ppio)
 801                 return;
 802
 803         ret = pp2_ppio_set_promisc(priv->ppio, 1);
 804         if (ret)
 805                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 806 }
 807
 808 /**
 809  * DPDK callback to enable allmulti mode.
 810  *
 811  * @param dev
 812  *   Pointer to Ethernet device structure.
 813  */
 814 static void
 815 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 816 {
 817         struct mrvl_priv *priv = dev->data->dev_private;
 818         int ret;
 819
 820         if (!priv->ppio)
 821                 return;
 822
 823         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 824         if (ret)
 825                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 826 }
 827
 828 /**
 829  * DPDK callback to disable promiscuous mode.
 830  *
 831  * @param dev
 832  *   Pointer to Ethernet device structure.
 833  */
 834 static void
 835 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 836 {
 837         struct mrvl_priv *priv = dev->data->dev_private;
 838         int ret;
 839
 840         if (!priv->ppio)
 841                 return;
 842
 843         ret = pp2_ppio_set_promisc(priv->ppio, 0);
 844         if (ret)
 845                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 846 }
 847
 848 /**
 849  * DPDK callback to disable allmulticast mode.
 850  *
 851  * @param dev
 852  *   Pointer to Ethernet device structure.
 853  */
 854 static void
 855 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 856 {
 857         struct mrvl_priv *priv = dev->data->dev_private;
 858         int ret;
 859
 860         if (!priv->ppio)
 861                 return;
 862
 863         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 864         if (ret)
 865                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 866 }
 867
 868 /**
 869  * DPDK callback to remove a MAC address.
 870  *
 871  * @param dev
 872  *   Pointer to Ethernet device structure.
 873  * @param index
 874  *   MAC address index.
 875  */
 876 static void
 877 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 878 {
 879         struct mrvl_priv *priv = dev->data->dev_private;
 880         char buf[ETHER_ADDR_FMT_SIZE];
 881         int ret;
 882
 883         if (!priv->ppio)
 884                 return;
 885
 886         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 887                                        dev->data->mac_addrs[index].addr_bytes);
 888         if (ret) {
 889                 ether_format_addr(buf, sizeof(buf),
 890                                   &dev->data->mac_addrs[index]);
 891                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 892         }
 893 }
 894
 895 /**
 896  * DPDK callback to add a MAC address.
 897  *
 898  * @param dev
 899  *   Pointer to Ethernet device structure.
 900  * @param mac_addr
 901  *   MAC address to register.
 902  * @param index
 903  *   MAC address index.
 904  * @param vmdq
 905  *   VMDq pool index to associate address with (unused).
 906  *
 907  * @return
 908  *   0 on success, negative error value otherwise.
 909  */
 910 static int
 911 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 912                   uint32_t index, uint32_t vmdq __rte_unused)
 913 {
 914         struct mrvl_priv *priv = dev->data->dev_private;
 915         char buf[ETHER_ADDR_FMT_SIZE];
 916         int ret;
 917
 918         if (index == 0)
 919                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 920                 return -1;
 921
 922         if (!priv->ppio)
 923                 return 0;
 924
 925         /*
 926          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 927          * parameter uc_filter_max. Maximum number of mc addresses is then
 928          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 929          * 21 respectively.
 930          *
 931          * If more than uc_filter_max uc addresses were added to filter list
 932          * then NIC will switch to promiscuous mode automatically.
 933          *
 934          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 935          * were added to filter list then NIC will switch to all-multicast mode
 936          * automatically.
 937          */
 938         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 939         if (ret) {
 940                 ether_format_addr(buf, sizeof(buf), mac_addr);
 941                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 942                 return -1;
 943         }
 944
 945         return 0;
 946 }
 947
 948 /**
 949  * DPDK callback to set the primary MAC address.
 950  *
 951  * @param dev
 952  *   Pointer to Ethernet device structure.
 953  * @param mac_addr
 954  *   MAC address to register.
 955  */
 956 static void
 957 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 958 {
 959         struct mrvl_priv *priv = dev->data->dev_private;
 960         int ret;
 961
 962         if (!priv->ppio)
 963                 return;
 964
 965         ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 966         if (ret) {
 967                 char buf[ETHER_ADDR_FMT_SIZE];
 968                 ether_format_addr(buf, sizeof(buf), mac_addr);
 969                 RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf);
 970         }
 971 }
 972
 973 /**
 974  * DPDK callback to get device statistics.
 975  *
 976  * @param dev
 977  *   Pointer to Ethernet device structure.
 978  * @param stats
 979  *   Stats structure output buffer.
 980  *
 981  * @return
 982  *   0 on success, negative error value otherwise.
 983  */
 984 static int
 985 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 986 {
 987         struct mrvl_priv *priv = dev->data->dev_private;
 988         struct pp2_ppio_statistics ppio_stats;
 989         uint64_t drop_mac = 0;
 990         unsigned int i, idx, ret;
 991
 992         if (!priv->ppio)
 993                 return -EPERM;
 994
 995         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 996                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 997                 struct pp2_ppio_inq_statistics rx_stats;
 998
 999                 if (!rxq)
1000                         continue;
1001
1002                 idx = rxq->queue_id;
1003                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1004                         RTE_LOG(ERR, PMD,
1005                                 "rx queue %d stats out of range (0 - %d)\n",
1006                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1007                         continue;
1008                 }
1009
1010                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
1011                                                   priv->rxq_map[idx].tc,
1012                                                   priv->rxq_map[idx].inq,
1013                                                   &rx_stats, 0);
1014                 if (unlikely(ret)) {
1015                         RTE_LOG(ERR, PMD,
1016                                 "Failed to update rx queue %d stats\n", idx);
1017                         break;
1018                 }
1019
1020                 stats->q_ibytes[idx] = rxq->bytes_recv;
1021                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
1022                 stats->q_errors[idx] = rx_stats.drop_early +
1023                                        rx_stats.drop_fullq +
1024                                        rx_stats.drop_bm +
1025                                        rxq->drop_mac;
1026                 stats->ibytes += rxq->bytes_recv;
1027                 drop_mac += rxq->drop_mac;
1028         }
1029
1030         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1031                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1032                 struct pp2_ppio_outq_statistics tx_stats;
1033
1034                 if (!txq)
1035                         continue;
1036
1037                 idx = txq->queue_id;
1038                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
1039                         RTE_LOG(ERR, PMD,
1040                                 "tx queue %d stats out of range (0 - %d)\n",
1041                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1042                 }
1043
1044                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1045                                                    &tx_stats, 0);
1046                 if (unlikely(ret)) {
1047                         RTE_LOG(ERR, PMD,
1048                                 "Failed to update tx queue %d stats\n", idx);
1049                         break;
1050                 }
1051
1052                 stats->q_opackets[idx] = tx_stats.deq_desc;
1053                 stats->q_obytes[idx] = txq->bytes_sent;
1054                 stats->obytes += txq->bytes_sent;
1055         }
1056
1057         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1058         if (unlikely(ret)) {
1059                 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1060                 return ret;
1061         }
1062
1063         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1064         stats->opackets += ppio_stats.tx_packets;
1065         stats->imissed += ppio_stats.rx_fullq_dropped +
1066                           ppio_stats.rx_bm_dropped +
1067                           ppio_stats.rx_early_dropped +
1068                           ppio_stats.rx_fifo_dropped +
1069                           ppio_stats.rx_cls_dropped;
1070         stats->ierrors = drop_mac;
1071
1072         return 0;
1073 }
1074
1075 /**
1076  * DPDK callback to clear device statistics.
1077  *
1078  * @param dev
1079  *   Pointer to Ethernet device structure.
1080  */
1081 static void
1082 mrvl_stats_reset(struct rte_eth_dev *dev)
1083 {
1084         struct mrvl_priv *priv = dev->data->dev_private;
1085         int i;
1086
1087         if (!priv->ppio)
1088                 return;
1089
1090         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1091                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1092
1093                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1094                                             priv->rxq_map[i].inq, NULL, 1);
1095                 rxq->bytes_recv = 0;
1096                 rxq->drop_mac = 0;
1097         }
1098
1099         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1100                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1101
1102                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1103                 txq->bytes_sent = 0;
1104         }
1105
1106         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1107 }
1108
1109 /**
1110  * DPDK callback to get information about the device.
1111  *
1112  * @param dev
1113  *   Pointer to Ethernet device structure (unused).
1114  * @param info
1115  *   Info structure output buffer.
1116  */
1117 static void
1118 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1119                    struct rte_eth_dev_info *info)
1120 {
1121         info->speed_capa = ETH_LINK_SPEED_10M |
1122                            ETH_LINK_SPEED_100M |
1123                            ETH_LINK_SPEED_1G |
1124                            ETH_LINK_SPEED_10G;
1125
1126         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1127         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1128         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1129
1130         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1131         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1132         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1133
1134         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1135         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1136         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1137
1138         info->rx_offload_capa = MRVL_RX_OFFLOADS;
1139         info->rx_queue_offload_capa = MRVL_RX_OFFLOADS;
1140
1141         info->tx_offload_capa = MRVL_TX_OFFLOADS;
1142         info->tx_queue_offload_capa = MRVL_TX_OFFLOADS;
1143
1144         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1145                                        ETH_RSS_NONFRAG_IPV4_TCP |
1146                                        ETH_RSS_NONFRAG_IPV4_UDP;
1147
1148         /* By default packets are dropped if no descriptors are available */
1149         info->default_rxconf.rx_drop_en = 1;
1150         info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP;
1151
1152         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1153 }
1154
1155 /**
1156  * Return supported packet types.
1157  *
1158  * @param dev
1159  *   Pointer to Ethernet device structure (unused).
1160  *
1161  * @return
1162  *   Const pointer to the table with supported packet types.
1163  */
1164 static const uint32_t *
1165 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1166 {
1167         static const uint32_t ptypes[] = {
1168                 RTE_PTYPE_L2_ETHER,
1169                 RTE_PTYPE_L3_IPV4,
1170                 RTE_PTYPE_L3_IPV4_EXT,
1171                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1172                 RTE_PTYPE_L3_IPV6,
1173                 RTE_PTYPE_L3_IPV6_EXT,
1174                 RTE_PTYPE_L2_ETHER_ARP,
1175                 RTE_PTYPE_L4_TCP,
1176                 RTE_PTYPE_L4_UDP
1177         };
1178
1179         return ptypes;
1180 }
1181
1182 /**
1183  * DPDK callback to get information about specific receive queue.
1184  *
1185  * @param dev
1186  *   Pointer to Ethernet device structure.
1187  * @param rx_queue_id
1188  *   Receive queue index.
1189  * @param qinfo
1190  *   Receive queue information structure.
1191  */
1192 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1193                               struct rte_eth_rxq_info *qinfo)
1194 {
1195         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1196         struct mrvl_priv *priv = dev->data->dev_private;
1197         int inq = priv->rxq_map[rx_queue_id].inq;
1198         int tc = priv->rxq_map[rx_queue_id].tc;
1199         struct pp2_ppio_tc_params *tc_params =
1200                 &priv->ppio_params.inqs_params.tcs_params[tc];
1201
1202         qinfo->mp = q->mp;
1203         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1204 }
1205
1206 /**
1207  * DPDK callback to get information about specific transmit queue.
1208  *
1209  * @param dev
1210  *   Pointer to Ethernet device structure.
1211  * @param tx_queue_id
1212  *   Transmit queue index.
1213  * @param qinfo
1214  *   Transmit queue information structure.
1215  */
1216 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1217                               struct rte_eth_txq_info *qinfo)
1218 {
1219         struct mrvl_priv *priv = dev->data->dev_private;
1220
1221         qinfo->nb_desc =
1222                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1223 }
1224
1225 /**
1226  * DPDK callback to Configure a VLAN filter.
1227  *
1228  * @param dev
1229  *   Pointer to Ethernet device structure.
1230  * @param vlan_id
1231  *   VLAN ID to filter.
1232  * @param on
1233  *   Toggle filter.
1234  *
1235  * @return
1236  *   0 on success, negative error value otherwise.
1237  */
1238 static int
1239 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1240 {
1241         struct mrvl_priv *priv = dev->data->dev_private;
1242
1243         if (!priv->ppio)
1244                 return -EPERM;
1245
1246         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1247                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1248 }
1249
1250 /**
1251  * Release buffers to hardware bpool (buffer-pool)
1252  *
1253  * @param rxq
1254  *   Receive queue pointer.
1255  * @param num
1256  *   Number of buffers to release to bpool.
1257  *
1258  * @return
1259  *   0 on success, negative error value otherwise.
1260  */
1261 static int
1262 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1263 {
1264         struct buff_release_entry entries[MRVL_PP2_TXD_MAX];
1265         struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX];
1266         int i, ret;
1267         unsigned int core_id;
1268         struct pp2_hif *hif;
1269         struct pp2_bpool *bpool;
1270
1271         core_id = rte_lcore_id();
1272         if (core_id == LCORE_ID_ANY)
1273                 core_id = 0;
1274
1275         hif = mrvl_get_hif(rxq->priv, core_id);
1276         if (!hif)
1277                 return -1;
1278
1279         bpool = rxq->priv->bpool;
1280
1281         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1282         if (ret)
1283                 return ret;
1284
1285         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1286                 cookie_addr_high =
1287                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1288
1289         for (i = 0; i < num; i++) {
1290                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1291                         != cookie_addr_high) {
1292                         RTE_LOG(ERR, PMD,
1293                                 "mbuf virtual addr high 0x%lx out of range\n",
1294                                 (uint64_t)mbufs[i] >> 32);
1295                         goto out;
1296                 }
1297
1298                 entries[i].buff.addr =
1299                         rte_mbuf_data_iova_default(mbufs[i]);
1300                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1301                 entries[i].bpool = bpool;
1302         }
1303
1304         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1305         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1306
1307         if (i != num)
1308                 goto out;
1309
1310         return 0;
1311 out:
1312         for (; i < num; i++)
1313                 rte_pktmbuf_free(mbufs[i]);
1314
1315         return -1;
1316 }
1317
1318 /**
1319  * Check whether requested rx queue offloads match port offloads.
1320  *
1321  * @param
1322  *   dev Pointer to the device.
1323  * @param
1324  *   requested Bitmap of the requested offloads.
1325  *
1326  * @return
1327  *   1 if requested offloads are okay, 0 otherwise.
1328  */
1329 static int
1330 mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1331 {
1332         uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1333         uint64_t supported = MRVL_RX_OFFLOADS;
1334         uint64_t unsupported = requested & ~supported;
1335         uint64_t missing = mandatory & ~requested;
1336
1337         if (unsupported) {
1338                 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1339                         "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1340                         requested, supported);
1341                 return 0;
1342         }
1343
1344         if (missing) {
1345                 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1346                         "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1347                         requested, missing);
1348                 return 0;
1349         }
1350
1351         return 1;
1352 }
1353
1354 /**
1355  * DPDK callback to configure the receive queue.
1356  *
1357  * @param dev
1358  *   Pointer to Ethernet device structure.
1359  * @param idx
1360  *   RX queue index.
1361  * @param desc
1362  *   Number of descriptors to configure in queue.
1363  * @param socket
1364  *   NUMA socket on which memory must be allocated.
1365  * @param conf
1366  *   Thresholds parameters.
1367  * @param mp
1368  *   Memory pool for buffer allocations.
1369  *
1370  * @return
1371  *   0 on success, negative error value otherwise.
1372  */
1373 static int
1374 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1375                     unsigned int socket,
1376                     const struct rte_eth_rxconf *conf,
1377                     struct rte_mempool *mp)
1378 {
1379         struct mrvl_priv *priv = dev->data->dev_private;
1380         struct mrvl_rxq *rxq;
1381         uint32_t min_size,
1382                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1383         int ret, tc, inq;
1384
1385         if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads))
1386                 return -ENOTSUP;
1387
1388         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1389                 /*
1390                  * Unknown TC mapping, mapping will not have a correct queue.
1391                  */
1392                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1393                         idx, priv->ppio_id);
1394                 return -EFAULT;
1395         }
1396
1397         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1398                    MRVL_PKT_EFFEC_OFFS;
1399         if (min_size < max_rx_pkt_len) {
1400                 RTE_LOG(ERR, PMD,
1401                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1402                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1403                         MRVL_PKT_EFFEC_OFFS,
1404                         max_rx_pkt_len);
1405                 return -EINVAL;
1406         }
1407
1408         if (dev->data->rx_queues[idx]) {
1409                 rte_free(dev->data->rx_queues[idx]);
1410                 dev->data->rx_queues[idx] = NULL;
1411         }
1412
1413         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1414         if (!rxq)
1415                 return -ENOMEM;
1416
1417         rxq->priv = priv;
1418         rxq->mp = mp;
1419         rxq->cksum_enabled =
1420                 dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM;
1421         rxq->queue_id = idx;
1422         rxq->port_id = dev->data->port_id;
1423         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1424
1425         tc = priv->rxq_map[rxq->queue_id].tc,
1426         inq = priv->rxq_map[rxq->queue_id].inq;
1427         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1428                 desc;
1429
1430         ret = mrvl_fill_bpool(rxq, desc);
1431         if (ret) {
1432                 rte_free(rxq);
1433                 return ret;
1434         }
1435
1436         priv->bpool_init_size += desc;
1437
1438         dev->data->rx_queues[idx] = rxq;
1439
1440         return 0;
1441 }
1442
1443 /**
1444  * DPDK callback to release the receive queue.
1445  *
1446  * @param rxq
1447  *   Generic receive queue pointer.
1448  */
1449 static void
1450 mrvl_rx_queue_release(void *rxq)
1451 {
1452         struct mrvl_rxq *q = rxq;
1453         struct pp2_ppio_tc_params *tc_params;
1454         int i, num, tc, inq;
1455         struct pp2_hif *hif;
1456         unsigned int core_id = rte_lcore_id();
1457
1458         if (core_id == LCORE_ID_ANY)
1459                 core_id = 0;
1460
1461         hif = mrvl_get_hif(q->priv, core_id);
1462
1463         if (!q || !hif)
1464                 return;
1465
1466         tc = q->priv->rxq_map[q->queue_id].tc;
1467         inq = q->priv->rxq_map[q->queue_id].inq;
1468         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1469         num = tc_params->inqs_params[inq].size;
1470         for (i = 0; i < num; i++) {
1471                 struct pp2_buff_inf inf;
1472                 uint64_t addr;
1473
1474                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1475                 addr = cookie_addr_high | inf.cookie;
1476                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1477         }
1478
1479         rte_free(q);
1480 }
1481
1482 /**
1483  * Check whether requested tx queue offloads match port offloads.
1484  *
1485  * @param
1486  *   dev Pointer to the device.
1487  * @param
1488  *   requested Bitmap of the requested offloads.
1489  *
1490  * @return
1491  *   1 if requested offloads are okay, 0 otherwise.
1492  */
1493 static int
1494 mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested)
1495 {
1496         uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
1497         uint64_t supported = MRVL_TX_OFFLOADS;
1498         uint64_t unsupported = requested & ~supported;
1499         uint64_t missing = mandatory & ~requested;
1500
1501         if (unsupported) {
1502                 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. "
1503                         "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n",
1504                         requested, supported);
1505                 return 0;
1506         }
1507
1508         if (missing) {
1509                 RTE_LOG(ERR, PMD, "Some Rx offloads are missing. "
1510                         "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n",
1511                         requested, missing);
1512                 return 0;
1513         }
1514
1515         return 1;
1516 }
1517
1518 /**
1519  * DPDK callback to configure the transmit queue.
1520  *
1521  * @param dev
1522  *   Pointer to Ethernet device structure.
1523  * @param idx
1524  *   Transmit queue index.
1525  * @param desc
1526  *   Number of descriptors to configure in the queue.
1527  * @param socket
1528  *   NUMA socket on which memory must be allocated.
1529  * @param conf
1530  *   Thresholds parameters.
1531  *
1532  * @return
1533  *   0 on success, negative error value otherwise.
1534  */
1535 static int
1536 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1537                     unsigned int socket,
1538                     const struct rte_eth_txconf *conf)
1539 {
1540         struct mrvl_priv *priv = dev->data->dev_private;
1541         struct mrvl_txq *txq;
1542
1543         if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads))
1544                 return -ENOTSUP;
1545
1546         if (dev->data->tx_queues[idx]) {
1547                 rte_free(dev->data->tx_queues[idx]);
1548                 dev->data->tx_queues[idx] = NULL;
1549         }
1550
1551         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1552         if (!txq)
1553                 return -ENOMEM;
1554
1555         txq->priv = priv;
1556         txq->queue_id = idx;
1557         txq->port_id = dev->data->port_id;
1558         dev->data->tx_queues[idx] = txq;
1559
1560         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1561         priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1562
1563         return 0;
1564 }
1565
1566 /**
1567  * DPDK callback to release the transmit queue.
1568  *
1569  * @param txq
1570  *   Generic transmit queue pointer.
1571  */
1572 static void
1573 mrvl_tx_queue_release(void *txq)
1574 {
1575         struct mrvl_txq *q = txq;
1576
1577         if (!q)
1578                 return;
1579
1580         rte_free(q);
1581 }
1582
1583 /**
1584  * Update RSS hash configuration
1585  *
1586  * @param dev
1587  *   Pointer to Ethernet device structure.
1588  * @param rss_conf
1589  *   Pointer to RSS configuration.
1590  *
1591  * @return
1592  *   0 on success, negative error value otherwise.
1593  */
1594 static int
1595 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1596                      struct rte_eth_rss_conf *rss_conf)
1597 {
1598         struct mrvl_priv *priv = dev->data->dev_private;
1599
1600         return mrvl_configure_rss(priv, rss_conf);
1601 }
1602
1603 /**
1604  * DPDK callback to get RSS hash configuration.
1605  *
1606  * @param dev
1607  *   Pointer to Ethernet device structure.
1608  * @rss_conf
1609  *   Pointer to RSS configuration.
1610  *
1611  * @return
1612  *   Always 0.
1613  */
1614 static int
1615 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1616                        struct rte_eth_rss_conf *rss_conf)
1617 {
1618         struct mrvl_priv *priv = dev->data->dev_private;
1619         enum pp2_ppio_hash_type hash_type =
1620                 priv->ppio_params.inqs_params.hash_type;
1621
1622         rss_conf->rss_key = NULL;
1623
1624         if (hash_type == PP2_PPIO_HASH_T_NONE)
1625                 rss_conf->rss_hf = 0;
1626         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1627                 rss_conf->rss_hf = ETH_RSS_IPV4;
1628         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1629                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1630         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1631                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1632
1633         return 0;
1634 }
1635
1636 static const struct eth_dev_ops mrvl_ops = {
1637         .dev_configure = mrvl_dev_configure,
1638         .dev_start = mrvl_dev_start,
1639         .dev_stop = mrvl_dev_stop,
1640         .dev_set_link_up = mrvl_dev_set_link_up,
1641         .dev_set_link_down = mrvl_dev_set_link_down,
1642         .dev_close = mrvl_dev_close,
1643         .link_update = mrvl_link_update,
1644         .promiscuous_enable = mrvl_promiscuous_enable,
1645         .allmulticast_enable = mrvl_allmulticast_enable,
1646         .promiscuous_disable = mrvl_promiscuous_disable,
1647         .allmulticast_disable = mrvl_allmulticast_disable,
1648         .mac_addr_remove = mrvl_mac_addr_remove,
1649         .mac_addr_add = mrvl_mac_addr_add,
1650         .mac_addr_set = mrvl_mac_addr_set,
1651         .mtu_set = mrvl_mtu_set,
1652         .stats_get = mrvl_stats_get,
1653         .stats_reset = mrvl_stats_reset,
1654         .dev_infos_get = mrvl_dev_infos_get,
1655         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1656         .rxq_info_get = mrvl_rxq_info_get,
1657         .txq_info_get = mrvl_txq_info_get,
1658         .vlan_filter_set = mrvl_vlan_filter_set,
1659         .rx_queue_setup = mrvl_rx_queue_setup,
1660         .rx_queue_release = mrvl_rx_queue_release,
1661         .tx_queue_setup = mrvl_tx_queue_setup,
1662         .tx_queue_release = mrvl_tx_queue_release,
1663         .rss_hash_update = mrvl_rss_hash_update,
1664         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1665 };
1666
1667 /**
1668  * Return packet type information and l3/l4 offsets.
1669  *
1670  * @param desc
1671  *   Pointer to the received packet descriptor.
1672  * @param l3_offset
1673  *   l3 packet offset.
1674  * @param l4_offset
1675  *   l4 packet offset.
1676  *
1677  * @return
1678  *   Packet type information.
1679  */
1680 static inline uint64_t
1681 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1682                                     uint8_t *l3_offset, uint8_t *l4_offset)
1683 {
1684         enum pp2_inq_l3_type l3_type;
1685         enum pp2_inq_l4_type l4_type;
1686         uint64_t packet_type;
1687
1688         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1689         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1690
1691         packet_type = RTE_PTYPE_L2_ETHER;
1692
1693         switch (l3_type) {
1694         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1695                 packet_type |= RTE_PTYPE_L3_IPV4;
1696                 break;
1697         case PP2_INQ_L3_TYPE_IPV4_OK:
1698                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1699                 break;
1700         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1701                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1702                 break;
1703         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1704                 packet_type |= RTE_PTYPE_L3_IPV6;
1705                 break;
1706         case PP2_INQ_L3_TYPE_IPV6_EXT:
1707                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1708                 break;
1709         case PP2_INQ_L3_TYPE_ARP:
1710                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1711                 /*
1712                  * In case of ARP l4_offset is set to wrong value.
1713                  * Set it to proper one so that later on mbuf->l3_len can be
1714                  * calculated subtracting l4_offset and l3_offset.
1715                  */
1716                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1717                 break;
1718         default:
1719                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1720                 break;
1721         }
1722
1723         switch (l4_type) {
1724         case PP2_INQ_L4_TYPE_TCP:
1725                 packet_type |= RTE_PTYPE_L4_TCP;
1726                 break;
1727         case PP2_INQ_L4_TYPE_UDP:
1728                 packet_type |= RTE_PTYPE_L4_UDP;
1729                 break;
1730         default:
1731                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1732                 break;
1733         }
1734
1735         return packet_type;
1736 }
1737
1738 /**
1739  * Get offload information from the received packet descriptor.
1740  *
1741  * @param desc
1742  *   Pointer to the received packet descriptor.
1743  *
1744  * @return
1745  *   Mbuf offload flags.
1746  */
1747 static inline uint64_t
1748 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1749 {
1750         uint64_t flags;
1751         enum pp2_inq_desc_status status;
1752
1753         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1754         if (unlikely(status != PP2_DESC_ERR_OK))
1755                 flags = PKT_RX_IP_CKSUM_BAD;
1756         else
1757                 flags = PKT_RX_IP_CKSUM_GOOD;
1758
1759         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1760         if (unlikely(status != PP2_DESC_ERR_OK))
1761                 flags |= PKT_RX_L4_CKSUM_BAD;
1762         else
1763                 flags |= PKT_RX_L4_CKSUM_GOOD;
1764
1765         return flags;
1766 }
1767
1768 /**
1769  * DPDK callback for receive.
1770  *
1771  * @param rxq
1772  *   Generic pointer to the receive queue.
1773  * @param rx_pkts
1774  *   Array to store received packets.
1775  * @param nb_pkts
1776  *   Maximum number of packets in array.
1777  *
1778  * @return
1779  *   Number of packets successfully received.
1780  */
1781 static uint16_t
1782 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1783 {
1784         struct mrvl_rxq *q = rxq;
1785         struct pp2_ppio_desc descs[nb_pkts];
1786         struct pp2_bpool *bpool;
1787         int i, ret, rx_done = 0;
1788         int num;
1789         struct pp2_hif *hif;
1790         unsigned int core_id = rte_lcore_id();
1791
1792         hif = mrvl_get_hif(q->priv, core_id);
1793
1794         if (unlikely(!q->priv->ppio || !hif))
1795                 return 0;
1796
1797         bpool = q->priv->bpool;
1798
1799         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1800                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1801         if (unlikely(ret < 0)) {
1802                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1803                 return 0;
1804         }
1805         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1806
1807         for (i = 0; i < nb_pkts; i++) {
1808                 struct rte_mbuf *mbuf;
1809                 uint8_t l3_offset, l4_offset;
1810                 enum pp2_inq_desc_status status;
1811                 uint64_t addr;
1812
1813                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1814                         struct pp2_ppio_desc *pref_desc;
1815                         u64 pref_addr;
1816
1817                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1818                         pref_addr = cookie_addr_high |
1819                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1820                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1821                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1822                 }
1823
1824                 addr = cookie_addr_high |
1825                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1826                 mbuf = (struct rte_mbuf *)addr;
1827                 rte_pktmbuf_reset(mbuf);
1828
1829                 /* drop packet in case of mac, overrun or resource error */
1830                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1831                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1832                         struct pp2_buff_inf binf = {
1833                                 .addr = rte_mbuf_data_iova_default(mbuf),
1834                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1835                         };
1836
1837                         pp2_bpool_put_buff(hif, bpool, &binf);
1838                         mrvl_port_bpool_size
1839                                 [bpool->pp2_id][bpool->id][core_id]++;
1840                         q->drop_mac++;
1841                         continue;
1842                 }
1843
1844                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1845                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1846                 mbuf->data_len = mbuf->pkt_len;
1847                 mbuf->port = q->port_id;
1848                 mbuf->packet_type =
1849                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1850                                                             &l3_offset,
1851                                                             &l4_offset);
1852                 mbuf->l2_len = l3_offset;
1853                 mbuf->l3_len = l4_offset - l3_offset;
1854
1855                 if (likely(q->cksum_enabled))
1856                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1857
1858                 rx_pkts[rx_done++] = mbuf;
1859                 q->bytes_recv += mbuf->pkt_len;
1860         }
1861
1862         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1863                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1864
1865                 if (unlikely(num <= q->priv->bpool_min_size ||
1866                              (!rx_done && num < q->priv->bpool_init_size))) {
1867                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1868                         if (ret)
1869                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1870                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1871                         int i;
1872                         int pkt_to_remove = num - q->priv->bpool_init_size;
1873                         struct rte_mbuf *mbuf;
1874                         struct pp2_buff_inf buff;
1875
1876                         RTE_LOG(DEBUG, PMD,
1877                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1878                                 bpool->pp2_id, q->priv->ppio->port_id,
1879                                 bpool->id, pkt_to_remove, num,
1880                                 q->priv->bpool_init_size);
1881
1882                         for (i = 0; i < pkt_to_remove; i++) {
1883                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1884                                 if (ret)
1885                                         break;
1886                                 mbuf = (struct rte_mbuf *)
1887                                         (cookie_addr_high | buff.cookie);
1888                                 rte_pktmbuf_free(mbuf);
1889                         }
1890                         mrvl_port_bpool_size
1891                                 [bpool->pp2_id][bpool->id][core_id] -= i;
1892                 }
1893                 rte_spinlock_unlock(&q->priv->lock);
1894         }
1895
1896         return rx_done;
1897 }
1898
1899 /**
1900  * Prepare offload information.
1901  *
1902  * @param ol_flags
1903  *   Offload flags.
1904  * @param packet_type
1905  *   Packet type bitfield.
1906  * @param l3_type
1907  *   Pointer to the pp2_ouq_l3_type structure.
1908  * @param l4_type
1909  *   Pointer to the pp2_outq_l4_type structure.
1910  * @param gen_l3_cksum
1911  *   Will be set to 1 in case l3 checksum is computed.
1912  * @param l4_cksum
1913  *   Will be set to 1 in case l4 checksum is computed.
1914  *
1915  * @return
1916  *   0 on success, negative error value otherwise.
1917  */
1918 static inline int
1919 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1920                         enum pp2_outq_l3_type *l3_type,
1921                         enum pp2_outq_l4_type *l4_type,
1922                         int *gen_l3_cksum,
1923                         int *gen_l4_cksum)
1924 {
1925         /*
1926          * Based on ol_flags prepare information
1927          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1928          * for offloading.
1929          */
1930         if (ol_flags & PKT_TX_IPV4) {
1931                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1932                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1933         } else if (ol_flags & PKT_TX_IPV6) {
1934                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1935                 /* no checksum for ipv6 header */
1936                 *gen_l3_cksum = 0;
1937         } else {
1938                 /* if something different then stop processing */
1939                 return -1;
1940         }
1941
1942         ol_flags &= PKT_TX_L4_MASK;
1943         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1944             ol_flags == PKT_TX_TCP_CKSUM) {
1945                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1946                 *gen_l4_cksum = 1;
1947         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1948                    ol_flags == PKT_TX_UDP_CKSUM) {
1949                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1950                 *gen_l4_cksum = 1;
1951         } else {
1952                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1953                 /* no checksum for other type */
1954                 *gen_l4_cksum = 0;
1955         }
1956
1957         return 0;
1958 }
1959
1960 /**
1961  * Release already sent buffers to bpool (buffer-pool).
1962  *
1963  * @param ppio
1964  *   Pointer to the port structure.
1965  * @param hif
1966  *   Pointer to the MUSDK hardware interface.
1967  * @param sq
1968  *   Pointer to the shadow queue.
1969  * @param qid
1970  *   Queue id number.
1971  * @param force
1972  *   Force releasing packets.
1973  */
1974 static inline void
1975 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1976                        unsigned int core_id, struct mrvl_shadow_txq *sq,
1977                        int qid, int force)
1978 {
1979         struct buff_release_entry *entry;
1980         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1981         int i;
1982
1983         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1984
1985         sq->num_to_release += nb_done;
1986
1987         if (likely(!force &&
1988                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1989                 return;
1990
1991         nb_done = sq->num_to_release;
1992         sq->num_to_release = 0;
1993
1994         for (i = 0; i < nb_done; i++) {
1995                 entry = &sq->ent[sq->tail + num];
1996                 if (unlikely(!entry->buff.addr)) {
1997                         RTE_LOG(ERR, PMD,
1998                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1999                                 sq->tail, (u64)entry->buff.cookie,
2000                                 (u64)entry->buff.addr);
2001                         skip_bufs = 1;
2002                         goto skip;
2003                 }
2004
2005                 if (unlikely(!entry->bpool)) {
2006                         struct rte_mbuf *mbuf;
2007
2008                         mbuf = (struct rte_mbuf *)
2009                                (cookie_addr_high | entry->buff.cookie);
2010                         rte_pktmbuf_free(mbuf);
2011                         skip_bufs = 1;
2012                         goto skip;
2013                 }
2014
2015                 mrvl_port_bpool_size
2016                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
2017                 num++;
2018                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
2019                         goto skip;
2020                 continue;
2021 skip:
2022                 if (likely(num))
2023                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2024                 num += skip_bufs;
2025                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2026                 sq->size -= num;
2027                 num = 0;
2028                 skip_bufs = 0;
2029         }
2030
2031         if (likely(num)) {
2032                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
2033                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
2034                 sq->size -= num;
2035         }
2036 }
2037
2038 /**
2039  * DPDK callback for transmit.
2040  *
2041  * @param txq
2042  *   Generic pointer transmit queue.
2043  * @param tx_pkts
2044  *   Packets to transmit.
2045  * @param nb_pkts
2046  *   Number of packets in array.
2047  *
2048  * @return
2049  *   Number of packets successfully transmitted.
2050  */
2051 static uint16_t
2052 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2053 {
2054         struct mrvl_txq *q = txq;
2055         struct mrvl_shadow_txq *sq;
2056         struct pp2_hif *hif;
2057         struct pp2_ppio_desc descs[nb_pkts];
2058         unsigned int core_id = rte_lcore_id();
2059         int i, ret, bytes_sent = 0;
2060         uint16_t num, sq_free_size;
2061         uint64_t addr;
2062
2063         hif = mrvl_get_hif(q->priv, core_id);
2064         sq = &q->shadow_txqs[core_id];
2065
2066         if (unlikely(!q->priv->ppio || !hif))
2067                 return 0;
2068
2069         if (sq->size)
2070                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
2071                                        sq, q->queue_id, 0);
2072
2073         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
2074         if (unlikely(nb_pkts > sq_free_size)) {
2075                 RTE_LOG(DEBUG, PMD,
2076                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
2077                         nb_pkts, sq_free_size);
2078                 nb_pkts = sq_free_size;
2079         }
2080
2081         for (i = 0; i < nb_pkts; i++) {
2082                 struct rte_mbuf *mbuf = tx_pkts[i];
2083                 int gen_l3_cksum, gen_l4_cksum;
2084                 enum pp2_outq_l3_type l3_type;
2085                 enum pp2_outq_l4_type l4_type;
2086
2087                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
2088                         struct rte_mbuf *pref_pkt_hdr;
2089
2090                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
2091                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
2092                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
2093                 }
2094
2095                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
2096                 sq->ent[sq->head].buff.addr =
2097                         rte_mbuf_data_iova_default(mbuf);
2098                 sq->ent[sq->head].bpool =
2099                         (unlikely(mbuf->port >= RTE_MAX_ETHPORTS ||
2100                          mbuf->refcnt > 1)) ? NULL :
2101                          mrvl_port_to_bpool_lookup[mbuf->port];
2102                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
2103                 sq->size++;
2104
2105                 pp2_ppio_outq_desc_reset(&descs[i]);
2106                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
2107                                                  rte_pktmbuf_iova(mbuf));
2108                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
2109                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
2110                                                rte_pktmbuf_pkt_len(mbuf));
2111
2112                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
2113                 /*
2114                  * in case unsupported ol_flags were passed
2115                  * do not update descriptor offload information
2116                  */
2117                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
2118                                               &l3_type, &l4_type, &gen_l3_cksum,
2119                                               &gen_l4_cksum);
2120                 if (unlikely(ret))
2121                         continue;
2122
2123                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2124                                                   mbuf->l2_len,
2125                                                   mbuf->l2_len + mbuf->l3_len,
2126                                                   gen_l3_cksum, gen_l4_cksum);
2127         }
2128
2129         num = nb_pkts;
2130         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2131         /* number of packets that were not sent */
2132         if (unlikely(num > nb_pkts)) {
2133                 for (i = nb_pkts; i < num; i++) {
2134                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2135                                 MRVL_PP2_TX_SHADOWQ_MASK;
2136                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2137                         bytes_sent -=
2138                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2139                 }
2140                 sq->size -= num - nb_pkts;
2141         }
2142
2143         q->bytes_sent += bytes_sent;
2144
2145         return nb_pkts;
2146 }
2147
2148 /**
2149  * Initialize packet processor.
2150  *
2151  * @return
2152  *   0 on success, negative error value otherwise.
2153  */
2154 static int
2155 mrvl_init_pp2(void)
2156 {
2157         struct pp2_init_params init_params;
2158
2159         memset(&init_params, 0, sizeof(init_params));
2160         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2161         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2162         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2163
2164         return pp2_init(&init_params);
2165 }
2166
2167 /**
2168  * Deinitialize packet processor.
2169  *
2170  * @return
2171  *   0 on success, negative error value otherwise.
2172  */
2173 static void
2174 mrvl_deinit_pp2(void)
2175 {
2176         pp2_deinit();
2177 }
2178
2179 /**
2180  * Create private device structure.
2181  *
2182  * @param dev_name
2183  *   Pointer to the port name passed in the initialization parameters.
2184  *
2185  * @return
2186  *   Pointer to the newly allocated private device structure.
2187  */
2188 static struct mrvl_priv *
2189 mrvl_priv_create(const char *dev_name)
2190 {
2191         struct pp2_bpool_params bpool_params;
2192         char match[MRVL_MATCH_LEN];
2193         struct mrvl_priv *priv;
2194         int ret, bpool_bit;
2195
2196         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2197         if (!priv)
2198                 return NULL;
2199
2200         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2201                                        &priv->pp_id, &priv->ppio_id);
2202         if (ret)
2203                 goto out_free_priv;
2204
2205         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2206                                      PP2_BPOOL_NUM_POOLS);
2207         if (bpool_bit < 0)
2208                 goto out_free_priv;
2209         priv->bpool_bit = bpool_bit;
2210
2211         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2212                  priv->bpool_bit);
2213         memset(&bpool_params, 0, sizeof(bpool_params));
2214         bpool_params.match = match;
2215         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2216         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2217         if (ret)
2218                 goto out_clear_bpool_bit;
2219
2220         priv->ppio_params.type = PP2_PPIO_T_NIC;
2221         rte_spinlock_init(&priv->lock);
2222
2223         return priv;
2224 out_clear_bpool_bit:
2225         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2226 out_free_priv:
2227         rte_free(priv);
2228         return NULL;
2229 }
2230
2231 /**
2232  * Create device representing Ethernet port.
2233  *
2234  * @param name
2235  *   Pointer to the port's name.
2236  *
2237  * @return
2238  *   0 on success, negative error value otherwise.
2239  */
2240 static int
2241 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2242 {
2243         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2244         struct rte_eth_dev *eth_dev;
2245         struct mrvl_priv *priv;
2246         struct ifreq req;
2247
2248         eth_dev = rte_eth_dev_allocate(name);
2249         if (!eth_dev)
2250                 return -ENOMEM;
2251
2252         priv = mrvl_priv_create(name);
2253         if (!priv) {
2254                 ret = -ENOMEM;
2255                 goto out_free_dev;
2256         }
2257
2258         eth_dev->data->mac_addrs =
2259                 rte_zmalloc("mac_addrs",
2260                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2261         if (!eth_dev->data->mac_addrs) {
2262                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2263                 ret = -ENOMEM;
2264                 goto out_free_priv;
2265         }
2266
2267         memset(&req, 0, sizeof(req));
2268         strcpy(req.ifr_name, name);
2269         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2270         if (ret)
2271                 goto out_free_mac;
2272
2273         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2274                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2275
2276         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2277         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2278         eth_dev->data->kdrv = RTE_KDRV_NONE;
2279         eth_dev->data->dev_private = priv;
2280         eth_dev->device = &vdev->device;
2281         eth_dev->dev_ops = &mrvl_ops;
2282
2283         return 0;
2284 out_free_mac:
2285         rte_free(eth_dev->data->mac_addrs);
2286 out_free_dev:
2287         rte_eth_dev_release_port(eth_dev);
2288 out_free_priv:
2289         rte_free(priv);
2290
2291         return ret;
2292 }
2293
2294 /**
2295  * Cleanup previously created device representing Ethernet port.
2296  *
2297  * @param name
2298  *   Pointer to the port name.
2299  */
2300 static void
2301 mrvl_eth_dev_destroy(const char *name)
2302 {
2303         struct rte_eth_dev *eth_dev;
2304         struct mrvl_priv *priv;
2305
2306         eth_dev = rte_eth_dev_allocated(name);
2307         if (!eth_dev)
2308                 return;
2309
2310         priv = eth_dev->data->dev_private;
2311         pp2_bpool_deinit(priv->bpool);
2312         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2313         rte_free(priv);
2314         rte_free(eth_dev->data->mac_addrs);
2315         rte_eth_dev_release_port(eth_dev);
2316 }
2317
2318 /**
2319  * Callback used by rte_kvargs_process() during argument parsing.
2320  *
2321  * @param key
2322  *   Pointer to the parsed key (unused).
2323  * @param value
2324  *   Pointer to the parsed value.
2325  * @param extra_args
2326  *   Pointer to the extra arguments which contains address of the
2327  *   table of pointers to parsed interface names.
2328  *
2329  * @return
2330  *   Always 0.
2331  */
2332 static int
2333 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2334                  void *extra_args)
2335 {
2336         struct mrvl_ifnames *ifnames = extra_args;
2337
2338         ifnames->names[ifnames->idx++] = value;
2339
2340         return 0;
2341 }
2342
2343 /**
2344  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2345  */
2346 static void
2347 mrvl_deinit_hifs(void)
2348 {
2349         int i;
2350
2351         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2352                 if (hifs[i])
2353                         pp2_hif_deinit(hifs[i]);
2354         }
2355         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2356         memset(hifs, 0, sizeof(hifs));
2357 }
2358
2359 /**
2360  * DPDK callback to register the virtual device.
2361  *
2362  * @param vdev
2363  *   Pointer to the virtual device.
2364  *
2365  * @return
2366  *   0 on success, negative error value otherwise.
2367  */
2368 static int
2369 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2370 {
2371         struct rte_kvargs *kvlist;
2372         struct mrvl_ifnames ifnames;
2373         int ret = -EINVAL;
2374         uint32_t i, ifnum, cfgnum;
2375         const char *params;
2376
2377         params = rte_vdev_device_args(vdev);
2378         if (!params)
2379                 return -EINVAL;
2380
2381         kvlist = rte_kvargs_parse(params, valid_args);
2382         if (!kvlist)
2383                 return -EINVAL;
2384
2385         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2386         if (ifnum > RTE_DIM(ifnames.names))
2387                 goto out_free_kvlist;
2388
2389         ifnames.idx = 0;
2390         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2391                            mrvl_get_ifnames, &ifnames);
2392
2393
2394         /*
2395          * The below system initialization should be done only once,
2396          * on the first provided configuration file
2397          */
2398         if (!mrvl_qos_cfg) {
2399                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2400                 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2401                 if (cfgnum > 1) {
2402                         RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2403                         goto out_free_kvlist;
2404                 } else if (cfgnum == 1) {
2405                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2406                                            mrvl_get_qoscfg, &mrvl_qos_cfg);
2407                 }
2408         }
2409
2410         if (mrvl_dev_num)
2411                 goto init_devices;
2412
2413         RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2414         /*
2415          * ret == -EEXIST is correct, it means DMA
2416          * has been already initialized (by another PMD).
2417          */
2418         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2419         if (ret < 0) {
2420                 if (ret != -EEXIST)
2421                         goto out_free_kvlist;
2422                 else
2423                         RTE_LOG(INFO, PMD,
2424                                 "DMA memory has been already initialized by a different driver.\n");
2425         }
2426
2427         ret = mrvl_init_pp2();
2428         if (ret) {
2429                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2430                 goto out_deinit_dma;
2431         }
2432
2433         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2434         memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup));
2435
2436         mrvl_lcore_first = RTE_MAX_LCORE;
2437         mrvl_lcore_last = 0;
2438
2439 init_devices:
2440         for (i = 0; i < ifnum; i++) {
2441                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2442                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2443                 if (ret)
2444                         goto out_cleanup;
2445         }
2446         mrvl_dev_num += ifnum;
2447
2448         rte_kvargs_free(kvlist);
2449
2450         return 0;
2451 out_cleanup:
2452         for (; i > 0; i--)
2453                 mrvl_eth_dev_destroy(ifnames.names[i]);
2454
2455         if (mrvl_dev_num == 0)
2456                 mrvl_deinit_pp2();
2457 out_deinit_dma:
2458         if (mrvl_dev_num == 0)
2459                 mv_sys_dma_mem_destroy();
2460 out_free_kvlist:
2461         rte_kvargs_free(kvlist);
2462
2463         return ret;
2464 }
2465
2466 /**
2467  * DPDK callback to remove virtual device.
2468  *
2469  * @param vdev
2470  *   Pointer to the removed virtual device.
2471  *
2472  * @return
2473  *   0 on success, negative error value otherwise.
2474  */
2475 static int
2476 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2477 {
2478         int i;
2479         const char *name;
2480
2481         name = rte_vdev_device_name(vdev);
2482         if (!name)
2483                 return -EINVAL;
2484
2485         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2486
2487         for (i = 0; i < rte_eth_dev_count(); i++) {
2488                 char ifname[RTE_ETH_NAME_MAX_LEN];
2489
2490                 rte_eth_dev_get_name_by_port(i, ifname);
2491                 mrvl_eth_dev_destroy(ifname);
2492                 mrvl_dev_num--;
2493         }
2494
2495         if (mrvl_dev_num == 0) {
2496                 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2497                 mrvl_deinit_hifs();
2498                 mrvl_deinit_pp2();
2499                 mv_sys_dma_mem_destroy();
2500         }
2501
2502         return 0;
2503 }
2504
2505 static struct rte_vdev_driver pmd_mrvl_drv = {
2506         .probe = rte_pmd_mrvl_probe,
2507         .remove = rte_pmd_mrvl_remove,
2508 };
2509
2510 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2511 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);