drivers/net/mrvl/mrvl_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2017 Marvell International Ltd.
   5  *   Copyright(c) 2017 Semihalf.
   6  *   All rights reserved.
   7  *
   8  *   Redistribution and use in source and binary forms, with or without
   9  *   modification, are permitted provided that the following conditions
  10  *   are met:
  11  *
  12  *     * Redistributions of source code must retain the above copyright
  13  *       notice, this list of conditions and the following disclaimer.
  14  *     * Redistributions in binary form must reproduce the above copyright
  15  *       notice, this list of conditions and the following disclaimer in
  16  *       the documentation and/or other materials provided with the
  17  *       distribution.
  18  *     * Neither the name of Semihalf nor the names of its
  19  *       contributors may be used to endorse or promote products derived
  20  *       from this software without specific prior written permission.
  21  *
  22  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <rte_ethdev.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_log.h>
  38 #include <rte_malloc.h>
  39 #include <rte_bus_vdev.h>
  40
  41 /* Unluckily, container_of is defined by both DPDK and MUSDK,
  42  * we'll declare only one version.
  43  *
  44  * Note that it is not used in this PMD anyway.
  45  */
  46 #ifdef container_of
  47 #undef container_of
  48 #endif
  49
  50 #include <drivers/mv_pp2.h>
  51 #include <drivers/mv_pp2_bpool.h>
  52 #include <drivers/mv_pp2_hif.h>
  53
  54 #include <fcntl.h>
  55 #include <linux/ethtool.h>
  56 #include <linux/sockios.h>
  57 #include <net/if.h>
  58 #include <net/if_arp.h>
  59 #include <sys/ioctl.h>
  60 #include <sys/socket.h>
  61 #include <sys/stat.h>
  62 #include <sys/types.h>
  63
  64 #include "mrvl_ethdev.h"
  65 #include "mrvl_qos.h"
  66
  67 /* bitmask with reserved hifs */
  68 #define MRVL_MUSDK_HIFS_RESERVED 0x0F
  69 /* bitmask with reserved bpools */
  70 #define MRVL_MUSDK_BPOOLS_RESERVED 0x07
  71 /* bitmask with reserved kernel RSS tables */
  72 #define MRVL_MUSDK_RSS_RESERVED 0x01
  73 /* maximum number of available hifs */
  74 #define MRVL_MUSDK_HIFS_MAX 9
  75
  76 /* prefetch shift */
  77 #define MRVL_MUSDK_PREFETCH_SHIFT 2
  78
  79 /* TCAM has 25 entries reserved for uc/mc filter entries */
  80 #define MRVL_MAC_ADDRS_MAX 25
  81 #define MRVL_MATCH_LEN 16
  82 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE)
  83 /* Maximum allowable packet size */
  84 #define MRVL_PKT_SIZE_MAX (10240 - MV_MH_SIZE)
  85
  86 #define MRVL_IFACE_NAME_ARG "iface"
  87 #define MRVL_CFG_ARG "cfg"
  88
  89 #define MRVL_BURST_SIZE 64
  90
  91 #define MRVL_ARP_LENGTH 28
  92
  93 #define MRVL_COOKIE_ADDR_INVALID ~0ULL
  94
  95 #define MRVL_COOKIE_HIGH_ADDR_SHIFT     (sizeof(pp2_cookie_t) * 8)
  96 #define MRVL_COOKIE_HIGH_ADDR_MASK      (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)
  97
  98 /* Memory size (in bytes) for MUSDK dma buffers */
  99 #define MRVL_MUSDK_DMA_MEMSIZE 41943040
 100
 101 static const char * const valid_args[] = {
 102         MRVL_IFACE_NAME_ARG,
 103         MRVL_CFG_ARG,
 104         NULL
 105 };
 106
 107 static int used_hifs = MRVL_MUSDK_HIFS_RESERVED;
 108 static struct pp2_hif *hifs[RTE_MAX_LCORE];
 109 static int used_bpools[PP2_NUM_PKT_PROC] = {
 110         [0 ... PP2_NUM_PKT_PROC - 1] = MRVL_MUSDK_BPOOLS_RESERVED
 111 };
 112
 113 struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS];
 114 int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE];
 115 uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID;
 116
 117 struct mrvl_ifnames {
 118         const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC];
 119         int idx;
 120 };
 121
 122 /*
 123  * To use buffer harvesting based on loopback port shadow queue structure
 124  * was introduced for buffers information bookkeeping.
 125  *
 126  * Before sending the packet, related buffer information (pp2_buff_inf) is
 127  * stored in shadow queue. After packet is transmitted no longer used
 128  * packet buffer is released back to it's original hardware pool,
 129  * on condition it originated from interface.
 130  * In case it  was generated by application itself i.e: mbuf->port field is
 131  * 0xff then its released to software mempool.
 132  */
 133 struct mrvl_shadow_txq {
 134         int head;           /* write index - used when sending buffers */
 135         int tail;           /* read index - used when releasing buffers */
 136         u16 size;           /* queue occupied size */
 137         u16 num_to_release; /* number of buffers sent, that can be released */
 138         struct buff_release_entry ent[MRVL_PP2_TX_SHADOWQ_SIZE]; /* q entries */
 139 };
 140
 141 struct mrvl_rxq {
 142         struct mrvl_priv *priv;
 143         struct rte_mempool *mp;
 144         int queue_id;
 145         int port_id;
 146         int cksum_enabled;
 147         uint64_t bytes_recv;
 148         uint64_t drop_mac;
 149 };
 150
 151 struct mrvl_txq {
 152         struct mrvl_priv *priv;
 153         int queue_id;
 154         int port_id;
 155         uint64_t bytes_sent;
 156         struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE];
 157 };
 158
 159 static int mrvl_lcore_first;
 160 static int mrvl_lcore_last;
 161 static int mrvl_dev_num;
 162
 163 static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num);
 164 static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio,
 165                         struct pp2_hif *hif, unsigned int core_id,
 166                         struct mrvl_shadow_txq *sq, int qid, int force);
 167
 168 static inline int
 169 mrvl_get_bpool_size(int pp2_id, int pool_id)
 170 {
 171         int i;
 172         int size = 0;
 173
 174         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++)
 175                 size += mrvl_port_bpool_size[pp2_id][pool_id][i];
 176
 177         return size;
 178 }
 179
 180 static inline int
 181 mrvl_reserve_bit(int *bitmap, int max)
 182 {
 183         int n = sizeof(*bitmap) * 8 - __builtin_clz(*bitmap);
 184
 185         if (n >= max)
 186                 return -1;
 187
 188         *bitmap |= 1 << n;
 189
 190         return n;
 191 }
 192
 193 static int
 194 mrvl_init_hif(int core_id)
 195 {
 196         struct pp2_hif_params params;
 197         char match[MRVL_MATCH_LEN];
 198         int ret;
 199
 200         ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX);
 201         if (ret < 0) {
 202                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 203                 return ret;
 204         }
 205
 206         snprintf(match, sizeof(match), "hif-%d", ret);
 207         memset(&params, 0, sizeof(params));
 208         params.match = match;
 209         params.out_size = MRVL_PP2_AGGR_TXQD_MAX;
 210         ret = pp2_hif_init(&params, &hifs[core_id]);
 211         if (ret) {
 212                 RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id);
 213                 return ret;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static inline struct pp2_hif*
 220 mrvl_get_hif(struct mrvl_priv *priv, int core_id)
 221 {
 222         int ret;
 223
 224         if (likely(hifs[core_id] != NULL))
 225                 return hifs[core_id];
 226
 227         rte_spinlock_lock(&priv->lock);
 228
 229         ret = mrvl_init_hif(core_id);
 230         if (ret < 0) {
 231                 RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id);
 232                 goto out;
 233         }
 234
 235         if (core_id < mrvl_lcore_first)
 236                 mrvl_lcore_first = core_id;
 237
 238         if (core_id > mrvl_lcore_last)
 239                 mrvl_lcore_last = core_id;
 240 out:
 241         rte_spinlock_unlock(&priv->lock);
 242
 243         return hifs[core_id];
 244 }
 245
 246 /**
 247  * Configure rss based on dpdk rss configuration.
 248  *
 249  * @param priv
 250  *   Pointer to private structure.
 251  * @param rss_conf
 252  *   Pointer to RSS configuration.
 253  *
 254  * @return
 255  *   0 on success, negative error value otherwise.
 256  */
 257 static int
 258 mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf)
 259 {
 260         if (rss_conf->rss_key)
 261                 RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n");
 262
 263         if (rss_conf->rss_hf == 0) {
 264                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 265         } else if (rss_conf->rss_hf & ETH_RSS_IPV4) {
 266                 priv->ppio_params.inqs_params.hash_type =
 267                         PP2_PPIO_HASH_T_2_TUPLE;
 268         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
 269                 priv->ppio_params.inqs_params.hash_type =
 270                         PP2_PPIO_HASH_T_5_TUPLE;
 271                 priv->rss_hf_tcp = 1;
 272         } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
 273                 priv->ppio_params.inqs_params.hash_type =
 274                         PP2_PPIO_HASH_T_5_TUPLE;
 275                 priv->rss_hf_tcp = 0;
 276         } else {
 277                 return -EINVAL;
 278         }
 279
 280         return 0;
 281 }
 282
 283 /**
 284  * Ethernet device configuration.
 285  *
 286  * Prepare the driver for a given number of TX and RX queues and
 287  * configure RSS.
 288  *
 289  * @param dev
 290  *   Pointer to Ethernet device structure.
 291  *
 292  * @return
 293  *   0 on success, negative error value otherwise.
 294  */
 295 static int
 296 mrvl_dev_configure(struct rte_eth_dev *dev)
 297 {
 298         struct mrvl_priv *priv = dev->data->dev_private;
 299         int ret;
 300
 301         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE &&
 302             dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
 303                 RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n",
 304                         dev->data->dev_conf.rxmode.mq_mode);
 305                 return -EINVAL;
 306         }
 307
 308         if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
 309                 RTE_LOG(INFO, PMD,
 310                         "L2 CRC stripping is always enabled in hw\n");
 311                 dev->data->dev_conf.rxmode.hw_strip_crc = 1;
 312         }
 313
 314         if (dev->data->dev_conf.rxmode.hw_vlan_strip) {
 315                 RTE_LOG(INFO, PMD, "VLAN stripping not supported\n");
 316                 return -EINVAL;
 317         }
 318
 319         if (dev->data->dev_conf.rxmode.split_hdr_size) {
 320                 RTE_LOG(INFO, PMD, "Split headers not supported\n");
 321                 return -EINVAL;
 322         }
 323
 324         if (dev->data->dev_conf.rxmode.enable_scatter) {
 325                 RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n");
 326                 return -EINVAL;
 327         }
 328
 329         if (dev->data->dev_conf.rxmode.enable_lro) {
 330                 RTE_LOG(INFO, PMD, "LRO not supported\n");
 331                 return -EINVAL;
 332         }
 333
 334         if (dev->data->dev_conf.rxmode.jumbo_frame)
 335                 dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len -
 336                                  ETHER_HDR_LEN - ETHER_CRC_LEN;
 337
 338         ret = mrvl_configure_rxqs(priv, dev->data->port_id,
 339                                   dev->data->nb_rx_queues);
 340         if (ret < 0)
 341                 return ret;
 342
 343         priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues;
 344         priv->ppio_params.maintain_stats = 1;
 345         priv->nb_rx_queues = dev->data->nb_rx_queues;
 346
 347         if (dev->data->nb_rx_queues == 1 &&
 348             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 349                 RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n");
 350                 priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE;
 351
 352                 return 0;
 353         }
 354
 355         return mrvl_configure_rss(priv,
 356                                   &dev->data->dev_conf.rx_adv_conf.rss_conf);
 357 }
 358
 359 /**
 360  * DPDK callback to change the MTU.
 361  *
 362  * Setting the MTU affects hardware MRU (packets larger than the MRU
 363  * will be dropped).
 364  *
 365  * @param dev
 366  *   Pointer to Ethernet device structure.
 367  * @param mtu
 368  *   New MTU.
 369  *
 370  * @return
 371  *   0 on success, negative error value otherwise.
 372  */
 373 static int
 374 mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 375 {
 376         struct mrvl_priv *priv = dev->data->dev_private;
 377         /* extra MV_MH_SIZE bytes are required for Marvell tag */
 378         uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN;
 379         int ret;
 380
 381         if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX)
 382                 return -EINVAL;
 383
 384         ret = pp2_ppio_set_mru(priv->ppio, mru);
 385         if (ret)
 386                 return ret;
 387
 388         return pp2_ppio_set_mtu(priv->ppio, mtu);
 389 }
 390
 391 /**
 392  * DPDK callback to bring the link up.
 393  *
 394  * @param dev
 395  *   Pointer to Ethernet device structure.
 396  *
 397  * @return
 398  *   0 on success, negative error value otherwise.
 399  */
 400 static int
 401 mrvl_dev_set_link_up(struct rte_eth_dev *dev)
 402 {
 403         struct mrvl_priv *priv = dev->data->dev_private;
 404         int ret;
 405
 406         ret = pp2_ppio_enable(priv->ppio);
 407         if (ret)
 408                 return ret;
 409
 410         /*
 411          * mtu/mru can be updated if pp2_ppio_enable() was called at least once
 412          * as pp2_ppio_enable() changes port->t_mode from default 0 to
 413          * PP2_TRAFFIC_INGRESS_EGRESS.
 414          *
 415          * Set mtu to default DPDK value here.
 416          */
 417         ret = mrvl_mtu_set(dev, dev->data->mtu);
 418         if (ret)
 419                 pp2_ppio_disable(priv->ppio);
 420
 421         dev->data->dev_link.link_status = ETH_LINK_UP;
 422
 423         return ret;
 424 }
 425
 426 /**
 427  * DPDK callback to bring the link down.
 428  *
 429  * @param dev
 430  *   Pointer to Ethernet device structure.
 431  *
 432  * @return
 433  *   0 on success, negative error value otherwise.
 434  */
 435 static int
 436 mrvl_dev_set_link_down(struct rte_eth_dev *dev)
 437 {
 438         struct mrvl_priv *priv = dev->data->dev_private;
 439         int ret;
 440
 441         ret = pp2_ppio_disable(priv->ppio);
 442         if (ret)
 443                 return ret;
 444
 445         dev->data->dev_link.link_status = ETH_LINK_DOWN;
 446
 447         return ret;
 448 }
 449
 450 /**
 451  * DPDK callback to start the device.
 452  *
 453  * @param dev
 454  *   Pointer to Ethernet device structure.
 455  *
 456  * @return
 457  *   0 on success, negative errno value on failure.
 458  */
 459 static int
 460 mrvl_dev_start(struct rte_eth_dev *dev)
 461 {
 462         struct mrvl_priv *priv = dev->data->dev_private;
 463         char match[MRVL_MATCH_LEN];
 464         int ret = 0, def_init_size;
 465
 466         snprintf(match, sizeof(match), "ppio-%d:%d",
 467                  priv->pp_id, priv->ppio_id);
 468         priv->ppio_params.match = match;
 469
 470         /*
 471          * Calculate the minimum bpool size for refill feature as follows:
 472          * 2 default burst sizes multiply by number of rx queues.
 473          * If the bpool size will be below this value, new buffers will
 474          * be added to the pool.
 475          */
 476         priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2;
 477
 478         /* In case initial bpool size configured in queues setup is
 479          * smaller than minimum size add more buffers
 480          */
 481         def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2;
 482         if (priv->bpool_init_size < def_init_size) {
 483                 int buffs_to_add = def_init_size - priv->bpool_init_size;
 484
 485                 priv->bpool_init_size += buffs_to_add;
 486                 ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add);
 487                 if (ret)
 488                         RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n");
 489         }
 490
 491         /*
 492          * Calculate the maximum bpool size for refill feature as follows:
 493          * maximum number of descriptors in rx queue multiply by number
 494          * of rx queues plus minimum bpool size.
 495          * In case the bpool size will exceed this value, superfluous buffers
 496          * will be removed
 497          */
 498         priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) +
 499                                 priv->bpool_min_size;
 500
 501         ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio);
 502         if (ret)
 503                 return ret;
 504
 505         /*
 506          * In case there are some some stale uc/mc mac addresses flush them
 507          * here. It cannot be done during mrvl_dev_close() as port information
 508          * is already gone at that point (due to pp2_ppio_deinit() in
 509          * mrvl_dev_stop()).
 510          */
 511         if (!priv->uc_mc_flushed) {
 512                 ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1);
 513                 if (ret) {
 514                         RTE_LOG(ERR, PMD,
 515                                 "Failed to flush uc/mc filter list\n");
 516                         goto out;
 517                 }
 518                 priv->uc_mc_flushed = 1;
 519         }
 520
 521         if (!priv->vlan_flushed) {
 522                 ret = pp2_ppio_flush_vlan(priv->ppio);
 523                 if (ret) {
 524                         RTE_LOG(ERR, PMD, "Failed to flush vlan list\n");
 525                         /*
 526                          * TODO
 527                          * once pp2_ppio_flush_vlan() is supported jump to out
 528                          * goto out;
 529                          */
 530                 }
 531                 priv->vlan_flushed = 1;
 532         }
 533
 534         /* For default QoS config, don't start classifier. */
 535         if (mrvl_qos_cfg) {
 536                 ret = mrvl_start_qos_mapping(priv);
 537                 if (ret) {
 538                         pp2_ppio_deinit(priv->ppio);
 539                         return ret;
 540                 }
 541         }
 542
 543         ret = mrvl_dev_set_link_up(dev);
 544         if (ret)
 545                 goto out;
 546
 547         return 0;
 548 out:
 549         pp2_ppio_deinit(priv->ppio);
 550         return ret;
 551 }
 552
 553 /**
 554  * Flush receive queues.
 555  *
 556  * @param dev
 557  *   Pointer to Ethernet device structure.
 558  */
 559 static void
 560 mrvl_flush_rx_queues(struct rte_eth_dev *dev)
 561 {
 562         int i;
 563
 564         RTE_LOG(INFO, PMD, "Flushing rx queues\n");
 565         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 566                 int ret, num;
 567
 568                 do {
 569                         struct mrvl_rxq *q = dev->data->rx_queues[i];
 570                         struct pp2_ppio_desc descs[MRVL_PP2_RXD_MAX];
 571
 572                         num = MRVL_PP2_RXD_MAX;
 573                         ret = pp2_ppio_recv(q->priv->ppio,
 574                                             q->priv->rxq_map[q->queue_id].tc,
 575                                             q->priv->rxq_map[q->queue_id].inq,
 576                                             descs, (uint16_t *)&num);
 577                 } while (ret == 0 && num);
 578         }
 579 }
 580
 581 /**
 582  * Flush transmit shadow queues.
 583  *
 584  * @param dev
 585  *   Pointer to Ethernet device structure.
 586  */
 587 static void
 588 mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev)
 589 {
 590         int i, j;
 591         struct mrvl_txq *txq;
 592
 593         RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n");
 594         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 595                 txq = (struct mrvl_txq *)dev->data->tx_queues[i];
 596
 597                 for (j = 0; j < RTE_MAX_LCORE; j++) {
 598                         struct mrvl_shadow_txq *sq;
 599
 600                         if (!hifs[j])
 601                                 continue;
 602
 603                         sq = &txq->shadow_txqs[j];
 604                         mrvl_free_sent_buffers(txq->priv->ppio,
 605                                 hifs[j], j, sq, txq->queue_id, 1);
 606                         while (sq->tail != sq->head) {
 607                                 uint64_t addr = cookie_addr_high |
 608                                         sq->ent[sq->tail].buff.cookie;
 609                                 rte_pktmbuf_free(
 610                                         (struct rte_mbuf *)addr);
 611                                 sq->tail = (sq->tail + 1) &
 612                                             MRVL_PP2_TX_SHADOWQ_MASK;
 613                         }
 614                         memset(sq, 0, sizeof(*sq));
 615                 }
 616         }
 617 }
 618
 619 /**
 620  * Flush hardware bpool (buffer-pool).
 621  *
 622  * @param dev
 623  *   Pointer to Ethernet device structure.
 624  */
 625 static void
 626 mrvl_flush_bpool(struct rte_eth_dev *dev)
 627 {
 628         struct mrvl_priv *priv = dev->data->dev_private;
 629         struct pp2_hif *hif;
 630         uint32_t num;
 631         int ret;
 632         unsigned int core_id = rte_lcore_id();
 633
 634         if (core_id == LCORE_ID_ANY)
 635                 core_id = 0;
 636
 637         hif = mrvl_get_hif(priv, core_id);
 638
 639         ret = pp2_bpool_get_num_buffs(priv->bpool, &num);
 640         if (ret) {
 641                 RTE_LOG(ERR, PMD, "Failed to get bpool buffers number\n");
 642                 return;
 643         }
 644
 645         while (num--) {
 646                 struct pp2_buff_inf inf;
 647                 uint64_t addr;
 648
 649                 ret = pp2_bpool_get_buff(hif, priv->bpool, &inf);
 650                 if (ret)
 651                         break;
 652
 653                 addr = cookie_addr_high | inf.cookie;
 654                 rte_pktmbuf_free((struct rte_mbuf *)addr);
 655         }
 656 }
 657
 658 /**
 659  * DPDK callback to stop the device.
 660  *
 661  * @param dev
 662  *   Pointer to Ethernet device structure.
 663  */
 664 static void
 665 mrvl_dev_stop(struct rte_eth_dev *dev)
 666 {
 667         struct mrvl_priv *priv = dev->data->dev_private;
 668
 669         mrvl_dev_set_link_down(dev);
 670         mrvl_flush_rx_queues(dev);
 671         mrvl_flush_tx_shadow_queues(dev);
 672         if (priv->qos_tbl) {
 673                 pp2_cls_qos_tbl_deinit(priv->qos_tbl);
 674                 priv->qos_tbl = NULL;
 675         }
 676         if (priv->ppio)
 677                 pp2_ppio_deinit(priv->ppio);
 678         priv->ppio = NULL;
 679 }
 680
 681 /**
 682  * DPDK callback to close the device.
 683  *
 684  * @param dev
 685  *   Pointer to Ethernet device structure.
 686  */
 687 static void
 688 mrvl_dev_close(struct rte_eth_dev *dev)
 689 {
 690         struct mrvl_priv *priv = dev->data->dev_private;
 691         size_t i;
 692
 693         for (i = 0; i < priv->ppio_params.inqs_params.num_tcs; ++i) {
 694                 struct pp2_ppio_tc_params *tc_params =
 695                         &priv->ppio_params.inqs_params.tcs_params[i];
 696
 697                 if (tc_params->inqs_params) {
 698                         rte_free(tc_params->inqs_params);
 699                         tc_params->inqs_params = NULL;
 700                 }
 701         }
 702
 703         mrvl_flush_bpool(dev);
 704 }
 705
 706 /**
 707  * DPDK callback to retrieve physical link information.
 708  *
 709  * @param dev
 710  *   Pointer to Ethernet device structure.
 711  * @param wait_to_complete
 712  *   Wait for request completion (ignored).
 713  *
 714  * @return
 715  *   0 on success, negative error value otherwise.
 716  */
 717 static int
 718 mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
 719 {
 720         /*
 721          * TODO
 722          * once MUSDK provides necessary API use it here
 723          */
 724         struct ethtool_cmd edata;
 725         struct ifreq req;
 726         int ret, fd;
 727
 728         edata.cmd = ETHTOOL_GSET;
 729
 730         strcpy(req.ifr_name, dev->data->name);
 731         req.ifr_data = (void *)&edata;
 732
 733         fd = socket(AF_INET, SOCK_DGRAM, 0);
 734         if (fd == -1)
 735                 return -EFAULT;
 736
 737         ret = ioctl(fd, SIOCETHTOOL, &req);
 738         if (ret == -1) {
 739                 close(fd);
 740                 return -EFAULT;
 741         }
 742
 743         close(fd);
 744
 745         switch (ethtool_cmd_speed(&edata)) {
 746         case SPEED_10:
 747                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10M;
 748                 break;
 749         case SPEED_100:
 750                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_100M;
 751                 break;
 752         case SPEED_1000:
 753                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_1G;
 754                 break;
 755         case SPEED_10000:
 756                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_10G;
 757                 break;
 758         default:
 759                 dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE;
 760         }
 761
 762         dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX :
 763                                                          ETH_LINK_HALF_DUPLEX;
 764         dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG :
 765                                                            ETH_LINK_FIXED;
 766
 767         return 0;
 768 }
 769
 770 /**
 771  * DPDK callback to enable promiscuous mode.
 772  *
 773  * @param dev
 774  *   Pointer to Ethernet device structure.
 775  */
 776 static void
 777 mrvl_promiscuous_enable(struct rte_eth_dev *dev)
 778 {
 779         struct mrvl_priv *priv = dev->data->dev_private;
 780         int ret;
 781
 782         ret = pp2_ppio_set_uc_promisc(priv->ppio, 1);
 783         if (ret)
 784                 RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n");
 785 }
 786
 787 /**
 788  * DPDK callback to enable allmulti mode.
 789  *
 790  * @param dev
 791  *   Pointer to Ethernet device structure.
 792  */
 793 static void
 794 mrvl_allmulticast_enable(struct rte_eth_dev *dev)
 795 {
 796         struct mrvl_priv *priv = dev->data->dev_private;
 797         int ret;
 798
 799         ret = pp2_ppio_set_mc_promisc(priv->ppio, 1);
 800         if (ret)
 801                 RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n");
 802 }
 803
 804 /**
 805  * DPDK callback to disable promiscuous mode.
 806  *
 807  * @param dev
 808  *   Pointer to Ethernet device structure.
 809  */
 810 static void
 811 mrvl_promiscuous_disable(struct rte_eth_dev *dev)
 812 {
 813         struct mrvl_priv *priv = dev->data->dev_private;
 814         int ret;
 815
 816         ret = pp2_ppio_set_uc_promisc(priv->ppio, 0);
 817         if (ret)
 818                 RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n");
 819 }
 820
 821 /**
 822  * DPDK callback to disable allmulticast mode.
 823  *
 824  * @param dev
 825  *   Pointer to Ethernet device structure.
 826  */
 827 static void
 828 mrvl_allmulticast_disable(struct rte_eth_dev *dev)
 829 {
 830         struct mrvl_priv *priv = dev->data->dev_private;
 831         int ret;
 832
 833         ret = pp2_ppio_set_mc_promisc(priv->ppio, 0);
 834         if (ret)
 835                 RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n");
 836 }
 837
 838 /**
 839  * DPDK callback to remove a MAC address.
 840  *
 841  * @param dev
 842  *   Pointer to Ethernet device structure.
 843  * @param index
 844  *   MAC address index.
 845  */
 846 static void
 847 mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
 848 {
 849         struct mrvl_priv *priv = dev->data->dev_private;
 850         char buf[ETHER_ADDR_FMT_SIZE];
 851         int ret;
 852
 853         ret = pp2_ppio_remove_mac_addr(priv->ppio,
 854                                        dev->data->mac_addrs[index].addr_bytes);
 855         if (ret) {
 856                 ether_format_addr(buf, sizeof(buf),
 857                                   &dev->data->mac_addrs[index]);
 858                 RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf);
 859         }
 860 }
 861
 862 /**
 863  * DPDK callback to add a MAC address.
 864  *
 865  * @param dev
 866  *   Pointer to Ethernet device structure.
 867  * @param mac_addr
 868  *   MAC address to register.
 869  * @param index
 870  *   MAC address index.
 871  * @param vmdq
 872  *   VMDq pool index to associate address with (unused).
 873  *
 874  * @return
 875  *   0 on success, negative error value otherwise.
 876  */
 877 static int
 878 mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 879                   uint32_t index, uint32_t vmdq __rte_unused)
 880 {
 881         struct mrvl_priv *priv = dev->data->dev_private;
 882         char buf[ETHER_ADDR_FMT_SIZE];
 883         int ret;
 884
 885         if (index == 0)
 886                 /* For setting index 0, mrvl_mac_addr_set() should be used.*/
 887                 return -1;
 888
 889         /*
 890          * Maximum number of uc addresses can be tuned via kernel module mvpp2x
 891          * parameter uc_filter_max. Maximum number of mc addresses is then
 892          * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and
 893          * 21 respectively.
 894          *
 895          * If more than uc_filter_max uc addresses were added to filter list
 896          * then NIC will switch to promiscuous mode automatically.
 897          *
 898          * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses
 899          * were added to filter list then NIC will switch to all-multicast mode
 900          * automatically.
 901          */
 902         ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes);
 903         if (ret) {
 904                 ether_format_addr(buf, sizeof(buf), mac_addr);
 905                 RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf);
 906                 return -1;
 907         }
 908
 909         return 0;
 910 }
 911
 912 /**
 913  * DPDK callback to set the primary MAC address.
 914  *
 915  * @param dev
 916  *   Pointer to Ethernet device structure.
 917  * @param mac_addr
 918  *   MAC address to register.
 919  */
 920 static void
 921 mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 922 {
 923         struct mrvl_priv *priv = dev->data->dev_private;
 924
 925         pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes);
 926         /*
 927          * TODO
 928          * Port stops sending packets if pp2_ppio_set_mac_addr()
 929          * was called after pp2_ppio_enable(). As a quick fix issue
 930          * enable port once again.
 931          */
 932         pp2_ppio_enable(priv->ppio);
 933 }
 934
 935 /**
 936  * DPDK callback to get device statistics.
 937  *
 938  * @param dev
 939  *   Pointer to Ethernet device structure.
 940  * @param stats
 941  *   Stats structure output buffer.
 942  *
 943  * @return
 944  *   0 on success, negative error value otherwise.
 945  */
 946 static int
 947 mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 948 {
 949         struct mrvl_priv *priv = dev->data->dev_private;
 950         struct pp2_ppio_statistics ppio_stats;
 951         uint64_t drop_mac = 0;
 952         unsigned int i, idx, ret;
 953
 954         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 955                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
 956                 struct pp2_ppio_inq_statistics rx_stats;
 957
 958                 if (!rxq)
 959                         continue;
 960
 961                 idx = rxq->queue_id;
 962                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 963                         RTE_LOG(ERR, PMD,
 964                                 "rx queue %d stats out of range (0 - %d)\n",
 965                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
 966                         continue;
 967                 }
 968
 969                 ret = pp2_ppio_inq_get_statistics(priv->ppio,
 970                                                   priv->rxq_map[idx].tc,
 971                                                   priv->rxq_map[idx].inq,
 972                                                   &rx_stats, 0);
 973                 if (unlikely(ret)) {
 974                         RTE_LOG(ERR, PMD,
 975                                 "Failed to update rx queue %d stats\n", idx);
 976                         break;
 977                 }
 978
 979                 stats->q_ibytes[idx] = rxq->bytes_recv;
 980                 stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac;
 981                 stats->q_errors[idx] = rx_stats.drop_early +
 982                                        rx_stats.drop_fullq +
 983                                        rx_stats.drop_bm +
 984                                        rxq->drop_mac;
 985                 stats->ibytes += rxq->bytes_recv;
 986                 drop_mac += rxq->drop_mac;
 987         }
 988
 989         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 990                 struct mrvl_txq *txq = dev->data->tx_queues[i];
 991                 struct pp2_ppio_outq_statistics tx_stats;
 992
 993                 if (!txq)
 994                         continue;
 995
 996                 idx = txq->queue_id;
 997                 if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) {
 998                         RTE_LOG(ERR, PMD,
 999                                 "tx queue %d stats out of range (0 - %d)\n",
1000                                 idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);
1001                 }
1002
1003                 ret = pp2_ppio_outq_get_statistics(priv->ppio, idx,
1004                                                    &tx_stats, 0);
1005                 if (unlikely(ret)) {
1006                         RTE_LOG(ERR, PMD,
1007                                 "Failed to update tx queue %d stats\n", idx);
1008                         break;
1009                 }
1010
1011                 stats->q_opackets[idx] = tx_stats.deq_desc;
1012                 stats->q_obytes[idx] = txq->bytes_sent;
1013                 stats->obytes += txq->bytes_sent;
1014         }
1015
1016         ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0);
1017         if (unlikely(ret)) {
1018                 RTE_LOG(ERR, PMD, "Failed to update port statistics\n");
1019                 return ret;
1020         }
1021
1022         stats->ipackets += ppio_stats.rx_packets - drop_mac;
1023         stats->opackets += ppio_stats.tx_packets;
1024         stats->imissed += ppio_stats.rx_fullq_dropped +
1025                           ppio_stats.rx_bm_dropped +
1026                           ppio_stats.rx_early_dropped +
1027                           ppio_stats.rx_fifo_dropped +
1028                           ppio_stats.rx_cls_dropped;
1029         stats->ierrors = drop_mac;
1030
1031         return 0;
1032 }
1033
1034 /**
1035  * DPDK callback to clear device statistics.
1036  *
1037  * @param dev
1038  *   Pointer to Ethernet device structure.
1039  */
1040 static void
1041 mrvl_stats_reset(struct rte_eth_dev *dev)
1042 {
1043         struct mrvl_priv *priv = dev->data->dev_private;
1044         int i;
1045
1046         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1047                 struct mrvl_rxq *rxq = dev->data->rx_queues[i];
1048
1049                 pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc,
1050                                             priv->rxq_map[i].inq, NULL, 1);
1051                 rxq->bytes_recv = 0;
1052                 rxq->drop_mac = 0;
1053         }
1054
1055         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1056                 struct mrvl_txq *txq = dev->data->tx_queues[i];
1057
1058                 pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1);
1059                 txq->bytes_sent = 0;
1060         }
1061
1062         pp2_ppio_get_statistics(priv->ppio, NULL, 1);
1063 }
1064
1065 /**
1066  * DPDK callback to get information about the device.
1067  *
1068  * @param dev
1069  *   Pointer to Ethernet device structure (unused).
1070  * @param info
1071  *   Info structure output buffer.
1072  */
1073 static void
1074 mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
1075                    struct rte_eth_dev_info *info)
1076 {
1077         info->speed_capa = ETH_LINK_SPEED_10M |
1078                            ETH_LINK_SPEED_100M |
1079                            ETH_LINK_SPEED_1G |
1080                            ETH_LINK_SPEED_10G;
1081
1082         info->max_rx_queues = MRVL_PP2_RXQ_MAX;
1083         info->max_tx_queues = MRVL_PP2_TXQ_MAX;
1084         info->max_mac_addrs = MRVL_MAC_ADDRS_MAX;
1085
1086         info->rx_desc_lim.nb_max = MRVL_PP2_RXD_MAX;
1087         info->rx_desc_lim.nb_min = MRVL_PP2_RXD_MIN;
1088         info->rx_desc_lim.nb_align = MRVL_PP2_RXD_ALIGN;
1089
1090         info->tx_desc_lim.nb_max = MRVL_PP2_TXD_MAX;
1091         info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN;
1092         info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN;
1093
1094         info->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME |
1095                                 DEV_RX_OFFLOAD_VLAN_FILTER |
1096                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1097                                 DEV_RX_OFFLOAD_UDP_CKSUM |
1098                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1099
1100         info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
1101                                 DEV_TX_OFFLOAD_UDP_CKSUM |
1102                                 DEV_TX_OFFLOAD_TCP_CKSUM;
1103
1104         info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1105                                        ETH_RSS_NONFRAG_IPV4_TCP |
1106                                        ETH_RSS_NONFRAG_IPV4_UDP;
1107
1108         /* By default packets are dropped if no descriptors are available */
1109         info->default_rxconf.rx_drop_en = 1;
1110
1111         info->max_rx_pktlen = MRVL_PKT_SIZE_MAX;
1112 }
1113
1114 /**
1115  * Return supported packet types.
1116  *
1117  * @param dev
1118  *   Pointer to Ethernet device structure (unused).
1119  *
1120  * @return
1121  *   Const pointer to the table with supported packet types.
1122  */
1123 static const uint32_t *
1124 mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1125 {
1126         static const uint32_t ptypes[] = {
1127                 RTE_PTYPE_L2_ETHER,
1128                 RTE_PTYPE_L3_IPV4,
1129                 RTE_PTYPE_L3_IPV4_EXT,
1130                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1131                 RTE_PTYPE_L3_IPV6,
1132                 RTE_PTYPE_L3_IPV6_EXT,
1133                 RTE_PTYPE_L2_ETHER_ARP,
1134                 RTE_PTYPE_L4_TCP,
1135                 RTE_PTYPE_L4_UDP
1136         };
1137
1138         return ptypes;
1139 }
1140
1141 /**
1142  * DPDK callback to get information about specific receive queue.
1143  *
1144  * @param dev
1145  *   Pointer to Ethernet device structure.
1146  * @param rx_queue_id
1147  *   Receive queue index.
1148  * @param qinfo
1149  *   Receive queue information structure.
1150  */
1151 static void mrvl_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
1152                               struct rte_eth_rxq_info *qinfo)
1153 {
1154         struct mrvl_rxq *q = dev->data->rx_queues[rx_queue_id];
1155         struct mrvl_priv *priv = dev->data->dev_private;
1156         int inq = priv->rxq_map[rx_queue_id].inq;
1157         int tc = priv->rxq_map[rx_queue_id].tc;
1158         struct pp2_ppio_tc_params *tc_params =
1159                 &priv->ppio_params.inqs_params.tcs_params[tc];
1160
1161         qinfo->mp = q->mp;
1162         qinfo->nb_desc = tc_params->inqs_params[inq].size;
1163 }
1164
1165 /**
1166  * DPDK callback to get information about specific transmit queue.
1167  *
1168  * @param dev
1169  *   Pointer to Ethernet device structure.
1170  * @param tx_queue_id
1171  *   Transmit queue index.
1172  * @param qinfo
1173  *   Transmit queue information structure.
1174  */
1175 static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
1176                               struct rte_eth_txq_info *qinfo)
1177 {
1178         struct mrvl_priv *priv = dev->data->dev_private;
1179
1180         qinfo->nb_desc =
1181                 priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size;
1182 }
1183
1184 /**
1185  * DPDK callback to Configure a VLAN filter.
1186  *
1187  * @param dev
1188  *   Pointer to Ethernet device structure.
1189  * @param vlan_id
1190  *   VLAN ID to filter.
1191  * @param on
1192  *   Toggle filter.
1193  *
1194  * @return
1195  *   0 on success, negative error value otherwise.
1196  */
1197 static int
1198 mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1199 {
1200         struct mrvl_priv *priv = dev->data->dev_private;
1201
1202         return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) :
1203                     pp2_ppio_remove_vlan(priv->ppio, vlan_id);
1204 }
1205
1206 /**
1207  * Release buffers to hardware bpool (buffer-pool)
1208  *
1209  * @param rxq
1210  *   Receive queue pointer.
1211  * @param num
1212  *   Number of buffers to release to bpool.
1213  *
1214  * @return
1215  *   0 on success, negative error value otherwise.
1216  */
1217 static int
1218 mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)
1219 {
1220         struct buff_release_entry entries[MRVL_PP2_RXD_MAX];
1221         struct rte_mbuf *mbufs[MRVL_PP2_RXD_MAX];
1222         int i, ret;
1223         unsigned int core_id;
1224         struct pp2_hif *hif;
1225         struct pp2_bpool *bpool;
1226
1227         core_id = rte_lcore_id();
1228         if (core_id == LCORE_ID_ANY)
1229                 core_id = 0;
1230
1231         hif = mrvl_get_hif(rxq->priv, core_id);
1232         if (!hif)
1233                 return -1;
1234
1235         bpool = rxq->priv->bpool;
1236
1237         ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num);
1238         if (ret)
1239                 return ret;
1240
1241         if (cookie_addr_high == MRVL_COOKIE_ADDR_INVALID)
1242                 cookie_addr_high =
1243                         (uint64_t)mbufs[0] & MRVL_COOKIE_HIGH_ADDR_MASK;
1244
1245         for (i = 0; i < num; i++) {
1246                 if (((uint64_t)mbufs[i] & MRVL_COOKIE_HIGH_ADDR_MASK)
1247                         != cookie_addr_high) {
1248                         RTE_LOG(ERR, PMD,
1249                                 "mbuf virtual addr high 0x%lx out of range\n",
1250                                 (uint64_t)mbufs[i] >> 32);
1251                         goto out;
1252                 }
1253
1254                 entries[i].buff.addr =
1255                         rte_mbuf_data_iova_default(mbufs[i]);
1256                 entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];
1257                 entries[i].bpool = bpool;
1258         }
1259
1260         pp2_bpool_put_buffs(hif, entries, (uint16_t *)&i);
1261         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] += i;
1262
1263         if (i != num)
1264                 goto out;
1265
1266         return 0;
1267 out:
1268         for (; i < num; i++)
1269                 rte_pktmbuf_free(mbufs[i]);
1270
1271         return -1;
1272 }
1273
1274 /**
1275  * DPDK callback to configure the receive queue.
1276  *
1277  * @param dev
1278  *   Pointer to Ethernet device structure.
1279  * @param idx
1280  *   RX queue index.
1281  * @param desc
1282  *   Number of descriptors to configure in queue.
1283  * @param socket
1284  *   NUMA socket on which memory must be allocated.
1285  * @param conf
1286  *   Thresholds parameters (unused_).
1287  * @param mp
1288  *   Memory pool for buffer allocations.
1289  *
1290  * @return
1291  *   0 on success, negative error value otherwise.
1292  */
1293 static int
1294 mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1295                     unsigned int socket,
1296                     const struct rte_eth_rxconf *conf __rte_unused,
1297                     struct rte_mempool *mp)
1298 {
1299         struct mrvl_priv *priv = dev->data->dev_private;
1300         struct mrvl_rxq *rxq;
1301         uint32_t min_size,
1302                  max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1303         int ret, tc, inq;
1304
1305         if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) {
1306                 /*
1307                  * Unknown TC mapping, mapping will not have a correct queue.
1308                  */
1309                 RTE_LOG(ERR, PMD, "Unknown TC mapping for queue %hu eth%hhu\n",
1310                         idx, priv->ppio_id);
1311                 return -EFAULT;
1312         }
1313
1314         min_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM -
1315                    MRVL_PKT_EFFEC_OFFS;
1316         if (min_size < max_rx_pkt_len) {
1317                 RTE_LOG(ERR, PMD,
1318                         "Mbuf size must be increased to %u bytes to hold up to %u bytes of data.\n",
1319                         max_rx_pkt_len + RTE_PKTMBUF_HEADROOM +
1320                         MRVL_PKT_EFFEC_OFFS,
1321                         max_rx_pkt_len);
1322                 return -EINVAL;
1323         }
1324
1325         if (dev->data->rx_queues[idx]) {
1326                 rte_free(dev->data->rx_queues[idx]);
1327                 dev->data->rx_queues[idx] = NULL;
1328         }
1329
1330         rxq = rte_zmalloc_socket("rxq", sizeof(*rxq), 0, socket);
1331         if (!rxq)
1332                 return -ENOMEM;
1333
1334         rxq->priv = priv;
1335         rxq->mp = mp;
1336         rxq->cksum_enabled = dev->data->dev_conf.rxmode.hw_ip_checksum;
1337         rxq->queue_id = idx;
1338         rxq->port_id = dev->data->port_id;
1339         mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool;
1340
1341         tc = priv->rxq_map[rxq->queue_id].tc,
1342         inq = priv->rxq_map[rxq->queue_id].inq;
1343         priv->ppio_params.inqs_params.tcs_params[tc].inqs_params[inq].size =
1344                 desc;
1345
1346         ret = mrvl_fill_bpool(rxq, desc);
1347         if (ret) {
1348                 rte_free(rxq);
1349                 return ret;
1350         }
1351
1352         priv->bpool_init_size += desc;
1353
1354         dev->data->rx_queues[idx] = rxq;
1355
1356         return 0;
1357 }
1358
1359 /**
1360  * DPDK callback to release the receive queue.
1361  *
1362  * @param rxq
1363  *   Generic receive queue pointer.
1364  */
1365 static void
1366 mrvl_rx_queue_release(void *rxq)
1367 {
1368         struct mrvl_rxq *q = rxq;
1369         struct pp2_ppio_tc_params *tc_params;
1370         int i, num, tc, inq;
1371         struct pp2_hif *hif;
1372         unsigned int core_id = rte_lcore_id();
1373
1374         if (core_id == LCORE_ID_ANY)
1375                 core_id = 0;
1376
1377         if (!q)
1378                 return;
1379
1380         hif = mrvl_get_hif(q->priv, core_id);
1381
1382         if (!hif)
1383                 return;
1384
1385         tc = q->priv->rxq_map[q->queue_id].tc;
1386         inq = q->priv->rxq_map[q->queue_id].inq;
1387         tc_params = &q->priv->ppio_params.inqs_params.tcs_params[tc];
1388         num = tc_params->inqs_params[inq].size;
1389         for (i = 0; i < num; i++) {
1390                 struct pp2_buff_inf inf;
1391                 uint64_t addr;
1392
1393                 pp2_bpool_get_buff(hif, q->priv->bpool, &inf);
1394                 addr = cookie_addr_high | inf.cookie;
1395                 rte_pktmbuf_free((struct rte_mbuf *)addr);
1396         }
1397
1398         rte_free(q);
1399 }
1400
1401 /**
1402  * DPDK callback to configure the transmit queue.
1403  *
1404  * @param dev
1405  *   Pointer to Ethernet device structure.
1406  * @param idx
1407  *   Transmit queue index.
1408  * @param desc
1409  *   Number of descriptors to configure in the queue.
1410  * @param socket
1411  *   NUMA socket on which memory must be allocated.
1412  * @param conf
1413  *   Thresholds parameters (unused).
1414  *
1415  * @return
1416  *   0 on success, negative error value otherwise.
1417  */
1418 static int
1419 mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1420                     unsigned int socket,
1421                     const struct rte_eth_txconf *conf __rte_unused)
1422 {
1423         struct mrvl_priv *priv = dev->data->dev_private;
1424         struct mrvl_txq *txq;
1425
1426         if (dev->data->tx_queues[idx]) {
1427                 rte_free(dev->data->tx_queues[idx]);
1428                 dev->data->tx_queues[idx] = NULL;
1429         }
1430
1431         txq = rte_zmalloc_socket("txq", sizeof(*txq), 0, socket);
1432         if (!txq)
1433                 return -ENOMEM;
1434
1435         txq->priv = priv;
1436         txq->queue_id = idx;
1437         txq->port_id = dev->data->port_id;
1438         dev->data->tx_queues[idx] = txq;
1439
1440         priv->ppio_params.outqs_params.outqs_params[idx].size = desc;
1441         priv->ppio_params.outqs_params.outqs_params[idx].weight = 1;
1442
1443         return 0;
1444 }
1445
1446 /**
1447  * DPDK callback to release the transmit queue.
1448  *
1449  * @param txq
1450  *   Generic transmit queue pointer.
1451  */
1452 static void
1453 mrvl_tx_queue_release(void *txq)
1454 {
1455         struct mrvl_txq *q = txq;
1456
1457         if (!q)
1458                 return;
1459
1460         rte_free(q);
1461 }
1462
1463 /**
1464  * Update RSS hash configuration
1465  *
1466  * @param dev
1467  *   Pointer to Ethernet device structure.
1468  * @param rss_conf
1469  *   Pointer to RSS configuration.
1470  *
1471  * @return
1472  *   0 on success, negative error value otherwise.
1473  */
1474 static int
1475 mrvl_rss_hash_update(struct rte_eth_dev *dev,
1476                      struct rte_eth_rss_conf *rss_conf)
1477 {
1478         struct mrvl_priv *priv = dev->data->dev_private;
1479
1480         return mrvl_configure_rss(priv, rss_conf);
1481 }
1482
1483 /**
1484  * DPDK callback to get RSS hash configuration.
1485  *
1486  * @param dev
1487  *   Pointer to Ethernet device structure.
1488  * @rss_conf
1489  *   Pointer to RSS configuration.
1490  *
1491  * @return
1492  *   Always 0.
1493  */
1494 static int
1495 mrvl_rss_hash_conf_get(struct rte_eth_dev *dev,
1496                        struct rte_eth_rss_conf *rss_conf)
1497 {
1498         struct mrvl_priv *priv = dev->data->dev_private;
1499         enum pp2_ppio_hash_type hash_type =
1500                 priv->ppio_params.inqs_params.hash_type;
1501
1502         rss_conf->rss_key = NULL;
1503
1504         if (hash_type == PP2_PPIO_HASH_T_NONE)
1505                 rss_conf->rss_hf = 0;
1506         else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE)
1507                 rss_conf->rss_hf = ETH_RSS_IPV4;
1508         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp)
1509                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP;
1510         else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp)
1511                 rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP;
1512
1513         return 0;
1514 }
1515
1516 static const struct eth_dev_ops mrvl_ops = {
1517         .dev_configure = mrvl_dev_configure,
1518         .dev_start = mrvl_dev_start,
1519         .dev_stop = mrvl_dev_stop,
1520         .dev_set_link_up = mrvl_dev_set_link_up,
1521         .dev_set_link_down = mrvl_dev_set_link_down,
1522         .dev_close = mrvl_dev_close,
1523         .link_update = mrvl_link_update,
1524         .promiscuous_enable = mrvl_promiscuous_enable,
1525         .allmulticast_enable = mrvl_allmulticast_enable,
1526         .promiscuous_disable = mrvl_promiscuous_disable,
1527         .allmulticast_disable = mrvl_allmulticast_disable,
1528         .mac_addr_remove = mrvl_mac_addr_remove,
1529         .mac_addr_add = mrvl_mac_addr_add,
1530         .mac_addr_set = mrvl_mac_addr_set,
1531         .mtu_set = mrvl_mtu_set,
1532         .stats_get = mrvl_stats_get,
1533         .stats_reset = mrvl_stats_reset,
1534         .dev_infos_get = mrvl_dev_infos_get,
1535         .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get,
1536         .rxq_info_get = mrvl_rxq_info_get,
1537         .txq_info_get = mrvl_txq_info_get,
1538         .vlan_filter_set = mrvl_vlan_filter_set,
1539         .rx_queue_setup = mrvl_rx_queue_setup,
1540         .rx_queue_release = mrvl_rx_queue_release,
1541         .tx_queue_setup = mrvl_tx_queue_setup,
1542         .tx_queue_release = mrvl_tx_queue_release,
1543         .rss_hash_update = mrvl_rss_hash_update,
1544         .rss_hash_conf_get = mrvl_rss_hash_conf_get,
1545 };
1546
1547 /**
1548  * Return packet type information and l3/l4 offsets.
1549  *
1550  * @param desc
1551  *   Pointer to the received packet descriptor.
1552  * @param l3_offset
1553  *   l3 packet offset.
1554  * @param l4_offset
1555  *   l4 packet offset.
1556  *
1557  * @return
1558  *   Packet type information.
1559  */
1560 static inline uint64_t
1561 mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc,
1562                                     uint8_t *l3_offset, uint8_t *l4_offset)
1563 {
1564         enum pp2_inq_l3_type l3_type;
1565         enum pp2_inq_l4_type l4_type;
1566         uint64_t packet_type;
1567
1568         pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset);
1569         pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset);
1570
1571         packet_type = RTE_PTYPE_L2_ETHER;
1572
1573         switch (l3_type) {
1574         case PP2_INQ_L3_TYPE_IPV4_NO_OPTS:
1575                 packet_type |= RTE_PTYPE_L3_IPV4;
1576                 break;
1577         case PP2_INQ_L3_TYPE_IPV4_OK:
1578                 packet_type |= RTE_PTYPE_L3_IPV4_EXT;
1579                 break;
1580         case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO:
1581                 packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
1582                 break;
1583         case PP2_INQ_L3_TYPE_IPV6_NO_EXT:
1584                 packet_type |= RTE_PTYPE_L3_IPV6;
1585                 break;
1586         case PP2_INQ_L3_TYPE_IPV6_EXT:
1587                 packet_type |= RTE_PTYPE_L3_IPV6_EXT;
1588                 break;
1589         case PP2_INQ_L3_TYPE_ARP:
1590                 packet_type |= RTE_PTYPE_L2_ETHER_ARP;
1591                 /*
1592                  * In case of ARP l4_offset is set to wrong value.
1593                  * Set it to proper one so that later on mbuf->l3_len can be
1594                  * calculated subtracting l4_offset and l3_offset.
1595                  */
1596                 *l4_offset = *l3_offset + MRVL_ARP_LENGTH;
1597                 break;
1598         default:
1599                 RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n");
1600                 break;
1601         }
1602
1603         switch (l4_type) {
1604         case PP2_INQ_L4_TYPE_TCP:
1605                 packet_type |= RTE_PTYPE_L4_TCP;
1606                 break;
1607         case PP2_INQ_L4_TYPE_UDP:
1608                 packet_type |= RTE_PTYPE_L4_UDP;
1609                 break;
1610         default:
1611                 RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n");
1612                 break;
1613         }
1614
1615         return packet_type;
1616 }
1617
1618 /**
1619  * Get offload information from the received packet descriptor.
1620  *
1621  * @param desc
1622  *   Pointer to the received packet descriptor.
1623  *
1624  * @return
1625  *   Mbuf offload flags.
1626  */
1627 static inline uint64_t
1628 mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc)
1629 {
1630         uint64_t flags;
1631         enum pp2_inq_desc_status status;
1632
1633         status = pp2_ppio_inq_desc_get_l3_pkt_error(desc);
1634         if (unlikely(status != PP2_DESC_ERR_OK))
1635                 flags = PKT_RX_IP_CKSUM_BAD;
1636         else
1637                 flags = PKT_RX_IP_CKSUM_GOOD;
1638
1639         status = pp2_ppio_inq_desc_get_l4_pkt_error(desc);
1640         if (unlikely(status != PP2_DESC_ERR_OK))
1641                 flags |= PKT_RX_L4_CKSUM_BAD;
1642         else
1643                 flags |= PKT_RX_L4_CKSUM_GOOD;
1644
1645         return flags;
1646 }
1647
1648 /**
1649  * DPDK callback for receive.
1650  *
1651  * @param rxq
1652  *   Generic pointer to the receive queue.
1653  * @param rx_pkts
1654  *   Array to store received packets.
1655  * @param nb_pkts
1656  *   Maximum number of packets in array.
1657  *
1658  * @return
1659  *   Number of packets successfully received.
1660  */
1661 static uint16_t
1662 mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1663 {
1664         struct mrvl_rxq *q = rxq;
1665         struct pp2_ppio_desc descs[nb_pkts];
1666         struct pp2_bpool *bpool;
1667         int i, ret, rx_done = 0;
1668         int num;
1669         struct pp2_hif *hif;
1670         unsigned int core_id = rte_lcore_id();
1671
1672         hif = mrvl_get_hif(q->priv, core_id);
1673
1674         if (unlikely(!q->priv->ppio || !hif))
1675                 return 0;
1676
1677         bpool = q->priv->bpool;
1678
1679         ret = pp2_ppio_recv(q->priv->ppio, q->priv->rxq_map[q->queue_id].tc,
1680                             q->priv->rxq_map[q->queue_id].inq, descs, &nb_pkts);
1681         if (unlikely(ret < 0)) {
1682                 RTE_LOG(ERR, PMD, "Failed to receive packets\n");
1683                 return 0;
1684         }
1685         mrvl_port_bpool_size[bpool->pp2_id][bpool->id][core_id] -= nb_pkts;
1686
1687         for (i = 0; i < nb_pkts; i++) {
1688                 struct rte_mbuf *mbuf;
1689                 uint8_t l3_offset, l4_offset;
1690                 enum pp2_inq_desc_status status;
1691                 uint64_t addr;
1692
1693                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1694                         struct pp2_ppio_desc *pref_desc;
1695                         u64 pref_addr;
1696
1697                         pref_desc = &descs[i + MRVL_MUSDK_PREFETCH_SHIFT];
1698                         pref_addr = cookie_addr_high |
1699                                     pp2_ppio_inq_desc_get_cookie(pref_desc);
1700                         rte_mbuf_prefetch_part1((struct rte_mbuf *)(pref_addr));
1701                         rte_mbuf_prefetch_part2((struct rte_mbuf *)(pref_addr));
1702                 }
1703
1704                 addr = cookie_addr_high |
1705                        pp2_ppio_inq_desc_get_cookie(&descs[i]);
1706                 mbuf = (struct rte_mbuf *)addr;
1707                 rte_pktmbuf_reset(mbuf);
1708
1709                 /* drop packet in case of mac, overrun or resource error */
1710                 status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]);
1711                 if (unlikely(status != PP2_DESC_ERR_OK)) {
1712                         struct pp2_buff_inf binf = {
1713                                 .addr = rte_mbuf_data_iova_default(mbuf),
1714                                 .cookie = (pp2_cookie_t)(uint64_t)mbuf,
1715                         };
1716
1717                         pp2_bpool_put_buff(hif, bpool, &binf);
1718                         mrvl_port_bpool_size
1719                                 [bpool->pp2_id][bpool->id][core_id]++;
1720                         q->drop_mac++;
1721                         continue;
1722                 }
1723
1724                 mbuf->data_off += MRVL_PKT_EFFEC_OFFS;
1725                 mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]);
1726                 mbuf->data_len = mbuf->pkt_len;
1727                 mbuf->port = q->port_id;
1728                 mbuf->packet_type =
1729                         mrvl_desc_to_packet_type_and_offset(&descs[i],
1730                                                             &l3_offset,
1731                                                             &l4_offset);
1732                 mbuf->l2_len = l3_offset;
1733                 mbuf->l3_len = l4_offset - l3_offset;
1734
1735                 if (likely(q->cksum_enabled))
1736                         mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]);
1737
1738                 rx_pkts[rx_done++] = mbuf;
1739                 q->bytes_recv += mbuf->pkt_len;
1740         }
1741
1742         if (rte_spinlock_trylock(&q->priv->lock) == 1) {
1743                 num = mrvl_get_bpool_size(bpool->pp2_id, bpool->id);
1744
1745                 if (unlikely(num <= q->priv->bpool_min_size ||
1746                              (!rx_done && num < q->priv->bpool_init_size))) {
1747                         ret = mrvl_fill_bpool(q, MRVL_BURST_SIZE);
1748                         if (ret)
1749                                 RTE_LOG(ERR, PMD, "Failed to fill bpool\n");
1750                 } else if (unlikely(num > q->priv->bpool_max_size)) {
1751                         int i;
1752                         int pkt_to_remove = num - q->priv->bpool_init_size;
1753                         struct rte_mbuf *mbuf;
1754                         struct pp2_buff_inf buff;
1755
1756                         RTE_LOG(DEBUG, PMD,
1757                                 "\nport-%d:%d: bpool %d oversize - remove %d buffers (pool size: %d -> %d)\n",
1758                                 bpool->pp2_id, q->priv->ppio->port_id,
1759                                 bpool->id, pkt_to_remove, num,
1760                                 q->priv->bpool_init_size);
1761
1762                         for (i = 0; i < pkt_to_remove; i++) {
1763                                 ret = pp2_bpool_get_buff(hif, bpool, &buff);
1764                                 if (ret)
1765                                         break;
1766                                 mbuf = (struct rte_mbuf *)
1767                                         (cookie_addr_high | buff.cookie);
1768                                 rte_pktmbuf_free(mbuf);
1769                         }
1770                         mrvl_port_bpool_size
1771                                 [bpool->pp2_id][bpool->id][core_id] -= i;
1772                 }
1773                 rte_spinlock_unlock(&q->priv->lock);
1774         }
1775
1776         return rx_done;
1777 }
1778
1779 /**
1780  * Prepare offload information.
1781  *
1782  * @param ol_flags
1783  *   Offload flags.
1784  * @param packet_type
1785  *   Packet type bitfield.
1786  * @param l3_type
1787  *   Pointer to the pp2_ouq_l3_type structure.
1788  * @param l4_type
1789  *   Pointer to the pp2_outq_l4_type structure.
1790  * @param gen_l3_cksum
1791  *   Will be set to 1 in case l3 checksum is computed.
1792  * @param l4_cksum
1793  *   Will be set to 1 in case l4 checksum is computed.
1794  *
1795  * @return
1796  *   0 on success, negative error value otherwise.
1797  */
1798 static inline int
1799 mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type,
1800                         enum pp2_outq_l3_type *l3_type,
1801                         enum pp2_outq_l4_type *l4_type,
1802                         int *gen_l3_cksum,
1803                         int *gen_l4_cksum)
1804 {
1805         /*
1806          * Based on ol_flags prepare information
1807          * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor
1808          * for offloading.
1809          */
1810         if (ol_flags & PKT_TX_IPV4) {
1811                 *l3_type = PP2_OUTQ_L3_TYPE_IPV4;
1812                 *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0;
1813         } else if (ol_flags & PKT_TX_IPV6) {
1814                 *l3_type = PP2_OUTQ_L3_TYPE_IPV6;
1815                 /* no checksum for ipv6 header */
1816                 *gen_l3_cksum = 0;
1817         } else {
1818                 /* if something different then stop processing */
1819                 return -1;
1820         }
1821
1822         ol_flags &= PKT_TX_L4_MASK;
1823         if ((packet_type & RTE_PTYPE_L4_TCP) &&
1824             ol_flags == PKT_TX_TCP_CKSUM) {
1825                 *l4_type = PP2_OUTQ_L4_TYPE_TCP;
1826                 *gen_l4_cksum = 1;
1827         } else if ((packet_type & RTE_PTYPE_L4_UDP) &&
1828                    ol_flags == PKT_TX_UDP_CKSUM) {
1829                 *l4_type = PP2_OUTQ_L4_TYPE_UDP;
1830                 *gen_l4_cksum = 1;
1831         } else {
1832                 *l4_type = PP2_OUTQ_L4_TYPE_OTHER;
1833                 /* no checksum for other type */
1834                 *gen_l4_cksum = 0;
1835         }
1836
1837         return 0;
1838 }
1839
1840 /**
1841  * Release already sent buffers to bpool (buffer-pool).
1842  *
1843  * @param ppio
1844  *   Pointer to the port structure.
1845  * @param hif
1846  *   Pointer to the MUSDK hardware interface.
1847  * @param sq
1848  *   Pointer to the shadow queue.
1849  * @param qid
1850  *   Queue id number.
1851  * @param force
1852  *   Force releasing packets.
1853  */
1854 static inline void
1855 mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif,
1856                        unsigned int core_id, struct mrvl_shadow_txq *sq,
1857                        int qid, int force)
1858 {
1859         struct buff_release_entry *entry;
1860         uint16_t nb_done = 0, num = 0, skip_bufs = 0;
1861         int i;
1862
1863         pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done);
1864
1865         sq->num_to_release += nb_done;
1866
1867         if (likely(!force &&
1868                    sq->num_to_release < MRVL_PP2_BUF_RELEASE_BURST_SIZE))
1869                 return;
1870
1871         nb_done = sq->num_to_release;
1872         sq->num_to_release = 0;
1873
1874         for (i = 0; i < nb_done; i++) {
1875                 entry = &sq->ent[sq->tail + num];
1876                 if (unlikely(!entry->buff.addr)) {
1877                         RTE_LOG(ERR, PMD,
1878                                 "Shadow memory @%d: cookie(%lx), pa(%lx)!\n",
1879                                 sq->tail, (u64)entry->buff.cookie,
1880                                 (u64)entry->buff.addr);
1881                         skip_bufs = 1;
1882                         goto skip;
1883                 }
1884
1885                 if (unlikely(!entry->bpool)) {
1886                         struct rte_mbuf *mbuf;
1887
1888                         mbuf = (struct rte_mbuf *)
1889                                (cookie_addr_high | entry->buff.cookie);
1890                         rte_pktmbuf_free(mbuf);
1891                         skip_bufs = 1;
1892                         goto skip;
1893                 }
1894
1895                 mrvl_port_bpool_size
1896                         [entry->bpool->pp2_id][entry->bpool->id][core_id]++;
1897                 num++;
1898                 if (unlikely(sq->tail + num == MRVL_PP2_TX_SHADOWQ_SIZE))
1899                         goto skip;
1900                 continue;
1901 skip:
1902                 if (likely(num))
1903                         pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1904                 num += skip_bufs;
1905                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1906                 sq->size -= num;
1907                 num = 0;
1908                 skip_bufs = 0;
1909         }
1910
1911         if (likely(num)) {
1912                 pp2_bpool_put_buffs(hif, &sq->ent[sq->tail], &num);
1913                 sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK;
1914                 sq->size -= num;
1915         }
1916 }
1917
1918 /**
1919  * DPDK callback for transmit.
1920  *
1921  * @param txq
1922  *   Generic pointer transmit queue.
1923  * @param tx_pkts
1924  *   Packets to transmit.
1925  * @param nb_pkts
1926  *   Number of packets in array.
1927  *
1928  * @return
1929  *   Number of packets successfully transmitted.
1930  */
1931 static uint16_t
1932 mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1933 {
1934         struct mrvl_txq *q = txq;
1935         struct mrvl_shadow_txq *sq;
1936         struct pp2_hif *hif;
1937         struct pp2_ppio_desc descs[nb_pkts];
1938         unsigned int core_id = rte_lcore_id();
1939         int i, ret, bytes_sent = 0;
1940         uint16_t num, sq_free_size;
1941         uint64_t addr;
1942
1943         hif = mrvl_get_hif(q->priv, core_id);
1944         sq = &q->shadow_txqs[core_id];
1945
1946         if (unlikely(!q->priv->ppio || !hif))
1947                 return 0;
1948
1949         if (sq->size)
1950                 mrvl_free_sent_buffers(q->priv->ppio, hif, core_id,
1951                                        sq, q->queue_id, 0);
1952
1953         sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1;
1954         if (unlikely(nb_pkts > sq_free_size)) {
1955                 RTE_LOG(DEBUG, PMD,
1956                         "No room in shadow queue for %d packets! %d packets will be sent.\n",
1957                         nb_pkts, sq_free_size);
1958                 nb_pkts = sq_free_size;
1959         }
1960
1961         for (i = 0; i < nb_pkts; i++) {
1962                 struct rte_mbuf *mbuf = tx_pkts[i];
1963                 int gen_l3_cksum, gen_l4_cksum;
1964                 enum pp2_outq_l3_type l3_type;
1965                 enum pp2_outq_l4_type l4_type;
1966
1967                 if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) {
1968                         struct rte_mbuf *pref_pkt_hdr;
1969
1970                         pref_pkt_hdr = tx_pkts[i + MRVL_MUSDK_PREFETCH_SHIFT];
1971                         rte_mbuf_prefetch_part1(pref_pkt_hdr);
1972                         rte_mbuf_prefetch_part2(pref_pkt_hdr);
1973                 }
1974
1975                 sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;
1976                 sq->ent[sq->head].buff.addr =
1977                         rte_mbuf_data_iova_default(mbuf);
1978                 sq->ent[sq->head].bpool =
1979                         (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ?
1980                          NULL : mrvl_port_to_bpool_lookup[mbuf->port];
1981                 sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK;
1982                 sq->size++;
1983
1984                 pp2_ppio_outq_desc_reset(&descs[i]);
1985                 pp2_ppio_outq_desc_set_phys_addr(&descs[i],
1986                                                  rte_pktmbuf_iova(mbuf));
1987                 pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0);
1988                 pp2_ppio_outq_desc_set_pkt_len(&descs[i],
1989                                                rte_pktmbuf_pkt_len(mbuf));
1990
1991                 bytes_sent += rte_pktmbuf_pkt_len(mbuf);
1992                 /*
1993                  * in case unsupported ol_flags were passed
1994                  * do not update descriptor offload information
1995                  */
1996                 ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type,
1997                                               &l3_type, &l4_type, &gen_l3_cksum,
1998                                               &gen_l4_cksum);
1999                 if (unlikely(ret))
2000                         continue;
2001
2002                 pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type,
2003                                                   mbuf->l2_len,
2004                                                   mbuf->l2_len + mbuf->l3_len,
2005                                                   gen_l3_cksum, gen_l4_cksum);
2006         }
2007
2008         num = nb_pkts;
2009         pp2_ppio_send(q->priv->ppio, hif, q->queue_id, descs, &nb_pkts);
2010         /* number of packets that were not sent */
2011         if (unlikely(num > nb_pkts)) {
2012                 for (i = nb_pkts; i < num; i++) {
2013                         sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) &
2014                                 MRVL_PP2_TX_SHADOWQ_MASK;
2015                         addr = cookie_addr_high | sq->ent[sq->head].buff.cookie;
2016                         bytes_sent -=
2017                                 rte_pktmbuf_pkt_len((struct rte_mbuf *)addr);
2018                 }
2019                 sq->size -= num - nb_pkts;
2020         }
2021
2022         q->bytes_sent += bytes_sent;
2023
2024         return nb_pkts;
2025 }
2026
2027 /**
2028  * Initialize packet processor.
2029  *
2030  * @return
2031  *   0 on success, negative error value otherwise.
2032  */
2033 static int
2034 mrvl_init_pp2(void)
2035 {
2036         struct pp2_init_params init_params;
2037
2038         memset(&init_params, 0, sizeof(init_params));
2039         init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED;
2040         init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED;
2041         init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED;
2042
2043         return pp2_init(&init_params);
2044 }
2045
2046 /**
2047  * Deinitialize packet processor.
2048  *
2049  * @return
2050  *   0 on success, negative error value otherwise.
2051  */
2052 static void
2053 mrvl_deinit_pp2(void)
2054 {
2055         pp2_deinit();
2056 }
2057
2058 /**
2059  * Create private device structure.
2060  *
2061  * @param dev_name
2062  *   Pointer to the port name passed in the initialization parameters.
2063  *
2064  * @return
2065  *   Pointer to the newly allocated private device structure.
2066  */
2067 static struct mrvl_priv *
2068 mrvl_priv_create(const char *dev_name)
2069 {
2070         struct pp2_bpool_params bpool_params;
2071         char match[MRVL_MATCH_LEN];
2072         struct mrvl_priv *priv;
2073         int ret, bpool_bit;
2074
2075         priv = rte_zmalloc_socket(dev_name, sizeof(*priv), 0, rte_socket_id());
2076         if (!priv)
2077                 return NULL;
2078
2079         ret = pp2_netdev_get_ppio_info((char *)(uintptr_t)dev_name,
2080                                        &priv->pp_id, &priv->ppio_id);
2081         if (ret)
2082                 goto out_free_priv;
2083
2084         bpool_bit = mrvl_reserve_bit(&used_bpools[priv->pp_id],
2085                                      PP2_BPOOL_NUM_POOLS);
2086         if (bpool_bit < 0)
2087                 goto out_free_priv;
2088         priv->bpool_bit = bpool_bit;
2089
2090         snprintf(match, sizeof(match), "pool-%d:%d", priv->pp_id,
2091                  priv->bpool_bit);
2092         memset(&bpool_params, 0, sizeof(bpool_params));
2093         bpool_params.match = match;
2094         bpool_params.buff_len = MRVL_PKT_SIZE_MAX + MRVL_PKT_EFFEC_OFFS;
2095         ret = pp2_bpool_init(&bpool_params, &priv->bpool);
2096         if (ret)
2097                 goto out_clear_bpool_bit;
2098
2099         priv->ppio_params.type = PP2_PPIO_T_NIC;
2100         rte_spinlock_init(&priv->lock);
2101
2102         return priv;
2103 out_clear_bpool_bit:
2104         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2105 out_free_priv:
2106         rte_free(priv);
2107         return NULL;
2108 }
2109
2110 /**
2111  * Create device representing Ethernet port.
2112  *
2113  * @param name
2114  *   Pointer to the port's name.
2115  *
2116  * @return
2117  *   0 on success, negative error value otherwise.
2118  */
2119 static int
2120 mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name)
2121 {
2122         int ret, fd = socket(AF_INET, SOCK_DGRAM, 0);
2123         struct rte_eth_dev *eth_dev;
2124         struct mrvl_priv *priv;
2125         struct ifreq req;
2126
2127         eth_dev = rte_eth_dev_allocate(name);
2128         if (!eth_dev)
2129                 return -ENOMEM;
2130
2131         priv = mrvl_priv_create(name);
2132         if (!priv) {
2133                 ret = -ENOMEM;
2134                 goto out_free_dev;
2135         }
2136
2137         eth_dev->data->mac_addrs =
2138                 rte_zmalloc("mac_addrs",
2139                             ETHER_ADDR_LEN * MRVL_MAC_ADDRS_MAX, 0);
2140         if (!eth_dev->data->mac_addrs) {
2141                 RTE_LOG(ERR, PMD, "Failed to allocate space for eth addrs\n");
2142                 ret = -ENOMEM;
2143                 goto out_free_priv;
2144         }
2145
2146         memset(&req, 0, sizeof(req));
2147         strcpy(req.ifr_name, name);
2148         ret = ioctl(fd, SIOCGIFHWADDR, &req);
2149         if (ret)
2150                 goto out_free_mac;
2151
2152         memcpy(eth_dev->data->mac_addrs[0].addr_bytes,
2153                req.ifr_addr.sa_data, ETHER_ADDR_LEN);
2154
2155         eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst;
2156         eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst;
2157         eth_dev->data->kdrv = RTE_KDRV_NONE;
2158         eth_dev->data->dev_private = priv;
2159         eth_dev->device = &vdev->device;
2160         eth_dev->dev_ops = &mrvl_ops;
2161
2162         return 0;
2163 out_free_mac:
2164         rte_free(eth_dev->data->mac_addrs);
2165 out_free_dev:
2166         rte_eth_dev_release_port(eth_dev);
2167 out_free_priv:
2168         rte_free(priv);
2169
2170         return ret;
2171 }
2172
2173 /**
2174  * Cleanup previously created device representing Ethernet port.
2175  *
2176  * @param name
2177  *   Pointer to the port name.
2178  */
2179 static void
2180 mrvl_eth_dev_destroy(const char *name)
2181 {
2182         struct rte_eth_dev *eth_dev;
2183         struct mrvl_priv *priv;
2184
2185         eth_dev = rte_eth_dev_allocated(name);
2186         if (!eth_dev)
2187                 return;
2188
2189         priv = eth_dev->data->dev_private;
2190         pp2_bpool_deinit(priv->bpool);
2191         used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit);
2192         rte_free(priv);
2193         rte_free(eth_dev->data->mac_addrs);
2194         rte_eth_dev_release_port(eth_dev);
2195 }
2196
2197 /**
2198  * Callback used by rte_kvargs_process() during argument parsing.
2199  *
2200  * @param key
2201  *   Pointer to the parsed key (unused).
2202  * @param value
2203  *   Pointer to the parsed value.
2204  * @param extra_args
2205  *   Pointer to the extra arguments which contains address of the
2206  *   table of pointers to parsed interface names.
2207  *
2208  * @return
2209  *   Always 0.
2210  */
2211 static int
2212 mrvl_get_ifnames(const char *key __rte_unused, const char *value,
2213                  void *extra_args)
2214 {
2215         struct mrvl_ifnames *ifnames = extra_args;
2216
2217         ifnames->names[ifnames->idx++] = value;
2218
2219         return 0;
2220 }
2221
2222 /**
2223  * Deinitialize per-lcore MUSDK hardware interfaces (hifs).
2224  */
2225 static void
2226 mrvl_deinit_hifs(void)
2227 {
2228         int i;
2229
2230         for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) {
2231                 if (hifs[i])
2232                         pp2_hif_deinit(hifs[i]);
2233         }
2234         used_hifs = MRVL_MUSDK_HIFS_RESERVED;
2235         memset(hifs, 0, sizeof(hifs));
2236 }
2237
2238 /**
2239  * DPDK callback to register the virtual device.
2240  *
2241  * @param vdev
2242  *   Pointer to the virtual device.
2243  *
2244  * @return
2245  *   0 on success, negative error value otherwise.
2246  */
2247 static int
2248 rte_pmd_mrvl_probe(struct rte_vdev_device *vdev)
2249 {
2250         struct rte_kvargs *kvlist;
2251         struct mrvl_ifnames ifnames;
2252         int ret = -EINVAL;
2253         uint32_t i, ifnum, cfgnum;
2254         const char *params;
2255
2256         params = rte_vdev_device_args(vdev);
2257         if (!params)
2258                 return -EINVAL;
2259
2260         kvlist = rte_kvargs_parse(params, valid_args);
2261         if (!kvlist)
2262                 return -EINVAL;
2263
2264         ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG);
2265         if (ifnum > RTE_DIM(ifnames.names))
2266                 goto out_free_kvlist;
2267
2268         ifnames.idx = 0;
2269         rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG,
2270                            mrvl_get_ifnames, &ifnames);
2271
2272
2273         /*
2274          * The below system initialization should be done only once,
2275          * on the first provided configuration file
2276          */
2277         if (!mrvl_qos_cfg) {
2278                 cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG);
2279                 RTE_LOG(INFO, PMD, "Parsing config file!\n");
2280                 if (cfgnum > 1) {
2281                         RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n");
2282                         goto out_free_kvlist;
2283                 } else if (cfgnum == 1) {
2284                         rte_kvargs_process(kvlist, MRVL_CFG_ARG,
2285                                            mrvl_get_qoscfg, &mrvl_qos_cfg);
2286                 }
2287         }
2288
2289         if (mrvl_dev_num)
2290                 goto init_devices;
2291
2292         RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n");
2293         /*
2294          * ret == -EEXIST is correct, it means DMA
2295          * has been already initialized (by another PMD).
2296          */
2297         ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE);
2298         if (ret < 0) {
2299                 if (ret != -EEXIST)
2300                         goto out_free_kvlist;
2301                 else
2302                         RTE_LOG(INFO, PMD,
2303                                 "DMA memory has been already initialized by a different driver.\n");
2304         }
2305
2306         ret = mrvl_init_pp2();
2307         if (ret) {
2308                 RTE_LOG(ERR, PMD, "Failed to init PP!\n");
2309                 goto out_deinit_dma;
2310         }
2311
2312         memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size));
2313
2314         mrvl_lcore_first = RTE_MAX_LCORE;
2315         mrvl_lcore_last = 0;
2316
2317 init_devices:
2318         for (i = 0; i < ifnum; i++) {
2319                 RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]);
2320                 ret = mrvl_eth_dev_create(vdev, ifnames.names[i]);
2321                 if (ret)
2322                         goto out_cleanup;
2323         }
2324         mrvl_dev_num += ifnum;
2325
2326         rte_kvargs_free(kvlist);
2327
2328         return 0;
2329 out_cleanup:
2330         for (; i > 0; i--)
2331                 mrvl_eth_dev_destroy(ifnames.names[i]);
2332
2333         if (mrvl_dev_num == 0)
2334                 mrvl_deinit_pp2();
2335 out_deinit_dma:
2336         if (mrvl_dev_num == 0)
2337                 mv_sys_dma_mem_destroy();
2338 out_free_kvlist:
2339         rte_kvargs_free(kvlist);
2340
2341         return ret;
2342 }
2343
2344 /**
2345  * DPDK callback to remove virtual device.
2346  *
2347  * @param vdev
2348  *   Pointer to the removed virtual device.
2349  *
2350  * @return
2351  *   0 on success, negative error value otherwise.
2352  */
2353 static int
2354 rte_pmd_mrvl_remove(struct rte_vdev_device *vdev)
2355 {
2356         int i;
2357         const char *name;
2358
2359         name = rte_vdev_device_name(vdev);
2360         if (!name)
2361                 return -EINVAL;
2362
2363         RTE_LOG(INFO, PMD, "Removing %s\n", name);
2364
2365         for (i = 0; i < rte_eth_dev_count(); i++) {
2366                 char ifname[RTE_ETH_NAME_MAX_LEN];
2367
2368                 rte_eth_dev_get_name_by_port(i, ifname);
2369                 mrvl_eth_dev_destroy(ifname);
2370                 mrvl_dev_num--;
2371         }
2372
2373         if (mrvl_dev_num == 0) {
2374                 RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n");
2375                 mrvl_deinit_hifs();
2376                 mrvl_deinit_pp2();
2377                 mv_sys_dma_mem_destroy();
2378         }
2379
2380         return 0;
2381 }
2382
2383 static struct rte_vdev_driver pmd_mrvl_drv = {
2384         .probe = rte_pmd_mrvl_probe,
2385         .remove = rte_pmd_mrvl_remove,
2386 };
2387
2388 RTE_PMD_REGISTER_VDEV(net_mrvl, pmd_mrvl_drv);
2389 RTE_PMD_REGISTER_ALIAS(net_mrvl, eth_mrvl);