drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014-2018 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev_driver.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfpcore/nfp_cpp.h"
  59 #include "nfpcore/nfp_nffw.h"
  60 #include "nfpcore/nfp_hwinfo.h"
  61 #include "nfpcore/nfp_mip.h"
  62 #include "nfpcore/nfp_rtsym.h"
  63 #include "nfpcore/nfp_nsp.h"
  64
  65 #include "nfp_net_pmd.h"
  66 #include "nfp_net_logs.h"
  67 #include "nfp_net_ctrl.h"
  68
  69 /* Prototypes */
  70 static void nfp_net_close(struct rte_eth_dev *dev);
  71 static int nfp_net_configure(struct rte_eth_dev *dev);
  72 static void nfp_net_dev_interrupt_handler(void *param);
  73 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  74 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  75 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  76                               struct rte_eth_dev_info *dev_info);
  77 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  78 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  79 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  80 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  81 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  82 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  83                                        uint16_t queue_idx);
  84 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  85                                   uint16_t nb_pkts);
  86 static void nfp_net_rx_queue_release(void *rxq);
  87 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_rxconf *rx_conf,
  90                                   struct rte_mempool *mp);
  91 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  92 static void nfp_net_tx_queue_release(void *txq);
  93 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  94                                   uint16_t nb_desc, unsigned int socket_id,
  95                                   const struct rte_eth_txconf *tx_conf);
  96 static int nfp_net_start(struct rte_eth_dev *dev);
  97 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  98                               struct rte_eth_stats *stats);
  99 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
 100 static void nfp_net_stop(struct rte_eth_dev *dev);
 101 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 102                                   uint16_t nb_pkts);
 103
 104 static int nfp_net_rss_config_default(struct rte_eth_dev *dev);
 105 static int nfp_net_rss_hash_update(struct rte_eth_dev *dev,
 106                                    struct rte_eth_rss_conf *rss_conf);
 107 static int nfp_net_rss_reta_write(struct rte_eth_dev *dev,
 108                     struct rte_eth_rss_reta_entry64 *reta_conf,
 109                     uint16_t reta_size);
 110 static int nfp_net_rss_hash_write(struct rte_eth_dev *dev,
 111                         struct rte_eth_rss_conf *rss_conf);
 112 static int nfp_set_mac_addr(struct rte_eth_dev *dev,
 113                              struct ether_addr *mac_addr);
 114
 115 /* The offset of the queue controller queues in the PCIe Target */
 116 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
 117
 118 /* Maximum value which can be added to a queue with one transaction */
 119 #define NFP_QCP_MAX_ADD 0x7f
 120
 121 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 122         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 123
 124 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 125 enum nfp_qcp_ptr {
 126         NFP_QCP_READ_PTR = 0,
 127         NFP_QCP_WRITE_PTR
 128 };
 129
 130 /*
 131  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 132  * @q: Base address for queue structure
 133  * @ptr: Add to the Read or Write pointer
 134  * @val: Value to add to the queue pointer
 135  *
 136  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 137  */
 138 static inline void
 139 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 140 {
 141         uint32_t off;
 142
 143         if (ptr == NFP_QCP_READ_PTR)
 144                 off = NFP_QCP_QUEUE_ADD_RPTR;
 145         else
 146                 off = NFP_QCP_QUEUE_ADD_WPTR;
 147
 148         while (val > NFP_QCP_MAX_ADD) {
 149                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 150                 val -= NFP_QCP_MAX_ADD;
 151         }
 152
 153         nn_writel(rte_cpu_to_le_32(val), q + off);
 154 }
 155
 156 /*
 157  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 158  * @q:  Base address for queue structure
 159  * @ptr: Read or Write pointer
 160  */
 161 static inline uint32_t
 162 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 163 {
 164         uint32_t off;
 165         uint32_t val;
 166
 167         if (ptr == NFP_QCP_READ_PTR)
 168                 off = NFP_QCP_QUEUE_STS_LO;
 169         else
 170                 off = NFP_QCP_QUEUE_STS_HI;
 171
 172         val = rte_cpu_to_le_32(nn_readl(q + off));
 173
 174         if (ptr == NFP_QCP_READ_PTR)
 175                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 176         else
 177                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 178 }
 179
 180 /*
 181  * Functions to read/write from/to Config BAR
 182  * Performs any endian conversion necessary.
 183  */
 184 static inline uint8_t
 185 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 186 {
 187         return nn_readb(hw->ctrl_bar + off);
 188 }
 189
 190 static inline void
 191 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 192 {
 193         nn_writeb(val, hw->ctrl_bar + off);
 194 }
 195
 196 static inline uint32_t
 197 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 198 {
 199         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 200 }
 201
 202 static inline void
 203 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 204 {
 205         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 206 }
 207
 208 static inline uint64_t
 209 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 210 {
 211         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 212 }
 213
 214 static inline void
 215 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 216 {
 217         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 218 }
 219
 220 static void
 221 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 222 {
 223         unsigned i;
 224
 225         if (rxq->rxbufs == NULL)
 226                 return;
 227
 228         for (i = 0; i < rxq->rx_count; i++) {
 229                 if (rxq->rxbufs[i].mbuf) {
 230                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 231                         rxq->rxbufs[i].mbuf = NULL;
 232                 }
 233         }
 234 }
 235
 236 static void
 237 nfp_net_rx_queue_release(void *rx_queue)
 238 {
 239         struct nfp_net_rxq *rxq = rx_queue;
 240
 241         if (rxq) {
 242                 nfp_net_rx_queue_release_mbufs(rxq);
 243                 rte_free(rxq->rxbufs);
 244                 rte_free(rxq);
 245         }
 246 }
 247
 248 static void
 249 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 250 {
 251         nfp_net_rx_queue_release_mbufs(rxq);
 252         rxq->rd_p = 0;
 253         rxq->nb_rx_hold = 0;
 254 }
 255
 256 static void
 257 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 258 {
 259         unsigned i;
 260
 261         if (txq->txbufs == NULL)
 262                 return;
 263
 264         for (i = 0; i < txq->tx_count; i++) {
 265                 if (txq->txbufs[i].mbuf) {
 266                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 267                         txq->txbufs[i].mbuf = NULL;
 268                 }
 269         }
 270 }
 271
 272 static void
 273 nfp_net_tx_queue_release(void *tx_queue)
 274 {
 275         struct nfp_net_txq *txq = tx_queue;
 276
 277         if (txq) {
 278                 nfp_net_tx_queue_release_mbufs(txq);
 279                 rte_free(txq->txbufs);
 280                 rte_free(txq);
 281         }
 282 }
 283
 284 static void
 285 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 286 {
 287         nfp_net_tx_queue_release_mbufs(txq);
 288         txq->wr_p = 0;
 289         txq->rd_p = 0;
 290 }
 291
 292 static int
 293 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 294 {
 295         int cnt;
 296         uint32_t new;
 297         struct timespec wait;
 298
 299         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...",
 300                     hw->qcp_cfg);
 301
 302         if (hw->qcp_cfg == NULL)
 303                 rte_panic("Bad configuration queue pointer\n");
 304
 305         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 306
 307         wait.tv_sec = 0;
 308         wait.tv_nsec = 1000000;
 309
 310         PMD_DRV_LOG(DEBUG, "Polling for update ack...");
 311
 312         /* Poll update field, waiting for NFP to ack the config */
 313         for (cnt = 0; ; cnt++) {
 314                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 315                 if (new == 0)
 316                         break;
 317                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 318                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 319                         return -1;
 320                 }
 321                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 322                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 323                                           " %dms", update, cnt);
 324                         rte_panic("Exiting\n");
 325                 }
 326                 nanosleep(&wait, 0); /* waiting for a 1ms */
 327         }
 328         PMD_DRV_LOG(DEBUG, "Ack DONE");
 329         return 0;
 330 }
 331
 332 /*
 333  * Reconfigure the NIC
 334  * @nn:    device to reconfigure
 335  * @ctrl:    The value for the ctrl field in the BAR config
 336  * @update:  The value for the update field in the BAR config
 337  *
 338  * Write the update word to the BAR and ping the reconfig queue. Then poll
 339  * until the firmware has acknowledged the update by zeroing the update word.
 340  */
 341 static int
 342 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 343 {
 344         uint32_t err;
 345
 346         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x",
 347                     ctrl, update);
 348
 349         rte_spinlock_lock(&hw->reconfig_lock);
 350
 351         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 352         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 353
 354         rte_wmb();
 355
 356         err = __nfp_net_reconfig(hw, update);
 357
 358         rte_spinlock_unlock(&hw->reconfig_lock);
 359
 360         if (!err)
 361                 return 0;
 362
 363         /*
 364          * Reconfig errors imply situations where they can be handled.
 365          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 366          */
 367         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 368                      ctrl, update);
 369         return -EIO;
 370 }
 371
 372 /*
 373  * Configure an Ethernet device. This function must be invoked first
 374  * before any other function in the Ethernet API. This function can
 375  * also be re-invoked when a device is in the stopped state.
 376  */
 377 static int
 378 nfp_net_configure(struct rte_eth_dev *dev)
 379 {
 380         struct rte_eth_conf *dev_conf;
 381         struct rte_eth_rxmode *rxmode;
 382         struct rte_eth_txmode *txmode;
 383         struct nfp_net_hw *hw;
 384
 385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 386
 387         /*
 388          * A DPDK app sends info about how many queues to use and how
 389          * those queues need to be configured. This is used by the
 390          * DPDK core and it makes sure no more queues than those
 391          * advertised by the driver are requested. This function is
 392          * called after that internal process
 393          */
 394
 395         PMD_INIT_LOG(DEBUG, "Configure");
 396
 397         dev_conf = &dev->data->dev_conf;
 398         rxmode = &dev_conf->rxmode;
 399         txmode = &dev_conf->txmode;
 400
 401         /* Checking TX mode */
 402         if (txmode->mq_mode) {
 403                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 404                 return -EINVAL;
 405         }
 406
 407         /* Checking RX mode */
 408         if (rxmode->mq_mode & ETH_MQ_RX_RSS &&
 409             !(hw->cap & NFP_NET_CFG_CTRL_RSS)) {
 410                 PMD_INIT_LOG(INFO, "RSS not supported");
 411                 return -EINVAL;
 412         }
 413
 414         /* KEEP_CRC offload flag is not supported by PMD
 415          * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
 416          */
 417         if (rte_eth_dev_must_keep_crc(rxmode->offloads))
 418                 PMD_INIT_LOG(INFO, "HW does strip CRC. No configurable!");
 419
 420         return 0;
 421 }
 422
 423 static void
 424 nfp_net_enable_queues(struct rte_eth_dev *dev)
 425 {
 426         struct nfp_net_hw *hw;
 427         uint64_t enabled_queues = 0;
 428         int i;
 429
 430         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431
 432         /* Enabling the required TX queues in the device */
 433         for (i = 0; i < dev->data->nb_tx_queues; i++)
 434                 enabled_queues |= (1 << i);
 435
 436         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 437
 438         enabled_queues = 0;
 439
 440         /* Enabling the required RX queues in the device */
 441         for (i = 0; i < dev->data->nb_rx_queues; i++)
 442                 enabled_queues |= (1 << i);
 443
 444         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 445 }
 446
 447 static void
 448 nfp_net_disable_queues(struct rte_eth_dev *dev)
 449 {
 450         struct nfp_net_hw *hw;
 451         uint32_t new_ctrl, update = 0;
 452
 453         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 454
 455         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 456         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 457
 458         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 459         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 460                  NFP_NET_CFG_UPDATE_MSIX;
 461
 462         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 463                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 464
 465         /* If an error when reconfig we avoid to change hw state */
 466         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 467                 return;
 468
 469         hw->ctrl = new_ctrl;
 470 }
 471
 472 static int
 473 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 474 {
 475         int i;
 476
 477         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 478                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 479                         return -1;
 480         }
 481         return 0;
 482 }
 483
 484 static void
 485 nfp_net_params_setup(struct nfp_net_hw *hw)
 486 {
 487         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 488         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 489 }
 490
 491 static void
 492 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 493 {
 494         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 495 }
 496
 497 #define ETH_ADDR_LEN    6
 498
 499 static void
 500 nfp_eth_copy_mac(uint8_t *dst, const uint8_t *src)
 501 {
 502         int i;
 503
 504         for (i = 0; i < ETH_ADDR_LEN; i++)
 505                 dst[i] = src[i];
 506 }
 507
 508 static int
 509 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 510 {
 511         struct nfp_eth_table *nfp_eth_table;
 512
 513         nfp_eth_table = nfp_eth_read_ports(hw->cpp);
 514         /*
 515          * hw points to port0 private data. We need hw now pointing to
 516          * right port.
 517          */
 518         hw += port;
 519         nfp_eth_copy_mac((uint8_t *)&hw->mac_addr,
 520                          (uint8_t *)&nfp_eth_table->ports[port].mac_addr);
 521
 522         free(nfp_eth_table);
 523         return 0;
 524 }
 525
 526 static void
 527 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 528 {
 529         uint32_t tmp;
 530
 531         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 532         memcpy(&hw->mac_addr[0], &tmp, 4);
 533
 534         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 535         memcpy(&hw->mac_addr[4], &tmp, 2);
 536 }
 537
 538 static void
 539 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 540 {
 541         uint32_t mac0 = *(uint32_t *)mac;
 542         uint16_t mac1;
 543
 544         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 545
 546         mac += 4;
 547         mac1 = *(uint16_t *)mac;
 548         nn_writew(rte_cpu_to_be_16(mac1),
 549                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 550 }
 551
 552 int
 553 nfp_set_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 554 {
 555         struct nfp_net_hw *hw;
 556         uint32_t update, ctrl;
 557
 558         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 559         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 560             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR)) {
 561                 PMD_INIT_LOG(INFO, "MAC address unable to change when"
 562                                   " port enabled");
 563                 return -EBUSY;
 564         }
 565
 566         if ((hw->ctrl & NFP_NET_CFG_CTRL_ENABLE) &&
 567             !(hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR))
 568                 return -EBUSY;
 569
 570         /* Writing new MAC to the specific port BAR address */
 571         nfp_net_write_mac(hw, (uint8_t *)mac_addr);
 572
 573         /* Signal the NIC about the change */
 574         update = NFP_NET_CFG_UPDATE_MACADDR;
 575         ctrl = hw->ctrl | NFP_NET_CFG_CTRL_LIVE_ADDR;
 576         if (nfp_net_reconfig(hw, ctrl, update) < 0) {
 577                 PMD_INIT_LOG(INFO, "MAC address update failed");
 578                 return -EIO;
 579         }
 580         return 0;
 581 }
 582
 583 static int
 584 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 585                            struct rte_intr_handle *intr_handle)
 586 {
 587         struct nfp_net_hw *hw;
 588         int i;
 589
 590         if (!intr_handle->intr_vec) {
 591                 intr_handle->intr_vec =
 592                         rte_zmalloc("intr_vec",
 593                                     dev->data->nb_rx_queues * sizeof(int), 0);
 594                 if (!intr_handle->intr_vec) {
 595                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 596                                      " intr_vec", dev->data->nb_rx_queues);
 597                         return -ENOMEM;
 598                 }
 599         }
 600
 601         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 602
 603         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 604                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 605                 /* UIO just supports one queue and no LSC*/
 606                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 607                 intr_handle->intr_vec[0] = 0;
 608         } else {
 609                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 610                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 611                         /*
 612                          * The first msix vector is reserved for non
 613                          * efd interrupts
 614                         */
 615                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 616                         intr_handle->intr_vec[i] = i + 1;
 617                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d", i,
 618                                             intr_handle->intr_vec[i]);
 619                 }
 620         }
 621
 622         /* Avoiding TX interrupts */
 623         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 624         return 0;
 625 }
 626
 627 static uint32_t
 628 nfp_check_offloads(struct rte_eth_dev *dev)
 629 {
 630         struct nfp_net_hw *hw;
 631         struct rte_eth_conf *dev_conf;
 632         struct rte_eth_rxmode *rxmode;
 633         struct rte_eth_txmode *txmode;
 634         uint32_t ctrl = 0;
 635
 636         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 637
 638         dev_conf = &dev->data->dev_conf;
 639         rxmode = &dev_conf->rxmode;
 640         txmode = &dev_conf->txmode;
 641
 642         if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) {
 643                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
 644                         ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 645         }
 646
 647         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 648                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
 649                         ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 650         }
 651
 652         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
 653                 hw->mtu = rxmode->max_rx_pkt_len;
 654
 655         if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
 656                 ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 657
 658         /* L2 broadcast */
 659         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 660                 ctrl |= NFP_NET_CFG_CTRL_L2BC;
 661
 662         /* L2 multicast */
 663         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 664                 ctrl |= NFP_NET_CFG_CTRL_L2MC;
 665
 666         /* TX checksum offload */
 667         if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
 668             txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
 669             txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM)
 670                 ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 671
 672         /* LSO offload */
 673         if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
 674                 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 675                         ctrl |= NFP_NET_CFG_CTRL_LSO;
 676                 else
 677                         ctrl |= NFP_NET_CFG_CTRL_LSO2;
 678         }
 679
 680         /* RX gather */
 681         if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 682                 ctrl |= NFP_NET_CFG_CTRL_GATHER;
 683
 684         return ctrl;
 685 }
 686
 687 static int
 688 nfp_net_start(struct rte_eth_dev *dev)
 689 {
 690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 692         uint32_t new_ctrl, update = 0;
 693         struct nfp_net_hw *hw;
 694         struct rte_eth_conf *dev_conf;
 695         struct rte_eth_rxmode *rxmode;
 696         uint32_t intr_vector;
 697         int ret;
 698
 699         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 700
 701         PMD_INIT_LOG(DEBUG, "Start");
 702
 703         /* Disabling queues just in case... */
 704         nfp_net_disable_queues(dev);
 705
 706         /* Enabling the required queues in the device */
 707         nfp_net_enable_queues(dev);
 708
 709         /* check and configure queue intr-vector mapping */
 710         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 711                 if (hw->pf_multiport_enabled) {
 712                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 713                                           "with NFP multiport PF");
 714                                 return -EINVAL;
 715                 }
 716                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 717                         /*
 718                          * Better not to share LSC with RX interrupts.
 719                          * Unregistering LSC interrupt handler
 720                          */
 721                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 722                                 nfp_net_dev_interrupt_handler, (void *)dev);
 723
 724                         if (dev->data->nb_rx_queues > 1) {
 725                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 726                                              "supports 1 queue with UIO");
 727                                 return -EIO;
 728                         }
 729                 }
 730                 intr_vector = dev->data->nb_rx_queues;
 731                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 732                         return -1;
 733
 734                 nfp_configure_rx_interrupt(dev, intr_handle);
 735                 update = NFP_NET_CFG_UPDATE_MSIX;
 736         }
 737
 738         rte_intr_enable(intr_handle);
 739
 740         new_ctrl = nfp_check_offloads(dev);
 741
 742         /* Writing configuration parameters in the device */
 743         nfp_net_params_setup(hw);
 744
 745         dev_conf = &dev->data->dev_conf;
 746         rxmode = &dev_conf->rxmode;
 747
 748         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 749                 nfp_net_rss_config_default(dev);
 750                 update |= NFP_NET_CFG_UPDATE_RSS;
 751                 new_ctrl |= NFP_NET_CFG_CTRL_RSS;
 752         }
 753
 754         /* Enable device */
 755         new_ctrl |= NFP_NET_CFG_CTRL_ENABLE;
 756
 757         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 758
 759         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 760                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 761
 762         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 763         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 764                 return -EIO;
 765
 766         /*
 767          * Allocating rte mbuffs for configured rx queues.
 768          * This requires queues being enabled before
 769          */
 770         if (nfp_net_rx_freelist_setup(dev) < 0) {
 771                 ret = -ENOMEM;
 772                 goto error;
 773         }
 774
 775         if (hw->is_pf)
 776                 /* Configure the physical port up */
 777                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 1);
 778
 779         hw->ctrl = new_ctrl;
 780
 781         return 0;
 782
 783 error:
 784         /*
 785          * An error returned by this function should mean the app
 786          * exiting and then the system releasing all the memory
 787          * allocated even memory coming from hugepages.
 788          *
 789          * The device could be enabled at this point with some queues
 790          * ready for getting packets. This is true if the call to
 791          * nfp_net_rx_freelist_setup() succeeds for some queues but
 792          * fails for subsequent queues.
 793          *
 794          * This should make the app exiting but better if we tell the
 795          * device first.
 796          */
 797         nfp_net_disable_queues(dev);
 798
 799         return ret;
 800 }
 801
 802 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 803 static void
 804 nfp_net_stop(struct rte_eth_dev *dev)
 805 {
 806         int i;
 807         struct nfp_net_hw *hw;
 808
 809         PMD_INIT_LOG(DEBUG, "Stop");
 810
 811         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812
 813         nfp_net_disable_queues(dev);
 814
 815         /* Clear queues */
 816         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 817                 nfp_net_reset_tx_queue(
 818                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 819         }
 820
 821         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 822                 nfp_net_reset_rx_queue(
 823                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 824         }
 825
 826         if (hw->is_pf)
 827                 /* Configure the physical port down */
 828                 nfp_eth_set_configured(hw->cpp, hw->pf_port_idx, 0);
 829 }
 830
 831 /* Reset and stop device. The device can not be restarted. */
 832 static void
 833 nfp_net_close(struct rte_eth_dev *dev)
 834 {
 835         struct nfp_net_hw *hw;
 836         struct rte_pci_device *pci_dev;
 837         int i;
 838
 839         PMD_INIT_LOG(DEBUG, "Close");
 840
 841         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 842         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 843
 844         /*
 845          * We assume that the DPDK application is stopping all the
 846          * threads/queues before calling the device close function.
 847          */
 848
 849         nfp_net_disable_queues(dev);
 850
 851         /* Clear queues */
 852         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 853                 nfp_net_reset_tx_queue(
 854                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 855         }
 856
 857         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 858                 nfp_net_reset_rx_queue(
 859                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 860         }
 861
 862         rte_intr_disable(&pci_dev->intr_handle);
 863         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 864
 865         /* unregister callback func from eal lib */
 866         rte_intr_callback_unregister(&pci_dev->intr_handle,
 867                                      nfp_net_dev_interrupt_handler,
 868                                      (void *)dev);
 869
 870         /*
 871          * The ixgbe PMD driver disables the pcie master on the
 872          * device. The i40e does not...
 873          */
 874 }
 875
 876 static void
 877 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 878 {
 879         uint32_t new_ctrl, update = 0;
 880         struct nfp_net_hw *hw;
 881
 882         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable");
 883
 884         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885
 886         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 887                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 888                 return;
 889         }
 890
 891         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 892                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled");
 893                 return;
 894         }
 895
 896         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 897         update = NFP_NET_CFG_UPDATE_GEN;
 898
 899         /*
 900          * DPDK sets promiscuous mode on just after this call assuming
 901          * it can not fail ...
 902          */
 903         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 904                 return;
 905
 906         hw->ctrl = new_ctrl;
 907 }
 908
 909 static void
 910 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 911 {
 912         uint32_t new_ctrl, update = 0;
 913         struct nfp_net_hw *hw;
 914
 915         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916
 917         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 918                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled");
 919                 return;
 920         }
 921
 922         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 923         update = NFP_NET_CFG_UPDATE_GEN;
 924
 925         /*
 926          * DPDK sets promiscuous mode off just before this call
 927          * assuming it can not fail ...
 928          */
 929         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 930                 return;
 931
 932         hw->ctrl = new_ctrl;
 933 }
 934
 935 /*
 936  * return 0 means link status changed, -1 means not changed
 937  *
 938  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 939  * status.
 940  */
 941 static int
 942 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 943 {
 944         struct nfp_net_hw *hw;
 945         struct rte_eth_link link;
 946         uint32_t nn_link_status;
 947         int ret;
 948
 949         static const uint32_t ls_to_ethtool[] = {
 950                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 951                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 952                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 953                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 954                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 955                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 956                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 957                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 958         };
 959
 960         PMD_DRV_LOG(DEBUG, "Link update");
 961
 962         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 963
 964         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
 965
 966         memset(&link, 0, sizeof(struct rte_eth_link));
 967
 968         if (nn_link_status & NFP_NET_CFG_STS_LINK)
 969                 link.link_status = ETH_LINK_UP;
 970
 971         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 972
 973         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
 974                          NFP_NET_CFG_STS_LINK_RATE_MASK;
 975
 976         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
 977                 link.link_speed = ETH_SPEED_NUM_NONE;
 978         else
 979                 link.link_speed = ls_to_ethtool[nn_link_status];
 980
 981         ret = rte_eth_linkstatus_set(dev, &link);
 982         if (ret == 0) {
 983                 if (link.link_status)
 984                         PMD_DRV_LOG(INFO, "NIC Link is Up");
 985                 else
 986                         PMD_DRV_LOG(INFO, "NIC Link is Down");
 987         }
 988         return ret;
 989 }
 990
 991 static int
 992 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 993 {
 994         int i;
 995         struct nfp_net_hw *hw;
 996         struct rte_eth_stats nfp_dev_stats;
 997
 998         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 999
1000         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1001
1002         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1003
1004         /* reading per RX ring stats */
1005         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1006                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1007                         break;
1008
1009                 nfp_dev_stats.q_ipackets[i] =
1010                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1011
1012                 nfp_dev_stats.q_ipackets[i] -=
1013                         hw->eth_stats_base.q_ipackets[i];
1014
1015                 nfp_dev_stats.q_ibytes[i] =
1016                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1017
1018                 nfp_dev_stats.q_ibytes[i] -=
1019                         hw->eth_stats_base.q_ibytes[i];
1020         }
1021
1022         /* reading per TX ring stats */
1023         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1024                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1025                         break;
1026
1027                 nfp_dev_stats.q_opackets[i] =
1028                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1029
1030                 nfp_dev_stats.q_opackets[i] -=
1031                         hw->eth_stats_base.q_opackets[i];
1032
1033                 nfp_dev_stats.q_obytes[i] =
1034                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1035
1036                 nfp_dev_stats.q_obytes[i] -=
1037                         hw->eth_stats_base.q_obytes[i];
1038         }
1039
1040         nfp_dev_stats.ipackets =
1041                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1042
1043         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1044
1045         nfp_dev_stats.ibytes =
1046                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1047
1048         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1049
1050         nfp_dev_stats.opackets =
1051                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1052
1053         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1054
1055         nfp_dev_stats.obytes =
1056                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1057
1058         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1059
1060         /* reading general device stats */
1061         nfp_dev_stats.ierrors =
1062                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1063
1064         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1065
1066         nfp_dev_stats.oerrors =
1067                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1068
1069         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1070
1071         /* RX ring mbuf allocation failures */
1072         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1073
1074         nfp_dev_stats.imissed =
1075                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1076
1077         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1078
1079         if (stats) {
1080                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1081                 return 0;
1082         }
1083         return -EINVAL;
1084 }
1085
1086 static void
1087 nfp_net_stats_reset(struct rte_eth_dev *dev)
1088 {
1089         int i;
1090         struct nfp_net_hw *hw;
1091
1092         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093
1094         /*
1095          * hw->eth_stats_base records the per counter starting point.
1096          * Lets update it now
1097          */
1098
1099         /* reading per RX ring stats */
1100         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1101                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1102                         break;
1103
1104                 hw->eth_stats_base.q_ipackets[i] =
1105                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1106
1107                 hw->eth_stats_base.q_ibytes[i] =
1108                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1109         }
1110
1111         /* reading per TX ring stats */
1112         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1113                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1114                         break;
1115
1116                 hw->eth_stats_base.q_opackets[i] =
1117                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1118
1119                 hw->eth_stats_base.q_obytes[i] =
1120                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1121         }
1122
1123         hw->eth_stats_base.ipackets =
1124                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1125
1126         hw->eth_stats_base.ibytes =
1127                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1128
1129         hw->eth_stats_base.opackets =
1130                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1131
1132         hw->eth_stats_base.obytes =
1133                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1134
1135         /* reading general device stats */
1136         hw->eth_stats_base.ierrors =
1137                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1138
1139         hw->eth_stats_base.oerrors =
1140                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1141
1142         /* RX ring mbuf allocation failures */
1143         dev->data->rx_mbuf_alloc_failed = 0;
1144
1145         hw->eth_stats_base.imissed =
1146                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1147 }
1148
1149 static void
1150 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1151 {
1152         struct nfp_net_hw *hw;
1153
1154         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155
1156         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1157         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1158         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1159         dev_info->max_rx_pktlen = hw->max_mtu;
1160         /* Next should change when PF support is implemented */
1161         dev_info->max_mac_addrs = 1;
1162
1163         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1164                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1165
1166         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1167                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1168                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1169                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1170
1171         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_JUMBO_FRAME |
1172                                      DEV_RX_OFFLOAD_KEEP_CRC;
1173
1174         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1175                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1176
1177         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1178                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1179                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1180                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1181
1182         if (hw->cap & NFP_NET_CFG_CTRL_LSO_ANY)
1183                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1184
1185         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
1186                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MULTI_SEGS;
1187
1188         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1189                 .rx_thresh = {
1190                         .pthresh = DEFAULT_RX_PTHRESH,
1191                         .hthresh = DEFAULT_RX_HTHRESH,
1192                         .wthresh = DEFAULT_RX_WTHRESH,
1193                 },
1194                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1195                 .rx_drop_en = 0,
1196         };
1197
1198         dev_info->default_txconf = (struct rte_eth_txconf) {
1199                 .tx_thresh = {
1200                         .pthresh = DEFAULT_TX_PTHRESH,
1201                         .hthresh = DEFAULT_TX_HTHRESH,
1202                         .wthresh = DEFAULT_TX_WTHRESH,
1203                 },
1204                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1205                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1206         };
1207
1208         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1209                                            ETH_RSS_NONFRAG_IPV4_UDP |
1210                                            ETH_RSS_NONFRAG_IPV6_TCP |
1211                                            ETH_RSS_NONFRAG_IPV6_UDP;
1212
1213         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1214         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1215
1216         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1217                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1218                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1219 }
1220
1221 static const uint32_t *
1222 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1223 {
1224         static const uint32_t ptypes[] = {
1225                 /* refers to nfp_net_set_hash() */
1226                 RTE_PTYPE_INNER_L3_IPV4,
1227                 RTE_PTYPE_INNER_L3_IPV6,
1228                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1229                 RTE_PTYPE_INNER_L4_MASK,
1230                 RTE_PTYPE_UNKNOWN
1231         };
1232
1233         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1234                 return ptypes;
1235         return NULL;
1236 }
1237
1238 static uint32_t
1239 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1240 {
1241         struct nfp_net_rxq *rxq;
1242         struct nfp_net_rx_desc *rxds;
1243         uint32_t idx;
1244         uint32_t count;
1245
1246         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1247
1248         idx = rxq->rd_p;
1249
1250         count = 0;
1251
1252         /*
1253          * Other PMDs are just checking the DD bit in intervals of 4
1254          * descriptors and counting all four if the first has the DD
1255          * bit on. Of course, this is not accurate but can be good for
1256          * performance. But ideally that should be done in descriptors
1257          * chunks belonging to the same cache line
1258          */
1259
1260         while (count < rxq->rx_count) {
1261                 rxds = &rxq->rxds[idx];
1262                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1263                         break;
1264
1265                 count++;
1266                 idx++;
1267
1268                 /* Wrapping? */
1269                 if ((idx) == rxq->rx_count)
1270                         idx = 0;
1271         }
1272
1273         return count;
1274 }
1275
1276 static int
1277 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1278 {
1279         struct rte_pci_device *pci_dev;
1280         struct nfp_net_hw *hw;
1281         int base = 0;
1282
1283         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1285
1286         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1287                 base = 1;
1288
1289         /* Make sure all updates are written before un-masking */
1290         rte_wmb();
1291         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1292                       NFP_NET_CFG_ICR_UNMASKED);
1293         return 0;
1294 }
1295
1296 static int
1297 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1298 {
1299         struct rte_pci_device *pci_dev;
1300         struct nfp_net_hw *hw;
1301         int base = 0;
1302
1303         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1305
1306         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1307                 base = 1;
1308
1309         /* Make sure all updates are written before un-masking */
1310         rte_wmb();
1311         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1312         return 0;
1313 }
1314
1315 static void
1316 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1317 {
1318         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1319         struct rte_eth_link link;
1320
1321         rte_eth_linkstatus_get(dev, &link);
1322         if (link.link_status)
1323                 PMD_DRV_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1324                             dev->data->port_id, link.link_speed,
1325                             link.link_duplex == ETH_LINK_FULL_DUPLEX
1326                             ? "full-duplex" : "half-duplex");
1327         else
1328                 PMD_DRV_LOG(INFO, " Port %d: Link Down",
1329                             dev->data->port_id);
1330
1331         PMD_DRV_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1332                 pci_dev->addr.domain, pci_dev->addr.bus,
1333                 pci_dev->addr.devid, pci_dev->addr.function);
1334 }
1335
1336 /* Interrupt configuration and handling */
1337
1338 /*
1339  * nfp_net_irq_unmask - Unmask an interrupt
1340  *
1341  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1342  * clear the ICR for the entry.
1343  */
1344 static void
1345 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1346 {
1347         struct nfp_net_hw *hw;
1348         struct rte_pci_device *pci_dev;
1349
1350         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1352
1353         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1354                 /* If MSI-X auto-masking is used, clear the entry */
1355                 rte_wmb();
1356                 rte_intr_enable(&pci_dev->intr_handle);
1357         } else {
1358                 /* Make sure all updates are written before un-masking */
1359                 rte_wmb();
1360                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1361                               NFP_NET_CFG_ICR_UNMASKED);
1362         }
1363 }
1364
1365 static void
1366 nfp_net_dev_interrupt_handler(void *param)
1367 {
1368         int64_t timeout;
1369         struct rte_eth_link link;
1370         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1371
1372         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!");
1373
1374         rte_eth_linkstatus_get(dev, &link);
1375
1376         nfp_net_link_update(dev, 0);
1377
1378         /* likely to up */
1379         if (!link.link_status) {
1380                 /* handle it 1 sec later, wait it being stable */
1381                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1382                 /* likely to down */
1383         } else {
1384                 /* handle it 4 sec later, wait it being stable */
1385                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1386         }
1387
1388         if (rte_eal_alarm_set(timeout * 1000,
1389                               nfp_net_dev_interrupt_delayed_handler,
1390                               (void *)dev) < 0) {
1391                 PMD_INIT_LOG(ERR, "Error setting alarm");
1392                 /* Unmasking */
1393                 nfp_net_irq_unmask(dev);
1394         }
1395 }
1396
1397 /*
1398  * Interrupt handler which shall be registered for alarm callback for delayed
1399  * handling specific interrupt to wait for the stable nic state. As the NIC
1400  * interrupt state is not stable for nfp after link is just down, it needs
1401  * to wait 4 seconds to get the stable status.
1402  *
1403  * @param handle   Pointer to interrupt handle.
1404  * @param param    The address of parameter (struct rte_eth_dev *)
1405  *
1406  * @return  void
1407  */
1408 static void
1409 nfp_net_dev_interrupt_delayed_handler(void *param)
1410 {
1411         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1412
1413         nfp_net_link_update(dev, 0);
1414         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1415
1416         nfp_net_dev_link_status_print(dev);
1417
1418         /* Unmasking */
1419         nfp_net_irq_unmask(dev);
1420 }
1421
1422 static int
1423 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1424 {
1425         struct nfp_net_hw *hw;
1426
1427         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428
1429         /* check that mtu is within the allowed range */
1430         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1431                 return -EINVAL;
1432
1433         /* mtu setting is forbidden if port is started */
1434         if (dev->data->dev_started) {
1435                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1436                             dev->data->port_id);
1437                 return -EBUSY;
1438         }
1439
1440         /* switch to jumbo mode if needed */
1441         if ((uint32_t)mtu > ETHER_MAX_LEN)
1442                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1443         else
1444                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1445
1446         /* update max frame size */
1447         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1448
1449         /* writing to configuration space */
1450         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1451
1452         hw->mtu = mtu;
1453
1454         return 0;
1455 }
1456
1457 static int
1458 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1459                        uint16_t queue_idx, uint16_t nb_desc,
1460                        unsigned int socket_id,
1461                        const struct rte_eth_rxconf *rx_conf,
1462                        struct rte_mempool *mp)
1463 {
1464         const struct rte_memzone *tz;
1465         struct nfp_net_rxq *rxq;
1466         struct nfp_net_hw *hw;
1467
1468         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469
1470         PMD_INIT_FUNC_TRACE();
1471
1472         /* Validating number of descriptors */
1473         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1474             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1475             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1476                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1477                 return -EINVAL;
1478         }
1479
1480         /*
1481          * Free memory prior to re-allocation if needed. This is the case after
1482          * calling nfp_net_stop
1483          */
1484         if (dev->data->rx_queues[queue_idx]) {
1485                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1486                 dev->data->rx_queues[queue_idx] = NULL;
1487         }
1488
1489         /* Allocating rx queue data structure */
1490         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1491                                  RTE_CACHE_LINE_SIZE, socket_id);
1492         if (rxq == NULL)
1493                 return -ENOMEM;
1494
1495         /* Hw queues mapping based on firmware confifguration */
1496         rxq->qidx = queue_idx;
1497         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1498         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1499         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1500         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1501
1502         /*
1503          * Tracking mbuf size for detecting a potential mbuf overflow due to
1504          * RX offset
1505          */
1506         rxq->mem_pool = mp;
1507         rxq->mbuf_size = rxq->mem_pool->elt_size;
1508         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1509         hw->flbufsz = rxq->mbuf_size;
1510
1511         rxq->rx_count = nb_desc;
1512         rxq->port_id = dev->data->port_id;
1513         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1514         rxq->drop_en = rx_conf->rx_drop_en;
1515
1516         /*
1517          * Allocate RX ring hardware descriptors. A memzone large enough to
1518          * handle the maximum ring size is allocated in order to allow for
1519          * resizing in later calls to the queue setup function.
1520          */
1521         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1522                                    sizeof(struct nfp_net_rx_desc) *
1523                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1524                                    socket_id);
1525
1526         if (tz == NULL) {
1527                 PMD_DRV_LOG(ERR, "Error allocatig rx dma");
1528                 nfp_net_rx_queue_release(rxq);
1529                 return -ENOMEM;
1530         }
1531
1532         /* Saving physical and virtual addresses for the RX ring */
1533         rxq->dma = (uint64_t)tz->iova;
1534         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1535
1536         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1537         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1538                                          sizeof(*rxq->rxbufs) * nb_desc,
1539                                          RTE_CACHE_LINE_SIZE, socket_id);
1540         if (rxq->rxbufs == NULL) {
1541                 nfp_net_rx_queue_release(rxq);
1542                 return -ENOMEM;
1543         }
1544
1545         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1546                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1547
1548         nfp_net_reset_rx_queue(rxq);
1549
1550         dev->data->rx_queues[queue_idx] = rxq;
1551         rxq->hw = hw;
1552
1553         /*
1554          * Telling the HW about the physical address of the RX ring and number
1555          * of descriptors in log2 format
1556          */
1557         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1558         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1559
1560         return 0;
1561 }
1562
1563 static int
1564 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1565 {
1566         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1567         uint64_t dma_addr;
1568         unsigned i;
1569
1570         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors",
1571                    rxq->rx_count);
1572
1573         for (i = 0; i < rxq->rx_count; i++) {
1574                 struct nfp_net_rx_desc *rxd;
1575                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1576
1577                 if (mbuf == NULL) {
1578                         PMD_DRV_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
1579                                 (unsigned)rxq->qidx);
1580                         return -ENOMEM;
1581                 }
1582
1583                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1584
1585                 rxd = &rxq->rxds[i];
1586                 rxd->fld.dd = 0;
1587                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1588                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1589                 rxe[i].mbuf = mbuf;
1590                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64, i, dma_addr);
1591         }
1592
1593         /* Make sure all writes are flushed before telling the hardware */
1594         rte_wmb();
1595
1596         /* Not advertising the whole ring as the firmware gets confused if so */
1597         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u",
1598                    rxq->rx_count - 1);
1599
1600         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1601
1602         return 0;
1603 }
1604
1605 static int
1606 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1607                        uint16_t nb_desc, unsigned int socket_id,
1608                        const struct rte_eth_txconf *tx_conf)
1609 {
1610         const struct rte_memzone *tz;
1611         struct nfp_net_txq *txq;
1612         uint16_t tx_free_thresh;
1613         struct nfp_net_hw *hw;
1614
1615         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         /* Validating number of descriptors */
1620         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1621             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1622             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1623                 PMD_DRV_LOG(ERR, "Wrong nb_desc value");
1624                 return -EINVAL;
1625         }
1626
1627         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1628                                     tx_conf->tx_free_thresh :
1629                                     DEFAULT_TX_FREE_THRESH);
1630
1631         if (tx_free_thresh > (nb_desc)) {
1632                 PMD_DRV_LOG(ERR,
1633                         "tx_free_thresh must be less than the number of TX "
1634                         "descriptors. (tx_free_thresh=%u port=%d "
1635                         "queue=%d)", (unsigned int)tx_free_thresh,
1636                         dev->data->port_id, (int)queue_idx);
1637                 return -(EINVAL);
1638         }
1639
1640         /*
1641          * Free memory prior to re-allocation if needed. This is the case after
1642          * calling nfp_net_stop
1643          */
1644         if (dev->data->tx_queues[queue_idx]) {
1645                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1646                            queue_idx);
1647                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1648                 dev->data->tx_queues[queue_idx] = NULL;
1649         }
1650
1651         /* Allocating tx queue data structure */
1652         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1653                                  RTE_CACHE_LINE_SIZE, socket_id);
1654         if (txq == NULL) {
1655                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1656                 return -ENOMEM;
1657         }
1658
1659         /*
1660          * Allocate TX ring hardware descriptors. A memzone large enough to
1661          * handle the maximum ring size is allocated in order to allow for
1662          * resizing in later calls to the queue setup function.
1663          */
1664         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1665                                    sizeof(struct nfp_net_tx_desc) *
1666                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1667                                    socket_id);
1668         if (tz == NULL) {
1669                 PMD_DRV_LOG(ERR, "Error allocating tx dma");
1670                 nfp_net_tx_queue_release(txq);
1671                 return -ENOMEM;
1672         }
1673
1674         txq->tx_count = nb_desc;
1675         txq->tx_free_thresh = tx_free_thresh;
1676         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1677         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1678         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1679
1680         /* queue mapping based on firmware configuration */
1681         txq->qidx = queue_idx;
1682         txq->tx_qcidx = queue_idx * hw->stride_tx;
1683         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1684
1685         txq->port_id = dev->data->port_id;
1686
1687         /* Saving physical and virtual addresses for the TX ring */
1688         txq->dma = (uint64_t)tz->iova;
1689         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1690
1691         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1692         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1693                                          sizeof(*txq->txbufs) * nb_desc,
1694                                          RTE_CACHE_LINE_SIZE, socket_id);
1695         if (txq->txbufs == NULL) {
1696                 nfp_net_tx_queue_release(txq);
1697                 return -ENOMEM;
1698         }
1699         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64,
1700                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1701
1702         nfp_net_reset_tx_queue(txq);
1703
1704         dev->data->tx_queues[queue_idx] = txq;
1705         txq->hw = hw;
1706
1707         /*
1708          * Telling the HW about the physical address of the TX ring and number
1709          * of descriptors in log2 format
1710          */
1711         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1712         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1713
1714         return 0;
1715 }
1716
1717 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1718 static inline void
1719 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1720                struct rte_mbuf *mb)
1721 {
1722         uint64_t ol_flags;
1723         struct nfp_net_hw *hw = txq->hw;
1724
1725         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO_ANY))
1726                 goto clean_txd;
1727
1728         ol_flags = mb->ol_flags;
1729
1730         if (!(ol_flags & PKT_TX_TCP_SEG))
1731                 goto clean_txd;
1732
1733         txd->l3_offset = mb->l2_len;
1734         txd->l4_offset = mb->l2_len + mb->l3_len;
1735         txd->lso_hdrlen = mb->l2_len + mb->l3_len + mb->l4_len;
1736         txd->mss = rte_cpu_to_le_16(mb->tso_segsz);
1737         txd->flags = PCIE_DESC_TX_LSO;
1738         return;
1739
1740 clean_txd:
1741         txd->flags = 0;
1742         txd->l3_offset = 0;
1743         txd->l4_offset = 0;
1744         txd->lso_hdrlen = 0;
1745         txd->mss = 0;
1746 }
1747
1748 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1749 static inline void
1750 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1751                  struct rte_mbuf *mb)
1752 {
1753         uint64_t ol_flags;
1754         struct nfp_net_hw *hw = txq->hw;
1755
1756         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1757                 return;
1758
1759         ol_flags = mb->ol_flags;
1760
1761         /* IPv6 does not need checksum */
1762         if (ol_flags & PKT_TX_IP_CKSUM)
1763                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1764
1765         switch (ol_flags & PKT_TX_L4_MASK) {
1766         case PKT_TX_UDP_CKSUM:
1767                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1768                 break;
1769         case PKT_TX_TCP_CKSUM:
1770                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1771                 break;
1772         }
1773
1774         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1775                 txd->flags |= PCIE_DESC_TX_CSUM;
1776 }
1777
1778 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1779 static inline void
1780 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1781                  struct rte_mbuf *mb)
1782 {
1783         struct nfp_net_hw *hw = rxq->hw;
1784
1785         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1786                 return;
1787
1788         /* If IPv4 and IP checksum error, fail */
1789         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1790             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1791                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1792
1793         /* If neither UDP nor TCP return */
1794         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1795             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1796                 return;
1797
1798         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1799             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1800                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1801
1802         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1803             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1804                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1805 }
1806
1807 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1808 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1809
1810 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1811
1812 /*
1813  * nfp_net_set_hash - Set mbuf hash data
1814  *
1815  * The RSS hash and hash-type are pre-pended to the packet data.
1816  * Extract and decode it and set the mbuf fields.
1817  */
1818 static inline void
1819 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1820                  struct rte_mbuf *mbuf)
1821 {
1822         struct nfp_net_hw *hw = rxq->hw;
1823         uint8_t *meta_offset;
1824         uint32_t meta_info;
1825         uint32_t hash = 0;
1826         uint32_t hash_type = 0;
1827
1828         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1829                 return;
1830
1831         /* this is true for new firmwares */
1832         if (likely(((hw->cap & NFP_NET_CFG_CTRL_RSS2) ||
1833             (NFD_CFG_MAJOR_VERSION_of(hw->ver) == 4)) &&
1834              NFP_DESC_META_LEN(rxd))) {
1835                 /*
1836                  * new metadata api:
1837                  * <----  32 bit  ----->
1838                  * m    field type word
1839                  * e     data field #2
1840                  * t     data field #1
1841                  * a     data field #0
1842                  * ====================
1843                  *    packet data
1844                  *
1845                  * Field type word contains up to 8 4bit field types
1846                  * A 4bit field type refers to a data field word
1847                  * A data field word can have several 4bit field types
1848                  */
1849                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1850                 meta_offset -= NFP_DESC_META_LEN(rxd);
1851                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1852                 meta_offset += 4;
1853                 /* NFP PMD just supports metadata for hashing */
1854                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1855                 case NFP_NET_META_HASH:
1856                         /* next field type is about the hash type */
1857                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1858                         /* hash value is in the data field */
1859                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1860                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1861                         break;
1862                 default:
1863                         /* Unsupported metadata can be a performance issue */
1864                         return;
1865                 }
1866         } else {
1867                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1868                         return;
1869
1870                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1871                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1872         }
1873
1874         mbuf->hash.rss = hash;
1875         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1876
1877         switch (hash_type) {
1878         case NFP_NET_RSS_IPV4:
1879                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1880                 break;
1881         case NFP_NET_RSS_IPV6:
1882                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1883                 break;
1884         case NFP_NET_RSS_IPV6_EX:
1885                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1886                 break;
1887         default:
1888                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1889         }
1890 }
1891
1892 static inline void
1893 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1894 {
1895         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1896 }
1897
1898 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1899
1900 /*
1901  * RX path design:
1902  *
1903  * There are some decissions to take:
1904  * 1) How to check DD RX descriptors bit
1905  * 2) How and when to allocate new mbufs
1906  *
1907  * Current implementation checks just one single DD bit each loop. As each
1908  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1909  * a single cache line instead. Tests with this change have not shown any
1910  * performance improvement but it requires further investigation. For example,
1911  * depending on which descriptor is next, the number of descriptors could be
1912  * less than 8 for just checking those in the same cache line. This implies
1913  * extra work which could be counterproductive by itself. Indeed, last firmware
1914  * changes are just doing this: writing several descriptors with the DD bit
1915  * for saving PCIe bandwidth and DMA operations from the NFP.
1916  *
1917  * Mbuf allocation is done when a new packet is received. Then the descriptor
1918  * is automatically linked with the new mbuf and the old one is given to the
1919  * user. The main drawback with this design is mbuf allocation is heavier than
1920  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1921  * cache point of view it does not seem allocating the mbuf early on as we are
1922  * doing now have any benefit at all. Again, tests with this change have not
1923  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1924  * so looking at the implications of this type of allocation should be studied
1925  * deeply
1926  */
1927
1928 static uint16_t
1929 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1930 {
1931         struct nfp_net_rxq *rxq;
1932         struct nfp_net_rx_desc *rxds;
1933         struct nfp_net_rx_buff *rxb;
1934         struct nfp_net_hw *hw;
1935         struct rte_mbuf *mb;
1936         struct rte_mbuf *new_mb;
1937         uint16_t nb_hold;
1938         uint64_t dma_addr;
1939         int avail;
1940
1941         rxq = rx_queue;
1942         if (unlikely(rxq == NULL)) {
1943                 /*
1944                  * DPDK just checks the queue is lower than max queues
1945                  * enabled. But the queue needs to be configured
1946                  */
1947                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1948                 return -EINVAL;
1949         }
1950
1951         hw = rxq->hw;
1952         avail = 0;
1953         nb_hold = 0;
1954
1955         while (avail < nb_pkts) {
1956                 rxb = &rxq->rxbufs[rxq->rd_p];
1957                 if (unlikely(rxb == NULL)) {
1958                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1959                         break;
1960                 }
1961
1962                 rxds = &rxq->rxds[rxq->rd_p];
1963                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1964                         break;
1965
1966                 /*
1967                  * Memory barrier to ensure that we won't do other
1968                  * reads before the DD bit.
1969                  */
1970                 rte_rmb();
1971
1972                 /*
1973                  * We got a packet. Let's alloc a new mbuff for refilling the
1974                  * free descriptor ring as soon as possible
1975                  */
1976                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1977                 if (unlikely(new_mb == NULL)) {
1978                         RTE_LOG_DP(DEBUG, PMD,
1979                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
1980                                 rxq->port_id, (unsigned int)rxq->qidx);
1981                         nfp_net_mbuf_alloc_failed(rxq);
1982                         break;
1983                 }
1984
1985                 nb_hold++;
1986
1987                 /*
1988                  * Grab the mbuff and refill the descriptor with the
1989                  * previously allocated mbuff
1990                  */
1991                 mb = rxb->mbuf;
1992                 rxb->mbuf = new_mb;
1993
1994                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u",
1995                            rxds->rxd.data_len, rxq->mbuf_size);
1996
1997                 /* Size of this segment */
1998                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1999                 /* Size of the whole packet. We just support 1 segment */
2000                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2001
2002                 if (unlikely((mb->data_len + hw->rx_offset) >
2003                              rxq->mbuf_size)) {
2004                         /*
2005                          * This should not happen and the user has the
2006                          * responsibility of avoiding it. But we have
2007                          * to give some info about the error
2008                          */
2009                         RTE_LOG_DP(ERR, PMD,
2010                                 "mbuf overflow likely due to the RX offset.\n"
2011                                 "\t\tYour mbuf size should have extra space for"
2012                                 " RX offset=%u bytes.\n"
2013                                 "\t\tCurrently you just have %u bytes available"
2014                                 " but the received packet is %u bytes long",
2015                                 hw->rx_offset,
2016                                 rxq->mbuf_size - hw->rx_offset,
2017                                 mb->data_len);
2018                         return -EINVAL;
2019                 }
2020
2021                 /* Filling the received mbuff with packet info */
2022                 if (hw->rx_offset)
2023                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2024                 else
2025                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2026                                        NFP_DESC_META_LEN(rxds);
2027
2028                 /* No scatter mode supported */
2029                 mb->nb_segs = 1;
2030                 mb->next = NULL;
2031
2032                 mb->port = rxq->port_id;
2033
2034                 /* Checking the RSS flag */
2035                 nfp_net_set_hash(rxq, rxds, mb);
2036
2037                 /* Checking the checksum flag */
2038                 nfp_net_rx_cksum(rxq, rxds, mb);
2039
2040                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2041                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2042                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2043                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2044                 }
2045
2046                 /* Adding the mbuff to the mbuff array passed by the app */
2047                 rx_pkts[avail++] = mb;
2048
2049                 /* Now resetting and updating the descriptor */
2050                 rxds->vals[0] = 0;
2051                 rxds->vals[1] = 0;
2052                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2053                 rxds->fld.dd = 0;
2054                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2055                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2056
2057                 rxq->rd_p++;
2058                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2059                         rxq->rd_p = 0;
2060         }
2061
2062         if (nb_hold == 0)
2063                 return nb_hold;
2064
2065         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received",
2066                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2067
2068         nb_hold += rxq->nb_rx_hold;
2069
2070         /*
2071          * FL descriptors needs to be written before incrementing the
2072          * FL queue WR pointer
2073          */
2074         rte_wmb();
2075         if (nb_hold > rxq->rx_free_thresh) {
2076                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u",
2077                            rxq->port_id, (unsigned int)rxq->qidx,
2078                            (unsigned)nb_hold, (unsigned)avail);
2079                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2080                 nb_hold = 0;
2081         }
2082         rxq->nb_rx_hold = nb_hold;
2083
2084         return avail;
2085 }
2086
2087 /*
2088  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2089  * status
2090  * @txq: TX queue to work with
2091  * Returns number of descriptors freed
2092  */
2093 int
2094 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2095 {
2096         uint32_t qcp_rd_p;
2097         int todo;
2098
2099         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2100                    " status", txq->qidx);
2101
2102         /* Work out how many packets have been sent */
2103         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2104
2105         if (qcp_rd_p == txq->rd_p) {
2106                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2107                            "packets (%u, %u)", txq->qidx,
2108                            qcp_rd_p, txq->rd_p);
2109                 return 0;
2110         }
2111
2112         if (qcp_rd_p > txq->rd_p)
2113                 todo = qcp_rd_p - txq->rd_p;
2114         else
2115                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2116
2117         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u",
2118                    qcp_rd_p, txq->rd_p, txq->rd_p);
2119
2120         if (todo == 0)
2121                 return todo;
2122
2123         txq->rd_p += todo;
2124         if (unlikely(txq->rd_p >= txq->tx_count))
2125                 txq->rd_p -= txq->tx_count;
2126
2127         return todo;
2128 }
2129
2130 /* Leaving always free descriptors for avoiding wrapping confusion */
2131 static inline
2132 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2133 {
2134         if (txq->wr_p >= txq->rd_p)
2135                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2136         else
2137                 return txq->rd_p - txq->wr_p - 8;
2138 }
2139
2140 /*
2141  * nfp_net_txq_full - Check if the TX queue free descriptors
2142  * is below tx_free_threshold
2143  *
2144  * @txq: TX queue to check
2145  *
2146  * This function uses the host copy* of read/write pointers
2147  */
2148 static inline
2149 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2150 {
2151         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2152 }
2153
2154 static uint16_t
2155 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2156 {
2157         struct nfp_net_txq *txq;
2158         struct nfp_net_hw *hw;
2159         struct nfp_net_tx_desc *txds, txd;
2160         struct rte_mbuf *pkt;
2161         uint64_t dma_addr;
2162         int pkt_size, dma_size;
2163         uint16_t free_descs, issued_descs;
2164         struct rte_mbuf **lmbuf;
2165         int i;
2166
2167         txq = tx_queue;
2168         hw = txq->hw;
2169         txds = &txq->txds[txq->wr_p];
2170
2171         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets",
2172                    txq->qidx, txq->wr_p, nb_pkts);
2173
2174         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2175                 nfp_net_tx_free_bufs(txq);
2176
2177         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2178         if (unlikely(free_descs == 0))
2179                 return 0;
2180
2181         pkt = *tx_pkts;
2182
2183         i = 0;
2184         issued_descs = 0;
2185         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets",
2186                    txq->qidx, nb_pkts);
2187         /* Sending packets */
2188         while ((i < nb_pkts) && free_descs) {
2189                 /* Grabbing the mbuf linked to the current descriptor */
2190                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2191                 /* Warming the cache for releasing the mbuf later on */
2192                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2193
2194                 pkt = *(tx_pkts + i);
2195
2196                 if (unlikely((pkt->nb_segs > 1) &&
2197                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2198                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2199                         rte_panic("Multisegment packet unsupported\n");
2200                 }
2201
2202                 /* Checking if we have enough descriptors */
2203                 if (unlikely(pkt->nb_segs > free_descs))
2204                         goto xmit_end;
2205
2206                 /*
2207                  * Checksum and VLAN flags just in the first descriptor for a
2208                  * multisegment packet, but TSO info needs to be in all of them.
2209                  */
2210                 txd.data_len = pkt->pkt_len;
2211                 nfp_net_tx_tso(txq, &txd, pkt);
2212                 nfp_net_tx_cksum(txq, &txd, pkt);
2213
2214                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2215                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2216                         txd.flags |= PCIE_DESC_TX_VLAN;
2217                         txd.vlan = pkt->vlan_tci;
2218                 }
2219
2220                 /*
2221                  * mbuf data_len is the data in one segment and pkt_len data
2222                  * in the whole packet. When the packet is just one segment,
2223                  * then data_len = pkt_len
2224                  */
2225                 pkt_size = pkt->pkt_len;
2226
2227                 while (pkt) {
2228                         /* Copying TSO, VLAN and cksum info */
2229                         *txds = txd;
2230
2231                         /* Releasing mbuf used by this descriptor previously*/
2232                         if (*lmbuf)
2233                                 rte_pktmbuf_free_seg(*lmbuf);
2234
2235                         /*
2236                          * Linking mbuf with descriptor for being released
2237                          * next time descriptor is used
2238                          */
2239                         *lmbuf = pkt;
2240
2241                         dma_size = pkt->data_len;
2242                         dma_addr = rte_mbuf_data_iova(pkt);
2243                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2244                                    "%" PRIx64 "", dma_addr);
2245
2246                         /* Filling descriptors fields */
2247                         txds->dma_len = dma_size;
2248                         txds->data_len = txd.data_len;
2249                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2250                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2251                         ASSERT(free_descs > 0);
2252                         free_descs--;
2253
2254                         txq->wr_p++;
2255                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2256                                 txq->wr_p = 0;
2257
2258                         pkt_size -= dma_size;
2259
2260                         /*
2261                          * Making the EOP, packets with just one segment
2262                          * the priority
2263                          */
2264                         if (likely(!pkt_size))
2265                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2266                         else
2267                                 txds->offset_eop = 0;
2268
2269                         pkt = pkt->next;
2270                         /* Referencing next free TX descriptor */
2271                         txds = &txq->txds[txq->wr_p];
2272                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2273                         issued_descs++;
2274                 }
2275                 i++;
2276         }
2277
2278 xmit_end:
2279         /* Increment write pointers. Force memory write before we let HW know */
2280         rte_wmb();
2281         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2282
2283         return i;
2284 }
2285
2286 static int
2287 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2288 {
2289         uint32_t new_ctrl, update;
2290         struct nfp_net_hw *hw;
2291         int ret;
2292
2293         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294         new_ctrl = 0;
2295
2296         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2297             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2298                 PMD_DRV_LOG(INFO, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2299                         " ETH_VLAN_EXTEND_OFFLOAD");
2300
2301         /* Enable vlan strip if it is not configured yet */
2302         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2303             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2304                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2305
2306         /* Disable vlan strip just if it is configured */
2307         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2308             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2309                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2310
2311         if (new_ctrl == 0)
2312                 return 0;
2313
2314         update = NFP_NET_CFG_UPDATE_GEN;
2315
2316         ret = nfp_net_reconfig(hw, new_ctrl, update);
2317         if (!ret)
2318                 hw->ctrl = new_ctrl;
2319
2320         return ret;
2321 }
2322
2323 static int
2324 nfp_net_rss_reta_write(struct rte_eth_dev *dev,
2325                     struct rte_eth_rss_reta_entry64 *reta_conf,
2326                     uint16_t reta_size)
2327 {
2328         uint32_t reta, mask;
2329         int i, j;
2330         int idx, shift;
2331         struct nfp_net_hw *hw =
2332                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333
2334         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2335                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2336                         "(%d) doesn't match the number hardware can supported "
2337                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2338                 return -EINVAL;
2339         }
2340
2341         /*
2342          * Update Redirection Table. There are 128 8bit-entries which can be
2343          * manage as 32 32bit-entries
2344          */
2345         for (i = 0; i < reta_size; i += 4) {
2346                 /* Handling 4 RSS entries per loop */
2347                 idx = i / RTE_RETA_GROUP_SIZE;
2348                 shift = i % RTE_RETA_GROUP_SIZE;
2349                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2350
2351                 if (!mask)
2352                         continue;
2353
2354                 reta = 0;
2355                 /* If all 4 entries were set, don't need read RETA register */
2356                 if (mask != 0xF)
2357                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2358
2359                 for (j = 0; j < 4; j++) {
2360                         if (!(mask & (0x1 << j)))
2361                                 continue;
2362                         if (mask != 0xF)
2363                                 /* Clearing the entry bits */
2364                                 reta &= ~(0xFF << (8 * j));
2365                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2366                 }
2367                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2368                               reta);
2369         }
2370         return 0;
2371 }
2372
2373 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2374 static int
2375 nfp_net_reta_update(struct rte_eth_dev *dev,
2376                     struct rte_eth_rss_reta_entry64 *reta_conf,
2377                     uint16_t reta_size)
2378 {
2379         struct nfp_net_hw *hw =
2380                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381         uint32_t update;
2382         int ret;
2383
2384         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2385                 return -EINVAL;
2386
2387         ret = nfp_net_rss_reta_write(dev, reta_conf, reta_size);
2388         if (ret != 0)
2389                 return ret;
2390
2391         update = NFP_NET_CFG_UPDATE_RSS;
2392
2393         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2394                 return -EIO;
2395
2396         return 0;
2397 }
2398
2399  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2400 static int
2401 nfp_net_reta_query(struct rte_eth_dev *dev,
2402                    struct rte_eth_rss_reta_entry64 *reta_conf,
2403                    uint16_t reta_size)
2404 {
2405         uint8_t i, j, mask;
2406         int idx, shift;
2407         uint32_t reta;
2408         struct nfp_net_hw *hw;
2409
2410         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411
2412         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2413                 return -EINVAL;
2414
2415         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2416                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2417                         "(%d) doesn't match the number hardware can supported "
2418                         "(%d)", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2419                 return -EINVAL;
2420         }
2421
2422         /*
2423          * Reading Redirection Table. There are 128 8bit-entries which can be
2424          * manage as 32 32bit-entries
2425          */
2426         for (i = 0; i < reta_size; i += 4) {
2427                 /* Handling 4 RSS entries per loop */
2428                 idx = i / RTE_RETA_GROUP_SIZE;
2429                 shift = i % RTE_RETA_GROUP_SIZE;
2430                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2431
2432                 if (!mask)
2433                         continue;
2434
2435                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2436                                     shift);
2437                 for (j = 0; j < 4; j++) {
2438                         if (!(mask & (0x1 << j)))
2439                                 continue;
2440                         reta_conf->reta[shift + j] =
2441                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2442                 }
2443         }
2444         return 0;
2445 }
2446
2447 static int
2448 nfp_net_rss_hash_write(struct rte_eth_dev *dev,
2449                         struct rte_eth_rss_conf *rss_conf)
2450 {
2451         struct nfp_net_hw *hw;
2452         uint64_t rss_hf;
2453         uint32_t cfg_rss_ctrl = 0;
2454         uint8_t key;
2455         int i;
2456
2457         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458
2459         /* Writing the key byte a byte */
2460         for (i = 0; i < rss_conf->rss_key_len; i++) {
2461                 memcpy(&key, &rss_conf->rss_key[i], 1);
2462                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2463         }
2464
2465         rss_hf = rss_conf->rss_hf;
2466
2467         if (rss_hf & ETH_RSS_IPV4)
2468                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2469                                 NFP_NET_CFG_RSS_IPV4_TCP |
2470                                 NFP_NET_CFG_RSS_IPV4_UDP;
2471
2472         if (rss_hf & ETH_RSS_IPV6)
2473                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2474                                 NFP_NET_CFG_RSS_IPV6_TCP |
2475                                 NFP_NET_CFG_RSS_IPV6_UDP;
2476
2477         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2478         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2479
2480         /* configuring where to apply the RSS hash */
2481         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2482
2483         /* Writing the key size */
2484         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2485
2486         return 0;
2487 }
2488
2489 static int
2490 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2491                         struct rte_eth_rss_conf *rss_conf)
2492 {
2493         uint32_t update;
2494         uint64_t rss_hf;
2495         struct nfp_net_hw *hw;
2496
2497         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498
2499         rss_hf = rss_conf->rss_hf;
2500
2501         /* Checking if RSS is enabled */
2502         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2503                 if (rss_hf != 0) { /* Enable RSS? */
2504                         PMD_DRV_LOG(ERR, "RSS unsupported");
2505                         return -EINVAL;
2506                 }
2507                 return 0; /* Nothing to do */
2508         }
2509
2510         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2511                 PMD_DRV_LOG(ERR, "hash key too long");
2512                 return -EINVAL;
2513         }
2514
2515         nfp_net_rss_hash_write(dev, rss_conf);
2516
2517         update = NFP_NET_CFG_UPDATE_RSS;
2518
2519         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2520                 return -EIO;
2521
2522         return 0;
2523 }
2524
2525 static int
2526 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2527                           struct rte_eth_rss_conf *rss_conf)
2528 {
2529         uint64_t rss_hf;
2530         uint32_t cfg_rss_ctrl;
2531         uint8_t key;
2532         int i;
2533         struct nfp_net_hw *hw;
2534
2535         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536
2537         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2538                 return -EINVAL;
2539
2540         rss_hf = rss_conf->rss_hf;
2541         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2542
2543         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2544                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2545
2546         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2547                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2548
2549         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2550                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2551
2552         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2553                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2554
2555         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2556                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2557
2558         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2559                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2560
2561         /* Reading the key size */
2562         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2563
2564         /* Reading the key byte a byte */
2565         for (i = 0; i < rss_conf->rss_key_len; i++) {
2566                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2567                 memcpy(&rss_conf->rss_key[i], &key, 1);
2568         }
2569
2570         return 0;
2571 }
2572
2573 static int
2574 nfp_net_rss_config_default(struct rte_eth_dev *dev)
2575 {
2576         struct rte_eth_conf *dev_conf;
2577         struct rte_eth_rss_conf rss_conf;
2578         struct rte_eth_rss_reta_entry64 nfp_reta_conf[2];
2579         uint16_t rx_queues = dev->data->nb_rx_queues;
2580         uint16_t queue;
2581         int i, j, ret;
2582
2583         PMD_DRV_LOG(INFO, "setting default RSS conf for %u queues",
2584                 rx_queues);
2585
2586         nfp_reta_conf[0].mask = ~0x0;
2587         nfp_reta_conf[1].mask = ~0x0;
2588
2589         queue = 0;
2590         for (i = 0; i < 0x40; i += 8) {
2591                 for (j = i; j < (i + 8); j++) {
2592                         nfp_reta_conf[0].reta[j] = queue;
2593                         nfp_reta_conf[1].reta[j] = queue++;
2594                         queue %= rx_queues;
2595                 }
2596         }
2597         ret = nfp_net_rss_reta_write(dev, nfp_reta_conf, 0x80);
2598         if (ret != 0)
2599                 return ret;
2600
2601         dev_conf = &dev->data->dev_conf;
2602         if (!dev_conf) {
2603                 PMD_DRV_LOG(INFO, "wrong rss conf");
2604                 return -EINVAL;
2605         }
2606         rss_conf = dev_conf->rx_adv_conf.rss_conf;
2607
2608         ret = nfp_net_rss_hash_write(dev, &rss_conf);
2609
2610         return ret;
2611 }
2612
2613
2614 /* Initialise and register driver with DPDK Application */
2615 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2616         .dev_configure          = nfp_net_configure,
2617         .dev_start              = nfp_net_start,
2618         .dev_stop               = nfp_net_stop,
2619         .dev_close              = nfp_net_close,
2620         .promiscuous_enable     = nfp_net_promisc_enable,
2621         .promiscuous_disable    = nfp_net_promisc_disable,
2622         .link_update            = nfp_net_link_update,
2623         .stats_get              = nfp_net_stats_get,
2624         .stats_reset            = nfp_net_stats_reset,
2625         .dev_infos_get          = nfp_net_infos_get,
2626         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2627         .mtu_set                = nfp_net_dev_mtu_set,
2628         .mac_addr_set           = nfp_set_mac_addr,
2629         .vlan_offload_set       = nfp_net_vlan_offload_set,
2630         .reta_update            = nfp_net_reta_update,
2631         .reta_query             = nfp_net_reta_query,
2632         .rss_hash_update        = nfp_net_rss_hash_update,
2633         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2634         .rx_queue_setup         = nfp_net_rx_queue_setup,
2635         .rx_queue_release       = nfp_net_rx_queue_release,
2636         .rx_queue_count         = nfp_net_rx_queue_count,
2637         .tx_queue_setup         = nfp_net_tx_queue_setup,
2638         .tx_queue_release       = nfp_net_tx_queue_release,
2639         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2640         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2641 };
2642
2643 /*
2644  * All eth_dev created got its private data, but before nfp_net_init, that
2645  * private data is referencing private data for all the PF ports. This is due
2646  * to how the vNIC bars are mapped based on first port, so all ports need info
2647  * about port 0 private data. Inside nfp_net_init the private data pointer is
2648  * changed to the right address for each port once the bars have been mapped.
2649  *
2650  * This functions helps to find out which port and therefore which offset
2651  * inside the private data array to use.
2652  */
2653 static int
2654 get_pf_port_number(char *name)
2655 {
2656         char *pf_str = name;
2657         int size = 0;
2658
2659         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2660                 pf_str++;
2661
2662         if (size == 30)
2663                 /*
2664                  * This should not happen at all and it would mean major
2665                  * implementation fault.
2666                  */
2667                 rte_panic("nfp_net: problem with pf device name\n");
2668
2669         /* Expecting _portX with X within [0,7] */
2670         pf_str += 5;
2671
2672         return (int)strtol(pf_str, NULL, 10);
2673 }
2674
2675 static int
2676 nfp_net_init(struct rte_eth_dev *eth_dev)
2677 {
2678         struct rte_pci_device *pci_dev;
2679         struct nfp_net_hw *hw, *hwport0;
2680
2681         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2682         uint32_t start_q;
2683         int stride = 4;
2684         int port = 0;
2685         int err;
2686
2687         PMD_INIT_FUNC_TRACE();
2688
2689         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2690
2691         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2692             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2693                 port = get_pf_port_number(eth_dev->data->name);
2694                 if (port < 0 || port > 7) {
2695                         PMD_DRV_LOG(ERR, "Port value is wrong");
2696                         return -ENODEV;
2697                 }
2698
2699                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d", port);
2700
2701                 /* This points to port 0 private data */
2702                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2703
2704                 /* This points to the specific port private data */
2705                 hw = &hwport0[port];
2706         } else {
2707                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2708                 hwport0 = 0;
2709         }
2710
2711         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2712         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2713         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2714
2715         /* For secondary processes, the primary has done all the work */
2716         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2717                 return 0;
2718
2719         rte_eth_copy_pci_info(eth_dev, pci_dev);
2720
2721         hw->device_id = pci_dev->id.device_id;
2722         hw->vendor_id = pci_dev->id.vendor_id;
2723         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2724         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2725
2726         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2727                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2728                      pci_dev->addr.domain, pci_dev->addr.bus,
2729                      pci_dev->addr.devid, pci_dev->addr.function);
2730
2731         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2732         if (hw->ctrl_bar == NULL) {
2733                 PMD_DRV_LOG(ERR,
2734                         "hw->ctrl_bar is NULL. BAR0 not configured");
2735                 return -ENODEV;
2736         }
2737
2738         if (hw->is_pf && port == 0) {
2739                 hw->ctrl_bar = nfp_rtsym_map(hw->sym_tbl, "_pf0_net_bar0",
2740                                              hw->total_ports * 32768,
2741                                              &hw->ctrl_area);
2742                 if (!hw->ctrl_bar) {
2743                         printf("nfp_rtsym_map fails for _pf0_net_ctrl_bar");
2744                         return -EIO;
2745                 }
2746
2747                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2748         }
2749
2750         if (port > 0) {
2751                 if (!hwport0->ctrl_bar)
2752                         return -ENODEV;
2753
2754                 /* address based on port0 offset */
2755                 hw->ctrl_bar = hwport0->ctrl_bar +
2756                                (port * NFP_PF_CSR_SLICE_SIZE);
2757         }
2758
2759         PMD_INIT_LOG(DEBUG, "ctrl bar: %p", hw->ctrl_bar);
2760
2761         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2762         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2763
2764         /* Work out where in the BAR the queues start. */
2765         switch (pci_dev->id.device_id) {
2766         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2767         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2768         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2769                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2770                 tx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2771                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2772                 rx_bar_off = start_q * NFP_QCP_QUEUE_ADDR_SZ;
2773                 break;
2774         default:
2775                 PMD_DRV_LOG(ERR, "nfp_net: no device ID matching");
2776                 err = -ENODEV;
2777                 goto dev_err_ctrl_map;
2778         }
2779
2780         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "", tx_bar_off);
2781         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "", rx_bar_off);
2782
2783         if (hw->is_pf && port == 0) {
2784                 /* configure access to tx/rx vNIC BARs */
2785                 hwport0->hw_queues = nfp_cpp_map_area(hw->cpp, 0, 0,
2786                                                       NFP_PCIE_QUEUE(0),
2787                                                       NFP_QCP_QUEUE_AREA_SZ,
2788                                                       &hw->hwqueues_area);
2789
2790                 if (!hwport0->hw_queues) {
2791                         printf("nfp_rtsym_map fails for net.qc");
2792                         err = -EIO;
2793                         goto dev_err_ctrl_map;
2794                 }
2795
2796                 PMD_INIT_LOG(DEBUG, "tx/rx bar address: 0x%p",
2797                                     hwport0->hw_queues);
2798         }
2799
2800         if (hw->is_pf) {
2801                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2802                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2803                 eth_dev->data->dev_private = hw;
2804         } else {
2805                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2806                              tx_bar_off;
2807                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2808                              rx_bar_off;
2809         }
2810
2811         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2812                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2813
2814         nfp_net_cfg_queue_setup(hw);
2815
2816         /* Get some of the read-only fields from the config BAR */
2817         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2818         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2819         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2820         hw->mtu = ETHER_MTU;
2821
2822         /* VLAN insertion is incompatible with LSOv2 */
2823         if (hw->cap & NFP_NET_CFG_CTRL_LSO2)
2824                 hw->cap &= ~NFP_NET_CFG_CTRL_TXVLAN;
2825
2826         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2827                 hw->rx_offset = NFP_NET_RX_OFFSET;
2828         else
2829                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2830
2831         PMD_INIT_LOG(INFO, "VER: %u.%u, Maximum supported MTU: %d",
2832                            NFD_CFG_MAJOR_VERSION_of(hw->ver),
2833                            NFD_CFG_MINOR_VERSION_of(hw->ver), hw->max_mtu);
2834
2835         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2836                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2837                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2838                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2839                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2840                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2841                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2842                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2843                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2844                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2845                      hw->cap & NFP_NET_CFG_CTRL_LIVE_ADDR ? "LIVE_ADDR "  : "",
2846                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2847                      hw->cap & NFP_NET_CFG_CTRL_LSO2     ? "TSOv2 "     : "",
2848                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "",
2849                      hw->cap & NFP_NET_CFG_CTRL_RSS2     ? "RSSv2 "     : "");
2850
2851         hw->ctrl = 0;
2852
2853         hw->stride_rx = stride;
2854         hw->stride_tx = stride;
2855
2856         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2857                      hw->max_rx_queues, hw->max_tx_queues);
2858
2859         /* Initializing spinlock for reconfigs */
2860         rte_spinlock_init(&hw->reconfig_lock);
2861
2862         /* Allocating memory for mac addr */
2863         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2864         if (eth_dev->data->mac_addrs == NULL) {
2865                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2866                 err = -ENOMEM;
2867                 goto dev_err_queues_map;
2868         }
2869
2870         if (hw->is_pf) {
2871                 nfp_net_pf_read_mac(hwport0, port);
2872                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2873         } else {
2874                 nfp_net_vf_read_mac(hw);
2875         }
2876
2877         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2878                 PMD_INIT_LOG(INFO, "Using random mac address for port %d",
2879                                    port);
2880                 /* Using random mac addresses for VFs */
2881                 eth_random_addr(&hw->mac_addr[0]);
2882                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2883         }
2884
2885         /* Copying mac address to DPDK eth_dev struct */
2886         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2887                         &eth_dev->data->mac_addrs[0]);
2888
2889         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2890                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2891                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2892                      pci_dev->id.device_id,
2893                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2894                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2895
2896         /* Registering LSC interrupt handler */
2897         rte_intr_callback_register(&pci_dev->intr_handle,
2898                                    nfp_net_dev_interrupt_handler,
2899                                    (void *)eth_dev);
2900
2901         /* Telling the firmware about the LSC interrupt entry */
2902         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2903
2904         /* Recording current stats counters values */
2905         nfp_net_stats_reset(eth_dev);
2906
2907         return 0;
2908
2909 dev_err_queues_map:
2910                 nfp_cpp_area_free(hw->hwqueues_area);
2911 dev_err_ctrl_map:
2912                 nfp_cpp_area_free(hw->ctrl_area);
2913
2914         return err;
2915 }
2916
2917 static int
2918 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2919                   struct nfp_cpp *cpp, struct nfp_hwinfo *hwinfo,
2920                   int phys_port, struct nfp_rtsym_table *sym_tbl, void **priv)
2921 {
2922         struct rte_eth_dev *eth_dev;
2923         struct nfp_net_hw *hw;
2924         char *port_name;
2925         int ret;
2926
2927         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2928         if (!port_name)
2929                 return -ENOMEM;
2930
2931         if (ports > 1)
2932                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2933         else
2934                 sprintf(port_name, "%s", dev->device.name);
2935
2936         eth_dev = rte_eth_dev_allocate(port_name);
2937         if (!eth_dev)
2938                 return -ENOMEM;
2939
2940         if (port == 0) {
2941                 *priv = rte_zmalloc(port_name,
2942                                     sizeof(struct nfp_net_adapter) * ports,
2943                                     RTE_CACHE_LINE_SIZE);
2944                 if (!*priv) {
2945                         rte_eth_dev_release_port(eth_dev);
2946                         return -ENOMEM;
2947                 }
2948         }
2949
2950         eth_dev->data->dev_private = *priv;
2951
2952         /*
2953          * dev_private pointing to port0 dev_private because we need
2954          * to configure vNIC bars based on port0 at nfp_net_init.
2955          * Then dev_private is adjusted per port.
2956          */
2957         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2958         hw->cpp = cpp;
2959         hw->hwinfo = hwinfo;
2960         hw->sym_tbl = sym_tbl;
2961         hw->pf_port_idx = phys_port;
2962         hw->is_pf = 1;
2963         if (ports > 1)
2964                 hw->pf_multiport_enabled = 1;
2965
2966         hw->total_ports = ports;
2967
2968         eth_dev->device = &dev->device;
2969         rte_eth_copy_pci_info(eth_dev, dev);
2970
2971         ret = nfp_net_init(eth_dev);
2972
2973         if (ret)
2974                 rte_eth_dev_release_port(eth_dev);
2975         else
2976                 rte_eth_dev_probing_finish(eth_dev);
2977
2978         rte_free(port_name);
2979
2980         return ret;
2981 }
2982
2983 #define DEFAULT_FW_PATH       "/lib/firmware/netronome"
2984
2985 static int
2986 nfp_fw_upload(struct rte_pci_device *dev, struct nfp_nsp *nsp, char *card)
2987 {
2988         struct nfp_cpp *cpp = nsp->cpp;
2989         int fw_f;
2990         char *fw_buf;
2991         char fw_name[125];
2992         char serial[40];
2993         struct stat file_stat;
2994         off_t fsize, bytes;
2995
2996         /* Looking for firmware file in order of priority */
2997
2998         /* First try to find a firmware image specific for this device */
2999         sprintf(serial, "serial-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x",
3000                 cpp->serial[0], cpp->serial[1], cpp->serial[2], cpp->serial[3],
3001                 cpp->serial[4], cpp->serial[5], cpp->interface >> 8,
3002                 cpp->interface & 0xff);
3003
3004         sprintf(fw_name, "%s/%s.nffw", DEFAULT_FW_PATH, serial);
3005
3006         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3007         fw_f = open(fw_name, O_RDONLY);
3008         if (fw_f > 0)
3009                 goto read_fw;
3010
3011         /* Then try the PCI name */
3012         sprintf(fw_name, "%s/pci-%s.nffw", DEFAULT_FW_PATH, dev->device.name);
3013
3014         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3015         fw_f = open(fw_name, O_RDONLY);
3016         if (fw_f > 0)
3017                 goto read_fw;
3018
3019         /* Finally try the card type and media */
3020         sprintf(fw_name, "%s/%s", DEFAULT_FW_PATH, card);
3021         PMD_DRV_LOG(DEBUG, "Trying with fw file: %s", fw_name);
3022         fw_f = open(fw_name, O_RDONLY);
3023         if (fw_f < 0) {
3024                 PMD_DRV_LOG(INFO, "Firmware file %s not found.", fw_name);
3025                 return -ENOENT;
3026         }
3027
3028 read_fw:
3029         if (fstat(fw_f, &file_stat) < 0) {
3030                 PMD_DRV_LOG(INFO, "Firmware file %s size is unknown", fw_name);
3031                 close(fw_f);
3032                 return -ENOENT;
3033         }
3034
3035         fsize = file_stat.st_size;
3036         PMD_DRV_LOG(INFO, "Firmware file found at %s with size: %" PRIu64 "",
3037                             fw_name, (uint64_t)fsize);
3038
3039         fw_buf = malloc((size_t)fsize);
3040         if (!fw_buf) {
3041                 PMD_DRV_LOG(INFO, "malloc failed for fw buffer");
3042                 close(fw_f);
3043                 return -ENOMEM;
3044         }
3045         memset(fw_buf, 0, fsize);
3046
3047         bytes = read(fw_f, fw_buf, fsize);
3048         if (bytes != fsize) {
3049                 PMD_DRV_LOG(INFO, "Reading fw to buffer failed."
3050                                    "Just %" PRIu64 " of %" PRIu64 " bytes read",
3051                                    (uint64_t)bytes, (uint64_t)fsize);
3052                 free(fw_buf);
3053                 close(fw_f);
3054                 return -EIO;
3055         }
3056
3057         PMD_DRV_LOG(INFO, "Uploading the firmware ...");
3058         nfp_nsp_load_fw(nsp, fw_buf, bytes);
3059         PMD_DRV_LOG(INFO, "Done");
3060
3061         free(fw_buf);
3062         close(fw_f);
3063
3064         return 0;
3065 }
3066
3067 static int
3068 nfp_fw_setup(struct rte_pci_device *dev, struct nfp_cpp *cpp,
3069              struct nfp_eth_table *nfp_eth_table, struct nfp_hwinfo *hwinfo)
3070 {
3071         struct nfp_nsp *nsp;
3072         const char *nfp_fw_model;
3073         char card_desc[100];
3074         int err = 0;
3075
3076         nfp_fw_model = nfp_hwinfo_lookup(hwinfo, "assembly.partno");
3077
3078         if (nfp_fw_model) {
3079                 PMD_DRV_LOG(INFO, "firmware model found: %s", nfp_fw_model);
3080         } else {
3081                 PMD_DRV_LOG(ERR, "firmware model NOT found");
3082                 return -EIO;
3083         }
3084
3085         if (nfp_eth_table->count == 0 || nfp_eth_table->count > 8) {
3086                 PMD_DRV_LOG(ERR, "NFP ethernet table reports wrong ports: %u",
3087                        nfp_eth_table->count);
3088                 return -EIO;
3089         }
3090
3091         PMD_DRV_LOG(INFO, "NFP ethernet port table reports %u ports",
3092                            nfp_eth_table->count);
3093
3094         PMD_DRV_LOG(INFO, "Port speed: %u", nfp_eth_table->ports[0].speed);
3095
3096         sprintf(card_desc, "nic_%s_%dx%d.nffw", nfp_fw_model,
3097                 nfp_eth_table->count, nfp_eth_table->ports[0].speed / 1000);
3098
3099         nsp = nfp_nsp_open(cpp);
3100         if (!nsp) {
3101                 PMD_DRV_LOG(ERR, "NFP error when obtaining NSP handle");
3102                 return -EIO;
3103         }
3104
3105         nfp_nsp_device_soft_reset(nsp);
3106         err = nfp_fw_upload(dev, nsp, card_desc);
3107
3108         nfp_nsp_close(nsp);
3109         return err;
3110 }
3111
3112 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3113                             struct rte_pci_device *dev)
3114 {
3115         struct nfp_cpp *cpp;
3116         struct nfp_hwinfo *hwinfo;
3117         struct nfp_rtsym_table *sym_tbl;
3118         struct nfp_eth_table *nfp_eth_table = NULL;
3119         int total_ports;
3120         void *priv = 0;
3121         int ret = -ENODEV;
3122         int err;
3123         int i;
3124
3125         if (!dev)
3126                 return ret;
3127
3128         /*
3129          * When device bound to UIO, the device could be used, by mistake,
3130          * by two DPDK apps, and the UIO driver does not avoid it. This
3131          * could lead to a serious problem when configuring the NFP CPP
3132          * interface. Here we avoid this telling to the CPP init code to
3133          * use a lock file if UIO is being used.
3134          */
3135         if (dev->kdrv == RTE_KDRV_VFIO)
3136                 cpp = nfp_cpp_from_device_name(dev, 0);
3137         else
3138                 cpp = nfp_cpp_from_device_name(dev, 1);
3139
3140         if (!cpp) {
3141                 PMD_DRV_LOG(ERR, "A CPP handle can not be obtained");
3142                 ret = -EIO;
3143                 goto error;
3144         }
3145
3146         hwinfo = nfp_hwinfo_read(cpp);
3147         if (!hwinfo) {
3148                 PMD_DRV_LOG(ERR, "Error reading hwinfo table");
3149                 return -EIO;
3150         }
3151
3152         nfp_eth_table = nfp_eth_read_ports(cpp);
3153         if (!nfp_eth_table) {
3154                 PMD_DRV_LOG(ERR, "Error reading NFP ethernet table");
3155                 return -EIO;
3156         }
3157
3158         if (nfp_fw_setup(dev, cpp, nfp_eth_table, hwinfo)) {
3159                 PMD_DRV_LOG(INFO, "Error when uploading firmware");
3160                 ret = -EIO;
3161                 goto error;
3162         }
3163
3164         /* Now the symbol table should be there */
3165         sym_tbl = nfp_rtsym_table_read(cpp);
3166         if (!sym_tbl) {
3167                 PMD_DRV_LOG(ERR, "Something is wrong with the firmware"
3168                                 " symbol table");
3169                 ret = -EIO;
3170                 goto error;
3171         }
3172
3173         total_ports = nfp_rtsym_read_le(sym_tbl, "nfd_cfg_pf0_num_ports", &err);
3174         if (total_ports != (int)nfp_eth_table->count) {
3175                 PMD_DRV_LOG(ERR, "Inconsistent number of ports");
3176                 ret = -EIO;
3177                 goto error;
3178         }
3179         PMD_INIT_LOG(INFO, "Total pf ports: %d", total_ports);
3180
3181         if (total_ports <= 0 || total_ports > 8) {
3182                 PMD_DRV_LOG(ERR, "nfd_cfg_pf0_num_ports symbol with wrong value");
3183                 ret = -ENODEV;
3184                 goto error;
3185         }
3186
3187         for (i = 0; i < total_ports; i++) {
3188                 ret = nfp_pf_create_dev(dev, i, total_ports, cpp, hwinfo,
3189                                         nfp_eth_table->ports[i].index,
3190                                         sym_tbl, &priv);
3191                 if (ret)
3192                         break;
3193         }
3194
3195 error:
3196         free(nfp_eth_table);
3197         return ret;
3198 }
3199
3200 int nfp_logtype_init;
3201 int nfp_logtype_driver;
3202
3203 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3204         {
3205                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3206                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3207         },
3208         {
3209                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3210                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3211         },
3212         {
3213                 .vendor_id = 0,
3214         },
3215 };
3216
3217 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3218         {
3219                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3220                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3221         },
3222         {
3223                 .vendor_id = 0,
3224         },
3225 };
3226
3227 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3228         struct rte_pci_device *pci_dev)
3229 {
3230         return rte_eth_dev_pci_generic_probe(pci_dev,
3231                 sizeof(struct nfp_net_adapter), nfp_net_init);
3232 }
3233
3234 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3235 {
3236         struct rte_eth_dev *eth_dev;
3237         struct nfp_net_hw *hw, *hwport0;
3238         int port = 0;
3239
3240         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3241         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3242             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3243                 port = get_pf_port_number(eth_dev->data->name);
3244                 /*
3245                  * hotplug is not possible with multiport PF although freeing
3246                  * data structures can be done for first port.
3247                  */
3248                 if (port != 0)
3249                         return -ENOTSUP;
3250                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3251                 hw = &hwport0[port];
3252                 nfp_cpp_area_free(hw->ctrl_area);
3253                 nfp_cpp_area_free(hw->hwqueues_area);
3254                 free(hw->hwinfo);
3255                 free(hw->sym_tbl);
3256                 nfp_cpp_free(hw->cpp);
3257         } else {
3258                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3259         }
3260         /* hotplug is not possible with multiport PF */
3261         if (hw->pf_multiport_enabled)
3262                 return -ENOTSUP;
3263         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3264 }
3265
3266 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3267         .id_table = pci_id_nfp_pf_net_map,
3268         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3269         .probe = nfp_pf_pci_probe,
3270         .remove = eth_nfp_pci_remove,
3271 };
3272
3273 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3274         .id_table = pci_id_nfp_vf_net_map,
3275         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3276         .probe = eth_nfp_pci_probe,
3277         .remove = eth_nfp_pci_remove,
3278 };
3279
3280 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3281 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3282 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3283 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3284 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3285 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3286
3287 RTE_INIT(nfp_init_log)
3288 {
3289         nfp_logtype_init = rte_log_register("pmd.net.nfp.init");
3290         if (nfp_logtype_init >= 0)
3291                 rte_log_set_level(nfp_logtype_init, RTE_LOG_NOTICE);
3292         nfp_logtype_driver = rte_log_register("pmd.net.nfp.driver");
3293         if (nfp_logtype_driver >= 0)
3294                 rte_log_set_level(nfp_logtype_driver, RTE_LOG_NOTICE);
3295 }
3296 /*
3297  * Local variables:
3298  * c-file-style: "Linux"
3299  * indent-tabs-mode: t
3300  * End:
3301  */