drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         if (rxmode->jumbo_frame)
 492                 /* this is handled in rte_eth_dev_configure */
 493
 494         if (rxmode->hw_strip_crc) {
 495                 PMD_INIT_LOG(INFO, "strip CRC not supported");
 496                 return -EINVAL;
 497         }
 498
 499         if (rxmode->enable_scatter) {
 500                 PMD_INIT_LOG(INFO, "Scatter not supported");
 501                 return -EINVAL;
 502         }
 503
 504         /* If next capabilities are supported, configure them by default */
 505
 506         /* VLAN insertion */
 507         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 508                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 509
 510         /* L2 broadcast */
 511         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 512                 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
 513
 514         /* L2 multicast */
 515         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 516                 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
 517
 518         /* TX checksum offload */
 519         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
 520                 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 521
 522         /* LSO offload */
 523         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 524                 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
 525
 526         /* RX gather */
 527         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
 528                 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
 529
 530         if (!new_ctrl)
 531                 return 0;
 532
 533         update |= NFP_NET_CFG_UPDATE_GEN;
 534
 535         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 536         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 537                 return -EIO;
 538
 539         hw->ctrl = new_ctrl;
 540
 541         return 0;
 542 }
 543
 544 static void
 545 nfp_net_enable_queues(struct rte_eth_dev *dev)
 546 {
 547         struct nfp_net_hw *hw;
 548         uint64_t enabled_queues = 0;
 549         int i;
 550
 551         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 552
 553         /* Enabling the required TX queues in the device */
 554         for (i = 0; i < dev->data->nb_tx_queues; i++)
 555                 enabled_queues |= (1 << i);
 556
 557         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 558
 559         enabled_queues = 0;
 560
 561         /* Enabling the required RX queues in the device */
 562         for (i = 0; i < dev->data->nb_rx_queues; i++)
 563                 enabled_queues |= (1 << i);
 564
 565         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 566 }
 567
 568 static void
 569 nfp_net_disable_queues(struct rte_eth_dev *dev)
 570 {
 571         struct nfp_net_hw *hw;
 572         uint32_t new_ctrl, update = 0;
 573
 574         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 577         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 578
 579         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 580         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 581                  NFP_NET_CFG_UPDATE_MSIX;
 582
 583         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 584                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 585
 586         /* If an error when reconfig we avoid to change hw state */
 587         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 588                 return;
 589
 590         hw->ctrl = new_ctrl;
 591 }
 592
 593 static int
 594 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 595 {
 596         int i;
 597
 598         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 599                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 600                         return -1;
 601         }
 602         return 0;
 603 }
 604
 605 static void
 606 nfp_net_params_setup(struct nfp_net_hw *hw)
 607 {
 608         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 609         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 610 }
 611
 612 static void
 613 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 614 {
 615         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 616 }
 617
 618 #define ETH_ADDR_LEN    6
 619
 620 static void
 621 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 622 {
 623         int i;
 624
 625         for (i = 0; i < ETH_ADDR_LEN; i++)
 626                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 627 }
 628
 629 static int
 630 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 631 {
 632         union eth_table_entry *entry;
 633         int idx, i;
 634
 635         idx = port;
 636         entry = hw->eth_table;
 637
 638         /* Reading NFP ethernet table obtained before */
 639         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 640                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 641                         /* port not in use */
 642                         entry++;
 643                         continue;
 644                 }
 645                 if (idx == 0)
 646                         break;
 647                 idx--;
 648                 entry++;
 649         }
 650
 651         if (i == NSP_ETH_MAX_COUNT)
 652                 return -EINVAL;
 653
 654         /*
 655          * hw points to port0 private data. We need hw now pointing to
 656          * right port.
 657          */
 658         hw += port;
 659         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 660                                  (uint8_t *)&entry->mac_addr);
 661
 662         return 0;
 663 }
 664
 665 static void
 666 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 667 {
 668         uint32_t tmp;
 669
 670         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 671         memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
 672
 673         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 674         memcpy(&hw->mac_addr[4], &tmp, 2);
 675 }
 676
 677 static void
 678 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 679 {
 680         uint32_t mac0 = *(uint32_t *)mac;
 681         uint16_t mac1;
 682
 683         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 684
 685         mac += 4;
 686         mac1 = *(uint16_t *)mac;
 687         nn_writew(rte_cpu_to_be_16(mac1),
 688                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 689 }
 690
 691 static int
 692 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 693                            struct rte_intr_handle *intr_handle)
 694 {
 695         struct nfp_net_hw *hw;
 696         int i;
 697
 698         if (!intr_handle->intr_vec) {
 699                 intr_handle->intr_vec =
 700                         rte_zmalloc("intr_vec",
 701                                     dev->data->nb_rx_queues * sizeof(int), 0);
 702                 if (!intr_handle->intr_vec) {
 703                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 704                                      " intr_vec", dev->data->nb_rx_queues);
 705                         return -ENOMEM;
 706                 }
 707         }
 708
 709         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710
 711         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 712                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 713                 /* UIO just supports one queue and no LSC*/
 714                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 715                 intr_handle->intr_vec[0] = 0;
 716         } else {
 717                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 718                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 719                         /*
 720                          * The first msix vector is reserved for non
 721                          * efd interrupts
 722                         */
 723                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 724                         intr_handle->intr_vec[i] = i + 1;
 725                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 726                                             intr_handle->intr_vec[i]);
 727                 }
 728         }
 729
 730         /* Avoiding TX interrupts */
 731         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 732         return 0;
 733 }
 734
 735 static int
 736 nfp_net_start(struct rte_eth_dev *dev)
 737 {
 738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 739         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 740         uint32_t new_ctrl, update = 0;
 741         struct nfp_net_hw *hw;
 742         uint32_t intr_vector;
 743         int ret;
 744
 745         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 746
 747         PMD_INIT_LOG(DEBUG, "Start");
 748
 749         /* Disabling queues just in case... */
 750         nfp_net_disable_queues(dev);
 751
 752         /* Writing configuration parameters in the device */
 753         nfp_net_params_setup(hw);
 754
 755         /* Enabling the required queues in the device */
 756         nfp_net_enable_queues(dev);
 757
 758         /* check and configure queue intr-vector mapping */
 759         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 760                 if (hw->pf_multiport_enabled) {
 761                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 762                                           "with NFP multiport PF");
 763                                 return -EINVAL;
 764                 }
 765                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 766                         /*
 767                          * Better not to share LSC with RX interrupts.
 768                          * Unregistering LSC interrupt handler
 769                          */
 770                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 771                                 nfp_net_dev_interrupt_handler, (void *)dev);
 772
 773                         if (dev->data->nb_rx_queues > 1) {
 774                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 775                                              "supports 1 queue with UIO");
 776                                 return -EIO;
 777                         }
 778                 }
 779                 intr_vector = dev->data->nb_rx_queues;
 780                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 781                         return -1;
 782
 783                 nfp_configure_rx_interrupt(dev, intr_handle);
 784                 update = NFP_NET_CFG_UPDATE_MSIX;
 785         }
 786
 787         rte_intr_enable(intr_handle);
 788
 789         /* Enable device */
 790         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 791
 792         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 793
 794         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 795                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 796
 797         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 798         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 799                 return -EIO;
 800
 801         /*
 802          * Allocating rte mbuffs for configured rx queues.
 803          * This requires queues being enabled before
 804          */
 805         if (nfp_net_rx_freelist_setup(dev) < 0) {
 806                 ret = -ENOMEM;
 807                 goto error;
 808         }
 809
 810         if (hw->is_pf)
 811                 /* Configure the physical port up */
 812                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 813
 814         hw->ctrl = new_ctrl;
 815
 816         return 0;
 817
 818 error:
 819         /*
 820          * An error returned by this function should mean the app
 821          * exiting and then the system releasing all the memory
 822          * allocated even memory coming from hugepages.
 823          *
 824          * The device could be enabled at this point with some queues
 825          * ready for getting packets. This is true if the call to
 826          * nfp_net_rx_freelist_setup() succeeds for some queues but
 827          * fails for subsequent queues.
 828          *
 829          * This should make the app exiting but better if we tell the
 830          * device first.
 831          */
 832         nfp_net_disable_queues(dev);
 833
 834         return ret;
 835 }
 836
 837 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 838 static void
 839 nfp_net_stop(struct rte_eth_dev *dev)
 840 {
 841         int i;
 842         struct nfp_net_hw *hw;
 843
 844         PMD_INIT_LOG(DEBUG, "Stop");
 845
 846         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 847
 848         nfp_net_disable_queues(dev);
 849
 850         /* Clear queues */
 851         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 852                 nfp_net_reset_tx_queue(
 853                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 854         }
 855
 856         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 857                 nfp_net_reset_rx_queue(
 858                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 859         }
 860
 861         if (hw->is_pf)
 862                 /* Configure the physical port down */
 863                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 864 }
 865
 866 /* Reset and stop device. The device can not be restarted. */
 867 static void
 868 nfp_net_close(struct rte_eth_dev *dev)
 869 {
 870         struct nfp_net_hw *hw;
 871         struct rte_pci_device *pci_dev;
 872         int i;
 873
 874         PMD_INIT_LOG(DEBUG, "Close");
 875
 876         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 878
 879         /*
 880          * We assume that the DPDK application is stopping all the
 881          * threads/queues before calling the device close function.
 882          */
 883
 884         nfp_net_disable_queues(dev);
 885
 886         /* Clear queues */
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 nfp_net_reset_tx_queue(
 889                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 890         }
 891
 892         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 893                 nfp_net_reset_rx_queue(
 894                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 895         }
 896
 897         rte_intr_disable(&pci_dev->intr_handle);
 898         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 899
 900         /* unregister callback func from eal lib */
 901         rte_intr_callback_unregister(&pci_dev->intr_handle,
 902                                      nfp_net_dev_interrupt_handler,
 903                                      (void *)dev);
 904
 905         /*
 906          * The ixgbe PMD driver disables the pcie master on the
 907          * device. The i40e does not...
 908          */
 909 }
 910
 911 static void
 912 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 913 {
 914         uint32_t new_ctrl, update = 0;
 915         struct nfp_net_hw *hw;
 916
 917         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 918
 919         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 922                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 923                 return;
 924         }
 925
 926         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 927                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 928                 return;
 929         }
 930
 931         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 932         update = NFP_NET_CFG_UPDATE_GEN;
 933
 934         /*
 935          * DPDK sets promiscuous mode on just after this call assuming
 936          * it can not fail ...
 937          */
 938         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 939                 return;
 940
 941         hw->ctrl = new_ctrl;
 942 }
 943
 944 static void
 945 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 946 {
 947         uint32_t new_ctrl, update = 0;
 948         struct nfp_net_hw *hw;
 949
 950         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 951
 952         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 953                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 954                 return;
 955         }
 956
 957         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 958         update = NFP_NET_CFG_UPDATE_GEN;
 959
 960         /*
 961          * DPDK sets promiscuous mode off just before this call
 962          * assuming it can not fail ...
 963          */
 964         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 965                 return;
 966
 967         hw->ctrl = new_ctrl;
 968 }
 969
 970 /*
 971  * return 0 means link status changed, -1 means not changed
 972  *
 973  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 974  * status.
 975  */
 976 static int
 977 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 978 {
 979         struct nfp_net_hw *hw;
 980         struct rte_eth_link link, old;
 981         uint32_t nn_link_status;
 982
 983         static const uint32_t ls_to_ethtool[] = {
 984                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 985                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 986                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 987                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 988                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 989                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 990                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 991                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 992         };
 993
 994         PMD_DRV_LOG(DEBUG, "Link update\n");
 995
 996         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997
 998         memset(&old, 0, sizeof(old));
 999         nfp_net_dev_atomic_read_link_status(dev, &old);
1000
1001         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1002
1003         memset(&link, 0, sizeof(struct rte_eth_link));
1004
1005         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1006                 link.link_status = ETH_LINK_UP;
1007
1008         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1009
1010         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1011                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1012
1013         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1014                 link.link_speed = ETH_SPEED_NUM_NONE;
1015         else
1016                 link.link_speed = ls_to_ethtool[nn_link_status];
1017
1018         if (old.link_status != link.link_status) {
1019                 nfp_net_dev_atomic_write_link_status(dev, &link);
1020                 if (link.link_status)
1021                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1022                 else
1023                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1024                 return 0;
1025         }
1026
1027         return -1;
1028 }
1029
1030 static int
1031 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1032 {
1033         int i;
1034         struct nfp_net_hw *hw;
1035         struct rte_eth_stats nfp_dev_stats;
1036
1037         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038
1039         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1040
1041         /* reading per RX ring stats */
1042         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1043                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1044                         break;
1045
1046                 nfp_dev_stats.q_ipackets[i] =
1047                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1048
1049                 nfp_dev_stats.q_ipackets[i] -=
1050                         hw->eth_stats_base.q_ipackets[i];
1051
1052                 nfp_dev_stats.q_ibytes[i] =
1053                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1054
1055                 nfp_dev_stats.q_ibytes[i] -=
1056                         hw->eth_stats_base.q_ibytes[i];
1057         }
1058
1059         /* reading per TX ring stats */
1060         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1062                         break;
1063
1064                 nfp_dev_stats.q_opackets[i] =
1065                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1066
1067                 nfp_dev_stats.q_opackets[i] -=
1068                         hw->eth_stats_base.q_opackets[i];
1069
1070                 nfp_dev_stats.q_obytes[i] =
1071                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1072
1073                 nfp_dev_stats.q_obytes[i] -=
1074                         hw->eth_stats_base.q_obytes[i];
1075         }
1076
1077         nfp_dev_stats.ipackets =
1078                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1079
1080         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1081
1082         nfp_dev_stats.ibytes =
1083                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1084
1085         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1086
1087         nfp_dev_stats.opackets =
1088                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1089
1090         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1091
1092         nfp_dev_stats.obytes =
1093                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1094
1095         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1096
1097         /* reading general device stats */
1098         nfp_dev_stats.ierrors =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1100
1101         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1102
1103         nfp_dev_stats.oerrors =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1105
1106         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1107
1108         /* RX ring mbuf allocation failures */
1109         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1110
1111         nfp_dev_stats.imissed =
1112                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1113
1114         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1115
1116         if (stats) {
1117                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1118                 return 0;
1119         }
1120         return -EINVAL;
1121 }
1122
1123 static void
1124 nfp_net_stats_reset(struct rte_eth_dev *dev)
1125 {
1126         int i;
1127         struct nfp_net_hw *hw;
1128
1129         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130
1131         /*
1132          * hw->eth_stats_base records the per counter starting point.
1133          * Lets update it now
1134          */
1135
1136         /* reading per RX ring stats */
1137         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1138                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1139                         break;
1140
1141                 hw->eth_stats_base.q_ipackets[i] =
1142                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1143
1144                 hw->eth_stats_base.q_ibytes[i] =
1145                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1146         }
1147
1148         /* reading per TX ring stats */
1149         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1150                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1151                         break;
1152
1153                 hw->eth_stats_base.q_opackets[i] =
1154                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1155
1156                 hw->eth_stats_base.q_obytes[i] =
1157                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1158         }
1159
1160         hw->eth_stats_base.ipackets =
1161                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1162
1163         hw->eth_stats_base.ibytes =
1164                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1165
1166         hw->eth_stats_base.opackets =
1167                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1168
1169         hw->eth_stats_base.obytes =
1170                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1171
1172         /* reading general device stats */
1173         hw->eth_stats_base.ierrors =
1174                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1175
1176         hw->eth_stats_base.oerrors =
1177                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1178
1179         /* RX ring mbuf allocation failures */
1180         dev->data->rx_mbuf_alloc_failed = 0;
1181
1182         hw->eth_stats_base.imissed =
1183                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1184 }
1185
1186 static void
1187 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1188 {
1189         struct nfp_net_hw *hw;
1190
1191         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192
1193         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1194         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1195         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1196         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1197         dev_info->max_rx_pktlen = hw->mtu;
1198         /* Next should change when PF support is implemented */
1199         dev_info->max_mac_addrs = 1;
1200
1201         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1202                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1203
1204         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1205                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1206                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1207                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1208
1209         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1210                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1211
1212         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1213                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1214                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1215                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1216
1217         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1218                 .rx_thresh = {
1219                         .pthresh = DEFAULT_RX_PTHRESH,
1220                         .hthresh = DEFAULT_RX_HTHRESH,
1221                         .wthresh = DEFAULT_RX_WTHRESH,
1222                 },
1223                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1224                 .rx_drop_en = 0,
1225         };
1226
1227         dev_info->default_txconf = (struct rte_eth_txconf) {
1228                 .tx_thresh = {
1229                         .pthresh = DEFAULT_TX_PTHRESH,
1230                         .hthresh = DEFAULT_TX_HTHRESH,
1231                         .wthresh = DEFAULT_TX_WTHRESH,
1232                 },
1233                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1234                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1235                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1236                              ETH_TXQ_FLAGS_NOOFFLOADS,
1237         };
1238
1239         dev_info->flow_type_rss_offloads = ETH_RSS_NONFRAG_IPV4_TCP |
1240                                            ETH_RSS_NONFRAG_IPV4_UDP |
1241                                            ETH_RSS_NONFRAG_IPV6_TCP |
1242                                            ETH_RSS_NONFRAG_IPV6_UDP;
1243
1244         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1245         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1246
1247         dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1248                                ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1249                                ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1250
1251         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1252                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1253 }
1254
1255 static const uint32_t *
1256 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1257 {
1258         static const uint32_t ptypes[] = {
1259                 /* refers to nfp_net_set_hash() */
1260                 RTE_PTYPE_INNER_L3_IPV4,
1261                 RTE_PTYPE_INNER_L3_IPV6,
1262                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1263                 RTE_PTYPE_INNER_L4_MASK,
1264                 RTE_PTYPE_UNKNOWN
1265         };
1266
1267         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1268                 return ptypes;
1269         return NULL;
1270 }
1271
1272 static uint32_t
1273 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1274 {
1275         struct nfp_net_rxq *rxq;
1276         struct nfp_net_rx_desc *rxds;
1277         uint32_t idx;
1278         uint32_t count;
1279
1280         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1281
1282         idx = rxq->rd_p;
1283
1284         count = 0;
1285
1286         /*
1287          * Other PMDs are just checking the DD bit in intervals of 4
1288          * descriptors and counting all four if the first has the DD
1289          * bit on. Of course, this is not accurate but can be good for
1290          * performance. But ideally that should be done in descriptors
1291          * chunks belonging to the same cache line
1292          */
1293
1294         while (count < rxq->rx_count) {
1295                 rxds = &rxq->rxds[idx];
1296                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1297                         break;
1298
1299                 count++;
1300                 idx++;
1301
1302                 /* Wrapping? */
1303                 if ((idx) == rxq->rx_count)
1304                         idx = 0;
1305         }
1306
1307         return count;
1308 }
1309
1310 static int
1311 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1312 {
1313         struct rte_pci_device *pci_dev;
1314         struct nfp_net_hw *hw;
1315         int base = 0;
1316
1317         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1318         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1319
1320         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1321                 base = 1;
1322
1323         /* Make sure all updates are written before un-masking */
1324         rte_wmb();
1325         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1326                       NFP_NET_CFG_ICR_UNMASKED);
1327         return 0;
1328 }
1329
1330 static int
1331 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1332 {
1333         struct rte_pci_device *pci_dev;
1334         struct nfp_net_hw *hw;
1335         int base = 0;
1336
1337         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1339
1340         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1341                 base = 1;
1342
1343         /* Make sure all updates are written before un-masking */
1344         rte_wmb();
1345         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1346         return 0;
1347 }
1348
1349 static void
1350 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1351 {
1352         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1353         struct rte_eth_link link;
1354
1355         memset(&link, 0, sizeof(link));
1356         nfp_net_dev_atomic_read_link_status(dev, &link);
1357         if (link.link_status)
1358                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1359                         dev->data->port_id, link.link_speed,
1360                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1361                         ? "full-duplex" : "half-duplex");
1362         else
1363                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1364                         dev->data->port_id);
1365
1366         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1367                 pci_dev->addr.domain, pci_dev->addr.bus,
1368                 pci_dev->addr.devid, pci_dev->addr.function);
1369 }
1370
1371 /* Interrupt configuration and handling */
1372
1373 /*
1374  * nfp_net_irq_unmask - Unmask an interrupt
1375  *
1376  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1377  * clear the ICR for the entry.
1378  */
1379 static void
1380 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1381 {
1382         struct nfp_net_hw *hw;
1383         struct rte_pci_device *pci_dev;
1384
1385         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1387
1388         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1389                 /* If MSI-X auto-masking is used, clear the entry */
1390                 rte_wmb();
1391                 rte_intr_enable(&pci_dev->intr_handle);
1392         } else {
1393                 /* Make sure all updates are written before un-masking */
1394                 rte_wmb();
1395                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1396                               NFP_NET_CFG_ICR_UNMASKED);
1397         }
1398 }
1399
1400 static void
1401 nfp_net_dev_interrupt_handler(void *param)
1402 {
1403         int64_t timeout;
1404         struct rte_eth_link link;
1405         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1406
1407         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1408
1409         /* get the link status */
1410         memset(&link, 0, sizeof(link));
1411         nfp_net_dev_atomic_read_link_status(dev, &link);
1412
1413         nfp_net_link_update(dev, 0);
1414
1415         /* likely to up */
1416         if (!link.link_status) {
1417                 /* handle it 1 sec later, wait it being stable */
1418                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1419                 /* likely to down */
1420         } else {
1421                 /* handle it 4 sec later, wait it being stable */
1422                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1423         }
1424
1425         if (rte_eal_alarm_set(timeout * 1000,
1426                               nfp_net_dev_interrupt_delayed_handler,
1427                               (void *)dev) < 0) {
1428                 RTE_LOG(ERR, PMD, "Error setting alarm");
1429                 /* Unmasking */
1430                 nfp_net_irq_unmask(dev);
1431         }
1432 }
1433
1434 /*
1435  * Interrupt handler which shall be registered for alarm callback for delayed
1436  * handling specific interrupt to wait for the stable nic state. As the NIC
1437  * interrupt state is not stable for nfp after link is just down, it needs
1438  * to wait 4 seconds to get the stable status.
1439  *
1440  * @param handle   Pointer to interrupt handle.
1441  * @param param    The address of parameter (struct rte_eth_dev *)
1442  *
1443  * @return  void
1444  */
1445 static void
1446 nfp_net_dev_interrupt_delayed_handler(void *param)
1447 {
1448         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1449
1450         nfp_net_link_update(dev, 0);
1451         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1452
1453         nfp_net_dev_link_status_print(dev);
1454
1455         /* Unmasking */
1456         nfp_net_irq_unmask(dev);
1457 }
1458
1459 static int
1460 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1461 {
1462         struct nfp_net_hw *hw;
1463
1464         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1465
1466         /* check that mtu is within the allowed range */
1467         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1468                 return -EINVAL;
1469
1470         /* switch to jumbo mode if needed */
1471         if ((uint32_t)mtu > ETHER_MAX_LEN)
1472                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1473         else
1474                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1475
1476         /* update max frame size */
1477         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1478
1479         /* writing to configuration space */
1480         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1481
1482         hw->mtu = mtu;
1483
1484         return 0;
1485 }
1486
1487 static int
1488 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1489                        uint16_t queue_idx, uint16_t nb_desc,
1490                        unsigned int socket_id,
1491                        const struct rte_eth_rxconf *rx_conf,
1492                        struct rte_mempool *mp)
1493 {
1494         const struct rte_memzone *tz;
1495         struct nfp_net_rxq *rxq;
1496         struct nfp_net_hw *hw;
1497
1498         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499
1500         PMD_INIT_FUNC_TRACE();
1501
1502         /* Validating number of descriptors */
1503         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1504             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1505             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1506                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1507                 return -EINVAL;
1508         }
1509
1510         /*
1511          * Free memory prior to re-allocation if needed. This is the case after
1512          * calling nfp_net_stop
1513          */
1514         if (dev->data->rx_queues[queue_idx]) {
1515                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1516                 dev->data->rx_queues[queue_idx] = NULL;
1517         }
1518
1519         /* Allocating rx queue data structure */
1520         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1521                                  RTE_CACHE_LINE_SIZE, socket_id);
1522         if (rxq == NULL)
1523                 return -ENOMEM;
1524
1525         /* Hw queues mapping based on firmware confifguration */
1526         rxq->qidx = queue_idx;
1527         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1528         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1529         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1530         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1531
1532         /*
1533          * Tracking mbuf size for detecting a potential mbuf overflow due to
1534          * RX offset
1535          */
1536         rxq->mem_pool = mp;
1537         rxq->mbuf_size = rxq->mem_pool->elt_size;
1538         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1539         hw->flbufsz = rxq->mbuf_size;
1540
1541         rxq->rx_count = nb_desc;
1542         rxq->port_id = dev->data->port_id;
1543         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1544         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1545                                   : ETHER_CRC_LEN);
1546         rxq->drop_en = rx_conf->rx_drop_en;
1547
1548         /*
1549          * Allocate RX ring hardware descriptors. A memzone large enough to
1550          * handle the maximum ring size is allocated in order to allow for
1551          * resizing in later calls to the queue setup function.
1552          */
1553         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1554                                    sizeof(struct nfp_net_rx_desc) *
1555                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1556                                    socket_id);
1557
1558         if (tz == NULL) {
1559                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1560                 nfp_net_rx_queue_release(rxq);
1561                 return -ENOMEM;
1562         }
1563
1564         /* Saving physical and virtual addresses for the RX ring */
1565         rxq->dma = (uint64_t)tz->iova;
1566         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1567
1568         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1569         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1570                                          sizeof(*rxq->rxbufs) * nb_desc,
1571                                          RTE_CACHE_LINE_SIZE, socket_id);
1572         if (rxq->rxbufs == NULL) {
1573                 nfp_net_rx_queue_release(rxq);
1574                 return -ENOMEM;
1575         }
1576
1577         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1578                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1579
1580         nfp_net_reset_rx_queue(rxq);
1581
1582         dev->data->rx_queues[queue_idx] = rxq;
1583         rxq->hw = hw;
1584
1585         /*
1586          * Telling the HW about the physical address of the RX ring and number
1587          * of descriptors in log2 format
1588          */
1589         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1590         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1591
1592         return 0;
1593 }
1594
1595 static int
1596 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1597 {
1598         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1599         uint64_t dma_addr;
1600         unsigned i;
1601
1602         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1603                    rxq->rx_count);
1604
1605         for (i = 0; i < rxq->rx_count; i++) {
1606                 struct nfp_net_rx_desc *rxd;
1607                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1608
1609                 if (mbuf == NULL) {
1610                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1611                                 (unsigned)rxq->qidx);
1612                         return -ENOMEM;
1613                 }
1614
1615                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1616
1617                 rxd = &rxq->rxds[i];
1618                 rxd->fld.dd = 0;
1619                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1620                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1621                 rxe[i].mbuf = mbuf;
1622                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1623         }
1624
1625         /* Make sure all writes are flushed before telling the hardware */
1626         rte_wmb();
1627
1628         /* Not advertising the whole ring as the firmware gets confused if so */
1629         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1630                    rxq->rx_count - 1);
1631
1632         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1633
1634         return 0;
1635 }
1636
1637 static int
1638 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1639                        uint16_t nb_desc, unsigned int socket_id,
1640                        const struct rte_eth_txconf *tx_conf)
1641 {
1642         const struct rte_memzone *tz;
1643         struct nfp_net_txq *txq;
1644         uint16_t tx_free_thresh;
1645         struct nfp_net_hw *hw;
1646
1647         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648
1649         PMD_INIT_FUNC_TRACE();
1650
1651         /* Validating number of descriptors */
1652         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1653             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1654             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1655                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1656                 return -EINVAL;
1657         }
1658
1659         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1660                                     tx_conf->tx_free_thresh :
1661                                     DEFAULT_TX_FREE_THRESH);
1662
1663         if (tx_free_thresh > (nb_desc)) {
1664                 RTE_LOG(ERR, PMD,
1665                         "tx_free_thresh must be less than the number of TX "
1666                         "descriptors. (tx_free_thresh=%u port=%d "
1667                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1668                         dev->data->port_id, (int)queue_idx);
1669                 return -(EINVAL);
1670         }
1671
1672         /*
1673          * Free memory prior to re-allocation if needed. This is the case after
1674          * calling nfp_net_stop
1675          */
1676         if (dev->data->tx_queues[queue_idx]) {
1677                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1678                            queue_idx);
1679                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1680                 dev->data->tx_queues[queue_idx] = NULL;
1681         }
1682
1683         /* Allocating tx queue data structure */
1684         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1685                                  RTE_CACHE_LINE_SIZE, socket_id);
1686         if (txq == NULL) {
1687                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1688                 return -ENOMEM;
1689         }
1690
1691         /*
1692          * Allocate TX ring hardware descriptors. A memzone large enough to
1693          * handle the maximum ring size is allocated in order to allow for
1694          * resizing in later calls to the queue setup function.
1695          */
1696         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1697                                    sizeof(struct nfp_net_tx_desc) *
1698                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1699                                    socket_id);
1700         if (tz == NULL) {
1701                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1702                 nfp_net_tx_queue_release(txq);
1703                 return -ENOMEM;
1704         }
1705
1706         txq->tx_count = nb_desc;
1707         txq->tx_free_thresh = tx_free_thresh;
1708         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1709         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1710         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1711
1712         /* queue mapping based on firmware configuration */
1713         txq->qidx = queue_idx;
1714         txq->tx_qcidx = queue_idx * hw->stride_tx;
1715         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1716
1717         txq->port_id = dev->data->port_id;
1718         txq->txq_flags = tx_conf->txq_flags;
1719
1720         /* Saving physical and virtual addresses for the TX ring */
1721         txq->dma = (uint64_t)tz->iova;
1722         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1723
1724         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1725         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1726                                          sizeof(*txq->txbufs) * nb_desc,
1727                                          RTE_CACHE_LINE_SIZE, socket_id);
1728         if (txq->txbufs == NULL) {
1729                 nfp_net_tx_queue_release(txq);
1730                 return -ENOMEM;
1731         }
1732         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1733                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1734
1735         nfp_net_reset_tx_queue(txq);
1736
1737         dev->data->tx_queues[queue_idx] = txq;
1738         txq->hw = hw;
1739
1740         /*
1741          * Telling the HW about the physical address of the TX ring and number
1742          * of descriptors in log2 format
1743          */
1744         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1745         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1746
1747         return 0;
1748 }
1749
1750 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1751 static inline void
1752 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1753                struct rte_mbuf *mb)
1754 {
1755         uint64_t ol_flags;
1756         struct nfp_net_hw *hw = txq->hw;
1757
1758         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1759                 goto clean_txd;
1760
1761         ol_flags = mb->ol_flags;
1762
1763         if (!(ol_flags & PKT_TX_TCP_SEG))
1764                 goto clean_txd;
1765
1766         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1767         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1768         txd->flags = PCIE_DESC_TX_LSO;
1769         return;
1770
1771 clean_txd:
1772         txd->flags = 0;
1773         txd->l4_offset = 0;
1774         txd->lso = 0;
1775 }
1776
1777 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1778 static inline void
1779 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1780                  struct rte_mbuf *mb)
1781 {
1782         uint64_t ol_flags;
1783         struct nfp_net_hw *hw = txq->hw;
1784
1785         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1786                 return;
1787
1788         ol_flags = mb->ol_flags;
1789
1790         /* IPv6 does not need checksum */
1791         if (ol_flags & PKT_TX_IP_CKSUM)
1792                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1793
1794         switch (ol_flags & PKT_TX_L4_MASK) {
1795         case PKT_TX_UDP_CKSUM:
1796                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1797                 break;
1798         case PKT_TX_TCP_CKSUM:
1799                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1800                 break;
1801         }
1802
1803         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1804                 txd->flags |= PCIE_DESC_TX_CSUM;
1805 }
1806
1807 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1808 static inline void
1809 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1810                  struct rte_mbuf *mb)
1811 {
1812         struct nfp_net_hw *hw = rxq->hw;
1813
1814         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1815                 return;
1816
1817         /* If IPv4 and IP checksum error, fail */
1818         if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1819             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1820                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1821
1822         /* If neither UDP nor TCP return */
1823         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1824             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1825                 return;
1826
1827         if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1828             !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1829                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1830
1831         if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1832             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1833                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1834 }
1835
1836 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1837 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1838
1839 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1840
1841 /*
1842  * nfp_net_set_hash - Set mbuf hash data
1843  *
1844  * The RSS hash and hash-type are pre-pended to the packet data.
1845  * Extract and decode it and set the mbuf fields.
1846  */
1847 static inline void
1848 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1849                  struct rte_mbuf *mbuf)
1850 {
1851         struct nfp_net_hw *hw = rxq->hw;
1852         uint8_t *meta_offset;
1853         uint32_t meta_info;
1854         uint32_t hash = 0;
1855         uint32_t hash_type = 0;
1856
1857         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1858                 return;
1859
1860         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1861                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1862                         return;
1863
1864                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1865                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1866
1867         } else if (NFP_DESC_META_LEN(rxd)) {
1868                 /*
1869                  * new metadata api:
1870                  * <----  32 bit  ----->
1871                  * m    field type word
1872                  * e     data field #2
1873                  * t     data field #1
1874                  * a     data field #0
1875                  * ====================
1876                  *    packet data
1877                  *
1878                  * Field type word contains up to 8 4bit field types
1879                  * A 4bit field type refers to a data field word
1880                  * A data field word can have several 4bit field types
1881                  */
1882                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1883                 meta_offset -= NFP_DESC_META_LEN(rxd);
1884                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1885                 meta_offset += 4;
1886                 /* NFP PMD just supports metadata for hashing */
1887                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1888                 case NFP_NET_META_HASH:
1889                         /* next field type is about the hash type */
1890                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1891                         /* hash value is in the data field */
1892                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1893                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1894                         break;
1895                 default:
1896                         /* Unsupported metadata can be a performance issue */
1897                         return;
1898                 }
1899         } else {
1900                 return;
1901         }
1902
1903         mbuf->hash.rss = hash;
1904         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1905
1906         switch (hash_type) {
1907         case NFP_NET_RSS_IPV4:
1908                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1909                 break;
1910         case NFP_NET_RSS_IPV6:
1911                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1912                 break;
1913         case NFP_NET_RSS_IPV6_EX:
1914                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1915                 break;
1916         default:
1917                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1918         }
1919 }
1920
1921 static inline void
1922 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1923 {
1924         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1925 }
1926
1927 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1928
1929 /*
1930  * RX path design:
1931  *
1932  * There are some decissions to take:
1933  * 1) How to check DD RX descriptors bit
1934  * 2) How and when to allocate new mbufs
1935  *
1936  * Current implementation checks just one single DD bit each loop. As each
1937  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1938  * a single cache line instead. Tests with this change have not shown any
1939  * performance improvement but it requires further investigation. For example,
1940  * depending on which descriptor is next, the number of descriptors could be
1941  * less than 8 for just checking those in the same cache line. This implies
1942  * extra work which could be counterproductive by itself. Indeed, last firmware
1943  * changes are just doing this: writing several descriptors with the DD bit
1944  * for saving PCIe bandwidth and DMA operations from the NFP.
1945  *
1946  * Mbuf allocation is done when a new packet is received. Then the descriptor
1947  * is automatically linked with the new mbuf and the old one is given to the
1948  * user. The main drawback with this design is mbuf allocation is heavier than
1949  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1950  * cache point of view it does not seem allocating the mbuf early on as we are
1951  * doing now have any benefit at all. Again, tests with this change have not
1952  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1953  * so looking at the implications of this type of allocation should be studied
1954  * deeply
1955  */
1956
1957 static uint16_t
1958 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1959 {
1960         struct nfp_net_rxq *rxq;
1961         struct nfp_net_rx_desc *rxds;
1962         struct nfp_net_rx_buff *rxb;
1963         struct nfp_net_hw *hw;
1964         struct rte_mbuf *mb;
1965         struct rte_mbuf *new_mb;
1966         uint16_t nb_hold;
1967         uint64_t dma_addr;
1968         int avail;
1969
1970         rxq = rx_queue;
1971         if (unlikely(rxq == NULL)) {
1972                 /*
1973                  * DPDK just checks the queue is lower than max queues
1974                  * enabled. But the queue needs to be configured
1975                  */
1976                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1977                 return -EINVAL;
1978         }
1979
1980         hw = rxq->hw;
1981         avail = 0;
1982         nb_hold = 0;
1983
1984         while (avail < nb_pkts) {
1985                 rxb = &rxq->rxbufs[rxq->rd_p];
1986                 if (unlikely(rxb == NULL)) {
1987                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1988                         break;
1989                 }
1990
1991                 /*
1992                  * Memory barrier to ensure that we won't do other
1993                  * reads before the DD bit.
1994                  */
1995                 rte_rmb();
1996
1997                 rxds = &rxq->rxds[rxq->rd_p];
1998                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1999                         break;
2000
2001                 /*
2002                  * We got a packet. Let's alloc a new mbuff for refilling the
2003                  * free descriptor ring as soon as possible
2004                  */
2005                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2006                 if (unlikely(new_mb == NULL)) {
2007                         RTE_LOG_DP(DEBUG, PMD,
2008                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2009                                 rxq->port_id, (unsigned int)rxq->qidx);
2010                         nfp_net_mbuf_alloc_failed(rxq);
2011                         break;
2012                 }
2013
2014                 nb_hold++;
2015
2016                 /*
2017                  * Grab the mbuff and refill the descriptor with the
2018                  * previously allocated mbuff
2019                  */
2020                 mb = rxb->mbuf;
2021                 rxb->mbuf = new_mb;
2022
2023                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2024                            rxds->rxd.data_len, rxq->mbuf_size);
2025
2026                 /* Size of this segment */
2027                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2028                 /* Size of the whole packet. We just support 1 segment */
2029                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2030
2031                 if (unlikely((mb->data_len + hw->rx_offset) >
2032                              rxq->mbuf_size)) {
2033                         /*
2034                          * This should not happen and the user has the
2035                          * responsibility of avoiding it. But we have
2036                          * to give some info about the error
2037                          */
2038                         RTE_LOG_DP(ERR, PMD,
2039                                 "mbuf overflow likely due to the RX offset.\n"
2040                                 "\t\tYour mbuf size should have extra space for"
2041                                 " RX offset=%u bytes.\n"
2042                                 "\t\tCurrently you just have %u bytes available"
2043                                 " but the received packet is %u bytes long",
2044                                 hw->rx_offset,
2045                                 rxq->mbuf_size - hw->rx_offset,
2046                                 mb->data_len);
2047                         return -EINVAL;
2048                 }
2049
2050                 /* Filling the received mbuff with packet info */
2051                 if (hw->rx_offset)
2052                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2053                 else
2054                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2055                                        NFP_DESC_META_LEN(rxds);
2056
2057                 /* No scatter mode supported */
2058                 mb->nb_segs = 1;
2059                 mb->next = NULL;
2060
2061                 /* Checking the RSS flag */
2062                 nfp_net_set_hash(rxq, rxds, mb);
2063
2064                 /* Checking the checksum flag */
2065                 nfp_net_rx_cksum(rxq, rxds, mb);
2066
2067                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2068                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2069                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2070                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2071                 }
2072
2073                 /* Adding the mbuff to the mbuff array passed by the app */
2074                 rx_pkts[avail++] = mb;
2075
2076                 /* Now resetting and updating the descriptor */
2077                 rxds->vals[0] = 0;
2078                 rxds->vals[1] = 0;
2079                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2080                 rxds->fld.dd = 0;
2081                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2082                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2083
2084                 rxq->rd_p++;
2085                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2086                         rxq->rd_p = 0;
2087         }
2088
2089         if (nb_hold == 0)
2090                 return nb_hold;
2091
2092         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2093                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2094
2095         nb_hold += rxq->nb_rx_hold;
2096
2097         /*
2098          * FL descriptors needs to be written before incrementing the
2099          * FL queue WR pointer
2100          */
2101         rte_wmb();
2102         if (nb_hold > rxq->rx_free_thresh) {
2103                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2104                            rxq->port_id, (unsigned int)rxq->qidx,
2105                            (unsigned)nb_hold, (unsigned)avail);
2106                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2107                 nb_hold = 0;
2108         }
2109         rxq->nb_rx_hold = nb_hold;
2110
2111         return avail;
2112 }
2113
2114 /*
2115  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2116  * status
2117  * @txq: TX queue to work with
2118  * Returns number of descriptors freed
2119  */
2120 int
2121 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2122 {
2123         uint32_t qcp_rd_p;
2124         int todo;
2125
2126         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2127                    " status\n", txq->qidx);
2128
2129         /* Work out how many packets have been sent */
2130         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2131
2132         if (qcp_rd_p == txq->rd_p) {
2133                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2134                            "packets (%u, %u)\n", txq->qidx,
2135                            qcp_rd_p, txq->rd_p);
2136                 return 0;
2137         }
2138
2139         if (qcp_rd_p > txq->rd_p)
2140                 todo = qcp_rd_p - txq->rd_p;
2141         else
2142                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2143
2144         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2145                    qcp_rd_p, txq->rd_p, txq->rd_p);
2146
2147         if (todo == 0)
2148                 return todo;
2149
2150         txq->rd_p += todo;
2151         if (unlikely(txq->rd_p >= txq->tx_count))
2152                 txq->rd_p -= txq->tx_count;
2153
2154         return todo;
2155 }
2156
2157 /* Leaving always free descriptors for avoiding wrapping confusion */
2158 static inline
2159 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2160 {
2161         if (txq->wr_p >= txq->rd_p)
2162                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2163         else
2164                 return txq->rd_p - txq->wr_p - 8;
2165 }
2166
2167 /*
2168  * nfp_net_txq_full - Check if the TX queue free descriptors
2169  * is below tx_free_threshold
2170  *
2171  * @txq: TX queue to check
2172  *
2173  * This function uses the host copy* of read/write pointers
2174  */
2175 static inline
2176 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2177 {
2178         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2179 }
2180
2181 static uint16_t
2182 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2183 {
2184         struct nfp_net_txq *txq;
2185         struct nfp_net_hw *hw;
2186         struct nfp_net_tx_desc *txds, txd;
2187         struct rte_mbuf *pkt;
2188         uint64_t dma_addr;
2189         int pkt_size, dma_size;
2190         uint16_t free_descs, issued_descs;
2191         struct rte_mbuf **lmbuf;
2192         int i;
2193
2194         txq = tx_queue;
2195         hw = txq->hw;
2196         txds = &txq->txds[txq->wr_p];
2197
2198         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2199                    txq->qidx, txq->wr_p, nb_pkts);
2200
2201         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2202                 nfp_net_tx_free_bufs(txq);
2203
2204         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2205         if (unlikely(free_descs == 0))
2206                 return 0;
2207
2208         pkt = *tx_pkts;
2209
2210         i = 0;
2211         issued_descs = 0;
2212         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2213                    txq->qidx, nb_pkts);
2214         /* Sending packets */
2215         while ((i < nb_pkts) && free_descs) {
2216                 /* Grabbing the mbuf linked to the current descriptor */
2217                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2218                 /* Warming the cache for releasing the mbuf later on */
2219                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2220
2221                 pkt = *(tx_pkts + i);
2222
2223                 if (unlikely((pkt->nb_segs > 1) &&
2224                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2225                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2226                         rte_panic("Multisegment packet unsupported\n");
2227                 }
2228
2229                 /* Checking if we have enough descriptors */
2230                 if (unlikely(pkt->nb_segs > free_descs))
2231                         goto xmit_end;
2232
2233                 /*
2234                  * Checksum and VLAN flags just in the first descriptor for a
2235                  * multisegment packet, but TSO info needs to be in all of them.
2236                  */
2237                 txd.data_len = pkt->pkt_len;
2238                 nfp_net_tx_tso(txq, &txd, pkt);
2239                 nfp_net_tx_cksum(txq, &txd, pkt);
2240
2241                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2242                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2243                         txd.flags |= PCIE_DESC_TX_VLAN;
2244                         txd.vlan = pkt->vlan_tci;
2245                 }
2246
2247                 /*
2248                  * mbuf data_len is the data in one segment and pkt_len data
2249                  * in the whole packet. When the packet is just one segment,
2250                  * then data_len = pkt_len
2251                  */
2252                 pkt_size = pkt->pkt_len;
2253
2254                 while (pkt) {
2255                         /* Copying TSO, VLAN and cksum info */
2256                         *txds = txd;
2257
2258                         /* Releasing mbuf used by this descriptor previously*/
2259                         if (*lmbuf)
2260                                 rte_pktmbuf_free_seg(*lmbuf);
2261
2262                         /*
2263                          * Linking mbuf with descriptor for being released
2264                          * next time descriptor is used
2265                          */
2266                         *lmbuf = pkt;
2267
2268                         dma_size = pkt->data_len;
2269                         dma_addr = rte_mbuf_data_iova(pkt);
2270                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2271                                    "%" PRIx64 "\n", dma_addr);
2272
2273                         /* Filling descriptors fields */
2274                         txds->dma_len = dma_size;
2275                         txds->data_len = txd.data_len;
2276                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2277                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2278                         ASSERT(free_descs > 0);
2279                         free_descs--;
2280
2281                         txq->wr_p++;
2282                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2283                                 txq->wr_p = 0;
2284
2285                         pkt_size -= dma_size;
2286                         if (!pkt_size)
2287                                 /* End of packet */
2288                                 txds->offset_eop |= PCIE_DESC_TX_EOP;
2289                         else
2290                                 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2291
2292                         pkt = pkt->next;
2293                         /* Referencing next free TX descriptor */
2294                         txds = &txq->txds[txq->wr_p];
2295                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2296                         issued_descs++;
2297                 }
2298                 i++;
2299         }
2300
2301 xmit_end:
2302         /* Increment write pointers. Force memory write before we let HW know */
2303         rte_wmb();
2304         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2305
2306         return i;
2307 }
2308
2309 static int
2310 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2311 {
2312         uint32_t new_ctrl, update;
2313         struct nfp_net_hw *hw;
2314         int ret;
2315
2316         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317         new_ctrl = 0;
2318
2319         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2320             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2321                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2322                         " ETH_VLAN_EXTEND_OFFLOAD");
2323
2324         /* Enable vlan strip if it is not configured yet */
2325         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2326             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2327                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2328
2329         /* Disable vlan strip just if it is configured */
2330         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2331             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2332                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2333
2334         if (new_ctrl == 0)
2335                 return 0;
2336
2337         update = NFP_NET_CFG_UPDATE_GEN;
2338
2339         ret = nfp_net_reconfig(hw, new_ctrl, update);
2340         if (!ret)
2341                 hw->ctrl = new_ctrl;
2342
2343         return ret;
2344 }
2345
2346 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2347 static int
2348 nfp_net_reta_update(struct rte_eth_dev *dev,
2349                     struct rte_eth_rss_reta_entry64 *reta_conf,
2350                     uint16_t reta_size)
2351 {
2352         uint32_t reta, mask;
2353         int i, j;
2354         int idx, shift;
2355         uint32_t update;
2356         struct nfp_net_hw *hw =
2357                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358
2359         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2360                 return -EINVAL;
2361
2362         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2363                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2364                         "(%d) doesn't match the number hardware can supported "
2365                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2366                 return -EINVAL;
2367         }
2368
2369         /*
2370          * Update Redirection Table. There are 128 8bit-entries which can be
2371          * manage as 32 32bit-entries
2372          */
2373         for (i = 0; i < reta_size; i += 4) {
2374                 /* Handling 4 RSS entries per loop */
2375                 idx = i / RTE_RETA_GROUP_SIZE;
2376                 shift = i % RTE_RETA_GROUP_SIZE;
2377                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2378
2379                 if (!mask)
2380                         continue;
2381
2382                 reta = 0;
2383                 /* If all 4 entries were set, don't need read RETA register */
2384                 if (mask != 0xF)
2385                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2386
2387                 for (j = 0; j < 4; j++) {
2388                         if (!(mask & (0x1 << j)))
2389                                 continue;
2390                         if (mask != 0xF)
2391                                 /* Clearing the entry bits */
2392                                 reta &= ~(0xFF << (8 * j));
2393                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2394                 }
2395                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2396                               reta);
2397         }
2398
2399         update = NFP_NET_CFG_UPDATE_RSS;
2400
2401         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2402                 return -EIO;
2403
2404         return 0;
2405 }
2406
2407  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2408 static int
2409 nfp_net_reta_query(struct rte_eth_dev *dev,
2410                    struct rte_eth_rss_reta_entry64 *reta_conf,
2411                    uint16_t reta_size)
2412 {
2413         uint8_t i, j, mask;
2414         int idx, shift;
2415         uint32_t reta;
2416         struct nfp_net_hw *hw;
2417
2418         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419
2420         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2421                 return -EINVAL;
2422
2423         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2424                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2425                         "(%d) doesn't match the number hardware can supported "
2426                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2427                 return -EINVAL;
2428         }
2429
2430         /*
2431          * Reading Redirection Table. There are 128 8bit-entries which can be
2432          * manage as 32 32bit-entries
2433          */
2434         for (i = 0; i < reta_size; i += 4) {
2435                 /* Handling 4 RSS entries per loop */
2436                 idx = i / RTE_RETA_GROUP_SIZE;
2437                 shift = i % RTE_RETA_GROUP_SIZE;
2438                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2439
2440                 if (!mask)
2441                         continue;
2442
2443                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2444                                     shift);
2445                 for (j = 0; j < 4; j++) {
2446                         if (!(mask & (0x1 << j)))
2447                                 continue;
2448                         reta_conf->reta[shift + j] =
2449                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2450                 }
2451         }
2452         return 0;
2453 }
2454
2455 static int
2456 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2457                         struct rte_eth_rss_conf *rss_conf)
2458 {
2459         uint32_t update;
2460         uint32_t cfg_rss_ctrl = 0;
2461         uint8_t key;
2462         uint64_t rss_hf;
2463         int i;
2464         struct nfp_net_hw *hw;
2465
2466         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467
2468         rss_hf = rss_conf->rss_hf;
2469
2470         /* Checking if RSS is enabled */
2471         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2472                 if (rss_hf != 0) { /* Enable RSS? */
2473                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2474                         return -EINVAL;
2475                 }
2476                 return 0; /* Nothing to do */
2477         }
2478
2479         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2480                 RTE_LOG(ERR, PMD, "hash key too long\n");
2481                 return -EINVAL;
2482         }
2483
2484         if (rss_hf & ETH_RSS_IPV4)
2485                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2486                                 NFP_NET_CFG_RSS_IPV4_TCP |
2487                                 NFP_NET_CFG_RSS_IPV4_UDP;
2488
2489         if (rss_hf & ETH_RSS_IPV6)
2490                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2491                                 NFP_NET_CFG_RSS_IPV6_TCP |
2492                                 NFP_NET_CFG_RSS_IPV6_UDP;
2493
2494         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2495         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2496
2497         /* configuring where to apply the RSS hash */
2498         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2499
2500         /* Writing the key byte a byte */
2501         for (i = 0; i < rss_conf->rss_key_len; i++) {
2502                 memcpy(&key, &rss_conf->rss_key[i], 1);
2503                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2504         }
2505
2506         /* Writing the key size */
2507         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2508
2509         update = NFP_NET_CFG_UPDATE_RSS;
2510
2511         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2512                 return -EIO;
2513
2514         return 0;
2515 }
2516
2517 static int
2518 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2519                           struct rte_eth_rss_conf *rss_conf)
2520 {
2521         uint64_t rss_hf;
2522         uint32_t cfg_rss_ctrl;
2523         uint8_t key;
2524         int i;
2525         struct nfp_net_hw *hw;
2526
2527         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528
2529         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2530                 return -EINVAL;
2531
2532         rss_hf = rss_conf->rss_hf;
2533         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2534
2535         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2536                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2537
2538         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2539                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2540
2541         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2542                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2543
2544         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2545                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2546
2547         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2548                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2549
2550         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2551                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2552
2553         /* Reading the key size */
2554         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2555
2556         /* Reading the key byte a byte */
2557         for (i = 0; i < rss_conf->rss_key_len; i++) {
2558                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2559                 memcpy(&rss_conf->rss_key[i], &key, 1);
2560         }
2561
2562         return 0;
2563 }
2564
2565 /* Initialise and register driver with DPDK Application */
2566 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2567         .dev_configure          = nfp_net_configure,
2568         .dev_start              = nfp_net_start,
2569         .dev_stop               = nfp_net_stop,
2570         .dev_close              = nfp_net_close,
2571         .promiscuous_enable     = nfp_net_promisc_enable,
2572         .promiscuous_disable    = nfp_net_promisc_disable,
2573         .link_update            = nfp_net_link_update,
2574         .stats_get              = nfp_net_stats_get,
2575         .stats_reset            = nfp_net_stats_reset,
2576         .dev_infos_get          = nfp_net_infos_get,
2577         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2578         .mtu_set                = nfp_net_dev_mtu_set,
2579         .vlan_offload_set       = nfp_net_vlan_offload_set,
2580         .reta_update            = nfp_net_reta_update,
2581         .reta_query             = nfp_net_reta_query,
2582         .rss_hash_update        = nfp_net_rss_hash_update,
2583         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2584         .rx_queue_setup         = nfp_net_rx_queue_setup,
2585         .rx_queue_release       = nfp_net_rx_queue_release,
2586         .rx_queue_count         = nfp_net_rx_queue_count,
2587         .tx_queue_setup         = nfp_net_tx_queue_setup,
2588         .tx_queue_release       = nfp_net_tx_queue_release,
2589         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2590         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2591 };
2592
2593 /*
2594  * All eth_dev created got its private data, but before nfp_net_init, that
2595  * private data is referencing private data for all the PF ports. This is due
2596  * to how the vNIC bars are mapped based on first port, so all ports need info
2597  * about port 0 private data. Inside nfp_net_init the private data pointer is
2598  * changed to the right address for each port once the bars have been mapped.
2599  *
2600  * This functions helps to find out which port and therefore which offset
2601  * inside the private data array to use.
2602  */
2603 static int
2604 get_pf_port_number(char *name)
2605 {
2606         char *pf_str = name;
2607         int size = 0;
2608
2609         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2610                 pf_str++;
2611
2612         if (size == 30)
2613                 /*
2614                  * This should not happen at all and it would mean major
2615                  * implementation fault.
2616                  */
2617                 rte_panic("nfp_net: problem with pf device name\n");
2618
2619         /* Expecting _portX with X within [0,7] */
2620         pf_str += 5;
2621
2622         return (int)strtol(pf_str, NULL, 10);
2623 }
2624
2625 static int
2626 nfp_net_init(struct rte_eth_dev *eth_dev)
2627 {
2628         struct rte_pci_device *pci_dev;
2629         struct nfp_net_hw *hw, *hwport0;
2630
2631         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2632         uint32_t start_q;
2633         int stride = 4;
2634
2635         nspu_desc_t *nspu_desc = NULL;
2636         uint64_t bar_offset;
2637         int port = 0;
2638
2639         PMD_INIT_FUNC_TRACE();
2640
2641         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2642
2643         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2644             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2645                 port = get_pf_port_number(eth_dev->data->name);
2646                 if (port < 0 || port > 7) {
2647                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2648                         return -ENODEV;
2649                 }
2650
2651                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2652
2653                 /* This points to port 0 private data */
2654                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2655
2656                 /* This points to the specific port private data */
2657                 hw = &hwport0[port];
2658                 hw->pf_port_idx = port;
2659         } else {
2660                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2661                 hwport0 = 0;
2662         }
2663
2664         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2665         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2666         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2667
2668         /* For secondary processes, the primary has done all the work */
2669         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2670                 return 0;
2671
2672         rte_eth_copy_pci_info(eth_dev, pci_dev);
2673
2674         hw->device_id = pci_dev->id.device_id;
2675         hw->vendor_id = pci_dev->id.vendor_id;
2676         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2677         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2678
2679         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2680                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2681                      pci_dev->addr.domain, pci_dev->addr.bus,
2682                      pci_dev->addr.devid, pci_dev->addr.function);
2683
2684         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2685         if (hw->ctrl_bar == NULL) {
2686                 RTE_LOG(ERR, PMD,
2687                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2688                 return -ENODEV;
2689         }
2690
2691         if (hw->is_pf && port == 0) {
2692                 nspu_desc = hw->nspu_desc;
2693
2694                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2695                         /*
2696                          * A firmware should be there after PF probe so this
2697                          * should not happen.
2698                          */
2699                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2700                         return -ENODEV;
2701                 }
2702
2703                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2704                 hw->ctrl_bar += bar_offset;
2705                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2706         }
2707
2708         if (port > 0) {
2709                 if (!hwport0->ctrl_bar)
2710                         return -ENODEV;
2711
2712                 /* address based on port0 offset */
2713                 hw->ctrl_bar = hwport0->ctrl_bar +
2714                                (port * NFP_PF_CSR_SLICE_SIZE);
2715         }
2716
2717         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2718
2719         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2720         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2721
2722         /* Work out where in the BAR the queues start. */
2723         switch (pci_dev->id.device_id) {
2724         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2725         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2726         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2727                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2728                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2729                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2730                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2731                 break;
2732         default:
2733                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2734                 return -ENODEV;
2735         }
2736
2737         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2738         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2739
2740         if (hw->is_pf && port == 0) {
2741                 /* configure access to tx/rx vNIC BARs */
2742                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2743                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2744                                     bar_offset);
2745                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2746
2747                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2748                 hwport0->hw_queues += bar_offset;
2749
2750                 /* Lets seize the chance to read eth table from hw */
2751                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2752                         return -ENODEV;
2753         }
2754
2755         if (hw->is_pf) {
2756                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2757                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2758                 eth_dev->data->dev_private = hw;
2759         } else {
2760                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2761                              tx_bar_off;
2762                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2763                              rx_bar_off;
2764         }
2765
2766         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2767                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2768
2769         nfp_net_cfg_queue_setup(hw);
2770
2771         /* Get some of the read-only fields from the config BAR */
2772         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2773         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2774         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2775         hw->mtu = hw->max_mtu;
2776
2777         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2778                 hw->rx_offset = NFP_NET_RX_OFFSET;
2779         else
2780                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2781
2782         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2783                      hw->ver, hw->max_mtu);
2784         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2785                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2786                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2787                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2788                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2789                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2790                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2791                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2792                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2793                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2794                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2795                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2796
2797         hw->ctrl = 0;
2798
2799         hw->stride_rx = stride;
2800         hw->stride_tx = stride;
2801
2802         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2803                      hw->max_rx_queues, hw->max_tx_queues);
2804
2805         /* Initializing spinlock for reconfigs */
2806         rte_spinlock_init(&hw->reconfig_lock);
2807
2808         /* Allocating memory for mac addr */
2809         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2810         if (eth_dev->data->mac_addrs == NULL) {
2811                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2812                 return -ENOMEM;
2813         }
2814
2815         if (hw->is_pf) {
2816                 nfp_net_pf_read_mac(hwport0, port);
2817                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2818         } else {
2819                 nfp_net_vf_read_mac(hw);
2820         }
2821
2822         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2823                 /* Using random mac addresses for VFs */
2824                 eth_random_addr(&hw->mac_addr[0]);
2825                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2826         }
2827
2828         /* Copying mac address to DPDK eth_dev struct */
2829         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2830                         &eth_dev->data->mac_addrs[0]);
2831
2832         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2833                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2834                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2835                      pci_dev->id.device_id,
2836                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2837                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2838
2839         /* Registering LSC interrupt handler */
2840         rte_intr_callback_register(&pci_dev->intr_handle,
2841                                    nfp_net_dev_interrupt_handler,
2842                                    (void *)eth_dev);
2843
2844         /* Telling the firmware about the LSC interrupt entry */
2845         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2846
2847         /* Recording current stats counters values */
2848         nfp_net_stats_reset(eth_dev);
2849
2850         return 0;
2851 }
2852
2853 static int
2854 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2855                   nfpu_desc_t *nfpu_desc, void **priv)
2856 {
2857         struct rte_eth_dev *eth_dev;
2858         struct nfp_net_hw *hw;
2859         char *port_name;
2860         int ret;
2861
2862         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2863         if (!port_name)
2864                 return -ENOMEM;
2865
2866         if (ports > 1)
2867                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2868         else
2869                 sprintf(port_name, "%s", dev->device.name);
2870
2871         eth_dev = rte_eth_dev_allocate(port_name);
2872         if (!eth_dev)
2873                 return -ENOMEM;
2874
2875         if (port == 0) {
2876                 *priv = rte_zmalloc(port_name,
2877                                     sizeof(struct nfp_net_adapter) * ports,
2878                                     RTE_CACHE_LINE_SIZE);
2879                 if (!*priv) {
2880                         rte_eth_dev_release_port(eth_dev);
2881                         return -ENOMEM;
2882                 }
2883         }
2884
2885         eth_dev->data->dev_private = *priv;
2886
2887         /*
2888          * dev_private pointing to port0 dev_private because we need
2889          * to configure vNIC bars based on port0 at nfp_net_init.
2890          * Then dev_private is adjusted per port.
2891          */
2892         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2893         hw->nspu_desc = nfpu_desc->nspu;
2894         hw->nfpu_desc = nfpu_desc;
2895         hw->is_pf = 1;
2896         if (ports > 1)
2897                 hw->pf_multiport_enabled = 1;
2898
2899         eth_dev->device = &dev->device;
2900         rte_eth_copy_pci_info(eth_dev, dev);
2901
2902         ret = nfp_net_init(eth_dev);
2903
2904         if (ret)
2905                 rte_eth_dev_release_port(eth_dev);
2906
2907         rte_free(port_name);
2908
2909         return ret;
2910 }
2911
2912 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2913                             struct rte_pci_device *dev)
2914 {
2915         nfpu_desc_t *nfpu_desc;
2916         nspu_desc_t *nspu_desc;
2917         uint64_t offset_symbol;
2918         uint8_t *bar_offset;
2919         int major, minor;
2920         int total_ports;
2921         void *priv = 0;
2922         int ret = -ENODEV;
2923         int i;
2924
2925         if (!dev)
2926                 return ret;
2927
2928         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2929         if (!nfpu_desc)
2930                 return -ENOMEM;
2931
2932         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2933                 RTE_LOG(ERR, PMD,
2934                         "nfpu_open failed\n");
2935                 goto nfpu_error;
2936         }
2937
2938         nspu_desc = nfpu_desc->nspu;
2939
2940
2941         /* Check NSP ABI version */
2942         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2943                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2944                 goto error;
2945         }
2946         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2947
2948         if ((major == 0) && (minor < 20)) {
2949                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2950                 goto error;
2951         }
2952
2953         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2954                                &offset_symbol);
2955         if (ret)
2956                 goto error;
2957
2958         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
2959         bar_offset += offset_symbol;
2960         total_ports = (uint32_t)*bar_offset;
2961         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
2962
2963         if (total_ports <= 0 || total_ports > 8) {
2964                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
2965                 ret = -ENODEV;
2966                 goto error;
2967         }
2968
2969         for (i = 0; i < total_ports; i++) {
2970                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
2971                 if (ret)
2972                         goto error;
2973         }
2974
2975         return 0;
2976
2977 error:
2978         nfpu_close(nfpu_desc);
2979 nfpu_error:
2980         rte_free(nfpu_desc);
2981
2982         return ret;
2983 }
2984
2985 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
2986         {
2987                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2988                                PCI_DEVICE_ID_NFP4000_PF_NIC)
2989         },
2990         {
2991                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2992                                PCI_DEVICE_ID_NFP6000_PF_NIC)
2993         },
2994         {
2995                 .vendor_id = 0,
2996         },
2997 };
2998
2999 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3000         {
3001                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3002                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3003         },
3004         {
3005                 .vendor_id = 0,
3006         },
3007 };
3008
3009 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3010         struct rte_pci_device *pci_dev)
3011 {
3012         return rte_eth_dev_pci_generic_probe(pci_dev,
3013                 sizeof(struct nfp_net_adapter), nfp_net_init);
3014 }
3015
3016 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3017 {
3018         struct rte_eth_dev *eth_dev;
3019         struct nfp_net_hw *hw, *hwport0;
3020         int port = 0;
3021
3022         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3023         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3024             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3025                 port = get_pf_port_number(eth_dev->data->name);
3026                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3027                 hw = &hwport0[port];
3028         } else {
3029                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3030         }
3031         /* hotplug is not possible with multiport PF */
3032         if (hw->pf_multiport_enabled)
3033                 return -ENOTSUP;
3034         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3035 }
3036
3037 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3038         .id_table = pci_id_nfp_pf_net_map,
3039         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3040         .probe = nfp_pf_pci_probe,
3041         .remove = eth_nfp_pci_remove,
3042 };
3043
3044 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3045         .id_table = pci_id_nfp_vf_net_map,
3046         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3047         .probe = eth_nfp_pci_probe,
3048         .remove = eth_nfp_pci_remove,
3049 };
3050
3051 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3052 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3053 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3054 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3055 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3056 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3057
3058 /*
3059  * Local variables:
3060  * c-file-style: "Linux"
3061  * indent-tabs-mode: t
3062  * End:
3063  */