drivers/net/nfp/nfp_net.c

   1 /*
   2  * Copyright (c) 2014, 2015 Netronome Systems, Inc.
   3  * All rights reserved.
   4  *
   5  * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *  this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *  notice, this list of conditions and the following disclaimer in the
  15  *  documentation and/or other materials provided with the distribution
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *  contributors may be used to endorse or promote products derived from this
  19  *  software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  25  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31  * POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * vim:shiftwidth=8:noexpandtab
  36  *
  37  * @file dpdk/pmd/nfp_net.c
  38  *
  39  * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
  40  */
  41
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_ethdev_pci.h>
  48 #include <rte_dev.h>
  49 #include <rte_ether.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memzone.h>
  52 #include <rte_mempool.h>
  53 #include <rte_version.h>
  54 #include <rte_string_fns.h>
  55 #include <rte_alarm.h>
  56 #include <rte_spinlock.h>
  57
  58 #include "nfp_nfpu.h"
  59 #include "nfp_net_pmd.h"
  60 #include "nfp_net_logs.h"
  61 #include "nfp_net_ctrl.h"
  62
  63 /* Prototypes */
  64 static void nfp_net_close(struct rte_eth_dev *dev);
  65 static int nfp_net_configure(struct rte_eth_dev *dev);
  66 static void nfp_net_dev_interrupt_handler(void *param);
  67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
  68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
  70                               struct rte_eth_dev_info *dev_info);
  71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
  72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
  74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
  75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
  76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
  77                                        uint16_t queue_idx);
  78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
  79                                   uint16_t nb_pkts);
  80 static void nfp_net_rx_queue_release(void *rxq);
  81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  82                                   uint16_t nb_desc, unsigned int socket_id,
  83                                   const struct rte_eth_rxconf *rx_conf,
  84                                   struct rte_mempool *mp);
  85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
  86 static void nfp_net_tx_queue_release(void *txq);
  87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  88                                   uint16_t nb_desc, unsigned int socket_id,
  89                                   const struct rte_eth_txconf *tx_conf);
  90 static int nfp_net_start(struct rte_eth_dev *dev);
  91 static int nfp_net_stats_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_stats *stats);
  93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
  94 static void nfp_net_stop(struct rte_eth_dev *dev);
  95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  96                                   uint16_t nb_pkts);
  97
  98 /*
  99  * The offset of the queue controller queues in the PCIe Target. These
 100  * happen to be at the same offset on the NFP6000 and the NFP3200 so
 101  * we use a single macro here.
 102  */
 103 #define NFP_PCIE_QUEUE(_q)      (0x800 * ((_q) & 0xff))
 104
 105 /* Maximum value which can be added to a queue with one transaction */
 106 #define NFP_QCP_MAX_ADD 0x7f
 107
 108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
 109         (uint64_t)((mb)->buf_iova + RTE_PKTMBUF_HEADROOM)
 110
 111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
 112 enum nfp_qcp_ptr {
 113         NFP_QCP_READ_PTR = 0,
 114         NFP_QCP_WRITE_PTR
 115 };
 116
 117 /*
 118  * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
 119  * @q: Base address for queue structure
 120  * @ptr: Add to the Read or Write pointer
 121  * @val: Value to add to the queue pointer
 122  *
 123  * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
 124  */
 125 static inline void
 126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
 127 {
 128         uint32_t off;
 129
 130         if (ptr == NFP_QCP_READ_PTR)
 131                 off = NFP_QCP_QUEUE_ADD_RPTR;
 132         else
 133                 off = NFP_QCP_QUEUE_ADD_WPTR;
 134
 135         while (val > NFP_QCP_MAX_ADD) {
 136                 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
 137                 val -= NFP_QCP_MAX_ADD;
 138         }
 139
 140         nn_writel(rte_cpu_to_le_32(val), q + off);
 141 }
 142
 143 /*
 144  * nfp_qcp_read - Read the current Read/Write pointer value for a queue
 145  * @q:  Base address for queue structure
 146  * @ptr: Read or Write pointer
 147  */
 148 static inline uint32_t
 149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
 150 {
 151         uint32_t off;
 152         uint32_t val;
 153
 154         if (ptr == NFP_QCP_READ_PTR)
 155                 off = NFP_QCP_QUEUE_STS_LO;
 156         else
 157                 off = NFP_QCP_QUEUE_STS_HI;
 158
 159         val = rte_cpu_to_le_32(nn_readl(q + off));
 160
 161         if (ptr == NFP_QCP_READ_PTR)
 162                 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
 163         else
 164                 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
 165 }
 166
 167 /*
 168  * Functions to read/write from/to Config BAR
 169  * Performs any endian conversion necessary.
 170  */
 171 static inline uint8_t
 172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
 173 {
 174         return nn_readb(hw->ctrl_bar + off);
 175 }
 176
 177 static inline void
 178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
 179 {
 180         nn_writeb(val, hw->ctrl_bar + off);
 181 }
 182
 183 static inline uint32_t
 184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
 185 {
 186         return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
 187 }
 188
 189 static inline void
 190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
 191 {
 192         nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
 193 }
 194
 195 static inline uint64_t
 196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
 197 {
 198         return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
 199 }
 200
 201 static inline void
 202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
 203 {
 204         nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
 205 }
 206
 207 /*
 208  * Atomically reads link status information from global structure rte_eth_dev.
 209  *
 210  * @param dev
 211  *   - Pointer to the structure rte_eth_dev to read from.
 212  *   - Pointer to the buffer to be saved with the link status.
 213  *
 214  * @return
 215  *   - On success, zero.
 216  *   - On failure, negative value.
 217  */
 218 static inline int
 219 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 220                                     struct rte_eth_link *link)
 221 {
 222         struct rte_eth_link *dst = link;
 223         struct rte_eth_link *src = &dev->data->dev_link;
 224
 225         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 226                                 *(uint64_t *)src) == 0)
 227                 return -1;
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * Atomically writes the link status information into global
 234  * structure rte_eth_dev.
 235  *
 236  * @param dev
 237  *   - Pointer to the structure rte_eth_dev to read from.
 238  *   - Pointer to the buffer to be saved with the link status.
 239  *
 240  * @return
 241  *   - On success, zero.
 242  *   - On failure, negative value.
 243  */
 244 static inline int
 245 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 246                                      struct rte_eth_link *link)
 247 {
 248         struct rte_eth_link *dst = &dev->data->dev_link;
 249         struct rte_eth_link *src = link;
 250
 251         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 252                                 *(uint64_t *)src) == 0)
 253                 return -1;
 254
 255         return 0;
 256 }
 257
 258 static void
 259 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
 260 {
 261         unsigned i;
 262
 263         if (rxq->rxbufs == NULL)
 264                 return;
 265
 266         for (i = 0; i < rxq->rx_count; i++) {
 267                 if (rxq->rxbufs[i].mbuf) {
 268                         rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
 269                         rxq->rxbufs[i].mbuf = NULL;
 270                 }
 271         }
 272 }
 273
 274 static void
 275 nfp_net_rx_queue_release(void *rx_queue)
 276 {
 277         struct nfp_net_rxq *rxq = rx_queue;
 278
 279         if (rxq) {
 280                 nfp_net_rx_queue_release_mbufs(rxq);
 281                 rte_free(rxq->rxbufs);
 282                 rte_free(rxq);
 283         }
 284 }
 285
 286 static void
 287 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
 288 {
 289         nfp_net_rx_queue_release_mbufs(rxq);
 290         rxq->rd_p = 0;
 291         rxq->nb_rx_hold = 0;
 292 }
 293
 294 static void
 295 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
 296 {
 297         unsigned i;
 298
 299         if (txq->txbufs == NULL)
 300                 return;
 301
 302         for (i = 0; i < txq->tx_count; i++) {
 303                 if (txq->txbufs[i].mbuf) {
 304                         rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
 305                         txq->txbufs[i].mbuf = NULL;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 nfp_net_tx_queue_release(void *tx_queue)
 312 {
 313         struct nfp_net_txq *txq = tx_queue;
 314
 315         if (txq) {
 316                 nfp_net_tx_queue_release_mbufs(txq);
 317                 rte_free(txq->txbufs);
 318                 rte_free(txq);
 319         }
 320 }
 321
 322 static void
 323 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
 324 {
 325         nfp_net_tx_queue_release_mbufs(txq);
 326         txq->wr_p = 0;
 327         txq->rd_p = 0;
 328 }
 329
 330 static int
 331 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
 332 {
 333         int cnt;
 334         uint32_t new;
 335         struct timespec wait;
 336
 337         PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
 338                     hw->qcp_cfg);
 339
 340         if (hw->qcp_cfg == NULL)
 341                 rte_panic("Bad configuration queue pointer\n");
 342
 343         nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
 344
 345         wait.tv_sec = 0;
 346         wait.tv_nsec = 1000000;
 347
 348         PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
 349
 350         /* Poll update field, waiting for NFP to ack the config */
 351         for (cnt = 0; ; cnt++) {
 352                 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
 353                 if (new == 0)
 354                         break;
 355                 if (new & NFP_NET_CFG_UPDATE_ERR) {
 356                         PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
 357                         return -1;
 358                 }
 359                 if (cnt >= NFP_NET_POLL_TIMEOUT) {
 360                         PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
 361                                           " %dms", update, cnt);
 362                         rte_panic("Exiting\n");
 363                 }
 364                 nanosleep(&wait, 0); /* waiting for a 1ms */
 365         }
 366         PMD_DRV_LOG(DEBUG, "Ack DONE\n");
 367         return 0;
 368 }
 369
 370 /*
 371  * Reconfigure the NIC
 372  * @nn:    device to reconfigure
 373  * @ctrl:    The value for the ctrl field in the BAR config
 374  * @update:  The value for the update field in the BAR config
 375  *
 376  * Write the update word to the BAR and ping the reconfig queue. Then poll
 377  * until the firmware has acknowledged the update by zeroing the update word.
 378  */
 379 static int
 380 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
 381 {
 382         uint32_t err;
 383
 384         PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
 385                     ctrl, update);
 386
 387         rte_spinlock_lock(&hw->reconfig_lock);
 388
 389         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
 390         nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
 391
 392         rte_wmb();
 393
 394         err = __nfp_net_reconfig(hw, update);
 395
 396         rte_spinlock_unlock(&hw->reconfig_lock);
 397
 398         if (!err)
 399                 return 0;
 400
 401         /*
 402          * Reconfig errors imply situations where they can be handled.
 403          * Otherwise, rte_panic is called inside __nfp_net_reconfig
 404          */
 405         PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
 406                      ctrl, update);
 407         return -EIO;
 408 }
 409
 410 /*
 411  * Configure an Ethernet device. This function must be invoked first
 412  * before any other function in the Ethernet API. This function can
 413  * also be re-invoked when a device is in the stopped state.
 414  */
 415 static int
 416 nfp_net_configure(struct rte_eth_dev *dev)
 417 {
 418         struct rte_eth_conf *dev_conf;
 419         struct rte_eth_rxmode *rxmode;
 420         struct rte_eth_txmode *txmode;
 421         uint32_t new_ctrl = 0;
 422         uint32_t update = 0;
 423         struct nfp_net_hw *hw;
 424
 425         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 426
 427         /*
 428          * A DPDK app sends info about how many queues to use and how
 429          * those queues need to be configured. This is used by the
 430          * DPDK core and it makes sure no more queues than those
 431          * advertised by the driver are requested. This function is
 432          * called after that internal process
 433          */
 434
 435         PMD_INIT_LOG(DEBUG, "Configure");
 436
 437         dev_conf = &dev->data->dev_conf;
 438         rxmode = &dev_conf->rxmode;
 439         txmode = &dev_conf->txmode;
 440
 441         /* Checking TX mode */
 442         if (txmode->mq_mode) {
 443                 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
 444                 return -EINVAL;
 445         }
 446
 447         /* Checking RX mode */
 448         if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
 449                 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
 450                         update = NFP_NET_CFG_UPDATE_RSS;
 451                         new_ctrl = NFP_NET_CFG_CTRL_RSS;
 452                 } else {
 453                         PMD_INIT_LOG(INFO, "RSS not supported");
 454                         return -EINVAL;
 455                 }
 456         }
 457
 458         if (rxmode->split_hdr_size) {
 459                 PMD_INIT_LOG(INFO, "rxmode does not support split header");
 460                 return -EINVAL;
 461         }
 462
 463         if (rxmode->hw_ip_checksum) {
 464                 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
 465                         new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
 466                 } else {
 467                         PMD_INIT_LOG(INFO, "RXCSUM not supported");
 468                         return -EINVAL;
 469                 }
 470         }
 471
 472         if (rxmode->hw_vlan_filter) {
 473                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 474                 return -EINVAL;
 475         }
 476
 477         if (rxmode->hw_vlan_strip) {
 478                 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
 479                         new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
 480                 } else {
 481                         PMD_INIT_LOG(INFO, "hw vlan strip not supported");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         if (rxmode->hw_vlan_extend) {
 487                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 488                 return -EINVAL;
 489         }
 490
 491         if (rxmode->jumbo_frame)
 492                 hw->mtu = rxmode->max_rx_pkt_len;
 493
 494         if (!rxmode->hw_strip_crc)
 495                 PMD_INIT_LOG(INFO, "HW does strip CRC and it is not configurable");
 496
 497         if (rxmode->enable_scatter) {
 498                 PMD_INIT_LOG(INFO, "Scatter not supported");
 499                 return -EINVAL;
 500         }
 501
 502         /* If next capabilities are supported, configure them by default */
 503
 504         /* VLAN insertion */
 505         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
 506                 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
 507
 508         /* L2 broadcast */
 509         if (hw->cap & NFP_NET_CFG_CTRL_L2BC)
 510                 new_ctrl |= NFP_NET_CFG_CTRL_L2BC;
 511
 512         /* L2 multicast */
 513         if (hw->cap & NFP_NET_CFG_CTRL_L2MC)
 514                 new_ctrl |= NFP_NET_CFG_CTRL_L2MC;
 515
 516         /* TX checksum offload */
 517         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
 518                 new_ctrl |= NFP_NET_CFG_CTRL_TXCSUM;
 519
 520         /* LSO offload */
 521         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
 522                 new_ctrl |= NFP_NET_CFG_CTRL_LSO;
 523
 524         /* RX gather */
 525         if (hw->cap & NFP_NET_CFG_CTRL_GATHER)
 526                 new_ctrl |= NFP_NET_CFG_CTRL_GATHER;
 527
 528         if (!new_ctrl)
 529                 return 0;
 530
 531         update |= NFP_NET_CFG_UPDATE_GEN;
 532
 533         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 534         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 535                 return -EIO;
 536
 537         hw->ctrl = new_ctrl;
 538
 539         return 0;
 540 }
 541
 542 static void
 543 nfp_net_enable_queues(struct rte_eth_dev *dev)
 544 {
 545         struct nfp_net_hw *hw;
 546         uint64_t enabled_queues = 0;
 547         int i;
 548
 549         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 550
 551         /* Enabling the required TX queues in the device */
 552         for (i = 0; i < dev->data->nb_tx_queues; i++)
 553                 enabled_queues |= (1 << i);
 554
 555         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
 556
 557         enabled_queues = 0;
 558
 559         /* Enabling the required RX queues in the device */
 560         for (i = 0; i < dev->data->nb_rx_queues; i++)
 561                 enabled_queues |= (1 << i);
 562
 563         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
 564 }
 565
 566 static void
 567 nfp_net_disable_queues(struct rte_eth_dev *dev)
 568 {
 569         struct nfp_net_hw *hw;
 570         uint32_t new_ctrl, update = 0;
 571
 572         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
 575         nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
 576
 577         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
 578         update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
 579                  NFP_NET_CFG_UPDATE_MSIX;
 580
 581         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 582                 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
 583
 584         /* If an error when reconfig we avoid to change hw state */
 585         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 586                 return;
 587
 588         hw->ctrl = new_ctrl;
 589 }
 590
 591 static int
 592 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
 593 {
 594         int i;
 595
 596         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 597                 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
 598                         return -1;
 599         }
 600         return 0;
 601 }
 602
 603 static void
 604 nfp_net_params_setup(struct nfp_net_hw *hw)
 605 {
 606         nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
 607         nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
 608 }
 609
 610 static void
 611 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
 612 {
 613         hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
 614 }
 615
 616 #define ETH_ADDR_LEN    6
 617
 618 static void
 619 nfp_eth_copy_mac_reverse(uint8_t *dst, const uint8_t *src)
 620 {
 621         int i;
 622
 623         for (i = 0; i < ETH_ADDR_LEN; i++)
 624                 dst[ETH_ADDR_LEN - i - 1] = src[i];
 625 }
 626
 627 static int
 628 nfp_net_pf_read_mac(struct nfp_net_hw *hw, int port)
 629 {
 630         union eth_table_entry *entry;
 631         int idx, i;
 632
 633         idx = port;
 634         entry = hw->eth_table;
 635
 636         /* Reading NFP ethernet table obtained before */
 637         for (i = 0; i < NSP_ETH_MAX_COUNT; i++) {
 638                 if (!(entry->port & NSP_ETH_PORT_LANES_MASK)) {
 639                         /* port not in use */
 640                         entry++;
 641                         continue;
 642                 }
 643                 if (idx == 0)
 644                         break;
 645                 idx--;
 646                 entry++;
 647         }
 648
 649         if (i == NSP_ETH_MAX_COUNT)
 650                 return -EINVAL;
 651
 652         /*
 653          * hw points to port0 private data. We need hw now pointing to
 654          * right port.
 655          */
 656         hw += port;
 657         nfp_eth_copy_mac_reverse((uint8_t *)&hw->mac_addr,
 658                                  (uint8_t *)&entry->mac_addr);
 659
 660         return 0;
 661 }
 662
 663 static void
 664 nfp_net_vf_read_mac(struct nfp_net_hw *hw)
 665 {
 666         uint32_t tmp;
 667
 668         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
 669         memcpy(&hw->mac_addr[0], &tmp, 4);
 670
 671         tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
 672         memcpy(&hw->mac_addr[4], &tmp, 2);
 673 }
 674
 675 static void
 676 nfp_net_write_mac(struct nfp_net_hw *hw, uint8_t *mac)
 677 {
 678         uint32_t mac0 = *(uint32_t *)mac;
 679         uint16_t mac1;
 680
 681         nn_writel(rte_cpu_to_be_32(mac0), hw->ctrl_bar + NFP_NET_CFG_MACADDR);
 682
 683         mac += 4;
 684         mac1 = *(uint16_t *)mac;
 685         nn_writew(rte_cpu_to_be_16(mac1),
 686                   hw->ctrl_bar + NFP_NET_CFG_MACADDR + 6);
 687 }
 688
 689 static int
 690 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
 691                            struct rte_intr_handle *intr_handle)
 692 {
 693         struct nfp_net_hw *hw;
 694         int i;
 695
 696         if (!intr_handle->intr_vec) {
 697                 intr_handle->intr_vec =
 698                         rte_zmalloc("intr_vec",
 699                                     dev->data->nb_rx_queues * sizeof(int), 0);
 700                 if (!intr_handle->intr_vec) {
 701                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 702                                      " intr_vec", dev->data->nb_rx_queues);
 703                         return -ENOMEM;
 704                 }
 705         }
 706
 707         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 708
 709         if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 710                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
 711                 /* UIO just supports one queue and no LSC*/
 712                 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
 713                 intr_handle->intr_vec[0] = 0;
 714         } else {
 715                 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
 716                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 717                         /*
 718                          * The first msix vector is reserved for non
 719                          * efd interrupts
 720                         */
 721                         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
 722                         intr_handle->intr_vec[i] = i + 1;
 723                         PMD_INIT_LOG(DEBUG, "intr_vec[%d]= %d\n", i,
 724                                             intr_handle->intr_vec[i]);
 725                 }
 726         }
 727
 728         /* Avoiding TX interrupts */
 729         hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
 730         return 0;
 731 }
 732
 733 static int
 734 nfp_net_start(struct rte_eth_dev *dev)
 735 {
 736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 738         uint32_t new_ctrl, update = 0;
 739         struct nfp_net_hw *hw;
 740         uint32_t intr_vector;
 741         int ret;
 742
 743         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 744
 745         PMD_INIT_LOG(DEBUG, "Start");
 746
 747         /* Disabling queues just in case... */
 748         nfp_net_disable_queues(dev);
 749
 750         /* Writing configuration parameters in the device */
 751         nfp_net_params_setup(hw);
 752
 753         /* Enabling the required queues in the device */
 754         nfp_net_enable_queues(dev);
 755
 756         /* check and configure queue intr-vector mapping */
 757         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 758                 if (hw->pf_multiport_enabled) {
 759                         PMD_INIT_LOG(ERR, "PMD rx interrupt is not supported "
 760                                           "with NFP multiport PF");
 761                                 return -EINVAL;
 762                 }
 763                 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
 764                         /*
 765                          * Better not to share LSC with RX interrupts.
 766                          * Unregistering LSC interrupt handler
 767                          */
 768                         rte_intr_callback_unregister(&pci_dev->intr_handle,
 769                                 nfp_net_dev_interrupt_handler, (void *)dev);
 770
 771                         if (dev->data->nb_rx_queues > 1) {
 772                                 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
 773                                              "supports 1 queue with UIO");
 774                                 return -EIO;
 775                         }
 776                 }
 777                 intr_vector = dev->data->nb_rx_queues;
 778                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 779                         return -1;
 780
 781                 nfp_configure_rx_interrupt(dev, intr_handle);
 782                 update = NFP_NET_CFG_UPDATE_MSIX;
 783         }
 784
 785         rte_intr_enable(intr_handle);
 786
 787         /* Enable device */
 788         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
 789
 790         update |= NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
 791
 792         if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
 793                 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
 794
 795         nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
 796         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 797                 return -EIO;
 798
 799         /*
 800          * Allocating rte mbuffs for configured rx queues.
 801          * This requires queues being enabled before
 802          */
 803         if (nfp_net_rx_freelist_setup(dev) < 0) {
 804                 ret = -ENOMEM;
 805                 goto error;
 806         }
 807
 808         if (hw->is_pf)
 809                 /* Configure the physical port up */
 810                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 1);
 811
 812         hw->ctrl = new_ctrl;
 813
 814         return 0;
 815
 816 error:
 817         /*
 818          * An error returned by this function should mean the app
 819          * exiting and then the system releasing all the memory
 820          * allocated even memory coming from hugepages.
 821          *
 822          * The device could be enabled at this point with some queues
 823          * ready for getting packets. This is true if the call to
 824          * nfp_net_rx_freelist_setup() succeeds for some queues but
 825          * fails for subsequent queues.
 826          *
 827          * This should make the app exiting but better if we tell the
 828          * device first.
 829          */
 830         nfp_net_disable_queues(dev);
 831
 832         return ret;
 833 }
 834
 835 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
 836 static void
 837 nfp_net_stop(struct rte_eth_dev *dev)
 838 {
 839         int i;
 840         struct nfp_net_hw *hw;
 841
 842         PMD_INIT_LOG(DEBUG, "Stop");
 843
 844         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845
 846         nfp_net_disable_queues(dev);
 847
 848         /* Clear queues */
 849         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 850                 nfp_net_reset_tx_queue(
 851                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 852         }
 853
 854         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 855                 nfp_net_reset_rx_queue(
 856                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 857         }
 858
 859         if (hw->is_pf)
 860                 /* Configure the physical port down */
 861                 nfp_nsp_eth_config(hw->nspu_desc, hw->pf_port_idx, 0);
 862 }
 863
 864 /* Reset and stop device. The device can not be restarted. */
 865 static void
 866 nfp_net_close(struct rte_eth_dev *dev)
 867 {
 868         struct nfp_net_hw *hw;
 869         struct rte_pci_device *pci_dev;
 870         int i;
 871
 872         PMD_INIT_LOG(DEBUG, "Close");
 873
 874         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 875         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 876
 877         /*
 878          * We assume that the DPDK application is stopping all the
 879          * threads/queues before calling the device close function.
 880          */
 881
 882         nfp_net_disable_queues(dev);
 883
 884         /* Clear queues */
 885         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 886                 nfp_net_reset_tx_queue(
 887                         (struct nfp_net_txq *)dev->data->tx_queues[i]);
 888         }
 889
 890         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 891                 nfp_net_reset_rx_queue(
 892                         (struct nfp_net_rxq *)dev->data->rx_queues[i]);
 893         }
 894
 895         rte_intr_disable(&pci_dev->intr_handle);
 896         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
 897
 898         /* unregister callback func from eal lib */
 899         rte_intr_callback_unregister(&pci_dev->intr_handle,
 900                                      nfp_net_dev_interrupt_handler,
 901                                      (void *)dev);
 902
 903         /*
 904          * The ixgbe PMD driver disables the pcie master on the
 905          * device. The i40e does not...
 906          */
 907 }
 908
 909 static void
 910 nfp_net_promisc_enable(struct rte_eth_dev *dev)
 911 {
 912         uint32_t new_ctrl, update = 0;
 913         struct nfp_net_hw *hw;
 914
 915         PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
 916
 917         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918
 919         if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
 920                 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
 921                 return;
 922         }
 923
 924         if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
 925                 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
 926                 return;
 927         }
 928
 929         new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
 930         update = NFP_NET_CFG_UPDATE_GEN;
 931
 932         /*
 933          * DPDK sets promiscuous mode on just after this call assuming
 934          * it can not fail ...
 935          */
 936         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 937                 return;
 938
 939         hw->ctrl = new_ctrl;
 940 }
 941
 942 static void
 943 nfp_net_promisc_disable(struct rte_eth_dev *dev)
 944 {
 945         uint32_t new_ctrl, update = 0;
 946         struct nfp_net_hw *hw;
 947
 948         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949
 950         if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
 951                 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
 952                 return;
 953         }
 954
 955         new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
 956         update = NFP_NET_CFG_UPDATE_GEN;
 957
 958         /*
 959          * DPDK sets promiscuous mode off just before this call
 960          * assuming it can not fail ...
 961          */
 962         if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
 963                 return;
 964
 965         hw->ctrl = new_ctrl;
 966 }
 967
 968 /*
 969  * return 0 means link status changed, -1 means not changed
 970  *
 971  * Wait to complete is needed as it can take up to 9 seconds to get the Link
 972  * status.
 973  */
 974 static int
 975 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
 976 {
 977         struct nfp_net_hw *hw;
 978         struct rte_eth_link link, old;
 979         uint32_t nn_link_status;
 980
 981         static const uint32_t ls_to_ethtool[] = {
 982                 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
 983                 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN]     = ETH_SPEED_NUM_NONE,
 984                 [NFP_NET_CFG_STS_LINK_RATE_1G]          = ETH_SPEED_NUM_1G,
 985                 [NFP_NET_CFG_STS_LINK_RATE_10G]         = ETH_SPEED_NUM_10G,
 986                 [NFP_NET_CFG_STS_LINK_RATE_25G]         = ETH_SPEED_NUM_25G,
 987                 [NFP_NET_CFG_STS_LINK_RATE_40G]         = ETH_SPEED_NUM_40G,
 988                 [NFP_NET_CFG_STS_LINK_RATE_50G]         = ETH_SPEED_NUM_50G,
 989                 [NFP_NET_CFG_STS_LINK_RATE_100G]        = ETH_SPEED_NUM_100G,
 990         };
 991
 992         PMD_DRV_LOG(DEBUG, "Link update\n");
 993
 994         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995
 996         memset(&old, 0, sizeof(old));
 997         nfp_net_dev_atomic_read_link_status(dev, &old);
 998
 999         nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
1000
1001         memset(&link, 0, sizeof(struct rte_eth_link));
1002
1003         if (nn_link_status & NFP_NET_CFG_STS_LINK)
1004                 link.link_status = ETH_LINK_UP;
1005
1006         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1007
1008         nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
1009                          NFP_NET_CFG_STS_LINK_RATE_MASK;
1010
1011         if (nn_link_status >= RTE_DIM(ls_to_ethtool))
1012                 link.link_speed = ETH_SPEED_NUM_NONE;
1013         else
1014                 link.link_speed = ls_to_ethtool[nn_link_status];
1015
1016         if (old.link_status != link.link_status) {
1017                 nfp_net_dev_atomic_write_link_status(dev, &link);
1018                 if (link.link_status)
1019                         PMD_DRV_LOG(INFO, "NIC Link is Up\n");
1020                 else
1021                         PMD_DRV_LOG(INFO, "NIC Link is Down\n");
1022                 return 0;
1023         }
1024
1025         return -1;
1026 }
1027
1028 static int
1029 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1030 {
1031         int i;
1032         struct nfp_net_hw *hw;
1033         struct rte_eth_stats nfp_dev_stats;
1034
1035         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036
1037         /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
1038
1039         memset(&nfp_dev_stats, 0, sizeof(nfp_dev_stats));
1040
1041         /* reading per RX ring stats */
1042         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1043                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1044                         break;
1045
1046                 nfp_dev_stats.q_ipackets[i] =
1047                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1048
1049                 nfp_dev_stats.q_ipackets[i] -=
1050                         hw->eth_stats_base.q_ipackets[i];
1051
1052                 nfp_dev_stats.q_ibytes[i] =
1053                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1054
1055                 nfp_dev_stats.q_ibytes[i] -=
1056                         hw->eth_stats_base.q_ibytes[i];
1057         }
1058
1059         /* reading per TX ring stats */
1060         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1061                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1062                         break;
1063
1064                 nfp_dev_stats.q_opackets[i] =
1065                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1066
1067                 nfp_dev_stats.q_opackets[i] -=
1068                         hw->eth_stats_base.q_opackets[i];
1069
1070                 nfp_dev_stats.q_obytes[i] =
1071                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1072
1073                 nfp_dev_stats.q_obytes[i] -=
1074                         hw->eth_stats_base.q_obytes[i];
1075         }
1076
1077         nfp_dev_stats.ipackets =
1078                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1079
1080         nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
1081
1082         nfp_dev_stats.ibytes =
1083                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1084
1085         nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1086
1087         nfp_dev_stats.opackets =
1088                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1089
1090         nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1091
1092         nfp_dev_stats.obytes =
1093                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1094
1095         nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1096
1097         /* reading general device stats */
1098         nfp_dev_stats.ierrors =
1099                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1100
1101         nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1102
1103         nfp_dev_stats.oerrors =
1104                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1105
1106         nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1107
1108         /* RX ring mbuf allocation failures */
1109         nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1110
1111         nfp_dev_stats.imissed =
1112                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1113
1114         nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1115
1116         if (stats) {
1117                 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1118                 return 0;
1119         }
1120         return -EINVAL;
1121 }
1122
1123 static void
1124 nfp_net_stats_reset(struct rte_eth_dev *dev)
1125 {
1126         int i;
1127         struct nfp_net_hw *hw;
1128
1129         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130
1131         /*
1132          * hw->eth_stats_base records the per counter starting point.
1133          * Lets update it now
1134          */
1135
1136         /* reading per RX ring stats */
1137         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1138                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1139                         break;
1140
1141                 hw->eth_stats_base.q_ipackets[i] =
1142                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1143
1144                 hw->eth_stats_base.q_ibytes[i] =
1145                         nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1146         }
1147
1148         /* reading per TX ring stats */
1149         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1150                 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1151                         break;
1152
1153                 hw->eth_stats_base.q_opackets[i] =
1154                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1155
1156                 hw->eth_stats_base.q_obytes[i] =
1157                         nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1158         }
1159
1160         hw->eth_stats_base.ipackets =
1161                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1162
1163         hw->eth_stats_base.ibytes =
1164                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1165
1166         hw->eth_stats_base.opackets =
1167                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1168
1169         hw->eth_stats_base.obytes =
1170                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1171
1172         /* reading general device stats */
1173         hw->eth_stats_base.ierrors =
1174                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1175
1176         hw->eth_stats_base.oerrors =
1177                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1178
1179         /* RX ring mbuf allocation failures */
1180         dev->data->rx_mbuf_alloc_failed = 0;
1181
1182         hw->eth_stats_base.imissed =
1183                 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1184 }
1185
1186 static void
1187 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1188 {
1189         struct nfp_net_hw *hw;
1190
1191         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192
1193         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1194         dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1195         dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1196         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1197         dev_info->max_rx_pktlen = hw->max_mtu;
1198         /* Next should change when PF support is implemented */
1199         dev_info->max_mac_addrs = 1;
1200
1201         if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1202                 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1203
1204         if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1205                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1206                                              DEV_RX_OFFLOAD_UDP_CKSUM |
1207                                              DEV_RX_OFFLOAD_TCP_CKSUM;
1208
1209         if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1210                 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1211
1212         if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1213                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1214                                              DEV_TX_OFFLOAD_UDP_CKSUM |
1215                                              DEV_TX_OFFLOAD_TCP_CKSUM;
1216
1217         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1218                 .rx_thresh = {
1219                         .pthresh = DEFAULT_RX_PTHRESH,
1220                         .hthresh = DEFAULT_RX_HTHRESH,
1221                         .wthresh = DEFAULT_RX_WTHRESH,
1222                 },
1223                 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1224                 .rx_drop_en = 0,
1225         };
1226
1227         dev_info->default_txconf = (struct rte_eth_txconf) {
1228                 .tx_thresh = {
1229                         .pthresh = DEFAULT_TX_PTHRESH,
1230                         .hthresh = DEFAULT_TX_HTHRESH,
1231                         .wthresh = DEFAULT_TX_WTHRESH,
1232                 },
1233                 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1234                 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1235                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1236                              ETH_TXQ_FLAGS_NOOFFLOADS,
1237         };
1238
1239         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1240                                            ETH_RSS_NONFRAG_IPV4_TCP |
1241                                            ETH_RSS_NONFRAG_IPV4_UDP |
1242                                            ETH_RSS_IPV6 |
1243                                            ETH_RSS_NONFRAG_IPV6_TCP |
1244                                            ETH_RSS_NONFRAG_IPV6_UDP;
1245
1246         dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1247         dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1248
1249         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1250                                ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
1251                                ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
1252
1253         if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1254                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1255 }
1256
1257 static const uint32_t *
1258 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1259 {
1260         static const uint32_t ptypes[] = {
1261                 /* refers to nfp_net_set_hash() */
1262                 RTE_PTYPE_INNER_L3_IPV4,
1263                 RTE_PTYPE_INNER_L3_IPV6,
1264                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1265                 RTE_PTYPE_INNER_L4_MASK,
1266                 RTE_PTYPE_UNKNOWN
1267         };
1268
1269         if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1270                 return ptypes;
1271         return NULL;
1272 }
1273
1274 static uint32_t
1275 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1276 {
1277         struct nfp_net_rxq *rxq;
1278         struct nfp_net_rx_desc *rxds;
1279         uint32_t idx;
1280         uint32_t count;
1281
1282         rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1283
1284         idx = rxq->rd_p;
1285
1286         count = 0;
1287
1288         /*
1289          * Other PMDs are just checking the DD bit in intervals of 4
1290          * descriptors and counting all four if the first has the DD
1291          * bit on. Of course, this is not accurate but can be good for
1292          * performance. But ideally that should be done in descriptors
1293          * chunks belonging to the same cache line
1294          */
1295
1296         while (count < rxq->rx_count) {
1297                 rxds = &rxq->rxds[idx];
1298                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1299                         break;
1300
1301                 count++;
1302                 idx++;
1303
1304                 /* Wrapping? */
1305                 if ((idx) == rxq->rx_count)
1306                         idx = 0;
1307         }
1308
1309         return count;
1310 }
1311
1312 static int
1313 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1314 {
1315         struct rte_pci_device *pci_dev;
1316         struct nfp_net_hw *hw;
1317         int base = 0;
1318
1319         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1321
1322         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1323                 base = 1;
1324
1325         /* Make sure all updates are written before un-masking */
1326         rte_wmb();
1327         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1328                       NFP_NET_CFG_ICR_UNMASKED);
1329         return 0;
1330 }
1331
1332 static int
1333 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1334 {
1335         struct rte_pci_device *pci_dev;
1336         struct nfp_net_hw *hw;
1337         int base = 0;
1338
1339         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1341
1342         if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1343                 base = 1;
1344
1345         /* Make sure all updates are written before un-masking */
1346         rte_wmb();
1347         nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1348         return 0;
1349 }
1350
1351 static void
1352 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1353 {
1354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1355         struct rte_eth_link link;
1356
1357         memset(&link, 0, sizeof(link));
1358         nfp_net_dev_atomic_read_link_status(dev, &link);
1359         if (link.link_status)
1360                 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1361                         dev->data->port_id, link.link_speed,
1362                         link.link_duplex == ETH_LINK_FULL_DUPLEX
1363                         ? "full-duplex" : "half-duplex");
1364         else
1365                 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1366                         dev->data->port_id);
1367
1368         RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1369                 pci_dev->addr.domain, pci_dev->addr.bus,
1370                 pci_dev->addr.devid, pci_dev->addr.function);
1371 }
1372
1373 /* Interrupt configuration and handling */
1374
1375 /*
1376  * nfp_net_irq_unmask - Unmask an interrupt
1377  *
1378  * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1379  * clear the ICR for the entry.
1380  */
1381 static void
1382 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1383 {
1384         struct nfp_net_hw *hw;
1385         struct rte_pci_device *pci_dev;
1386
1387         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1388         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1389
1390         if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1391                 /* If MSI-X auto-masking is used, clear the entry */
1392                 rte_wmb();
1393                 rte_intr_enable(&pci_dev->intr_handle);
1394         } else {
1395                 /* Make sure all updates are written before un-masking */
1396                 rte_wmb();
1397                 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1398                               NFP_NET_CFG_ICR_UNMASKED);
1399         }
1400 }
1401
1402 static void
1403 nfp_net_dev_interrupt_handler(void *param)
1404 {
1405         int64_t timeout;
1406         struct rte_eth_link link;
1407         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1408
1409         PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1410
1411         /* get the link status */
1412         memset(&link, 0, sizeof(link));
1413         nfp_net_dev_atomic_read_link_status(dev, &link);
1414
1415         nfp_net_link_update(dev, 0);
1416
1417         /* likely to up */
1418         if (!link.link_status) {
1419                 /* handle it 1 sec later, wait it being stable */
1420                 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1421                 /* likely to down */
1422         } else {
1423                 /* handle it 4 sec later, wait it being stable */
1424                 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1425         }
1426
1427         if (rte_eal_alarm_set(timeout * 1000,
1428                               nfp_net_dev_interrupt_delayed_handler,
1429                               (void *)dev) < 0) {
1430                 RTE_LOG(ERR, PMD, "Error setting alarm");
1431                 /* Unmasking */
1432                 nfp_net_irq_unmask(dev);
1433         }
1434 }
1435
1436 /*
1437  * Interrupt handler which shall be registered for alarm callback for delayed
1438  * handling specific interrupt to wait for the stable nic state. As the NIC
1439  * interrupt state is not stable for nfp after link is just down, it needs
1440  * to wait 4 seconds to get the stable status.
1441  *
1442  * @param handle   Pointer to interrupt handle.
1443  * @param param    The address of parameter (struct rte_eth_dev *)
1444  *
1445  * @return  void
1446  */
1447 static void
1448 nfp_net_dev_interrupt_delayed_handler(void *param)
1449 {
1450         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1451
1452         nfp_net_link_update(dev, 0);
1453         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1454
1455         nfp_net_dev_link_status_print(dev);
1456
1457         /* Unmasking */
1458         nfp_net_irq_unmask(dev);
1459 }
1460
1461 static int
1462 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1463 {
1464         struct nfp_net_hw *hw;
1465
1466         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467
1468         /* check that mtu is within the allowed range */
1469         if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1470                 return -EINVAL;
1471
1472         /* mtu setting is forbidden if port is started */
1473         if (dev->data->dev_started) {
1474                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
1475                             dev->data->port_id);
1476                 return -EBUSY;
1477         }
1478
1479         /* switch to jumbo mode if needed */
1480         if ((uint32_t)mtu > ETHER_MAX_LEN)
1481                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1482         else
1483                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1484
1485         /* update max frame size */
1486         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1487
1488         /* writing to configuration space */
1489         nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1490
1491         hw->mtu = mtu;
1492
1493         return 0;
1494 }
1495
1496 static int
1497 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1498                        uint16_t queue_idx, uint16_t nb_desc,
1499                        unsigned int socket_id,
1500                        const struct rte_eth_rxconf *rx_conf,
1501                        struct rte_mempool *mp)
1502 {
1503         const struct rte_memzone *tz;
1504         struct nfp_net_rxq *rxq;
1505         struct nfp_net_hw *hw;
1506
1507         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508
1509         PMD_INIT_FUNC_TRACE();
1510
1511         /* Validating number of descriptors */
1512         if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1513             (nb_desc > NFP_NET_MAX_RX_DESC) ||
1514             (nb_desc < NFP_NET_MIN_RX_DESC)) {
1515                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1516                 return -EINVAL;
1517         }
1518
1519         /*
1520          * Free memory prior to re-allocation if needed. This is the case after
1521          * calling nfp_net_stop
1522          */
1523         if (dev->data->rx_queues[queue_idx]) {
1524                 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1525                 dev->data->rx_queues[queue_idx] = NULL;
1526         }
1527
1528         /* Allocating rx queue data structure */
1529         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1530                                  RTE_CACHE_LINE_SIZE, socket_id);
1531         if (rxq == NULL)
1532                 return -ENOMEM;
1533
1534         /* Hw queues mapping based on firmware confifguration */
1535         rxq->qidx = queue_idx;
1536         rxq->fl_qcidx = queue_idx * hw->stride_rx;
1537         rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1538         rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1539         rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1540
1541         /*
1542          * Tracking mbuf size for detecting a potential mbuf overflow due to
1543          * RX offset
1544          */
1545         rxq->mem_pool = mp;
1546         rxq->mbuf_size = rxq->mem_pool->elt_size;
1547         rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1548         hw->flbufsz = rxq->mbuf_size;
1549
1550         rxq->rx_count = nb_desc;
1551         rxq->port_id = dev->data->port_id;
1552         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1553         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1554                                   : ETHER_CRC_LEN);
1555         rxq->drop_en = rx_conf->rx_drop_en;
1556
1557         /*
1558          * Allocate RX ring hardware descriptors. A memzone large enough to
1559          * handle the maximum ring size is allocated in order to allow for
1560          * resizing in later calls to the queue setup function.
1561          */
1562         tz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1563                                    sizeof(struct nfp_net_rx_desc) *
1564                                    NFP_NET_MAX_RX_DESC, NFP_MEMZONE_ALIGN,
1565                                    socket_id);
1566
1567         if (tz == NULL) {
1568                 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1569                 nfp_net_rx_queue_release(rxq);
1570                 return -ENOMEM;
1571         }
1572
1573         /* Saving physical and virtual addresses for the RX ring */
1574         rxq->dma = (uint64_t)tz->iova;
1575         rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1576
1577         /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1578         rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1579                                          sizeof(*rxq->rxbufs) * nb_desc,
1580                                          RTE_CACHE_LINE_SIZE, socket_id);
1581         if (rxq->rxbufs == NULL) {
1582                 nfp_net_rx_queue_release(rxq);
1583                 return -ENOMEM;
1584         }
1585
1586         PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1587                    rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1588
1589         nfp_net_reset_rx_queue(rxq);
1590
1591         dev->data->rx_queues[queue_idx] = rxq;
1592         rxq->hw = hw;
1593
1594         /*
1595          * Telling the HW about the physical address of the RX ring and number
1596          * of descriptors in log2 format
1597          */
1598         nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1599         nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1600
1601         return 0;
1602 }
1603
1604 static int
1605 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1606 {
1607         struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1608         uint64_t dma_addr;
1609         unsigned i;
1610
1611         PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1612                    rxq->rx_count);
1613
1614         for (i = 0; i < rxq->rx_count; i++) {
1615                 struct nfp_net_rx_desc *rxd;
1616                 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1617
1618                 if (mbuf == NULL) {
1619                         RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1620                                 (unsigned)rxq->qidx);
1621                         return -ENOMEM;
1622                 }
1623
1624                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1625
1626                 rxd = &rxq->rxds[i];
1627                 rxd->fld.dd = 0;
1628                 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1629                 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1630                 rxe[i].mbuf = mbuf;
1631                 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1632         }
1633
1634         /* Make sure all writes are flushed before telling the hardware */
1635         rte_wmb();
1636
1637         /* Not advertising the whole ring as the firmware gets confused if so */
1638         PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1639                    rxq->rx_count - 1);
1640
1641         nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1642
1643         return 0;
1644 }
1645
1646 static int
1647 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1648                        uint16_t nb_desc, unsigned int socket_id,
1649                        const struct rte_eth_txconf *tx_conf)
1650 {
1651         const struct rte_memzone *tz;
1652         struct nfp_net_txq *txq;
1653         uint16_t tx_free_thresh;
1654         struct nfp_net_hw *hw;
1655
1656         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657
1658         PMD_INIT_FUNC_TRACE();
1659
1660         /* Validating number of descriptors */
1661         if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1662             (nb_desc > NFP_NET_MAX_TX_DESC) ||
1663             (nb_desc < NFP_NET_MIN_TX_DESC)) {
1664                 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1665                 return -EINVAL;
1666         }
1667
1668         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1669                                     tx_conf->tx_free_thresh :
1670                                     DEFAULT_TX_FREE_THRESH);
1671
1672         if (tx_free_thresh > (nb_desc)) {
1673                 RTE_LOG(ERR, PMD,
1674                         "tx_free_thresh must be less than the number of TX "
1675                         "descriptors. (tx_free_thresh=%u port=%d "
1676                         "queue=%d)\n", (unsigned int)tx_free_thresh,
1677                         dev->data->port_id, (int)queue_idx);
1678                 return -(EINVAL);
1679         }
1680
1681         /*
1682          * Free memory prior to re-allocation if needed. This is the case after
1683          * calling nfp_net_stop
1684          */
1685         if (dev->data->tx_queues[queue_idx]) {
1686                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1687                            queue_idx);
1688                 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1689                 dev->data->tx_queues[queue_idx] = NULL;
1690         }
1691
1692         /* Allocating tx queue data structure */
1693         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1694                                  RTE_CACHE_LINE_SIZE, socket_id);
1695         if (txq == NULL) {
1696                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1697                 return -ENOMEM;
1698         }
1699
1700         /*
1701          * Allocate TX ring hardware descriptors. A memzone large enough to
1702          * handle the maximum ring size is allocated in order to allow for
1703          * resizing in later calls to the queue setup function.
1704          */
1705         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1706                                    sizeof(struct nfp_net_tx_desc) *
1707                                    NFP_NET_MAX_TX_DESC, NFP_MEMZONE_ALIGN,
1708                                    socket_id);
1709         if (tz == NULL) {
1710                 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1711                 nfp_net_tx_queue_release(txq);
1712                 return -ENOMEM;
1713         }
1714
1715         txq->tx_count = nb_desc;
1716         txq->tx_free_thresh = tx_free_thresh;
1717         txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1718         txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1719         txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1720
1721         /* queue mapping based on firmware configuration */
1722         txq->qidx = queue_idx;
1723         txq->tx_qcidx = queue_idx * hw->stride_tx;
1724         txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1725
1726         txq->port_id = dev->data->port_id;
1727         txq->txq_flags = tx_conf->txq_flags;
1728
1729         /* Saving physical and virtual addresses for the TX ring */
1730         txq->dma = (uint64_t)tz->iova;
1731         txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1732
1733         /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1734         txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1735                                          sizeof(*txq->txbufs) * nb_desc,
1736                                          RTE_CACHE_LINE_SIZE, socket_id);
1737         if (txq->txbufs == NULL) {
1738                 nfp_net_tx_queue_release(txq);
1739                 return -ENOMEM;
1740         }
1741         PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1742                    txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1743
1744         nfp_net_reset_tx_queue(txq);
1745
1746         dev->data->tx_queues[queue_idx] = txq;
1747         txq->hw = hw;
1748
1749         /*
1750          * Telling the HW about the physical address of the TX ring and number
1751          * of descriptors in log2 format
1752          */
1753         nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1754         nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), rte_log2_u32(nb_desc));
1755
1756         return 0;
1757 }
1758
1759 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1760 static inline void
1761 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1762                struct rte_mbuf *mb)
1763 {
1764         uint64_t ol_flags;
1765         struct nfp_net_hw *hw = txq->hw;
1766
1767         if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1768                 goto clean_txd;
1769
1770         ol_flags = mb->ol_flags;
1771
1772         if (!(ol_flags & PKT_TX_TCP_SEG))
1773                 goto clean_txd;
1774
1775         txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1776         txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1777         txd->flags = PCIE_DESC_TX_LSO;
1778         return;
1779
1780 clean_txd:
1781         txd->flags = 0;
1782         txd->l4_offset = 0;
1783         txd->lso = 0;
1784 }
1785
1786 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1787 static inline void
1788 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1789                  struct rte_mbuf *mb)
1790 {
1791         uint64_t ol_flags;
1792         struct nfp_net_hw *hw = txq->hw;
1793
1794         if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1795                 return;
1796
1797         ol_flags = mb->ol_flags;
1798
1799         /* IPv6 does not need checksum */
1800         if (ol_flags & PKT_TX_IP_CKSUM)
1801                 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1802
1803         switch (ol_flags & PKT_TX_L4_MASK) {
1804         case PKT_TX_UDP_CKSUM:
1805                 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1806                 break;
1807         case PKT_TX_TCP_CKSUM:
1808                 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1809                 break;
1810         }
1811
1812         if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1813                 txd->flags |= PCIE_DESC_TX_CSUM;
1814 }
1815
1816 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1817 static inline void
1818 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1819                  struct rte_mbuf *mb)
1820 {
1821         struct nfp_net_hw *hw = rxq->hw;
1822
1823         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1824                 return;
1825
1826         /* If IPv4 and IP checksum error, fail */
1827         if (unlikely((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1828             !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK)))
1829                 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1830         else
1831                 mb->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1832
1833         /* If neither UDP nor TCP return */
1834         if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1835             !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1836                 return;
1837
1838         if (likely(rxd->rxd.flags & PCIE_DESC_RX_L4_CSUM_OK))
1839                 mb->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1840         else
1841                 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1842 }
1843
1844 #define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1845 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1846
1847 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1848
1849 /*
1850  * nfp_net_set_hash - Set mbuf hash data
1851  *
1852  * The RSS hash and hash-type are pre-pended to the packet data.
1853  * Extract and decode it and set the mbuf fields.
1854  */
1855 static inline void
1856 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1857                  struct rte_mbuf *mbuf)
1858 {
1859         struct nfp_net_hw *hw = rxq->hw;
1860         uint8_t *meta_offset;
1861         uint32_t meta_info;
1862         uint32_t hash = 0;
1863         uint32_t hash_type = 0;
1864
1865         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1866                 return;
1867
1868         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) <= 3) {
1869                 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1870                         return;
1871
1872                 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1873                 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1874
1875         } else if (NFP_DESC_META_LEN(rxd)) {
1876                 /*
1877                  * new metadata api:
1878                  * <----  32 bit  ----->
1879                  * m    field type word
1880                  * e     data field #2
1881                  * t     data field #1
1882                  * a     data field #0
1883                  * ====================
1884                  *    packet data
1885                  *
1886                  * Field type word contains up to 8 4bit field types
1887                  * A 4bit field type refers to a data field word
1888                  * A data field word can have several 4bit field types
1889                  */
1890                 meta_offset = rte_pktmbuf_mtod(mbuf, uint8_t *);
1891                 meta_offset -= NFP_DESC_META_LEN(rxd);
1892                 meta_info = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1893                 meta_offset += 4;
1894                 /* NFP PMD just supports metadata for hashing */
1895                 switch (meta_info & NFP_NET_META_FIELD_MASK) {
1896                 case NFP_NET_META_HASH:
1897                         /* next field type is about the hash type */
1898                         meta_info >>= NFP_NET_META_FIELD_SIZE;
1899                         /* hash value is in the data field */
1900                         hash = rte_be_to_cpu_32(*(uint32_t *)meta_offset);
1901                         hash_type = meta_info & NFP_NET_META_FIELD_MASK;
1902                         break;
1903                 default:
1904                         /* Unsupported metadata can be a performance issue */
1905                         return;
1906                 }
1907         } else {
1908                 return;
1909         }
1910
1911         mbuf->hash.rss = hash;
1912         mbuf->ol_flags |= PKT_RX_RSS_HASH;
1913
1914         switch (hash_type) {
1915         case NFP_NET_RSS_IPV4:
1916                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1917                 break;
1918         case NFP_NET_RSS_IPV6:
1919                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1920                 break;
1921         case NFP_NET_RSS_IPV6_EX:
1922                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1923                 break;
1924         case NFP_NET_RSS_IPV4_TCP:
1925                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1926                 break;
1927         case NFP_NET_RSS_IPV6_TCP:
1928                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1929                 break;
1930         case NFP_NET_RSS_IPV4_UDP:
1931                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1932                 break;
1933         case NFP_NET_RSS_IPV6_UDP:
1934                 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1935                 break;
1936         default:
1937                 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1938         }
1939 }
1940
1941 static inline void
1942 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1943 {
1944         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1945 }
1946
1947 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1948
1949 /*
1950  * RX path design:
1951  *
1952  * There are some decissions to take:
1953  * 1) How to check DD RX descriptors bit
1954  * 2) How and when to allocate new mbufs
1955  *
1956  * Current implementation checks just one single DD bit each loop. As each
1957  * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1958  * a single cache line instead. Tests with this change have not shown any
1959  * performance improvement but it requires further investigation. For example,
1960  * depending on which descriptor is next, the number of descriptors could be
1961  * less than 8 for just checking those in the same cache line. This implies
1962  * extra work which could be counterproductive by itself. Indeed, last firmware
1963  * changes are just doing this: writing several descriptors with the DD bit
1964  * for saving PCIe bandwidth and DMA operations from the NFP.
1965  *
1966  * Mbuf allocation is done when a new packet is received. Then the descriptor
1967  * is automatically linked with the new mbuf and the old one is given to the
1968  * user. The main drawback with this design is mbuf allocation is heavier than
1969  * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1970  * cache point of view it does not seem allocating the mbuf early on as we are
1971  * doing now have any benefit at all. Again, tests with this change have not
1972  * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1973  * so looking at the implications of this type of allocation should be studied
1974  * deeply
1975  */
1976
1977 static uint16_t
1978 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1979 {
1980         struct nfp_net_rxq *rxq;
1981         struct nfp_net_rx_desc *rxds;
1982         struct nfp_net_rx_buff *rxb;
1983         struct nfp_net_hw *hw;
1984         struct rte_mbuf *mb;
1985         struct rte_mbuf *new_mb;
1986         uint16_t nb_hold;
1987         uint64_t dma_addr;
1988         int avail;
1989
1990         rxq = rx_queue;
1991         if (unlikely(rxq == NULL)) {
1992                 /*
1993                  * DPDK just checks the queue is lower than max queues
1994                  * enabled. But the queue needs to be configured
1995                  */
1996                 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1997                 return -EINVAL;
1998         }
1999
2000         hw = rxq->hw;
2001         avail = 0;
2002         nb_hold = 0;
2003
2004         while (avail < nb_pkts) {
2005                 rxb = &rxq->rxbufs[rxq->rd_p];
2006                 if (unlikely(rxb == NULL)) {
2007                         RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
2008                         break;
2009                 }
2010
2011                 rxds = &rxq->rxds[rxq->rd_p];
2012                 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
2013                         break;
2014
2015                 /*
2016                  * Memory barrier to ensure that we won't do other
2017                  * reads before the DD bit.
2018                  */
2019                 rte_rmb();
2020
2021                 /*
2022                  * We got a packet. Let's alloc a new mbuff for refilling the
2023                  * free descriptor ring as soon as possible
2024                  */
2025                 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
2026                 if (unlikely(new_mb == NULL)) {
2027                         RTE_LOG_DP(DEBUG, PMD,
2028                         "RX mbuf alloc failed port_id=%u queue_id=%u\n",
2029                                 rxq->port_id, (unsigned int)rxq->qidx);
2030                         nfp_net_mbuf_alloc_failed(rxq);
2031                         break;
2032                 }
2033
2034                 nb_hold++;
2035
2036                 /*
2037                  * Grab the mbuff and refill the descriptor with the
2038                  * previously allocated mbuff
2039                  */
2040                 mb = rxb->mbuf;
2041                 rxb->mbuf = new_mb;
2042
2043                 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
2044                            rxds->rxd.data_len, rxq->mbuf_size);
2045
2046                 /* Size of this segment */
2047                 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2048                 /* Size of the whole packet. We just support 1 segment */
2049                 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
2050
2051                 if (unlikely((mb->data_len + hw->rx_offset) >
2052                              rxq->mbuf_size)) {
2053                         /*
2054                          * This should not happen and the user has the
2055                          * responsibility of avoiding it. But we have
2056                          * to give some info about the error
2057                          */
2058                         RTE_LOG_DP(ERR, PMD,
2059                                 "mbuf overflow likely due to the RX offset.\n"
2060                                 "\t\tYour mbuf size should have extra space for"
2061                                 " RX offset=%u bytes.\n"
2062                                 "\t\tCurrently you just have %u bytes available"
2063                                 " but the received packet is %u bytes long",
2064                                 hw->rx_offset,
2065                                 rxq->mbuf_size - hw->rx_offset,
2066                                 mb->data_len);
2067                         return -EINVAL;
2068                 }
2069
2070                 /* Filling the received mbuff with packet info */
2071                 if (hw->rx_offset)
2072                         mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
2073                 else
2074                         mb->data_off = RTE_PKTMBUF_HEADROOM +
2075                                        NFP_DESC_META_LEN(rxds);
2076
2077                 /* No scatter mode supported */
2078                 mb->nb_segs = 1;
2079                 mb->next = NULL;
2080
2081                 mb->port = rxq->port_id;
2082
2083                 /* Checking the RSS flag */
2084                 nfp_net_set_hash(rxq, rxds, mb);
2085
2086                 /* Checking the checksum flag */
2087                 nfp_net_rx_cksum(rxq, rxds, mb);
2088
2089                 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
2090                     (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
2091                         mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
2092                         mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2093                 }
2094
2095                 /* Adding the mbuff to the mbuff array passed by the app */
2096                 rx_pkts[avail++] = mb;
2097
2098                 /* Now resetting and updating the descriptor */
2099                 rxds->vals[0] = 0;
2100                 rxds->vals[1] = 0;
2101                 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
2102                 rxds->fld.dd = 0;
2103                 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
2104                 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
2105
2106                 rxq->rd_p++;
2107                 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
2108                         rxq->rd_p = 0;
2109         }
2110
2111         if (nb_hold == 0)
2112                 return nb_hold;
2113
2114         PMD_RX_LOG(DEBUG, "RX  port_id=%u queue_id=%u, %d packets received\n",
2115                    rxq->port_id, (unsigned int)rxq->qidx, nb_hold);
2116
2117         nb_hold += rxq->nb_rx_hold;
2118
2119         /*
2120          * FL descriptors needs to be written before incrementing the
2121          * FL queue WR pointer
2122          */
2123         rte_wmb();
2124         if (nb_hold > rxq->rx_free_thresh) {
2125                 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
2126                            rxq->port_id, (unsigned int)rxq->qidx,
2127                            (unsigned)nb_hold, (unsigned)avail);
2128                 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
2129                 nb_hold = 0;
2130         }
2131         rxq->nb_rx_hold = nb_hold;
2132
2133         return avail;
2134 }
2135
2136 /*
2137  * nfp_net_tx_free_bufs - Check for descriptors with a complete
2138  * status
2139  * @txq: TX queue to work with
2140  * Returns number of descriptors freed
2141  */
2142 int
2143 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
2144 {
2145         uint32_t qcp_rd_p;
2146         int todo;
2147
2148         PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
2149                    " status\n", txq->qidx);
2150
2151         /* Work out how many packets have been sent */
2152         qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
2153
2154         if (qcp_rd_p == txq->rd_p) {
2155                 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
2156                            "packets (%u, %u)\n", txq->qidx,
2157                            qcp_rd_p, txq->rd_p);
2158                 return 0;
2159         }
2160
2161         if (qcp_rd_p > txq->rd_p)
2162                 todo = qcp_rd_p - txq->rd_p;
2163         else
2164                 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2165
2166         PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2167                    qcp_rd_p, txq->rd_p, txq->rd_p);
2168
2169         if (todo == 0)
2170                 return todo;
2171
2172         txq->rd_p += todo;
2173         if (unlikely(txq->rd_p >= txq->tx_count))
2174                 txq->rd_p -= txq->tx_count;
2175
2176         return todo;
2177 }
2178
2179 /* Leaving always free descriptors for avoiding wrapping confusion */
2180 static inline
2181 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2182 {
2183         if (txq->wr_p >= txq->rd_p)
2184                 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2185         else
2186                 return txq->rd_p - txq->wr_p - 8;
2187 }
2188
2189 /*
2190  * nfp_net_txq_full - Check if the TX queue free descriptors
2191  * is below tx_free_threshold
2192  *
2193  * @txq: TX queue to check
2194  *
2195  * This function uses the host copy* of read/write pointers
2196  */
2197 static inline
2198 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2199 {
2200         return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2201 }
2202
2203 static uint16_t
2204 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2205 {
2206         struct nfp_net_txq *txq;
2207         struct nfp_net_hw *hw;
2208         struct nfp_net_tx_desc *txds, txd;
2209         struct rte_mbuf *pkt;
2210         uint64_t dma_addr;
2211         int pkt_size, dma_size;
2212         uint16_t free_descs, issued_descs;
2213         struct rte_mbuf **lmbuf;
2214         int i;
2215
2216         txq = tx_queue;
2217         hw = txq->hw;
2218         txds = &txq->txds[txq->wr_p];
2219
2220         PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2221                    txq->qidx, txq->wr_p, nb_pkts);
2222
2223         if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2224                 nfp_net_tx_free_bufs(txq);
2225
2226         free_descs = (uint16_t)nfp_free_tx_desc(txq);
2227         if (unlikely(free_descs == 0))
2228                 return 0;
2229
2230         pkt = *tx_pkts;
2231
2232         i = 0;
2233         issued_descs = 0;
2234         PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2235                    txq->qidx, nb_pkts);
2236         /* Sending packets */
2237         while ((i < nb_pkts) && free_descs) {
2238                 /* Grabbing the mbuf linked to the current descriptor */
2239                 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2240                 /* Warming the cache for releasing the mbuf later on */
2241                 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2242
2243                 pkt = *(tx_pkts + i);
2244
2245                 if (unlikely((pkt->nb_segs > 1) &&
2246                              !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2247                         PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2248                         rte_panic("Multisegment packet unsupported\n");
2249                 }
2250
2251                 /* Checking if we have enough descriptors */
2252                 if (unlikely(pkt->nb_segs > free_descs))
2253                         goto xmit_end;
2254
2255                 /*
2256                  * Checksum and VLAN flags just in the first descriptor for a
2257                  * multisegment packet, but TSO info needs to be in all of them.
2258                  */
2259                 txd.data_len = pkt->pkt_len;
2260                 nfp_net_tx_tso(txq, &txd, pkt);
2261                 nfp_net_tx_cksum(txq, &txd, pkt);
2262
2263                 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2264                     (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2265                         txd.flags |= PCIE_DESC_TX_VLAN;
2266                         txd.vlan = pkt->vlan_tci;
2267                 }
2268
2269                 /*
2270                  * mbuf data_len is the data in one segment and pkt_len data
2271                  * in the whole packet. When the packet is just one segment,
2272                  * then data_len = pkt_len
2273                  */
2274                 pkt_size = pkt->pkt_len;
2275
2276                 while (pkt) {
2277                         /* Copying TSO, VLAN and cksum info */
2278                         *txds = txd;
2279
2280                         /* Releasing mbuf used by this descriptor previously*/
2281                         if (*lmbuf)
2282                                 rte_pktmbuf_free_seg(*lmbuf);
2283
2284                         /*
2285                          * Linking mbuf with descriptor for being released
2286                          * next time descriptor is used
2287                          */
2288                         *lmbuf = pkt;
2289
2290                         dma_size = pkt->data_len;
2291                         dma_addr = rte_mbuf_data_iova(pkt);
2292                         PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2293                                    "%" PRIx64 "\n", dma_addr);
2294
2295                         /* Filling descriptors fields */
2296                         txds->dma_len = dma_size;
2297                         txds->data_len = txd.data_len;
2298                         txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2299                         txds->dma_addr_lo = (dma_addr & 0xffffffff);
2300                         ASSERT(free_descs > 0);
2301                         free_descs--;
2302
2303                         txq->wr_p++;
2304                         if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2305                                 txq->wr_p = 0;
2306
2307                         pkt_size -= dma_size;
2308
2309                         /*
2310                          * Making the EOP, packets with just one segment
2311                          * the priority
2312                          */
2313                         if (likely(!pkt_size))
2314                                 txds->offset_eop = PCIE_DESC_TX_EOP;
2315                         else
2316                                 txds->offset_eop = 0;
2317
2318                         pkt = pkt->next;
2319                         /* Referencing next free TX descriptor */
2320                         txds = &txq->txds[txq->wr_p];
2321                         lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2322                         issued_descs++;
2323                 }
2324                 i++;
2325         }
2326
2327 xmit_end:
2328         /* Increment write pointers. Force memory write before we let HW know */
2329         rte_wmb();
2330         nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2331
2332         return i;
2333 }
2334
2335 static int
2336 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2337 {
2338         uint32_t new_ctrl, update;
2339         struct nfp_net_hw *hw;
2340         int ret;
2341
2342         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         new_ctrl = 0;
2344
2345         if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2346             (mask & ETH_VLAN_EXTEND_OFFLOAD))
2347                 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2348                         " ETH_VLAN_EXTEND_OFFLOAD");
2349
2350         /* Enable vlan strip if it is not configured yet */
2351         if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2352             !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2353                 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2354
2355         /* Disable vlan strip just if it is configured */
2356         if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2357             (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2358                 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2359
2360         if (new_ctrl == 0)
2361                 return 0;
2362
2363         update = NFP_NET_CFG_UPDATE_GEN;
2364
2365         ret = nfp_net_reconfig(hw, new_ctrl, update);
2366         if (!ret)
2367                 hw->ctrl = new_ctrl;
2368
2369         return ret;
2370 }
2371
2372 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2373 static int
2374 nfp_net_reta_update(struct rte_eth_dev *dev,
2375                     struct rte_eth_rss_reta_entry64 *reta_conf,
2376                     uint16_t reta_size)
2377 {
2378         uint32_t reta, mask;
2379         int i, j;
2380         int idx, shift;
2381         uint32_t update;
2382         struct nfp_net_hw *hw =
2383                 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384
2385         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2386                 return -EINVAL;
2387
2388         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2389                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2390                         "(%d) doesn't match the number hardware can supported "
2391                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2392                 return -EINVAL;
2393         }
2394
2395         /*
2396          * Update Redirection Table. There are 128 8bit-entries which can be
2397          * manage as 32 32bit-entries
2398          */
2399         for (i = 0; i < reta_size; i += 4) {
2400                 /* Handling 4 RSS entries per loop */
2401                 idx = i / RTE_RETA_GROUP_SIZE;
2402                 shift = i % RTE_RETA_GROUP_SIZE;
2403                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2404
2405                 if (!mask)
2406                         continue;
2407
2408                 reta = 0;
2409                 /* If all 4 entries were set, don't need read RETA register */
2410                 if (mask != 0xF)
2411                         reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2412
2413                 for (j = 0; j < 4; j++) {
2414                         if (!(mask & (0x1 << j)))
2415                                 continue;
2416                         if (mask != 0xF)
2417                                 /* Clearing the entry bits */
2418                                 reta &= ~(0xFF << (8 * j));
2419                         reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2420                 }
2421                 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) + shift,
2422                               reta);
2423         }
2424
2425         update = NFP_NET_CFG_UPDATE_RSS;
2426
2427         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2428                 return -EIO;
2429
2430         return 0;
2431 }
2432
2433  /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2434 static int
2435 nfp_net_reta_query(struct rte_eth_dev *dev,
2436                    struct rte_eth_rss_reta_entry64 *reta_conf,
2437                    uint16_t reta_size)
2438 {
2439         uint8_t i, j, mask;
2440         int idx, shift;
2441         uint32_t reta;
2442         struct nfp_net_hw *hw;
2443
2444         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445
2446         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2447                 return -EINVAL;
2448
2449         if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2450                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2451                         "(%d) doesn't match the number hardware can supported "
2452                         "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2453                 return -EINVAL;
2454         }
2455
2456         /*
2457          * Reading Redirection Table. There are 128 8bit-entries which can be
2458          * manage as 32 32bit-entries
2459          */
2460         for (i = 0; i < reta_size; i += 4) {
2461                 /* Handling 4 RSS entries per loop */
2462                 idx = i / RTE_RETA_GROUP_SIZE;
2463                 shift = i % RTE_RETA_GROUP_SIZE;
2464                 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2465
2466                 if (!mask)
2467                         continue;
2468
2469                 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + (idx * 64) +
2470                                     shift);
2471                 for (j = 0; j < 4; j++) {
2472                         if (!(mask & (0x1 << j)))
2473                                 continue;
2474                         reta_conf->reta[shift + j] =
2475                                 (uint8_t)((reta >> (8 * j)) & 0xF);
2476                 }
2477         }
2478         return 0;
2479 }
2480
2481 static int
2482 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2483                         struct rte_eth_rss_conf *rss_conf)
2484 {
2485         uint32_t update;
2486         uint32_t cfg_rss_ctrl = 0;
2487         uint8_t key;
2488         uint64_t rss_hf;
2489         int i;
2490         struct nfp_net_hw *hw;
2491
2492         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493
2494         rss_hf = rss_conf->rss_hf;
2495
2496         /* Checking if RSS is enabled */
2497         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2498                 if (rss_hf != 0) { /* Enable RSS? */
2499                         RTE_LOG(ERR, PMD, "RSS unsupported\n");
2500                         return -EINVAL;
2501                 }
2502                 return 0; /* Nothing to do */
2503         }
2504
2505         if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2506                 RTE_LOG(ERR, PMD, "hash key too long\n");
2507                 return -EINVAL;
2508         }
2509
2510         if (rss_hf & ETH_RSS_IPV4)
2511                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4;
2512
2513         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2514                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_TCP;
2515
2516         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2517                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4_UDP;
2518
2519         if (rss_hf & ETH_RSS_IPV6)
2520                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6;
2521
2522         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2523                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_TCP;
2524
2525         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2526                 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6_UDP;
2527
2528         cfg_rss_ctrl |= NFP_NET_CFG_RSS_MASK;
2529         cfg_rss_ctrl |= NFP_NET_CFG_RSS_TOEPLITZ;
2530
2531         /* configuring where to apply the RSS hash */
2532         nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2533
2534         /* Writing the key byte a byte */
2535         for (i = 0; i < rss_conf->rss_key_len; i++) {
2536                 memcpy(&key, &rss_conf->rss_key[i], 1);
2537                 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2538         }
2539
2540         /* Writing the key size */
2541         nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2542
2543         update = NFP_NET_CFG_UPDATE_RSS;
2544
2545         if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2546                 return -EIO;
2547
2548         return 0;
2549 }
2550
2551 static int
2552 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2553                           struct rte_eth_rss_conf *rss_conf)
2554 {
2555         uint64_t rss_hf;
2556         uint32_t cfg_rss_ctrl;
2557         uint8_t key;
2558         int i;
2559         struct nfp_net_hw *hw;
2560
2561         hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562
2563         if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2564                 return -EINVAL;
2565
2566         rss_hf = rss_conf->rss_hf;
2567         cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2568
2569         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2570                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2571
2572         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2573                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2574
2575         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2576                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2577
2578         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2579                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2580
2581         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2582                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2583
2584         if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2585                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2586
2587         /* Reading the key size */
2588         rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2589
2590         /* Reading the key byte a byte */
2591         for (i = 0; i < rss_conf->rss_key_len; i++) {
2592                 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2593                 memcpy(&rss_conf->rss_key[i], &key, 1);
2594         }
2595
2596         return 0;
2597 }
2598
2599 /* Initialise and register driver with DPDK Application */
2600 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2601         .dev_configure          = nfp_net_configure,
2602         .dev_start              = nfp_net_start,
2603         .dev_stop               = nfp_net_stop,
2604         .dev_close              = nfp_net_close,
2605         .promiscuous_enable     = nfp_net_promisc_enable,
2606         .promiscuous_disable    = nfp_net_promisc_disable,
2607         .link_update            = nfp_net_link_update,
2608         .stats_get              = nfp_net_stats_get,
2609         .stats_reset            = nfp_net_stats_reset,
2610         .dev_infos_get          = nfp_net_infos_get,
2611         .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2612         .mtu_set                = nfp_net_dev_mtu_set,
2613         .vlan_offload_set       = nfp_net_vlan_offload_set,
2614         .reta_update            = nfp_net_reta_update,
2615         .reta_query             = nfp_net_reta_query,
2616         .rss_hash_update        = nfp_net_rss_hash_update,
2617         .rss_hash_conf_get      = nfp_net_rss_hash_conf_get,
2618         .rx_queue_setup         = nfp_net_rx_queue_setup,
2619         .rx_queue_release       = nfp_net_rx_queue_release,
2620         .rx_queue_count         = nfp_net_rx_queue_count,
2621         .tx_queue_setup         = nfp_net_tx_queue_setup,
2622         .tx_queue_release       = nfp_net_tx_queue_release,
2623         .rx_queue_intr_enable   = nfp_rx_queue_intr_enable,
2624         .rx_queue_intr_disable  = nfp_rx_queue_intr_disable,
2625 };
2626
2627 /*
2628  * All eth_dev created got its private data, but before nfp_net_init, that
2629  * private data is referencing private data for all the PF ports. This is due
2630  * to how the vNIC bars are mapped based on first port, so all ports need info
2631  * about port 0 private data. Inside nfp_net_init the private data pointer is
2632  * changed to the right address for each port once the bars have been mapped.
2633  *
2634  * This functions helps to find out which port and therefore which offset
2635  * inside the private data array to use.
2636  */
2637 static int
2638 get_pf_port_number(char *name)
2639 {
2640         char *pf_str = name;
2641         int size = 0;
2642
2643         while ((*pf_str != '_') && (*pf_str != '\0') && (size++ < 30))
2644                 pf_str++;
2645
2646         if (size == 30)
2647                 /*
2648                  * This should not happen at all and it would mean major
2649                  * implementation fault.
2650                  */
2651                 rte_panic("nfp_net: problem with pf device name\n");
2652
2653         /* Expecting _portX with X within [0,7] */
2654         pf_str += 5;
2655
2656         return (int)strtol(pf_str, NULL, 10);
2657 }
2658
2659 static int
2660 nfp_net_init(struct rte_eth_dev *eth_dev)
2661 {
2662         struct rte_pci_device *pci_dev;
2663         struct nfp_net_hw *hw, *hwport0;
2664
2665         uint64_t tx_bar_off = 0, rx_bar_off = 0;
2666         uint32_t start_q;
2667         int stride = 4;
2668
2669         nspu_desc_t *nspu_desc = NULL;
2670         uint64_t bar_offset;
2671         int port = 0;
2672
2673         PMD_INIT_FUNC_TRACE();
2674
2675         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2676
2677         /* NFP can not handle DMA addresses requiring more than 40 bits */
2678         if (rte_eal_check_dma_mask(40) < 0) {
2679                 RTE_LOG(INFO, PMD, "device %s can not be used:",
2680                                    pci_dev->device.name);
2681                 RTE_LOG(INFO, PMD, "\trestricted dma mask to 40 bits!\n");
2682                 return -ENODEV;
2683         };
2684
2685         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
2686             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
2687                 port = get_pf_port_number(eth_dev->data->name);
2688                 if (port < 0 || port > 7) {
2689                         RTE_LOG(ERR, PMD, "Port value is wrong\n");
2690                         return -ENODEV;
2691                 }
2692
2693                 PMD_INIT_LOG(DEBUG, "Working with PF port value %d\n", port);
2694
2695                 /* This points to port 0 private data */
2696                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2697
2698                 /* This points to the specific port private data */
2699                 hw = &hwport0[port];
2700                 hw->pf_port_idx = port;
2701         } else {
2702                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2703                 hwport0 = 0;
2704         }
2705
2706         eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2707         eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2708         eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2709
2710         /* For secondary processes, the primary has done all the work */
2711         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2712                 return 0;
2713
2714         rte_eth_copy_pci_info(eth_dev, pci_dev);
2715
2716         hw->device_id = pci_dev->id.device_id;
2717         hw->vendor_id = pci_dev->id.vendor_id;
2718         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2719         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2720
2721         PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2722                      pci_dev->id.vendor_id, pci_dev->id.device_id,
2723                      pci_dev->addr.domain, pci_dev->addr.bus,
2724                      pci_dev->addr.devid, pci_dev->addr.function);
2725
2726         hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2727         if (hw->ctrl_bar == NULL) {
2728                 RTE_LOG(ERR, PMD,
2729                         "hw->ctrl_bar is NULL. BAR0 not configured\n");
2730                 return -ENODEV;
2731         }
2732
2733         if (hw->is_pf && port == 0) {
2734                 nspu_desc = hw->nspu_desc;
2735
2736                 if (nfp_nsp_map_ctrl_bar(nspu_desc, &bar_offset) != 0) {
2737                         /*
2738                          * A firmware should be there after PF probe so this
2739                          * should not happen.
2740                          */
2741                         RTE_LOG(ERR, PMD, "PF BAR symbol resolution failed\n");
2742                         return -ENODEV;
2743                 }
2744
2745                 /* vNIC PF control BAR is a subset of PF PCI device BAR */
2746                 hw->ctrl_bar += bar_offset;
2747                 PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2748         }
2749
2750         if (port > 0) {
2751                 if (!hwport0->ctrl_bar)
2752                         return -ENODEV;
2753
2754                 /* address based on port0 offset */
2755                 hw->ctrl_bar = hwport0->ctrl_bar +
2756                                (port * NFP_PF_CSR_SLICE_SIZE);
2757         }
2758
2759         PMD_INIT_LOG(DEBUG, "ctrl bar: %p\n", hw->ctrl_bar);
2760
2761         hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2762         hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2763
2764         /* Work out where in the BAR the queues start. */
2765         switch (pci_dev->id.device_id) {
2766         case PCI_DEVICE_ID_NFP4000_PF_NIC:
2767         case PCI_DEVICE_ID_NFP6000_PF_NIC:
2768         case PCI_DEVICE_ID_NFP6000_VF_NIC:
2769                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2770                 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2771                 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2772                 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2773                 break;
2774         default:
2775                 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2776                 return -ENODEV;
2777         }
2778
2779         PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%" PRIx64 "\n", tx_bar_off);
2780         PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%" PRIx64 "\n", rx_bar_off);
2781
2782         if (hw->is_pf && port == 0) {
2783                 /* configure access to tx/rx vNIC BARs */
2784                 nfp_nsp_map_queues_bar(nspu_desc, &bar_offset);
2785                 PMD_INIT_LOG(DEBUG, "tx/rx bar_offset: %" PRIx64 "\n",
2786                                     bar_offset);
2787                 hwport0->hw_queues = (uint8_t *)pci_dev->mem_resource[0].addr;
2788
2789                 /* vNIC PF tx/rx BARs are a subset of PF PCI device */
2790                 hwport0->hw_queues += bar_offset;
2791
2792                 /* Lets seize the chance to read eth table from hw */
2793                 if (nfp_nsp_eth_read_table(nspu_desc, &hw->eth_table))
2794                         return -ENODEV;
2795         }
2796
2797         if (hw->is_pf) {
2798                 hw->tx_bar = hwport0->hw_queues + tx_bar_off;
2799                 hw->rx_bar = hwport0->hw_queues + rx_bar_off;
2800                 eth_dev->data->dev_private = hw;
2801         } else {
2802                 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2803                              tx_bar_off;
2804                 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr +
2805                              rx_bar_off;
2806         }
2807
2808         PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2809                      hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2810
2811         nfp_net_cfg_queue_setup(hw);
2812
2813         /* Get some of the read-only fields from the config BAR */
2814         hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2815         hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2816         hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2817         hw->mtu = ETHER_MTU;
2818
2819         if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2820                 hw->rx_offset = NFP_NET_RX_OFFSET;
2821         else
2822                 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2823
2824         PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2825                      hw->ver, hw->max_mtu);
2826         PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s%s%s", hw->cap,
2827                      hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2828                      hw->cap & NFP_NET_CFG_CTRL_L2BC    ? "L2BCFILT " : "",
2829                      hw->cap & NFP_NET_CFG_CTRL_L2MC    ? "L2MCFILT " : "",
2830                      hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? "RXCSUM "  : "",
2831                      hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? "TXCSUM "  : "",
2832                      hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? "RXVLAN "  : "",
2833                      hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? "TXVLAN "  : "",
2834                      hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2835                      hw->cap & NFP_NET_CFG_CTRL_GATHER  ? "GATHER "  : "",
2836                      hw->cap & NFP_NET_CFG_CTRL_LSO     ? "TSO "     : "",
2837                      hw->cap & NFP_NET_CFG_CTRL_RSS     ? "RSS "     : "");
2838
2839         hw->ctrl = 0;
2840
2841         hw->stride_rx = stride;
2842         hw->stride_tx = stride;
2843
2844         PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2845                      hw->max_rx_queues, hw->max_tx_queues);
2846
2847         /* Initializing spinlock for reconfigs */
2848         rte_spinlock_init(&hw->reconfig_lock);
2849
2850         /* Allocating memory for mac addr */
2851         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2852         if (eth_dev->data->mac_addrs == NULL) {
2853                 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2854                 return -ENOMEM;
2855         }
2856
2857         if (hw->is_pf) {
2858                 nfp_net_pf_read_mac(hwport0, port);
2859                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2860         } else {
2861                 nfp_net_vf_read_mac(hw);
2862         }
2863
2864         if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr)) {
2865                 /* Using random mac addresses for VFs */
2866                 eth_random_addr(&hw->mac_addr[0]);
2867                 nfp_net_write_mac(hw, (uint8_t *)&hw->mac_addr);
2868         }
2869
2870         /* Copying mac address to DPDK eth_dev struct */
2871         ether_addr_copy((struct ether_addr *)hw->mac_addr,
2872                         &eth_dev->data->mac_addrs[0]);
2873
2874         PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2875                      "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2876                      eth_dev->data->port_id, pci_dev->id.vendor_id,
2877                      pci_dev->id.device_id,
2878                      hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2879                      hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2880
2881         /* Registering LSC interrupt handler */
2882         rte_intr_callback_register(&pci_dev->intr_handle,
2883                                    nfp_net_dev_interrupt_handler,
2884                                    (void *)eth_dev);
2885
2886         /* Telling the firmware about the LSC interrupt entry */
2887         nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2888
2889         /* Recording current stats counters values */
2890         nfp_net_stats_reset(eth_dev);
2891
2892         return 0;
2893 }
2894
2895 static int
2896 nfp_pf_create_dev(struct rte_pci_device *dev, int port, int ports,
2897                   nfpu_desc_t *nfpu_desc, void **priv)
2898 {
2899         struct rte_eth_dev *eth_dev;
2900         struct nfp_net_hw *hw;
2901         char *port_name;
2902         int ret;
2903
2904         port_name = rte_zmalloc("nfp_pf_port_name", 100, 0);
2905         if (!port_name)
2906                 return -ENOMEM;
2907
2908         if (ports > 1)
2909                 sprintf(port_name, "%s_port%d", dev->device.name, port);
2910         else
2911                 sprintf(port_name, "%s", dev->device.name);
2912
2913         eth_dev = rte_eth_dev_allocate(port_name);
2914         if (!eth_dev)
2915                 return -ENOMEM;
2916
2917         if (port == 0) {
2918                 *priv = rte_zmalloc(port_name,
2919                                     sizeof(struct nfp_net_adapter) * ports,
2920                                     RTE_CACHE_LINE_SIZE);
2921                 if (!*priv) {
2922                         rte_eth_dev_release_port(eth_dev);
2923                         return -ENOMEM;
2924                 }
2925         }
2926
2927         eth_dev->data->dev_private = *priv;
2928
2929         /*
2930          * dev_private pointing to port0 dev_private because we need
2931          * to configure vNIC bars based on port0 at nfp_net_init.
2932          * Then dev_private is adjusted per port.
2933          */
2934         hw = (struct nfp_net_hw *)(eth_dev->data->dev_private) + port;
2935         hw->nspu_desc = nfpu_desc->nspu;
2936         hw->nfpu_desc = nfpu_desc;
2937         hw->is_pf = 1;
2938         if (ports > 1)
2939                 hw->pf_multiport_enabled = 1;
2940
2941         eth_dev->device = &dev->device;
2942         rte_eth_copy_pci_info(eth_dev, dev);
2943
2944         ret = nfp_net_init(eth_dev);
2945
2946         if (ret)
2947                 rte_eth_dev_release_port(eth_dev);
2948
2949         rte_free(port_name);
2950
2951         return ret;
2952 }
2953
2954 static int nfp_pf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2955                             struct rte_pci_device *dev)
2956 {
2957         nfpu_desc_t *nfpu_desc;
2958         nspu_desc_t *nspu_desc;
2959         uint64_t offset_symbol;
2960         uint8_t *bar_offset;
2961         int major, minor;
2962         int total_ports;
2963         void *priv = 0;
2964         int ret = -ENODEV;
2965         int i;
2966
2967         if (!dev)
2968                 return ret;
2969
2970         nfpu_desc = rte_malloc("nfp nfpu", sizeof(nfpu_desc_t), 0);
2971         if (!nfpu_desc)
2972                 return -ENOMEM;
2973
2974         if (nfpu_open(dev, nfpu_desc, 0) < 0) {
2975                 RTE_LOG(ERR, PMD,
2976                         "nfpu_open failed\n");
2977                 goto nfpu_error;
2978         }
2979
2980         nspu_desc = nfpu_desc->nspu;
2981
2982
2983         /* Check NSP ABI version */
2984         if (nfp_nsp_get_abi_version(nspu_desc, &major, &minor) < 0) {
2985                 RTE_LOG(INFO, PMD, "NFP NSP not present\n");
2986                 goto error;
2987         }
2988         PMD_INIT_LOG(INFO, "nspu ABI version: %d.%d\n", major, minor);
2989
2990         if ((major == 0) && (minor < 20)) {
2991                 RTE_LOG(INFO, PMD, "NFP NSP ABI version too old. Required 0.20 or higher\n");
2992                 goto error;
2993         }
2994
2995         ret = nfp_nsp_fw_setup(nspu_desc, "nfd_cfg_pf0_num_ports",
2996                                &offset_symbol);
2997         if (ret)
2998                 goto error;
2999
3000         bar_offset = (uint8_t *)dev->mem_resource[0].addr;
3001         bar_offset += offset_symbol;
3002         total_ports = (uint32_t)*bar_offset;
3003         PMD_INIT_LOG(INFO, "Total pf ports: %d\n", total_ports);
3004
3005         if (total_ports <= 0 || total_ports > 8) {
3006                 RTE_LOG(ERR, PMD, "nfd_cfg_pf0_num_ports symbol with wrong value");
3007                 ret = -ENODEV;
3008                 goto error;
3009         }
3010
3011         for (i = 0; i < total_ports; i++) {
3012                 ret = nfp_pf_create_dev(dev, i, total_ports, nfpu_desc, &priv);
3013                 if (ret)
3014                         goto error;
3015         }
3016
3017         return 0;
3018
3019 error:
3020         nfpu_close(nfpu_desc);
3021 nfpu_error:
3022         rte_free(nfpu_desc);
3023
3024         return ret;
3025 }
3026
3027 static const struct rte_pci_id pci_id_nfp_pf_net_map[] = {
3028         {
3029                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3030                                PCI_DEVICE_ID_NFP4000_PF_NIC)
3031         },
3032         {
3033                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3034                                PCI_DEVICE_ID_NFP6000_PF_NIC)
3035         },
3036         {
3037                 .vendor_id = 0,
3038         },
3039 };
3040
3041 static const struct rte_pci_id pci_id_nfp_vf_net_map[] = {
3042         {
3043                 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
3044                                PCI_DEVICE_ID_NFP6000_VF_NIC)
3045         },
3046         {
3047                 .vendor_id = 0,
3048         },
3049 };
3050
3051 static int eth_nfp_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3052         struct rte_pci_device *pci_dev)
3053 {
3054         return rte_eth_dev_pci_generic_probe(pci_dev,
3055                 sizeof(struct nfp_net_adapter), nfp_net_init);
3056 }
3057
3058 static int eth_nfp_pci_remove(struct rte_pci_device *pci_dev)
3059 {
3060         struct rte_eth_dev *eth_dev;
3061         struct nfp_net_hw *hw, *hwport0;
3062         int port = 0;
3063
3064         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
3065         if ((pci_dev->id.device_id == PCI_DEVICE_ID_NFP4000_PF_NIC) ||
3066             (pci_dev->id.device_id == PCI_DEVICE_ID_NFP6000_PF_NIC)) {
3067                 port = get_pf_port_number(eth_dev->data->name);
3068                 hwport0 = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3069                 hw = &hwport0[port];
3070         } else {
3071                 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
3072         }
3073         /* hotplug is not possible with multiport PF */
3074         if (hw->pf_multiport_enabled)
3075                 return -ENOTSUP;
3076         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3077 }
3078
3079 static struct rte_pci_driver rte_nfp_net_pf_pmd = {
3080         .id_table = pci_id_nfp_pf_net_map,
3081         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3082                      RTE_PCI_DRV_IOVA_AS_VA,
3083         .probe = nfp_pf_pci_probe,
3084         .remove = eth_nfp_pci_remove,
3085 };
3086
3087 static struct rte_pci_driver rte_nfp_net_vf_pmd = {
3088         .id_table = pci_id_nfp_vf_net_map,
3089         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3090                      RTE_PCI_DRV_IOVA_AS_VA,
3091         .probe = eth_nfp_pci_probe,
3092         .remove = eth_nfp_pci_remove,
3093 };
3094
3095 RTE_PMD_REGISTER_PCI(net_nfp_pf, rte_nfp_net_pf_pmd);
3096 RTE_PMD_REGISTER_PCI(net_nfp_vf, rte_nfp_net_vf_pmd);
3097 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_pf, pci_id_nfp_pf_net_map);
3098 RTE_PMD_REGISTER_PCI_TABLE(net_nfp_vf, pci_id_nfp_vf_net_map);
3099 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_pf, "* igb_uio | uio_pci_generic | vfio");
3100 RTE_PMD_REGISTER_KMOD_DEP(net_nfp_vf, "* igb_uio | uio_pci_generic | vfio");
3101
3102 /*
3103  * Local variables:
3104  * c-file-style: "Linux"
3105  * indent-tabs-mode: t
3106  * End:
3107  */