drivers/net/qede/base/ecore.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #ifndef __ECORE_H
   8 #define __ECORE_H
   9
  10 /* @DPDK */
  11 #include <sys/stat.h>
  12 #include <fcntl.h>
  13 #include <unistd.h>
  14
  15 #define CONFIG_ECORE_BINARY_FW
  16 #undef CONFIG_ECORE_ZIPPED_FW
  17
  18 #ifdef CONFIG_ECORE_ZIPPED_FW
  19 #include <zlib.h>
  20 #endif
  21
  22 #include "ecore_hsi_common.h"
  23 #include "ecore_hsi_debug_tools.h"
  24 #include "ecore_hsi_init_func.h"
  25 #include "ecore_hsi_init_tool.h"
  26 #include "ecore_proto_if.h"
  27 #include "mcp_public.h"
  28
  29 #define ECORE_MAJOR_VERSION             8
  30 #define ECORE_MINOR_VERSION             30
  31 #define ECORE_REVISION_VERSION          8
  32 #define ECORE_ENGINEERING_VERSION       0
  33
  34 #define ECORE_VERSION                                                   \
  35         ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) |    \
  36          (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION)
  37
  38 #define STORM_FW_VERSION                                                \
  39         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |  \
  40          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  41
  42 #define IS_ECORE_PACING(p_hwfn) \
  43         (!!(p_hwfn->b_en_pacing))
  44
  45 #define MAX_HWFNS_PER_DEVICE    2
  46 #define NAME_SIZE 128 /* @DPDK */
  47 #define ECORE_WFQ_UNIT  100
  48 #include "../qede_logs.h" /* @DPDK */
  49
  50 #define ISCSI_BDQ_ID(_port_id) (_port_id)
  51 #define FCOE_BDQ_ID(_port_id) (_port_id + 2)
  52 /* Constants */
  53 #define ECORE_WID_SIZE          (1024)
  54 #define ECORE_MIN_WIDS          (4)
  55
  56 /* Configurable */
  57 #define ECORE_PF_DEMS_SIZE      (4)
  58
  59 /* cau states */
  60 enum ecore_coalescing_mode {
  61         ECORE_COAL_MODE_DISABLE,
  62         ECORE_COAL_MODE_ENABLE
  63 };
  64
  65 enum ecore_nvm_cmd {
  66         ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  67         ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  68         ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM,
  69         ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  70         ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE,
  71         ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE,
  72         ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE,
  73         ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ,
  74         ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
  75         ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
  76         ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
  77         ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
  78 };
  79
  80 #ifndef LINUX_REMOVE
  81 #if !defined(CONFIG_ECORE_L2)
  82 #define CONFIG_ECORE_L2
  83 #define CONFIG_ECORE_SRIOV
  84 #endif
  85 #endif
  86
  87 /* helpers */
  88 #ifndef __EXTRACT__LINUX__
  89 #define MASK_FIELD(_name, _value)                                       \
  90                 ((_value) &= (_name##_MASK))
  91
  92 #define FIELD_VALUE(_name, _value)                                      \
  93                 ((_value & _name##_MASK) << _name##_SHIFT)
  94
  95 #define SET_FIELD(value, name, flag)                                    \
  96 do {                                                                    \
  97         (value) &= ~(name##_MASK << name##_SHIFT);                      \
  98         (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
  99 } while (0)
 100
 101 #define GET_FIELD(value, name)                                          \
 102         (((value) >> (name##_SHIFT)) & name##_MASK)
 103
 104 #define GET_MFW_FIELD(name, field)                              \
 105         (((name) & (field ## _MASK)) >> (field ## _OFFSET))
 106
 107 #define SET_MFW_FIELD(name, field, value)                               \
 108 do {                                                                    \
 109         (name) &= ~((field ## _MASK));          \
 110         (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \
 111 } while (0)
 112 #endif
 113
 114 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 115 {
 116         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 117                       (cid * ECORE_PF_DEMS_SIZE);
 118
 119         return db_addr;
 120 }
 121
 122 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 123 {
 124         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 125                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 126
 127         return db_addr;
 128 }
 129
 130 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                              \
 131         ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \
 132          ~((1 << (p_hwfn->p_dev->cache_shift)) - 1))
 133
 134 #ifndef LINUX_REMOVE
 135 #ifndef U64_HI
 136 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 137 #endif
 138
 139 #ifndef U64_LO
 140 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 141 #endif
 142 #endif
 143
 144 #ifndef __EXTRACT__LINUX__
 145 enum DP_LEVEL {
 146         ECORE_LEVEL_VERBOSE     = 0x0,
 147         ECORE_LEVEL_INFO        = 0x1,
 148         ECORE_LEVEL_NOTICE      = 0x2,
 149         ECORE_LEVEL_ERR         = 0x3,
 150 };
 151
 152 #define ECORE_LOG_LEVEL_SHIFT   (30)
 153 #define ECORE_LOG_VERBOSE_MASK  (0x3fffffff)
 154 #define ECORE_LOG_INFO_MASK     (0x40000000)
 155 #define ECORE_LOG_NOTICE_MASK   (0x80000000)
 156
 157 enum DP_MODULE {
 158 #ifndef LINUX_REMOVE
 159         ECORE_MSG_DRV           = 0x0001,
 160         ECORE_MSG_PROBE         = 0x0002,
 161         ECORE_MSG_LINK          = 0x0004,
 162         ECORE_MSG_TIMER         = 0x0008,
 163         ECORE_MSG_IFDOWN        = 0x0010,
 164         ECORE_MSG_IFUP          = 0x0020,
 165         ECORE_MSG_RX_ERR        = 0x0040,
 166         ECORE_MSG_TX_ERR        = 0x0080,
 167         ECORE_MSG_TX_QUEUED     = 0x0100,
 168         ECORE_MSG_INTR          = 0x0200,
 169         ECORE_MSG_TX_DONE       = 0x0400,
 170         ECORE_MSG_RX_STATUS     = 0x0800,
 171         ECORE_MSG_PKTDATA       = 0x1000,
 172         ECORE_MSG_HW            = 0x2000,
 173         ECORE_MSG_WOL           = 0x4000,
 174 #endif
 175         ECORE_MSG_SPQ           = 0x10000,
 176         ECORE_MSG_STATS         = 0x20000,
 177         ECORE_MSG_DCB           = 0x40000,
 178         ECORE_MSG_IOV           = 0x80000,
 179         ECORE_MSG_SP            = 0x100000,
 180         ECORE_MSG_STORAGE       = 0x200000,
 181         ECORE_MSG_OOO           = 0x200000,
 182         ECORE_MSG_CXT           = 0x800000,
 183         ECORE_MSG_LL2           = 0x1000000,
 184         ECORE_MSG_ILT           = 0x2000000,
 185         ECORE_MSG_RDMA          = 0x4000000,
 186         ECORE_MSG_DEBUG         = 0x8000000,
 187         /* to be added...up to 0x8000000 */
 188 };
 189 #endif
 190
 191 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++)
 192
 193 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 194         (val == (cond1) ? true1 : \
 195          (val == (cond2) ? true2 : def))
 196
 197 /* forward */
 198 struct ecore_ptt_pool;
 199 struct ecore_spq;
 200 struct ecore_sb_info;
 201 struct ecore_sb_attn_info;
 202 struct ecore_cxt_mngr;
 203 struct ecore_dma_mem;
 204 struct ecore_sb_sp_info;
 205 struct ecore_ll2_info;
 206 struct ecore_l2_info;
 207 struct ecore_igu_info;
 208 struct ecore_mcp_info;
 209 struct ecore_dcbx_info;
 210
 211 struct ecore_rt_data {
 212         u32     *init_val;
 213         bool    *b_valid;
 214 };
 215
 216 enum ecore_tunn_mode {
 217         ECORE_MODE_L2GENEVE_TUNN,
 218         ECORE_MODE_IPGENEVE_TUNN,
 219         ECORE_MODE_L2GRE_TUNN,
 220         ECORE_MODE_IPGRE_TUNN,
 221         ECORE_MODE_VXLAN_TUNN,
 222 };
 223
 224 enum ecore_tunn_clss {
 225         ECORE_TUNN_CLSS_MAC_VLAN,
 226         ECORE_TUNN_CLSS_MAC_VNI,
 227         ECORE_TUNN_CLSS_INNER_MAC_VLAN,
 228         ECORE_TUNN_CLSS_INNER_MAC_VNI,
 229         ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 230         MAX_ECORE_TUNN_CLSS,
 231 };
 232
 233 struct ecore_tunn_update_type {
 234         bool b_update_mode;
 235         bool b_mode_enabled;
 236         enum ecore_tunn_clss tun_cls;
 237 };
 238
 239 struct ecore_tunn_update_udp_port {
 240         bool b_update_port;
 241         u16 port;
 242 };
 243
 244 struct ecore_tunnel_info {
 245         struct ecore_tunn_update_type vxlan;
 246         struct ecore_tunn_update_type l2_geneve;
 247         struct ecore_tunn_update_type ip_geneve;
 248         struct ecore_tunn_update_type l2_gre;
 249         struct ecore_tunn_update_type ip_gre;
 250
 251         struct ecore_tunn_update_udp_port vxlan_port;
 252         struct ecore_tunn_update_udp_port geneve_port;
 253
 254         bool b_update_rx_cls;
 255         bool b_update_tx_cls;
 256 };
 257
 258 /* The PCI personality is not quite synonymous to protocol ID:
 259  * 1. All personalities need CORE connections
 260  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 261  */
 262 enum ecore_pci_personality {
 263         ECORE_PCI_ETH,
 264         ECORE_PCI_FCOE,
 265         ECORE_PCI_ISCSI,
 266         ECORE_PCI_ETH_ROCE,
 267         ECORE_PCI_ETH_IWARP,
 268         ECORE_PCI_ETH_RDMA,
 269         ECORE_PCI_DEFAULT /* default in shmem */
 270 };
 271
 272 /* All VFs are symmetric, all counters are PF + all VFs */
 273 struct ecore_qm_iids {
 274         u32 cids;
 275         u32 vf_cids;
 276         u32 tids;
 277 };
 278
 279 #define MAX_PF_PER_PORT 8
 280
 281 /* HW / FW resources, output of features supported below, most information
 282  * is received from MFW.
 283  */
 284 enum ecore_resources {
 285         ECORE_L2_QUEUE,
 286         ECORE_VPORT,
 287         ECORE_RSS_ENG,
 288         ECORE_PQ,
 289         ECORE_RL,
 290         ECORE_MAC,
 291         ECORE_VLAN,
 292         ECORE_RDMA_CNQ_RAM,
 293         ECORE_ILT,
 294         ECORE_LL2_QUEUE,
 295         ECORE_CMDQS_CQS,
 296         ECORE_RDMA_STATS_QUEUE,
 297         ECORE_BDQ,
 298
 299         /* This is needed only internally for matching against the IGU.
 300          * In case of legacy MFW, would be set to `0'.
 301          */
 302         ECORE_SB,
 303
 304         ECORE_MAX_RESC,
 305 };
 306
 307 /* Features that require resources, given as input to the resource management
 308  * algorithm, the output are the resources above
 309  */
 310 enum ecore_feature {
 311         ECORE_PF_L2_QUE,
 312         ECORE_PF_TC,
 313         ECORE_VF,
 314         ECORE_EXTRA_VF_QUE,
 315         ECORE_VMQ,
 316         ECORE_RDMA_CNQ,
 317         ECORE_ISCSI_CQ,
 318         ECORE_FCOE_CQ,
 319         ECORE_VF_L2_QUE,
 320         ECORE_MAX_FEATURES,
 321 };
 322
 323 enum ecore_port_mode {
 324         ECORE_PORT_MODE_DE_2X40G,
 325         ECORE_PORT_MODE_DE_2X50G,
 326         ECORE_PORT_MODE_DE_1X100G,
 327         ECORE_PORT_MODE_DE_4X10G_F,
 328         ECORE_PORT_MODE_DE_4X10G_E,
 329         ECORE_PORT_MODE_DE_4X20G,
 330         ECORE_PORT_MODE_DE_1X40G,
 331         ECORE_PORT_MODE_DE_2X25G,
 332         ECORE_PORT_MODE_DE_1X25G,
 333         ECORE_PORT_MODE_DE_4X25G,
 334         ECORE_PORT_MODE_DE_2X10G,
 335 };
 336
 337 enum ecore_dev_cap {
 338         ECORE_DEV_CAP_ETH,
 339         ECORE_DEV_CAP_FCOE,
 340         ECORE_DEV_CAP_ISCSI,
 341         ECORE_DEV_CAP_ROCE,
 342         ECORE_DEV_CAP_IWARP
 343 };
 344
 345 #ifndef __EXTRACT__LINUX__
 346 enum ecore_hw_err_type {
 347         ECORE_HW_ERR_FAN_FAIL,
 348         ECORE_HW_ERR_MFW_RESP_FAIL,
 349         ECORE_HW_ERR_HW_ATTN,
 350         ECORE_HW_ERR_DMAE_FAIL,
 351         ECORE_HW_ERR_RAMROD_FAIL,
 352         ECORE_HW_ERR_FW_ASSERT,
 353 };
 354 #endif
 355
 356 enum ecore_db_rec_exec {
 357         DB_REC_DRY_RUN,
 358         DB_REC_REAL_DEAL,
 359         DB_REC_ONCE,
 360 };
 361
 362 struct ecore_hw_info {
 363         /* PCI personality */
 364         enum ecore_pci_personality personality;
 365 #define ECORE_IS_RDMA_PERSONALITY(dev) \
 366         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 367          (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 368          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 369 #define ECORE_IS_ROCE_PERSONALITY(dev) \
 370         ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
 371          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 372 #define ECORE_IS_IWARP_PERSONALITY(dev) \
 373         ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
 374          (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
 375 #define ECORE_IS_L2_PERSONALITY(dev) \
 376         ((dev)->hw_info.personality == ECORE_PCI_ETH || \
 377          ECORE_IS_RDMA_PERSONALITY(dev))
 378 #define ECORE_IS_FCOE_PERSONALITY(dev) \
 379         ((dev)->hw_info.personality == ECORE_PCI_FCOE)
 380 #define ECORE_IS_ISCSI_PERSONALITY(dev) \
 381         ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
 382
 383         /* Resource Allocation scheme results */
 384         u32 resc_start[ECORE_MAX_RESC];
 385         u32 resc_num[ECORE_MAX_RESC];
 386         u32 feat_num[ECORE_MAX_FEATURES];
 387
 388         #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 389         #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 390         #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 391                                          RESC_NUM(_p_hwfn, resc))
 392         #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 393
 394         /* Amount of traffic classes HW supports */
 395         u8 num_hw_tc;
 396
 397 /* Amount of TCs which should be active according to DCBx or upper layer driver
 398  * configuration
 399  */
 400
 401         u8 num_active_tc;
 402
 403         /* The traffic class used by PF for it's offloaded protocol */
 404         u8 offload_tc;
 405
 406         u32 concrete_fid;
 407         u16 opaque_fid;
 408         u16 ovlan;
 409         u32 part_num[4];
 410
 411         unsigned char hw_mac_addr[ETH_ALEN];
 412         u64 node_wwn; /* For FCoE only */
 413         u64 port_wwn; /* For FCoE only */
 414
 415         u16 num_iscsi_conns;
 416         u16 num_fcoe_conns;
 417
 418         struct ecore_igu_info *p_igu_info;
 419         /* Sriov */
 420         u8 max_chains_per_vf;
 421
 422         u32 port_mode;
 423         u32     hw_mode;
 424         unsigned long device_capabilities;
 425
 426         /* Default DCBX mode */
 427         u8 dcbx_mode;
 428
 429         u16 mtu;
 430 };
 431
 432 /* maximun size of read/write commands (HW limit) */
 433 #define DMAE_MAX_RW_SIZE        0x2000
 434
 435 struct ecore_dmae_info {
 436         /* Spinlock for synchronizing access to functions */
 437         osal_spinlock_t lock;
 438
 439         bool b_mem_ready;
 440
 441         u8 channel;
 442
 443         dma_addr_t completion_word_phys_addr;
 444
 445         /* The memory location where the DMAE writes the completion
 446          * value when an operation is finished on this context.
 447          */
 448         u32 *p_completion_word;
 449
 450         dma_addr_t intermediate_buffer_phys_addr;
 451
 452         /* An intermediate buffer for DMAE operations that use virtual
 453          * addresses - data is DMA'd to/from this buffer and then
 454          * memcpy'd to/from the virtual address
 455          */
 456         u32 *p_intermediate_buffer;
 457
 458         dma_addr_t dmae_cmd_phys_addr;
 459         struct dmae_cmd *p_dmae_cmd;
 460 };
 461
 462 struct ecore_wfq_data {
 463         u32 default_min_speed; /* When wfq feature is not configured */
 464         u32 min_speed; /* when feature is configured for any 1 vport */
 465         bool configured;
 466 };
 467
 468 struct ecore_qm_info {
 469         struct init_qm_pq_params    *qm_pq_params;
 470         struct init_qm_vport_params *qm_vport_params;
 471         struct init_qm_port_params  *qm_port_params;
 472         u16                     start_pq;
 473         u8                      start_vport;
 474         u16                     pure_lb_pq;
 475         u16                     offload_pq;
 476         u16                     pure_ack_pq;
 477         u16                     ooo_pq;
 478         u16                     first_vf_pq;
 479         u16                     first_mcos_pq;
 480         u16                     first_rl_pq;
 481         u16                     num_pqs;
 482         u16                     num_vf_pqs;
 483         u8                      num_vports;
 484         u8                      max_phys_tcs_per_port;
 485         u8                      ooo_tc;
 486         bool                    pf_rl_en;
 487         bool                    pf_wfq_en;
 488         bool                    vport_rl_en;
 489         bool                    vport_wfq_en;
 490         u8                      pf_wfq;
 491         u32                     pf_rl;
 492         struct ecore_wfq_data   *wfq_data;
 493         u8                      num_pf_rls;
 494 };
 495
 496 struct ecore_db_recovery_info {
 497         osal_list_t list;
 498         osal_spinlock_t lock;
 499         u32 db_recovery_counter;
 500 };
 501
 502 struct storm_stats {
 503         u32 address;
 504         u32 len;
 505 };
 506
 507 struct ecore_fw_data {
 508 #ifdef CONFIG_ECORE_BINARY_FW
 509         struct fw_ver_info *fw_ver_info;
 510 #endif
 511         const u8 *modes_tree_buf;
 512         union init_op *init_ops;
 513         const u32 *arr_data;
 514         u32 init_ops_size;
 515 };
 516
 517 enum ecore_mf_mode_bit {
 518         /* Supports PF-classification based on tag */
 519         ECORE_MF_OVLAN_CLSS,
 520
 521         /* Supports PF-classification based on MAC */
 522         ECORE_MF_LLH_MAC_CLSS,
 523
 524         /* Supports PF-classification based on protocol type */
 525         ECORE_MF_LLH_PROTO_CLSS,
 526
 527         /* Requires a default PF to be set */
 528         ECORE_MF_NEED_DEF_PF,
 529
 530         /* Allow LL2 to multicast/broadcast */
 531         ECORE_MF_LL2_NON_UNICAST,
 532
 533         /* Allow Cross-PF [& child VFs] Tx-switching */
 534         ECORE_MF_INTER_PF_SWITCH,
 535
 536         /* TODO - if we ever re-utilize any of this logic, we can rename */
 537         ECORE_MF_UFP_SPECIFIC,
 538
 539         ECORE_MF_DISABLE_ARFS,
 540
 541         /* Use vlan for steering */
 542         ECORE_MF_8021Q_TAGGING,
 543
 544         /* Use stag for steering */
 545         ECORE_MF_8021AD_TAGGING,
 546 };
 547
 548 enum ecore_ufp_mode {
 549         ECORE_UFP_MODE_ETS,
 550         ECORE_UFP_MODE_VNIC_BW,
 551 };
 552
 553 enum ecore_ufp_pri_type {
 554         ECORE_UFP_PRI_OS,
 555         ECORE_UFP_PRI_VNIC
 556 };
 557
 558 struct ecore_ufp_info {
 559         enum ecore_ufp_pri_type pri_type;
 560         enum ecore_ufp_mode mode;
 561         u8 tc;
 562 };
 563
 564 enum BAR_ID {
 565         BAR_ID_0,       /* used for GRC */
 566         BAR_ID_1        /* Used for doorbells */
 567 };
 568
 569 struct ecore_hwfn {
 570         struct ecore_dev                *p_dev;
 571         u8                              my_id;          /* ID inside the PF */
 572 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 573         u8                              rel_pf_id;      /* Relative to engine*/
 574         u8                              abs_pf_id;
 575 #define ECORE_PATH_ID(_p_hwfn) \
 576         (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
 577         u8                              port_id;
 578         bool                            b_active;
 579
 580         u32                             dp_module;
 581         u8                              dp_level;
 582         char                            name[NAME_SIZE];
 583         void                            *dp_ctx;
 584
 585         bool                            first_on_engine;
 586         bool                            hw_init_done;
 587
 588         u8                              num_funcs_on_engine;
 589         u8                              enabled_func_idx;
 590
 591         /* BAR access */
 592         void OSAL_IOMEM                 *regview;
 593         void OSAL_IOMEM                 *doorbells;
 594         u64                             db_phys_addr;
 595         unsigned long                   db_size;
 596
 597         /* PTT pool */
 598         struct ecore_ptt_pool           *p_ptt_pool;
 599
 600         /* HW info */
 601         struct ecore_hw_info            hw_info;
 602
 603         /* rt_array (for init-tool) */
 604         struct ecore_rt_data            rt_data;
 605
 606         /* SPQ */
 607         struct ecore_spq                *p_spq;
 608
 609         /* EQ */
 610         struct ecore_eq                 *p_eq;
 611
 612         /* Consolidate Q*/
 613         struct ecore_consq              *p_consq;
 614
 615         /* Slow-Path definitions */
 616         osal_dpc_t                      sp_dpc;
 617         bool                            b_sp_dpc_enabled;
 618
 619         struct ecore_ptt                *p_main_ptt;
 620         struct ecore_ptt                *p_dpc_ptt;
 621
 622         struct ecore_sb_sp_info         *p_sp_sb;
 623         struct ecore_sb_attn_info       *p_sb_attn;
 624
 625         /* Protocol related */
 626         bool                            using_ll2;
 627         struct ecore_ll2_info           *p_ll2_info;
 628         struct ecore_ooo_info           *p_ooo_info;
 629         struct ecore_iscsi_info         *p_iscsi_info;
 630         struct ecore_fcoe_info          *p_fcoe_info;
 631         struct ecore_rdma_info          *p_rdma_info;
 632         struct ecore_pf_params          pf_params;
 633
 634         bool                            b_rdma_enabled_in_prs;
 635         u32                             rdma_prs_search_reg;
 636
 637         struct ecore_cxt_mngr           *p_cxt_mngr;
 638
 639         /* Flag indicating whether interrupts are enabled or not*/
 640         bool                            b_int_enabled;
 641         bool                            b_int_requested;
 642
 643         /* True if the driver requests for the link */
 644         bool                            b_drv_link_init;
 645
 646         struct ecore_vf_iov             *vf_iov_info;
 647         struct ecore_pf_iov             *pf_iov_info;
 648         struct ecore_mcp_info           *mcp_info;
 649         struct ecore_dcbx_info          *p_dcbx_info;
 650         struct ecore_ufp_info           ufp_info;
 651
 652         struct ecore_dmae_info          dmae_info;
 653
 654         /* QM init */
 655         struct ecore_qm_info            qm_info;
 656
 657 #ifdef CONFIG_ECORE_ZIPPED_FW
 658         /* Buffer for unzipping firmware data */
 659         void *unzip_buf;
 660 #endif
 661
 662         struct dbg_tools_data           dbg_info;
 663
 664         struct z_stream_s               *stream;
 665
 666         /* PWM region specific data */
 667         u32                             dpi_size;
 668         u32                             dpi_count;
 669         u32                             dpi_start_offset; /* this is used to
 670                                                            * calculate th
 671                                                            * doorbell address
 672                                                            */
 673
 674         /* If one of the following is set then EDPM shouldn't be used */
 675         u8                              dcbx_no_edpm;
 676         u8                              db_bar_no_edpm;
 677
 678         /* L2-related */
 679         struct ecore_l2_info            *p_l2_info;
 680
 681         /* Mechanism for recovering from doorbell drop */
 682         struct ecore_db_recovery_info   db_recovery_info;
 683
 684         /* Enable/disable pacing, if request to enable then
 685          * IOV and mcos configuration will be skipped.
 686          * this actually reflects the value requested in
 687          * struct ecore_hw_prepare_params by ecore client.
 688          */
 689         bool b_en_pacing;
 690
 691         /* @DPDK */
 692         struct ecore_ptt                *p_arfs_ptt;
 693 };
 694
 695 enum ecore_mf_mode {
 696         ECORE_MF_DEFAULT,
 697         ECORE_MF_OVLAN,
 698         ECORE_MF_NPAR,
 699         ECORE_MF_UFP,
 700 };
 701
 702 /* @DPDK */
 703 struct ecore_dbg_feature {
 704         u8                              *dump_buf;
 705         u32                             buf_size;
 706         u32                             dumped_dwords;
 707 };
 708
 709 enum qed_dbg_features {
 710         DBG_FEATURE_BUS,
 711         DBG_FEATURE_GRC,
 712         DBG_FEATURE_IDLE_CHK,
 713         DBG_FEATURE_MCP_TRACE,
 714         DBG_FEATURE_REG_FIFO,
 715         DBG_FEATURE_PROTECTION_OVERRIDE,
 716         DBG_FEATURE_NUM
 717 };
 718
 719 enum ecore_dev_type {
 720         ECORE_DEV_TYPE_BB,
 721         ECORE_DEV_TYPE_AH,
 722 };
 723
 724 struct ecore_dev {
 725         u32                             dp_module;
 726         u8                              dp_level;
 727         char                            name[NAME_SIZE];
 728         void                            *dp_ctx;
 729
 730         enum ecore_dev_type             type;
 731 /* Translate type/revision combo into the proper conditions */
 732 #define ECORE_IS_BB(dev)        ((dev)->type == ECORE_DEV_TYPE_BB)
 733 #define ECORE_IS_BB_A0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev))
 734 #ifndef ASIC_ONLY
 735 #define ECORE_IS_BB_B0(dev)     ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \
 736                                  (CHIP_REV_IS_TEDIBEAR(dev)))
 737 #else
 738 #define ECORE_IS_BB_B0(dev)     (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev))
 739 #endif
 740 #define ECORE_IS_AH(dev)        ((dev)->type == ECORE_DEV_TYPE_AH)
 741 #define ECORE_IS_K2(dev)        ECORE_IS_AH(dev)
 742
 743         u16 vendor_id;
 744         u16 device_id;
 745 #define ECORE_DEV_ID_MASK       0xff00
 746 #define ECORE_DEV_ID_MASK_BB    0x1600
 747 #define ECORE_DEV_ID_MASK_AH    0x8000
 748
 749         u16                             chip_num;
 750 #define CHIP_NUM_MASK                   0xffff
 751 #define CHIP_NUM_SHIFT                  0
 752
 753         u8                              chip_rev;
 754 #define CHIP_REV_MASK                   0xf
 755 #define CHIP_REV_SHIFT                  0
 756 #ifndef ASIC_ONLY
 757 #define CHIP_REV_IS_TEDIBEAR(_p_dev)    ((_p_dev)->chip_rev == 0x5)
 758 #define CHIP_REV_IS_EMUL_A0(_p_dev)     ((_p_dev)->chip_rev == 0xe)
 759 #define CHIP_REV_IS_EMUL_B0(_p_dev)     ((_p_dev)->chip_rev == 0xc)
 760 #define CHIP_REV_IS_EMUL(_p_dev) \
 761         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev))
 762 #define CHIP_REV_IS_FPGA_A0(_p_dev)     ((_p_dev)->chip_rev == 0xf)
 763 #define CHIP_REV_IS_FPGA_B0(_p_dev)     ((_p_dev)->chip_rev == 0xd)
 764 #define CHIP_REV_IS_FPGA(_p_dev) \
 765         (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev))
 766 #define CHIP_REV_IS_SLOW(_p_dev) \
 767         (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev))
 768 #define CHIP_REV_IS_A0(_p_dev) \
 769         (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \
 770          (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal))
 771 #define CHIP_REV_IS_B0(_p_dev) \
 772         (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \
 773          ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal))
 774 #define CHIP_REV_IS_ASIC(_p_dev)        !CHIP_REV_IS_SLOW(_p_dev)
 775 #else
 776 #define CHIP_REV_IS_A0(_p_dev) \
 777         (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)
 778 #define CHIP_REV_IS_B0(_p_dev) \
 779         ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)
 780 #endif
 781
 782         u8                              chip_metal;
 783 #define CHIP_METAL_MASK                 0xff
 784 #define CHIP_METAL_SHIFT                0
 785
 786         u8                              chip_bond_id;
 787 #define CHIP_BOND_ID_MASK               0xff
 788 #define CHIP_BOND_ID_SHIFT              0
 789
 790         u8                              num_engines;
 791         u8                              num_ports;
 792         u8                              num_ports_in_engine;
 793         u8                              num_funcs_in_port;
 794
 795         u8                              path_id;
 796
 797         unsigned long                   mf_bits;
 798         enum ecore_mf_mode              mf_mode;
 799 #define IS_MF_DEFAULT(_p_hwfn)  \
 800         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
 801 #define IS_MF_SI(_p_hwfn)       \
 802         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
 803 #define IS_MF_SD(_p_hwfn)       \
 804         (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
 805
 806         int                             pcie_width;
 807         int                             pcie_speed;
 808
 809         /* Add MF related configuration */
 810         u8                              mcp_rev;
 811         u8                              boot_mode;
 812
 813         u8                              wol;
 814
 815         u32                             int_mode;
 816         enum ecore_coalescing_mode      int_coalescing_mode;
 817         u16                             rx_coalesce_usecs;
 818         u16                             tx_coalesce_usecs;
 819
 820         /* Start Bar offset of first hwfn */
 821         void OSAL_IOMEM                 *regview;
 822         void OSAL_IOMEM                 *doorbells;
 823         u64                             db_phys_addr;
 824         unsigned long                   db_size;
 825
 826         /* PCI */
 827         u8                              cache_shift;
 828
 829         /* Init */
 830         const struct iro                *iro_arr;
 831         #define IRO (p_hwfn->p_dev->iro_arr)
 832
 833         /* HW functions */
 834         u8                              num_hwfns;
 835         struct ecore_hwfn               hwfns[MAX_HWFNS_PER_DEVICE];
 836 #define ECORE_IS_CMT(dev)               ((dev)->num_hwfns > 1)
 837
 838         /* SRIOV */
 839         struct ecore_hw_sriov_info      *p_iov_info;
 840 #define IS_ECORE_SRIOV(p_dev)           (!!(p_dev)->p_iov_info)
 841         struct ecore_tunnel_info        tunnel;
 842         bool                            b_is_vf;
 843         bool                            b_dont_override_vf_msix;
 844
 845         u32                             drv_type;
 846
 847         u32                             rdma_max_sge;
 848         u32                             rdma_max_inline;
 849         u32                             rdma_max_srq_sge;
 850
 851         struct ecore_eth_stats          *reset_stats;
 852         struct ecore_fw_data            *fw_data;
 853
 854         u32                             mcp_nvm_resp;
 855
 856         /* Recovery */
 857         bool                            recov_in_prog;
 858
 859 /* Indicates whether should prevent attentions from being reasserted */
 860
 861         bool                            attn_clr_en;
 862
 863         /* Indicates whether allowing the MFW to collect a crash dump */
 864         bool                            allow_mdump;
 865
 866         /* Indicates if the reg_fifo is checked after any register access */
 867         bool                            chk_reg_fifo;
 868
 869 #ifndef ASIC_ONLY
 870         bool                            b_is_emul_full;
 871 #endif
 872
 873 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
 874         void                            *firmware;
 875         u64                             fw_len;
 876 #endif
 877
 878         /* @DPDK */
 879         struct ecore_dbg_feature        dbg_features[DBG_FEATURE_NUM];
 880         u8                              engine_for_debug;
 881 };
 882
 883 #define NUM_OF_VFS(dev)         (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
 884                                                   : MAX_NUM_VFS_K2)
 885 #define NUM_OF_L2_QUEUES(dev)   (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 886                                                   : MAX_NUM_L2_QUEUES_K2)
 887 #define NUM_OF_PORTS(dev)       (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 888                                                   : MAX_NUM_PORTS_K2)
 889 #define NUM_OF_SBS(dev)         (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 890                                                   : MAX_SB_PER_PATH_K2)
 891 #define NUM_OF_ENG_PFS(dev)     (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
 892                                                   : MAX_NUM_PFS_K2)
 893
 894 #define CRC8_TABLE_SIZE 256
 895
 896 /**
 897  * @brief ecore_concrete_to_sw_fid - get the sw function id from
 898  *        the concrete value.
 899  *
 900  * @param concrete_fid
 901  *
 902  * @return OSAL_INLINE u8
 903  */
 904 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
 905 {
 906         u8 vfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 907         u8 pfid     = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 908         u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID);
 909         u8 sw_fid;
 910
 911         if (vf_valid)
 912                 sw_fid = vfid + MAX_NUM_PFS;
 913         else
 914                 sw_fid = pfid;
 915
 916         return sw_fid;
 917 }
 918
 919 #define PKT_LB_TC 9
 920 #define MAX_NUM_VOQS_E4 20
 921
 922 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
 923 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
 924                                            struct ecore_ptt *p_ptt,
 925                                            u32 min_pf_rate);
 926
 927 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw);
 928 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw);
 929 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 930 int ecore_device_num_engines(struct ecore_dev *p_dev);
 931 int ecore_device_num_ports(struct ecore_dev *p_dev);
 932 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
 933                            u8 *mac);
 934
 935 /* Flags for indication of required queues */
 936 #define PQ_FLAGS_RLS    (1 << 0)
 937 #define PQ_FLAGS_MCOS   (1 << 1)
 938 #define PQ_FLAGS_LB     (1 << 2)
 939 #define PQ_FLAGS_OOO    (1 << 3)
 940 #define PQ_FLAGS_ACK    (1 << 4)
 941 #define PQ_FLAGS_OFLD   (1 << 5)
 942 #define PQ_FLAGS_VFS    (1 << 6)
 943 #define PQ_FLAGS_LLT    (1 << 7)
 944
 945 /* physical queue index for cm context intialization */
 946 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
 947 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
 948 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
 949 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
 950
 951 /* qm vport for rate limit configuration */
 952 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
 953
 954 const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
 955
 956 /* doorbell recovery mechanism */
 957 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn);
 958 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 959                                enum ecore_db_rec_exec);
 960
 961 /* amount of resources used in qm init */
 962 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
 963 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
 964 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
 965 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
 966 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
 967
 968 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
 969
 970 #endif /* __ECORE_H */