drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore_hsi_eth.h"
  13 #include "ecore_rt_defs.h"
  14 #include "ecore_status.h"
  15 #include "ecore.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_init_fw_funcs.h"
  18 #include "ecore_cxt.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_dev_api.h"
  21
  22 /* Max number of connection types in HW (DQ/CDU etc.) */
  23 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  24 #define NUM_TASK_TYPES          2
  25 #define NUM_TASK_PF_SEGMENTS    4
  26 #define NUM_TASK_VF_SEGMENTS    1
  27
  28 /* Doorbell-Queue constants */
  29 #define DQ_RANGE_SHIFT  4
  30 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  31
  32 /* Searcher constants */
  33 #define SRC_MIN_NUM_ELEMS 256
  34
  35 /* Timers constants */
  36 #define TM_SHIFT        7
  37 #define TM_ALIGN        (1 << TM_SHIFT)
  38 #define TM_ELEM_SIZE    4
  39
  40 /* ILT constants */
  41 /* If for some reason, HW P size is modified to be less than 32K,
  42  * special handling needs to be made for CDU initialization
  43  */
  44 #define ILT_DEFAULT_HW_P_SIZE   3
  45
  46 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  47 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  48
  49 /* ILT entry structure */
  50 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  51 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  52 #define ILT_ENTRY_VALID_MASK            0x1ULL
  53 #define ILT_ENTRY_VALID_SHIFT           52
  54 #define ILT_ENTRY_IN_REGS               2
  55 #define ILT_REG_SIZE_IN_BYTES           4
  56
  57 /* connection context union */
  58 union conn_context {
  59         struct core_conn_context core_ctx;
  60         struct eth_conn_context eth_ctx;
  61 };
  62
  63 struct src_ent {
  64         u8 opaque[56];
  65         u64 next;
  66 };
  67
  68 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  69 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  70
  71 #define CONN_CXT_SIZE(p_hwfn) \
  72         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  73
  74 /* PF per protocl configuration object */
  75 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  76 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  77
  78 struct ecore_tid_seg {
  79         u32 count;
  80         u8 type;
  81         bool has_fl_mem;
  82 };
  83
  84 struct ecore_conn_type_cfg {
  85         u32 cid_count;
  86         u32 cid_start;
  87         u32 cids_per_vf;
  88         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
  89 };
  90
  91 /* ILT Client configuration,
  92  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
  93  * 1 - for connection context (CDUC) and for each task context we need two
  94  * values, for regular task context and for force load memory
  95  */
  96 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
  97 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
  98 #define CDUC_BLK                (0)
  99 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 100 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 101
 102 enum ilt_clients {
 103         ILT_CLI_CDUC,
 104         ILT_CLI_CDUT,
 105         ILT_CLI_QM,
 106         ILT_CLI_TM,
 107         ILT_CLI_SRC,
 108         ILT_CLI_MAX
 109 };
 110
 111 struct ilt_cfg_pair {
 112         u32 reg;
 113         u32 val;
 114 };
 115
 116 struct ecore_ilt_cli_blk {
 117         u32 total_size;         /* 0 means not active */
 118         u32 real_size_in_page;
 119         u32 start_line;
 120         u32 dynamic_line_cnt;
 121 };
 122
 123 struct ecore_ilt_client_cfg {
 124         bool active;
 125
 126         /* ILT boundaries */
 127         struct ilt_cfg_pair first;
 128         struct ilt_cfg_pair last;
 129         struct ilt_cfg_pair p_size;
 130
 131         /* ILT client blocks for PF */
 132         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 133         u32 pf_total_lines;
 134
 135         /* ILT client blocks for VFs */
 136         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 137         u32 vf_total_lines;
 138 };
 139
 140 /* Per Path -
 141  *      ILT shadow table
 142  *      Protocol acquired CID lists
 143  *      PF start line in ILT
 144  */
 145 struct ecore_dma_mem {
 146         dma_addr_t p_phys;
 147         void *p_virt;
 148         osal_size_t size;
 149 };
 150
 151 #define MAP_WORD_SIZE           sizeof(unsigned long)
 152 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 153
 154 struct ecore_cid_acquired_map {
 155         u32 start_cid;
 156         u32 max_count;
 157         unsigned long *cid_map;
 158 };
 159
 160 struct ecore_cxt_mngr {
 161         /* Per protocl configuration */
 162         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 163
 164         /* computed ILT structure */
 165         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 166
 167         /* Task type sizes */
 168         u32 task_type_size[NUM_TASK_TYPES];
 169
 170         /* total number of VFs for this hwfn -
 171          * ALL VFs are symmetric in terms of HW resources
 172          */
 173         u32 vf_count;
 174
 175         /* Acquired CIDs */
 176         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 177
 178         /* ILT  shadow table */
 179         struct ecore_dma_mem *ilt_shadow;
 180         u32 pf_start_line;
 181
 182         /* SRC T2 */
 183         struct ecore_dma_mem *t2;
 184         u32 t2_num_pages;
 185         u64 first_free;
 186         u64 last_free;
 187 };
 188
 189 /* check if resources/configuration is required according to protocol type */
 190 static OSAL_INLINE bool src_proto(enum protocol_type type)
 191 {
 192         return type == PROTOCOLID_TOE;
 193 }
 194
 195 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 196 {
 197         return type == PROTOCOLID_TOE;
 198 }
 199
 200 /* counts the iids for the CDU/CDUC ILT client configuration */
 201 struct ecore_cdu_iids {
 202         u32 pf_cids;
 203         u32 per_vf_cids;
 204 };
 205
 206 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 207                                struct ecore_cdu_iids *iids)
 208 {
 209         u32 type;
 210
 211         for (type = 0; type < MAX_CONN_TYPES; type++) {
 212                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 213                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 214         }
 215 }
 216
 217 /* counts the iids for the Searcher block configuration */
 218 struct ecore_src_iids {
 219         u32 pf_cids;
 220         u32 per_vf_cids;
 221 };
 222
 223 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 224                                            struct ecore_src_iids *iids)
 225 {
 226         u32 i;
 227
 228         for (i = 0; i < MAX_CONN_TYPES; i++) {
 229                 if (!src_proto(i))
 230                         continue;
 231
 232                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 233                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 234         }
 235 }
 236
 237 /* counts the iids for the Timers block configuration */
 238 struct ecore_tm_iids {
 239         u32 pf_cids;
 240         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 241         u32 pf_tids_total;
 242         u32 per_vf_cids;
 243         u32 per_vf_tids;
 244 };
 245
 246 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 247                                           struct ecore_tm_iids *iids)
 248 {
 249         u32 i, j;
 250
 251         for (i = 0; i < MAX_CONN_TYPES; i++) {
 252                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 253
 254                 if (tm_cid_proto(i)) {
 255                         iids->pf_cids += p_cfg->cid_count;
 256                         iids->per_vf_cids += p_cfg->cids_per_vf;
 257                 }
 258         }
 259
 260         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 261         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 262         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 263
 264         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 265                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 266                 iids->pf_tids_total += iids->pf_tids[j];
 267         }
 268 }
 269
 270 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 271 {
 272         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 273         struct ecore_tid_seg *segs;
 274         u32 vf_cids = 0, type, j;
 275         u32 vf_tids = 0;
 276
 277         for (type = 0; type < MAX_CONN_TYPES; type++) {
 278                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 279                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 280
 281                 segs = p_mngr->conn_cfg[type].tid_seg;
 282                 /* for each segment there is at most one
 283                  * protocol for which count is not 0.
 284                  */
 285                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 286                         iids->tids += segs[j].count;
 287
 288                 /* The last array elelment is for the VFs. As for PF
 289                  * segments there can be only one protocol for
 290                  * which this value is not 0.
 291                  */
 292                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 293         }
 294
 295         iids->vf_cids += vf_cids * p_mngr->vf_count;
 296         iids->tids += vf_tids * p_mngr->vf_count;
 297
 298         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 299                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 300                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 301 }
 302
 303 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 304                                                     u32 seg)
 305 {
 306         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 307         u32 i;
 308
 309         /* Find the protocol with tid count > 0 for this segment.
 310          * Note: there can only be one and this is already validated.
 311          */
 312         for (i = 0; i < MAX_CONN_TYPES; i++) {
 313                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 314                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 315         }
 316         return OSAL_NULL;
 317 }
 318
 319 /* set the iids (cid/tid) count per protocol */
 320 void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 321                                    enum protocol_type type,
 322                                    u32 cid_count, u32 vf_cid_cnt)
 323 {
 324         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 325         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 326
 327         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 328         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 329 }
 330
 331 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 332                                   enum protocol_type type, u32 *vf_cid)
 333 {
 334         if (vf_cid)
 335                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 336
 337         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 338 }
 339
 340 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 341                                   enum protocol_type type)
 342 {
 343         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 344 }
 345
 346 static u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 347                                          enum protocol_type type)
 348 {
 349         u32 cnt = 0;
 350         int i;
 351
 352         for (i = 0; i < TASK_SEGMENTS; i++)
 353                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 354
 355         return cnt;
 356 }
 357
 358 static OSAL_INLINE void
 359 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 360                               enum protocol_type proto,
 361                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 362 {
 363         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 364         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 365
 366         p_seg->count = count;
 367         p_seg->has_fl_mem = has_fl;
 368         p_seg->type = seg_type;
 369 }
 370
 371 /* the *p_line parameter must be either 0 for the first invocation or the
 372  * value returned in the previous invocation.
 373  */
 374 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 375                                    struct ecore_ilt_cli_blk *p_blk,
 376                                    u32 start_line,
 377                                    u32 total_size, u32 elem_size)
 378 {
 379         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 380
 381         /* verfiy called once for each block */
 382         if (p_blk->total_size)
 383                 return;
 384
 385         p_blk->total_size = total_size;
 386         p_blk->real_size_in_page = 0;
 387         if (elem_size)
 388                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 389         p_blk->start_line = start_line;
 390 }
 391
 392 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 393                                    struct ecore_ilt_client_cfg *p_cli,
 394                                    struct ecore_ilt_cli_blk *p_blk,
 395                                    u32 *p_line, enum ilt_clients client_id)
 396 {
 397         if (!p_blk->total_size)
 398                 return;
 399
 400         if (!p_cli->active)
 401                 p_cli->first.val = *p_line;
 402
 403         p_cli->active = true;
 404         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 405         p_cli->last.val = *p_line - 1;
 406
 407         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 408                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 409                    client_id, p_cli->first.val, p_cli->last.val,
 410                    p_blk->total_size, p_blk->real_size_in_page,
 411                    p_blk->start_line);
 412 }
 413
 414 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 415                                           enum ilt_clients ilt_client)
 416 {
 417         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 418         struct ecore_ilt_client_cfg *p_cli;
 419         u32 lines_to_skip = 0;
 420         u32 cxts_per_p;
 421
 422         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 423
 424         if (ilt_client == ILT_CLI_CDUC) {
 425                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 426
 427                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 428                     (u32)CONN_CXT_SIZE(p_hwfn);
 429
 430                 lines_to_skip = cid_count / cxts_per_p;
 431         }
 432
 433         return lines_to_skip;
 434 }
 435
 436 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 437 {
 438         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 439         u32 curr_line, total, i, task_size, line;
 440         struct ecore_ilt_client_cfg *p_cli;
 441         struct ecore_ilt_cli_blk *p_blk;
 442         struct ecore_cdu_iids cdu_iids;
 443         struct ecore_src_iids src_iids;
 444         struct ecore_qm_iids qm_iids;
 445         struct ecore_tm_iids tm_iids;
 446         struct ecore_tid_seg *p_seg;
 447
 448         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 449         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 450         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 451         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 452
 453         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 454
 455         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 456                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 457                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 458
 459         /* CDUC */
 460         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 461
 462         curr_line = p_mngr->pf_start_line;
 463
 464         /* CDUC PF */
 465         p_cli->pf_total_lines = 0;
 466
 467         /* get the counters for the CDUC,CDUC and QM clients  */
 468         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 469
 470         p_blk = &p_cli->pf_blks[CDUC_BLK];
 471
 472         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 473
 474         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 475                                total, CONN_CXT_SIZE(p_hwfn));
 476
 477         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 478         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 479
 480         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 481                                                                  ILT_CLI_CDUC);
 482
 483         /* CDUC VF */
 484         p_blk = &p_cli->vf_blks[CDUC_BLK];
 485         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 486
 487         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 488                                total, CONN_CXT_SIZE(p_hwfn));
 489
 490         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 491         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 492
 493         for (i = 1; i < p_mngr->vf_count; i++)
 494                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 495                                        ILT_CLI_CDUC);
 496
 497         /* CDUT PF */
 498         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 499         p_cli->first.val = curr_line;
 500
 501         /* first the 'working' task memory */
 502         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 503                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 504                 if (!p_seg || p_seg->count == 0)
 505                         continue;
 506
 507                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 508                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 509                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 510                                        p_mngr->task_type_size[p_seg->type]);
 511
 512                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 513                                        ILT_CLI_CDUT);
 514         }
 515
 516         /* next the 'init' task memory (forced load memory) */
 517         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 518                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 519                 if (!p_seg || p_seg->count == 0)
 520                         continue;
 521
 522                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 523
 524                 if (!p_seg->has_fl_mem) {
 525                         /* The segment is active (total size pf 'working'
 526                          * memory is > 0) but has no FL (forced-load, Init)
 527                          * memory. Thus:
 528                          *
 529                          * 1.   The total-size in the corrsponding FL block of
 530                          *      the ILT client is set to 0 - No ILT line are
 531                          *      provisioned and no ILT memory allocated.
 532                          *
 533                          * 2.   The start-line of said block is set to the
 534                          *      start line of the matching working memory
 535                          *      block in the ILT client. This is later used to
 536                          *      configure the CDU segment offset registers and
 537                          *      results in an FL command for TIDs of this
 538                          *      segment behaves as regular load commands
 539                          *      (loading TIDs from the working memory).
 540                          */
 541                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 542
 543                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 544                         continue;
 545                 }
 546                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 547
 548                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 549                                        curr_line, total,
 550                                        p_mngr->task_type_size[p_seg->type]);
 551
 552                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 553                                        ILT_CLI_CDUT);
 554         }
 555         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 556
 557         /* CDUT VF */
 558         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 559         if (p_seg && p_seg->count) {
 560                 /* Stricly speaking we need to iterate over all VF
 561                  * task segment types, but a VF has only 1 segment
 562                  */
 563
 564                 /* 'working' memory */
 565                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 566
 567                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 568                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 569                                        curr_line, total,
 570                                        p_mngr->task_type_size[p_seg->type]);
 571
 572                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 573                                        ILT_CLI_CDUT);
 574
 575                 /* 'init' memory */
 576                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 577                 if (!p_seg->has_fl_mem) {
 578                         /* see comment above */
 579                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 580                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 581                 } else {
 582                         task_size = p_mngr->task_type_size[p_seg->type];
 583                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 584                                                curr_line, total, task_size);
 585                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 586                                                ILT_CLI_CDUT);
 587                 }
 588                 p_cli->vf_total_lines = curr_line -
 589                     p_cli->vf_blks[0].start_line;
 590
 591                 /* Now for the rest of the VFs */
 592                 for (i = 1; i < p_mngr->vf_count; i++) {
 593                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 594                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 595                                                ILT_CLI_CDUT);
 596
 597                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 598                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 599                                                ILT_CLI_CDUT);
 600                 }
 601         }
 602
 603         /* QM */
 604         p_cli = &p_mngr->clients[ILT_CLI_QM];
 605         p_blk = &p_cli->pf_blks[0];
 606
 607         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 608         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 609                                      qm_iids.vf_cids, qm_iids.tids,
 610                                      p_hwfn->qm_info.num_pqs,
 611                                      p_hwfn->qm_info.num_vf_pqs);
 612
 613         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 614                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 615                    " num_vf_pqs=%d, memory_size=%d)\n",
 616                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 617                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 618
 619         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 620                                QM_PQ_ELEMENT_SIZE);
 621
 622         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 623         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 624
 625         /* SRC */
 626         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 627         ecore_cxt_src_iids(p_mngr, &src_iids);
 628
 629         /* Both the PF and VFs searcher connections are stored in the per PF
 630          * database. Thus sum the PF searcher cids and all the VFs searcher
 631          * cids.
 632          */
 633         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 634         if (total) {
 635                 u32 local_max = OSAL_MAX_T(u32, total,
 636                                            SRC_MIN_NUM_ELEMS);
 637
 638                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 639
 640                 p_blk = &p_cli->pf_blks[0];
 641                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 642                                        total * sizeof(struct src_ent),
 643                                        sizeof(struct src_ent));
 644
 645                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 646                                        ILT_CLI_SRC);
 647                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 648         }
 649
 650         /* TM PF */
 651         p_cli = &p_mngr->clients[ILT_CLI_TM];
 652         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 653         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 654         if (total) {
 655                 p_blk = &p_cli->pf_blks[0];
 656                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 657                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 658
 659                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 660                                        ILT_CLI_TM);
 661                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 662         }
 663
 664         /* TM VF */
 665         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 666         if (total) {
 667                 p_blk = &p_cli->vf_blks[0];
 668                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 669                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 670
 671                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 672                                        ILT_CLI_TM);
 673                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 674
 675                 for (i = 1; i < p_mngr->vf_count; i++) {
 676                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 677                                                ILT_CLI_TM);
 678                 }
 679         }
 680
 681         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 682             RESC_NUM(p_hwfn, ECORE_ILT)) {
 683                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 684                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 685                 return ECORE_INVAL;
 686         }
 687
 688         return ECORE_SUCCESS;
 689 }
 690
 691 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 692 {
 693         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 694         u32 i;
 695
 696         if (!p_mngr->t2)
 697                 return;
 698
 699         for (i = 0; i < p_mngr->t2_num_pages; i++)
 700                 if (p_mngr->t2[i].p_virt)
 701                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 702                                                p_mngr->t2[i].p_virt,
 703                                                p_mngr->t2[i].p_phys,
 704                                                p_mngr->t2[i].size);
 705
 706         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 707         p_mngr->t2 = OSAL_NULL;
 708 }
 709
 710 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 711 {
 712         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 713         u32 conn_num, total_size, ent_per_page, psz, i;
 714         struct ecore_ilt_client_cfg *p_src;
 715         struct ecore_src_iids src_iids;
 716         struct ecore_dma_mem *p_t2;
 717         enum _ecore_status_t rc;
 718
 719         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 720
 721         /* if the SRC ILT client is inactive - there are no connection
 722          * requiring the searcer, leave.
 723          */
 724         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 725         if (!p_src->active)
 726                 return ECORE_SUCCESS;
 727
 728         ecore_cxt_src_iids(p_mngr, &src_iids);
 729         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 730         total_size = conn_num * sizeof(struct src_ent);
 731
 732         /* use the same page size as the SRC ILT client */
 733         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 734         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 735
 736         /* allocate t2 */
 737         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 738                                  p_mngr->t2_num_pages *
 739                                  sizeof(struct ecore_dma_mem));
 740         if (!p_mngr->t2) {
 741                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 742                 rc = ECORE_NOMEM;
 743                 goto t2_fail;
 744         }
 745
 746         /* allocate t2 pages */
 747         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 748                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 749                 void **p_virt = &p_mngr->t2[i].p_virt;
 750
 751                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 752                                                   &p_mngr->t2[i].p_phys, size);
 753                 if (!p_mngr->t2[i].p_virt) {
 754                         rc = ECORE_NOMEM;
 755                         goto t2_fail;
 756                 }
 757                 OSAL_MEM_ZERO(*p_virt, size);
 758                 p_mngr->t2[i].size = size;
 759                 total_size -= size;
 760         }
 761
 762         /* Set the t2 pointers */
 763
 764         /* entries per page - must be a power of two */
 765         ent_per_page = psz / sizeof(struct src_ent);
 766
 767         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 768
 769         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 770         p_mngr->last_free = (u64)p_t2->p_phys +
 771             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 772
 773         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 774                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 775                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 776                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 777                 u32 j;
 778
 779                 for (j = 0; j < ent_num - 1; j++) {
 780                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 781                         entries[j].next = OSAL_CPU_TO_BE64(val);
 782                 }
 783
 784                 if (i < p_mngr->t2_num_pages - 1)
 785                         val = (u64)p_mngr->t2[i + 1].p_phys;
 786                 else
 787                         val = 0;
 788                 entries[j].next = OSAL_CPU_TO_BE64(val);
 789
 790                 conn_num -= ent_per_page;
 791         }
 792
 793         return ECORE_SUCCESS;
 794
 795 t2_fail:
 796         ecore_cxt_src_t2_free(p_hwfn);
 797         return rc;
 798 }
 799
 800 /* Total number of ILT lines used by this PF */
 801 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 802 {
 803         u32 size = 0;
 804         u32 i;
 805
 806         for (i = 0; i < ILT_CLI_MAX; i++)
 807                 if (!ilt_clients[i].active)
 808                         continue;
 809                 else
 810                         size += (ilt_clients[i].last.val -
 811                                 ilt_clients[i].first.val + 1);
 812
 813         return size;
 814 }
 815
 816 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 817 {
 818         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 819         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 820         u32 ilt_size, i;
 821
 822         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 823
 824         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 825                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 826
 827                 if (p_dma->p_virt)
 828                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 829                                                p_dma->p_virt,
 830                                                p_dma->p_phys, p_dma->size);
 831                 p_dma->p_virt = OSAL_NULL;
 832         }
 833         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 834 }
 835
 836 static enum _ecore_status_t
 837 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 838                     struct ecore_ilt_cli_blk *p_blk,
 839                     enum ilt_clients ilt_client, u32 start_line_offset)
 840 {
 841         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 842         u32 lines, line, sz_left, lines_to_skip = 0;
 843
 844         /* Special handling for RoCE that supports dynamic allocation */
 845         if (ilt_client == ILT_CLI_CDUT)
 846                 return ECORE_SUCCESS;
 847
 848         lines_to_skip = p_blk->dynamic_line_cnt;
 849
 850         if (!p_blk->total_size)
 851                 return ECORE_SUCCESS;
 852
 853         sz_left = p_blk->total_size;
 854         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 855         line = p_blk->start_line + start_line_offset -
 856             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 857
 858         for (; lines; lines--) {
 859                 dma_addr_t p_phys;
 860                 void *p_virt;
 861                 u32 size;
 862
 863                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 864
 865 /* @DPDK */
 866 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 867                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 868                                                          &p_phys, size,
 869                                                          ILT_BLOCK_ALIGN_SIZE);
 870                 if (!p_virt)
 871                         return ECORE_NOMEM;
 872                 OSAL_MEM_ZERO(p_virt, size);
 873
 874                 ilt_shadow[line].p_phys = p_phys;
 875                 ilt_shadow[line].p_virt = p_virt;
 876                 ilt_shadow[line].size = size;
 877
 878                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 879                            "ILT shadow: Line [%d] Physical 0x%" PRIx64
 880                            " Virtual %p Size %d\n",
 881                            line, (u64)p_phys, p_virt, size);
 882
 883                 sz_left -= size;
 884                 line++;
 885         }
 886
 887         return ECORE_SUCCESS;
 888 }
 889
 890 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 891 {
 892         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 893         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 894         struct ecore_ilt_cli_blk *p_blk;
 895         enum _ecore_status_t rc;
 896         u32 size, i, j, k;
 897
 898         size = ecore_cxt_ilt_shadow_size(clients);
 899         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 900                                          size * sizeof(struct ecore_dma_mem));
 901
 902         if (!p_mngr->ilt_shadow) {
 903                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt shadow table");
 904                 rc = ECORE_NOMEM;
 905                 goto ilt_shadow_fail;
 906         }
 907
 908         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 909                    "Allocated 0x%x bytes for ilt shadow\n",
 910                    (u32)(size * sizeof(struct ecore_dma_mem)));
 911
 912         for (i = 0; i < ILT_CLI_MAX; i++)
 913                 if (!clients[i].active) {
 914                         continue;
 915                 } else {
 916                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 917                         p_blk = &clients[i].pf_blks[j];
 918                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 919                         if (rc != ECORE_SUCCESS)
 920                                 goto ilt_shadow_fail;
 921                 }
 922                 for (k = 0; k < p_mngr->vf_count; k++) {
 923                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 924                                 u32 lines = clients[i].vf_total_lines * k;
 925
 926                                 p_blk = &clients[i].vf_blks[j];
 927                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
 928                                                          i, lines);
 929                                 if (rc != ECORE_SUCCESS)
 930                                         goto ilt_shadow_fail;
 931                         }
 932                 }
 933         }
 934
 935         return ECORE_SUCCESS;
 936
 937 ilt_shadow_fail:
 938         ecore_ilt_shadow_free(p_hwfn);
 939         return rc;
 940 }
 941
 942 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
 943 {
 944         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 945         u32 type;
 946
 947         for (type = 0; type < MAX_CONN_TYPES; type++) {
 948                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
 949                 p_mngr->acquired[type].max_count = 0;
 950                 p_mngr->acquired[type].start_cid = 0;
 951         }
 952 }
 953
 954 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
 955 {
 956         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 957         u32 start_cid = 0;
 958         u32 type;
 959
 960         for (type = 0; type < MAX_CONN_TYPES; type++) {
 961                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 962                 u32 size;
 963
 964                 if (cid_cnt == 0)
 965                         continue;
 966
 967                 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
 968                 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
 969                                                              GFP_KERNEL, size);
 970                 if (!p_mngr->acquired[type].cid_map)
 971                         goto cid_map_fail;
 972
 973                 p_mngr->acquired[type].max_count = cid_cnt;
 974                 p_mngr->acquired[type].start_cid = start_cid;
 975
 976                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
 977
 978                 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
 979                            "Type %08x start: %08x count %08x\n",
 980                            type, p_mngr->acquired[type].start_cid,
 981                            p_mngr->acquired[type].max_count);
 982                 start_cid += cid_cnt;
 983         }
 984
 985         return ECORE_SUCCESS;
 986
 987 cid_map_fail:
 988         ecore_cid_map_free(p_hwfn);
 989         return ECORE_NOMEM;
 990 }
 991
 992 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
 993 {
 994         struct ecore_cxt_mngr *p_mngr;
 995         u32 i;
 996
 997         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
 998         if (!p_mngr) {
 999                 DP_NOTICE(p_hwfn, true,
1000                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1001                 return ECORE_NOMEM;
1002         }
1003
1004         /* Initialize ILT client registers */
1005         p_mngr->clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1006         p_mngr->clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
1007         p_mngr->clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1008
1009         p_mngr->clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
1010         p_mngr->clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
1011         p_mngr->clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
1012
1013         p_mngr->clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
1014         p_mngr->clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
1015         p_mngr->clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
1016
1017         p_mngr->clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
1018         p_mngr->clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
1019         p_mngr->clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1020
1021         p_mngr->clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1022         p_mngr->clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
1023         p_mngr->clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1024
1025         /* default ILT page size for all clients is 32K */
1026         for (i = 0; i < ILT_CLI_MAX; i++)
1027                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1028
1029         /* Initialize task sizes */
1030         p_mngr->task_type_size[0] = 512;        /* @DPDK */
1031         p_mngr->task_type_size[1] = 128;        /* @DPDK */
1032
1033         p_mngr->vf_count = p_hwfn->p_dev->sriov_info.total_vfs;
1034         /* Set the cxt mangr pointer priori to further allocations */
1035         p_hwfn->p_cxt_mngr = p_mngr;
1036
1037         return ECORE_SUCCESS;
1038 }
1039
1040 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1041 {
1042         enum _ecore_status_t rc;
1043
1044         /* Allocate the ILT shadow table */
1045         rc = ecore_ilt_shadow_alloc(p_hwfn);
1046         if (rc) {
1047                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1048                 goto tables_alloc_fail;
1049         }
1050
1051         /* Allocate the T2  table */
1052         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1053         if (rc) {
1054                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1055                 goto tables_alloc_fail;
1056         }
1057
1058         /* Allocate and initialize the acquired cids bitmaps */
1059         rc = ecore_cid_map_alloc(p_hwfn);
1060         if (rc) {
1061                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1062                 goto tables_alloc_fail;
1063         }
1064
1065         return ECORE_SUCCESS;
1066
1067 tables_alloc_fail:
1068         ecore_cxt_mngr_free(p_hwfn);
1069         return rc;
1070 }
1071
1072 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1073 {
1074         if (!p_hwfn->p_cxt_mngr)
1075                 return;
1076
1077         ecore_cid_map_free(p_hwfn);
1078         ecore_cxt_src_t2_free(p_hwfn);
1079         ecore_ilt_shadow_free(p_hwfn);
1080         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1081
1082         p_hwfn->p_cxt_mngr = OSAL_NULL;
1083 }
1084
1085 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1086 {
1087         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1088         int type;
1089
1090         /* Reset acquired cids */
1091         for (type = 0; type < MAX_CONN_TYPES; type++) {
1092                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1093                 u32 i;
1094
1095                 if (cid_cnt == 0)
1096                         continue;
1097
1098                 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1099                         p_mngr->acquired[type].cid_map[i] = 0;
1100         }
1101 }
1102
1103 /* HW initialization helper (per Block, per phase) */
1104
1105 /* CDU Common */
1106 #define CDUC_CXT_SIZE_SHIFT                                             \
1107         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1108
1109 #define CDUC_CXT_SIZE_MASK                                              \
1110         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1111
1112 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1113         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1114
1115 #define CDUC_BLOCK_WASTE_MASK                                           \
1116         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1117
1118 #define CDUC_NCIB_SHIFT                                                 \
1119         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1120
1121 #define CDUC_NCIB_MASK                                                  \
1122         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1123
1124 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1125         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1126
1127 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1128         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1129         CDUT_TYPE0_CXT_SIZE_SHIFT)
1130
1131 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1132         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1133
1134 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1135         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1136         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1137
1138 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1139         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1140
1141 #define CDUT_TYPE0_NCIB_MASK                                            \
1142         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1143         CDUT_TYPE0_NCIB_SHIFT)
1144
1145 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1146         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1147
1148 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1149         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1150         CDUT_TYPE1_CXT_SIZE_SHIFT)
1151
1152 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1153         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1154
1155 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1156         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1157         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1158
1159 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1160         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1161
1162 #define CDUT_TYPE1_NCIB_MASK                                            \
1163         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1164         CDUT_TYPE1_NCIB_SHIFT)
1165
1166 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1167 {
1168         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1169
1170         /* CDUC - connection configuration */
1171         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1172         cxt_size = CONN_CXT_SIZE(p_hwfn);
1173         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1174         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1175
1176         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1177         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1178         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1179         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1180
1181         /* CDUT - type-0 tasks configuration */
1182         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1183         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1184         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1185         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1186
1187         /* cxt size and block-waste are multipes of 8 */
1188         cdu_params = 0;
1189         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1190         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1191         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1192         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1193
1194         /* CDUT - type-1 tasks configuration */
1195         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1196         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1197         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1198
1199         /* cxt size and block-waste are multipes of 8 */
1200         cdu_params = 0;
1201         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1202         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1203         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1204         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1205 }
1206
1207 /* CDU PF */
1208 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1209 #define CDU_SEG_REG_TYPE_MASK           0x1
1210 #define CDU_SEG_REG_OFFSET_SHIFT        0
1211 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1212
1213 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1214 {
1215         struct ecore_ilt_client_cfg *p_cli;
1216         struct ecore_tid_seg *p_seg;
1217         u32 cdu_seg_params, offset;
1218         int i;
1219
1220         static const u32 rt_type_offset_arr[] = {
1221                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1222                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1223                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1224                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1225         };
1226
1227         static const u32 rt_type_offset_fl_arr[] = {
1228                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1229                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1230                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1231                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1232         };
1233
1234         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1235
1236         /* There are initializations only for CDUT during pf Phase */
1237         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1238                 /* Segment 0 */
1239                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1240                 if (!p_seg)
1241                         continue;
1242
1243                 /* Note: start_line is already adjusted for the CDU
1244                  * segment register granularity, so we just need to
1245                  * divide. Adjustment is implicit as we assume ILT
1246                  * Page size is larger than 32K!
1247                  */
1248                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1249                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1250                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1251
1252                 cdu_seg_params = 0;
1253                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1254                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1255                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1256
1257                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1258                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1259                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1260
1261                 cdu_seg_params = 0;
1262                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1263                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1264                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1265         }
1266 }
1267
1268 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1269 {
1270         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1271         struct ecore_qm_iids iids;
1272
1273         OSAL_MEM_ZERO(&iids, sizeof(iids));
1274         ecore_cxt_qm_iids(p_hwfn, &iids);
1275
1276         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1277                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1278                             p_hwfn->first_on_engine,
1279                             iids.cids, iids.vf_cids, iids.tids,
1280                             qm_info->start_pq,
1281                             qm_info->num_pqs - qm_info->num_vf_pqs,
1282                             qm_info->num_vf_pqs,
1283                             qm_info->start_vport,
1284                             qm_info->num_vports, qm_info->pf_wfq,
1285                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1286                             p_hwfn->qm_info.qm_vport_params);
1287 }
1288
1289 /* CM PF */
1290 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1291 {
1292         union ecore_qm_pq_params pq_params;
1293         u16 pq;
1294
1295         /* XCM pure-LB queue */
1296         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1297         pq_params.core.tc = LB_TC;
1298         pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1299         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1300
1301         return ECORE_SUCCESS;
1302 }
1303
1304 /* DQ PF */
1305 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1306 {
1307         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1308         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1309
1310         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1311         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1312
1313         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1314         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1315
1316         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1317         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1318
1319         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1320         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1321
1322         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1323         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1324
1325         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1326         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1327
1328         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1329         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1330
1331         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1332         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1333
1334         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1335         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1336
1337         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1338         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1339
1340         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1341         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1342
1343         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1344         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1345
1346         /* Connection types 6 & 7 are not in use, yet they must be configured
1347          * as the highest possible connection. Not configuring them means the
1348          * defaults will be  used, and with a large number of cids a bug may
1349          * occur, if the defaults will be smaller than dq_pf_max_cid /
1350          * dq_vf_max_cid.
1351          */
1352         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1353         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1354
1355         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1356         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1357 }
1358
1359 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1360 {
1361         struct ecore_ilt_client_cfg *ilt_clients;
1362         int i;
1363
1364         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1365         for (i = 0; i < ILT_CLI_MAX; i++)
1366                 if (!ilt_clients[i].active) {
1367                         continue;
1368                 } else {
1369                 STORE_RT_REG(p_hwfn,
1370                              ilt_clients[i].first.reg,
1371                              ilt_clients[i].first.val);
1372                 STORE_RT_REG(p_hwfn,
1373                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1374                 STORE_RT_REG(p_hwfn,
1375                              ilt_clients[i].p_size.reg,
1376                              ilt_clients[i].p_size.val);
1377         }
1378 }
1379
1380 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1381 {
1382         struct ecore_ilt_client_cfg *p_cli;
1383         u32 blk_factor;
1384
1385         /* For simplicty  we set the 'block' to be an ILT page */
1386         STORE_RT_REG(p_hwfn,
1387                      PSWRQ2_REG_VF_BASE_RT_OFFSET,
1388                      p_hwfn->hw_info.first_vf_in_pf);
1389         STORE_RT_REG(p_hwfn,
1390                      PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1391                      p_hwfn->hw_info.first_vf_in_pf +
1392                      p_hwfn->p_dev->sriov_info.total_vfs);
1393
1394         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1395         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1396         if (p_cli->active) {
1397                 STORE_RT_REG(p_hwfn,
1398                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1399                              blk_factor);
1400                 STORE_RT_REG(p_hwfn,
1401                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1402                              p_cli->pf_total_lines);
1403                 STORE_RT_REG(p_hwfn,
1404                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1405                              p_cli->vf_total_lines);
1406         }
1407
1408         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1409         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1410         if (p_cli->active) {
1411                 STORE_RT_REG(p_hwfn,
1412                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1413                              blk_factor);
1414                 STORE_RT_REG(p_hwfn,
1415                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1416                              p_cli->pf_total_lines);
1417                 STORE_RT_REG(p_hwfn,
1418                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1419                              p_cli->vf_total_lines);
1420         }
1421
1422         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1423         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1424         if (p_cli->active) {
1425                 STORE_RT_REG(p_hwfn,
1426                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1427                 STORE_RT_REG(p_hwfn,
1428                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1429                              p_cli->pf_total_lines);
1430                 STORE_RT_REG(p_hwfn,
1431                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1432                              p_cli->vf_total_lines);
1433         }
1434 }
1435
1436 /* ILT (PSWRQ2) PF */
1437 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1438 {
1439         struct ecore_ilt_client_cfg *clients;
1440         struct ecore_cxt_mngr *p_mngr;
1441         struct ecore_dma_mem *p_shdw;
1442         u32 line, rt_offst, i;
1443
1444         ecore_ilt_bounds_init(p_hwfn);
1445         ecore_ilt_vf_bounds_init(p_hwfn);
1446
1447         p_mngr = p_hwfn->p_cxt_mngr;
1448         p_shdw = p_mngr->ilt_shadow;
1449         clients = p_hwfn->p_cxt_mngr->clients;
1450
1451         for (i = 0; i < ILT_CLI_MAX; i++)
1452                 if (!clients[i].active) {
1453                         continue;
1454                 } else {
1455                 /* Client's 1st val and RT array are absolute, ILT shadows'
1456                  * lines are relative.
1457                  */
1458                 line = clients[i].first.val - p_mngr->pf_start_line;
1459                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1460                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1461
1462                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1463                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1464                         u64 ilt_hw_entry = 0;
1465
1466                         /** p_virt could be OSAL_NULL incase of dynamic
1467                          *  allocation
1468                          */
1469                         if (p_shdw[line].p_virt != OSAL_NULL) {
1470                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1471                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1472                                           (p_shdw[line].p_phys >> 12));
1473
1474                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1475                                         "Setting RT[0x%08x] from"
1476                                         " ILT[0x%08x] [Client is %d] to"
1477                                         " Physical addr: 0x%" PRIx64 "\n",
1478                                         rt_offst, line, i,
1479                                         (u64)(p_shdw[line].p_phys >> 12));
1480                         }
1481
1482                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1483                 }
1484         }
1485 }
1486
1487 /* SRC (Searcher) PF */
1488 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1489 {
1490         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1491         u32 rounded_conn_num, conn_num, conn_max;
1492         struct ecore_src_iids src_iids;
1493
1494         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1495         ecore_cxt_src_iids(p_mngr, &src_iids);
1496         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1497         if (!conn_num)
1498                 return;
1499
1500         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1501         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1502
1503         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1504         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1505                      OSAL_LOG2(rounded_conn_num));
1506
1507         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1508                          p_hwfn->p_cxt_mngr->first_free);
1509         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1510                          p_hwfn->p_cxt_mngr->last_free);
1511 }
1512
1513 /* Timers PF */
1514 #define TM_CFG_NUM_IDS_SHIFT            0
1515 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1516 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1517 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1518 #define TM_CFG_PARENT_PF_SHIFT          25
1519 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1520
1521 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1522 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1523
1524 #define TM_CFG_TID_OFFSET_SHIFT         30
1525 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1526 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1527 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1528
1529 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1530 {
1531         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1532         u32 active_seg_mask = 0, tm_offset, rt_reg;
1533         struct ecore_tm_iids tm_iids;
1534         u64 cfg_word;
1535         u8 i;
1536
1537         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1538         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1539
1540         /* @@@TBD No pre-scan for now */
1541
1542         /* Note: We assume consecutive VFs for a PF */
1543         for (i = 0; i < p_mngr->vf_count; i++) {
1544                 cfg_word = 0;
1545                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1546                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1547                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1548                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1549
1550                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1551                     (sizeof(cfg_word) / sizeof(u32)) *
1552                     (p_hwfn->hw_info.first_vf_in_pf + i);
1553                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1554         }
1555
1556         cfg_word = 0;
1557         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1558         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1559         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1560         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
1561
1562         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1563             (sizeof(cfg_word) / sizeof(u32)) *
1564             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1565         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1566
1567         /* enale scan */
1568         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1569                      tm_iids.pf_cids ? 0x1 : 0x0);
1570
1571         /* @@@TBD how to enable the scan for the VFs */
1572
1573         tm_offset = tm_iids.per_vf_cids;
1574
1575         /* Note: We assume consecutive VFs for a PF */
1576         for (i = 0; i < p_mngr->vf_count; i++) {
1577                 cfg_word = 0;
1578                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1579                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1580                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1581                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1582                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1583
1584                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1585                     (sizeof(cfg_word) / sizeof(u32)) *
1586                     (p_hwfn->hw_info.first_vf_in_pf + i);
1587
1588                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1589         }
1590
1591         tm_offset = tm_iids.pf_cids;
1592         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1593                 cfg_word = 0;
1594                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1595                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1596                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1597                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1598                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1599
1600                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1601                     (sizeof(cfg_word) / sizeof(u32)) *
1602                     (NUM_OF_VFS(p_hwfn->p_dev) +
1603                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1604
1605                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1606                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1607
1608                 tm_offset += tm_iids.pf_tids[i];
1609         }
1610
1611         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1612
1613         /* @@@TBD how to enable the scan for the VFs */
1614 }
1615
1616 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn)
1617 {
1618 }
1619
1620 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1621 {
1622         /* CDU configuration */
1623         ecore_cdu_init_common(p_hwfn);
1624         ecore_prs_init_common(p_hwfn);
1625 }
1626
1627 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1628 {
1629         ecore_qm_init_pf(p_hwfn);
1630         ecore_cm_init_pf(p_hwfn);
1631         ecore_dq_init_pf(p_hwfn);
1632         ecore_cdu_init_pf(p_hwfn);
1633         ecore_ilt_init_pf(p_hwfn);
1634         ecore_src_init_pf(p_hwfn);
1635         ecore_tm_init_pf(p_hwfn);
1636 }
1637
1638 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1639                                            enum protocol_type type, u32 *p_cid)
1640 {
1641         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1642         u32 rel_cid;
1643
1644         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1645                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1646                 return ECORE_INVAL;
1647         }
1648
1649         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1650                                            p_mngr->acquired[type].max_count);
1651
1652         if (rel_cid >= p_mngr->acquired[type].max_count) {
1653                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d",
1654                           type);
1655                 return ECORE_NORESOURCES;
1656         }
1657
1658         OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1659
1660         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1661
1662         return ECORE_SUCCESS;
1663 }
1664
1665 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1666                                         u32 cid, enum protocol_type *p_type)
1667 {
1668         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1669         struct ecore_cid_acquired_map *p_map;
1670         enum protocol_type p;
1671         u32 rel_cid;
1672
1673         /* Iterate over protocols and find matching cid range */
1674         for (p = 0; p < MAX_CONN_TYPES; p++) {
1675                 p_map = &p_mngr->acquired[p];
1676
1677                 if (!p_map->cid_map)
1678                         continue;
1679                 if (cid >= p_map->start_cid &&
1680                     cid < p_map->start_cid + p_map->max_count) {
1681                         break;
1682                 }
1683         }
1684         *p_type = p;
1685
1686         if (p == MAX_CONN_TYPES) {
1687                 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1688                 return false;
1689         }
1690         rel_cid = cid - p_map->start_cid;
1691         if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1692                 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1693                 return false;
1694         }
1695         return true;
1696 }
1697
1698 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1699 {
1700         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1701         enum protocol_type type;
1702         bool b_acquired;
1703         u32 rel_cid;
1704
1705         /* Test acquired and find matching per-protocol map */
1706         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1707
1708         if (!b_acquired)
1709                 return;
1710
1711         rel_cid = cid - p_mngr->acquired[type].start_cid;
1712         OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1713 }
1714
1715 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1716                                             struct ecore_cxt_info *p_info)
1717 {
1718         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1719         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1720         enum protocol_type type;
1721         bool b_acquired;
1722
1723         /* Test acquired and find matching per-protocol map */
1724         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1725
1726         if (!b_acquired)
1727                 return ECORE_INVAL;
1728
1729         /* set the protocl type */
1730         p_info->type = type;
1731
1732         /* compute context virtual pointer */
1733         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1734
1735         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1736         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1737         line = p_info->iid / cxts_per_p;
1738
1739         /* Make sure context is allocated (dynamic allocation) */
1740         if (!p_mngr->ilt_shadow[line].p_virt)
1741                 return ECORE_INVAL;
1742
1743         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1744             p_info->iid % cxts_per_p * conn_cxt_size;
1745
1746         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1747                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1748                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1749
1750         return ECORE_SUCCESS;
1751 }
1752
1753 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1754 {
1755         /* Set the number of required CORE connections */
1756         u32 core_cids = 1;      /* SPQ */
1757
1758         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1759
1760         switch (p_hwfn->hw_info.personality) {
1761         case ECORE_PCI_ETH:
1762                 {
1763                         struct ecore_eth_pf_params *p_params =
1764                             &p_hwfn->pf_params.eth_pf_params;
1765
1766                         ecore_cxt_set_proto_cid_count(p_hwfn,
1767                                 PROTOCOLID_ETH,
1768                                 p_params->num_cons, 1); /* FIXME VF count... */
1769
1770                         break;
1771                 }
1772         default:
1773                 return ECORE_INVAL;
1774         }
1775
1776         return ECORE_SUCCESS;
1777 }
1778
1779 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1780                                                 struct ecore_tid_mem *p_info)
1781 {
1782         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1783         u32 proto, seg, total_lines, i, shadow_line;
1784         struct ecore_ilt_client_cfg *p_cli;
1785         struct ecore_ilt_cli_blk *p_fl_seg;
1786         struct ecore_tid_seg *p_seg_info;
1787
1788         /* Verify the personality */
1789         switch (p_hwfn->hw_info.personality) {
1790         default:
1791                 return ECORE_INVAL;
1792         }
1793
1794         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1795         if (!p_cli->active)
1796                 return ECORE_INVAL;
1797
1798         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1799         if (!p_seg_info->has_fl_mem)
1800                 return ECORE_INVAL;
1801
1802         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1803         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1804                                    p_fl_seg->real_size_in_page);
1805
1806         for (i = 0; i < total_lines; i++) {
1807                 shadow_line = i + p_fl_seg->start_line -
1808                     p_hwfn->p_cxt_mngr->pf_start_line;
1809                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1810         }
1811         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1812             p_fl_seg->real_size_in_page;
1813         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1814         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1815             p_info->tid_size;
1816
1817         return ECORE_SUCCESS;
1818 }
1819
1820 /* This function is very RoCE oriented, if another protocol in the future
1821  * will want this feature we'll need to modify the function to be more generic
1822  */
1823 static enum _ecore_status_t
1824 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
1825                          enum ecore_cxt_elem_type elem_type,
1826                          u32 start_iid, u32 count)
1827 {
1828         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
1829         u32 start_line, end_line, shadow_start_line, shadow_end_line;
1830         struct ecore_ilt_client_cfg *p_cli;
1831         struct ecore_ilt_cli_blk *p_blk;
1832         u32 end_iid = start_iid + count;
1833         struct ecore_ptt *p_ptt;
1834         u64 ilt_hw_entry = 0;
1835         u32 i;
1836
1837         if (elem_type == ECORE_ELEM_CXT) {
1838                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1839                 elem_size = CONN_CXT_SIZE(p_hwfn);
1840                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1841         }
1842
1843         /* Calculate line in ilt */
1844         hw_p_size = p_cli->p_size.val;
1845         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1846         start_line = p_blk->start_line + (start_iid / elems_per_p);
1847         end_line = p_blk->start_line + (end_iid / elems_per_p);
1848         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
1849                 end_line--;
1850
1851         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
1852         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
1853
1854         p_ptt = ecore_ptt_acquire(p_hwfn);
1855         if (!p_ptt) {
1856                 DP_NOTICE(p_hwfn, false,
1857                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1858                 return ECORE_TIMEOUT;
1859         }
1860
1861         for (i = shadow_start_line; i < shadow_end_line; i++) {
1862                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
1863                         continue;
1864
1865                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1866                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
1867                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
1868                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
1869
1870                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
1871                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
1872                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
1873
1874                 /* compute absolute offset */
1875                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
1876                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
1877                      ILT_ENTRY_IN_REGS);
1878
1879                 ecore_wr(p_hwfn, p_ptt, reg_offset, U64_LO(ilt_hw_entry));
1880                 ecore_wr(p_hwfn, p_ptt, reg_offset + ILT_REG_SIZE_IN_BYTES,
1881                          U64_HI(ilt_hw_entry));
1882         }
1883
1884         ecore_ptt_release(p_hwfn, p_ptt);
1885
1886         return ECORE_SUCCESS;
1887 }
1888
1889 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
1890                                               enum protocol_type proto)
1891 {
1892         enum _ecore_status_t rc;
1893         u32 cid;
1894
1895         /* Free Connection CXT */
1896         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
1897                                       ecore_cxt_get_proto_cid_start(p_hwfn,
1898                                                                     proto),
1899                                       ecore_cxt_get_proto_cid_count(p_hwfn,
1900                                                                     proto,
1901                                                                     &cid));
1902
1903         if (rc)
1904                 return rc;
1905
1906         /* Free Task CXT */
1907         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
1908                                       ecore_cxt_get_proto_tid_count(p_hwfn,
1909                                                                     proto));
1910
1911         return rc;
1912 }
1913
1914 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
1915                                             u32 tid,
1916                                             u8 ctx_type, void **pp_task_ctx)
1917 {
1918         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1919         struct ecore_ilt_client_cfg *p_cli;
1920         struct ecore_ilt_cli_blk *p_seg;
1921         struct ecore_tid_seg *p_seg_info;
1922         u32 proto, seg;
1923         u32 total_lines;
1924         u32 tid_size, ilt_idx;
1925         u32 num_tids_per_block;
1926
1927         /* Verify the personality */
1928         switch (p_hwfn->hw_info.personality) {
1929         default:
1930                 return ECORE_INVAL;
1931         }
1932
1933         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1934         if (!p_cli->active)
1935                 return ECORE_INVAL;
1936
1937         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1938
1939         if (ctx_type == ECORE_CTX_WORKING_MEM) {
1940                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
1941         } else if (ctx_type == ECORE_CTX_FL_MEM) {
1942                 if (!p_seg_info->has_fl_mem)
1943                         return ECORE_INVAL;
1944                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1945         } else {
1946                 return ECORE_INVAL;
1947         }
1948         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
1949         tid_size = p_mngr->task_type_size[p_seg_info->type];
1950         num_tids_per_block = p_seg->real_size_in_page / tid_size;
1951
1952         if (total_lines < tid / num_tids_per_block)
1953                 return ECORE_INVAL;
1954
1955         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
1956             p_mngr->pf_start_line;
1957         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
1958             (tid % num_tids_per_block) * tid_size;
1959
1960         return ECORE_SUCCESS;
1961 }