drivers/net/qede/base/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_hsi_common.h"
  12 #include "ecore_hsi_eth.h"
  13 #include "ecore_rt_defs.h"
  14 #include "ecore_status.h"
  15 #include "ecore.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_init_fw_funcs.h"
  18 #include "ecore_cxt.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_dev_api.h"
  21 #include "ecore_sriov.h"
  22
  23 /* Max number of connection types in HW (DQ/CDU etc.) */
  24 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  25 #define NUM_TASK_TYPES          2
  26 #define NUM_TASK_PF_SEGMENTS    4
  27 #define NUM_TASK_VF_SEGMENTS    1
  28
  29 /* Doorbell-Queue constants */
  30 #define DQ_RANGE_SHIFT  4
  31 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  32
  33 /* Searcher constants */
  34 #define SRC_MIN_NUM_ELEMS 256
  35
  36 /* Timers constants */
  37 #define TM_SHIFT        7
  38 #define TM_ALIGN        (1 << TM_SHIFT)
  39 #define TM_ELEM_SIZE    4
  40
  41 /* ILT constants */
  42 /* If for some reason, HW P size is modified to be less than 32K,
  43  * special handling needs to be made for CDU initialization
  44  */
  45 #define ILT_DEFAULT_HW_P_SIZE   3
  46
  47 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  48 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  49
  50 /* ILT entry structure */
  51 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  52 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  53 #define ILT_ENTRY_VALID_MASK            0x1ULL
  54 #define ILT_ENTRY_VALID_SHIFT           52
  55 #define ILT_ENTRY_IN_REGS               2
  56 #define ILT_REG_SIZE_IN_BYTES           4
  57
  58 /* connection context union */
  59 union conn_context {
  60         struct core_conn_context core_ctx;
  61         struct eth_conn_context eth_ctx;
  62 };
  63
  64 /* TYPE-0 task context - iSCSI, FCOE */
  65 union type0_task_context {
  66 };
  67
  68 /* TYPE-1 task context - ROCE */
  69 union type1_task_context {
  70         struct regpair reserved; /* @DPDK */
  71 };
  72
  73 struct src_ent {
  74         u8 opaque[56];
  75         u64 next;
  76 };
  77
  78 #define CDUT_SEG_ALIGNMET 3     /* in 4k chunks */
  79 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
  80
  81 #define CONN_CXT_SIZE(p_hwfn) \
  82         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
  83
  84 #define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
  85
  86 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
  87         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
  88
  89 /* Alignment is inherent to the type1_task_context structure */
  90 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
  91
  92 /* PF per protocl configuration object */
  93 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
  94 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
  95
  96 struct ecore_tid_seg {
  97         u32 count;
  98         u8 type;
  99         bool has_fl_mem;
 100 };
 101
 102 struct ecore_conn_type_cfg {
 103         u32 cid_count;
 104         u32 cid_start;
 105         u32 cids_per_vf;
 106         struct ecore_tid_seg tid_seg[TASK_SEGMENTS];
 107 };
 108
 109 /* ILT Client configuration,
 110  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 111  * 1 - for connection context (CDUC) and for each task context we need two
 112  * values, for regular task context and for force load memory
 113  */
 114 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 115 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 116 #define CDUC_BLK                (0)
 117 #define SRQ_BLK                 (0)
 118 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 119 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 120
 121 enum ilt_clients {
 122         ILT_CLI_CDUC,
 123         ILT_CLI_CDUT,
 124         ILT_CLI_QM,
 125         ILT_CLI_TM,
 126         ILT_CLI_SRC,
 127         ILT_CLI_TSDM,
 128         ILT_CLI_MAX
 129 };
 130
 131 struct ilt_cfg_pair {
 132         u32 reg;
 133         u32 val;
 134 };
 135
 136 struct ecore_ilt_cli_blk {
 137         u32 total_size;         /* 0 means not active */
 138         u32 real_size_in_page;
 139         u32 start_line;
 140         u32 dynamic_line_cnt;
 141 };
 142
 143 struct ecore_ilt_client_cfg {
 144         bool active;
 145
 146         /* ILT boundaries */
 147         struct ilt_cfg_pair first;
 148         struct ilt_cfg_pair last;
 149         struct ilt_cfg_pair p_size;
 150
 151         /* ILT client blocks for PF */
 152         struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
 153         u32 pf_total_lines;
 154
 155         /* ILT client blocks for VFs */
 156         struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
 157         u32 vf_total_lines;
 158 };
 159
 160 /* Per Path -
 161  *      ILT shadow table
 162  *      Protocol acquired CID lists
 163  *      PF start line in ILT
 164  */
 165 struct ecore_dma_mem {
 166         dma_addr_t p_phys;
 167         void *p_virt;
 168         osal_size_t size;
 169 };
 170
 171 #define MAP_WORD_SIZE           sizeof(unsigned long)
 172 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 173
 174 struct ecore_cid_acquired_map {
 175         u32 start_cid;
 176         u32 max_count;
 177         unsigned long *cid_map;
 178 };
 179
 180 struct ecore_cxt_mngr {
 181         /* Per protocl configuration */
 182         struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
 183
 184         /* computed ILT structure */
 185         struct ecore_ilt_client_cfg clients[ILT_CLI_MAX];
 186
 187         /* Task type sizes */
 188         u32 task_type_size[NUM_TASK_TYPES];
 189
 190         /* total number of VFs for this hwfn -
 191          * ALL VFs are symmetric in terms of HW resources
 192          */
 193         u32 vf_count;
 194
 195         /* total number of SRQ's for this hwfn */
 196         u32                             srq_count;
 197
 198         /* Acquired CIDs */
 199         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 200
 201         /* ILT  shadow table */
 202         struct ecore_dma_mem *ilt_shadow;
 203         u32 pf_start_line;
 204
 205         /* Mutex for a dynamic ILT allocation */
 206         osal_mutex_t mutex;
 207
 208         /* SRC T2 */
 209         struct ecore_dma_mem *t2;
 210         u32 t2_num_pages;
 211         u64 first_free;
 212         u64 last_free;
 213 };
 214
 215 /* check if resources/configuration is required according to protocol type */
 216 static OSAL_INLINE bool src_proto(enum protocol_type type)
 217 {
 218         return type == PROTOCOLID_TOE;
 219 }
 220
 221 static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
 222 {
 223         return type == PROTOCOLID_TOE;
 224 }
 225
 226 static bool tm_tid_proto(enum protocol_type type)
 227 {
 228         return type == PROTOCOLID_FCOE;
 229 }
 230
 231 /* counts the iids for the CDU/CDUC ILT client configuration */
 232 struct ecore_cdu_iids {
 233         u32 pf_cids;
 234         u32 per_vf_cids;
 235 };
 236
 237 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr,
 238                                struct ecore_cdu_iids *iids)
 239 {
 240         u32 type;
 241
 242         for (type = 0; type < MAX_CONN_TYPES; type++) {
 243                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 244                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 245         }
 246 }
 247
 248 /* counts the iids for the Searcher block configuration */
 249 struct ecore_src_iids {
 250         u32 pf_cids;
 251         u32 per_vf_cids;
 252 };
 253
 254 static OSAL_INLINE void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 255                                            struct ecore_src_iids *iids)
 256 {
 257         u32 i;
 258
 259         for (i = 0; i < MAX_CONN_TYPES; i++) {
 260                 if (!src_proto(i))
 261                         continue;
 262
 263                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 264                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 265         }
 266 }
 267
 268 /* counts the iids for the Timers block configuration */
 269 struct ecore_tm_iids {
 270         u32 pf_cids;
 271         u32 pf_tids[NUM_TASK_PF_SEGMENTS];      /* per segment */
 272         u32 pf_tids_total;
 273         u32 per_vf_cids;
 274         u32 per_vf_tids;
 275 };
 276
 277 static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 278                                           struct ecore_tm_iids *iids)
 279 {
 280         u32 i, j;
 281
 282         for (i = 0; i < MAX_CONN_TYPES; i++) {
 283                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 284
 285                 if (tm_cid_proto(i)) {
 286                         iids->pf_cids += p_cfg->cid_count;
 287                         iids->per_vf_cids += p_cfg->cids_per_vf;
 288                 }
 289
 290                 if (tm_tid_proto(i)) {
 291                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 292
 293                         /* for each segment there is at most one
 294                          * protocol for which count is not 0.
 295                          */
 296                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 297                                 iids->pf_tids[j] += segs[j].count;
 298
 299                         /* The last array elelment is for the VFs. As for PF
 300                          * segments there can be only one protocol for
 301                          * which this value is not 0.
 302                          */
 303                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 304                 }
 305         }
 306
 307         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 308         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 309         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 310
 311         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 312                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 313                 iids->pf_tids_total += iids->pf_tids[j];
 314         }
 315 }
 316
 317 void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids)
 318 {
 319         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 320         struct ecore_tid_seg *segs;
 321         u32 vf_cids = 0, type, j;
 322         u32 vf_tids = 0;
 323
 324         for (type = 0; type < MAX_CONN_TYPES; type++) {
 325                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 326                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 327
 328                 segs = p_mngr->conn_cfg[type].tid_seg;
 329                 /* for each segment there is at most one
 330                  * protocol for which count is not 0.
 331                  */
 332                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 333                         iids->tids += segs[j].count;
 334
 335                 /* The last array elelment is for the VFs. As for PF
 336                  * segments there can be only one protocol for
 337                  * which this value is not 0.
 338                  */
 339                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 340         }
 341
 342         iids->vf_cids += vf_cids * p_mngr->vf_count;
 343         iids->tids += vf_tids * p_mngr->vf_count;
 344
 345         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 346                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 347                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 348 }
 349
 350 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
 351                                                     u32 seg)
 352 {
 353         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 354         u32 i;
 355
 356         /* Find the protocol with tid count > 0 for this segment.
 357          * Note: there can only be one and this is already validated.
 358          */
 359         for (i = 0; i < MAX_CONN_TYPES; i++) {
 360                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 361                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 362         }
 363         return OSAL_NULL;
 364 }
 365
 366 /* set the iids (cid/tid) count per protocol */
 367 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 368                                    enum protocol_type type,
 369                                    u32 cid_count, u32 vf_cid_cnt)
 370 {
 371         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 372         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 373
 374         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 375         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 376 }
 377
 378 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
 379                                   enum protocol_type type, u32 *vf_cid)
 380 {
 381         if (vf_cid)
 382                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 383
 384         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 385 }
 386
 387 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
 388                                   enum protocol_type type)
 389 {
 390         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 391 }
 392
 393 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 394                                          enum protocol_type type)
 395 {
 396         u32 cnt = 0;
 397         int i;
 398
 399         for (i = 0; i < TASK_SEGMENTS; i++)
 400                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 401
 402         return cnt;
 403 }
 404
 405 static OSAL_INLINE void
 406 ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 407                               enum protocol_type proto,
 408                               u8 seg, u8 seg_type, u32 count, bool has_fl)
 409 {
 410         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 411         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 412
 413         p_seg->count = count;
 414         p_seg->has_fl_mem = has_fl;
 415         p_seg->type = seg_type;
 416 }
 417
 418 /* the *p_line parameter must be either 0 for the first invocation or the
 419  * value returned in the previous invocation.
 420  */
 421 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli,
 422                                    struct ecore_ilt_cli_blk *p_blk,
 423                                    u32 start_line,
 424                                    u32 total_size, u32 elem_size)
 425 {
 426         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 427
 428         /* verify that it's called once for each block */
 429         if (p_blk->total_size)
 430                 return;
 431
 432         p_blk->total_size = total_size;
 433         p_blk->real_size_in_page = 0;
 434         if (elem_size)
 435                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 436         p_blk->start_line = start_line;
 437 }
 438
 439 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn,
 440                                    struct ecore_ilt_client_cfg *p_cli,
 441                                    struct ecore_ilt_cli_blk *p_blk,
 442                                    u32 *p_line, enum ilt_clients client_id)
 443 {
 444         if (!p_blk->total_size)
 445                 return;
 446
 447         if (!p_cli->active)
 448                 p_cli->first.val = *p_line;
 449
 450         p_cli->active = true;
 451         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 452         p_cli->last.val = *p_line - 1;
 453
 454         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 455                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x"
 456                    " [Real %08x] Start line %d\n",
 457                    client_id, p_cli->first.val, p_cli->last.val,
 458                    p_blk->total_size, p_blk->real_size_in_page,
 459                    p_blk->start_line);
 460 }
 461
 462 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 463                                           enum ilt_clients ilt_client)
 464 {
 465         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 466         struct ecore_ilt_client_cfg *p_cli;
 467         u32 lines_to_skip = 0;
 468         u32 cxts_per_p;
 469
 470         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 471
 472         if (ilt_client == ILT_CLI_CDUC) {
 473                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 474
 475                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 476                     (u32)CONN_CXT_SIZE(p_hwfn);
 477
 478                 lines_to_skip = cid_count / cxts_per_p;
 479         }
 480
 481         return lines_to_skip;
 482 }
 483
 484 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
 485 {
 486         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 487         u32 curr_line, total, i, task_size, line;
 488         struct ecore_ilt_client_cfg *p_cli;
 489         struct ecore_ilt_cli_blk *p_blk;
 490         struct ecore_cdu_iids cdu_iids;
 491         struct ecore_src_iids src_iids;
 492         struct ecore_qm_iids qm_iids;
 493         struct ecore_tm_iids tm_iids;
 494         struct ecore_tid_seg *p_seg;
 495
 496         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 497         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 498         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 499         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 500
 501         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 502
 503         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 504                    "hwfn [%d] - Set context mngr starting line to be 0x%08x\n",
 505                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 506
 507         /* CDUC */
 508         p_cli = &p_mngr->clients[ILT_CLI_CDUC];
 509
 510         curr_line = p_mngr->pf_start_line;
 511
 512         /* CDUC PF */
 513         p_cli->pf_total_lines = 0;
 514
 515         /* get the counters for the CDUC,CDUC and QM clients  */
 516         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 517
 518         p_blk = &p_cli->pf_blks[CDUC_BLK];
 519
 520         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 521
 522         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 523                                total, CONN_CXT_SIZE(p_hwfn));
 524
 525         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 526         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 527
 528         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 529                                                                  ILT_CLI_CDUC);
 530
 531         /* CDUC VF */
 532         p_blk = &p_cli->vf_blks[CDUC_BLK];
 533         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 534
 535         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 536                                total, CONN_CXT_SIZE(p_hwfn));
 537
 538         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 539         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 540
 541         for (i = 1; i < p_mngr->vf_count; i++)
 542                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 543                                        ILT_CLI_CDUC);
 544
 545         /* CDUT PF */
 546         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 547         p_cli->first.val = curr_line;
 548
 549         /* first the 'working' task memory */
 550         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 551                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 552                 if (!p_seg || p_seg->count == 0)
 553                         continue;
 554
 555                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
 556                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 557                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 558                                        p_mngr->task_type_size[p_seg->type]);
 559
 560                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 561                                        ILT_CLI_CDUT);
 562         }
 563
 564         /* next the 'init' task memory (forced load memory) */
 565         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 566                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 567                 if (!p_seg || p_seg->count == 0)
 568                         continue;
 569
 570                 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
 571
 572                 if (!p_seg->has_fl_mem) {
 573                         /* The segment is active (total size pf 'working'
 574                          * memory is > 0) but has no FL (forced-load, Init)
 575                          * memory. Thus:
 576                          *
 577                          * 1.   The total-size in the corrsponding FL block of
 578                          *      the ILT client is set to 0 - No ILT line are
 579                          *      provisioned and no ILT memory allocated.
 580                          *
 581                          * 2.   The start-line of said block is set to the
 582                          *      start line of the matching working memory
 583                          *      block in the ILT client. This is later used to
 584                          *      configure the CDU segment offset registers and
 585                          *      results in an FL command for TIDs of this
 586                          *      segment behaves as regular load commands
 587                          *      (loading TIDs from the working memory).
 588                          */
 589                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 590
 591                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 592                         continue;
 593                 }
 594                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 595
 596                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 597                                        curr_line, total,
 598                                        p_mngr->task_type_size[p_seg->type]);
 599
 600                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 601                                        ILT_CLI_CDUT);
 602         }
 603         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 604
 605         /* CDUT VF */
 606         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 607         if (p_seg && p_seg->count) {
 608                 /* Stricly speaking we need to iterate over all VF
 609                  * task segment types, but a VF has only 1 segment
 610                  */
 611
 612                 /* 'working' memory */
 613                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 614
 615                 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 616                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 617                                        curr_line, total,
 618                                        p_mngr->task_type_size[p_seg->type]);
 619
 620                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 621                                        ILT_CLI_CDUT);
 622
 623                 /* 'init' memory */
 624                 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 625                 if (!p_seg->has_fl_mem) {
 626                         /* see comment above */
 627                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 628                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 629                 } else {
 630                         task_size = p_mngr->task_type_size[p_seg->type];
 631                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 632                                                curr_line, total, task_size);
 633                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 634                                                ILT_CLI_CDUT);
 635                 }
 636                 p_cli->vf_total_lines = curr_line -
 637                     p_cli->vf_blks[0].start_line;
 638
 639                 /* Now for the rest of the VFs */
 640                 for (i = 1; i < p_mngr->vf_count; i++) {
 641                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 642                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 643                                                ILT_CLI_CDUT);
 644
 645                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 646                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 647                                                ILT_CLI_CDUT);
 648                 }
 649         }
 650
 651         /* QM */
 652         p_cli = &p_mngr->clients[ILT_CLI_QM];
 653         p_blk = &p_cli->pf_blks[0];
 654
 655         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 656         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 657                                      qm_iids.vf_cids, qm_iids.tids,
 658                                      p_hwfn->qm_info.num_pqs,
 659                                      p_hwfn->qm_info.num_vf_pqs);
 660
 661         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 662                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d,"
 663                    " num_vf_pqs=%d, memory_size=%d)\n",
 664                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 665                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 666
 667         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 668                                QM_PQ_ELEMENT_SIZE);
 669
 670         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 671         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 672
 673         /* SRC */
 674         p_cli = &p_mngr->clients[ILT_CLI_SRC];
 675         ecore_cxt_src_iids(p_mngr, &src_iids);
 676
 677         /* Both the PF and VFs searcher connections are stored in the per PF
 678          * database. Thus sum the PF searcher cids and all the VFs searcher
 679          * cids.
 680          */
 681         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 682         if (total) {
 683                 u32 local_max = OSAL_MAX_T(u32, total,
 684                                            SRC_MIN_NUM_ELEMS);
 685
 686                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 687
 688                 p_blk = &p_cli->pf_blks[0];
 689                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 690                                        total * sizeof(struct src_ent),
 691                                        sizeof(struct src_ent));
 692
 693                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 694                                        ILT_CLI_SRC);
 695                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 696         }
 697
 698         /* TM PF */
 699         p_cli = &p_mngr->clients[ILT_CLI_TM];
 700         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 701         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 702         if (total) {
 703                 p_blk = &p_cli->pf_blks[0];
 704                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 705                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 706
 707                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 708                                        ILT_CLI_TM);
 709                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 710         }
 711
 712         /* TM VF */
 713         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 714         if (total) {
 715                 p_blk = &p_cli->vf_blks[0];
 716                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 717                                        total * TM_ELEM_SIZE, TM_ELEM_SIZE);
 718
 719                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 720                                        ILT_CLI_TM);
 721
 722                 for (i = 1; i < p_mngr->vf_count; i++) {
 723                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 724                                                ILT_CLI_TM);
 725                 }
 726
 727                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 728         }
 729
 730         /* TSDM (SRQ CONTEXT) */
 731         total = ecore_cxt_get_srq_count(p_hwfn);
 732
 733         if (total) {
 734                 p_cli = &p_mngr->clients[ILT_CLI_TSDM];
 735                 p_blk = &p_cli->pf_blks[SRQ_BLK];
 736                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 737                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 738
 739                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 740                                        ILT_CLI_TSDM);
 741                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 742         }
 743
 744         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 745             RESC_NUM(p_hwfn, ECORE_ILT)) {
 746                 DP_ERR(p_hwfn, "too many ilt lines...#lines=%d\n",
 747                        curr_line - p_hwfn->p_cxt_mngr->pf_start_line);
 748                 return ECORE_INVAL;
 749         }
 750
 751         return ECORE_SUCCESS;
 752 }
 753
 754 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 755 {
 756         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 757         u32 i;
 758
 759         if (!p_mngr->t2)
 760                 return;
 761
 762         for (i = 0; i < p_mngr->t2_num_pages; i++)
 763                 if (p_mngr->t2[i].p_virt)
 764                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 765                                                p_mngr->t2[i].p_virt,
 766                                                p_mngr->t2[i].p_phys,
 767                                                p_mngr->t2[i].size);
 768
 769         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 770         p_mngr->t2 = OSAL_NULL;
 771 }
 772
 773 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 774 {
 775         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 776         u32 conn_num, total_size, ent_per_page, psz, i;
 777         struct ecore_ilt_client_cfg *p_src;
 778         struct ecore_src_iids src_iids;
 779         struct ecore_dma_mem *p_t2;
 780         enum _ecore_status_t rc;
 781
 782         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 783
 784         /* if the SRC ILT client is inactive - there are no connection
 785          * requiring the searcer, leave.
 786          */
 787         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 788         if (!p_src->active)
 789                 return ECORE_SUCCESS;
 790
 791         ecore_cxt_src_iids(p_mngr, &src_iids);
 792         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 793         total_size = conn_num * sizeof(struct src_ent);
 794
 795         /* use the same page size as the SRC ILT client */
 796         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 797         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 798
 799         /* allocate t2 */
 800         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 801                                  p_mngr->t2_num_pages *
 802                                  sizeof(struct ecore_dma_mem));
 803         if (!p_mngr->t2) {
 804                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 805                 rc = ECORE_NOMEM;
 806                 goto t2_fail;
 807         }
 808
 809         /* allocate t2 pages */
 810         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 811                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 812                 void **p_virt = &p_mngr->t2[i].p_virt;
 813
 814                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 815                                                   &p_mngr->t2[i].p_phys, size);
 816                 if (!p_mngr->t2[i].p_virt) {
 817                         rc = ECORE_NOMEM;
 818                         goto t2_fail;
 819                 }
 820                 OSAL_MEM_ZERO(*p_virt, size);
 821                 p_mngr->t2[i].size = size;
 822                 total_size -= size;
 823         }
 824
 825         /* Set the t2 pointers */
 826
 827         /* entries per page - must be a power of two */
 828         ent_per_page = psz / sizeof(struct src_ent);
 829
 830         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 831
 832         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 833         p_mngr->last_free = (u64)p_t2->p_phys +
 834             ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
 835
 836         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 837                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
 838                 struct src_ent *entries = p_mngr->t2[i].p_virt;
 839                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
 840                 u32 j;
 841
 842                 for (j = 0; j < ent_num - 1; j++) {
 843                         val = p_ent_phys + (j + 1) * sizeof(struct src_ent);
 844                         entries[j].next = OSAL_CPU_TO_BE64(val);
 845                 }
 846
 847                 if (i < p_mngr->t2_num_pages - 1)
 848                         val = (u64)p_mngr->t2[i + 1].p_phys;
 849                 else
 850                         val = 0;
 851                 entries[j].next = OSAL_CPU_TO_BE64(val);
 852
 853                 conn_num -= ent_num;
 854         }
 855
 856         return ECORE_SUCCESS;
 857
 858 t2_fail:
 859         ecore_cxt_src_t2_free(p_hwfn);
 860         return rc;
 861 }
 862
 863 #define for_each_ilt_valid_client(pos, clients)         \
 864         for (pos = 0; pos < ILT_CLI_MAX; pos++)         \
 865                 if (!clients[pos].active) {             \
 866                         continue;                       \
 867                 } else                                  \
 868
 869
 870 /* Total number of ILT lines used by this PF */
 871 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
 872 {
 873         u32 size = 0;
 874         u32 i;
 875
 876         for_each_ilt_valid_client(i, ilt_clients)
 877                 size += (ilt_clients[i].last.val -
 878                          ilt_clients[i].first.val + 1);
 879
 880         return size;
 881 }
 882
 883 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
 884 {
 885         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
 886         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 887         u32 ilt_size, i;
 888
 889         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
 890
 891         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
 892                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
 893
 894                 if (p_dma->p_virt)
 895                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 896                                                p_dma->p_virt,
 897                                                p_dma->p_phys, p_dma->size);
 898                 p_dma->p_virt = OSAL_NULL;
 899         }
 900         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
 901 }
 902
 903 static enum _ecore_status_t
 904 ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
 905                     struct ecore_ilt_cli_blk *p_blk,
 906                     enum ilt_clients ilt_client, u32 start_line_offset)
 907 {
 908         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
 909         u32 lines, line, sz_left, lines_to_skip = 0;
 910
 911         /* Special handling for RoCE that supports dynamic allocation */
 912         if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
 913                 return ECORE_SUCCESS;
 914
 915         lines_to_skip = p_blk->dynamic_line_cnt;
 916
 917         if (!p_blk->total_size)
 918                 return ECORE_SUCCESS;
 919
 920         sz_left = p_blk->total_size;
 921         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip;
 922         line = p_blk->start_line + start_line_offset -
 923             p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
 924
 925         for (; lines; lines--) {
 926                 dma_addr_t p_phys;
 927                 void *p_virt;
 928                 u32 size;
 929
 930                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
 931
 932 /* @DPDK */
 933 #define ILT_BLOCK_ALIGN_SIZE 0x1000
 934                 p_virt = OSAL_DMA_ALLOC_COHERENT_ALIGNED(p_hwfn->p_dev,
 935                                                          &p_phys, size,
 936                                                          ILT_BLOCK_ALIGN_SIZE);
 937                 if (!p_virt)
 938                         return ECORE_NOMEM;
 939                 OSAL_MEM_ZERO(p_virt, size);
 940
 941                 ilt_shadow[line].p_phys = p_phys;
 942                 ilt_shadow[line].p_virt = p_virt;
 943                 ilt_shadow[line].size = size;
 944
 945                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 946                            "ILT shadow: Line [%d] Physical 0x%lx"
 947                            " Virtual %p Size %d\n",
 948                            line, (unsigned long)p_phys, p_virt, size);
 949
 950                 sz_left -= size;
 951                 line++;
 952         }
 953
 954         return ECORE_SUCCESS;
 955 }
 956
 957 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
 958 {
 959         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 960         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
 961         struct ecore_ilt_cli_blk *p_blk;
 962         u32 size, i, j, k;
 963         enum _ecore_status_t rc;
 964
 965         size = ecore_cxt_ilt_shadow_size(clients);
 966         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 967                                          size * sizeof(struct ecore_dma_mem));
 968
 969         if (!p_mngr->ilt_shadow) {
 970                 DP_NOTICE(p_hwfn, true,
 971                           "Failed to allocate ilt shadow table\n");
 972                 rc = ECORE_NOMEM;
 973                 goto ilt_shadow_fail;
 974         }
 975
 976         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 977                    "Allocated 0x%x bytes for ilt shadow\n",
 978                    (u32)(size * sizeof(struct ecore_dma_mem)));
 979
 980         for_each_ilt_valid_client(i, clients) {
 981                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
 982                         p_blk = &clients[i].pf_blks[j];
 983                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
 984                         if (rc != ECORE_SUCCESS)
 985                                 goto ilt_shadow_fail;
 986                 }
 987                 for (k = 0; k < p_mngr->vf_count; k++) {
 988                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
 989                                 u32 lines = clients[i].vf_total_lines * k;
 990
 991                                 p_blk = &clients[i].vf_blks[j];
 992                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
 993                                                          i, lines);
 994                                 if (rc != ECORE_SUCCESS)
 995                                         goto ilt_shadow_fail;
 996                         }
 997                 }
 998         }
 999
1000         return ECORE_SUCCESS;
1001
1002 ilt_shadow_fail:
1003         ecore_ilt_shadow_free(p_hwfn);
1004         return rc;
1005 }
1006
1007 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1008 {
1009         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1010         u32 type;
1011
1012         for (type = 0; type < MAX_CONN_TYPES; type++) {
1013                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1014                 p_mngr->acquired[type].max_count = 0;
1015                 p_mngr->acquired[type].start_cid = 0;
1016         }
1017 }
1018
1019 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1020 {
1021         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1022         u32 start_cid = 0;
1023         u32 type;
1024
1025         for (type = 0; type < MAX_CONN_TYPES; type++) {
1026                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1027                 u32 size;
1028
1029                 if (cid_cnt == 0)
1030                         continue;
1031
1032                 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD);
1033                 p_mngr->acquired[type].cid_map = OSAL_ZALLOC(p_hwfn->p_dev,
1034                                                              GFP_KERNEL, size);
1035                 if (!p_mngr->acquired[type].cid_map)
1036                         goto cid_map_fail;
1037
1038                 p_mngr->acquired[type].max_count = cid_cnt;
1039                 p_mngr->acquired[type].start_cid = start_cid;
1040
1041                 p_hwfn->p_cxt_mngr->conn_cfg[type].cid_start = start_cid;
1042
1043                 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1044                            "Type %08x start: %08x count %08x\n",
1045                            type, p_mngr->acquired[type].start_cid,
1046                            p_mngr->acquired[type].max_count);
1047                 start_cid += cid_cnt;
1048         }
1049
1050         return ECORE_SUCCESS;
1051
1052 cid_map_fail:
1053         ecore_cid_map_free(p_hwfn);
1054         return ECORE_NOMEM;
1055 }
1056
1057 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1058 {
1059         struct ecore_ilt_client_cfg *clients;
1060         struct ecore_cxt_mngr *p_mngr;
1061         u32 i;
1062
1063         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1064         if (!p_mngr) {
1065                 DP_NOTICE(p_hwfn, true,
1066                           "Failed to allocate `struct ecore_cxt_mngr'\n");
1067                 return ECORE_NOMEM;
1068         }
1069
1070         /* Initialize ILT client registers */
1071         clients = p_mngr->clients;
1072         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1073         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1074         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1075
1076         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1077         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1078         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1079
1080         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1081         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1082         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1083
1084         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1085         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1086         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1087
1088         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1089         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1090         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1091
1092         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1093         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1094         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1095
1096         /* default ILT page size for all clients is 32K */
1097         for (i = 0; i < ILT_CLI_MAX; i++)
1098                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1099
1100         /* due to removal of ISCSI/FCoE files union type0_task_context
1101          * task_type_size will be 0. So hardcoded for now.
1102          */
1103         p_mngr->task_type_size[0] = 512; /* @DPDK */
1104         p_mngr->task_type_size[1] = 128; /* @DPDK */
1105
1106         if (p_hwfn->p_dev->p_iov_info)
1107                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1108
1109         /* Initialize the dynamic ILT allocation mutex */
1110         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1111         OSAL_MUTEX_INIT(&p_mngr->mutex);
1112
1113         /* Set the cxt mangr pointer priori to further allocations */
1114         p_hwfn->p_cxt_mngr = p_mngr;
1115
1116         return ECORE_SUCCESS;
1117 }
1118
1119 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1120 {
1121         enum _ecore_status_t rc;
1122
1123         /* Allocate the ILT shadow table */
1124         rc = ecore_ilt_shadow_alloc(p_hwfn);
1125         if (rc) {
1126                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1127                 goto tables_alloc_fail;
1128         }
1129
1130         /* Allocate the T2  table */
1131         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1132         if (rc) {
1133                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1134                 goto tables_alloc_fail;
1135         }
1136
1137         /* Allocate and initialize the acquired cids bitmaps */
1138         rc = ecore_cid_map_alloc(p_hwfn);
1139         if (rc) {
1140                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1141                 goto tables_alloc_fail;
1142         }
1143
1144         return ECORE_SUCCESS;
1145
1146 tables_alloc_fail:
1147         ecore_cxt_mngr_free(p_hwfn);
1148         return rc;
1149 }
1150
1151 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1152 {
1153         if (!p_hwfn->p_cxt_mngr)
1154                 return;
1155
1156         ecore_cid_map_free(p_hwfn);
1157         ecore_cxt_src_t2_free(p_hwfn);
1158         ecore_ilt_shadow_free(p_hwfn);
1159         OSAL_MUTEX_DEALLOC(&p_mngr->mutex);
1160         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1161
1162         p_hwfn->p_cxt_mngr = OSAL_NULL;
1163 }
1164
1165 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1166 {
1167         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1168         int type;
1169
1170         /* Reset acquired cids */
1171         for (type = 0; type < MAX_CONN_TYPES; type++) {
1172                 u32 cid_cnt = p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
1173                 u32 i;
1174
1175                 if (cid_cnt == 0)
1176                         continue;
1177
1178                 for (i = 0; i < DIV_ROUND_UP(cid_cnt, BITS_PER_MAP_WORD); i++)
1179                         p_mngr->acquired[type].cid_map[i] = 0;
1180         }
1181 }
1182
1183 /* HW initialization helper (per Block, per phase) */
1184
1185 /* CDU Common */
1186 #define CDUC_CXT_SIZE_SHIFT                                             \
1187         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1188
1189 #define CDUC_CXT_SIZE_MASK                                              \
1190         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1191
1192 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1193         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1194
1195 #define CDUC_BLOCK_WASTE_MASK                                           \
1196         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1197
1198 #define CDUC_NCIB_SHIFT                                                 \
1199         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1200
1201 #define CDUC_NCIB_MASK                                                  \
1202         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1203
1204 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1205         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1206
1207 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1208         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1209         CDUT_TYPE0_CXT_SIZE_SHIFT)
1210
1211 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1212         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1213
1214 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1215         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1216         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1217
1218 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1219         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1220
1221 #define CDUT_TYPE0_NCIB_MASK                                            \
1222         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1223         CDUT_TYPE0_NCIB_SHIFT)
1224
1225 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1226         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1227
1228 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1229         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1230         CDUT_TYPE1_CXT_SIZE_SHIFT)
1231
1232 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1233         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1234
1235 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1236         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1237         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1238
1239 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1240         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1241
1242 #define CDUT_TYPE1_NCIB_MASK                                            \
1243         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1244         CDUT_TYPE1_NCIB_SHIFT)
1245
1246 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1247 {
1248         u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0;
1249
1250         /* CDUC - connection configuration */
1251         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1252         cxt_size = CONN_CXT_SIZE(p_hwfn);
1253         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1254         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1255
1256         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1257         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1258         SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page);
1259         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1260
1261         /* CDUT - type-0 tasks configuration */
1262         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1263         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1264         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1265         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1266
1267         /* cxt size and block-waste are multipes of 8 */
1268         cdu_params = 0;
1269         SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1270         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1271         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1272         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1273
1274         /* CDUT - type-1 tasks configuration */
1275         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1276         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1277         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1278
1279         /* cxt size and block-waste are multipes of 8 */
1280         cdu_params = 0;
1281         SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1282         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1283         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1284         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1285 }
1286
1287 /* CDU PF */
1288 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1289 #define CDU_SEG_REG_TYPE_MASK           0x1
1290 #define CDU_SEG_REG_OFFSET_SHIFT        0
1291 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1292
1293 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1294 {
1295         struct ecore_ilt_client_cfg *p_cli;
1296         struct ecore_tid_seg *p_seg;
1297         u32 cdu_seg_params, offset;
1298         int i;
1299
1300         static const u32 rt_type_offset_arr[] = {
1301                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1302                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1303                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1304                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1305         };
1306
1307         static const u32 rt_type_offset_fl_arr[] = {
1308                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1309                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1310                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1311                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1312         };
1313
1314         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1315
1316         /* There are initializations only for CDUT during pf Phase */
1317         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1318                 /* Segment 0 */
1319                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1320                 if (!p_seg)
1321                         continue;
1322
1323                 /* Note: start_line is already adjusted for the CDU
1324                  * segment register granularity, so we just need to
1325                  * divide. Adjustment is implicit as we assume ILT
1326                  * Page size is larger than 32K!
1327                  */
1328                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1329                           (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1330                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1331
1332                 cdu_seg_params = 0;
1333                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1334                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1335                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params);
1336
1337                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1338                           (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1339                            p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1340
1341                 cdu_seg_params = 0;
1342                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1343                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1344                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params);
1345         }
1346 }
1347
1348 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1349 {
1350         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1351         struct ecore_qm_iids iids;
1352
1353         OSAL_MEM_ZERO(&iids, sizeof(iids));
1354         ecore_cxt_qm_iids(p_hwfn, &iids);
1355
1356         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1357                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1358                             p_hwfn->first_on_engine,
1359                             iids.cids, iids.vf_cids, iids.tids,
1360                             qm_info->start_pq,
1361                             qm_info->num_pqs - qm_info->num_vf_pqs,
1362                             qm_info->num_vf_pqs,
1363                             qm_info->start_vport,
1364                             qm_info->num_vports, qm_info->pf_wfq,
1365                             qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
1366                             p_hwfn->qm_info.qm_vport_params);
1367 }
1368
1369 /* CM PF */
1370 static enum _ecore_status_t ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1371 {
1372         union ecore_qm_pq_params pq_params;
1373         u16 pq;
1374
1375         /* XCM pure-LB queue */
1376         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
1377         pq_params.core.tc = LB_TC;
1378         pq = ecore_get_qm_pq(p_hwfn, PROTOCOLID_CORE, &pq_params);
1379         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, pq);
1380
1381         return ECORE_SUCCESS;
1382 }
1383
1384 /* DQ PF */
1385 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1386 {
1387         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1388         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1389
1390         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1391         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1392
1393         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1394         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1395
1396         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1397         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1398
1399         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1400         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1401
1402         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1403         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1404
1405         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1406         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1407
1408         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1409         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1410
1411         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1412         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1413
1414         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1415         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1416
1417         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1418         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1419
1420         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1421         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1422
1423         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1424         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1425
1426         /* Connection types 6 & 7 are not in use, yet they must be configured
1427          * as the highest possible connection. Not configuring them means the
1428          * defaults will be  used, and with a large number of cids a bug may
1429          * occur, if the defaults will be smaller than dq_pf_max_cid /
1430          * dq_vf_max_cid.
1431          */
1432         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1433         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1434
1435         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1436         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1437 }
1438
1439 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1440 {
1441         struct ecore_ilt_client_cfg *ilt_clients;
1442         int i;
1443
1444         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1445         for_each_ilt_valid_client(i, ilt_clients) {
1446                 STORE_RT_REG(p_hwfn,
1447                              ilt_clients[i].first.reg,
1448                              ilt_clients[i].first.val);
1449                 STORE_RT_REG(p_hwfn,
1450                              ilt_clients[i].last.reg, ilt_clients[i].last.val);
1451                 STORE_RT_REG(p_hwfn,
1452                              ilt_clients[i].p_size.reg,
1453                              ilt_clients[i].p_size.val);
1454         }
1455 }
1456
1457 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1458 {
1459         struct ecore_ilt_client_cfg *p_cli;
1460         u32 blk_factor;
1461
1462         /* For simplicty  we set the 'block' to be an ILT page */
1463         if (p_hwfn->p_dev->p_iov_info) {
1464                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1465
1466                 STORE_RT_REG(p_hwfn,
1467                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1468                              p_iov->first_vf_in_pf);
1469                 STORE_RT_REG(p_hwfn,
1470                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1471                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1472         }
1473
1474         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1475         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1476         if (p_cli->active) {
1477                 STORE_RT_REG(p_hwfn,
1478                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1479                              blk_factor);
1480                 STORE_RT_REG(p_hwfn,
1481                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1482                              p_cli->pf_total_lines);
1483                 STORE_RT_REG(p_hwfn,
1484                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1485                              p_cli->vf_total_lines);
1486         }
1487
1488         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1489         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1490         if (p_cli->active) {
1491                 STORE_RT_REG(p_hwfn,
1492                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1493                              blk_factor);
1494                 STORE_RT_REG(p_hwfn,
1495                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1496                              p_cli->pf_total_lines);
1497                 STORE_RT_REG(p_hwfn,
1498                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1499                              p_cli->vf_total_lines);
1500         }
1501
1502         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1503         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1504         if (p_cli->active) {
1505                 STORE_RT_REG(p_hwfn,
1506                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor);
1507                 STORE_RT_REG(p_hwfn,
1508                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1509                              p_cli->pf_total_lines);
1510                 STORE_RT_REG(p_hwfn,
1511                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1512                              p_cli->vf_total_lines);
1513         }
1514 }
1515
1516 /* ILT (PSWRQ2) PF */
1517 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1518 {
1519         struct ecore_ilt_client_cfg *clients;
1520         struct ecore_cxt_mngr *p_mngr;
1521         struct ecore_dma_mem *p_shdw;
1522         u32 line, rt_offst, i;
1523
1524         ecore_ilt_bounds_init(p_hwfn);
1525         ecore_ilt_vf_bounds_init(p_hwfn);
1526
1527         p_mngr = p_hwfn->p_cxt_mngr;
1528         p_shdw = p_mngr->ilt_shadow;
1529         clients = p_hwfn->p_cxt_mngr->clients;
1530
1531         for_each_ilt_valid_client(i, clients) {
1532                 /* Client's 1st val and RT array are absolute, ILT shadows'
1533                  * lines are relative.
1534                  */
1535                 line = clients[i].first.val - p_mngr->pf_start_line;
1536                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1537                     clients[i].first.val * ILT_ENTRY_IN_REGS;
1538
1539                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1540                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1541                         u64 ilt_hw_entry = 0;
1542
1543                         /** p_virt could be OSAL_NULL incase of dynamic
1544                          *  allocation
1545                          */
1546                         if (p_shdw[line].p_virt != OSAL_NULL) {
1547                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1548                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1549                                           (p_shdw[line].p_phys >> 12));
1550
1551                                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1552                                         "Setting RT[0x%08x] from"
1553                                         " ILT[0x%08x] [Client is %d] to"
1554                                         " Physical addr: 0x%lx\n",
1555                                         rt_offst, line, i,
1556                                         (unsigned long)(p_shdw[line].
1557                                                         p_phys >> 12));
1558                         }
1559
1560                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1561                 }
1562         }
1563 }
1564
1565 /* SRC (Searcher) PF */
1566 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1567 {
1568         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1569         u32 rounded_conn_num, conn_num, conn_max;
1570         struct ecore_src_iids src_iids;
1571
1572         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1573         ecore_cxt_src_iids(p_mngr, &src_iids);
1574         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1575         if (!conn_num)
1576                 return;
1577
1578         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1579         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1580
1581         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1582         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1583                      OSAL_LOG2(rounded_conn_num));
1584
1585         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1586                          p_hwfn->p_cxt_mngr->first_free);
1587         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1588                          p_hwfn->p_cxt_mngr->last_free);
1589 }
1590
1591 /* Timers PF */
1592 #define TM_CFG_NUM_IDS_SHIFT            0
1593 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1594 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1595 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1596 #define TM_CFG_PARENT_PF_SHIFT          25
1597 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1598
1599 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1600 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1601
1602 #define TM_CFG_TID_OFFSET_SHIFT         30
1603 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1604 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1605 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1606
1607 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1608 {
1609         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1610         u32 active_seg_mask = 0, tm_offset, rt_reg;
1611         struct ecore_tm_iids tm_iids;
1612         u64 cfg_word;
1613         u8 i;
1614
1615         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1616         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1617
1618         /* @@@TBD No pre-scan for now */
1619
1620         /* Note: We assume consecutive VFs for a PF */
1621         for (i = 0; i < p_mngr->vf_count; i++) {
1622                 cfg_word = 0;
1623                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1624                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1625                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1626                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1627
1628                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1629                     (sizeof(cfg_word) / sizeof(u32)) *
1630                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1631                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1632         }
1633
1634         cfg_word = 0;
1635         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1636         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1637         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);       /* n/a for PF */
1638         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1639
1640         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1641             (sizeof(cfg_word) / sizeof(u32)) *
1642             (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1643         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1644
1645         /* enale scan */
1646         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1647                      tm_iids.pf_cids ? 0x1 : 0x0);
1648
1649         /* @@@TBD how to enable the scan for the VFs */
1650
1651         tm_offset = tm_iids.per_vf_cids;
1652
1653         /* Note: We assume consecutive VFs for a PF */
1654         for (i = 0; i < p_mngr->vf_count; i++) {
1655                 cfg_word = 0;
1656                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1657                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1658                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1659                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1660                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1661
1662                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1663                     (sizeof(cfg_word) / sizeof(u32)) *
1664                     (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1665
1666                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1667         }
1668
1669         tm_offset = tm_iids.pf_cids;
1670         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1671                 cfg_word = 0;
1672                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1673                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1674                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1675                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1676                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1677
1678                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1679                     (sizeof(cfg_word) / sizeof(u32)) *
1680                     (NUM_OF_VFS(p_hwfn->p_dev) +
1681                      p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1682
1683                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1684                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1685
1686                 tm_offset += tm_iids.pf_tids[i];
1687         }
1688
1689         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1690
1691         /* @@@TBD how to enable the scan for the VFs */
1692 }
1693
1694 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1695 {
1696         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1697         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1698         struct ecore_tid_seg *p_tid;
1699
1700         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1701         if (!p_fcoe->cid_count)
1702                 return;
1703
1704         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1705         STORE_RT_REG_AGG(p_hwfn,
1706                         PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1707                         p_tid->count);
1708 }
1709
1710 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1711 {
1712         /* CDU configuration */
1713         ecore_cdu_init_common(p_hwfn);
1714 }
1715
1716 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1717 {
1718         ecore_qm_init_pf(p_hwfn);
1719         ecore_cm_init_pf(p_hwfn);
1720         ecore_dq_init_pf(p_hwfn);
1721         ecore_cdu_init_pf(p_hwfn);
1722         ecore_ilt_init_pf(p_hwfn);
1723         ecore_src_init_pf(p_hwfn);
1724         ecore_tm_init_pf(p_hwfn);
1725         ecore_prs_init_pf(p_hwfn);
1726 }
1727
1728 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1729                                            enum protocol_type type, u32 *p_cid)
1730 {
1731         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1732         u32 rel_cid;
1733
1734         if (type >= MAX_CONN_TYPES || !p_mngr->acquired[type].cid_map) {
1735                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1736                 return ECORE_INVAL;
1737         }
1738
1739         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_mngr->acquired[type].cid_map,
1740                                            p_mngr->acquired[type].max_count);
1741
1742         if (rel_cid >= p_mngr->acquired[type].max_count) {
1743                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1744                           type);
1745                 return ECORE_NORESOURCES;
1746         }
1747
1748         OSAL_SET_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1749
1750         *p_cid = rel_cid + p_mngr->acquired[type].start_cid;
1751
1752         return ECORE_SUCCESS;
1753 }
1754
1755 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
1756                                         u32 cid, enum protocol_type *p_type)
1757 {
1758         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1759         struct ecore_cid_acquired_map *p_map;
1760         enum protocol_type p;
1761         u32 rel_cid;
1762
1763         /* Iterate over protocols and find matching cid range */
1764         for (p = 0; p < MAX_CONN_TYPES; p++) {
1765                 p_map = &p_mngr->acquired[p];
1766
1767                 if (!p_map->cid_map)
1768                         continue;
1769                 if (cid >= p_map->start_cid &&
1770                     cid < p_map->start_cid + p_map->max_count) {
1771                         break;
1772                 }
1773         }
1774         *p_type = p;
1775
1776         if (p == MAX_CONN_TYPES) {
1777                 DP_NOTICE(p_hwfn, true, "Invalid CID %d", cid);
1778                 return false;
1779         }
1780         rel_cid = cid - p_map->start_cid;
1781         if (!OSAL_TEST_BIT(rel_cid, p_map->cid_map)) {
1782                 DP_NOTICE(p_hwfn, true, "CID %d not acquired", cid);
1783                 return false;
1784         }
1785         return true;
1786 }
1787
1788 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
1789 {
1790         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1791         enum protocol_type type;
1792         bool b_acquired;
1793         u32 rel_cid;
1794
1795         /* Test acquired and find matching per-protocol map */
1796         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, &type);
1797
1798         if (!b_acquired)
1799                 return;
1800
1801         rel_cid = cid - p_mngr->acquired[type].start_cid;
1802         OSAL_CLEAR_BIT(rel_cid, p_mngr->acquired[type].cid_map);
1803 }
1804
1805 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
1806                                             struct ecore_cxt_info *p_info)
1807 {
1808         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1809         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
1810         enum protocol_type type;
1811         bool b_acquired;
1812
1813         /* Test acquired and find matching per-protocol map */
1814         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, &type);
1815
1816         if (!b_acquired)
1817                 return ECORE_INVAL;
1818
1819         /* set the protocl type */
1820         p_info->type = type;
1821
1822         /* compute context virtual pointer */
1823         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1824
1825         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
1826         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
1827         line = p_info->iid / cxts_per_p;
1828
1829         /* Make sure context is allocated (dynamic allocation) */
1830         if (!p_mngr->ilt_shadow[line].p_virt)
1831                 return ECORE_INVAL;
1832
1833         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
1834             p_info->iid % cxts_per_p * conn_cxt_size;
1835
1836         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
1837                 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1838                 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
1839
1840         return ECORE_SUCCESS;
1841 }
1842
1843 void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
1844 {
1845         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1846
1847         p_mgr->srq_count = num_srqs;
1848 }
1849
1850 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
1851 {
1852         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
1853
1854         return p_mgr->srq_count;
1855 }
1856
1857 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
1858 {
1859         /* Set the number of required CORE connections */
1860         u32 core_cids = 1;      /* SPQ */
1861
1862         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
1863
1864         switch (p_hwfn->hw_info.personality) {
1865         case ECORE_PCI_ETH:
1866                 {
1867                         struct ecore_eth_pf_params *p_params =
1868                             &p_hwfn->pf_params.eth_pf_params;
1869
1870                         ecore_cxt_set_proto_cid_count(p_hwfn,
1871                                 PROTOCOLID_ETH,
1872                                 p_params->num_cons, 1); /* FIXME VF count... */
1873
1874                         break;
1875                 }
1876         default:
1877                 return ECORE_INVAL;
1878         }
1879
1880         return ECORE_SUCCESS;
1881 }
1882
1883 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
1884                                                 struct ecore_tid_mem *p_info)
1885 {
1886         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1887         u32 proto, seg, total_lines, i, shadow_line;
1888         struct ecore_ilt_client_cfg *p_cli;
1889         struct ecore_ilt_cli_blk *p_fl_seg;
1890         struct ecore_tid_seg *p_seg_info;
1891
1892         /* Verify the personality */
1893         switch (p_hwfn->hw_info.personality) {
1894         default:
1895                 return ECORE_INVAL;
1896         }
1897
1898         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
1899         if (!p_cli->active)
1900                 return ECORE_INVAL;
1901
1902         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
1903         if (!p_seg_info->has_fl_mem)
1904                 return ECORE_INVAL;
1905
1906         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
1907         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
1908                                    p_fl_seg->real_size_in_page);
1909
1910         for (i = 0; i < total_lines; i++) {
1911                 shadow_line = i + p_fl_seg->start_line -
1912                     p_hwfn->p_cxt_mngr->pf_start_line;
1913                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
1914         }
1915         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
1916             p_fl_seg->real_size_in_page;
1917         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
1918         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
1919             p_info->tid_size;
1920
1921         return ECORE_SUCCESS;
1922 }
1923
1924 /* This function is very RoCE oriented, if another protocol in the future
1925  * will want this feature we'll need to modify the function to be more generic
1926  */
1927 enum _ecore_status_t
1928 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
1929                             enum ecore_cxt_elem_type elem_type,
1930                             u32 iid)
1931 {
1932         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
1933         struct ecore_ilt_client_cfg *p_cli;
1934         struct ecore_ilt_cli_blk *p_blk;
1935         struct ecore_ptt *p_ptt;
1936         dma_addr_t p_phys;
1937         u64 ilt_hw_entry;
1938         void *p_virt;
1939         enum _ecore_status_t rc = ECORE_SUCCESS;
1940
1941         switch (elem_type) {
1942         case ECORE_ELEM_CXT:
1943                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1944                 elem_size = CONN_CXT_SIZE(p_hwfn);
1945                 p_blk = &p_cli->pf_blks[CDUC_BLK];
1946                 break;
1947         case ECORE_ELEM_SRQ:
1948                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
1949                 elem_size = SRQ_CXT_SIZE;
1950                 p_blk = &p_cli->pf_blks[SRQ_BLK];
1951                 break;
1952         case ECORE_ELEM_TASK:
1953                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1954                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
1955                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
1956                 break;
1957         default:
1958                 DP_NOTICE(p_hwfn, false,
1959                           "ECORE_INVALID elem type = %d", elem_type);
1960                 return ECORE_INVAL;
1961         }
1962
1963         /* Calculate line in ilt */
1964         hw_p_size = p_cli->p_size.val;
1965         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
1966         line = p_blk->start_line + (iid / elems_per_p);
1967         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
1968
1969         /* If line is already allocated, do nothing, otherwise allocate it and
1970          * write it to the PSWRQ2 registers.
1971          * This section can be run in parallel from different contexts and thus
1972          * a mutex protection is needed.
1973          */
1974
1975         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
1976
1977         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
1978                 goto out0;
1979
1980         p_ptt = ecore_ptt_acquire(p_hwfn);
1981         if (!p_ptt) {
1982                 DP_NOTICE(p_hwfn, false,
1983                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
1984                 rc = ECORE_TIMEOUT;
1985                 goto out0;
1986         }
1987
1988         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1989                                          &p_phys,
1990                                          p_blk->real_size_in_page);
1991         if (!p_virt) {
1992                 rc = ECORE_NOMEM;
1993                 goto out1;
1994         }
1995         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
1996
1997         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
1998         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
1999         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2000                 p_blk->real_size_in_page;
2001
2002         /* compute absolute offset */
2003         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2004                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2005
2006         ilt_hw_entry = 0;
2007         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2008         SET_FIELD(ilt_hw_entry,
2009                   ILT_ENTRY_PHY_ADDR,
2010                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2011
2012 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2013
2014         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2015                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2016                             0 /* no flags */);
2017
2018         if (elem_type == ECORE_ELEM_CXT) {
2019                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2020                                          elems_per_p;
2021
2022                 /* Update the relevant register in the parser */
2023                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2024                          last_cid_allocated - 1);
2025
2026                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2027                         /* Enable RoCE search */
2028                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2029                         p_hwfn->b_rdma_enabled_in_prs = true;
2030                 }
2031         }
2032
2033 out1:
2034         ecore_ptt_release(p_hwfn, p_ptt);
2035 out0:
2036         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2037
2038         return rc;
2039 }
2040
2041 /* This function is very RoCE oriented, if another protocol in the future
2042  * will want this feature we'll need to modify the function to be more generic
2043  */
2044 static enum _ecore_status_t
2045 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2046                          enum ecore_cxt_elem_type elem_type,
2047                          u32 start_iid, u32 count)
2048 {
2049         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2050         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2051         struct ecore_ilt_client_cfg *p_cli;
2052         struct ecore_ilt_cli_blk *p_blk;
2053         u32 end_iid = start_iid + count;
2054         struct ecore_ptt *p_ptt;
2055         u64 ilt_hw_entry = 0;
2056         u32 i;
2057
2058         switch (elem_type) {
2059         case ECORE_ELEM_CXT:
2060                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2061                 elem_size = CONN_CXT_SIZE(p_hwfn);
2062                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2063                 break;
2064         case ECORE_ELEM_SRQ:
2065                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2066                 elem_size = SRQ_CXT_SIZE;
2067                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2068                 break;
2069         case ECORE_ELEM_TASK:
2070                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2071                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2072                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2073                 break;
2074         default:
2075                 DP_NOTICE(p_hwfn, false,
2076                           "ECORE_INVALID elem type = %d", elem_type);
2077                 return ECORE_INVAL;
2078         }
2079
2080         /* Calculate line in ilt */
2081         hw_p_size = p_cli->p_size.val;
2082         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2083         start_line = p_blk->start_line + (start_iid / elems_per_p);
2084         end_line = p_blk->start_line + (end_iid / elems_per_p);
2085         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2086                 end_line--;
2087
2088         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2089         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2090
2091         p_ptt = ecore_ptt_acquire(p_hwfn);
2092         if (!p_ptt) {
2093                 DP_NOTICE(p_hwfn, false,
2094                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2095                 return ECORE_TIMEOUT;
2096         }
2097
2098         for (i = shadow_start_line; i < shadow_end_line; i++) {
2099                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2100                         continue;
2101
2102                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2103                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2104                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2105                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2106
2107                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2108                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2109                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2110
2111                 /* compute absolute offset */
2112                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2113                     ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2114                      ILT_ENTRY_IN_REGS);
2115
2116                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2117                  * wide-bus.
2118                  */
2119                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2120                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2121                                     reg_offset,
2122                                     sizeof(ilt_hw_entry) / sizeof(u32),
2123                                     0 /* no flags */);
2124         }
2125
2126         ecore_ptt_release(p_hwfn, p_ptt);
2127
2128         return ECORE_SUCCESS;
2129 }
2130
2131 enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
2132                                               enum protocol_type proto)
2133 {
2134         enum _ecore_status_t rc;
2135         u32 cid;
2136
2137         /* Free Connection CXT */
2138         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_CXT,
2139                                       ecore_cxt_get_proto_cid_start(p_hwfn,
2140                                                                     proto),
2141                                       ecore_cxt_get_proto_cid_count(p_hwfn,
2142                                                                     proto,
2143                                                                     &cid));
2144
2145         if (rc)
2146                 return rc;
2147
2148         /* Free Task CXT */
2149         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
2150                                       ecore_cxt_get_proto_tid_count(p_hwfn,
2151                                                                     proto));
2152         if (rc)
2153                 return rc;
2154
2155         /* Free TSDM CXT */
2156         rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
2157                                       ecore_cxt_get_srq_count(p_hwfn));
2158
2159         return rc;
2160 }
2161
2162 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2163                                             u32 tid,
2164                                             u8 ctx_type, void **pp_task_ctx)
2165 {
2166         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2167         struct ecore_ilt_client_cfg *p_cli;
2168         struct ecore_ilt_cli_blk *p_seg;
2169         struct ecore_tid_seg *p_seg_info;
2170         u32 proto, seg;
2171         u32 total_lines;
2172         u32 tid_size, ilt_idx;
2173         u32 num_tids_per_block;
2174
2175         /* Verify the personality */
2176         switch (p_hwfn->hw_info.personality) {
2177         default:
2178                 return ECORE_INVAL;
2179         }
2180
2181         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2182         if (!p_cli->active)
2183                 return ECORE_INVAL;
2184
2185         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2186
2187         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2188                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2189         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2190                 if (!p_seg_info->has_fl_mem)
2191                         return ECORE_INVAL;
2192                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2193         } else {
2194                 return ECORE_INVAL;
2195         }
2196         total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page);
2197         tid_size = p_mngr->task_type_size[p_seg_info->type];
2198         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2199
2200         if (total_lines < tid / num_tids_per_block)
2201                 return ECORE_INVAL;
2202
2203         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2204             p_mngr->pf_start_line;
2205         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2206             (tid % num_tids_per_block) * tid_size;
2207
2208         return ECORE_SUCCESS;
2209 }